Compal LA-6032P NDU01, LA-6032P NDU11 Schematic

A

1 1

B

C

D

E

Compal confidential

2 2

Thin & Light

NDU01/NDU11 LA-6032P REV 1.0 Schematics Document

Mobile AMD ASB2/RS880M/SB820M

2010-03-22 Rev. 1.0

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-6032P

145Tuesday, March 23, 2010

E

of

1.0

A

B

C

D

E

Compal Confidential

Model Name : NDU01(11.3)-S/NDU11(13.6)-M

File Name : LA-6032P

1 1

Fan Control

CRT

page 17

LCD Conn.

page 18

page 5

AMD ASB2 CPU

BGA-812 Package

page 5,6,7,8

Hyper Transport Link 2.6GHz

16X16

ATI

RS880M

HDMI Conn.

page 19

page 11,12,13,14,15

2 2

USB/B Right

USB port 0,1

page 29

BT conn

USB port 6

page 29

Int. Camera

USB port 9

page 18

A-Link Express II
4X PCI-E

USB

5V 480MHz

ATI

SB820M

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 800MHZ

PCIe 4 x

1.5V 2.5GHz(250MB/s)

SATA port 0

5V 1.5GHz(150MB/s)

SATA HDD0

ADM1032ARMZ

FUJIN OZ600FJ1

5IN1

PCIe port 1

PCIeMini Card
WLAN (Slot 1)

USB Port 8

RTL8105E
LAN 10/100M

PCIe port 3

PCIeMini Card
WWAN / 3G (Slot2)

USB Port 10 for 3G card

page 25

page 7

200pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

page 30

PCIe Port 2

page 26

page 27

Thermal Sensor

Clock Generator

page 9,10

5IN1

page 30

RJ45

page 17

page 16

SLG8SP626

page 26

SATA port 3

5V 1.5GHz(150MB/s)

USB port 2

5V 480MHz

3.3V 24.576MHz/48Mhz

GSENSOR

page 32

G-Sensor Controller

R5F211B4D34SP

LPC BUS

3.3V 33 MHz

ENE KB926 D3

SPI ROM

page 20,21,22,23,24

HD Audio

page 31

page 32

EC
SMBUS

page 33

SPI ROM

page 34

Debug Port

page 32

Int.KBD

page 32

3 3

RTC CKT.

page 20

Right USB&Audio/B
LS-6031P

page 29

RJ45&VGA/B

Power On/Off CKT.

page 33

DC/DC Interface CKT.

page 34

LS-6032P

HD/B
LS-6033P

LED/B
LS-6034P

Power Circuit DC/DC

4 4

page 37,38,39.40
41,42,43,44

Touch Pad BTN/B
LS-6035P(13.3)

page 17

page 25

page 33

page 33

Touch Pad BTN/B
LS-6037P(11.6)

page 32

eSATA

page 25

Int.

MIC CONN

page 18

HDA Codec

ALC259Q

page 28

page 29 page 29 page 29

HP CONN

SPK CONNMIC CONN

PWR BTN
LS-6036P

A

page 33

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE CO MPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. N EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Title

Size Document Num ber Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-6032P

E

of

245Tuesday, March 23, 2010

1.0

A

B+

SUSP

N-CHANNEL

1 1

SI4800BDY

SUSP#

MP2121DQ

TPS51125RGER

SUSP

N-CHANNEL

SI4800BDY

2 2

B

DESIGN CURRENT 0.1A

DESIGN CURRENT 0.1A

DESIGN CURRENT 4.5A

DESIGN CURRENT 2A

+5VS

LDO

G9191

ENVDD

P-CHANNEL

AO-3413

BT_PWR#

P-CHANNEL

AO-3413

WOL_EN#

P-CHANNEL

AO-3413

DESIGN CURRENT 300mA

DESIGN CURRENT 1.5A

DESIGN CURRENT 1A

DESIGN CURRENT 4A

DESIGN CURRENT 1.0A

DESIGN CURRENT 180mA

DESIGN CURRENT 500mA

C

+3VL
+5VL
+5VALW

+5VS

+3VS_HDP

+1.8VS

+3VALW

+3VS

+LCD_VDD

+BT_VCC

+3V_LAN

D

E

LDO

APL5508

POK

RT8209BGQW

3 3

VR_ON

VGATE#

N-CHANNEL

IRF8113PBF

VLDT_EN#

N-CHANNEL

IRF8113PBF

ISL6265

SYSON

RT8209BGQW

4 4

SUSP

N-CHANNEL

IRF8113PBF

SUSP

LDO

G2992F1U

VR_ON#

LDO

G2992F1U

DESIGN CURRENT 300mA

DESIGN CURRENT 0.3A

DESIGN CURRENT 6.5A

DESIGN CURRENT 7.6A

DESIGN CURRENT 15A

DESIGN CURRENT 2A

DESIGN CURRENT 7A

DESIGN CURRENT 1A

DESIGN CURRENT 0.5A

DESIGN CURRENT 1.5A

+2.5VS

+1.1VALW

+1.1VS

+NB_CORE

+CPU_CORE0

+VDDNB

+1.5V

+1.5VS

+0.75VS

+0.9V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/04/14 2009/04/14

C

Compal Secret Dat a

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

D

Date: Sheet

Power Map

LA-5381P

E

1.0

of

345Tuesday, March 23, 2010

A

Voltage Rails

1 1

State

O MEANS ON X MEANS OFF

power
plane

+RTCVCC

B+

+3VL

+5VL

+3VALW

+1.1VALW

B

+5VS

+3VS

+2.5VS

+1.8VS

+1.5VS

+1.5V+5VALW

+1.1VS

+0.9VS

+0.75VS
+NB_CORE

+VDDNB

+CPU_CORE_0

GSENSOR@ : means just reserve for G sensor part

1STGSENSOR@ : means just reserve 1st G sensor IC

C

Symbol Note :

: means Digital Ground : means Analog Ground

@ : means just reserve , no build
K625R3@ : means just for 1.5G CPU
K125R3@ : means just for 1.7G CPU
K325R3@ : means just for 1.3G CPU
K625R1@ : means just for 1.5G CPU
K125R1@ : means just for 1.7G CPU
K325R1@ : means just for 1.3G CPU

M@ : means just reserve for 13.3 control
S@ : means just reserve for 11.6 control

1ST@ : means just reserve 1st G sensor IC

D

U1
K125 CPU

K625R3@

E

For 11.6 and 13.3 DAZ

ZZZ

PCB-MB

K125 mean 1.7G CPU

U1

K125R1@

K125 CPU

K125 mean 1.7G CPU K325 mean 1.3G CPUK625 mean 1.7G CPU

U1

K125R3@

K125 CPU

RS880M SB820M

U5

RS880MR3@

RS880M

K325 mean 1.3G CPU

U1
K325 CPU

U1
K325 CPU

U7
SB820M

K325R1@

K325R3@

SB820MR3@

2ND@ : means just reserve 2nd G sensor IC

2NDGSENSOR@ : means just reserve 2nd G sensor IC

S0

2 2

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O

O

O

O

O

X

O

O

O

O

X

O

XX

X

OO

OO

X

X

XX X

NOSIDE@ : means just reserve NOSIDE

SIDE@ : means just reserve SIDE port
RS880MR1@ : means just for RS880MR1
RS880MR3@ : means just for RS880MR3
SB820MR1@ : means just for SB820MR1
SB820MR3@ : means just for SB820MR3

SB SM Bus1 Address

HEX

A0 H

D2 H

Address

1010 0000 b

1010 0100 bA4 H

1101 0010 b

Power

3 3

+3VS

+3VS

+3VS

Device

DDR SO-DIMM 0

DDR SO-DIMM 1

Clock Generator

EC SM Bus1 Address

Device Address Address

+3VL +3VS

4 4

HEX HEX

16 H

0001 011X bSmart Battery

A

PowerPower

+3VS

SB SM Bus2 Address

DevicePower

+3VALW

WLAN/WIMAX

EC SM Bus2 Address

Device

G-Sensor

B

HEX Address

98 H

1001 100X bCPU_ADM1032-1

SMBUS Control Table

SOURCE

EC_SMB_CK1

EC_SMB_DA1

EC_SMB_CK2

EC_SMB_DA2

I2C_CLK

I2C_DATA

DDC_CLK0

DDC_DATA0

SCL0

SDA0

SCL1

SDA1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

KB926

KB926

RS880M

RS880M

SB820

SB820

2008/04/14 2009/04/14

BATT

V

Compal Secret Data

Deciphered Date

CPU

THERMAL

SENSOR

V

D

SODIMM

I / II

CLK
GEN

VV

Custom

Date: Sheet

WLAN

LCD
DDC
ROM

DDC
ROM

G-sensor

HDMI

V

V

V

V

Title

Size Document Number Rev

Compal Electronics, Inc.

Notes List

LA-6032P

445Tuesday, March 23, 2010

E

of

1.0

A

1 1

B

C

D

E

H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

H_CLKOP1
H_CLKON1

H_CLKOP0
H_CLKON0

H_CTLOP1
H_CTLON1

H_CTLOP0
H_CTLON0

H_CADOP[0..15]

H_CADON[0..15]

H_CADOP[0..15] 11

H_CADON[0..15] 11H_CADIN[0..15]11

H_CLKOP1 11
H_CLKON1 11

H_CLKOP0 11
H_CLKON0 11

H_CTLOP1 11
H_CTLON1 11

H_CTLOP0 11
H_CTLON0 11

FAN Control Circuit

+5VS

1A

12

@

1SS355_SOD323-2

2

1

D1

12

2

@

D2

1

1SS355_SOD323-2

+FAN1

C2
1000P_0402_50V7K

@

@

C1

10U_0805_10V6K

U2

1

EN

2

EN_DFAN131

+FAN1

1

2

3
4

APL5607KI-TRG_SO8
C3
10U_0805_10V6K

VIN
VOUT
VSET

GND
GND
GND
GND

8
7
6
5

1
2
3

4
5

ACES_88231-03041

10K_0402_5%

2

C4

0.01U_0402_25V7K

1

JFAN1

1
2
3

GND
GND

R1

@

12

+3VS

FAN_SPEED1 31

H_CADIP[0..15]11

2 2

3 3

H_CLKIP111
H_CLKIN111

H_CLKIP011
H_CLKIN011

H_CTLIP111
H_CTLIN111

H_CTLIP011
H_CTLIN011

H_CADIP[0..15]

H_CADIN[0..15]

H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0

H_CLKIP1
H_CLKIN1

H_CLKIP0
H_CLKIN0

H_CTLIP1
H_CTLIN1

H_CTLIP0
H_CTLIN0

U1A

W7

L0_CADIN_H15

W6

L0_CADIN_L15

U6

L0_CADIN_H14

U5

L0_CADIN_L14

R7

L0_CADIN_H13

R6

L0_CADIN_L13

P6

L0_CADIN_H12

P5

L0_CADIN_L12

L6

L0_CADIN_H11

L5

L0_CADIN_L11

J6

L0_CADIN_H10

J5

L0_CADIN_L10

H4

L0_CADIN_H9

H3

L0_CADIN_L9

G6

L0_CADIN_H8

G5

L0_CADIN_L8

T3

L0_CADIN_H7

T4

L0_CADIN_L7

T2

L0_CADIN_H6

T1

L0_CADIN_L6

P3

L0_CADIN_H5

P4

L0_CADIN_L5

P2

L0_CADIN_H4

P1

L0_CADIN_L4

M2

L0_CADIN_H3

M1

L0_CADIN_L3

K3

L0_CADIN_H2

K4

L0_CADIN_L2

K2

L0_CADIN_H1

K1

L0_CADIN_L1

H2

L0_CADIN_H0

H1

L0_CADIN_L0

M8

L0_CLKIN_H1

M7

L0_CLKIN_L1

M3

L0_CLKIN_H0

M4

L0_CLKIN_L0

Y6

L0_CTLIN_H1

Y5

L0_CTLIN_L1

V2

L0_CTLIN_H0

V1

L0_CTLIN_L0

TMK625DBV23GM_FCBGA812

K625@

L0_CADOUT_H15

L0_CADOUT_L15

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H6

HT LINK

L0_CADOUT_L6

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H0

L0_CADOUT_L0

L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

AB6
AB5
AB9
AB8
AC7
AC6
AE6
AE5
AE9
AE8
AH3
AH4
AK3
AK4
AH1
AH2
Y1
Y2
Y4
Y3
AB1
AB2
AB4
AB3
AD4
AD3
AF1
AF2
AF4
AF3
AK1
AK2

AF6
AF5

AD1
AD2

Y8
Y9

V4
V3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

AMD CPU S1G2 HT I/F

LA-6032P

545Tuesday, March 23, 2010

E

of

1.0

A

B

C

D

E

DDR_B_MA[15..0]10

1 1

DDR_B_BS#210
DDR_B_BS#110
DDR_B_BS#010

DDR_B_DQS710
DDR_B_DQS#710
DDR_B_DQS610
DDR_B_DQS#610
DDR_B_DQS510
DDR_B_DQS#510

2 2

3 3

DDR_B_DQS410
DDR_B_DQS#410
DDR_B_DQS310
DDR_B_DQS#310
DDR_B_DQS210
DDR_B_DQS#210
DDR_B_DQS110
DDR_B_DQS#110
DDR_B_DQS010
DDR_B_DQS#010

DDR_B_CLK010

DDR_B_CLK#010

DDR_B_CLK110

DDR_B_CLK#110

DDR_CKE1_DIMMB10
DDR_CKE0_DIMMB10

DDR_B_ODT110
DDR_B_ODT010

DDR_CS1_DIMMB#10
DDR_CS0_DIMMB#10

DDR_B_RAS#10
DDR_B_CAS#10

DDR_B_WE#10

MEM_MB_RST#10 MEM_MA_RST#9

+1.5V

1 2

R792 1K_0402_5%

DDR_B_MA15
DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0

DDR_B_BS#2
DDR_B_BS#1
DDR_B_BS#0

DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0

DDR_B_CLK0

DDR_B_CLK#0

DDR_B_CLK1

DDR_B_CLK#1

DDR_CKE1_DIMMB
DDR_CKE0_DIMMB

DDR_B_ODT1
DDR_B_ODT0

DDR_CS1_DIMMB#
DDR_CS0_DIMMB#

DDR_B_RAS#
DDR_B_CAS#

DDR_B_WE#

MB_EVENT_L

U1C

P33

MB_ADD15

P31

MB_ADD14

AJ33

MB_ADD13

T32

MB_ADD12

T31

MB_ADD11

AD32

MB_ADD10

T33

MB_ADD9

V32

MB_ADD8

U33

MB_ADD7

V33

MB_ADD6

V31

MB_ADD5

W33

MB_ADD4

Y31

MB_ADD3

Y33

MB_ADD2

Y32

MB_ADD1

AC33

MB_ADD0

R33

MB_BANK2

AD33

MB_BANK1

AE33

MB_BANK0

K33

MB_CHECK7

K31

MB_CHECK6

G32

MB_CHECK5

F32

MB_CHECK4

L33

MB_CHECK3

K32

MB_CHECK2

H31

MB_CHECK1

G33

MB_CHECK0

J33

MB_DQS_H8

H32

MB_DQS_L8

AM14

MB_DQS_H7

AN14

MB_DQS_L7

AL20

MB_DQS_H6

AM20

MB_DQS_L6

AN26

MB_DQS_H5

AM26

MB_DQS_L5

AN30

MB_DQS_H4

AM30

MB_DQS_L4

D33

MB_DQS_H3

D32

MB_DQS_L3

B28

MB_DQS_H2

A28

MB_DQS_L2

A21

MB_DQS_H1

B20

MB_DQS_L1

B16

MB_DQS_H0

A15

MB_DQS_L0

AN22

MB_CLK_H7

AM22

MB_CLK_L7

AN21

MB_CLK_H6

AM21

MB_CLK_L6

AA32

MB_CLK_H5

AA33

MB_CLK_L5

AB33

MB_CLK_H4

AB32

MB_CLK_L4

AB31

MB_CLK_H3

AB30

MB_CLK_L3

AD31

MB_CLK_H2

AD30

MB_CLK_L2

C22

MB_CLK_H1

B22

MB_CLK_L1

A22

MB_CLK_H0

A23

MB_CLK_L0

N33

MB_CKE1

P32

MB_CKE0

AK31

MB1_ODT1

AH31

MB1_ODT0

AK32

MB0_ODT1

AH33

MB0_ODT0

AK33

MB1_CS_L1

AF33

MB1_CS_L0

AJ32

MB0_CS_L1

AF31

MB0_CS_L0

AF32

MB_RAS_L

AH32

MB_CAS_L

AG33

MB_WE_L

L32

MB_RESET_L

M33

FREE|MB_EVENT_L

TMK625DBV23GM_FCBGA812

DDR III: CHANNEL B

MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10

MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0

MB_DM8
MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0

AN13
AL14
AL16
AN17
AN12
AM12
AM16
AN16
AL18
AN19
AM24
AN24
AM18
AN18
AL22
AN23
AM25
AL26
AN28
AL28
AL24
AN25
AN27
AM28
AM29
AL30
AL32
AL33
AK28
AN29
AM31
AM32
E33
D31
B31
A31
F33
F31
C32
B32
C30
A29
B26
A26
B30
A30
A27
C26
A24
B24
C18
A18
A25
C24
C20
A19
C16
A16
B14
A13
B18
A17
C14
A14

H33
AN15
AN20
AK26
AN31
C33
C28
A20
D14

K625@

DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0

DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0

DDR_B_D[63..0] 10

DDR_B_DM[7..0] 10

DDR_A_MA[15..0]9

DDR_A_BS#29
DDR_A_BS#19
DDR_A_BS#09

DDR_A_DQS79

DDR_A_DQS#79

DDR_A_DQS69

DDR_A_DQS#69

DDR_A_DQS59

DDR_A_DQS#59

DDR_A_DQS49

DDR_A_DQS#49

DDR_A_DQS39

DDR_A_DQS#39

DDR_A_DQS29

DDR_A_DQS#29

DDR_A_DQS19

DDR_A_DQS#19

DDR_A_DQS09

DDR_A_DQS#09

DDR_A_CLK09

DDR_A_CLK#09

DDR_A_CLK19

DDR_A_CLK#19

DDR_CKE1_DIMMA9
DDR_CKE0_DIMMA9

DDR_A_ODT19
DDR_A_ODT09

DDR_CS1_DIMMA#9
DDR_CS0_DIMMA#9

DDR_A_RAS#9
DDR_A_CAS#9
DDR_A_WE#9

+1.5V

1 2

R793 1K_0402_5%

DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1

DDR_CKE1_DIMMA
DDR_CKE0_DIMMA

DDR_A_ODT1

DDR_CS1_DIMMA#
DDR_CS0_DIMMA#

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

MA_EVENT_L

U1B

P30

MA_ADD15

M29

MA_ADD14

AG28

MA_ADD13

P28

MA_ADD12

T30

MA_ADD11

AC28

MA_ADD10

P27

MA_ADD9

R26

MA_ADD8

R27

MA_ADD7

U28

MA_ADD6

V30

MA_ADD5

U27

MA_ADD4

Y30

MA_ADD3

AB29

MA_ADD2

W29

MA_ADD1

AC26

MA_ADD0

R29

MA_BANK2

AC29

MA_BANK1

AE28

MA_BANK0

K30

MA_CHECK7

J29

MA_CHECK6

G29

MA_CHECK5

F29

MA_CHECK4

L28

MA_CHECK3

L29

MA_CHECK2

H29

MA_CHECK1

H27

MA_CHECK0

J27

MA_DQS_H8

J26

MA_DQS_L8

AJ11

MA_DQS_H7

AK12

MA_DQS_L7

AG15

MA_DQS_H6

AH15

MA_DQS_L6

AH22

MA_DQS_H5

AG22

MA_DQS_L5

AG26

MA_DQS_H4

AH26

MA_DQS_L4

E28

MA_DQS_H3

F28

MA_DQS_L3

E25

MA_DQS_H2

F25

MA_DQS_L2

G17

MA_DQS_H1

H17

MA_DQS_L1

E12

MA_DQS_H0

F12

MA_DQS_L0

AK18

MA_CLK_H7

AJ17

MA_CLK_L7

AH17

MA_CLK_H6

AG17

MA_CLK_L6

Y28

MA_CLK_H5

Y27

MA_CLK_L5

AB27

MA_CLK_H4

AB26

MA_CLK_L4

W27

MA_CLK_H3

W26

MA_CLK_L3

P26

MA_CLK_H2

M26

MA_CLK_L2

D18

MA_CLK_H1

F19

MA_CLK_L1

E20

MA_CLK_H0

E19

MA_CLK_L0

M30

MA_CKE1

M28

MA_CKE0

AJ29

MA1_ODT1

AF27

MA1_ODT0

AJ30

MA0_ODT1

AG29

MA0_ODT0

AH29

MA1_CS_L1

AE29

MA1_CS_L0

AH30

MA0_CS_L1

AF29

MA0_CS_L0

AC27

MA_RAS_L

AF30

MA_CAS_L

AE27

MA_WE_L

L27

MA_RESET_L

M32

FREE|MA_EVENT_L

TMK625DBV23GM_FCBGA812

DDR III: CHANNEL A

MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10

MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0

MA_DM8
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0

AG11
AH11
AJ12
AJ14
AF11
AF12
AG12
AH12
AK14
AF15
AH19
AK20
AF14
AG14
AF17
AG19
AG20
AJ20
AF22
AK24
AF19
AF20
AJ23
AG23
AF23
AF25
AH27
AK30
AJ25
AG25
AJ26
AJ28
D28
G28
D26
E26
F30
E29
F27
H26
H25
D24
H22
E22
F26
G26
D22
G23
G22
G20
G15
F15
D20
F22
D16
E17
H15
H14
G12
H12
E15
E14
E11
F11

H30
AL12
AK16
AK22
AJ27
E27
E23
H19
G14

K625@

DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0

DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1DDR_A_ODT0
DDR_A_DM0

DDR_A_D[63..0] 9

DDR_A_DM[7..0] 9

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

AMD CPU S1G2 DDRII I/F

LA-6032P

645Tuesday, March 23, 2010

E

of

1.0

A

B

C

D

E

1 2

R2 10K_0402_5%

1 2

R3 1K_0402_5%

CPU_THERMTRIP#_R

1 2

R4 300_0402_5%

CPU_PROCHOT #_1.8

+1.5V

+1.1VS

+1.5V

@

@

@

@

R43220_0402_5%

R42220_0402_5%

R41220_0402_5%

R44300_0402_5%

12

12

12

12

D

B

2

E

3 1

MMBT3904_NL_SOT23-3

R5

@

1 2

0_0402_5%

CPU_DBREQ#
CPU_TEST27_SINGLECHAIN

CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN

CPU_TEST15_BP1
CPU_TEST14_BP0

CPU_TEST18_PLLTEST1
CPU_TEST19_PLLTEST0
CPU_TEST23_TSTUPD
CPU_DBRDY

R45300_0402_5%

1 2

CPU_TCK_R
CPU_TMS_R
CPU_TDI_R
CPU_TRST#_R
CPU_TDO_R

CONN@

Title

Size Document Number Rev

Custom

Date: Sheet

D4 CH751H-40PT_SOD323-2

Q1

C

21

CPU_VDDNB_RUN_FB_H

Close to CPU

CPU_SVC

CPU_SVD

R19 300_0402_5%

1 2

R21 1K_0402_5%

1 2

R23 300_0402_5% @

1 2

R24 1K_0402_5%

1 2
1 2

R26 1K_0402_5%

1 2

R27 1K_0402_5%

1 2

R28 300_0402_5% @

1 2

R29 300_0402_5% @

1 2

R30 1K_0402_5%

1 2

R31 1K_0402_5%

1 2

R32 1K_0402_5%

1 2

R34 300_0402_5% @

1 2

JP1

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

2423
26

SAMTEC_ASP-68200-07

R12 1K_0402_5%

R13 1K_0402_5%

+1.5V

@

Compal Electronics, Inc.

AMD CPU S1G2 CTRL

LA-6032P

E

H_THERMTRIP# 21

H_PROCHOT# 20

R9 10_0402_5%

1 2

+VDDNB

1 2

1 2

CPU_TEST26_BURNIN_L

R20 1K_0402_5%

1 2

745Tuesday, March 23, 2010

of

+1.5V

LDT_RST#

1.0

R18

80.6_0402_1%

1 2

T10 PAD@
T11 PAD@

T16 PAD@
T18 PAD@

+1.5V

+1.5V

+2.5VDDA

+2.5VS

@

100U_D2_10VM

1 1

CLK_CPU_BCLK20

CLK_CPU_BCLK#20

+1.5VS

R11
300_0402_5%

1 2

LDT_RST#20

2 2

H_PWRGD20,42

3 3

LDT_STOP#12,20

4 4

C17

1 2

LDT_RST#

1

C11

0.01U_0402_25V7K

2

+1.5VS

1 2

1

2

+1.5VS

1 2

1

2

+3VS

1

C16

2

0.1U_0402_16V4Z

THERMDA_CPU

THERMDC_CPU

2200P_0402_50V7K

A

@

R17
300_0402_5%

H_PWRGD

C13

0.1U_0402_16V7K

R33
300_0402_5%

LDT_STOP#

C14

0.01U_0402_25V7K

@

Thermal Sensor

R8 Close to CPU within 0.6"

L

C9 C10 Close to CPU within 1.2"

U4

1

VDD

2

D+

3

D-

THERM#4GND

ADM1032ARM-1 ZREEL_MSOP8

1 2

C10

1 2

C9 3900P_0402_50V7K

+1.1VALW

+1.5V

+0.9V

L

+1.5V

R802
1K_0402_1%

1 2

R803
1K_0402_1%

1 2

8

SCLK

7

SDATA

6

ALERT#

5

R355 10_0402_5%

R356 10_0402_5%

R357 10_0402_5%

Close to CPU within
1"

L1

1 2

FBM_L11_201209_300L_0805

1

+

C5

2

3900P_0402_50V7K

12

R8
169_0402_1%

@

@

@

0.01U_0402_25V7K

2

C654

1

EC_SMB_CK2 31,32

EC_SMB_DA2 31,32

+1.5V

CPU_VLDT_SENSE

CPU_VDDIO_SENSE

CPU_VDD0_RUN_FB_L42

CPU_VDD0_RUN_FB_H42

CPU_VDDNB_RUN_FB_H42

0.1U_0402_16V7K

@
@
@
@

M_VREF

1

C655

2

1000P_0402_25V8J

B

3300P_0402_50V7K

1

1

C7

C64.7U_0805_10V4Z

2

2

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

R7 1K_0402_5%

1 2

R10 1K_0402_5%

1 2

C12

@

1 2

1 2

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

CPU_TEST9_ANALOGIN

R22

1 2

0_0402_5%

T12 PAD
T14 PAD
T15 PAD
T17 PAD

CPU_TEST17_BP3

T22PAD@

CPU_TEST16_BP2

T23PAD@ R25 1K_0402_5%

CPU_TEST15_BP1
CPU_TEST14_BP0

CPU_TEST7_ANALOG_T
CPU_TEST6_DIECRACKMON
CPU_TEST3
CPU_TEST2

+2.5VDDA@250mA

1

C8

0.22U_0603_16V4Z

2

H_PWRGD
LDT_STOP#
LDT_RST#

CPU_SIC
CPU_SID

CPU_TDI
CPU_TRST#
CPU_TCK
CPU_TMS

CPU_DBREQ#

CPU_VDD0_RUN_FB_L
CPU_VLDT_SENSE
CPU_VDD0_RUN_FB_H
CPU_VDDNB_RUN_FB_H
CPU_VDDIO_SENSE
CPU_VDDR_SENSECPU_VDDR_SENSE

M_VREF

R16

39.2_0402_1~D

R35

@

1 2

510_0402_5%

R38

1 2

510_0402_5%

U1D

A8

VDDA_1

B8

VDDA_2

A6

CLKIN_H

A7

CLKIN_L

D10

PWROK

E9

LDTSTOP_L

F9

RESET_L

AN4

SIC

AN5

SID

AM2

RSVD_SA0

AN3

ALERT_L

AM8

TDI

AL8

TRST_L

AK8

TCK

AN8

TMS

G9

DBREQ_L

D2

VSS_SENSE

E2

VLDT_SENSE

E1

VDD_SENSE

D1

VDDNB_SENSE

D3

VDDIO_SENSE

C2

VDDR_SENSE

A11

M_ZP
M_ZN

CPU_TEST25_H_BYPASSCLK_H

CPU_TEST25_L_BYPASSCLK_L

M_VREF

AM9

M_ZN_H

AN9

M_ZN_L

A9

BYPASSCLK_H

B9

BYPASSCLK_L

A5

PLLTEST0

B6

PLLTEST1

G8

ANALOGIN

F8

BP3

C8

BP2

D9

BP1

E8

BP0

C6

ANALOG_T

AH7

DIECRACKMON

AK5

GATE0

AJ7

DRAIN0

TMK625DBV23GM_FCBGA812 K625@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MISC

R36

1 2

510_0402_5%

R39

1 2

510_0402_5%

@

C

RSVD|CORE_TYPE

THERMTRIP_L

PROCHOT_L

CPU_PRESENT_L

FBCLKOUT_H

FBCLKOUT_L

SCANSHIFTEN

SINGLECHAIN

ANALOGOUT

+1.5V

M31

CPU_SVC

C1

SVC

CPU_SVD

B2

SVD

THERMDC_CPU

AL6

THERMDC
THERMDA

TDO

DBRDY

RSVD3

HTREF1
HTREF0

SCANCLK1

TSTUPD

SCANEN

SCANCLK2

PLLCHRZ_H

PLLCHRZ_L

BURNIN_L

DIG_T

M_TEST

THERMDA_CPU

AM5

CPU_THERMTRIP#_R

AK6

CPU_PROCHOT#_1.8

AN6

AN7

CPU_DBRDY

H9

T1 PAD @

AM6

CPU_PRESENT_L

AJ9

CPU_HTREF1

V10

CPU_HTREF0

V9

CPU_TEST29_H_FBCLKOUT_P

B10

CPU_TEST29_L_FBCLKOUT_N

A10

CPU_TEST24_SCANCLK1

AK7

CPU_TEST23_TSTUPD

AG8

CPU_TEST22_SCANSHIFTEN

AK9

CPU_TEST21_SCANEN

AH9

CPU_TEST20_SCANCLK2

AM7

CPU_TEST28_H_PLLCHRZ_P

G11

CPU_TEST28_L_PLLCHRZ_N

H11

CPU_TEST27_SINGLECHAIN

AJ8

CPU_TEST26_BURNIN_L

AM4

CPU_TEST10_ANALOGOUT

D7

CPU_TEST8_DIG_T

B5

AG9

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

2008/04/14 2009/04/14

CPU_SVC 42
CPU_SVD 42

CPU_TDO

R801 1K_0402_5%

1 2

R14 R15 Close to CPU within 1.5"

L

R14 44.2_0402_1%

1 2

R15 44.2_0402_1%

1 2

R850 0_0402_5%

1 2

R851 0_0402_5%

1 2

R852 0_0402_5%

1 2

R853 0_0402_5%

1 2

R854 0_0402_5%

1 2

Compal Secret Data

Deciphered Date

A

+CPU_CORE_0@15000mA

+CPU_CORE_0 +CPU_CORE_0

1 1

2 2

U1E

D4

VDD_1

D5

VDD_2

D6

VDD_3

E5

VDD_4

E6

VDD_5

E7

VDD_6

F5

VDD_7

F6

VDD_8

F7

VDD_9

H7

VDD_10

H8

VDD_11

J8

VDD_12

E4

VDD_13

J10

VDD_14

J12

VDD_15

J14

VDD_16

J18

VDD_17

J20

VDD_18

J21

VDD_19

J23

VDD_20

J9

VDD_21

K10

VDD_22

K12

VDD_23

K14

VDD_24

K18

VDD_25

K20

VDD_26

K21

VDD_27

K23

VDD_28

N4

VDD_29

L11

VDD_30

L13

VDD_31

L7

VDD_32

L9

VDD_33

M10

VDD_34

M12

VDD_35

R4

VDD_36

M5

VDD_37

N11

VDD_38

N24

VDD_39
VDD_40W4VDD_46

N9

VDD_41

P15

VDD_42

P18

VDD_43

TMK625DBV23GM_FCBGA812

K625@

VDD_85
VDD_84
VDD_83
VDD_82
VDD_81
VDD_80
VDD_79
VDD_78
VDD_77
VDD_76
VDD_75
VDD_74
VDD_73
VDD_72
VDD_71
VDD_70
VDD_69
VDD_68
VDD_67

POWER1

VDD_66
VDD_65
VDD_64
VDD_63
VDD_62
VDD_61
VDD_60
VDD_59
VDD_58
VDD_57
VDD_56
VDD_55
VDD_54
VDD_53
VDD_52
VDD_51
VDD_50
VDD_49
VDD_48
VDD_47

VDD_45
VDD_44

AE12
AD9
AE21
AD21
AD18
AD14
AD12
AD11
AC5
AE18
AC24
AC12
AC10
AB13
AB11
AE14
AA24
AA12
AA10
Y19
Y16
Y14
W5
W20
W18
W15
AE23
V24
V19
V16
V14
T20
T18
T15
T10
R5
R19
R16
R14
AC4
P24
P20

3000mA

VLDT_A&VLDT_B(+1.1VS) decoupling.

+1.1VS

1

C18

4.7U_0805_10V4Z

2

1

C19

4.7U_0805_10V4Z

2

1

C20
22U_0805_6.3V6M

2

1

C21

0.22U_0603_16V4Z

2

1

C22

0.22U_0603_16V4Z

2

B

+1.5V

M27
Y26
U26
N32
U32
N30
P29
R28
R30
R32
U29

U30
W28
W30
W32

Y29

AA30
AB28
AE32
AC30
AC32
AE26
AE30
AF28
AG30
AG32
AD25
AA25
AC25

V25

P25

N25
M25

K25

L25

T25

Y25

AB25

1

C23
180P_0402_50V8J

2

U1F

POWER2

PROGEN_L

1

C24
180P_0402_50V8J

2

VLDT_A_1
VLDT_A_2
VLDT_A_3
VLDT_A_4

VLDT_B_1
VLDT_B_2
VLDT_B_3
VLDT_B_4

VDDR_1
VDDR_2
VDDR_3
VDDR_4

VDDR_5
VDDR_6
VDDR_7
VDDR_8

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
VDDNB_6

FREE_1
FREE_2
FREE_3
FREE_4
FREE_5
FREE_6
FREE_7
FREE_8
FREE_9

VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
VDDIO_6
VDDIO_7
VDDIO_8
VDDIO_9
VDDIO_10
VDDIO_11
VDDIO_12
VDDIO_13
VDDIO_14
VDDIO_15
VDDIO_16
VDDIO_17
VDDIO_18
VDDIO_19
VDDIO_20
VDDIO_21
VDDIO_22
VDDIO_23
VDDIO_24
VDDIO_25
VDDIO_26
VDDIO_27
VDDIO_28
VDDIO_29
VDDIO_30
VDDIO_31
VDDIO_32
VDDIO_33
VDDIO_34
VDDIO_35
VDDIO_36
VDDIO_37
VDDIO_38

TMK625DBV23GM_FCBGA812

K625@

+1.1VS

F1
F2

+1.1VS@1500mA

F3
F4

AL1
AL2
AL3
AL4

A12
B12
C12
D12

AK10
AL10
AM10
AN10

+VDDNB

A3
A4
B3
B4

+VDDNB@2000mA

C3
C4

B11

G7
B7
AH8
AJ6
B25
AM3
AN11
P9
P8

C

+0.9V

+0.9V@1250mA

U1G

B1

VSS_1

N2

VSS_28

N22

VSS_29

N23

VSS_30

B13

VSS_2

B15

VSS_3

B17

VSS_4

M21

VSS_27

B19

VSS_5

B21

VSS_6

B23

VSS_7

B27

VSS_8

B29

VSS_9

B33

VSS_10

C10

VSS_11

P10

VSS_31

P14

VSS_32

P16

VSS_33

P19

VSS_34

P7

VSS_35

C31

VSS_12

D11

VSS_13

D13

VSS_14

D15

VSS_15

R1

VSS_36

D17

VSS_16

D19

VSS_17

D21

VSS_18

D23

VSS_19

D25

VSS_20

D27

VSS_21

R15

VSS_37

R18

VSS_38

R2

VSS_39

R20

VSS_40

D29

VSS_46

D30

VSS_47

D8

VSS_48

E30

VSS_49

E32

VSS_50

F14

VSS_51

F17

VSS_52

R8

VSS_53

T14

VSS_54

T16

VSS_55

F20

VSS_56

T19

VSS_57

T24

VSS_58

T9

VSS_59

U1

VSS_60

F23

VSS_61

N1

VSS_62

G1

VSS_63

G19

VSS_64

G2

VSS_65

G25

VSS_66

G27

VSS_67

N10

VSS_115

TMK625DBV23GM_FCBGA812

K625@

VSS_45
VSS_44
VSS_43
VSS_42
VSS_26
VSS_25
VSS_41
VSS_24
VSS_23
VSS_22
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75

GND1

VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114

W19
W1
V20
V18
M11
L8
V15
L4
L30
L26
L24
L23
L22
L21
L2
L12
L10
L1
K9
M6
K24
K22
K16
M22
K13
M24
K11
M23
J7
W16
J4
W14
J32
J30
M13
J28
U8
J25
U4
J24
U7
U2
J2
J16
J13
J11
J1
H6
H5
H28
H23
H20
J22
M9
G4
G30
N12

D

U1H

AM19

VSS_207

AF7

VSS_167

AF26

VSS_166

AE7

VSS_165

AF8

VSS_168

AF9

VSS_169

AG1

VSS_170

AG2

VSS_171

AG27

VSS_172

AG4

VSS_173

AG5

VSS_174

AG6

VSS_175

AG7

VSS_176

AE4

VSS_164

AE25

VSS_163

AE24

VSS_162

AE22

VSS_161

AE20

VSS_160

AE2

VSS_159

AE16

VSS_158

AE13

VSS_157

AH14

VSS_177

AE11

VSS_156

AE10

VSS_155

AE1

VSS_154

AD24

VSS_153

AD23

VSS_152

AD22

VSS_151

AH20

VSS_178

AH23

VSS_179

AH25

VSS_180

AH28

VSS_181

AD20

VSS_150

AD16

VSS_149

AD13

VSS_148

AD10

VSS_147

AC9

VSS_146

AC8

VSS_145
VSS_214A2VSS_215

AC23

VSS_144

AH5

VSS_182

AJ1

VSS_183

AJ15

VSS_184

W2

VSS_116

A32

VSS_213

W8

VSS_117

Y10

VSS_118

Y15

VSS_119

Y18

VSS_120

AJ19

VSS_185

AJ2

VSS_186

AJ22

VSS_187

AJ4

VSS_188

Y20

VSS_121

Y24

VSS_122

AK11

VSS_189

AK13

VSS_190

Y7

VSS_123

AA1

VSS_124

AA11

VSS_125

TMK625DBV23GM_FCBGA812

VSS_191
VSS_192
VSS_193
VSS_194
VSS_126
VSS_127
VSS_128
VSS_195
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_196
VSS_197

GND2

VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_137
VSS_138
VSS_205
VSS_206
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212

E

AK15
AK17
AK19
AK21
AA2
AA22
AA23
AK23
AA4
AA9
AB10
AB12
AB21
AB22
AB23
AB24
AK25
AK27
AK29
AJ5
AH6
AL31
AM1
AM13
AB7
AC1
AM15
AM17
AC11
AC13
AC2
AC21
AC22
AM23
AM27
AM33
AN2
AN32
AM11

K625@

VDDR(+0.9V) decoupling.

+0.9V

1

C25

4.7U_0805_10V4Z

2

3 3

+0.9V

1

C36

1000P_0402_50V7K

2

1

C26

4.7U_0805_10V4Z

2

1

C37

1000P_0402_50V7K

2

1

C27

4.7U_0805_10V4Z

2

1

C38

1000P_0402_50V7K

2

VDD(+CPU_CORE_0) decoupling.

+CPU_CORE_0

1

C50
22U_0805_6.3V6M

2

4 4

+CPU_CORE_0

1

C59
22U_0805_6.3V6M

2

CPU BOT site

L

1

C51
22U_0805_6.3V6M

2

1

C60
22U_0805_6.3V6M

2

A

1

2

1

2

1

2

1

1000P_0402_50V7K

2

C52
22U_0805_6.3V6M

C61
22U_0805_6.3V6M

C28

4.7U_0805_10V4Z

C39

1

C53
22U_0805_6.3V6M

2

1

C62
22U_0805_6.3V6M

2

1

C29

0.22U_0603_16V4Z

2

1

C40
180P_0402_50V8J

2

1

C54

0.22U_0603_16V4Z

2

1

C63

0.22U_0603_16V4Z

2

1

C30

0.22U_0603_16V4Z

2

1

C41
180P_0402_50V8J

2

1

C55

0.01U_0402_25V7K

2

1

C64

0.01U_0402_25V7K

2

B

1

C31

0.22U_0603_16V4Z

2

1

C42
180P_0402_50V8J

2

1

C56
180P_0402_50V8J

2

1

C65
180P_0402_50V8J

2

1

C32

0.22U_0603_16V4Z

2

1

C43
180P_0402_50V8J

2

C526

330U_2.5V_M

VDD(+CPU_CORE_0) decoupling.

+CPU_CORE_0

1

+

C494
330U_SX_2VY~D

2

1

+

C495
330U_SX_2VY~D

2

1

+

C496
330U_SX_2VY~D

2

1

+

C497
330U_SX_2VY~D

@

2

1

C649

4.7U_0805_10V4Z

2

1

2

VDDIO(+1.5V) decoupling.

+1.5V

1

1

+

C44
22U_0805_6.3V6M

2

2

+1.5V

1

C651

0.22U_0603_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

1

C652

0.22U_0603_16V4Z

2

C

C45
22U_0805_6.3V6M

1

C57

4.7U_0805_10V4Z

2

1

C625

0.22U_0603_16V4Z

2

2008/04/14 2009/04/14

1

C58

4.7U_0805_10V4Z

2

1

C626

0.22U_0603_16V4Z

2

Compal Secret Data

Deciphered Date

1

C623

4.7U_0805_10V4Z

2

1

C627

0.22U_0603_16V4Z

2

1

C628

0.22U_0603_16V4Z

2

D

1

C624

4.7U_0805_10V4Z

2

1

2

VDDNB(+VDDNB) decoupling.

+VDDNB

1

C650

4.7U_0805_10V4Z

1

C48
180P_0402_50V8J

2

C46

0.22U_0603_16V4Z

Title

Size Document Number Rev

Custom

Date: Sheet

C33
22U_0805_6.3V6M

2

1

C49
180P_0402_50V8J

2

1

C47

0.22U_0603_16V4Z

2

Compal Electronics, Inc.

AMD CPU S1G2 PWR & GND

1

C34
22U_0805_6.3V6M

2

1

C653
180P_0402_50V8J

2

1

C630

0.1U_0402_16V7K

2

LA-6032P

E

1

C35
22U_0805_6.3V6M

2

1

C629

0.01U_0402_25V7K

2

1

C631

0.1U_0402_16V7K

2

845Tuesday, March 23, 2010

of

1.0

A

B

C

D

E

+VREF_DQ

DDR_A_D0
DDR_A_D1

DDR_A_DM0

DDR_A_D2

1 1

DDR_A_DQS#16
DDR_A_DQS16

DDR_A_DQS#26
DDR_A_DQS26

DDR_CKE0_DIMMA6

2 2

3 3

4 4

DDR_CS1_DIMMA#6

DDR_A_DQS#46
DDR_A_DQS46

DDR_A_DQS#66
DDR_A_DQS66

+3VS

C445

2.2U_0805_10V6K

DDR_A_BS#26

DDR_A_CLK06
DDR_A_CLK#06

DDR_A_BS#06

DDR_A_WE#6

DDR_A_CAS#6 DDR_A_ODT0 6

1

C446

0.1U_0402_16V4Z

2

A

DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

DDR_A_CLK0
DDR_A_CLK#0

DDR_A_MA10
DDR_A_BS#0

DDR_A_WE#
DDR_A_CAS# DDR_A_ODT0

DDR_A_MA13
DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM5

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7

DDR_A_D58
DDR_A_D59

R285 10K_0402_5%

+3VS

1

2

1 2

+1.5V +1.5V

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

12

R286

10K_0402_5%

203

VTT1

205

G1

FOX_AS0A626-U4RN-7F
CONN@

DIMM_A STD H:4mm

<Address: 00>

DQ4
DQ5

VSS3

DQS#0

DQS0
VSS6

DQ6

DQ7
VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

VDD10

CK1
CK1#

VDD12

BA1
RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

SCL
VTT2

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DQS#0

10

DDR_A_DQS0

12
14

DDR_A_D6

16

DDR_A_D7

18
20

DDR_A_D12

22

DDR_A_D13

24
26

DDR_A_DM1

28

MEM_MA_RST#

30
32

DDR_A_D14

34

DDR_A_D15

36
38

DDR_A_D20

40

DDR_A_D21

42
44

DDR_A_DM2

46
48

DDR_A_D22

50

DDR_A_D23

52
54

DDR_A_D28

56

DDR_A_D29

58
60

DDR_A_DQS#3

62

DDR_A_DQS3

64
66

DDR_A_D30

68

DDR_A_D31

70
72

DDR_CKE1_DIMMA

74
76

DDR_A_MA15

78

A15
A14

A11

A7

A6
A4

A2
A0

S0#

G2

80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

B

DDR_A_MA14

DDR_A_MA11
DDR_A_MA7

DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_CLK1
DDR_A_CLK#1

DDR_A_BS#1
DDR_A_RAS#

DDR_CS0_DIMMA#

DDR_A_ODT1

DDR_A_D36
DDR_A_D37

DDR_A_DM4

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

DDR_A_DM6

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

EVENT#_A

+0.75VS

DDR_A_DQS#0 6
DDR_A_DQS0 6

MEM_MA_RST# 6

DDR_A_DQS#3 6
DDR_A_DQS3 6

DDR_CKE1_DIMMA 6

DDR_A_CLK1 6
DDR_A_CLK#1 6

DDR_A_BS#1 6
DDR_A_RAS# 6

DDR_CS0_DIMMA# 6

DDR_A_ODT1 6

1

C431

2

DDR_A_DQS#5 6
DDR_A_DQS5 6

DDR_A_DQS#7 6
DDR_A_DQS7 6

+VREF_CA

1000P_0402_25V8J

DDR_A_D[0..63]

DDR_A_DM[0..7]

DDR_A_MA[0..15]

12/25 Solve layout test point issue

SMB_CK_DAT0 10,21
SMB_CK_CLK0 10,21

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

DDR_A_D[0..63] 6

DDR_A_DM[0..7] 6

DDR_A_MA[0..15] 6

1

C427

2

1000P_0402_25V8J

2

C433

1

0.1U_0402_16V4Z

C443

4.7U_0603_6.3V6K

1

C701
180P_0402_50V8J

2

+1.5V

R281
1K_0402_1%

1 2

R283
1K_0402_1%

1 2

0.1U_0402_16V4Z

C434

1

C444

2

2

C435

1

0.1U_0402_16V4Z

1

C702
180P_0402_50V8J

2

D

2

1

+VREF_DQ

+VREF_DQ

0.01U_0402_25V7K

1

2

C425

C426

@

2

+1.5V

0.1U_0402_16V4Z

2

C432

1

+0.75VS

2

C442

1

0.1U_0402_16V4Z

+1.5V

1

C700
180P_0402_50V8J

2

Compal Secret Data

1

2

1

0.1U_0402_16V4Z

2

1

Deciphered Date

4.7U_0805_10V4Z

0.1U_0402_16V4Z

2008/10/06 2010/03/12

4.7U_0805_10V4Z

0.1U_0402_16V4Z

C436

1

C703
180P_0402_50V8J

2

+1.5V+VREF_CA

R282
1K_0402_1%

1

C428

@

2

2

C437

1

+VREF_CA

0.01U_0402_25V7K

2

C429

1

2

C438

1

0.1U_0402_16V4Z

1

2

1000P_0402_25V8J

0.1U_0402_16V4Z

2

1

C430

C439

0.1U_0402_16V4Z

1 2

1 2

2

C440

1

R284
1K_0402_1%

0.1U_0402_16V4Z

2

C441

1

Place near DIMM1

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRII SO-DIMM 1

LA-6032P

E

945Tuesday, March 23, 2010

1.0

of

A

B

C

D

E

DQ4
DQ5

DQ6
DQ7

DM1

DM2

CK1

BA1

NC2

DM4

DM6

SDA
SCL

+1.5V+1.5V

2

DDR_B_D4

4

DDR_B_D5

6
8

DDR_B_DQS#0

10

DDR_B_DQS0

12
14

DDR_B_D6

16

DDR_B_D7

18
20

DDR_B_D12

22

DDR_B_D13

24
26

DDR_B_DM1

28

MEM_MB_RST#

30
32

DDR_B_D14

34

DDR_B_D15

36
38

DDR_B_D20

40

DDR_B_D21

42
44

DDR_B_DM2

46
48

DDR_B_D22

50

DDR_B_D23

52
54

DDR_B_D28

56

DDR_B_D29

58
60

DDR_B_DQS#3

62

DDR_B_DQS3

64
66

DDR_B_D30

68

DDR_B_D31

70
72

DDR_CKE1_DIMMB

74
76

DDR_B_MA15

78

A15
A14

A11

A7

A6
A4

A2
A0

S0#

G2

80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDR_B_MA14

DDR_B_MA11
DDR_B_MA7

DDR_B_MA6
DDR_B_MA4

DDR_B_MA2
DDR_B_MA0

DDR_B_CLK1
DDR_B_CLK#1

DDR_B_BS#1
DDR_B_RAS#

DDR_CS0_DIMMB#
DDR_B_ODT0DDR_B_CAS#

DDR_B_ODT1

DDR_B_D36
DDR_B_D37

DDR_B_DM4

DDR_B_D38
DDR_B_D39

DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D47

DDR_B_D52
DDR_B_D53

DDR_B_DM6

DDR_B_D54
DDR_B_D55

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

EVENT#_B

+0.75VS

DDR_B_DQS#0 6
DDR_B_DQS0 6

MEM_MB_RST# 6

DDR_B_DQS#3 6
DDR_B_DQS3 6

DDR_CKE1_DIMMB 6

DDR_B_CLK1 6
DDR_B_CLK#1 6

DDR_B_BS#1 6
DDR_B_RAS# 6

DDR_CS0_DIMMB# 6
DDR_B_ODT0 6

DDR_B_ODT1 6

+VREF_CA

1

C453

2

1000P_0402_25V8J

DDR_B_DQS#5 6
DDR_B_DQS5 6

DDR_B_DQS#7 6
DDR_B_DQS7 6

12/25 Solve layout test point issue

SMB_CK_DAT0 9,21
SMB_CK_CLK0 9,21

DDR_B_D[0..63]

DDR_B_DM[0..7]

DDR_B_MA[0..15]

+VREF_DQ

+1.5V

2

1

0.1U_0402_16V4Z

+0.75VS

0.1U_0402_16V4Z

1

C447

2

4.7U_0805_10V4Z

0.1U_0402_16V4Z

C454

0.1U_0402_16V4Z

2

C464

1

DDR_B_D[0..63] 6

DDR_B_DM[0..7] 6

DDR_B_MA[0..15] 6

+VREF_DQ

0.1U_0402_16V4Z

1

C448

2

2

C455

1

0.1U_0402_16V4Z

2

C465

1

4.7U_0603_6.3V6K

1

2

1000P_0402_25V8J

2

C456

1

1

C466

2

+VREF_CA

C449

0.1U_0402_16V4Z

2

C457

1

1

C450

2

4.7U_0805_10V4Z

2

C458

1

0.1U_0402_16V4Z

+VREF_CA

0.1U_0402_16V4Z

1

C451

2

1000P_0402_25V8J

0.1U_0402_16V4Z

2

C459

1

0.1U_0402_16V4Z

C468 Co-layout with C467

Place near DIMM2

1

C452

2

2

1

0.1U_0402_16V4Z

C460

+1.5V

1

+

C468
330U_2.5V_M

2

2

C461

1

2

C462

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C463

1

+VREF_DQ

DDR_B_D0
DDR_B_D1

DDR_B_DM0

DDR_B_D2

+3VS

DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE0_DIMMB

DDR_B_BS#2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

DDR_B_CLK0
DDR_B_CLK#0

DDR_B_MA10
DDR_B_BS#0

DDR_B_WE#

DDR_B_MA13
DDR_CS1_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_DM7

DDR_B_D58
DDR_B_D59

R287 10K_0402_5%

1 2

12

R288

10K_0402_5%

1 1

DDR_B_DQS#16
DDR_B_DQS16

DDR_B_DQS#26
DDR_B_DQS26

DDR_CKE0_DIMMB6

2 2

3 3

4 4

DDR_B_BS#26

DDR_B_CLK06
DDR_B_CLK#06

DDR_B_BS#06

DDR_B_WE#6

DDR_B_CAS#6

DDR_CS1_DIMMB#6

DDR_B_DQS#46
DDR_B_DQS46

DDR_B_DQS#66
DDR_B_DQS66

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4SN-7F

CONN@

VSS3

DQS#0

DQS0

VSS6

VSS8
DQ12
DQ13

VSS10

DQ14
DQ15

DQ20
DQ21

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

VTT2

Security Classification

Issued Date

DIMM_B STD H:4mm

<Address: 01>

A

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/10/06 2010/03/12

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

DDRII SO-DIMM 2

LA-6032P

E

10 45Tuesday, March 23, 2010

1.0

of

A

1 1

< To Card crader >

< To WLAN >

< To LAN >

2 2

H_CADIP[0..15]

H_CADIN[0..15]

3 3

H_CADIP[0..15] 5

H_CADIN[0..15] 5

PCIE_PTX_C_IRX_P130
PCIE_PTX_C_IRX_N130
PCIE_PTX_C_IRX_P226
PCIE_PTX_C_IRX_N226
PCIE_PTX_C_IRX_P327
PCIE_PTX_C_IRX_N327

< From S1G4 CPU : x16 HT> < To S1G4 CPU : x16 HT>

H_CLKOP05
H_CLKON05
H_CLKOP15
H_CLKON15

H_CTLOP05

H_CTLON05

H_CTLOP15

H_CTLON15

4 4

R52 301_0402_1%

L L

SB_RX0P20
SB_RX0N20
SB_RX1P20
SB_RX1N20
SB_RX2P20
SB_RX2N20
SB_RX3P20
SB_RX3N20

1 2

B

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7

H_CADOP8
H_CADON8
H_CADOP9

H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1

U5B

D4

GFX_RX0P

AD4

AD3
AD1
AD2

AE3

AE2

AA8

AA7

AA5
AA6

C4

A3

B3
C2
C1

E5

F5
G5
G6
H5
H6

J6

J5

J7

J8

L5

L6
M8

L8

P7
M7

P5
M5
R8

P8
R6
R5

P4

P3

T4

T3

V5

W6

U5
U6
U8
U7

Y8

Y7

W5

Y5

GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

PART 2 OF 6

PCIE I/F GFX

PCIE I/F GPP

PCIE I/F SB

PCE_CALRP(PCE_BCALRP)

PCE_CALRN(PCE_BCALRN)

RS880M_FCBGA528

U5A

Y25

HT_RXCAD0P

Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

AC24
AC25
AB25
AB24
AA24
AA25

Y22

Y23
W21
W20

V21

V20

U20

U21

U19

U18

T22

T23

AB23
AA22

M22
M23

R21

R20

C23

A24

RS880M_FCBGA528 RS880MR1@

HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_RXCALP
HT_RXCALN

PART 1 OF 6

HYPER TRANSPORT CPU I/F

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P

GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

GPP_TX0P

GPP_TX0N

GPP_TX1P

GPP_TX1N

GPP_TX2P

GPP_TX2N

GPP_TX3P

GPP_TX3N

GPP_TX4P

GPP_TX4N

GPP_TX5P

GPP_TX5N

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

RS880MR1@

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P

HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

HT_TXCLK0P

HT_TXCLK0N

HT_TXCLK1P

HT_TXCLK1N

HT_TXCTL0P

HT_TXCTL0N

HT_TXCTL1P

HT_TXCTL1N

HT_TXCALP
HT_TXCALN

C

HDMI_TXD2+

A5

HDMI_TXD2-

B5

HDMI_TXD1+

A4

HDMI_TXD1-

B4

HDMI_TXD0+

C3

HDMI_TXD0-

B2

HDMI_CLK0+

D1

HDMI_CLK0-

D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2

AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5

AC8
AB8

< If integrated GFX is used, some PCIE pairs are used as HDMI signal pairs >

RS880M Display Port Support (muxed on GFX)

PCIE_ITX_PRX_P1
PCIE_ITX_PRX_N1
PCIE_ITX_PRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P3
PCIE_ITX_PRX_N3

SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C

R51 1.27K_0402_1%
R54 2K_0402_1%

C122 0.1U_0402_16V7K
C123 0.1U_0402_16V7K
C124 0.1U_0402_16V7K
C125 0.1U_0402_16V7K
C126 0.1U_0402_16V7K
C127 0.1U_0402_16V7K

C130 0.1U_0402_16V7K
C131 0.1U_0402_16V7K
C132 0.1U_0402_16V7K
C133 0.1U_0402_16V7K
C134 0.1U_0402_16V7K
C135 0.1U_0402_16V7K
C136 0.1U_0402_16V7K
C137 0.1U_0402_16V7K

1 2
1 2

L

H_CADIP0

D24

H_CADIN0

D25

H_CADIP1

E24

H_CADIN1

E25

H_CADIP2

F24

H_CADIN2

F25

H_CADIP3

F23

H_CADIN3

F22

H_CADIP4

H23

H_CADIN4

H22

H_CADIP5

J25

H_CADIN5

J24

H_CADIP6

K24

H_CADIN6

K25

H_CADIP7

K23

H_CADIN7

K22

H_CADIP8

F21

H_CADIN8

G21

H_CADIP9

G20

H_CADIN9

H21

H_CADIP10

J20

H_CADIN10

J21

H_CADIP11

J18

H_CADIN11

K17

H_CADIP12

L19

H_CADIN12

J19

H_CADIP13

M19

H_CADIN13

L18

H_CADIP14

M21

H_CADIN14

P21

H_CADIP15

P18

H_CADIN15

M18

H_CLKIP0

H24

H_CLKIN0

H25

H_CLKIP1

L21

H_CLKIN1

L20

H_CTLIP0

M24

H_CTLIN0

M25

H_CTLIP1

P19

H_CTLIN1

R18

R53 301_0402_1%

B24
B25

1 2

Place within 1" layout 1:2Place within 1" layout 1:2

HDMI_TXD2+ 19
HDMI_TXD2- 19
HDMI_TXD1+ 19
HDMI_TXD1- 19
HDMI_TXD0+ 19
HDMI_TXD0- 19
HDMI_CLK0+ 19
HDMI_CLK0- 19

GFX_TX0,TX1,TX2 and TX3

GFX_TX4,TX5,TX6 and TX7

1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

R51 within U5 1"
R54 within U5 1"

H_CLKIP0 5
H_CLKIN0 5
H_CLKIP1 5
H_CLKIN1 5

H_CTLIP0 5
H_CTLIN0 5
H_CTLIP1 5
H_CTLIN1 5

AUX0 and HPD0

AUX1 and HPD1

+1.1VS

D

HDMI

PCIE_ITX_C_PRX_P1 30
PCIE_ITX_C_PRX_N1 30
PCIE_ITX_C_PRX_P2 26
PCIE_ITX_C_PRX_N2 26
PCIE_ITX_C_PRX_P3 27
PCIE_ITX_C_PRX_N3 27

SB_TX0P 20
SB_TX0N 20
SB_TX1P 20
SB_TX1N 20
SB_TX2P 20
SB_TX2N 20
SB_TX3P 20
SB_TX3N 20

H_CADOP[0..15]5

H_CADON[0..15]5

< To Card crader >

< To WLAN >

< To LAN >

< To WWAN >

< To SB820 : x4 PCEI A-link>< From SB820 : x4 PCIE A-link >

< TX Impedance Calibrati on. Connect to GND >
< RX Impedance Cali bration. Connect to VDDPCIE >

H_CADOP[0..15]

H_CADON[0..15]

E

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

RS880M HT/PCIE

LA-6032P

11 45Tuesday, March 23, 2010

E

of

1.0Custom

A

B

C

D

E

+3VS

1 2

BLM18PG121SN1D_0603

+1.8VS

1 1

+1.8VS

BLM18PG121SN1D_0603

0_0603_5%

2.2U_0603_6.3V6K

1 2

Total +1.1VS_PLL@230mA

+1.1VS

1 2

BLM18PG121SN1D_0603

2.2U_0603_6.3V6K

2 2

3 3

4 4

Total +1.8VS PLL@100mA

1 2

BLM18PG121SN1D_0603

2.2U_0603_6.3V6K

+1.8VS +VDDA18HTPLL

+1.8VS +VDDA18PCIEPLL

L9

1 2

BLM18PG121SN1D_0603

2.2U_0603_6.3V6K

L10

1 2

BLM18PG121SN1D_0603

2.2U_0603_6.3V6K

+1.8VS

R804

1 2

R63 300_0402_5%

CPU_LDT_REQ# Pull +1.8VS on page 20

+AVDD1@125mA

L3

C139

2.2U_0603_6.3V6K

L5

1

C142

2

L6

C144

2.2U_0603_6.3V6K

C145

C146

C147

C148

CPU_LDT_REQ#

NB_PWRGD

+NB_PLLVDD

1

2

1

2

1

2

1

2

L7

L8

12

1K_0402_5%

1 2

R55 140_0402_1%

1 2

R56 150_0402_1%

1 2

R57 150_0402_1%

+AVDD1

1

2

+AVDD2

1

C143

0.1U_0402_16V4Z

2

+AVDDQ

1

2

+NB_HTPVDD+1.8VS

12/07 Internal clock gen

12

RS15

4.7K_0402_5%

CRT_R_R

CRT_G_R

CRT_B_R

U5C

F12

AVDD1(NC)

E12

AVDD2(NC)

F14

AVDDDI(NC)

G15

AVSSDI(NC)

H15

AVDDQ(NC)

H14

AVSSQ(NC)

E17

C_Pr(DFT_GPIO5 )

F17

Y(DFT_GPIO2)

F15

COMP_Pb(DFT_GPIO4)

G18

RED(DFT_GPIO0)

G17

REDb(NC)

E18

GREEN(DFT_ GPIO1)

F18

GREENb(NC)

E19

BLUE(DFT_GPIO3)

F19

BLUEb(NC)

A11

DAC_HSYNC(PWM_GPIO4)

B11

DAC_VSYNC(PWM_GPIO6)

F8

DAC_SCL(PCE_RCALRN)

E8

DAC_SDA(PCE_TCALRN)

G14

DAC_RSET(PWM_GPIO1)

A12

PLLVDD(NC)

D14

PLLVDD18(NC)

B12

PLLVSS(NC)

H17

VDDA18HTPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

D8

SYSRESETb

A10

POWERGOOD

C10

LDTSTOPb

C12

ALLOW_LDTSTOP

C25

HT_REFCLKP

C24

HT_REFCLKN

E11

REFCLK_P/OSCIN(OSCIN)

F11

REFCLK_N(PWM_GPIO3)

T2

GFX_REFCL KP

T1

GFX_REFCL KN

U1

GPP_REFCLKP

U2

GPP_REFCLKN

V4

GPPSB_REFCLKP(SB_REFCLKP)

V3

GPPSB_REFCLKN(SB_REFCLKN)

B9

I2C_CLK

A9

I2C_DATA

B8

DDC_DATA0/AUX0N(NC)

A8

DDC_CLK0/AUX0P(NC)

B7

DDC_CLK1/AUX1P(NC)

A7

DDC_DATA1/AUX1N(NC)

B10

STRP_DATA

G11

RSVD

C8

AUX_CAL(NC)

PART 3 OF 6

RS880M_FCBGA528

+1.8VS

R805

2.2K_0402_5%

E

3 1

MMBT3904_NL_SOT23-3

R822 0_0402_5%

1 2

+1.8VS

12

B

2

Q36

C

@

TXOUT_L2N(DBG_GPIO0)

TXOUT_L3N(DBG_GPIO2)

TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)

TXOUT_U3P(PCIE_RESET_GPIO5)

CRT/TVOUT

TXCLK_LP(DBG_GPIO1)

TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)

LVTM

PM

LVDS_DIGON(P CE_TCALRP)

LVDS_BLON(PCE_RCALRP)

LVDS_ENA_BL(PWM_GPIO2)

CLOCKs PLL PWR

MIS.

SUS_STAT#(PWM_GPIO5)

12

R806

2.2K_0402_5%

NB_LDTSTOP#

TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)

TXOUT_L3P(NC)

TXOUT_U0P(NC)
TXOUT_U0N(NC)

TXOUT_U2P(NC)
TXOUT_U2N(NC)

TXOUT_U3N(NC)

VDDLTP18(NC)

VSSLTP18(NC)

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

TMDS_HPD(NC)

HPD(NC)

THERMALDIODE_P
THERMALDIODE_N

TESTMODE

RS880MR1@

A22
B22
A21
B21
B20
A20
A19

< LVDS dual channel : channel 1 >

B19

B18
A18
A17
B17
D20
D21
D18
D19

B16
A16
D16
D17

+VDDLTP18

A13
B13

+VDDLT18

A15
B15
A14
B14

C14
D15
C16
C18
C20
E20
C22

E9
F7
G12

12

@

4.7K_0402_5%

R778

HPD

D9
D10

SUS_STAT#

D12

AE8
AD8

D13

1 2

R65 1.8K_0402_5%

12

@

R781

4.7K_0402_5%

VARY_ENBKL

LCD_TXOUT0+ 18
LCD_TXOUT0- 18
LCD_TXOUT1+ 18
LCD_TXOUT1- 18
LCD_TXOUT2+ 18
LCD_TXOUT2- 18

LCD_TXCLK+ 18
LCD_TXCLK- 18

12

@

R779

Strap pin

2/2 Fine tune pin define

PLT_RST#15,20,26,27,30,31,32

NBGFX_CLK
NBGFX_CLK#

12

RS16

4.7K_0402_5%

LCD_EDID_CLK18

LCD_EDID_DATA18

+AVDD1

+AVDD2

+AVDDQ

CRT_HSYNC15,17

CRT_VSYNC15,17
UMA_CRT_CLK17
UMA_CRT_DATA17

R58 715_0402_1%

+NB_PLLVDD

+NB_HTPVDD

+VDDA18HTPLL

+VDDA18PCIEPLL

R59

1 2

NB_PWRGD21

CPU_LDT_REQ#20

CLK_NBHT20
CLK_NBHT#20

CLK_NB_REFCLK20
CLK_NB_REFCLK#20

CLK_SBLINK_BCLK20
CLK_SBLINK_BCLK#20

HDMIDAT_UMA19

HDMICLK_UMA19

+3VS

R66 150_0402_1%

CRT_R_R

CRT_G_R

CRT_B_R

UMA_CRT_CLK
UMA_CRT_DATA

1 2

0_0402_5%

R64 10K_0402_5%

@

NB_RESET#
NB_PWRGD
NB_LDTSTOP#
CPU_LDT_REQ#

CLK_NBHT
CLK_NBHT#

CLK_NB_REFCLK
CLK_NB_REFCLK#

NBGFX_CLK
NBGFX_CLK#

CLK_SBLINK_BCLK
CLK_SBLINK_BCLK#

LCD_EDID_CLK
LCD_EDID_DATA
HDMIDAT_UMA
HDMICLK_UMA

@

12

AUX_CAL

12

Strap pin

LDT_STOP#7,20

Contact with NB signal Contact to CRT conn signal

CRT_R_R

L41 NBQ100505T-800Y-N_2P

CRT_G_R

CRT_B_R

1 2

L42 NBQ100505T-800Y-N_2P

1 2

L43 NBQ100505T-800Y-N_2P

1 2

1

C913

2.2P_0402_50V8C

2

1

C912

2.2P_0402_50V8C

2

1

C911

2.2P_0402_50V8C

2

CRT_R 17

CRT_G 17

CRT_B 17

+VDDLT18@220mA

+VDDLTP18

+VDDLT18

C140

0.1U_0402_16V4Z

If support VB, R780 R777->SMT, R776->@
If no support VB, R776-->SMT, R780 R777->@

R776 0_0402_5%@

1 2

R780 0_0402_5%

1 2

R777 0_0402_5%

1 2

4.7K_0402_5%

PS:Need to fine tune R783 and R784 on Page17

HPD 19

SUS_STAT# 15,21

< HDMI hot-plug detecti on >

< Strap option pin or gate s ide-port memory IO >

1 2

BLM18PG121SN1D_0603

1

C138

2

2.2U_0603_6.3V6K

BLM18PG121SN1D_0603

1

1

C141

2

2

4.7U_0805_10V4Z

UMA_ENVDD 18

UMA_ENBKL 31

GMCH_INVT_PWM 18

L2

L4

1 2

+1.8VS

+1.8VS

2/2 Add L41 L42 L43 C911 C912 C913 for EMI request

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

RS880M VEDIO/CLK GEN

LA-6032P

12 45Tuesday, March 23, 2010

E

of

1.0

2

1

@

SP_DDR3_RST#21

MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12

MEM_A13

MEM_BA0
MEM_BA1
MEM_BA2

MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE
MEM_ODT

MEM_CLKP
MEM_CLKN

MEM_COMP_P

MEM_COMP_N

12

R341 10K_0402_5%SIDE@

243_0402_1%

/

Security Classification

+MEM_VREF MEM_DQ0

MEM_BA0
MEM_BA1
MEM_BA2

MEM_CKE

MEM_ODT
MEM_CS#
MEM_RAS#
MEM_CAS#
MEM_WE#

MEM_DQS_P0
MEM_DQS_P1

MEM_DM0
MEM_DM1

MEM_DQS_N0
MEM_DQS_N1

+1.5VS

2

SIDE@

C600
1U_0402_6.3V4Z

1

B B

A A

+1.5VS

1

2

1

2

+1.5VS

1

2

1

2

2

SIDE@

C601
1U_0402_6.3V4Z

1

SIDE@

C608

0.1U_0402_16V4Z

SIDE@

C609

0.1U_0402_16V4Z

SIDE@

C610

0.1U_0402_16V4Z

SIDE@

C611

0.1U_0402_16V4Z

1

SIDE@

C602

0.1U_0402_16V4Z

2

SIDE@

R335
1K_0402_1%

1 2

+MEM_VREF

SIDE@

R337
1K_0402_1%

1 2

SIDE@

R338
1K_0402_1%

1 2

+MEM_VREF1

SIDE@

R339
1K_0402_1%

1 2

1

SIDE@

C603

0.1U_0402_16V4Z

2

1

SIDE@

C614

10U_0603_6.3V6M

2

1

SIDE@

C604
10U_0603_6.3V6M

2

R334

SIDE@

SIDE@

+1.5VS

MEM_COMP_P and MEM_COMP_N trace
width >=10mils and 10mils s pacing from
other Signals in X,Y, Z directions

R336

12

12

+1.5VS

For Side port only

40.2_0402_1%

40.2_0402_1%

R340 100_0402_1%

MEM_CLKP
MEM_CLKN

12

R342

SIDE@

AB12
AE16

V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14

Y14

AD16
AE17
AD17

W12

Y12
AD18
AB13
AB18

V14

V15

W14

AE12
AD12

MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13

U5D

1 2

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PAR 4 OF 6

MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)

MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)

MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)

MEM_CKP(NC)
MEM_CKN(NC)

MEM_COMPP(NC)
MEM_COMPN(NC)

M9
H2

N4
P8
P4
N3
P9
P3
R9
R3

T9

R4

L8
R8
N8

T4

T8
M8

M3
N9
M4

J8
K8

K10

K2

L3

J4
K4

L4

F4
C8

E8
D4

G4
B8

T3

L9

J2

L2

J10

L10

A1

A11

T1

T11

2008/04/14 2009/04/14

MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)

MEM_DQ2/DVO_DE(NC)

MEM_DQ3/DVO_D0(NC)

MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)

MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)

MEM_DQ12(NC)

MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

MEM_DQS0P/DVO_IDCKP(NC)

MEM_DQS0N/DVO_IDCKN(NC)

MEM_DQS1P(NC)
MEM_DQS1N(NC)

MEM_DM0(NC)

MEM_DM1/DVO_D8(NC)

SBD_MEM/DVO_I/F

RS880M_FCBGA528RS880MR1@

U27

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

BA0
BA1
BA2

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET

ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NC/ZQ1

NC
NC
NC
NC

100-BALL
SDRAM DDR3

K4W1G1646D-EC15_FBGA100

SIDE@

IOPLLVDD18(NC)

IOPLLVDD(NC)

MEM_VREF(NC)

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

Compal Secret Data

IOPLLVSS(NC)

E4
F8
F3
F9
H4
H9
G3
H8

D8
C4
C9
C3
A8
A3
B9
A4

B3
D10
G8
K3
K9
N2
N10
R2
R10

A2
A9
C2
C10
D3
E10
F2
H3
H10

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

B2
B10
D2
D9
E3
E9
F10
G2
G10

Deciphered Date

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

Y17
W18
AD20
AE21

W17
AE19

AE23
AE24

AD23

AE18

MEM_DQ6
MEM_DQ2
MEM_DQ5
MEM_DQ3
MEM_DQ7
MEM_DQ1
MEM_DQ4

MEM_DQ11
MEM_DQ15
MEM_DQ9
MEM_DQ10
MEM_DQ12
MEM_DQ14
MEM_DQ8
MEM_DQ13

+1.5VS

MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15

MEM_DQS_P0
MEM_DQS_N0
MEM_DQS_P1
MEM_DQS_N1

MEM_DM0
MEM_DM1

+1.8V_IOPLLVDD
+NB_IOPLLVDD

+MEM_VREF1

R332

0_0603_5%

1 2

1

SIDE@

C605

2.2U_0603_6.3V4Z

2

R333

0_0603_5%

1 2

1

SIDE@

C606

2.2U_0603_6.3V4Z

2

Title

Size Document Number Rev

Custom

1

Date: Sheet

Compal Electronics, Inc.

RS880M SIDE PORT

+1.8VS

+1.1VS

LA-6032P

13 45Tuesday, March 23, 2010

1.0

of

A

1 1

2 2

3 3

+1.1VS

+1.1VS

+1.8VS

0_0805_5%

0_0805_5%

0_0805_5%

4.7U_0805_10V4Z

+VDDHT/+VDDHTRX@680mA

L12

12

1

C150

C151

2

4.7U_0805_10V4Z

L13

L14

0_0805_5%

L16

0.1U_0402_16V4Z

12

C156

10U_0805_10V6K

12

4.7U_0805_10V4Z

12

C173

4.7U_0805_10V4Z

1U_0402_6.3V4Z

1

C162

C157

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+VDDHTTX@680mA

1

C169

C168

2

0.1U_0402_16V4Z

+VDDA18PCIE@640mA

1

1

C175

C174

2

2

0.1U_0402_16V4Z

+1.8VS

1

C192

2

1

1

C152

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C163

2

0.1U_0402_16V4Z

1

1

C170

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C179

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C153

C171

C180

1

C158

2

1

C154

2

0.1U_0402_16V4Z

+VDDHTRX

1

2

0.1U_0402_16V4Z

1

C172

2

0.1U_0402_16V4Z

1

C176

2

0.1U_0402_16V4Z

5mA

+1.8VS

+VDDHT

1

2

+VDDHTTX

1

2

+VDDA18PCIE

1

2

1 2

0_0603_5%

50mA

B

U5E

J17

VDDHT_1

K16

2A

L18

L16
M16
P16
R16
T16

H18
G19
F20
E21
D22
B23
A23

AE25
AD24
AC23
AB22
AA21

Y20

W19

V18
U17
T17
R17
P17

M17

P10
K10

M10

L10

T10
R10

AA9
AB9

AD9

AE9
U10

AE11
AD11

1

SIDE@

C193
1U_0402_6.3V4Z

2

J10

W9

H9

Y9

F9

G9

PART 5/6

VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7

VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13

VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15

VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)

RS880M_FCBGA528 RS880MR1@

+VDDA11PCIE@2500mA

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8

VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12

POWER

VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)

VDD33_1(NC)
VDD33_2(NC)

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

AE10
AA11
Y11
AD10
AB10
AC10

H11
H12

C

+VDDA11PCIE

60mA

1 2

FBMA-L11-201209-221LMA30T_0805

C159

C155

C160 1U_0402_6.3V4Z
C161 1U_0402_6.3V4Z
C164 1U_0402_6.3V4Z
C165 1U_0402_6.3V4Z
C166 0.1U_0402_16V4Z
C167 0.1U_0402_16V4Z

+NB_CORE@7600mA

1

1

1

C1810.1U_0402_16V4Z

2

+3VS

1

C1820.1U_0402_16V4Z

2

1

1

C1840.1U_0402_16V4Z

C1830.1U_0402_16V4Z

C1850.1U_0402_16V4Z

C1770.1U_0402_16V4Z

2

2

2

2

1 2

1 2

L11

1 2
1 2
1 2
1 2

1

C1860.1U_0402_16V4Z

2

10U_0805_10V6K

10U_0805_10V6K

12
12

1

1

C1870.1U_0402_16V4Z

C1780.1U_0402_16V4Z

2

2

C1940.1U_0402_16V4Z

C2000.1U_0402_16V4Z

1

C18810U_0805_10V6K

2

+NB_CORE

1

C18910U_0805_10V6K

2

0_0402_5%

NOSIDE@

R67

+1.1VS

C191

1

2

1000P_0402_50V7K

D

U5F

A25

VSSAHT1

D23

VSSAHT2

E22

VSSAHT3

G22

VSSAHT4

G24

VSSAHT5

G25

VSSAHT6

H19

VSSAHT7

J22

VSSAHT8

L17

VSSAHT9

L22

VSSAHT10

L24

VSSAHT11

L25

VSSAHT12

M20

VSSAHT13

N22

VSSAHT14

P20

VSSAHT15

R19

VSSAHT16

R22

VSSAHT17

R24

VSSAHT18

R25

VSSAHT19

H20

VSSAHT20

U22

VSSAHT21

V19

VSSAHT22

W22

VSSAHT23

W24

VSSAHT24

W25

VSSAHT25

Y21

VSSAHT26

AD25

VSSAHT27

L12

VSS11

M14

VSS12

N13

VSS13

P12

VSS14

P15

VSS15

R11

VSS16

R14

VSS17

T12

VSS18

U14

VSS19

U11

VSS20

U15

VSS21

V12

VSS22

W11

VSS23

W15

VSS24

AC12

VSS25

1

C5970.1U_0402_16V4Z SIDE@

2

AA14

VSS26

Y18

VSS27

AB11

VSS28

AB15

VSS29

AB17

VSS30

AB19

VSS31

AE20

VSS32

AB21

VSS33

K11

VSS34

RS880M_FCBGA528 RS880MR1@

L82

SIDE@

1 2

0_0603_5%

1

1

C5990.1U_0402_16V4Z SIDE@

C5980.1U_0402_16V4Z SIDE@

2

2

12

1

1

C6131U_0402_6.3V4Z SIDE@

C6124.7U_0805_10V4Z SIDE@

2

2

PART 6/6

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8

VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30

GROUND

VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

VSS10

+1.8VS

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

E

4 4

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

RS880MPWR/GND

LA-6032P

14 45Tuesday, March 23, 2010

E

1.0Custom

of