Cirrus Logic CS48DV2B User Manual

CS48DV2B Data Sheet

FEATURES

 World’s most cost-effective 32-bit DSP featuring Dolby

Volum e and Audistry

— Supports native processing at input Fs up to 48kHz
— Single download image enables su pport for 32 KHz,

44.1 kHz, and 48 kHz audio input

 CS48DV2B supports up to 2.0 channels of audio input

and up to 2.1 channels of output

 Enables concurrent processing features beyond Dolby

Volum e including Tone Control, Multiba nd Parametric EQ,
Bass Management, Delays.

 Configurable Serial Audio Inputs/Outputs

— Configurable for all input/output digital audio types

2

(I

S/LJ/RJ)

— 32-bit data path delivers uncompromised dynamic

range
— 192 kHz capable integra ted S/PDIF trans mitte r
— DAO can operate in master o r slave mod e (SCLK &

LRCLK)

 Integrated Clock Manager/PLL

— Capable of operating from a wide va riety of external

crystals or external oscillators

 Slave Host Boot Capability via Serial Interface

— SPI

 1.8V Core and 3.3V I/O that is tolerant to 5V input
 Low-power Mode enabled

—Energy Star® Design Compli ance Capability via low-

™

interface capable of running up to 25 MHz

during run time

power mode, 268 µW in Standby mode

®

by Dolby

The new CS48DV2B supports a host of signal processing
applications concurre ntly, including the mass production -ready

®

Dolby Volume solution. See Section 3. for details about
firmware concurrency on the CS48DV2B. The target
applications for the CS48DV2B DSP are:

— Digital Televisions
— Soundbars / DTVs with Integrated Soundbars

®

—PMD/iPod
— Automotive Head Units
— Automotive Outboard Amplifiers

— Blu-ray Disc
— PC Speakers

All of these applications and many more that use volume
control and are subject to playback from sources that do not
have consistent volume le vels w ill bene fit from the CS48D V2B
Dolby Volume solution.

Docking Stations

®

& DVD Receivers / HTiBs

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Ordering Information:

See page 21 for ordering informat ion.

A

2.0 Ch.

Audio In

S/PDIF

Up to 2.1 Ch

Audio Out

Serial

Control 1

32-bit

DSP

P X Y

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GPIO Debug

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Copyright 2009 Cirrus Logic FEB ’09

http://www.cirrus.com

CONFIDENTIAL DS875F2

Watchdog

TMR1
TMR2

PLL

CS48DV2B Data Sheet

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32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

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Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject t
change without notice and is provided “A S IS” witho ut warranty of any kind (express or implied). Customers are advised to obtai n t he lat est versi on of rel evant i nf o
mation to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplie
at the time of ord er a cknowl edgment, including those pertaining to warranty, i n demn if ica t i on, and limitation of l i ability. No responsibility is assumed by Cirrus for th
use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties
This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights
trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copie
to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not exten
to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOL VE POTENTIAL RISKS OF DEATH, PERS ONAL INJURY, OR SEVERE PRO PER
TY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIO NS” ). CIRRUS PRO D UCT S ARE NO T DES IGNED, AUTHORIZED OR WARRANTED FOR USE IN
PRODUCTS SURGICALLY IMPLANTED INTO T HE BODY, AUTOMO TIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICA
APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRU
DISCLAIMS AND MAKES NO WARRAN TY, EXPRE SS, STAT UTORY OR IMPLIED, INCLUDING THE IMPLIED WARRAN TIES OF MERCHAN TABILITY AND FIT
NESS FOR PARTICULAR PUR POSE, WITH REGARD TO ANY CIRRUS PRODUCT T HAT IS US ED IN SUCH A MANNER . IF THE C USTOMER OR CUSTOME R'
CUSTOMER USES OR PERMITS TH E USE O F C IRRUS PRO D UCTS IN CRITICAL APPLICATIONS, CUSTOMER AGR EES, BY SUCH USE, TO FULLY INDEM
NIFY CIRRUS, ITS OFFICERS, DIRECTORS, EM PLOYEES, DISTRIBU TORS AND OT HER AGENT S FROM ANY AN D ALL LIABILITY, INCLUD ING ATTORNEYS
FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, the Cirrus Logic l ogo desi gn s, DSP Composer is a tradem arks of Cir r us Logic, Inc. All other brand and product names in this document may b
trademarks or service marks of their respective owners.

Dolby, Audistry, and the sound shell logo are registered trademarks of Dolby Laboratories. Supply of an implementation of Dolby Technology does not convey a licens
nor imply a right u nder any patent, or any o ther industrial or In tel l ectual Property Right of Dol by Laboratories, to use the I mp le mentation in any finished end-user o
ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories.

SPI is a trademark of Motorola, Inc.

2

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C is a registered trademark of Philips Semiconductor.
iPod is a registered trademark of Apple Computer, Inc.
Blu-ray Disc is a registered trademark of SONY KABUSHIKI KAISHA CORPORATION.
Energy Star is a registered trademark of the Environmental Protection Agency, a federal agency of the United States government.

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www.cirrus.com

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2 Copyright 2009 Cirrus Logic DS875F2

CONFIDENTIAL

CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

Table of Contents

1. Documentation Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.1 Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3. Code Overlays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

4. Hardware Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

4.1 DSP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.1.1 DSP Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.1.2 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.2 On-chip DSP Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.1 Digital Audio Input Port (DAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.2 Digital Audio Output Port (DAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.3 Serial Control Port (I

4.2.4 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.5 PLL-based Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.6 Hardware Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.3 DSP I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.3.1 Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.3.2 Termination Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.3.3 Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.4 Application Code Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5. Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.3 Digital DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.4 Power Supply Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5.5 Thermal Data (48-Pin LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5.6 Switching Characteristics— RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.7 Switching Characteristics — XTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.8 Switching Characteristics — Internal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.10 Switching Characteristics — Serial Control Port - SPI Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.11 Switching Characteristics — Serial Control Port - I

5.12 Switching Characteristics — Serial Control Port - I

5.13 Switching Characteristics — Digital Audio Slave Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.14 Switching Characteristics — DSD Slave Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.15 Switching Characteristics — Digital Audio Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

7. Environmental, Manufac turi ng, & Handli ng Infor mation . . . . . . . . . . . . . . . . . . . . . . . . . .22

8. Device Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

8.1 CS48DV2B, 48-pin LQFP Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.2 48-pin LQFP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

2C®

or SPI™) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

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2

C Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2

C Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 17

HI

DELP

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DS875F2 Copyright 2009 Cirrus Logic 3

CONFIDENTIAL

CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

List of Figures

Figure 1. RESET Timing ......................................................................................................................................... 12

Figure 2. XTI Timing ............................................................................................................................................... 12

Figure 3. Serial Control Port - SPI Slave Mode Timing...........................................................................................14

Figure 4. Serial Control Port - SPI Master Mode Timing.........................................................................................15

Figure 5. Serial Control Port - I
Figure 6. Serial Control Port - I

Figure 7. Digital Audio Input (DAI) Port Timing Diagram ........................................................................................18

Figure 8. Direct Stream Digital - Serial Audio Input Timing..................................................................................... 18

Figure 9. Digital Audio Output Port Timing, Master Mode.......................................................................................20

Figure 10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)............................................ 20

Figure 11. CS48DV2B 48-Pin LQFP Pinout Diagram............................................................................................. 23

Figure 12. 48-Pin LQFP Package Drawing............................................................................................................. 24

2

C Slave Mode Timing ........................................................................................... 16

2

C Master Mode Timing ......................................................................................... 17

FT

List of Tables

Table 1. CS48DV2B DSP Related Documentation................................................................................................5

Table 2. Device and Firmware Selection Guide.....................................................................................................7

Table 3. Ordering Information..............................................................................................................................21

Table 4. Environmental, Manufacturing, & Handling Information.........................................................................22

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4 Copyright 2009 Cirrus Logic DS875F2

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CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

1. Documentation Strategy

The CS48DV2B Data Sheet describes CS48DV2B multichannel audio processors. This document
should be used in conjunction with the following documents when evaluating or designing a system
around the CS48DV2B processors.

Table 1. CS48DV2B DSP Related Documentation

Document Name Description

CS48DV2B Data Sheet This document

Includes detai led system des ign information inc luding

CS485xx Family Hardware User’s Manual

AN298 - CS485xx Family Firmware User’s Manual

Typical Connection Diagrams, Boot-Procedures, Pin
Descriptions, etc.

Includes detailed firmware design information
including signal processing flow diagram s and cont rol
API information

FT

DSP Composer User’s Manual

®

AN298VPMA,Audistry

AN298PPMN, Dolby® Volume Firmware User’s

Manual for the CS48DV2x Family

The scope of the CS48DV2B Data Sheet is primarily the hardware specifications of the CS48DV2B
devices. This includes hardware functionality, characteristic data, pinout, and packaging information.

The intended audience for the CS48DV2B Data Sheet is the system PCB designer, MCU
programmer, and the quality control engineer.

2. Overview

The CS48DV2B DSP is designed to provide high-performance post-processing and mixing of digital
audio. The dual clock domain provided on the PCM inputs all ows for the mixi ng of audio streams wit h
different sampling frequencies. The low-power standby preserves battery life for applications which
are always on, but not necessarily processing audio, such as automotive audio systems.

The CS48DV2B supports dual input clock domains and dual audio processing paths. The
CS48DV2B is available in a 48-pin QFP package. Please refer to Table 2 on page 7 for the input,
output, firmware features of each device.

by Dolby

®”

Includes detailed configuration and usage
information for the GUI development tool.

Describes API used to control the Audistry firmware
module.

Describes API used to control the Dolby Volume
firmware module.

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2.1 Licensing

Licenses are required for all of the 3rd party audio processing algorithms listed in Section 3. Please
contact your local Cirrus Logic Sales representative for more informat ion.

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DS875F2 Copyright 2009 Cirrus Logic 5

CONFIDENTIAL

CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

3. Code Overlays

The suite of software available for the CS48DV2B DSP consists of an operating system (OS) and a
library of overlays. The overlays have been divided into three main groups called Matrix-processors,
Virtualizer-processors, and Post-processors. All sof tware components are defined below:

1. OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external
memory, processing host messages, calling audio-processing subroutines, error concealment,
etc.

2. Matrix-processor- Any Module that performs a matrix decode on PCM data to produce more

®

output channels than input channels (2Ön channels). Examples are Dolby
DTS Neo:6

audio I/O buffer.

3. Virtualizer-processor - Any module that encodes PCM data into fewer output channels than
input channels (nÖ2 channels) with the effect of providing “phantom” speakers to represent the

physical audio channels that were eliminated. Examples are Dolby Headphone
Virtual S peaker

audio I/O buffer.

™

. Generally speaking, these modules increase the number of valid channels in the

®

. Generally speaking, these modules reduce the number of valid channel s in the

Pro Logic® IIx and

FT

®

and Dolby®

4. Post-processors - Any module that processes audio I/O buffer PCM data in-place after the
matrix- or virtualizer-processors. Examples are the Dolby Volume and Audistry by Dolby
firmware, bass management, audio manager, tone control, EQ, delay, and customer- specific
effects

The bulk of each overlay is stored in ROM within the CS48DV2B, but a small image is required to

configure the overlays and boot the DSP. This small image can either be stored in an external serial
FLASH/EEPROM, or downloaded via a host controller through the

The overlay structure reduces the t ime required t o reconfigu re the DSP when a process ing change is
requested. Each overlay can be reloaded independently without disturbing the other overlays. For
example, when a new matrix-processor is selected, the OS, virtualizer-, and post-processors do not
need to be reloaded — only the new matrix-processor. This fact is also true for the other overlays.

Table 2 lists the firmware available based on device selection. Please refer to AN298, CS485xx

Firmware User’s Manual for the latest listing of application codes and Cirrus Framework
available.

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SPI™/I2C

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serial port.

™ modules

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6 Copyright 2009 Cirrus Logic DS875F2

CONFIDENTIAL

CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

Table 2. Device and Firmware Selection Guide

Devices Availability Suggested Applications Specific Features

• Digital TV
Portable Audio
Docking Station

• Portable DVD

CS48DV2B-CQZ

In Production Now

CS48DV2B-DQZ

4. Hardware Functional Description

4.1 DSP Core

The CS48DV2B DSPs are single-core DSP with separate X and Y data and P code memory spaces .
The DSP core is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of
performing two multiply-and-accumulate (MAC) operations per clock cycle. The DSP core has eight
72-bit accumulators, four X- and four Y-data registers, and 12 index registers.

The DSP core is coupled to a flexible DMA engine. The DMA engine can move data between
peripherals such as the serial control port (SCP), digital audio input (DAI) and digital audio output
(DAO), or any DSP core memory, all without the intervention of the DSP. The DMA engine off loads
data move instructions from the DSP core, leaving more MIPS available for signal processing
instructions.

Players

• Multimedia PC
Speakers

• Soundbars

• Automotive
Entertainment
Systems

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• 2.1 channels of audio
input and 2.1
channels of PCM
audio output.

• 512 FFT Window, 20­Bands/Channel

• Dolby Volume Native
Processing of the
following Fs:

— 32 kHz
— 44.1 kHz

FT

— 48 kHz

CS48DV2B functionality is controlled by application codes that are stored in on-board ROM or

downloaded to the CS48DV2B from a host controller or external serial FLASH/EEPROM.

Users can develop their applications using DSP Composer to create the processing chain and then
compile the image into a series of commands that are sent to the CS48DV2B through the SCP. The
processing application can either load modules (matrix-processors, virtualizers, post-processors)
from the DSPs on-board ROM, or custom firmware can be downloaded through the SCP.

The CS48DV2B is suitable for a variety of audio post-processing applications such as automotive
head-ends, automotive amplifiers, and boom boxes.

4.1.1 DSP Memory

The DSP core has its own on-chip data and program RAM and ROM and does not require external
memory for post-processing applications.

The Y-RAM and P-RAM share a single block of memory that can be configured to make Y and P
equal in size, or more memory can be allocated for Y-RAM in 2kword blocks.

4.1.2 DMA Controller

The powerful 8-channel DMA controller can move data between 8 on-chip resources. Each resource
has its own arbiter: X, Y, and P RAMs/ROMs and the peripheral bus. Modulo and linear addressing

DS875F2 Copyright 2009 Cirrus Logic 7

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CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

modes are supported, with flexible start address and increment controls. The service intervals for
each DMA channel, as well as up to 6 interrupt events, are programmable.

4.2 On-chip DSP Peripherals

4.2.1 Digital Audio Input Port (DAI)

The DAI port supports a wide variety of data input formats at sample rates (Fs) as high as 192 kHz.
The port is capable of accepting PCM or DSD formats. Up to 32-bi t word l engths are supported. DSD
is supported and internally converted to PCM before processing. The DAI also supports a time
division multiplexed (TDM) one-line data mode that packs multiple chann els of PCM audio input on a
single data line. The total number of channels that are possible depends on the ratio of SCLK to
LRCLK.

The port has two independent slave-only clock domains. Each data input can be independently
assigned to a clock domain. The sample rate of the input clock domains can be determined
automatically by the DSP, off-loading the task of monitoring the S/PDIF receiver from the host. A
time-stamping feature allows the i nput data to be sample-rate converted via softwar e.

4.2.2 Digital Audio Output Port (DAO)

DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high as
192 kHz. The port can be configured as an independent clock domain mastered by the DSP, or as a
clock slave if an external MCLK or SCLK/LRCLK source is available. One of the serial audio pins can
be re-configured as a S/PDIF transmitter that drives a bi-phase encoded S/PDIF signal (data with
embedded clock on a single line).

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The DAO also supports a time division multiplexed (TDM) one-line data mode, that packs multiple
channels of PCM audio on a single data line.

2C®

4.2.3 Serial Control Port (I

The on-chip serial control port is capable of operating as master or slave in either
modes. Master/Slave operation is chosen by mode select pins when the CS48DV2B comes out of
Reset. The serial clock pin can support frequencies as high as 25 MHz in SPI mode ( SPI clock speed
must always be ≤ (F

the communications interface (SCP_BSY
host (SCP_IRQ

dclk

).

or SPI™)

/2)). The CS48DV2B serial control port also includes a pin for flow control of

) and a pin to indicate when the DSP has a message for the

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4.2.4 GPIO

Many of the CS48DV2B peripheral pins are multiple xed with GPIO. Each GPIO can be configur ed as
an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising
edge, falling edge, active-low, or active-high.

4.2.5 PLL-based Clock Generator

The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used
to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock
domain can be output on the DAO port for driving audio converters. The CS48DV2B defaults to
running from the external reference frequency and is switched to use the PLL output after overlays
have been loaded and configured, either through master boot from an external FLASH or through
host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output
frequency ratio is selectable between 1:1 (default) or 2:1.

CONFIDENTI

®

8 Copyright 2009 Cirrus Logic DS875F2

CONFIDENTIAL

CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

4.2.6 Hardware Watchdog Timer

The CS48DV2B has an integrated watchdog timer that acts as a “health” monitor for the DSP. The
watchdog timer must be reset by the DSP before the counter expires, or the entire chip is reset. This
peripheral ensures that the CS48DV2B will reset itself in the event of a temporary system failure. In
stand-alone mode (that is, no host MCU), the DSP will reboot from external FLASH. In slave mode
(that is, host MCU present) a GPIO will be used to signal the host that the watchdog has expired and
the DSP should be rebooted and re-configured.

4.3 DSP I/O Description

4.3.1 Multiplexed Pins

Many of the CS48DV2B pins are multi-functional. For details on pin functionality please refer to the
CS485xx Hardware User’s Manual.

4.3.2 Termination Requirements

Open-drain pins on the CS48DV2B must be pulled high for proper operation. Please refer to the
CS485xx Hardware User’s Manual to identify which pins are open-drain and what value of pull-up
resistor is required for proper operation.

Mode select pins in the CS48DV2B are used to select the boot mode upon the rising edge from
reset. A detailed explanation of termination requirements for each communication mode select pin
can be found in the CS485xx Hardware User’s Manual.

4.3.3 Pads

DRA

FT

The CS48DV2B I/Os operate from the 3.3 V supply and are 5 V tolerant.

4.4 Application Code Security

The external program code may be encrypted by the programmer to protect any int ellectual property
it may contain. A secret, customer-specific key is used to encrypt the program code that is to be
stored external to the device. Please contact your local Cirrus representative for details.

L

A

HI

DELP

CONFIDENTI

DS875F2 Copyright 2009 Cirrus Logic 9

CONFIDENTIAL

CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

5. Characteristics and Specifications

Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and

temperature. All data sheet typical parameters are measured under the following conditions: T = 25 °C,
C

= 20 pF, VDD = VDDA = 1.8 V, VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V.

L

5.1 Absolute Maximum Ratings

(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0V)

Parameter Symbol Min Max Unit

DC power supplies: Core supply

PLL supply

I/O supply

|VDDA – VDDIO|
Input pin current, any pin except supplies I
Input voltage on PLL_REF_RES V
Input voltage on I/O pins V
Storage temperature T

Caution: Operation at or beyond the se limit s may resul t in perma nent damage to the device. N ormal ope ration is

not guaranteed at these extremes.

VDD

VDDA

VDDIO

in

filt
inio
stg

-0.3

-0.3

-0.3

-

-+/-10mA

-0.3 3.6 V

-0.3 5.0 V

-65 150 °C

2.0

3.6

3.6

0.3

FT

V
V
V
V

5.2 Recommended Operating Conditions

(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0V)

Parameter Symbol Min Typ Max Unit

DC power supplies: Core supply

PLL supply

I/O supply

|VDDA – VDDIO|

Ambient operating temperature

CS48DV2B-CQZ
CS48DV2B-DQZ

VDD

VDDA

A

VDDIO

T

A

L

DRA

1.71

3.13

3.13

0

-40

1.8

3.3

3.3
0

-

1.89

3.46

3.46

+70
+85

V
V
V
V

°C

ELPHI

Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.

5.3 Digital DC Characteristics

(Measurements performed under static conditions.)

Parameter Symbol Min Typ Max Unit

High-level input voltage V
Low-level input voltage, except XTI V
Low-level input voltage, XTI V
Input Hysteresis V
High-level output voltage (I
Low-level output voltage (I
Input leakage XTI I
Input leakage current (all digital pins with internal

pull-up resist ors enabled)

CONFIDENTI

= -2mA), except XTI V

O

= 2mA), except XTI V

O

D

IH

IL

ILXTI

hys
OH

OL

LXTI

I

LEAK

2.0 - - V

--0.8V

--0.6V

0.4 V

VDDIO * 0.9 - - V

- - VDDIO * 0.1 V

--5μA

--70μA

10 Copyright 2009 Cirrus Logic DS875F2

CONFIDENTIAL

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

5.4 Power Supply Characteristics

(Measurements performed under operating conditions)

Parameter Min Typ Max Unit

Operational Power Supply Current:

VDD: Core and I/O operating
VDDA: PLL operating
VDDIO: With most ports operating

Total Operational Power Dissipation:

Standby Power Supply Current:

VDD: Core and I/O not clocked
VDDA: PLL halted
VDDIO: All connected I/O pins 3-stated by other ICs in system

Total Standby Power Dissipation:

1. Dependent on application firmware and DSP clock speed.

5.5 Thermal Data (48-Pin LQFP)

Junction Temperature
Thermal Resistance (Junction to Ambient)

Thermal Resistance (Junction to Top of Package)

1

Parameter Symbol Min Typ Max Unit

Two-layer Board

Four-layer Board

Two-layer Board

Four-layer Board

1
2

3
4

T

j

θ

ja

ψ

jt

A

-

-

-

-

-

-

-

- - 125

DRA

-

-

63.5
54

L

-

-

0.70

HI

0.64

CS48DV2B Data Sheet

203

8

27

480

100

1

50

348

-

-

-

-

-

-

-

FT

-

-

-

-

mA
mA
mA

mW

μA
μA
μA

μW

°C

°C / Watt

°C / Watt

1. Two-layer board is specified as a 76mm X 114mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20 % of the top &
bottom layers.

2. Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20 % of the top &
bottom layers and 0.5-oz. copper covering 90 % of the internal power plane & ground plane layers.

3. To calculate the die temperature for a given power dissipation

T

= Ambient T emperature + [ (Power Dissipation in Watts) * θja ]

j

4. To calculate the case temperature for a given power dissipation

T

= T

- [ (Power Dissipation in Watts) * ψjt ]

c

j

DELP

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CS48DV2B Data Sheet

A

X

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

5.6 Switching Charac teristics— RESET

Parameter Symbol Min Max Unit

RESET
All bidirectional pin s hig h- Z after
Configuration pins setup before RESET
Configuration pins hold after RESET

minimum pulse width low T

RESET low T

high T

high T

RESET

HS[3:0]

ll Bidirectional

Pins

T

rst2z

T

rstl

rstl
rst2z
rstsu

rsthld

T

rstsu

T

1-ms

-100ns
50 - ns
20 - ns

FT

rsthld

DRA

Figure 1. RESET Timing

L

5.7 Switching Characteristics — XTI

Parameter Symbol Min Max Unit

External Crystal operating frequency
XTI period T
XTI high time T
XTI low time T
External Crystal Load Capacitance (parallel resonant)
External Crystal Equivalent Series Resistance ESR 50 Ω

1

2

A

F

xtal
clki

clkih

clkil

ELPHI

C

L

11.2896 27 MHz

33.3 100 ns

13.3 - ns

13.3 - ns
10 18 pF

D

1. Part characterized with the following crystal frequency values: 11.2896, 12.288, 18.432, 24.576, & 27 MH.z

2. C

refers to the total load capacitance as specified by the crystal manufacturer. Crystals that require a CL outside this range should

L

be avoided. The crystal oscillator circuit design should follow the crystal manufacturer’s recommendation for load capacitor
selection.

TI

t

clkih

CONFIDENTI

12 Copyright 2009 Cirrus Logic DS875F2

T

clki

Figure 2. XTI Timing

CONFIDENTIAL

t

clkil

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

5.8 Switching Characteristics — Internal Clock

Parameter Symbol Min Max Unit

Internal DCLK frequency

Internal DCLK period

1. After initial power-on reset, F
the next power-on reset.

1

CS48DV2B-CQZ
CS48DV2B-DQZ

1

CS48DV2B-CQZ
CS48DV2B-DQZ

= F

dclk

. After initial kickstart commands, the PLL is locked to max F

xtal

F

dclk

DCLKP -

F
F

6.7

6.7

CS48DV2B Data Sheet

-

xtal
xtal

and remains locked until

dclk

150
150

1/F

xtal

1/F

xtal

FT

MHz

ns

DRA

L

A

HI

DELP

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CS48DV2B Data Sheet

S

S

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

5.9 Switching Charac teristics — Serial Contr ol Port - SPI Slave Mode.

Parameter Symbol Min Typical Max Units

SCP_CLK frequency
SCP_CS
SCP_CLK low time t
SCP_CLK high time t
Setup time SCP_MOSI input t
Hold time SCP_MOSI input t
SCP_CLK low to SCP_MISO output valid t
SCP_CLK falling to SCP_
SCP_CS
SCP_CLK low to SCP_CS
SCP_CS
SCP_CLK rising t o SCP_BSY

falling to SCP_CLK rising t

rising to SCP_IRQ falling t

rising to SCP_MISO output high-Z t

1. The specification f
maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY

should be implemented to prevent overflow of the input data buffer. At boot the maximum speed is F

1

IRQ rising t

rising t

falling t

indicates the maximum speed of the hardware. The system designer should be aware that the actual

spisck

f

spisck
spicss

spickl
spickh
spidsu

spidh
spidov

spiirqh

spiirql

spicsh

spicsdz

spicbsyl

-25MHz
24 - ns
20 - ns
20 - ns

5-ns
5-ns

-11ns

-20ns

0ns

24 - ns

-20 ns

-3

DCLKP+20 ns

*

DRA

xtal

FT

pin

/3.

L

A

56

t

7

spicsh

SCP_CS

SCP_CLK

t

f

spisck

spicss

t

t

spickh

spickl

0

12670

ELPHI

CP_MOSI

CP_MISO

SCP_IRQ

SCP_BSY

CONFIDENTI

A6 A5 A0 R/W MSB LSB

t

spidov

D

MSB

t

spiirqh

LSB

t

spidsu

t

spidh

t

spibsyl

t

spicsdz

t

spiirql

14 Copyright 2009 Cirrus Logic DS875F2

Figure 3. Serial Control Port - SPI Slave Mode Timing

CONFIDENTIAL

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

S

S

5.10 Switching Characteristics — Serial Control Port - SPI Master Mode

Parameter Symbol Min T ypical Max Units

SCP_CLK frequency

SCP_CS

falling to SCP_CLK rising

1

3

f

spisck

t

spicss

-F

- 11*DCLKP +
(SCP_CLK PERIOD)/2

CS48DV2B Data Sheet

2

/2

xtal

MHz

-ns

SCP_CLK low time t
SCP_CLK high time t
Setup time SCP_MISO input t
Hold time SCP_MISO input t
SCP_CLK low to SCP_MOSI output valid t
SCP_CLK low to SCP_
SCP_CLK low to SCP_CS

Bus free time between active SCP_CS t
SCP_CLK falling to SCP_MOSI output high-Z t

1. The specification f
maximum speed of the communication port may be limited by the firmware application.

2. See Section 5.7.

3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter

CS falling t

rising t

indicates the maximum speed of the hardware. The system designer should be aware that the actual

spisck

spickl
spickh
spidsu

spidh
spidov

spicsl
spicsh

spicsx

spidz

20 - ns
20 - ns

9-ns
5-ns

-8ns

7-ns

- 11*DCLKP +
(SCP_CLK PERIOD)/2

3*DCLKP - ns

-20ns

FT

DRA

L

t

spicsx

t

spicsh

EE_CS#

t

spicsl

t

spicss

A

t

0

12670

spickl

56

HI

7

-ns

SCP_CLK

f

spisck

t

spickh

DELP

CP_MISO

CP_MOSI

A6 A5 A0 R/W MSB LSB
t

spidsu

t

spidh

Figure 4. Serial Control Port - SPI Master Mode Timing

t

spidov

MSB

LSB

t

spidz

CONFIDENTI

DS875F2 Copyright 2009 Cirrus Logic 15

CONFIDENTIAL

CS48DV2B Data Sheet

S

S

ft

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

5.11 Switching Characteristics — Serial Contr o l Port - I2C Slave Mode

Parameter Symbol Min Typical Max Units

SCP_CLK frequency
SCP_CLK low time t
SCP_CLK high time t
SCP_CLK rising t o SCP_SDA rising or falling for

START or STOP condition

1

f

iicck

iicckl

iicckh

t

iicckcmd

- 400 kHz

1.25 - µs

1.25 - µs

1.25 µs

START condition to SCP_CLK falling t
SCP_CLK falling to STOP condition t
Bus free time between STOP and START conditions t
Setup time SCP_SDA input valid to SCP_CLK rising t
Hold time SCP_SDA input after SCP_CLK falling t
SCP_CLK low to SCP_SDA out valid t
SCP_CLK falling to SCP_IRQ
NAK condition to SCP_IRQ
SCP_CLK rising t o SCB_BSY

1. The specification f
maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY

should be implemented to prevent overflow of the input data buffer.

iicck

rising t

low t

low t

indicates the maximum speed of the hardware. The system designer should be aware that the actual

iicstscl

iicstp

iicbft
iicsu

iich

iicdov

iicirqh

iicirql

iicbsyl

1.25 - µs

2.5 - µs
3-µs

100 ns

20 - ns

-18ns

-3
3*DCLKP + 20 ns

-3*DCLKP + 20 ns

DRA

L

A

t

iicckl

t

iicr

t

iicf

6

CP_CLK

t

iicckcmd

01 67801 7

ELPHI

t

iicstscl

t

iicckh

t

iicdov

f

iicck

D

SCP_SDA

A6 A0 R/W ACK

MSB

LSB

FT

DCLKP + 40 ns

*

pin

t

iicckcmd

8

t

iicstp

ACK

t

iicb

t

iicirqh

t

iicsutiich

SCP_IRQ

t

CP_BSY

iiccbsyl

t

iicirql

CONFIDENTI

Figure 5. Serial Control Port - I2C Slave Mode Timing

16 Copyright 2009 Cirrus Logic DS875F2

CONFIDENTIAL

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

bf

5.12 Switching Characteristics — Serial Control Port - I2C Master Mode

Parameter Symbol Min Max Units

SCP_CLK frequency
SCP_CLK low time t
SCP_CLK high time t
SCP_SCK rising to SCP_SDA rising or falling for START or

STOP condition
START condition to SCP_CLK falling t
SCP_CLK falling to STOP condition t
Bus free time between STOP and START conditions t
Setup time SCP_SDA input valid to SCP_CLK rising t
Hold time SCP_SDA input after SCP_CLK falling t
SCP_CLK low to SCP_SDA out valid t

1. The specification f
maximum speed of the communication port may be limited by the firmware application.

1

indicates the maximum speed of the hardware. The system designer should be aware that the actual

iicck

f

iicck

iicckl

iicckh

t

iicckcmd

iicstscl

iicstp

iicbft
iicsu

iich

iicdov

-400kHz

1.25 - µs

1.25 - µs

1.25 µs

1.25 - µs

2.5 - µs
3-µs

100 ns

20 - ns

-18ns

CS48DV2B Data Sheet

FT

CP_CLK

CP_SDA

t

iicckcmd

t

iicstscl

DRA

t

iicckl

01 67801 7

t

iicckh

A6 A0 R/W ACK

t

iicsutiich

Figure 6. Serial Control Port - I2C Master Mode Timing

t

iicr

t

iicdov

t

iicf

A

MSB

L

f

iicck

6

HI

DELP

LSB

8

ACK

t

t

iicstp

iicckcmd

t

iic

CONFIDENTI

DS875F2 Copyright 2009 Cirrus Logic 17

CONFIDENTIAL

CS48DV2B Data Sheet

D

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

5.13 Switching Characteristics — Digital Audio Slave Input Port

Parameter Symbol Min Max Unit

DAI_SCLK period T
DAI_SCLK duty cycle - 45 55 %
Setup time DAI_DATAn t
Hold time DAI_DATAn t

DAI_SCLK

t

daidsu

daiclkp

daidsu

daidh

t

daidh

40 - ns

10 - ns

5-ns

AI_DATAn

Figure 7. Digital Audio Input (DAI) Port Timing Diagram

5.14 Switching Characteristics — DSD Slave Input Port

Parameter Symbol Min Typ Max Unit

DSD_SCLK Pulse Width Low t
DSD_SCLK Pulse Width High t
DSD_SCLK Frequency (64x Oversampled) - 1.024 - 3.2 MHz
DSD_A / _B valid to DSD_SCLK rising se tup tim e t
DSD_SCLK rising to DSD_A or DSD_B hold time t

L

sclkl

sclkh

A

sdlrs

sdh

DRA

78 - - ns
78 - - ns

20 - - ns
20 - - ns

FT

ELPHI

D

CONFIDENTI

Figure 8. Direct Stream Digital - Serial Audio Input Timing

18 Copyright 2009 Cirrus Logic DS875F2

CONFIDENTIAL

CS48DV2B Data Sheet

D

D

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

5.15 Switching Characteristics — Digital Audio Output Port

Parameter Symbol Min Max Unit

DAO_MCLK period T
DAO_MCLK duty cycle - 45 55 %
DAO_SCLK period for Master or Slave mode
DAO_SCLK duty cycle for Master or Slave mode

Master Mode (Output A1 Mode)

DAO_SCLK delay from DAO_MCLK rising edge,
DAO_MCLK as an input

DAO_LRCLK delay from DAO_SCLK transition, respectively
DAO_SCLK delay from DAO_LRCLK transition, respectively
DAO1_DATA[3..0], DAO2_DATA[1..0]

delay from DAO_SCLK transition

Slave Mode (Output A0 Mode)

DAO1_DATA[3..0], DAO2_DATA[1..0]
delay from DAO_SCLK transition

DAO_LRCLK delay from DAO_SCLK transition, respectively
DAO_SCLK delay from DAO_LRCLK transition, respectively

1. Master mode timing specifications are characterized, not production tested.

2. Master mode is defined as the CS48DVxx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce
DAO_SCLK, DAO_LRCLK.

3. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the
data is valid.

4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.

3

3

1

1

1,2

3
3

4

3
3

daomclk

T

daosclk

-4060%

t

daomsck

t

daomstlr

t

daomlrts

t

daomdv

t

daosdv

t

daosstlr

t

daoslrts

L

A

40 - ns

40 - ns

-19ns

-8ns

-8ns

-10ns

-15ns

-30ns

-15ns

DRA

FT

HI

t

DAO_MCLK

daomlclk

t

DAO_MCLK

daomsck

t

daomclk

t

daomsck

DELP

DAO_SCLK

t

daomdv

AOn_DATAn

t

daomlrts

DAO_LRCLK

CONFIDENTI

Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK

DS875F2 Copyright 2009 Cirrus Logic 19

CONFIDENTIAL

DAO_SCLK

AOn_DATAn

DAO_LRCLK

t

daomstlr

CS48DV2B Data Sheet

D

D

D

v

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

Figure 9. Digital Audio Output Port Timing, Master Mode

DAO_LRCLK

DAO_SCLK

AOn_DATAn

Figure 10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)

t

daosstlr

AO_LRCLK

t

daosclk

Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK

AO_SCLK

t

daoslrts

DRA

L

t

daosclk

FT

t

daosd

A

ELPHI

D

CONFIDENTI

20 Copyright 2009 Cirrus Logic DS875F2

CONFIDENTIAL

6. Ordering Infor mation

The CS48DV2B part number is described as follows:

CS48DVNI-XYZR

where

N - Product Number Variant
I - ROM ID Number
X - Product Grade
Y - Package Type
Z - Lead (Pb) Free
R - Tape and Reel Packaging

Part No. Grade Temp. Range Package

CS48DV2B-CQZ Commercial 0 to +70 °C 48-pin LQFP

CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

FT

Table 3. Ordering Information

CS48DV2B-DQZ Automotive -40 to +85 °C 48-pin LQFP

NOTE: Please contact the factory for availability of the -D (automotive grade) package.

DRA

L

A

HI

DELP

CONFIDENTI

DS875F2 Copyright 2009 Cirrus Logic 21

CONFIDENTIAL

CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

7. Environmental, Manufacturing, & Handling Information

Table 4. Environmental, Manufacturing, & Handling Information

Model Number Peak Reflow Temp MSL Rating* Max Floor Life

CS48DV2B-CQZ

CS48DV2B-CQZR

260 °C 3 7 Days

CS48DV2B-DQZ

CS48DV2B-DQZR

* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

FT

DRA

L

A

ELPHI

D

CONFIDENTI

22 Copyright 2009 Cirrus Logic DS875F2

CONFIDENTIAL

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

8. Device Pinout Diagrams

8.1 CS48DV2B, 48-pin LQFP Pinout Diagram

CS48DV2B Data Sheet

VDDIO3

GPIO8, SCP_CS

GPOI12, SCP_IRQ

GNDIO4

GPIO13, SCP_BSY , EE_CS

VDD3

XTAL_OUT GPIO15, DAI2_SCLK

GNDA

XTI

XTO

GPIO10, SCP__MISO / SDA

GPIO9, SCP_MOSI

GPIO11, SCP_CLK

35

36

37

38

39

40

41

42

GND4

33

34

GPIO7, DAO2_D ATA1, HS4

32

GPIO6, DAO2 _DATA0, HS3

31

CS48DV2B

43

44

45

46

48-Pin LQFP

GNDIO3

30

GPIO5, DAO1_DATA3, X MTA

VDD2GND2

28

29

A

GPIO3, DAO1_ DATA1, HS1

27

DRA

L

GPIO4, DAO1_ DATA2, HS2

GPIO18, DAO_MCLK

26

25

24

23

22

21

20

19

18

17

HI

16

15

VDDIO2

DAO_SCLK

FT

GND3

DAO_LRCLK

DAO1_DATA0, HS0

GNDIO2

GPIO14, DAI2_LRCLK

VDD1

GPIO17, DAI2_DATA0, DSD4

PLL_REF_RES

VDDA (3.3V)

47

48

1

2

3

4

5

TEST

RESET#

DBDA

GND1

DBCK

DELP

6

7

GNDIO1

DAI1_LRCLK, DAI1_DATA4, DSD5

9

8

DAI1_SCLK, DSD-CLK

10

GPIO16, DAI1_DATA0, TM0, DSD0

11

GPIO0, DAI1_DATA1, TM1, DSD1

14

GPIO2, DAI1_DATA3, TM3, DSD3

GPIO1, DAI1_DATA2, TM2, DSD2

13

12

VDDIO1

CONFIDENTI

Figure 11. CS48DV2B 48-Pin LQFP Pinout Diagram

DS875F2 Copyright 2009 Cirrus Logic 23

CONFIDENTIAL

CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

8.2 48-pin LQFP Package Drawing

48LDLQFP(7x7x1.4mmbody)

FT

DRA

L

A

Number of Leads

MIN NOM MAX

A1.60
A1 0.05 0.15
A2 1.35 1.40 1.45

b 0.17 0.22 0.27

D9.00BSC
D1 7.00 BSC

e0.50BSC

E9.00BSC
E1 7.00 BSC

theta 0 7

L 0.45 0.60 0.75

L1 1.00 REF

NOTES:

1) Reference document: JEDEC MS-026

2) All dimensions are in millimeters and controlling dimension is in millimeters.

3) D1 and E1 do not include mold flash which is 0.25 mm max. per side.A1

CONFIDENTI

4) Dimension b does not include a total allowable dambar protrusion of 0.08 mm max.

48

ELPHI

D

Figure 12. 48-Pin LQFP Package Drawing

24 Copyright 2009 Cirrus Logic DS875F2

CONFIDENTIAL

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

9. Revision History

Revision Date Changes

F1 December 3, 2008 Initial Release of CS48DV2B Data Sheet
F2 February 16, 2009 Updated Section 5.5, adding Junction Temperature specification.

CS48DV2B Data Sheet

FT

DRA

L

A

HI

DELP

CONFIDENTI

DS875F2 Copyright 2009 Cirrus Logic 25

CONFIDENTIAL

CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

FT

DRA

L

A

ELPHI

D

CONFIDENTI

26 Copyright 2009 Cirrus Logic DS875F2

CONFIDENTIAL