Cirrus Logic CS48DV2B User Manual

CS48DV2B Data Sheet

FEATURES

 World’s most cost-effective 32-bit DSP featuring Dolby

Volum e and Audistry

— Supports native processing at input Fs up to 48kHz — Single download image enables su pport for 32 KHz,

44.1 kHz, and 48 kHz audio input

 CS48DV2B supports up to 2.0 channels of audio input

and up to 2.1 channels of output

 Enables concurrent processing features beyond Dolby

Volum e including Tone Control, Multiba nd Parametric EQ, Bass Management, Delays.

 Configurable Serial Audio Inputs/Outputs

— Configurable for all input/output digital audio types

S/LJ/RJ)

— 32-bit data path delivers uncompromised dynamic

range — 192 kHz capable integra ted S/PDIF trans mitte r — DAO can operate in master o r slave mod e (SCLK &

LRCLK)

 Integrated Clock Manager/PLL

— Capable of operating from a wide va riety of external

crystals or external oscillators

 Slave Host Boot Capability via Serial Interface

— SPI

 1.8V Core and 3.3V I/O that is tolerant to 5V input  Low-power Mode enabled

—Energy Star® Design Compli ance Capability via low-

™

interface capable of running up to 25 MHz

during run time

power mode, 268 µW in Standby mode

by Dolby

The new CS48DV2B supports a host of signal processing applications concurre ntly, including the mass production -ready

Dolby Volume solution. See Section 3. for details about firmware concurrency on the CS48DV2B. The target applications for the CS48DV2B DSP are:

— Digital Televisions — Soundbars / DTVs with Integrated Soundbars

—PMD/iPod — Automotive Head Units — Automotive Outboard Amplifiers

— Blu-ray Disc — PC Speakers

All of these applications and many more that use volume control and are subject to playback from sources that do not have consistent volume le vels w ill bene fit from the CS48D V2B Dolby Volume solution.

Docking Stations

& DVD Receivers / HTiBs

DRA

Ordering Information:

See page 21 for ordering informat ion.

2.0 Ch.

Audio In

S/PDIF

Up to 2.1 Ch

Audio Out

Serial

Control 1

32-bit

DSP

P X Y

DELPHI

D M A

GPIO Debug

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Watchdog

TMR1 TMR2

PLL

CS48DV2B Data Sheet

d e

, s d

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

DRA

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject t change without notice and is provided “A S IS” witho ut warranty of any kind (express or implied). Customers are advised to obtai n t he lat est versi on of rel evant i nf o mation to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplie at the time of ord er a cknowl edgment, including those pertaining to warranty, i n demn if ica t i on, and limitation of l i ability. No responsibility is assumed by Cirrus for th use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copie to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not exten to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOL VE POTENTIAL RISKS OF DEATH, PERS ONAL INJURY, OR SEVERE PRO PER TY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIO NS” ). CIRRUS PRO D UCT S ARE NO T DES IGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO T HE BODY, AUTOMO TIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICA APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRU DISCLAIMS AND MAKES NO WARRAN TY, EXPRE SS, STAT UTORY OR IMPLIED, INCLUDING THE IMPLIED WARRAN TIES OF MERCHAN TABILITY AND FIT NESS FOR PARTICULAR PUR POSE, WITH REGARD TO ANY CIRRUS PRODUCT T HAT IS US ED IN SUCH A MANNER . IF THE C USTOMER OR CUSTOME R' CUSTOMER USES OR PERMITS TH E USE O F C IRRUS PRO D UCTS IN CRITICAL APPLICATIONS, CUSTOMER AGR EES, BY SUCH USE, TO FULLY INDEM NIFY CIRRUS, ITS OFFICERS, DIRECTORS, EM PLOYEES, DISTRIBU TORS AND OT HER AGENT S FROM ANY AN D ALL LIABILITY, INCLUD ING ATTORNEYS FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, the Cirrus Logic l ogo desi gn s, DSP Composer is a tradem arks of Cir r us Logic, Inc. All other brand and product names in this document may b trademarks or service marks of their respective owners.

Dolby, Audistry, and the sound shell logo are registered trademarks of Dolby Laboratories. Supply of an implementation of Dolby Technology does not convey a licens nor imply a right u nder any patent, or any o ther industrial or In tel l ectual Property Right of Dol by Laboratories, to use the I mp le mentation in any finished end-user o ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories.

SPI is a trademark of Motorola, Inc.

C is a registered trademark of Philips Semiconductor. iPod is a registered trademark of Apple Computer, Inc. Blu-ray Disc is a registered trademark of SONY KABUSHIKI KAISHA CORPORATION. Energy Star is a registered trademark of the Environmental Protection Agency, a federal agency of the United States government.

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CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

Table of Contents

1. Documentation Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.1 Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3. Code Overlays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

4. Hardware Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

4.1 DSP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.1.1 DSP Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.1.2 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.2 On-chip DSP Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.1 Digital Audio Input Port (DAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.2 Digital Audio Output Port (DAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.3 Serial Control Port (I

4.2.4 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.5 PLL-based Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.6 Hardware Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.3 DSP I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.3.1 Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.3.2 Termination Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.3.3 Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.4 Application Code Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5. Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.3 Digital DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.4 Power Supply Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5.5 Thermal Data (48-Pin LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5.6 Switching Characteristics— RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.7 Switching Characteristics — XTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.8 Switching Characteristics — Internal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.10 Switching Characteristics — Serial Control Port - SPI Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.11 Switching Characteristics — Serial Control Port - I

5.12 Switching Characteristics — Serial Control Port - I

5.13 Switching Characteristics — Digital Audio Slave Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.14 Switching Characteristics — DSD Slave Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.15 Switching Characteristics — Digital Audio Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

7. Environmental, Manufac turi ng, & Handli ng Infor mation . . . . . . . . . . . . . . . . . . . . . . . . . .22

8. Device Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

8.1 CS48DV2B, 48-pin LQFP Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.2 48-pin LQFP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

2C®

or SPI™) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

DRA

C Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

C Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 17

DELP

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CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

List of Figures

Figure 1. RESET Timing ......................................................................................................................................... 12

Figure 2. XTI Timing ............................................................................................................................................... 12

Figure 3. Serial Control Port - SPI Slave Mode Timing...........................................................................................14

Figure 4. Serial Control Port - SPI Master Mode Timing.........................................................................................15

Figure 5. Serial Control Port - I Figure 6. Serial Control Port - I

Figure 7. Digital Audio Input (DAI) Port Timing Diagram ........................................................................................18

Figure 8. Direct Stream Digital - Serial Audio Input Timing..................................................................................... 18

Figure 9. Digital Audio Output Port Timing, Master Mode.......................................................................................20

Figure 10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)............................................ 20

Figure 11. CS48DV2B 48-Pin LQFP Pinout Diagram............................................................................................. 23

Figure 12. 48-Pin LQFP Package Drawing............................................................................................................. 24

C Slave Mode Timing ........................................................................................... 16

C Master Mode Timing ......................................................................................... 17

List of Tables

Table 1. CS48DV2B DSP Related Documentation................................................................................................5

Table 2. Device and Firmware Selection Guide.....................................................................................................7

Table 3. Ordering Information..............................................................................................................................21

Table 4. Environmental, Manufacturing, & Handling Information.........................................................................22

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CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

1. Documentation Strategy

The CS48DV2B Data Sheet describes CS48DV2B multichannel audio processors. This document should be used in conjunction with the following documents when evaluating or designing a system around the CS48DV2B processors.

Table 1. CS48DV2B DSP Related Documentation

Document Name Description

CS48DV2B Data Sheet This document

Includes detai led system des ign information inc luding

CS485xx Family Hardware User’s Manual

AN298 - CS485xx Family Firmware User’s Manual

Typical Connection Diagrams, Boot-Procedures, Pin Descriptions, etc.

Includes detailed firmware design information including signal processing flow diagram s and cont rol API information

DSP Composer User’s Manual

AN298VPMA,Audistry

AN298PPMN, Dolby® Volume Firmware User’s

Manual for the CS48DV2x Family

The scope of the CS48DV2B Data Sheet is primarily the hardware specifications of the CS48DV2B devices. This includes hardware functionality, characteristic data, pinout, and packaging information.

The intended audience for the CS48DV2B Data Sheet is the system PCB designer, MCU programmer, and the quality control engineer.

2. Overview

The CS48DV2B DSP is designed to provide high-performance post-processing and mixing of digital audio. The dual clock domain provided on the PCM inputs all ows for the mixi ng of audio streams wit h different sampling frequencies. The low-power standby preserves battery life for applications which are always on, but not necessarily processing audio, such as automotive audio systems.

The CS48DV2B supports dual input clock domains and dual audio processing paths. The CS48DV2B is available in a 48-pin QFP package. Please refer to Table 2 on page 7 for the input, output, firmware features of each device.

by Dolby

®”

Includes detailed configuration and usage information for the GUI development tool.

Describes API used to control the Audistry firmware module.

Describes API used to control the Dolby Volume firmware module.

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2.1 Licensing

Licenses are required for all of the 3rd party audio processing algorithms listed in Section 3. Please contact your local Cirrus Logic Sales representative for more informat ion.

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CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

3. Code Overlays

The suite of software available for the CS48DV2B DSP consists of an operating system (OS) and a library of overlays. The overlays have been divided into three main groups called Matrix-processors, Virtualizer-processors, and Post-processors. All sof tware components are defined below:

1. OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external memory, processing host messages, calling audio-processing subroutines, error concealment, etc.

2. Matrix-processor- Any Module that performs a matrix decode on PCM data to produce more

output channels than input channels (2Ön channels). Examples are Dolby DTS Neo:6

audio I/O buffer.

3. Virtualizer-processor - Any module that encodes PCM data into fewer output channels than input channels (nÖ2 channels) with the effect of providing “phantom” speakers to represent the

physical audio channels that were eliminated. Examples are Dolby Headphone Virtual S peaker

audio I/O buffer.

™

. Generally speaking, these modules increase the number of valid channels in the

. Generally speaking, these modules reduce the number of valid channel s in the

Pro Logic® IIx and

and Dolby®

4. Post-processors - Any module that processes audio I/O buffer PCM data in-place after the matrix- or virtualizer-processors. Examples are the Dolby Volume and Audistry by Dolby firmware, bass management, audio manager, tone control, EQ, delay, and customer- specific effects

The bulk of each overlay is stored in ROM within the CS48DV2B, but a small image is required to

configure the overlays and boot the DSP. This small image can either be stored in an external serial FLASH/EEPROM, or downloaded via a host controller through the

The overlay structure reduces the t ime required t o reconfigu re the DSP when a process ing change is requested. Each overlay can be reloaded independently without disturbing the other overlays. For example, when a new matrix-processor is selected, the OS, virtualizer-, and post-processors do not need to be reloaded — only the new matrix-processor. This fact is also true for the other overlays.

Table 2 lists the firmware available based on device selection. Please refer to AN298, CS485xx

Firmware User’s Manual for the latest listing of application codes and Cirrus Framework available.

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SPI™/I2C

serial port.

™ modules

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CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

Table 2. Device and Firmware Selection Guide

Devices Availability Suggested Applications Specific Features

• Digital TV Portable Audio Docking Station

• Portable DVD

CS48DV2B-CQZ

In Production Now

CS48DV2B-DQZ

4. Hardware Functional Description

4.1 DSP Core

The CS48DV2B DSPs are single-core DSP with separate X and Y data and P code memory spaces . The DSP core is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two multiply-and-accumulate (MAC) operations per clock cycle. The DSP core has eight 72-bit accumulators, four X- and four Y-data registers, and 12 index registers.

The DSP core is coupled to a flexible DMA engine. The DMA engine can move data between peripherals such as the serial control port (SCP), digital audio input (DAI) and digital audio output (DAO), or any DSP core memory, all without the intervention of the DSP. The DMA engine off loads data move instructions from the DSP core, leaving more MIPS available for signal processing instructions.

Players

• Multimedia PC Speakers

• Soundbars

• Automotive Entertainment Systems

DRA

• 2.1 channels of audio input and 2.1 channels of PCM audio output.

• 512 FFT Window, 20Bands/Channel

• Dolby Volume Native Processing of the following Fs:

— 32 kHz — 44.1 kHz

— 48 kHz

CS48DV2B functionality is controlled by application codes that are stored in on-board ROM or

downloaded to the CS48DV2B from a host controller or external serial FLASH/EEPROM.

Users can develop their applications using DSP Composer to create the processing chain and then compile the image into a series of commands that are sent to the CS48DV2B through the SCP. The processing application can either load modules (matrix-processors, virtualizers, post-processors) from the DSPs on-board ROM, or custom firmware can be downloaded through the SCP.

The CS48DV2B is suitable for a variety of audio post-processing applications such as automotive head-ends, automotive amplifiers, and boom boxes.

4.1.1 DSP Memory

The DSP core has its own on-chip data and program RAM and ROM and does not require external memory for post-processing applications.

The Y-RAM and P-RAM share a single block of memory that can be configured to make Y and P equal in size, or more memory can be allocated for Y-RAM in 2kword blocks.

4.1.2 DMA Controller

The powerful 8-channel DMA controller can move data between 8 on-chip resources. Each resource has its own arbiter: X, Y, and P RAMs/ROMs and the peripheral bus. Modulo and linear addressing

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CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

modes are supported, with flexible start address and increment controls. The service intervals for each DMA channel, as well as up to 6 interrupt events, are programmable.

4.2 On-chip DSP Peripherals

4.2.1 Digital Audio Input Port (DAI)

The DAI port supports a wide variety of data input formats at sample rates (Fs) as high as 192 kHz. The port is capable of accepting PCM or DSD formats. Up to 32-bi t word l engths are supported. DSD is supported and internally converted to PCM before processing. The DAI also supports a time division multiplexed (TDM) one-line data mode that packs multiple chann els of PCM audio input on a single data line. The total number of channels that are possible depends on the ratio of SCLK to LRCLK.

The port has two independent slave-only clock domains. Each data input can be independently assigned to a clock domain. The sample rate of the input clock domains can be determined automatically by the DSP, off-loading the task of monitoring the S/PDIF receiver from the host. A time-stamping feature allows the i nput data to be sample-rate converted via softwar e.

4.2.2 Digital Audio Output Port (DAO)

DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high as 192 kHz. The port can be configured as an independent clock domain mastered by the DSP, or as a clock slave if an external MCLK or SCLK/LRCLK source is available. One of the serial audio pins can be re-configured as a S/PDIF transmitter that drives a bi-phase encoded S/PDIF signal (data with embedded clock on a single line).

DRA

The DAO also supports a time division multiplexed (TDM) one-line data mode, that packs multiple channels of PCM audio on a single data line.

2C®

4.2.3 Serial Control Port (I

The on-chip serial control port is capable of operating as master or slave in either modes. Master/Slave operation is chosen by mode select pins when the CS48DV2B comes out of Reset. The serial clock pin can support frequencies as high as 25 MHz in SPI mode ( SPI clock speed must always be ≤ (F

the communications interface (SCP_BSY host (SCP_IRQ

dclk

or SPI™)

/2)). The CS48DV2B serial control port also includes a pin for flow control of

) and a pin to indicate when the DSP has a message for the

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4.2.4 GPIO

Many of the CS48DV2B peripheral pins are multiple xed with GPIO. Each GPIO can be configur ed as an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low, or active-high.

4.2.5 PLL-based Clock Generator

The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the DAO port for driving audio converters. The CS48DV2B defaults to running from the external reference frequency and is switched to use the PLL output after overlays have been loaded and configured, either through master boot from an external FLASH or through host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1.

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