Cirrus Logic CS485xx User Manual

CS485xx Family Data Sheet

32-bit

DSP

D M A

P X Y

Serial

Control 1

12 Ch PCM

Audio Out

GPIO Debug

Watchdog

TMR1 TMR2

PLL

S/PDIF

12 Ch. Audio In /

6 Ch. SACD In

CS485xx

Features

 Cost-effective, High-performance 32-bit DSP

 300,000,000 MAC/S (multiply accumulates per second)  Dual MAC cycles per clock  72-bit accumulators are the most accurate in the industry  24k x 32 SRAM, 2k blocks - assignable to data or program  Internal ROM contains a variety of configurable sound

enhancement feature sets

 8-channel internal DMA  Internal watch-dog DSP lock-up prevention

 DSP Tool Set w/ Private Keys for Protecting Customer IP  Configurable Serial Audio Inputs/Output s

 Configurable for all input/output types  Maximum 32-bit @ 192 kHz  Supports 32-bit audio sample I/O between DSP chips  TDM input modes (multiple channels on same line)  192 kHz SPDIF transmitter  Multi-channel DSD direct stream digital SACD input

 Supports Two Different Input Fs Sample Rates

 Output can be master or slave  Dual processing path capability  Input supports dual domain slave clocking  Hardware assist time sampling for sample rate conversion

 Integrated Clock Manager/PLL

 Can operate from external crystal, external oscillator

 Input Fs Auto Detection  Host & Boot via Serial Interface  Configurable GPIOs and External Interrupt Input  1.8V Core and a 3.3V I/O that is tolerant to 5V input

Differentiating from the legacy Cirrus multi-standard, multi-channel decoders, this new CS485xx family is still based on the same high-performance 32-bit fixed point Digital Si gnal Processor core but instead is equipped with much less memory, t ai lo ring it f or more cost-effective applications associat ed with multi-channel and virtual-channel sound enhancements. Target applications are:

 Digital Televisions  Multimedia Peripherals

 iPod

Docking Stations

 Automotive Head Units  Automotive Outboard Amplifiers  HD-DVD

™

and Blu-ray Disc® DVD Receivers

 PC Speakers

There are also a wide variety of licensable DSP codes available today as seen by the following examples:

Cirrus also has developed, or is developing their own royalty-free versions of popular features sets like Cirrus Bass Manager, Cirrus Dynamic Volume Leveler, Cirrus Original Multichannel Surround, Cirrus Virtual Speaker & Cirrus 3D-Audio.

The CS485xx family is programmed using the Cirrus proprietary DSP Composer designed using a drag-and-drop interface to place/utilize functional macro audio DSP primitives. The end result is a software image that is down-loaded to the DSP via serial host or serial boot modes.

See Section 6 for ordering information.

™

GUI development tool. Processing chains may be

 Low-power Mode

 “Energy Star

http://www.cirrus.com

Ready” in low-power mode, 268 µW in standby

CS485xx Block Diagram

DS734F5

OCT '11

Contacting Cirrus Logic Support

For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com.

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is pr ov i de d “A S I S” wi t hou t war r an ty of a ny k i nd ( ex p res s o r impl i ed ). Cus to mer s ar e adv ise d to obtain the lat est version of relevant information to verify, before placing orders, that informatio n being relied on is current and complet e. All products are s old subject to the terms and conditions of s al e suppl i ed at the ti me of or de r acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this in formation, including use of this information as the b asis fo r manufacture or sale of any items, or for infring ement of patents or other rights of third parties. This document is the property of Cirrus and by furnishi ng thi s i nformation, Cirrus grant s n o license, express or implied under any patents, mask work rights, copyrights, trademarks, t r a de se cre t s o r o t her intellectual proper ty rig hts. Cirr us owns t he co pyri ght s ass ociat ed with the i nf ormati on c onta ine d here in a nd giv es c onse nt f or copies to be made of the information only for use within your organiz ation with respect to Cirrus integrated circuits or other products of Cirrus. Th is consent does not ext end to other copying such as copying for general distribution, advertising or promotional pu rp oses, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PR ODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATI ONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PER MITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATION S, CUSTOMER AGRE ES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, DSP Com poser, and Cirru s Framework ar e tradema rks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

Dolby, Dolby Digitaol, Dolby Headphone, Virtual Speaker, and Pro Logic are registered trademarks of Dolby Laboratories, Inc. Supply of an implementation of Dolby Technology does not convey a license no r imply a right under any pate nt, or any other industrial or Intelle ctual Property Right of Dolby Laboratories, to use the Implementation in any finished end-user or ready-to-use final pro d uct. It is hereby no tified that a li cen s e for such u se is required from Dolby Laboratories.

DTS and DTS Neo:6 are regist ered trademarks of Dig i tal Theater Systems, Inc. It is hereby notified that a third-party license from DTS is necessary to distribute software of DTS in any finished end-user or ready-to-use final pro du ct.

SRS, Circle Surround and Trusurround XT are registered trademarks of SRS Labs, Inc. Circl e Surround II is a trademark of SRS Labs, Inc. The Circle Surround technology is incorporated under li cense from SRS Labs, Inc. The Circle Surround tec hnology rights incor porated in the CS485xx are owned by SRS Labs, a U.S. Cor poration and licensed to Cirrus Logic, Inc. Purchaser of CS485xx must sign a license for use of the chip and display of the SRS Labs trademarks. Any products incorporating the CS485xx must be sent to SRS Labs for review. The Circle Surround technology is protected under US and foreign patents issued and/or pending. Circle Surround, SRS and (O) symbol are trademarks of SRS Labs, Inc. in the United States and selected foreign countrie s. Neither the purchase of the CS485xx, nor the corresponding sale of audio enhancement equipment conveys the r ight to sell commerci alized recordings made wi th any SRS technology/sol ution. SRS Labs requires all set makers to comply with all rules and regulations as outlined in the SRS Trademar k U sag e M a nual.

SPI is a trademark of Motorola, Inc. I²C is a trademark of Philips Semiconductor. iPod is a registered trademark of Apple Comput er, Inc. HD DVD is a trademark of DVD Format/Logo Licensin g Corporation. Blu-Ray Disc is a registered trademark of SONY KABUSHIKI KAISHA CORPORATION. Energy Star is a registered trademark of the Environmental Protection Agency, a federal agency of the United States government.

DS734F5 2

TABLE OF CONTENTS

1 Documentation Strategy ........................................................................................................................................... 1-5

2 Overview ..................................................................................................................................................................... 2-5

2.1 Licensing ............................................................................................................................................................ 2-5

3 Code Overlays ............................................................................................................................................................ 3-6

4 Hardware Functional Description ............................................................................................................................ 4-7

4.1 DSP Core ........................................................................................................................................................... 4-7

4.1.1 DSP Memory ............................................................................................................................................. 4-7

4.1.2 DMA Controller .......................................................................................................................................... 4-7

4.2 On-chip DSP Peripherals ................................................................................................................................... 4-7

4.2.1 Digital Audio Input Port (DAI) ............. ... ... ... ... .......................................... .... ............................................. 4-7

4.2.2 Digital Audio Output Port (DAO) ................................................................................................................ 4-8

4.2.3 Serial Control Port (I

4.2.4 GPIO ......................................................................................................................................................... 4-8

4.2.5 PLL-based Clock Generator ...................................................................................................................... 4-8

4.2.6 Hardware Watchdog Timer ....................................................................................................................... 4-8

4.3 DSP I/O Description ........................................................................................................................................... 4-8

4.3.1 Multiplexed Pins ........................................................................................................................................4-8

4.3.2 Termination Requirements ........................................................................................................................ 4-8

4.3.3 Pads .......................................................................................................................................................... 4-9

4.4 Application Code Security .................................................................................................................................. 4-9

5 Characteristics and Specifications .......................................................................................................................... 5-9

5.1 Absolute Maximum Ratings ................................................................................................................................ 5-9

5.2 Recommended Operations Conditions ..................................... ............. ............ ............. ............. .......................5-9

5.3 Digital DC Characteristics ................................................................................................................................... 5-9

5.4 Power Supply Characteristics ......................... ................ ................ ................ ................ .................................. 5-10

5.5 Thermal Data (48-pin LQFP) ............................................................................................................................ 5-10

5.6 Switching Characteristics—RESET .................................................................................................................. 5-11

5.7 Switching Characteristics—XTI ........................................................................................................................ 5-11

5.8 Switching Characteristics—Internal Clock ........................................................................................................5-11

5.9 Switching Characteristics—Serial Control Port–SPI Slave Mode ..................................................................... 5-12

5.10 Switching Characteristics—Serial Control Port–SPI Master Mode ................................................................. 5-13

5.11 Switching Characteristics—Serial Control Port–I

5.12 Switching Characteristics—Serial Control Port–I

5.13 Switching Characteristics—Digital Audio Slave Input Port .................................. ... ........................................ 5-15

5.14 Switching Characteristics—DSD Slave Input Port ..... ... .......................................... ........................................ 5-15

5.15 Switching Characteristics—Digital Audio Output (DAO) Port ....................... ... .... ... ........................................ 5-16

6 Ordering Information ............................................................................................................................................... 6-18

7 Environmental, Manufacturing, and Handling Information .................................................................................7-18

8 Device Pinout Diagrams .......................................................................................................................................... 8-19

8.1 CS48520, 48-pin LQFP Pinout Diagram .......................................................................................................... 8-19

8.2 CS48540, 48-pin LQFP Pinout Diagram .......................................................................................................... 8-20

8.3 CS48560, 48-pin LQFP Pinout Diagram .......................................................................................................... 8-21

9 Package Mechanical Drawings ............................................................................................................................... 9-22

9.1 48-pin LQFP Package Drawing ........................................................................................................................ 9-22

10 Revision History .............................. .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ................................................................... 10-23

2C™

or SPI™) ..................................... ............. ............. ............. ............ ............. ....... 4-8

C Slave Mode ................................................................... 5-13

C Master Mode ................................................................. 5-14

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LIST OF FIGURES

Figure 5-1. RESET Timing ...................................................................................................................................... 5-11

Figure 5-2. XTI Timing............................................................................................................................................. 5-11

Figure 5-3. Serial Control Port–SPI Slave Mode Timing .........................................................................................5-12

Figure 5-4. Serial Control Port–SPI Master Mode Timing .......................................................................................5-13

Figure 5-5. Serial Control Port–I Figure 5-6. Serial Control Port–I

Figure 5-7. Digital Audio Input (DAI) Port Timing Diagram....... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .................................. 5-15

Figure 5-8. Direct Stream Digital–Serial Audio Input Timing........................................ ... ... ... .... ... ... ... ... .................. 5-15

Figure 5-9. Digital Audio Output Port Timing, Master Mode.................................................................................... 5-17

Figure 5-10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)......................................... 5-17

Figure 8-1. CS48520, 48-pin LQFP Pinout.............................................................................................................. 8-19

Figure 8-2. CS48540, 48-pin LQFP Pinout.............................................................................................................. 8-20

Figure 8-3. CS48560, 48-pin LQFP......................................................................................................................... 8-21

Figure 9-1. 48-pin LQFP Package Drawing............................................................................................................. 8-22

C Slave Mode Timing.......................................................................................... 5-14

C Master Mode Timing........................................................................................ 5-15

LIST OF TABLES

Table 1-1. CS485xx Family Related Documentation....................................... ... ... ... .... ... .......................................... 1-5

Table 3-1. Device and Firmware Selection Guide................................. ... .... ... .......................................................... 3-6

Table 5-1. Master Mode (Output A1 Mode)............................................................................................................. 5-16

Table 5-2. Slave Mode (Output A0 Mode)............................................................................................................... 5-17

Table 6-1. Ordering Information .............................................................................................................................. 6-18

Table 7-1. Environmental, Manufacturing, and Handling Information .....................................................................7-18

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1 Documentation Strategy

The CS485xx Family Data Sheet describes the CS485xx family of multichannel audio proce ssors. This document should be used in conjunction with the following documents when evaluating or designing a system around the CS485xx family of processors.

Table 1-1. CS485xx Family Related Documentation

Document Name Description

CS485xx Family Data Sheet This document

CS485xx Family Hardware User’s Manual Includes detailed system design information including Typical Connection Diagrams,

AN298–CS485xx Family Firmware User’s Manual Includes detailed firmware design information including signal processing flow

DSP Composer User’s Manual Includes detailed configuration and usage information for the GUI development tool.

The scope of the CS485xx Family Data Sheet is primarily the hardware specifications of the CS485xx family of devices. This includes hardware functionality, characteristic data, pinout, and packaging information.

The intended audience for the CS485xx Family Data Sheet is the system PCB designer, MCU programmer, and the quality control engineer.

Boot-Procedures, Pin Descriptions, etc.

diagrams and control API information

2 Overview

The CS485xx DSP Family is designed to provide high-performance post-processing and mixing of digital audio. The dual clock domain provided on the PCM inputs allows for the mixing of audio streams with different sampling frequencies. The low-power standby preserves battery life for applications which are always on, but not necessarily processing audio, such as automotive audio systems.

There are three devices comprising the CS485xx family. The CS48520, CS485 40 and CS48560 are differentiated by the number of inputs and outputs available. All DSPs support dual input clock domains and dual audio processing paths. All DSPs are available in a 48-pin QFP package. Refer to Table3-1 for the input, output, firmware features of each device.

2.1 Licensing

Licenses are required for all of the third party audio processing algorithms listed in Section 3. Contact your local Cirrus Logic Sales representative for more information.

5 DS734F5

3 Code Overlays

The suite of software available for the CS485xx family consists o f an operating system (OS) and a librar y of overlays. The overlays have been divided into three main groups called Matrix-processors, Virtualizer-processors, and Post-processors. All software components are defined below:

1. OS/Kernel—Encompasses all non-audio processing tasks, including loading data from external memory, processing host messages, calling audio-processing subroutines, error concealment, etc.

2. Matrix-processor—Any Module that performs a matrix decode on PCM data to produce more output channels than input channels (2n channels). Examples are Dolby ProLogic IIx and DTS Neo :6. Ge nerally speaking , these modules increase the number of valid channe ls in the au dio I/O bu ffer.

3. Virtualizer-processor—Any module that encodes PCM data into fewer output channels than inpu t channels (n2 channels) with the effect of providing “phantom” speakers to represent the physical audio channels that were eliminated. Examples are Dolby Headphone reduce the number of valid channels in the audio I/O buffer.

4. Post-processors—Any module that processes audio I/O buffer PCM data in-place after the matrix- or virtualizer-processors. Examples are bass management, audio manager, tone control, EQ, delay, customer-specific effects, etc.

The bulk of each overlay is stored in ROM within the CS485xx, but a small imag e is required to configure the overlays and boot the DSP. This small image can either be stored in an external serial FLASH/EEPROM, or downloaded via a host controller through the SPI

™

/I2C™ serial port.

and Dolby Virtual Speaker®. Generally speaking, these modules

The overlay structure reduces the time required to reconfigure the DSP when a processing change is requested. Each overlay can be reloaded independently without disturbing the other overlays. Fo r example, when a new matrix-processor is selected, the OS, virtualizer-, and post-processors do not need to be reloaded — only the new matrix-processor (the same is true for the other overlays).

Table 3-1 lists the firmware available based on device selection. Refer AN298, CS485xx Firmware User’s

Manual for the latest listing of application codes and Cirrus Framework

Table 3-1. Device and Firmware Selection Guide

Device Suggested Application Channel Count Input/Output Package

CS48520-CQZ Digital TV, portable audio docking station, portable DVD, DVD mini/

CS48540-CQZ CS48540-DQZ CS48560-CQZ CS48560-DQZ

receiver, multimedia PC speakers CS48520 features plus 8-channel car audio, DVD receiver Up to 8-channel in/8-channel out 48-pin QFP

CS48540 features plus 12-channel car audio, high-end digi tal TV , dual source/dual zone SACD

™ modules available.

Up to 4-channel in/4-channel out 48-pin QFP

Up to 12-channel in/12-channel out 48-pin QFP

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4 Hardware Functional Description

4.1 DSP Core

The CS485xx family DSPs are single-core DSP with separate X and Y data and P code memory spaces. The DSP core is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two multiply-and-accumulate (MAC) operations per clock cycle. The DSP core has eight 72-bit accumulators, four X- and four Y-data registers, and 12 index registers.

The DSP core is coupled to a flexible DMA engine. The DMA engine can move data between peripherals such as the serial control port (SCP), digital audio input (DAI) and digital audio output (DAO), or any DSP core memory, all without the intervention of the DSP. The DMA engine off loads data move instructions from the DSP core, leaving more MIPS available for signal processing instructions.

CS485xx family functionality is controlled by application codes that are stored in on-board ROM or downloaded to the CS485xx from a host controller or external serial FLASH/EEPROM.

Users can develop their applications using DSP Composer to crea te the processing chain and then compile the image into a series of commands that are sent to the CS485xx through the SCP. The processing application can either load modules (matrix-processors, virtualizers, post-processors) from the DSPs on-board ROM, or custom firmware can be downloaded through the SCP.

The CS485xx is suitable for a variety of audio post-processing applications such as automotive hea d-ends, automotive amplifiers, and boom boxes.

4.1.1 DSP Memory

The DSP core has its own on-chip data and program RAM and ROM and does not require external memory for post-processing applications.

The Y-RAM and P-RAM share a single block of memory that can be configured to make Y and P equal in size, or more memory can be allocated for Y-RAM in 2kword blocks.

4.1.2 DMA Controller

The powerful 8-channel DMA controller can move data between 8 on-chip resources. Each resource has its own arbiter: X, Y, and P RAMs/ROMs and the peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and increment controls. The service intervals for each DMA channel, as well as up to 6 interrupt events, are programmable.

4.2 On-chip DSP Peripherals

4.2.1 Digital Audio Input Port (DAI)

Each version of the CS485xx supports a different number of input channels. Refer to Table 3-1 for more details. The DAI port supports a wide variety of data input formats at sa mple rates (Fs) as hig h as 192 kHz. The por t is capable of

accepting PCM or DSD formats. Up to 32-bit word lengths are supported. DSD is supported and internally converted to PCM before processing. The DAI also supports a time division multiplexed (TDM) one-line data mode, that packs PCM audio on a single data line (the total number possible depe nds on the ratio of SCLK to LRCLK and the ver sion of chip. For example on the CS48520 only 4 ch of PCM are supported in one line mode and on the CS48560 up to 8 channels are supported.).

The port has two independent slave-only clock domains. Each data input can be independently assigned to a clock domain. The sample rate of the input clock domains can be determined au tomatically by the DSP, off- loading the task of monitoring the SPDIF receiver from the host. A time-stamping feature allows the input data to be sample-rate converted via software.

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