Cirrus Logic CS4384 User Manual

Download

CS4384

103 dB, 192 kHz 8-Channel D/A Converter

Features

 Advanced Multi-bit Delta Sigma Architecture  24-bit Conversion  Automatic Detection of Sample Rates up to

192 kHz

 103 dB Dynamic Range  -88 dB THD+N  Single-Ended Output Architecture  Direct Stream Digital

(DSD

– Non-Decimating Volume Control – On-Chip 50 kHz Filter – Matched PCM and DSD Analog Ou tput

Levels

 Compatible with Industry-Standard Time

Division Multiplexed (TDM) Serial Interface

 Selectable Digital Filters  Volume Control with 1/2-dB Step Size and Soft

Ramp

 Low Clock-Jitter Sensitivity  +5 V Analog Supply, +2.5 V Digital Supply  Separate 1.8 to 5 V Logic Supplies for the

Control and Serial Ports

™)

Mode

Description

The CS4384 is a complete 8-channel digital-to-analog system. This D/A system includes digital de-emphasis, half-dB step size volume control, ATAPI channel mixing, selectable fast and slow digital interpolation filters followed by an oversampled, multi-bit delta sigma modulator which includes mismatch shaping technology that eliminates distortion due to capacitor mismatch. Following this stage is a multi-element switched capacitor stage and low-pass filter with single-ended analog outputs.

The CS4384 also has a proprietary DSD processor which allows for volume control and 50 kHz on-chip filtering without an intermediate decimation stage. It also offers an optional path for direct DSD conve r sion by directly using the multi-element switched capacitor array.

The CS4384 accepts PCM data at sample rates from 4 kHz to 216 kHz, DSD audio data, and delivers excellent sound quality. These featu res are ideal for multichannel audio systems including SACD players, A/V receivers, digital TV’s, mixing consoles, effects processors, and sound cards.

This product is available in 48-pin LQFP package in Commercial (-40°C to +85°C) temperature grade. See

“Ordering Information” on page 5 1 for complete details.

Control Port Supply = 1.8 V to 5 V

Hardware Mode or

C/SPI Software Mode

Control Data

Reset

Serial Audio Port Supply = 1.8 V to 5 V

PCM Serial

Audio Input

TDM Serial

Audio Input

DSD Audio

Inp ut

http://www.cirrus.com

Digital Supply = 2.5 V

Configura tion

Level Translator

Volume

Controls

DSD Processor

-Volume control

Level Translator

S e ria l In te rfa ce

-50 kHz filter

Digital F ilte rs

Multi-bit ∆Σ Modulators

Analog Supply = 5 V

Inte rna l Volta ge

Reference

Switch-C ap

DAC and

Analog Filters

E xterna l Mu te

Control

Eight Channels of Single-Ended Outputs

Mute Signals

MAY '08

DS620F1

TABLE OF CONTENTS

1. PIN DESCRIPTION................................................................................................................................. 6

2. CHARACTERISTICS AND SPECIFICATIONS...................................................................................... 8

RECOMMENDED OPERATING CONDITIONS .......................................................................................... 8

ABSOLUTE MAXIMUM RATINGS............................................................................................................... 8

DAC ANALOG CHARACTERISTICS........................................................................................................... 9

POWER AND THERMAL CHARACTERISTICS........................................................................................ 10

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE............................................ 11

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE............................................ 12

DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE ..................................................12

DIGITAL CHARACTERISTICS ............... ... ... ... ... .... ... ... ... .... ... ... ... .... ......................................... .... ............ 13

SWITCHING CHARACTERISTICS - PCM ................................................................................................ 14

SWITCHING CHARACTERISTICS - DSD.................................................................................................15

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT.................................................... 16

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT....................... ... ... ... ... .... ... ... ... ... 17

3. TYPICAL CONNECTION DIAGRAM ................................................................................................ 18

4. APPLICATIONS ................................................................................................................................... 20

4.1 Master Clock.................................................................................................................................. 20

4.2 Mode Select.................................................................................................................................. 21

4.3 Digital Interface Formats ............................................................................................................... 22

4.3.1 OLM #1 ................................................................................................................................ 23

4.3.2 OLM #2 ................................................................................................................................ 23

4.3.3 OLM #3 ................................................................................................................................ 24

4.3.4 OLM #4 ................................................................................................................................ 24

4.3.5 TDM ..................................................................................................................................... 24

4.4 Oversampling Modes..................................................................................................................... 25

4.5 Interpolation Filter.......................................................................................................................... 25

4.6 De-Emphasis................................................................................................................................. 25

4.7 ATAPI Specification....................................................................................................................... 26

4.8 Direct Stream Digital (DSD) Mode. ... ... ... .... ... .......................................... ... ... .... ... ... ... ... .... ... ......... 26

4.9 Grounding and Power Supply Arrangements................................................................................ 27

4.9.1 Capacitor Placement............................................................................................................ 27

4.10 Analog Output and Filtering...................... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... ................ 27

4.11 The MUTEC Outputs................................................ ... ... .... ... .......................................... ............ 28

4.12 Recommended Power-Up Sequence.......................................................................................... 29

4.12.1 Hardware Mode............................................................... ... ... .... ... ...................................... 29

4.12.2 Software Mode...................................................... .... ... ... ... ................................................ 29

4.13 Recommended Procedure for Switching Operational Modes...................................................... 30

4.14 Control Port Interface .................................................................................................................. 30

4.14.1 MAP Auto Increment.......................................................................................................... 30

4.14.2 I²C Mode ................................................................... ... ... ... ... .... ......................................... 30

4.14.3 SPI Mode ........................................................................... ... .... ... ...................................... 31

4.15 Memory Address Pointer (MAP)................................................................................................. 32

4.15.1 INCR (Auto Map Increment Enable) .................................................................................. 32

4.15.2 MAP4-0 (Memory Address Pointer) ................................................................................... 32

5. REGISTER QUICK REFERENCE ....................................................................................................... 33

6. REGISTER DESCRIPTION .................................................................................................................. 35

6.1 Chip Revision (Address 01h)......................................................................................................... 35

6.1.1 Part Number ID (PART) [Read Only] ......... .... ... ... ... .... ......................................... ................ 35

6.1.2 Revision ID (REV) [Read Only]............................................................................................ 35

6.2 Mode Control 1 (Address 02h) ...................................................................................................... 35

6.2.1 Control Port Enable (CPEN) ................................................................................................35

6.2.2 Freeze Controls (FREEZE)..................................................................................................35

CS4384

2 DS620F1

CS4384

6.2.3 PCM/DSD Selection (DSD/PCM)......................................................................................... 36

6.2.4 DAC Pair Disable (DACx_DIS) ............................................................................................ 36

6.2.5 Power Down (PDN).............................................................................................................. 36

6.3 PCM Control (Address 03h) .......................................................................................................... 36

6.3.1 Digital Interface Format (DIF)........ .... ... ... ... .... ... .......................................... ... ... ... .... ............ 36

6.3.2 Functional Mode (FM).......................................................................................................... 37

6.4 DSD Control (Address 04h)........... .......................................... ... .......................................... ......... 37

6.4.1 DSD Mode Digital Interface Format (DSD_DIF) .................................................................. 37

6.4.2 Direct DSD Conversion (DIR_DSD)........ ... .... ... ... ... .... ... .......................................... ... ......... 38

6.4.3 Static DSD Detect (STATIC_DSD) ...................................................................................... 38

6.4.4 Invalid DSD Detect (INVALID_DSD).................................................................................... 38

6.4.5 DSD Phase Modulation Mode Select (DSD_PM_MODE).................................................... 38

6.4.6 DSD Phase Modulation Mode Enable (DSD_PM_EN) ........................................................ 38

6.5 Filter Control (Address 05h) .......................................................................................................... 39

6.5.1 Interpolation Filter Select (FILT_SEL).................................................................................. 39

6.6 Invert Control (Address 06h) ................................................... ... ... ... .... ... ... ... .... ............................ 39

6.6.1 Invert Signal Polarity (INV_xx) ... ... .... ... ....................................... ... ... ... .... ... ... ... ... ................ 39

6.7 Group Control (Address 07h) ........................................................................................................ 39

6.7.1 Mutec Pin Control (MUTEC) ................................................................................................ 39

6.7.2 Channel A Volume = Channel B Volume (Px_A=B)............................................................. 39

6.7.3 Single Volume Control (SNGLVOL)..................................................................................... 40

6.8 Ramp and Mute (Address 08h) ..................................................................................................... 40

6.8.1 Soft Ramp and Zero Cross Control (SZC) ........................................................................... 40

6.8.2 Soft Volume Ramp-Up After Error (RMP_UP) ..................................................................... 41

6.8.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN)................................................... 41

6.8.4 PCM Auto-Mute (PAMUTE)................................................................................................. 41

6.8.5 DSD Auto-Mute (DAMUTE) ................................................................................................. 41

6.8.6 MUTE Polarity and DETECT (MUTEP1:0)..... ...................................................................... 41

6.9 Mute Control (Address 09h) .......................................................................................................... 42

6.9.1 Mute (MUTE_xx)........................................ .... ... ... ... ....................................... ... ... .... ... ......... 42

6.10 Mixing Control (Address 0Ah, 0Dh, 10h, 13h) ............. ... .... ... ... ................................................... 42

6.10.1 De-Emphasis Control (PX_DEM1:0).................................................................................. 42

6.10.2 ATAPI Channel Mixing and Muting (ATAPI) ...................................................................... 43

6.11 Volume Control (Address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h, 14h, 15h)........................................... 44

6.11.1 Digital Volume Control (xx_VOL7:0) .................................................................................. 44

6.12 PCM Clock Mode (Address 16h)................................................................................................. 44

6.12.1 Master Clock Divide by 2 Enable (MCLKDIV).................................................................... 44

7. FILTER RESPONSE PLOTS ............................................................................................................... 45

8. REFERENCES...................................................................................................................................... 49

9. PARAMETER DEFINITIONS................................................................................................................ 49

10. PACKAGE DIMENSIONS ............................................................. .......................................... ......... .. 50

11. ORDERING INFORMATION ......................................................... ... ... ... ............................................ 51

12. REVISION HISTORY .................................................... ... ... ... .... ... ................................................... .. 51

DS620F1 3

LIST OF FIGURES

Figure 1. Serial Audio Interface Timing...................................................................................................... 14

Figure 2. TDM Serial Audio Interface Timing............................................................................................. 14

Figure 3. Direct Stream Digital - Serial Audio Input Timing........................................................................ 15

Figure 4. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode........................... 15

Figure 5. Control Port Timing - I²C Format................................................................................................. 16

Figure 6. Control Port Timing - SPI Format................................................................................................ 17

Figure 7. Typical Connection Diagram, Software Mode.............................................................................18

Figure 8. Typical Connection Diagram, Hardware Mode........................ ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 19

Figure 9. Format 0 - Left-Justified up to 24-bit Data .................................................................................. 22

Figure 10. Format 1 - I²S up to 24-bit Data................................................................................................ 22

Figure 11. Format 2 - Right-Justified 16-bit Data....................................................................................... 22

Figure 12. Format 3 - Right-Justified 24-bit Data....................................................................................... 22

Figure 13. Format 4 - Right-Justified 20-bit Data....................................................................................... 22

Figure 14. Format 5 - Right-Justified 18-bit Data....................................................................................... 23

Figure 15. Format 8 - One Line Mode 1..................................................................................................... 23

Figure 16. Format 9 - One Line Mode 2..................................................................................................... 23

Figure 17. Format 10 - One Line Mode 3................................................................................................... 24

Figure 18. Format 11 - One Line Mode 4................................................................................................... 24

Figure 19. Format 12 - TDM Mode............................................................................................................. 24

Figure 20. De-Emphasis Curve.................................................................................................................. 25

Figure 21. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4)............................................................... 26

Figure 22. DSD Phase Modulation Mode Diagram....................................................................................27

Figure 23. Full-Scale Output...................................................................................................................... 28

Figure 24. Recommended Output Filter..................................................................................................... 28

Figure 25. Recommended Mute Circuitry .................................................................................................. 29

Figure 26. Control Port Timing, I²C Mode.................................. ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ............ 31

Figure 27. Control Port Timing, SPI Mode................................. ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ............ 32

Figure 28. Single-Speed (fast) Stopband Rejection................................................................................... 45

Figure 29. Single-Speed (fast) Transition Band......................................................................................... 45

Figure 30. Single-Speed (fast) Transition Band (detail)............................................................................. 45

Figure 31. Single-Speed (fast) Passband Ripple.................................................... ... .... ... ... ... ... ................ 45

Figure 32. Single-Speed (slow) Stopband Rejection .............................................................. ... .... ... ... ...... 45

Figure 33. Single-Speed (slow) Transition Band........................................................................................ 45

Figure 34. Single-Speed (slow) Transition Band (detail)............................................................................ 46

Figure 35. Single-Speed (slow) Passband Ripple...................................................................................... 46

Figure 36. Double-Speed (fast) Stopband Rejection ................................................................................. 46

Figure 37. Double-Speed (fast) Transition Band........................................................................................ 46

Figure 38. Double-Speed (fast) Transition Band (detail)............................................................................ 46

Figure 39. Double-Speed (fast) Passband Ripple...................................................................................... 46

Figure 40. Double-Speed (slow) Stopband Rejection................................................................................ 47

Figure 41. Double-Speed (slow) Transition Band................................ ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... . ..... 47

Figure 42. Double-Speed (slow) Transition Band (detail)................................. ... ... ... .... ... ... ... ... .... ... ... ... ... 47

Figure 43. Double-Speed (slow) Passband Ripple.................................................................................... 47

Figure 44. Quad-Speed (fast) Stopband Rejection....................................... .... ... ... ... .... ............................ 47

Figure 45. Quad-Speed (fast) Transition Band .......................................................................................... 47

Figure 46. Quad-Speed (fast) Transition Band (detail)........................ ... ... ... .... ... ... ... .... ... ... ... ................... 48

Figure 47. Quad-Speed (fast) Passband Ripple........................................................................................ 48

Figure 48. Quad-Speed (slow) Stopband Rejection................................................................................... 48

Figure 49. Quad-Speed (slow) Transition Band......................................................................................... 48

Figure 50. Quad-Speed (slow) Transition Band (detail)............................................................................. 48

Figure 51. Quad-Speed (slow) Passband Ripple....................................................................................... 48

CS4384

4 DS620F1

LIST OF TABLES

Table 1. Single-Speed Mode Standard Frequencies ................................................................................ 20

Table 2. Double-Speed Mode Standard Frequencies............................................................................... 20

Table 3. Quad-Speed Mode Standard Frequencies ......................................................................... ... ... .. 20

Table 4. PCM Digital Interface Format, Hardware Mode Options............................................................. 21

Table 5. Mode Selection, Hardware Mode Options .................................................................................. 21

Table 6. Direct Stream Digital (DSD), Hardware Mode Options ............................................................... 21

Table 7. Digital Interface Formats - PCM Mode........................................................................................ 37

Table 8. Digital Interface Formats - DSD Mode ........................................................................................ 37

Table 9. ATAPI Decode .......................................................................... ... ... .... ... ... ... ............................... 43

Table 10. Example Digital Volume Settings.............................................................................................. 44

CS4384

DS620F1 5

1. PIN DESCRIPTION

DSD3

DSD2 DSD1

GND MCLK LRCK SDIN1 SCLK

M4(TST)

SDIN2

M3(TST)

DSD6

DSD5

DSD7

SDIN4

CS4384

M1(SDA/CDIN)

M2(SCL/CCLK)

DSD8

M0(AD0/CS)

DSD4

48 47 46 45 44 43 42 41 40 39 38 37

13 14 15 16 17 18 19 20 21 22

SDIN3

VLS

VLC

CS4384

AOUT2

AOUT1

23 24

MUTEC2

TST_OUT

AOUT8

TST_OUT AOUT3 AOUT4 TST_OUT VA GND TST_OUT AOUT5 AOUT6 TST_OUT

TST_OUT AOUT7

TST_OUT

MUTEC1

DSD_SCLK

RST

FILT+

Pin Name # Pin Description

VD 4

GND

MCLK 6

LRCK 7 SDIN1

SDIN2 SDIN3 SDIN4

SCLK 9 Serial Clock (Input) - Serial clocks for the serial audio interface.

VLC 18

RST

FILT+ 20

VQ 21 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. MUTEC1

MUTEC234

Digital Power (Input) - Positive power supply for the digital section. Refer to the Recommended Operating Conditions for appropriate voltages.

Ground (Input) - Ground reference. Should be connected to analog ground.

Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Table 1 illus- trates several standard audio sample rates and the required master clock frequencies.

Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.

Serial Data Input (Input) - Input for two’s complement serial audio data.

13 14

Control Port Power (Input) - Determines the required signal level for the control port and hardware mode configuration pins. Refer to the Recommended Operating Conditions fo r appropriate voltages.

Reset (Input) - The device enters a low power mode and all internal registers are reset to their

default settings when low. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir-

cuits. Requires the capacitive decoupling to analog ground as shown in the Typical Connection Diagram.

4122Mute Control (Output) - These pins are intended to be used as a control for external mute circuits

on the line outputs to prevent the clicks and pops that can occur in any single supply system.

6 DS620F1

CS4384

Pin Name # Pin Description

AOUT1 AOUT2 AOUT3 AOUT4 AOUT5 AOUT6 AOUT7 AOUT8

VA 32

VLS 43

TST_OUT

Hardware Mode Definitions

M0 M1 M2 M3 M4

Software Mode Definitions

SCL/CCLK 15

SDA/CDIN 16

AD0/CS 17

TST

DSD Definitions

DSD1, DSD2 DSD3, DSD4 DSD5, DSD6 DSD7, DSD8

DSD_SCLK 42 DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital serial audio interface.

39 38 35 34 29 28 25 24

23, 26 27, 30 33, 36 37, 40

17 16 15 12 10

10 12

3, 2

1, 48

47,46

45, 44

Analog Output (Output) - The full scale analog output level is specified in the Analog Characteris- tics specification table.

Analog Power (Input) - Positive power supply for the analog section. Refer to the Recommended Operating Conditions for appropriate voltages.

Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio interface. Refer to the Recommended Operating Conditions for appropriate voltages.

Test Output - These pins need to be floating and not connected to any trace or plane.

Mode Selection (Input) - Determines the operational mode of the device as detailed in Tables 4 and 5.

Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up resistor to the logic interface voltage in I²C

gram. Serial Control Port Data (Input/Output) - SDA is a data I/O line in I²C mode and is open drain,

requiring an external pull-up resistor to the logic interface voltage, as shown in the Typical Connection Diagram; CDIN is the input data line for the control port interface in SPI

Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C mode; CS

Test - T hese pins need to be tied to analog ground.

Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data.

is the chip select signal for SPI mode.

mode as shown in the Typical Connection Dia-

™

mode.

DS620F1 7

CS4384

2. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

(GND = 0 V; all voltages with respect to ground.)

Parameters Symbol Min Typ Max Units

DC Power Supply Analog power

Digital internal power

Serial data port interface power

Control port interface power

Ambient Operating Temperature (Power Applied) -CQZ T

VA VD

VLS

VLC

4.75

2.37

1.71

-40 - +85 °C

5.0

2.5

5.0

5.25

2.63

5.25

V V V V

ABSOLUTE MAXIMUM RATINGS

(GND = 0 V; all voltages with respect to ground.)

Parameters Symbol Min Max Units

DC Power Supply Analog power

Digital internal power

Serial data port interface power

Control port interface power Input Current Any Pin Except Supplies I Digital Input Voltage Serial data port interface

Control port interface Ambient Operating Temperature (power applie d) T Storage Temperature T

WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

VD VLS VLC

IND-S

IND-C

stg

-0.3

-±10mA

-0.3

-55 125 °C

-65 150 °C

6.0

3.2

6.0

VLS+ 0.4 VLC+ 0.4

V V V V

V V

8 DS620F1

CS4384

DAC ANALOG CHARACTERISTICS

Test Conditions (unless otherwise indicated): VA = VLS = VLC = 5 V; VD = 2.5 V; TA = 25 °C; Full-Scale 997 Hz input sine wave

“Typical Connection Diagram” on page 18; Measurement Bandwidth 10 Hz to 20 kHz.

FS = 48 kHz, 96 kHz, 192 kHz and DSD

Dynamic Range 24-bit A-weighted

Total Harmonic Distortion + Noise 24-bit -0 dB

Idle Channel Noise / Signal-to-noise ratio - 100 - dB Interchannel Isolation (1 kHz) - 110 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB Gain Drift - 100 - ppm/°

Analog Output

Full Scale Differential- PCM, DSD processor Output Voltage (Note 3) Direct DSD Mode

Output Impedance Z Max DC Current draw from an AOUT pin I Min AC-Load Resistance R Max Load Capacitance C Quiescent Voltage V Max Current draw from V

(Note 1); Tested under max ac-load resistance; Valid with FILT+ and VQ capacitors as shown in

Parameters Symbol Min Typ Max Unit

16-bit A-weighted

(Note 2) unweighted

(Note 2) 16-bit 0 dB

unweighted

-20 dB

-60 dB

-20 dB

-60 dB

THD+N -

64%•V 47%•V

OUT

OUTmax

L L

QMAX

97 94

A A

- 130 - Ω

-1.0-mA

-3-kΩ

- 100 - pF

- 50% VA-VDC

-10-µA

103 100

97 94

-88

-80

-40

-88

-74

-34

66%•V 48%•V

-82

-74

-34

dB dB dB dB

dB dB dB dB dB dB

A A

68%•V 49%•V

Vpp

Notes:

1. One-half LSB of triangular PDF dither is added to data.

2. Performance limited by 16-bit quantization noise.

3. V

is tested under load RL and includes attenuation due to Z

OUT

DS620F1 9

CS4384

POWER AND THERMAL CHARACTERISTICS

Parameters Symbol Min Typ Max Units

Power Supplies

Power Supply Current normal operation, VA= 5 V

(Note 4) VD= 2.5 V

(Note 5) Interface current, VLC=5 V

VLS=5 V

(Note 6) power-down state (all supplies)

Power Dissipation (Note 4) VA = 5V, VD = 2.5V

normal operation

(Note 6) power-down

Package Thermal Resistance multi-layer

dual-layer

Power Supply Rejection Ratio (Note 7) (1 kHz) (60 Hz)

Notes:

4. Current consumption increases with increasing FS within a given spe ed mode and is signal dependant. Max values are based on highest FS and highest MCLK.

5. I

6. Power Down Mode is defined as RST

measured with no external loading on the SDA pin.

pin = Low with all clock and data lines held static.

7. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 7 and 8.

PSRR -

83 20

200

465

48 65 15

60 40

92 25

520

mA mA

µA µA µA

mW mW

°C/Watt °C/Watt °C/Watt

dB dB

10 DS620F1

CS4384

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. (See (Note 12))

Parameter

Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz

Passband (Note 9) to -0.01 dB corner Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB

StopBand 0.547 - - Fs StopBand Attenuation (Note 10) 102 - - dB Group Delay - 10.4/Fs - s De-emphasis Error (Note 11) Fs = 32 kHz (Relative to 1 kHz) Fs = 44.1 kHz

Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz

Passband (Note 9) to -0.01 dB corner Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB

StopBand .583 - - Fs StopBand Attenuation (Note 10) 80 - - dB Group Delay - 6.15/Fs - s

Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz

Passband (Note 9) to -0.01 dB corner Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB

StopBand .635 - - Fs StopBand Attenuation (Note 10) 90 - - dB Group Delay - 7.1/Fs - s

to -3 dB corner

Fs = 48 kHz

to -3 dB corner

0 0

Fast Roll-Off

.454 .499

±0.36 ±0.21 ±0.14

.430 .499

.105 .490

UnitMin Typ Max

Fs Fs

dB dB dB

Fs Fs

Notes:

8. Slow Roll-off interpolation filter is only available in Software Mode.

9. Response is clock dependent and will scale with Fs.

10. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.

11. De-emphasis is available only in Single-Speed Mode; Only 44.1 kHz De-emphasis is available in Hardware Mode.

12. Amplitude vs. Frequency plots of this data are available in the “Filter Response Plots” on page 45.

DS620F1 11

CS4384

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

(CONTINED)

Slow Roll-Off (Note 8)

Parameter

Single-Speed Mode - 48 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB StopBand .583 - - Fs StopBand Attenuation (Note 10) 64 - - dB Group Delay - 7.8/Fs - s De-emphasis Error (Note 11) Fs = 32 kHz (Relative to 1 kHz) Fs = 44.1 kHz

Fs = 48 kHz

0 0

0.417

0.499

±0.36 ±0.21 ±0.14

Double-Speed Mode - 96 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB StopBand .792 - - Fs StopBand Attenuation (Note 10) 70 - - dB Group Delay - 5.4/Fs - s

0 0

.296 .499

Quad-Speed Mode - 192 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB StopBand .868 - - Fs StopBand Attenuation (Note 10) 75 - - dB Group Delay - 6.6/Fs - s

0 0

.104 .481

UnitMin Typ Max

Fs Fs

dB dB dB

Fs Fs

DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE

Parameter Min Typ Max Unit

DSD Processor Mode

Passband (Note 9) to -3 dB corner 0 - 50 kHz Frequency Response 10 Hz to 20 kHz -0.05 - +0.05 dB Roll-off 27 - - dB/Oct

Direct DSD Mode

Passband (Note 9) to -0.1 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz -0.1 - 0 dB

0 0

26.9

176.4

kHz kHz

12 DS620F1

CS4384

DIGITAL CHARACTERISTICS

Parameters Symbol Min Typ Max Units

Input Leakage Current (Note 13) I

Input Capacitance - 8 - pF High-Level Input Voltage Serial I/O

Control I/O

Low-Level Input Voltage Serial I/O

Control I/O

Low-Level Output Voltage (IOL= -1.2 mA) Control I/O = 3.3 V, 5 V

Control I/O = 1.8 V, 2.5 V MUTEC auto detect input high voltage V MUTEC auto detect input low voltage V Maximum MUTEC Drive Current I MUTEC High-Level Output Voltage V MUTEC Low-Level Output Voltage V

V V

max

IH IH

IL IL

OL OL

IH IL

OH OL

13. Any pin except supplies. Transient currents of up to ±100 mA on the input pins will not cause SCR latch-up

--±10µA

70% 70%

30% 30%

20% 25%

70% - - VA

--30%VA

-3-mA

-VA-V

-0-V

DS620F1 13

CS4384

SWITCHING CHARACTERISTICS - PCM

(Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 30 pF)

Parameters Symbol Min Max Units

RST pin Low Pulse Width (Note 14) MCLK Frequency 1.024 55.2 MHz MCLK Duty Cycle (Note 15) 45 55 % Input Sample Rate - LRCK (Manual selection) Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

Input Sample Rate - LRCK (Auto detect) Single-Spe ed Mode

Double-Speed Mode

Quad-Speed Mode

F F F

Fs Fs Fs

s s s

LRCK Duty Cycle (Note 16) 45 55 % SCLK Duty Cycle 45 55 % SCLK High Time t SCLK Low Time t LRCK Edge to SCLK Rising Edge t SCLK Rising Edge to LRCK Falling Edge t SDIN Setup Time Before SCLK Rising Edge t SDIN Hold Time After SCLK Rising Edge t

sckh

sckl lcks lckd

1-ms

100

170

54 108 216

kHz kHz kHz

8-ns 8-ns 5-ns 5-ns 3-ns 5-ns

Notes:

14. After powering up, RST

should be held low until after the power supplies and clocks are settled.

15. See Tables 1 - 3 for suggested MCLK frequencies.

16. Not required for TDM Mode.

LRCK

sckh

MSB

SCLK

SDINx

lcks

Figure 1. Serial Audio Interface Timing Figure 2. TDM Serial Audio Interface Timing

sckl

MSB-1

LRCK

SCLK

SDIN1

lcks

lckd

lcks

sckh

MSB MSB-1

sckl

14 DS620F1

CS4384

SWITCHING CHARACTERISTICS - DSD

(Logic 0 = AGND = DGND; Logic 1 = VLS; CL=30pF)

Parameter Symbol Min Typ Max Unit

MCLK Duty Cycle 40 - 60 % DSD_SCLK Pulse Width Low t DSD_SCLK Pulse Width High t DSD_SCLK Frequency (64x Oversampled)

(128x Oversampled) DSD_A / _B valid to DSD_SCLK rising setup time t DSD_SCLK rising to DSD_A or DSD_B hold time t DSD clock to data transition (Phase Modulation Mode) t

DSD_SCLK

sclkl

sclkh

sdlrs

sdh

dpm

sclkl

160 - - ns 160 - - ns

1.024

2.048 20 - - ns 20 - - ns

-20 - 20 ns

sclkh

3.2

6.4

MHz MHz

sdlrstsdh

DSDxx

Figure 3. Direct Stream Digital - Serial Audio Input Timing

dpm

DSD_SCLK

(128Fs)

DSD_SCLK

(64Fs)

DSDxx

Figure 4. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode

dpm

DS620F1 15

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT

(Inputs: Logic 0 = GND, Logic 1 = VLC, CL=30pF)

Parameter Symbol Min Max Unit

CS4384

SCL Clock Frequency f

Rising Edge to Start t

RST Bus Free Time Between Transmissions t Start Condition Hold Time (prior to first clock pulse) t Clock Low time t Clock High Time t Setup Time for Repeated Start Condition t SDA Hold Time from SCL Falling (Note 17) t SDA Setup time to SCL Rising t Rise Time of SCL and SDA t Fall Time SCL and SDA t Setup Time for Stop Condition t Acknowledge Delay from SCL Falling t

Notes:

17. Data must be held for sufficient time to bridge the transition time, t

buf

hdst

low high sust

hdd

sud

susp

ack

scl

- 100 kHz

irs

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs 0-µs

250 - ns

, t

-1µs

- 300 ns

4.7 - µs

300 1000 ns

, of SCL.

RST

SDA

SCL

irs

Stop S ta rt

buf

hdd

high

sud

hdst

low

Figure 5. Control Port Timing - I²C Format

Repeated

Start

sust

hdst

Stop

susp

16 DS620F1

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT

(Inputs: Logic 0 = GND, Logic 1 = VLC, CL=30pF)

Parameter Symbol Min Max Unit

CS4384

CCLK Clock Frequency f

Rising Edge to CS Falling t

RST CCLK Edge to CS CS

High Time Between Transmissions t Falling to CCLK Edge t

CS CCLK Low Time t CCLK High Time t CDIN to CCLK Rising Setup Time t CCLK Rising to DATA Hold Time (Note 19) t Rise Time of CCLK and CDIN (Note 20) t Fall Time of CCLK and CDIN (Note 20) t

Falling (Note 18) t

sclk

srs

spi csh css

scl sch dsu

r2 f2

Notes:

18. t

only needed before first falling edge of CS after RST rising edge. t

spi

19. Data must be held for sufficient time to bridge the transition time of CCLK.

20. For F

< 1 MHz.

SCK

RST

srs

-6MHz 500 - ns 500 - ns

1.0 - µs 20 - ns 66 - ns 66 - ns 40 - ns 15 - ns

-100ns

= 0 at all other times.

spi

css

scl

sch

csh

CCLK

CDIN

Figure 6. Control Port Timing - SPI Fo rmat

DS620F1 17

dsu

3. TYPICAL CONNECTION DIAGRAM

CS4384

+1.8 V t o +5 V

+2.5 V

PCM Digital Audio

Source

DSD

Audio

Source

1 µF

220 Ω

470 Ω

6 7 9

8 11 13 14

0.1 µF

46 45 44 42

0.1 µF

3 2 1

MCLK LRCK

SCLK SDI N 1

SDI N 2 SDI N 3 SDI N 4

VLS

DSD1 DSD2 DSD3 DSD4

DSD5 DSD6 DSD7 DSD8 DSD_SCLK

CS4384

AOUT1

AOUT2

AOUT3

AOUT4

AOUT5

AOUT6

AOUT7

AOUT8

MUTEC1

MUTEC234

0.1 µF

41 22

1 µF

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Mute Driv e

+5 V

RST

Note*

0.1 µF

15 16 17

SC L/CCLK

SDA/CDIN

ADO/CS

VLC

GND

TST_OUT

FILT+

TST*

*P ins:

10, 12

0.1 µ

Pins: 23, 26, 27,

30, 33, 36, 37, 40

1 µF

0.1 µ

47 µF

+1.8 V t o +5 V

Note: Necessary f or I2C

Mic ro-

Controller

2 KΩ2 KΩ

control port operation

Figure 7. Typical Connection Diagram, Software Mode

18 DS620F1

CS4384

+1.8 V to +5 V

PCM Digital Audio

Source

DSD

Audio

Source

Stand-Alone

Configuration

+2.5 V

Mode

220 Ω

470 Ω

1 µF

Optional

47 K Ω

0.1 µF

0.1 µ

+5 V

47 µF

0.1 µF 4

MCLK

LRCK

SCLK

SDIN1

SDIN2

SDIN3

SDIN4

VLS

CS 4384

DSDA1

DSDB1

DSDA2

DSDB2

DSDA3

DSDB3

DSDA4

DSDB4

DSD_SCLK

MUTEC234

RST

AOUT1

AOUT2

AOUT3

AOUT4

AOUT5

AOUT6

AOUT7

AOUT8

MUTEC1

FILT+

0.1 µF

41 22

1 µF

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Mute Drive

1 µF

0.1 µ

0.1 µF

VLC

GND

TST_OUT

GND

Pins : 23, 26, 27,

30, 33, 36, 37, 40

+1.8 V to +5 V

Figure 8. Typical Connection Diagram, Hardware Mode

DS620F1 19

CS4384

4. APPLICATIONS

The CS4384 serially accepts twos complement formatted PCM data at standard audio sample rates including 48,

44.1 and 32 kHz in SSM, 96, 88.2 a nd 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer. For more information on serial audio interfaces see AN282 “The 2-Channel Serial Audio Interface: A Tutoria l”.

The CS4384 can be configured in Hardware Mode by the M0, M1, M2, M3 and M4 pins and in Software Mode through I²C or SPI.

4.1 Master Clock

MCLK/LRCK must be an integer ratio as shown in Tables 1 - 3. The LRCK frequency is equal to Fs, the frequency at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio and speed mode is detected automatically during the initialization sequence by counting the number of MCLK transitions during a single LRCK period and by detecting the absolute speed of MCLK. Internal dividers are then set to generate the proper internal clocks. Tables 1 - 3 illustrate several standard audio sample rates and the required MCLK and LRCK frequencies. Please note there is no required phase relationship, but MCLK, LRCK and SCLK must be synchronous.

Sample Rate

(kHz)

32 8.1920 12.2880 16.3840 24.5760 32.7680 36.8640

44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520

256x 384x 512x 768x 1024x 1152x

Table 1. Single-Speed Mode Standard Frequencies

Sample Rate

(kHz)

64 8.1920 12.2880 16.3840 24.5760 32.7680

88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520

128x 192x 256x 384x 512x

Table 2. Double-Speed Mode Standard Frequencies

Sample Rate

(kHz)

176.4 11.2896 16.9344 22.5792 33.8688 45.1584 192

64x 96x 128x 192x 256x

12.2880 18.4320 24.5760 36.8640 49.1520

Table 3. Quad-Speed Mode Standard Frequencies

MCLK (MHz)

= Denotes clock ratio and sample rate combinations which are NOT supported under auto

speed-mode detection. Please see “Switching Characteristics - PCM” on page 14.

20 DS620F1

4.2 Mode Select

In Hardware Mode, operation is determined by the Mode Select pins. The states of these pins are continually scanned for any changes; however, the mode should only be changed while the device is in reset (RST

pin low) to ensure prope r switching from one mod e to another. These pin s require co nnection to supply or ground as outlined in Figure 8. For M0, M1, and M2, supply is VLC. For M3 and M4, supply is VLS.

Tables 4 - 6 show the decode of these pins.

In Software Mode, the operational mode and data format are set in the FM and DIF registers. See “PCM

Control (Address 03h)” on page 36.

CS4384

(DIF1)

(DIF0)

00 01

10 11

M4 M3 M2

(DEM)

000 001 010 011 100 101 11 Table 6

DESCRIPTION FORMAT FIGURE

Left Justified, up to 24-bit data

S, up to 24-bit data Right Justified, 16-bit Data Right Justified, 24-bit Data

Table 4. PCM Digital Interface Format, Hardware Mode Options

M1 M0 DESCRIPTION

Single-Speed without De-Emphasis (4 kHz to 50 kHz sample rates) Single-Speed with 44.1 kHz De-Emphasis; see Figure 20 Double-Speed (50 kHz to 100 kHz sample rates)

Table 4

Quad-Speed (100 kHz to 200 kHz sample rates) Auto Speed-Mode Detect (32 kHz to 200 kHz sample rates) Auto Speed-Mode Detect with 44.1 kHz De-Emphasis; see Figure 20 DSD Processor Mode

Table 5. Mode Selection, Hardware Mode Options

0 9 1 10

2 11 3 12

M2 M1 M0 DESCRIPTION

000 001 010 011 100 101 110 111

Table 6. Direct Stre am Digital (DSD), Hardware Mode Options

64x oversampled DSD data with a 4x MCLK to DSD data rate 64x oversampled DSD data with a 6x MCLK to DSD data rate 64x oversampled DSD data with a 8x MCLK to DSD data rate 64x oversampled DSD data with a 12x MCLK to DSD data rate 128x oversampled DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate

DS620F1 21

4.3 Digital Interface Formats

The serial port operates as a slave and supports the I²S, Left-Justified, Right-Justified, One-Line Mode (OLM) and TDM digital interface formats with varying bit depths from 16 to 32 as shown in Figures 9-19. Data is clocked into the DAC on the rising edge. OLM and TDM configurations are only supported in Software Mode.

CS4384

LRCK

SCLK

SDINx +3 +2 +1+5 +4

MSB LSB MSB LSB

-1 -2 -3 -4 -5

Left Channel

Figure 9. Format 0 - Left-Justified up to 24-bit Data

LRCK

SCLK

SDINx +3 +2 +1+5 +4

LRCK

SCLK

SDINx

MSB

-2 -3 -4 -5

-1

15 14 13 12 11 10

Left Channel

-2 -3 -4

-1

LSB LSB

MSB

-1

-2 -3 -4

Figure 10. Format 1 - I²S up to 24-bit Data

6543210987

15 14 13 12 11 10

Right Channel

+3 +2 +1+5 +4

Right Channel

+3 +2 +1+5 +4

Right Channel

6543210987

Figure 11. Format 2 - Right-Justified 16-bit Data

Left Channel

65432107

Figure 12. Format 3 - Right-Justified 24-bit Data

Right Channel

23 22 21 20 19 18

65432107

LRCK

SCLK

SDINx

32 clocks

23 22 21 20 19 18

32 clocks

LRCK

SCLK

SDINx

Left Channel

17 16 17 16

19 18 19 18

15 14 13 12 11 10

Figure 13. Format 4 - Right-Justified 20-bit Data

32 clocks

6543210987

15 14 13 12 11 10

Right Channel

6543210987

22 DS620F1

CS4384

LRCK

SCLK

SDINx

4.3.1 OLM #1

OLM #1 serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to SCLK at 128 Fs. Six channels of MSB first 20-bit PCM data are input on SDIN1. The last two channels are input on SDIN4.

LRCK

SCLK

SDIN1

SDIN4

DAC_A1

20 clks

DAC_A4

20 clks 20 clks

Left Channel

17 16 17 16

15 14 13 12 11 10

32 clocks

Figure 14. Format 5 - Right-Justified 18-bit Data

64 clks 64 clks

Left Channel Right Channel

LSBMSB

LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB MSB

DAC_A2 DAC_A3

20 clks 20 clks 20 clks 20 clks 20 clks

6543210987

DAC_B1

DAC_B4

Right Channel

15 14 13 12 11 10

DAC_B2 DAC_B3

6543210987

4.3.2 OLM #2

OLM #2 serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to SCLK at 256 Fs. Six channels of MSB first 24-bit PCM data are input on SDIN1. The last two channels are input on SDIN4.

LRCK

SCLK

SDIN1

SDIN4

DAC_A1

24 clks

DAC_A4

24 clks 24 clks

Figure 15. Format 8 - One Line Mode 1

128 clks

Left Channel Right Channel

LSBMSB

DAC_A2 DAC_A3 DAC_B1 DAC_B2 DAC_B3

LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB MSB

24 clks 24 clks 24 clks 24 clks 24 clks

DAC_B4

Figure 16. Format 9 - One Line Mode 2

128 clks

DS620F1 23

4.3.3 OLM #3

OLM #3 serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to SCLK at 256 Fs. Eight channels of MSB first 20-bit PCM data are input on SDIN1.

CS4384

LRCK

SCLK

SDIN1

LSBMSB

DAC_A1

20 clks

4.3.4 OLM #4

OLM #4 serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to SCLK at 256 Fs. Eight channels of MSB first 24-bit PCM data are input on SDIN1.

LRCK

SCLK

SDIN1

LSBMSB

DAC_A1

24 clks

128 clks

Left Channel

LSBMSB LSBMSB

DAC_A2 DAC_A3

20 clks 20 clks

Figure 17. Format 10 - One Line Mode 3

128 clks

Left Channel

LSBMSB LSBMSB

DAC_A2 DAC_A3

24 clks 24 clks

Figure 18. Format 11 - One Line Mode 4

DAC_A4

20 clks

DAC_A4

24 clks

128 clks

Right Channel

LSBMSB

LSBMSB LSBMSB LSBMSB MSB

DAC_B1 DAC_B2 DAC_B3

20 clks 20 clks 20 clks

128 clks

Right Channel

LSBMSB LSBMSB LS BMSB MSB

DAC_B1 DAC_B2 DAC_B3

24 clks 24 clks 24 clks

DAC_B4

20 clks

DAC_B4

24 clks

LSBMSB

4.3.5 TDM

The TDM serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to SCLK at 256 Fs. Data is received most significant bit first on the first SCLK after an LRCK transition and is valid on the rising edge of SCLK. LRCK identifies the start of a new frame and is equal to the sample rate, Fs. LRCK is sampled as valid on the rising SCLK edge preceding the most significant bit of the first data sample and must be held valid for one SCLK period . Each time slot is 32 bits wide, with the valid data sample left justified within the time slot with the remaining bits being zero padded.

RCK

CLK

DIN1

LSB

256 clks

LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB

DAC_A1 DAC_B1 DAC_A3DAC_A2

32 clks 32 clks 32 clks 32 clks 32 clks

Data

LSBMSB

zero

DAC_B2

32 clks

LSBMSB

DAC_B3

Figure 19. Format 12 - TDM Mode

DAC_A4

32 clks

LSBMSB

DAC_B4

32 clks

24 DS620F1

4.4 Oversampling Modes

The CS4384 operates in one of three oversampling mode s based on the input sample rate. Mo de selection is determined by the M4, M3 and M2 pins in Hardware Mode or the FM bits in Software Mode. Single-Speed Mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed Mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed Mode supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x.

The auto speed-mode detect feature allows for the automatic selection of speed mode based off of the incoming sample rate. This allows the CS4384 to accept a wide range of sample rates with no external intervention necessary. The auto speed-mode detect feature is available in both Hardware and Software Mod e.

4.5 Interpolation Filter

To accommodate the increasingly complex requirements of digital audio systems, the CS4384 incorporates selectable interpolation filters for each mode of operation. A “fast” and a “s low” roll-off filter is available in each of Single-, Double-, or Quad-Speed Modes. These filters have been designed to accommodate a variety of musical tastes and styles. The FILT_SEL bit is used to select which filter is used (see the “Parameter

Definitions” on page 49 for more details).

When in Hardware Mode, only the “fast” roll-off filter is available. Filter specifications can be found in Section 2, and filter response plots can be found in Figures 28 to 51.

CS4384

4.6 De-Emphasis

The CS4384 includes on-chip digital de-emphasis filters. The de-emphasis featur e is included to accommodate older audio recordings that utilize pre-emphasis equalization as a means of noise reduction. Figure 20 shows the de-emphasis curve. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs if the input sample rate does not match the coefficient which has been selected.

In Software Mode the required d e- em p ha sis f i lt er co efficients for 32 kHz, 44.1 kHz, or 48 kHz are select ed via the de-emphasis control bits.

In Hardware Mode only the 44.1 kHz coefficient is available (enabled through the M2 pin). If the input sample rate is not 44.1 kHz and de-emphasis has been selected th en the corner frequencies of the de-emphasis filter will be scaled by a factor of the actual Fs over 44,100.

Gain

0dB

-10dB

T1=50 µs

T2 = 15 µs

F1 F2

3.183 kHz 10.61 kHz

Figure 20. De-Emphasis Curve

Frequency

DS620F1 25

4.7 ATAPI Specification

The CS4384 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 9 on page 43 and Figure 21 for additional information.

CS4384

Left Chan

SDINx

Right Channel

nel

Audio Data

ΣΣ

Audio Data

Figure 21. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4)

4.8 Direct Stream Digital (DSD) Mode

In Software Mode the DSD/PCM bits (Reg. 02h) are used to configure the device for DSD mode. The DSD_DIF bits (Reg 04h) then control the expected DSD rate and MCLK ratio.

The DIR_DSD bit (Reg 04h) selects between two proprietary methods for DSD to analog conversion. The first method uses a decimation free DSD processing technique which allows for features such as matched PCM level output, DSD volume control, and 50kHz on chip filter. The second method sends the DSD data directly to the on-chip switched-capacitor filter for conversion (without the above mentioned features).

A Channel

Volume Control

BChannel

Volume Control

MUTE

AoutAx

AoutBx

The DSD_PM_EN bit (Reg. 04h) selects Pha se Modulation (data plus data inver ted) as the style of data input. In this mode the DSD_PM_Mode bit selects whether a 128Fs or 64x clock is used for phase modulated 64x data (see Figure 22). Use of Phase Modulation Mode may not directly effect the performance of the CS4384, but may lower the sensitivity to board level routing of the DSD data signals.

The CS4384 can detect errors in the DSD data which does not comply with the SACD specification. The STATIC_DSD and INVALID_DSD bits (Reg. 04h) allow the CS4384 to alter the incoming in valid DSD data. Depending on the error, the data may either be attenuated or replaced with a muted DSD signal (the MUTEC pins would be set according to the DAMUTE bit (Reg. 08h)).

More information for any of these register bits can be found in the “Parameter Definitions” on page 49. The DSD input structure and analog outputs are designed to handle a nominal 0 dB-SACD (50% modulation

index) at full rated performance. Signals of +3 dB-SACD may be applied for brief periods of time however, performance at these levels is not guaranteed. If sustained +3 dB-SACD levels are required, the digital volume control should be set to -3.0 dB. This same volume control register affects PCM output levels. There is no need to change the volume control setting between PCM and DSD in order to have the 0 dB output levels match (both 0 dBFS and 0 dB-SACD will output at -3 dB in this case).

26 DS620F1

DSD Normal Mode

CS4384

DSD Phase

Modulation Mode

Not Used

BCKA

(64Fs)

DSD_SCLK

Not Used

DSDAx,

DSDBx

D1D0 D2

Figure 22. DSD Phase Modulation Mode Diagram

4.9 Grounding and Power Supply Arrangements

As with any high resolution converter, the CS4384 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. The Typical Connection Diagram shows the recommended power arrangements, with VA, VD, VLC, and VLS connected to clean supplies. If the ground planes are split between digital ground and analog ground, the GND pins of the CS4384 should be connected to the analog ground plane.

D2D0

DSD_SCLK

DSDAx,

DSDBx

Not Used

BCKA

(128Fs)

BCKD (64Fs)

All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the DAC.

4.9.1 Capacitor Placement

Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceram ic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same layer as the DAC. If desired, all supply pins with similar voltage ratings may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin.

Note: All decoupling capacitors should be referenced to analog ground. The CDB4384 evaluation board demonstrates the optimum layout and power supply arrangements.

4.10 Analog Output and Filtering

The CS4384 does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry.

Figure 23 shows how the full-scale analog output level specification is derived. Figure 24 shows how the recommended outp ut filtering with location for optional mute circuit.

DS620F1 27

CS4384

4.175 V

AOUT

4.11 The MUTEC Outputs

The MUTEC1 and MUTEC234 pins have an auto-polarity detect feature. The MUTEC output pins are high impedance at the time of r eset. The exte rnal mute circ uitry needs to be self biased into an active state in order to be muted during reset. Upon release of reset, the CS438 4 will detect the status of the MUTEC pins (high or low) and will then select that state as the polarity to drive when the mutes become active. The external-bias voltage level that th e MUTEC pins see a t the time of rele ase of reset must m eet the “MUTEC auto detect input high/low voltage” specs as outlined in the Digital Characteristics section.

2.5 V

0.825 V

Full-Scale Output Level= AOUT= 3.35 Vpp

Figure 23. Full-Scale Output

Figure 24. Recommended Output Filter

Figure 25 shows a single example of both an a ctive high and an acti ve low mute dr ive circuit. In these de -

signs, the pull-up and pull-down resistors have been especially chosen to meet the input high/low th reshold when used with the MMUN2111 and MMUN2211 internal bias resistances of 10 kΩ.

Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.

28 DS620F1

Figure 25. Recommended Mute Circuitry

4.12 Recommended Power-Up Sequence

CS4384

4.12.1 Hardware Mode

1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in Section 4.1. In this state, the registers are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2. If RST

can not be held low long enough the SDINx pins should remain static low until all other clocks

are stable, and if possible the RST

2. Bring RST Hardware power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).

high. The device will remain in a low power state with FILT+ low and will initiate the

4.12.2 Software Mode

1. Hold RST low until the power supply is stable, and the master and left/right clocks are loc ked to the appropriate frequencies, as discussed in Section 4.1. In this state, the register s are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2.

2. Bring RST Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in QuadSpeed Mode).

3. In order to reduce the chances of clicks and pops, perform a write to the CP_EN bit prior to the completion of approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in DoubleSpeed Mode, and 2048 LRCK cycles in Quad-Speed Mode). The desired register settings can be loaded while keeping the PDN bit set to 1. Set the RMP_UP and RMP_DN bits to 1, then set the format and mode control bits to the desired settings.

high. The device will remain in a low power state with FILT+ low for 512 LRCK cycles in

should be toggled low again once the system is stable.

If more than the stated number of LRCK cycles passes before CPEN bit is written then the chip will enter Hardware Mode and begin to operate with the M0-M4 as the mode settings. CPEN bit may be written at anytime, even after the Hardware sequ e nc e ha s begu n. It is advised tha t if the CPEN bit can not be set in time then the SDINx pins should remain static low (this way no audio data can be

DS620F1 29

converted incorrectly by the Hardware Mode settings).

4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs.

4.13 Recommended Procedure for Switching Operational Modes

For systems where the absolute minimum in clicks and pops is required, it is reco mmended that the MUTE bits are set prior to changing significant D AC functions (s uch as chan ging sample ra tes or clock sou rces). The mute bits may then be released after clocks have settled and the proper modes have been set.

It is required to have the device held in reset if the minimum high/low time specs of MCLK can not be met during clock source changes.

4.14 Control Port Interface

The control port is used to load all the internal register settings in order to operate in Software Mode (see the “Parameter Definitions” on page 49 ). The operation of the contro l port may be completely asynch ronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required.

CS4384

The control port operates in one of two modes:

4.14.1 MAP Auto Increment

The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit (also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes of successive registers.

4.14.2 I²C Mode

In the I²C Mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial control port clock, SCL (see Figure 26 for the clock to data relationship). There is no CS ables the user to alter the chip address (001100[AD0][R/W quired, before powering up the device. If the device ever detects a high to low transition on the AD0/CS pin after power-up, SPI Mode will be selected.

4.14.2.1 I²C Write

To write to the device, follow the procedure below while adhering to the control port Switching Specifications in Section 2.

1. Initiate a START condition to the

001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth bit of the address byte is the R/W

2. Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This byte points to the register to be written.

3. Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to by the MAP.

4. If the INCR bit (see Section 4.14.1) is set to 1, repeat the previous step until all the desired registers are written, then initiate a STOP condition to the bus.

5. If the INCR bit is set to 0 and further a repeated START condition and follow the pro cedure detailed from step 1. If no further writes to other registers are desired, initiate a STOP condition to the bus.

I²C or SPI.

I²C writes or reads and

pin. Pin AD0 en-

]) and should be tied to VLC or GND as re-

I²C bus followed by the address byte. The upper 6 bits must be

bit.

I²C writes to other registers are desired, it is necessary to initiate

30 DS620F1

CS4384

4.14.2.2 I²C Read

To read from the device, follow the procedure below while adhering to the control port Switching Specifications.

1. Initiate a START condition to the

I²C bus followed by the address byte. The upper 6 bits must be

001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth bit of the address byte is the R/W

bit.

2. After transmitting an acknowledge (ACK), the device will then trans mit the contents of the register pointed to by the MAP. The MAP register will contain the address of the last register written to the MAP, or the default address (see Section 4.14.1) if an

I²C read is the first operation performed on the

device.

3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.

4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Continue providing a clock and issue an ACK after each byte un til all the de sired reg ister s are re ad, then initiate a STOP condition to the bus.

5. If the INCR bit is set to 0 and further a repeated START condition and follow the procedure detailed from steps 1 and 2 from the instructions followed by step 1 of the

I²C reads from other registers are desired, it is necessary to initiate

I²C Write

I²C Read section. If no further reads from other registers are de-

sired, initiate a STOP condition to the bus.

Note 1

SDA

SCL

Start

001100

ADDR AD0

R/W

ACK

DATA 1-8

ACK

DATA 1-8

ACK

Stop

Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.

4.14.3 SPI Mode

In SPI Mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK (see Figure 27 for the clock to data relationship). There is no AD0 pin. Pin CS is used to control SPI writes to the control port. When the device detects a high to low transition on the AD0/CS

pin after power-up, SPI Mode will be selected. All signals are inputs and data is clocked in on the

rising edge of CCLK.

4.14.3.1 SPI Write

To write to the device, follow the procedure below while adhe ring to the contr ol port Switching Spe cifications in Section 2.

1. Bring CS

2. The address byte on the CDIN pin must then be 00110000.

3. Write to the memory address pointer, MAP. This byte points to the register to be written.

4. Write the desired data to the register pointed to by the MAP.

5. If the INCR bit (see Section 4.14.1) is set to 1, repeat the previous step until all the desired registers are written, then bring CS

Figure 26. Control Port Timing, I²C Mode

is the chip select signal and

low.

high.

DS620F1 31

CS4384

6. If the INC R bit is set to 0 and furt her SPI writ es to other registers are desired, it is necessary to bring CS

high, and follow the procedure detailed from step 1. If no further writes to other registers are de-

sired, bring CS

high.

CCLK

CDIN

CHIP

ADDRESS

0011000

MAP = Memory Address Pointer

Figure 27. Control Port Timing, SPI Mode

R/W

MAP

MSB

byte 1

DATA

LSB

byte n

4.15 Memory Address Pointer (MAP)

76543210

INCR Reserved Reserved MAP4 MAP3 MAP2 MAP1 MAP0

00000000

4.15.1 INCR (Auto Map Increment Enable)

Default = ‘0’ 0 - Disabled 1 - Enabled

4.15.2 MAP4-0 (Memory Address Pointer)

Default = ‘00000’

32 DS620F1

CS4384

5. REGISTER QUICK REFERENCE

Addr Function 7 6 5 4 3 2 1 0

01h Chip Revision PART4 PART3 PART2 PART1 PART0 REV2 REV1 REV0

default 0 0 0 0 0 x x x

02h Mode Control CPEN FREEZE DSD/PCM

default 0 0 0 0 0 0 0 1

03h PCM Control DIF3 DIF 2 DIF1 DIF0 Reserved Reserved FM1 FM 0

default 0 0 0 0 0 0 1 1

04h DSD Control DSD_DIF2 DSD_DIF1 DSD_DIF0 DIR_DSD STATIC_DSDINVALID_DSDDSD_PM_MDDSD_PM_

default 0 0 0 0 1 0 0 0

05h Filter Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved FILT_SEL

default 0 0 0 0 0 0 0 0

06h Invert Control INV_B4 INV_A4 INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1

default 0 0 0 0 0 0 0 0

07h Group Control Reserved MUTEC Reserve d P1_A=B P2_A=B P3_A= B P4_A=B SNGLVOL

default 0 0 0 0 0 0 0 0

08h Ramp and Mute SZC1 SZC0 RMP_UP RMP_DN PAMUTE DAMUTE MUTE_P1 MUTE_P0

default 1 0 1 1 1 1 0 0

09h Mute Control MUTE_B4 MUTE_A4 MUTE_B3 MUTE_A3 MUTE_B2 MUTE_A2 MUTE_B1 MUTE_A1

default 0 0 0 0 0 0 0 0

0Ah Mixing Control

Pair 1 (AOUTx1)

default 0 0 0 0 1 0 0 1

0Bh Vol. Control A1 A1_VOL7 A1_VOL6 A1_VOL5 A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1 A1_VOL0

default 0 0 0 0 0 0 0 0

0Ch Vol. Control B1 B1_VOL7 B1_VOL6 B1_VOL5 B1_VOL4 B1_VOL3 B1_VOL2 B1_VOL1 B1_VOL0

default 0 0 0 0 0 0 0 0

0Dh Mixing Control

Pair 2 (AOUTx1)

default 0 0 0 0 1 0 0 1

0Eh Vol. Control A2 A2_VOL7 A2_VOL6 A2_VOL5 A2_VOL4 A2_VOL3 A2_VOL2 A2_VOL1 A2_VOL0

default 0 0 0 0 0 0 0 0

0Fh Vol. Control B2 B2_VOL7 B2_VOL6 B2_VOL5 B2_VOL4 B2_VOL3 B2_VOL2 B2_VOL1 B2_VOL0

default 0 0 0 0 0 0 0 0

10h Mixing Control

Pair 3 (AOUTx1)

default 0 0 0 0 1 0 0 1

11h Vol. Control A3 A3_VOL7 A3_ VOL6 A3_VOL5 A3_VOL4 A3_VOL3 A3_VOL2 A3_VOL1 A3_VOL0

default 0 0 0 0 0 0 0 0

12h Vol. Control B3 B3_VOL7 B3_VOL6 B3_VOL5 B3_VOL4 B3_VOL3 B3_VOL2 B3_VOL1 B3_VOL0

default 0 0 0 0 0 0 0 0

13h Mixing Control

Pair 4 (AOUTx1)

default 0 0 0 0 1 0 0 1

Reserved P1_DEM1 P1_DEM0 P1ATAPI4 P1ATAPI3 P1ATAPI2 P1ATAPI1 P1ATAPI0

Reserved P2_DEM1 P2_DEM0 P2ATAPI4 P2ATAPI3 P2ATAPI2 P2ATAPI1 P2ATAPI0

Reserved P3_DEM1 P3_DEM0 P3ATAPI4 P3ATAPI3 P3ATAPI2 P3ATAPI1 P3ATAPI0

Reserved P4_DEM1 P4_DEM0 P4ATAPI4 P4ATAPI3 P4ATAPI2 P4ATAPI1 P4ATAPI0

DAC4_DIS DAC3_DIS DAC2_DIS DAC1_DIS PDN

DS620F1 33

CS4384

Addr Function 7 6 5 4 3 2 1 0

14h Vol. Control A4 A4_VOL7 A4_VOL6 A4_VOL5 A4_VOL4 A4_VOL3 A4_VOL2 A4_VOL1 A4_VOL0

default00000000

15h Vol. Control B4 B4_VOL7 B4_VOL6 B4_VOL5 B4_VOL4 B4_VOL3 B4_VOL2 B4_VOL1 B4_VOL0

default00000000

16h PCM clock mode Reserved Reserved MCLKDIV Reserved Reserved Reserved Reserved Reserved

default00000000

34 DS620F1

CS4384

6. REGISTER DESCRIPTION

Note: All registers are read/write in I²C Mode and write only in SPI, unless otherwise noted.

6.1 Chip Revision (Address 01h)

76543210

PART4 PART3 PART2 PART1 PART0 REV2 REV1 REV0

00000- --

6.1.1 Part Number ID (PART) [R ead Only]

00000- CS4384

6.1.2 Revision ID (REV) [Read Only]

000 - Revision A0 001 - Revision B0

Function: This read-only register can be used to identify the model and revision number of the device.

6.2 Mode Control 1 (Address 02h)

76543210

CPEN FREEZE DSD/PCM

00000001

DAC4_DIS DAC3_DIS DAC2_DIS DAC1_DIS PDN

6.2.1 Control Port Enable (CPEN)

Default = 0 0 - Disabled 1 - Enabled

Function: This bit defaults to 0, allowing the device to power-up in Stand-Alone Mode. The Control Port Mode can

be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the registers and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user should write this bit within 10 ms following the release of Reset.

6.2.2 Freeze Controls (FREEZE)

Default = 0 0 - Disabled 1 - Enabled

Function: This function allows modifications to be made to the registers without the changes taking effect until the

FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneously, enable the FREEZE Bit, make all register changes, then Disable the FREEZE bit.

DS620F1 35

6.2.3 PCM/DSD Selection (DSD/PCM)

Default = 0 0 - PCM 1 - DSD

Function: This function selects DSD or PCM Mode. The appropriate data and clocks should be present before

changing modes, or else MUTE should be selected.

6.2.4 DAC Pair Disable (DACx_DIS)

Default = 0 0 - DAC Pair x Enabled 1 - DAC Pair x Disabled

Function: When the bit is set, the respective DAC channel pair (AOUTAx and AOUTBx) will remain in a reset state.

It is advised that changes to these bits be made while th e power-d own (PDN) bit is enabled to eliminate the possibility of audible artifacts.

Note: When the device is configured in TDM Mode by setting DIF[3:0] to 1100 (see Digital Interface

Format (DIF)), this function is not available and these bits must be set to 0 for proper op eration.

CS4384

6.2.5 Power Down (PDN)

Default = 1 0 - Disabled 1 - Enabled

Function: The entire device will enter a low-power state when this function is enabled, and the contents of the control

registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation in Control Port Mode can occur.

6.3 PCM Control (Address 03h)

76543210

DIF3 DIF2 DIF1 DIF0 Reserved Reserved FM1 FM0

00000011

6.3.1 Digital Interface Format (DIF)

Default = 0000 - Format 0 (Left Justified, up to 24-bit data ) Function: These bits select the interface format fo r the serial audio input. The DSD/PCM

PCM or DSD Mode is selected.

bit determines whether

The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 9-19.

Note: While in PCM Mode, the DIF bits should only be changed when the power-do wn (PDN) bit is set to ensure proper switching from one mode to another.

36 DS620F1

CS4384

DIF3 DIF2 DIF1 DIF0 DESCRIPTION Format FIGURE

0000 0001 0010 0011 0100 0101 1000 1001 1010 1011 1100 XXXX

Table 7. Digital Interface Formats - PCM Mode

6.3.2 Functional Mode (FM)

Default = 11 00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 200 kHz sample rates) 11 - Auto Speed Mode detect (32 kHz to 200 kHz sample rates)

Left Justified, up to 24-bit data I2S, up to 24-bit data Right Justified, 16-bit data Right Justified, 24-bit data Right Justified, 20-bit data Right Justified, 18-bit data One-line Mode 1, 24-bit Data +SDIN4 One-line Mode 2, 20-bit Data +SDIN4 One-line Mode 3, 24-bit 6-channel One-line Mode 4, 20-bit 6-channel TDM All other combinations are Reserved

0 9 1 10 2 11 3 12 4 13 5 14 8 15

9 16 10 17 11 18 12 19

Function: Selects the required range of input sample rates or Auto Speed Mode.

6.4 DSD Control (Address 04h)

765 4 3 2 1 0

DSD_DIF2 DSD_DIF1 DSD_DIF0 DIR_DSD STATIC_DSD INVALID_DSD DSD_PM_MD DSD_PM_EN

000 0 1 1 0 0

6.4.1 DSD Mode Digital Interface Format (DSD_DIF)

Default = 000 - Format 0 (64x oversampled DSD data with a 4x MCLK to DSD data rate) Function: The relationship between the oversampling ratio of the DSD audio data and the required Master clock to

DSD data rate is defined by the Digital Interface Format pins. The DSD/PCM

DIF2 DIF1 DIFO DESCRIPTION

0 0 0 64x oversampled DSD data with a 4x MCLK to DSD data rate 0 0 1 64x oversampled DSD data with a 6x MCLK to DSD data rate 0 1 0 64x oversampled DSD data with a 8x MCLK to DSD data rate 0 1 1 64x oversamp l e d DSD data with a 12x MCLK to DSD data rate 1 0 0 128x oversampled DSD data with a 2x MCLK to DSD data rate. 1 0 1 128x oversampled DSD data with a 3x MCLK to DSD data rate. 1 1 0 128x oversampled DSD data with a 4x MCLK to DSD data rate. 1 1 1 128x oversampled DSD data with a 6x MCLK to DSD data rate.

bit determines whether PCM or DSD Mode is selected.

T able 8. Digital Interface Formats - DSD Mode

DS620F1 37

6.4.2 Direct DSD Conversion (DIR_DSD)

Function: When set to 0 (default), DSD input data is sent to the DSD processor for filtering and volume control fu nc-

tions. When set to 1, DSD input data is sent directly to the switched capacitor DACs for a pure DSD conversion.

In this mode, the full-scale DSD and PCM levels will not be matched (see Section 2), the dynamic range performance may be reduced, the volume control is inactive, and the 50 kHz low-pass filter is not available (see Section 2 for filter specifications).

6.4.3 Static DSD Detect (STATIC_DSD)

Function: When set to 1 (default), the DSD processor che cks for 28 consecutive zeroes or ones and, if detected,

sends a mute signal to the DACs. The MUTEC pins will eventually go active according to the DAMUTE register.

When set to 0, this function is disabled.

6.4.4 Invalid DSD Detect (INVALID_DSD)

CS4384

Function: When set to 1, the DSD processor checks for greater than 24 out of 28 bits of the same value and, if de-

tected, will attenuate the data sent to the DACs. The MUTEC pins go active according to the DAMUTE register.

When set to 0 (default), this function is disabled.

6.4.5 DSD Phase Modulation Mode Select (DSD_PM_MODE)

Function: When set to 0 (default), the 128Fs (BCKA) clock should be input to DSD_SCLK for Phase Modulation

Mode. (See Figure 20 on page 25.) When set to 1, the 64Fs (BCKD) clock should be input to DSD_SCLK for Phase Modulation Mode.

6.4.6 DSD Phase Modulation Mode Enable (DSD_PM_EN)

Function: When set to 1, DSD Phase Modulation Input Mod e is enable d and the DSD_PM_MODE bit should be set

accordingly. When set to 0 (default), this function is disabled (DSD normal mode).

38 DS620F1

CS4384

6.5 Filter Control (Address 05h)

76543210

Reserved Reserved Reserved Reserved Reserved Reserved Reserved FILT_SEL

00000000

6.5.1 Interpolation Filter Select (FILT_SEL)

Function: When set to 0 (default), the Interpolation Filter has a fast roll off. When set to 1, the Interpolation Filter has a slow roll off.

The specifications for each filter can be found in the Analog characteristics table, and re sponse plots can be found in Figures 26 to 49.

6.6 Invert Control (Address 06h)

76543210

INV_B4 INV_A4 INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1

00000000

6.6.1 Invert Signal Polarity (INV_xx)

Function: When set to 1, this bit inverts the signal polarity of channel xx. When set to 0 (default), this function is disabled.

6.7 Group Control (Address 07h)

76543210

Reserved MUTEC Reserved P1_A=B P2_A=B P3_A=B P4_A=B SNGLVOL

00000000

6.7.1 Mutec Pin Control (MUTEC)

Default = 0

0 - Two Mute control signals 1 - Single mute control signal on MUTEC1

Function: Selects how the internal mute signals are routed to the MUTEC1 and MUTEC234 pins. When set to ‘0’,

a logical AND of DAC pair 1 mute control signals are output on MUTEC1 and a logical AND of the mute control signals of DAC pairs 2, 3, and 4 are output on MUTEC234. When set to ‘1’, a logical AND of all DAC pair mute control signals is output on the MUTEC1 pin, MUTEC234 will remain static. For more information on the use of the mute control function see the MUTEC1 and MUTEC234 p ins in Section 4.11.

6.7.2 Channel A Volume = Channel B Volume (Px_A=B)

Default = 0

0 - Disabled 1 - Enabled

Function:

DS620F1 39

CS4384

The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are determined by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes are ignored when this function is enabled.

6.7.3 Single Volume Control (SNGLVOL)

Default = 0

0 - Disabled 1 - Enabled

Function: The individual channel volume levels are independently controlled by their respective Volume Control

Bytes when this function is disabled. The volume on all channels is determined by the A1 Channel Volume Control Byte, and the other Volume Control Bytes are ignored when this function is enabled.

6.8 Ramp and Mute (Address 08h)

76543210

SZC1 SZC0 RMP_UP RMP_DN PAMUTE DAMUTE MUTE_P1 MUTE_P0

10111100

6.8.1 Soft Ramp and Zero Cross Control (SZC)

Default = 10

00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings

Function: Immediate When Immediate Change is selected all level changes will take effect immediately in one step. Zero Cross Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur

on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and impl emented for each channel.

Soft Ramp Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-

ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Soft Ramp on Zero Crossing Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or

muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.

Change

40 DS620F1

6.8.2 Soft Volume Ramp-Up After Error (RMP_UP)

Function: An un-mute will be performed after executing an LRCK/MCLK ratio change or error, and after changing

the Functional Mode. When set to 1 (default), this un-mute is effected, similar to attenuation changes, by the Soft and Zero

Cross bits in the Volume and Mixing Control register. When set to 0, an immediate un-mute is performed in these instances. Note: For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.

6.8.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN)

Function: If either the FILT_SEL or DEM bits are changed the DAC will stop conversion for a period of time to

change its filter values. This bit selects how the data is effected prior to and after the change of the filter values.

When set to 1 (default), a mute will be performed prior to executing a filter mode change and an un-mute will be performed after executing the filter mode change. This mute and un-mute are effected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register.

CS4384

When set to 0, an immediate mute is performed prior to executing a filter mode change. Note: For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.

6.8.4 PCM Auto-Mute (PAMUTE)

Function: When set to 1 (default) the Digital-to-Analog converter output will mute following the reception of 8192

consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period.

When set to 0 this function is disabled.

6.8.5 DSD Auto-Mute (DAMUTE)

Function: When set to 1 (default) the Digital-to-Analog converter output will mute following the reception of 256 re-

peated 8-bit DSD mute patterns (as defined in the SACD specification).

A single bit not fitting the repeated mute pattern (mentioned above) will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period.

6.8.6 MUTE Polarity and DETECT (MUTEP1:0)

Default = 00 00 - Auto polarity detect, selected from MUTEC1 pin 01 - Reserved 10 - Active low mute polarity 11 - Active high mute polarity

DS620F1 41

Function: Auto mute polarity detect (00) See Section 4.11 on page 28 for the description. Active low mute polarity (10)

CS4384

When RST released and after this bit is set, the MUTEC output pins will be active low polarity.

Active high mute polarity (11) At reset time the outputs are high impedance and will need to be biased active. Once reset has been re-

leased and after this bit is set, the MUTEC output pins will be active high polarity.

is low the outputs are high impedance and will need to be biased active. Once reset has been

6.9 Mute Control (Address 09h)

76543210

MUTE_B4 MUTE_A4 MUTE_B3 MUTE_A3 MUTE_B2 MUTE_A2 MUTE_B1 MUTE_A1

00000000

6.9.1 Mute (MUTE_xx)

Default = 0 0 - Disabled 1 - Enabled

Function: The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output will

be retained. The muting function is affected, similarly to attenuation changes, by the Soft and Zero Cross bits. The MUTE pins will go active during the mute period according to the MUTEC bit.

6.10 Mixing Control (Address 0Ah, 0Dh, 10h, 13h)

76543210

Reserved Px_DEM1 Px_DEM0 PxATAPI4 PxATAPI3 PxATAPI2 PxATAPI1 PxATAPI0

00001001

6.10.1 De-Emphasis Control (PX_DEM1:0)

Default = 00 00 - Disabled 01 - 44.1 kHz 10 - 48 kHz 11 - 32 kHz

Function: Selects the appropriate digital filte r to maintain the standard 15 µs/50 µs digital de-emphasis filter re-

sponse at 32, 44.1 or 48 kHz sample rates. (Figure 20 on page 25) De-emphasis is only available in Single-Speed Mode.

42 DS620F1

CS4384

6.10.2 ATAPI Channel Mixing and Muting (ATAPI)

Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo) Function: The CS4384 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI

functions are applied per A-B pair. Refer to Table 9 and Figure 21 for additional information.

ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTAx AOUTBx

0 0 0 0 0 MUTE MUTE 00001 MUTE bR 00010 MUTE bL 00011 MUTE b[(L+R)/2] 00100 aR MUTE 00101 aR bR 00110 aR bL 00111 aR b[(L+R)/2] 01000 aL MUTE 01001 aL bR 01010 aL bL 01011 aL b[(L+R)/2] 0 1 1 0 0 a[(L+R)/2] MUTE 01101 a[(L+R)/2] bR 01110 a[(L+R)/2] bL 0 1 1 1 1 a[(L+R)/2] b[(L+R)/2] 1 0 0 0 0 MUTE MUTE 10001 MUTE bR 10010 MUTE bL 1 0 0 1 1 MUTE [(bL+aR)/2] 10100 aR MUTE 10101 aR bR 10110 aR bL 1 0 1 1 1 aR [(aL+bR)/2] 11000 aL MUTE 11001 aL bR 11010 aL bL 1 1 0 1 1 aL [(aL+bR)/2] 1 1 1 0 0 [(aL+bR)/2] MUTE 1 1 1 0 1 [(aL+bR)/2] bR 1 1 1 1 0 [(bL+aR)/2] bL 1 1 1 1 1 [(aL+bR)/2] [(aL+bR)/2]

Table 9. ATAPI Decode

DS620F1 43

CS4384

6.11 Volume Control (Address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h, 14h, 15h)

76543210

xx_VOL7 xx_VOL6 xx_VOL5 xx_VOL4 xx_VOL3 xx_VOL2 xx_VOL1 xx_VOL0

00000000

These eight registers provide individual volume and mute control for each of the eight channels. The values for “xx” in the bit fields above are as follows: Register address 0Bh - xx = A1 Register address 0Ch - xx = B1 Register address 0Eh - xx = A2 Register address 0Fh - xx = B2 Register address 11h - xx = A3 Register address 12h - xx = B3 Register address 14h - xx = A4 Register address 15h - xx = B4

6.11.1 Digital Volume Control (xx_VOL7:0)

Default = 00h (0 dB) Function: The Digital Volume Control registers allow independent control of the signal levels in 1/2 dB increments

from 0 to -127.5 dB. Volume settings are de coded as shown in Table 10. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. Note that the values in the volume setting column in Table 10 are approximate. The actual attenuation is determined by taking the decimal value of the volume register and multiplying by 6.02/12.

Binary Code Decimal Value Volume Setting

00000000 0 0 dB 00000001 1 -0.5 dB 00000110 6 -3.0 dB

11111111 255 -127.5 dB

T able 10. Example Digital Volume Settings

6.12 PCM Clock Mode (Address 16h)

76543210

Reserved Reserved MCLKDIV Reserved Reserved Reserved Reserved Reserved

00000000

6.12.1 Master Clock Divide by 2 Enable (MCLKDIV)

Function: When set to 1, the MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2

prior to all other internal circuitry. When set to 0 (default), MCLK is unchanged.

44 DS620F1

7. FILTER RESPONSE PLOTS

CS4384

−20

−40

−60

Amplitude (dB)

−80

−100

−120

0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency(normalized to Fs)

−20

−40

−60

Amplitude (dB)

−80

−100

−120

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6

Frequency(normalized to Fs)

Figure 28. Single-Speed (fast) Stopband Rejection Figure 29. Single-Speed (fast) Transition Band

−1

−2

−3

−4

−5

Amplitude (dB)

−6

−7

−8

−9

−10

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency(normalized to Fs)

0.02

0.015

0.01

0.005

Amplitude (dB)

−0.005

−0.01

−0.015

−0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Frequency(normalized to Fs)

Figure 30. Single-Speed (fast) Transition Band (detail) Figure 31. Single-Speed (fast) Passband Ripple

−20

−40

−60

Amplitude (dB)

−80

−100

−120

0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency(normalized to Fs)

−20

−40

−60

Amplitude (dB)

−80

−100

−120

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6

Frequency(normalized to Fs)

Figure 32. Single-Speed (slow) Stopband Rejection Figure 33. Single-Speed (slow) Transition Band

DS620F1 45

CS4384

−1

−2

−3

−4

−5

Amplitude (dB)

−6

−7

−8

−9

−10

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency(normalized to Fs)

Figure 34. Single-Speed (slow) Transition Band (detail) F i gure 35. Single-Speed (slow) Passband Ripple

0.02

0.015

0.01

0.005

Amplitude (dB)

−0.005

−0.01

−0.015

−0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Frequency(normalized to Fs)

Amplitude (dB)

100

120

0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency(normalized to Fs)

Amplitude (dB)

100

120

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6

Frequency(normalized to Fs)

Figure 36. Double-Speed (fast) Stopband Rejection Figure 37. Double-Speed (fast) Transition Band

Amplitude (dB)

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency(normalized to Fs)

0.02

0.015

0.01

0.005

Amplitude (dB)

0.005

0.01

0.015

0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Frequency(normalized to Fs)

Figure 38. Double-Speed (fast) Transition Band (detail) Figure 39. Double-Speed (fast) Passband Ripple

46 DS620F1

CS4384

Amplitude (dB)

100

120

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency(normalized to Fs)

Amplitude (dB)

100

120

0.2 0.3 0.4 0.5 0.6 0.7 0.8

Frequency(normalized to Fs)

Figure 40. Double-Speed (slow) Stopband Rejection Figure 41. Double-Speed (slow) Transition Band

Amplitude (dB)

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency(normalized to Fs)

0.02

0.015

0.01

0.005

Amplitude (dB)

0.005

0.01

0.015

0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35

Frequency(normalized to Fs)

Figure 42. Double-Speed (slow) Transition Band (detail) Figure 43. Double-Speed (slow) Passband Ripple

Amplitude (dB)

100

120

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency(normalized to Fs)

Amplitude (dB)

100

120

0.2 0.3 0.4 0.5 0.6 0.7 0.8

Frequency(normalized to Fs)

Figure 44. Quad-Speed (fast) Stopband Rejection Figure 45. Quad-Speed (fast) Transition Band

DS620F1 47

CS4384

Amplitude (dB)

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency(normalized to Fs)

0.2

0.15

0.1

0.05

Amplitude (dB)

0.05

0.1

0.15

0.2 0 0.05 0.1 0.15 0.2 0.25

Frequency(normalized to Fs)

Figure 46. Quad-Speed (fast) Transition Band (detail) Figure 47. Quad-Speed (fast) Passband Ripple

Amplitude (dB)

100

120

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency(normalized to Fs)

100

120

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Frequency(normalized to Fs)

Figure 48. Quad-Speed (slow) Stopband Rejection F igure 49. Quad-Speed (slow) Transition Band

Amplitude (dB)

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency(normalized to Fs)

0.02

0.015

0.01

0.005

Amplitude (dB)

0.005

0.01

0.015

0.02 0 0.02 0.04 0.06 0.08 0.1 0.12

Frequency(normalized to Fs)

Figure 50. Quad-Speed (slow) Transition Band (detail) Figure 51. Quad-Speed (slow) Passband Ripple

48 DS620F1

CS4384

8. REFERENCES

1. How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters, by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.

2. CDB4364 data sheet, available at http://www.cirrus.com.

3. Design Notes for a 2-Pole Filter with Differential Input, by Steven Green. Cirrus Logic Application Note AN48

4. The

5. AN282 “The 2-Channel Serial Audio Interface: A Tutorial”

I²C-Bus Specification: Version 2.0, Philips Semiconductors, December 1998.

http://www.semiconductors.philips.com

9. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the spec ified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise le vel and do not affect the measurement. This measurement technique has bee n accepted by the Audio En gineering Society, AES171991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the conver ter's output with all zeros to the input under test and a full- scale signal applied to the other channel. Units in decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full-scale analog output for a full-scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

DS620F1 49

10.PACKAGE DIMENSIONS 48L LQFP PACKAGE DRAWING

CS4384

∝

INCHES MILLIMETERS

DIM MIN NOM MAX MIN NOM MAX

A --- 0.055 0.063 --- 1.40 1.60

A1 0.002 0.004 0.006 0.05 0.10 0.15

B 0.007 0.009 0.011 0.17 0.22 0.27

D 0.343 0.354 0.366 8.70 9.0 BSC 9.30

D1 0.272 0.28 0.280 6.90 7.0 BSC 7.10

E 0.343 0.354 0.366 8.70 9.0 BSC 9.30

E1 0.272 0.28 0.280 6.90 7.0 BSC 7.10

e* 0.016 0.020 0 .0 24 0.40 0.50 BSC 0.60

L 0.018 0.24 0.030 0.45 0.60 0.75

∝

0.000° 4° 7.000° 0.00° 4° 7.00°

* Nominal pin pitch is 0.50 mm

Controlling dimension is mm.

JEDEC Designation: MS022

50 DS620F1

CS4384

11.ORDERING INFORMATION

Product Description Package Pb-Free Grade Temp Range Container Order #

CS4384

114 dB, 192 kHz 8-

channel D/A Converter

48-pin LQFP

YES Commercial -40° to +85° C

CDB4384 CS4384 Evaluation Board - - - - CDB4384

Tray CS4384-CQZ

Tape & Reel CS4384-CQZR

12.REVISION HISTORY

Release Changes

A1 Initial Release

Corrected DAC Pair Disable register de scri p ti o n in “DAC Pair Disable (DACx_DIS)” on page 36 Added note to Digital Interface Format register description in “Digital Interface Format (DIF)” on page 36 Removed Automotive Grade Added PCM mode format changeable in reset only to “Mode Select” on page 21

Updated ambient operating temperature range for commercial grade Updated Full Scale Differential Output Voltage in “DAC Analog Characteristics” on page 9 Updated VD power supply current and package thermal resistance in Power and Thermal Characteristics Updated “Digital Characteristics” on page 13 Updated Legal Information under “IMPORTANT NOTICE” on page 51

Contacting Cirrus Logic Support

For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com.

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the informati on contained in this document is accurate and reliable. However, the information is su bject to change without notice and is provided "AS IS" wit hout warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgm ent, including thos e pertaining to warranty, ind emnification, and li mitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this inform atio n, Cirrus gran ts no license , express or implied un der an y patents, mask wor k rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use with in your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMI CO NDUCT OR PRODUCT S MAY INVO LVE POT ENTI AL RI SKS OF DEATH, PERS ONAL IN JU RY, OR SEVE RE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs a re trade ma rks of Cirrus Lo gic, Inc. All othe r brand an d p roduc t names in this docum en t may be trad em arks or service marks of their respective owners.

I²C is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. Direct Stream Digital is a registered trademark of Sony Kabushiki Kaisha TA Sony Corporation. DSD is a trademark of Sony Kabushiki Kaish a TA So ny Co rporation.

DS620F1 51

CS4384

52 DS620F1

Cirrus Logic CS4384 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. PIN DESCRIPTION

2. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

DAC ANALOG CHARACTERISTICS

POWER AND THERMAL CHARACTERISTICS

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE

DIGITAL CHARACTERISTICS

SWITCHING CHARACTERISTICS - PCM

Figure 1. Serial Audio Interface Timing Figure 2. TDM Serial Audio Interface Timing

SWITCHING CHARACTERISTICS - DSD

Figure 3. Direct Stream Digital - Serial Audio Input Timing

Figure 4. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT

Figure 6. Control Port Timing - SPI Fo rmat

3. TYPICAL CONNECTION DIAGRAM

Figure 7. Typical Connection Diagram, Software Mode

Figure 8. Typical Connection Diagram, Hardware Mode

4. APPLICATIONS

4.1 Master Clock

Table 1. Single-Speed Mode Standard Frequencies

Table 2. Double-Speed Mode Standard Frequencies

Table 3. Quad-Speed Mode Standard Frequencies

4.2 Mode Select

Table 4. PCM Digital Interface Format, Hardware Mode Options

Table 5. Mode Selection, Hardware Mode Options

Table 6. Direct Stre am Digital (DSD), Hardware Mode Options

4.3 Digital Interface Formats

Figure 9. Format 0 - Left-Justified up to 24-bit Data

Figure 11. Format 2 - Right-Justified 16-bit Data

Figure 12. Format 3 - Right-Justified 24-bit Data

Figure 13. Format 4 - Right-Justified 20-bit Data

4.3.1 OLM #1

Figure 14. Format 5 - Right-Justified 18-bit Data

4.3.2 OLM #2

Figure 15. Format 8 - One Line Mode 1

Figure 16. Format 9 - One Line Mode 2

4.3.3 OLM #3

4.3.4 OLM #4

Figure 17. Format 10 - One Line Mode 3

Figure 18. Format 11 - One Line Mode 4

4.3.5 TDM

Figure 19. Format 12 - TDM Mode

4.4 Oversampling Modes

4.5 Interpolation Filter

4.6 De-Emphasis

Figure 20. De-Emphasis Curve

4.7 ATAPI Specification

Figure 21. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4)

4.8 Direct Stream Digital (DSD) Mode

Figure 22. DSD Phase Modulation Mode Diagram

4.9 Grounding and Power Supply Arrangements

4.9.1 Capacitor Placement

4.10 Analog Output and Filtering

4.11 The MUTEC Outputs

Figure 23. Full-Scale Output

Figure 24. Recommended Output Filter

Figure 25. Recommended Mute Circuitry

4.12 Recommended Power-Up Sequence

4.12.1 Hardware Mode

4.12.2 Software Mode

4.13 Recommended Procedure for Switching Operational Modes

4.14 Control Port Interface

4.14.1 MAP Auto Increment

4.14.3 SPI Mode

Figure 27. Control Port Timing, SPI Mode

4.15 Memory Address Pointer (MAP)

4.15.1 INCR (Auto Map Increment Enable)

4.15.2 MAP4-0 (Memory Address Pointer)

5. REGISTER QUICK REFERENCE

6. REGISTER DESCRIPTION

6.1 Chip Revision (Address 01h)

6.1.1 Part Number ID (PART) [R ead Only]

6.1.2 Revision ID (REV) [Read Only]