Cirrus Logic CS4364 User Manual

CS4364

103 dB, 192 kHz 6-Channel D/A Converter

Features

 Advanced Multi-bit Delta Sigma Architecture  24-bit Conversion  Automatic Detection of Sample Rates up to

192 kHz

 103 dB Dynamic Range  -88 dB THD+N  Single-Ended Output Architecture  Direct Stream Digital

(DSD

– Non-Decimating Volume Control – On-Chip 50 kHz Filter – Matched PCM and DSD Analog Ou tput

Levels

 Selectable Digital Filters  Volume Control with 1/2-dB Step Size and Soft

Ramp

 Low Clock-Jitter Sensitivity  +5 V Analog Supply, +2.5 V Digital Supply  Separate 1.8 to 5 V Logic Supplies for the

Control and Serial Ports

™)

Mode

Description

The CS4364 is a complete 6-channel digital-to-analog system. This D/A system includes digital de-emphasis, half-dB step size volume control, ATAPI channel mixing, selectable fast and slow digital interpolation filters followed by an oversampled, multi-bit delta sigma modulator which includes mismatch shaping technology that eliminates distortion due to capacitor mismatch. Following this stage is a multi-element switched capacitor stage and low-pass filter with single-ended analog outputs.

The CS4364 also has a proprietary DSD processor which allows for volume control and 50 kHz on-chip filtering without an intermediate decimation stage. It also offers an optional path for direct DSD conve r sion by directly using the multi-element switched capacitor array.

The CS4364 accepts PCM data at sample rates from 4 kHz to 216 kHz, DSD audio data, and delivers excellent sound quality. These featu res are ideal for multichannel audio systems including SACD players, A/V receivers, digital TV’s, mixing consoles, effects processors, and sound cards.

This product is available in 48-pin LQFP package in Commercial (-40°C to +85°C) temperature grade. See

“Ordering Information” on page 4 9 for complete details.

Control Port Supply = 1.8 V to 5 V

Hardware Mode or

C/SPI Software Mode

Control Data

Reset

Serial Audio Port Supply = 1.8 V to 5 V

PCM Serial Audio Input

DSD Audio

Input

http://www.cirrus.com

Level Translator

Configuration

Volume

Controls

DSD Processor

-Volume control

Serial Interface

-50 kHz filter

Digital Supply = 2.5 V

Digital Filters

Multi-bit ∆Σ Modulators

Analog Supply = 5 V

Internal Voltage

Reference

Switch-Cap

DAC and

Analog Filters

Extern al Mute

Control

Six Channels of Single-Ended Outputs

Mute S i gnals

MAY '08

DS619F1

TABLE OF CONTENTS

1. PIN DESCRIPTION................................................................................................................................. 6

2. CHARACTERISTICS AND SPECIFICATIONS...................................................................................... 8

RECOMMENDED OPERATING CONDITIONS .......................................................................................... 8

ABSOLUTE MAXIMUM RATINGS............................................................................................................... 8

DAC ANALOG CHARACTERISTICS........................................................................................................... 9

POWER AND THERMAL CHARACTERISTICS........................................................................................ 10

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE............................................ 11

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE............................................ 12

DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE ..................................................12

DIGITAL CHARACTERISTICS ............... ... ... ... ... .... ... ... ... .... ... ... ... .... ......................................... .... ............ 13

SWITCHING CHARACTERISTICS - PCM ................................................................................................ 14

SWITCHING CHARACTERISTICS - DSD.................................................................................................15

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT.................................................... 16

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT....................... ... ... ... ... .... ... ... ... ... 17

3. TYPICAL CONNECTION DIAGRAM .............................................................................................. 18

4. APPLICATIONS ................................................................................................................................... 20

4.1 Master Clock.................................................................................................................................. 20

4.2 Mode Select.................................................................................................................................. 21

4.3 Digital Interface Formats ............................................................................................................... 22

4.3.1 OLM #1 ................................................................................................................................ 23

4.3.2 OLM #2 ................................................................................................................................ 23

4.4 Oversampling Modes..................................................................................................................... 23

4.5 Interpolation Filter.......................................................................................................................... 24

4.6 De-Emphasis................................................................................................................................. 24

4.7 ATAPI Specification....................................................................................................................... 25

4.8 Direct Stream Digital (DSD) Mode. ... ... ... .... ... .......................................... ... ... .... ... ... ... ... .... ... ......... 25

4.9 Grounding and Power Supply Arrangements................................................................................ 26

4.9.1 Capacitor Placement............................................................................................................ 26

4.10 Analog Output and Filtering...................... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... ................ 26

4.11 The MUTEC Outputs................................................ ... ... .... ... .......................................... ............ 27

4.12 Recommended Power-Up Sequence.......................................................................................... 28

4.12.1 Hardware Mode............................................................... ... ... .... ... ...................................... 28

4.12.2 Software Mode...................................................... .... ... ... ... ................................................ 28

4.13 Recommended Procedure for Switching Operational Modes...................................................... 29

4.14 Control Port Interface .................................................................................................................. 29

4.14.1 MAP Auto Increment.......................................................................................................... 29

4.14.2 I²C Mode ................................................................... ... ... ... ... .... ......................................... 29

4.14.3 SPI Mode ........................................................................... ... .... ... ...................................... 30

4.15 Memory Address Pointer (MAP)................................................................................................. 31

4.15.1 INCR (Auto Map Increment Enable) .................................................................................. 31

4.15.2 MAP4-0 (Memory Address Pointer) ................................................................................... 31

5. REGISTER QUICK REFERENCE ....................................................................................................... 32

6. REGISTER DESCRIPTION .................................................................................................................. 33

6.1 Chip Revision (Address 01h)................................................................................................

6.1.1 Part Number ID (PART) [Read Only] ......... .... ... ... ... .... ......................................... ................ 33

6.1.2 Revision ID (REV) [Read Only]............................................................................................ 33

6.2 Mode Control 1 (Address 02h) ...................................................................................................... 33

6.2.1 Control Port Enable (CPEN) ................................................................................................33

6.2.2 Freeze Controls (FREEZE)..................................................................................................33

6.2.3 PCM/DSD Selection (DSD/PCM)......................................................................................... 34

6.2.4 DAC Pair Disable (DACx_DIS) ............................................................................................ 34

6.2.5 Power Down (PDN).............................................................................................................. 34

CS4364

......... 33

2 DS619F1

CS4364

6.3 PCM Control (Address 03h) .......................................................................................................... 34

6.3.1 Digital Interface Format (DIF)........ .... ... ... ... .... ... .......................................... ... ... ... .... ............ 34

6.3.2 Functional Mode (FM).......................................................................................................... 35

6.4 DSD Control (Address 04h)........... .......................................... ... .......................................... ......... 35

6.4.1 DSD Mode Digital Interface Format (DSD_DIF) .................................................................. 35

6.4.2 Direct DSD Conversion (DIR_DSD)........ ... .... ... ... ... .... ... .......................................... ... ......... 36

6.4.3 Static DSD Detect (STATIC_DSD) ...................................................................................... 36

6.4.4 Invalid DSD Detect (INVALID_DSD).................................................................................... 36

6.4.5 DSD Phase Modulation Mode Select (DSD_PM_MODE).................................................... 36

6.4.6 DSD Phase Modulation Mode Enable (DSD_PM_EN) ........................................................ 36

6.5 Filter Control (Address 05h) .......................................................................................................... 37

6.5.1 Interpolation Filter Select (FILT_SEL).................................................................................. 37

6.6 Invert Control (Address 06h) ................................................... ... ... ... .... ... ... ... .... ............................ 37

6.6.1 Invert Signal Polarity (INV_xx) ... ... .... ... ....................................... ... ... ... .... ... ... ... ... ................ 37

6.7 Group Control (Address 07h) ........................................................................................................ 37

6.7.1 Mute Pin Control (MUTEC1, MUTEC0) ............................................................................... 37

6.7.2 Channel A Volume = Channel B Volume (Px_A=B)............................................................. 37

6.7.3 Single Volume Control (SNGLVOL)..................................................................................... 38

6.8 Ramp and Mute (Address 08h) ..................................................................................................... 38

6.8.1 Soft Ramp and Zero Cross Control (SZC) ........................................................................... 38

6.8.2 Soft Volume Ramp-Up After Error (RMP_UP) ..................................................................... 39

6.8.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN)................................................... 39

6.8.4 PCM Auto-Mute (PAMUTE)................................................................................................. 39

6.8.5 DSD Auto-Mute (DAMUTE) ................................................................................................. 39

6.8.6 MUTE Polarity and DETECT (MUTEP1:0)..... ...................................................................... 40

6.9 Mute Control (Address 09h) .......................................................................................................... 40

6.9.1 Mute (MUTE_xx)........................................ .... ... ... ... ....................................... ... ... .... ... ......... 40

6.10 Mixing Control (Address 0Ah, 0Dh, 10h, 13h) ............. ... .... ... ... ................................................... 40

6.10.1 De-Emphasis Control (PX_DEM1:0).................................................................................. 40

6.10.2 ATAPI Channel Mixing and Muting (ATAPI) ...................................................................... 41

6.11 Volume Control (Address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h)........................................................... 42

6.11.1 Digital Volume Control (xx_VOL7:0) .................................................................................. 42

6.12 PCM Clock Mode (Address 16h)................................................................................................. 42

6.12.1 Master Clock Divide by 2 Enable (MCLKDIV).................................................................... 42

7. FILTER RESPONSE PLOTS ............................................................................................................... 43

8. REFERENCES...................................................................................................................................... 47

9. PARAMETER DEFINITIONS................................................................................................................ 47

10. PACKAGE DIMENSIONS ............................................................. .......................................... ......... .. 48

11. ORDERING INFORMATION ......................................................... ... ... ... ............................................ 49

12. REVISION HISTORY .................................................... ... ... ... .... ... ................................................... .. 50

DS619F1 3

LIST OF FIGURES

Figure 1. Serial Audio Interface Timing...................................................................................................... 14

Figure 2. Direct Stream Digital - Serial Audio Input Timing........................................................................ 15

Figure 3. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode........................... 15

Figure 4. Control Port Timing - I²C Format................................................................................................. 16

Figure 5. Control Port Timing - SPI Format................................................................................................ 17

Figure 6. Typical Connection Diagram, Software Mode.............................................................................18

Figure 7. Typical Connection Diagram, Hardware Mode........................ ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 19

Figure 8. Format 0 - Left-Justified up to 24-bit Data .................................................................................. 22

Figure 9. Format 1 - I²S up to 24-bit Data .................................................................................................. 22

Figure 10. Format 2 - Right-Justified 16-bit Data....................................................................................... 22

Figure 11. Format 3 - Right-Justified 24-bit Data....................................................................................... 22

Figure 12. Format 4 - Right-Justified 20-bit Data....................................................................................... 22

Figure 13. Format 5 - Right-Justified 18-bit Data....................................................................................... 23

Figure 14. Format 8 - One Line Mode 1..................................................................................................... 23

Figure 15. Format 9 - One Line Mode 2..................................................................................................... 23

Figure 16. De-Emphasis Curve.................................................................................................................. 24

Figure 17. ATAPI Block Diagram (x = channel pair 1, 2, or 3) ................................................................... 25

Figure 18. DSD Phase Modulation Mode Diagram....................................................................................26

Figure 19. Full-Scale Output...................................................................................................................... 27

Figure 20. Recommended Output Filter..................................................................................................... 27

Figure 21. Recommended Mute Circuitry .................................................................................................. 28

Figure 22. Control Port Timing, I²C Mode.................................. ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ............ 30

Figure 23. Control Port Timing, SPI Mode................................. ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ............ 31

Figure 24. Single-Speed (fast) Stopband Rejection................................................................................... 43

Figure 25. Single-Speed (fast) Transition Band......................................................................................... 43

Figure 26. Single-Speed (fast) Transition Band (detail)............................................................................. 43

Figure 27. Single-Speed (fast) Passband Ripple.................................................... ... .... ... ... ... ... ................ 43

Figure 28. Single-Speed (slow) Stopband Rejection .............................................................. ... .... ... ... ...... 43

Figure 29. Single-Speed (slow) Transition Band........................................................................................ 43

Figure 30. Single-Speed (slow) Transition Band (detail)............................................................................ 44

Figure 31. Single-Speed (slow) Passband Ripple...................................................................................... 44

Figure 32. Double-Speed (fast) Stopband Rejection ................................................................................. 44

Figure 33. Double-Speed (fast) Transition Band........................................................................................ 44

Figure 34. Double-Speed (fast) Transition Band (detail)............................................................................ 44

Figure 35. Double-Speed (fast) Passband Ripple...................................................................................... 44

Figure 36. Double-Speed (slow) Stopband Rejection................................................................................ 45

Figure 37. Double-Speed (slow) Transition Band................................ ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... . ..... 45

Figure 38. Double-Speed (slow) Transition Band (detail)................................. ... ... ... .... ... ... ... ... .... ... ... ... ... 45

Figure 39. Double-Speed (slow) Passband Ripple.................................................................................

Figure 40. Quad-Speed (fast) Stopband Rejection....................................... .... ... ... ... .... ............................ 45

Figure 41. Quad-Speed (fast) Transition Band .......................................................................................... 45

Figure 42. Quad-Speed (fast) Transition Band (detail)........................ ... ... ... .... ... ... ... .... ... ... ... ................... 46

Figure 43. Quad-Speed (fast) Passband Ripple........................................................................................ 46

Figure 44. Quad-Speed (slow) Stopband Rejection................................................................................... 46

Figure 45. Quad-Speed (slow) Transition Band......................................................................................... 46

Figure 46. Quad-Speed (slow) Transition Band (detail)............................................................................. 46

Figure 47. Quad-Speed (slow) Passband Ripple....................................................................................... 46

CS4364

... 45

4 DS619F1

LIST OF TABLES

Table 1. Single-Speed Mode Standard Frequencies ................................................................................ 20

Table 2. Double-Speed Mode Standard Frequencies............................................................................... 20

Table 3. Quad-Speed Mode Standard Frequencies ......................................................................... ... ... .. 20

Table 4. PCM Digital Interface Format, Hardware Mode Options............................................................. 21

Table 5. Mode Selection, Hardware Mode Options .................................................................................. 21

Table 6. Direct Stream Digital (DSD), Hardware Mode Options ............................................................... 21

Table 7. Digital Interface Formats - PCM Mode........................................................................................ 35

Table 8. Digital Interface Formats - DSD Mode ........................................................................................ 35

Table 9. ATAPI Decode .......................................................................... ... ... .... ... ... ... ............................... 41

Table 10. Example Digital Volume Settings.............................................................................................. 42

CS4364

DS619F1 5

1. PIN DESCRIPTION

DSD3

DSD2 DSD1

GND

MCLK

LRCK

SDIN1

SCLK

M4(TST)

SDIN2

M3(TST)

TST

DSD6

DSD5

DSD4

48 47 46 45 44 43 42 41 40 39 38 37

13 14 15 16 17 18 19 20 21 22

CS4364

MUTE1

TST

TST_OUT

VLS

DSD_SCLK

AOUT1

23 24

AOUT2

TST_OUT

CS4364

TST_OUT AOUT3 AOUT4 TST_OUT VA GND TST_OUT AOUT5 AOUT6 TST_OUT MUTE2 MUTE3

TST

SDIN3

M0(AD0/CS)

M1(SDA/CDIN)

M2(SCL/CCLK)

VLC

RST

FILT+

MUTE5

MUTE6

MUTE4

Pin Name # Pin Description

VD 4

GND

MCLK 6

LRCK 7 SDIN1

SDIN2 SDIN3

SCLK 9 Serial Clock (Input) - Serial clocks for the serial audio interface.

TST

RST

VA 32

VLS 43

VLC 18

VQ 21 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.

Digital Power (Input) - Positive power supply for the digital section. Refer to the Recommended Operating Conditions for appropriate voltages.

Ground (Input) - Ground reference. Should be connected to analog ground.

Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Table 1 illus- trates several standard audio sample rates and the required master clock frequencies.

Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.

1113Serial Data Input (Input) - Input for two’s complement serial audio data.

14 4445Test - These pins need to be tied to analog ground.

Reset (Input) - The device enters a low power mode and all internal registers are reset to their

default settings when low. Analog Power (Input) - Positive power supply for the analog section. Refer to the Recommended

Operating Conditions for appropriate voltages. Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio

interface. Refer to the Recommended Operating Conditions for appropriate voltages. Control Port Power (Input) - Determines the required signal level for the control port and hard-

ware mode configuration pins. Refer to the Recommended Operating Conditions for appropriate voltages.

6 DS619F1

CS4364

Pin Name # Pin Description

Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir-

FILT+ 20

AOUT1 AOUT2 AOUT3 AOUT4 AOUT5 AOUT6

MUTEC1 MUTEC2 MUTEC3 MUTEC4 MUTEC5 MUTEC6

40, 37

TST_OUT

36, 33 30, 27

Hardware Mode Definitions

M0 M1 M2 M3 M4

Software Mode Definitions

SCL/CCLK 15

SDA/CDIN 16

AD0/CS

TST

DSD Definitions

DSD1, DSD2 DSD3, DSD4 DSD5, DSD6

DSD_SCLK 42 DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital serial audio interface.

47,46

cuits. Requires the capacitive decoupling to analog ground as shown in the Typical Connection Diagram.

39 38 35

Analog Output (Output) - The full scale analog output level is specified in the Analog Character-

istics specification table. 29 28

41 26 25

Mute Control (Output) - These pins are intended to be used as a control for external mute circuits 24

on the line outputs to prevent the clicks and pops that can occur in any single supply system. 23 22

Test Output - These pins need to be floating and not connected to any trace or plane.

17 16

Mode Selection (Input) - Determines the operational mode of the device as detailed in Tables 4 15

and 5. 12

Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external

pull-up resistor to the logic interface voltage in I²C

gram.

Serial Control Port Data (Input/Output) - SDA is a data I/O line in I²C mode and is open drain,

requiring an external pull-up resistor to the logic interface voltage, as shown in the Typical Con-

nection Diagram; CDIN is the input data line for the control port interface in SPI™ mode.

Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C 17

mode; CS 10

Test - These pins need to be tied to analog ground. 12

3, 2

1, 48

Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data.

is the chip select signal for SPI mode.

mode as shown in the Typical Connection Dia-

DS619F1 7

CS4364

2. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

(GND = 0 V; all voltages with respect to ground.)

Parameters Symbol Min Typ Max Units

DC Power Supply Analog power

Digital internal power

Serial data port interface power

Control port interface power

Ambient Operating Temperature (Power Applied) -CQZ T

VD VLS VLC

4.75

2.37

1.71

-40 - +85 °C

5.0

2.5

5.0

5.25

2.63

5.25

V V V V

ABSOLUTE MAXIMUM RATINGS

(GND = 0 V; all voltages with respect to ground.)

Parameters Symbol Min Max Units

DC Power Supply Analog power

Digital internal power

Serial data port interface power

Control port interface power Input Current Any Pin Except Supplies I Digital Input Voltage Serial data port interface

Control port interface Ambient Operating Temperature (power applied) T Storage Temperature T

WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

VD VLS VLC

IND-S

IND-C

stg

-0.3

-±10mA

-0.3

-55 125 °C

-65 150 °C

6.0

3.2

6.0

VLS+ 0.4 VLC+ 0.4

V V V V

V V

8 DS619F1

CS4364

DAC ANALOG CHARACTERISTICS

Test Conditions (unless otherwise indicated): VA = VLS = VLC = 5 V; VD = 2.5 V; TA = 25 °C; Full-Scale 997 Hz input sine wave

“Typical Connection Diagram” on page 18; Measurement Bandwidth 10 Hz to 20 kHz.

FS = 48 kHz, 96 kHz, 192 kHz and DSD

Dynamic Range 24-bit A-weighted

Total Harmonic Distortion + Noise 24-bit -0 dB

Idle Channel Noise / Signal-to-noise ratio - 100 - dB Interchannel Isolation (1 kHz) - 110 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB Gain Drift - 100 - ppm/°

Analog Output

Full Scale Differential- PCM, DSD processor Output Voltage (Note 3) Direct DSD Mode

Output Impedance Z Max DC Current draw from an AOUT pin I Min AC-Load Resistance R Max Load Capacitance C Quiescent Voltage V Max Current draw from V

(Note 1); Tested under max ac-load resistance; Valid with FILT+ and VQ capacitors as shown in

Parameters Symbol Min Typ Max Unit

16-bit A-weighted

(Note 2) unweighted

(Note 2) 16-bit 0 dB

unweighted

-20 dB

-60 dB

-20 dB

-60 dB

THD+N -

64%•V 47%•V

OUT

OUTmax

L L

QMAX

97 94

A A

- 130 - Ω

-1.0-mA

-3-kΩ

- 100 - pF

- 50% VA-VDC

-10-µA

103 100

97 94

-88

-80

-40

-88

-74

-34

66%•V 48%•V

-82

-74

-34

dB dB dB dB

dB dB dB dB dB dB

A A

68%•V 49%•V

Vpp

Notes:

1. One-half LSB of triangular PDF dither is added to data.

2. Performance limited by 16-bit quantization noise.

3. V

is tested under load RL and includes attenuation due to Z

OUT

DS619F1 9

CS4364

POWER AND THERMAL CHARACTERISTICS

Parameters Symbol Min Typ Max Units

Power Supplies

Power Supply Current normal operation, VA= 5 V

(Note 4) VD= 2.5 V

(Note 5) Interface current, VLC=5 V

VLS=5 V

(Note 6) power-down state (all supplies)

Power Dissipation (Note 4) VA = 5V, VD = 2.5V

normal operation

(Note 6) power-down

Package Thermal Resistance multi-layer

dual-layer

Power Supply Rejection Ratio (Note 7) (1 kHz) (60 Hz)

Notes:

4. Current consumption increases with increasing FS within a given spe ed mode and is signal dependant. Max values are based on highest FS and highest MCLK.

5. I

6. Power Down Mode is defined as RST

measured with no external loading on the SDA pin.

pin = Low with all clock and data lines held static.

7. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 6 and 7.

PSRR -

63 18

200

360

48 65 15

60 40

69 22

400

mA mA

µA µA µA

mW mW

°C/Watt °C/Watt °C/Watt

dB dB

10 DS619F1

CS4364

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. (See (Note 12))

Parameter

Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz

Passband (Note 9) to -0.01 dB corner Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB

StopBand 0.547 - - Fs StopBand Attenuation (Note 10) 102 - - dB Group Delay - 10.4/Fs - s De-emphasis Error (Note 11) Fs = 32 kHz (Relative to 1 kHz) Fs = 44.1 kHz

Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz

Passband (Note 9) to -0.01 dB corner Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB

StopBand .583 - - Fs StopBand Attenuation (Note 10) 80 - - dB Group Delay - 6.15/Fs - s

Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz

Passband (Note 9) to -0.01 dB corner Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB

StopBand .635 - - Fs StopBand Attenuation (Note 10) 90 - - dB Group Delay - 7.1/Fs - s

to -3 dB corner

Fs = 48 kHz

to -3 dB corner

0 0

Fast Roll-Off

.454 .499

±0.36 ±0.21 ±0.14

.430 .499

.105 .490

UnitMin Typ Max

Fs Fs

dB dB dB

Fs Fs

Notes:

8. Slow Roll-off interpolation filter is only available in Software Mode.

9. Response is clock dependent and will scale with Fs.

10. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.

11. De-emphasis is available only in Single-Speed Mode; Only 44.1 kHz De-emphasis is available in Hardware Mode.

12. Amplitude vs. Frequency plots of this data are available in the “Filter Response Plots” on page 43.

DS619F1 11

CS4364

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

(CONTINED)

Slow Roll-Off (Note 8)

Parameter

Single-Speed Mode - 48 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB StopBand .583 - - Fs StopBand Attenuation (Note 10) 64 - - dB Group Delay - 7.8/Fs - s De-emphasis Error (Note 11) Fs = 32 kHz (Relative to 1 kHz) Fs = 44.1 kHz

Fs = 48 kHz

0 0

0.417

0.499

±0.36 ±0.21 ±0.14

Double-Speed Mode - 96 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB StopBand .792 - - Fs StopBand Attenuation (Note 10) 70 - - dB Group Delay - 5.4/Fs - s

0 0

.296 .499

Quad-Speed Mode - 192 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB StopBand .868 - - Fs StopBand Attenuation (Note 10) 75 - - dB Group Delay - 6.6/Fs - s

0 0

.104 .481

UnitMin Typ Max

Fs Fs

dB dB dB

Fs Fs

DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE

Parameter Min Typ Max Unit

DSD Processor Mode

Passband (Note 9) to -3 dB corner 0 - 50 kHz Frequency Response 10 Hz to 20 kHz -0.05 - +0.05 dB Roll-off 27 - - dB/Oct

Direct DSD Mode

Passband (Note 9) to -0.1 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz -0.1 - 0 dB

0 0

26.9

176.4

kHz kHz

12 DS619F1

CS4364

DIGITAL CHARACTERISTICS

Parameters Symbol Min Typ Max Units

Input Leakage Current (Note 13) I

Input Capacitance - 8 - pF High-Level Input Voltage Serial I/O

Control I/O

Low-Level Input Voltage Serial I/O

Control I/O

Low-Level Output Voltage (IOL= -1.2 mA) Control I/O = 3.3 V, 5 V

Control I/O = 1.8 V, 2.5 V MUTEC auto detect input high voltage V MUTEC auto detect input low voltage V Maximum MUTEC Drive Current I MUTEC High-Level Output Voltage V MUTEC Low-Level Output Voltage V

V V

max

IH IH

IL IL

OL OL

OH OL

13. Any pin except supplies. Transient currents of up to ±100 mA on the input pins will not cause SCR latch-up

--±10µA

70% 70%

30% 30%

20% 25%

70% - - VA

--30%VA

-3-mA

-VA-V

-0-V

DS619F1 13

CS4364

SWITCHING CHARACTERISTICS - PCM

(Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 30 pF)

Parameters Symbol Min Max Units

RST pin Low Pulse Width (Note 14) MCLK Frequency 1.024 55.2 MHz MCLK Duty Cycle (Note 15) 45 55 % Input Sample Rate - LRCK (Manual selection) Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

Input Sample Rate - LRCK (Auto detect) Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

F F F

Fs Fs Fs

s s s

LRCK Duty Cycle 45 55 % SCLK Duty Cycle 45 55 % SCLK High Time t SCLK Low Time t LRCK Edge to SCLK Rising Edge t SCLK Rising Edge to LRCK Falling Edge t SDIN Setup Time Before SCLK Rising Edge t SDIN Hold Time After SCLK Rising Edge t

sckh

sckl lcks lckd

1-ms

100

170

54 108 216

kHz kHz kHz

8-ns 8-ns 5-ns 5-ns 3-ns 5-ns

Notes:

14. After powering up, RST

should be held low until after the power supplies and clocks are settled.

15. See Tables 1 - 3 for suggested MCLK frequencies.

LRCK

SCLK

SDINx

Figure 1. Serial Audio Interface Timing

lcks

sckh

MSB

sckl

MSB-1

14 DS619F1

CS4364

SWITCHING CHARACTERISTICS - DSD

(Logic 0 = AGND = DGND; Logic 1 = VLS; CL=30pF)

Parameter Symbol Min Typ Max Unit

MCLK Duty Cycle 40 - 60 % DSD_SCLK Pulse Width Low t DSD_SCLK Pulse Width High t DSD_SCLK Frequency (64x Oversampled)

(128x Oversampled) DSD_A / _B valid to DSD_SCLK rising setup time t DSD_SCLK rising to DSD_A or DSD_B hold time t DSD clock to data transition (Phase Modulation Mode) t

DSD_SCLK

sclkl

sclkh

sdlrs

sdh

dpm

sclkl

160 - - ns 160 - - ns

1.024

2.048 20 - - ns 20 - - ns

-20 - 20 ns

sclkh

3.2

6.4

MHz MHz

sdlrstsdh

DSDxx

Figure 2. Direct Stream Digital - Serial Audio Input Timing

dpm

DSD_SCLK

(128Fs)

DSD_SCLK

(64Fs)

DSDxx

Figure 3. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode

dpm

DS619F1 15

+ 35 hidden pages