Cirrus Logic CS4362 User Manual

CS4362

114 dB, 192 kHz 6-Channel D/A Converter

Features

 24-bit Conversion
 Up to 192 kHz Sample Rates
 114 dB Dynamic Range
 -100 dB THD+N
 Supports PCM or DSD Data Formats
 Selectable Digital Filters
 Volume Control with Soft Ramp

– 1 dB Step Size
– Zero Crossing Click-free Transitions

 Dedicated DSD Inputs
 Low Clock Jitter Sensitivity
 Simultaneous Support for Two Synchronous

Sample Rates for DVD Audio

 μC or Stand-Alone Operation

I

Description

The CS4362 is a complete 6-channel digital-to-analog
system including digital interpolation, fifth-order delta­sigma digital-to-analog conversion, digital de-empha­sis, volume control and analog filtering. The advantages
of this architecture include: ideal differential linearity, no
distortion mechanisms due to resistor matching errors,
no linearity drift over time and temperature and a high
tolerance to clock jitter.

The CS4362 is available in a 48-pin LQFP package in
Commercial grade (-10°C to +70°C). The CDB4362
Customer Demonstration Board is also available for de­vice evaluation and implementation suggestions.
Please see “Ordering Information” on page 42 for com­plete details.

The CS4362 accepts PCM data at sample rates from
4 kHz to 192 kHz, DSD audio data, and operates over a
wide power supply range. These features are ideal for
multi-channel audio systems including DVD players.
SACD players, A/V receivers, digital TV ’s, mixing con­soles, and effects processors.

M3/DSD_SCLK

RST

VLS

1

SCLK
LRCK

1
2

SCLK

LRCK2
SD IN1
SD IN2
SD IN3

MCLK

2

÷

DSDxx

6

http://www.cirrus.com

M1/S C L /C C L K

Volume Control Interpolation Filter Analog FilterΔΣ

Volume Control

Volume Control Interpolation Filter Analog FilterΔΣ

Serial Port

Volume Control

Volume Control Interpolation Filter Analog FilterΔΣ

Volume Control

M2/SDA /CDIN M0/AD0/CS

Control Port/Mode Select

Mixer

Interpolation Filter

Mixer

Interpolation Filter

Mixer

Interpolation Filter

GND

Copyright © Cirrus Logic, Inc. 2008

(All Rights Reserved)

VLC

MUTEC[1:6]

6

External

Mute Control

DAC

ΔΣ

DAC

DAC

ΔΣ

DAC

DAC

ΔΣ

DAC

VAGNDVD

Analog Filter

Analog Filter

Analog Filter

AO UTA1+
AO UTA1-

AO UTB1+
AO UTB1-

AO UTA2+

A2-

AO UT

AO UTB2+
AO UTB2-

AO UTA3+
AO UTA3-

AO UTB3+
AO UTB3-

VQ

FILT+

FEB '08

DS257F2

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 5

ANALOG CHARACTERISTICS.............................................................................................................5

ANALOG CHARACTERISTICS.............................................................................................................6

POWER AND THERMAL CHARACTERISTICS ................................................................................... 6

ANALOG FILTER RESPONSE ............................................................................................................. 7

DIGITAL CHARACTERISTICS............................ ... ... .... ... ... ... .... ...................................... ... .... ... ... ........ 8

ABSOLUTE MAXIMUM RATINGS........................................................................................................8

RECOMMENDED OPERATING CONDITIONS.................................................................................... 8

SWITCHING CHARACTERISTICS............................................ ...................................... ... .... ... ... ........9

DSD - SWITCHING CHARACTERISTICS .......................................................................................... 10

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT......................................... 12

2. TYPICAL CONNECTION DIAGRAM ............................................................................................... 13

3. REGISTER QUICK REFERENCE ....................................... ....................................... ... ... ... .... ............ 15

4. REGISTER DESCRIPTION ....... ... ....................................... ... .... ... ... ... ................................................ 16

4.1 Mode Control 1 (address 01h) ...................................................................................................... 16

4.1.1 Control Port Enable (CPEN) ............................................................................................ 16

4.1.2 Freeze Controls (FREEZE) .............................................................................................. 16

4.1.3 Master Clock Divide Enable (MCLKDIV) ......................................................................... 16

4.1.4 DAC Pair Disable (DACx_DIS) ........................................................................................ 16

4.1.5 Power Down (PDN) .......................................................................................................... 17

4.2 Mode Control 2 (address 02h) ...................................................................................................... 17

4.2.1 Digital Interface Format (DIF) .......................................................................................... 17

4.2.2 Serial Audio Data Clock Source (SDINXCLK) ................................................................. 18

4.3 Mode Control 3 (address 03h) ...................................................................................................... 18

4.3.1 Soft Ramp and Zero Cross Control (SZC) ....................................................................... 18

4.3.2 Single Volume Control (SNGLVOL) ................................................................................. 19

4.3.3 Soft Volume Ramp-Up After Error (RMP_UP) ................................................................. 19

4.3.4 MUTEC Polarity (MUTEC+/-) ........................................................................................... 19

4.3.5 Auto-Mute (AMUTE) ........................................................................................................20

4.3.6 Mute Pin Control (MUTEC1, MUTEC0) ........................................................................... 20

4.4 Filter Control (address 04h) ....................... ...... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ...... ... ................ 20

4.4.1 Interpolation Filter Select (FILT_SEL) ..................... ... ... ... ... .... ...................................... ... 20

4.4.2 De-Emphasis Control (DEM) ........................................................................................... 20

4.4.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN) ...................................... ... ... ... 21

4.5 Invert Control (address 05h) ......................... .......................................................... ......................21

4.5.1 Invert Signal Polarity (Inv_Xx) ..........................................................................................21

4.6 Mixing Control Pair 1 (Channels A1 & B1)(address 06h)
Mixing Control Pair 2 (Channels A2 & B2)(address 09h)
Mixing Control Pair 3 (Channels A3 & B3)(address 0Ch)
21

4.6.1 Channel A Volume = Channel B Volume (A=B) .................. ............. ............. .......... ......... 21

4.6.2 ATAPI Channel Mixing and Muting (ATAPI) .................................................................... 22

4.6.3 Functional Mode (FM) ................................... ... ... .... ... ...................................... .... ... ... ... ... 23

4.7 Volume Control (addresses 07h, 08h, 0Ah, 0Bh, 0D h, 0Eh) .................................... ... .... ... ... ...... 23

4.7.1 Mute (MUTE) ................................................................................................................... 23

4.7.2 Volume Control (xx_VOL) ................................................................................................ 23

4.8 Chip Revision (address 12h) ........................................................................................................ 24

4.8.1 Part Number ID (PART) [Read Only] ............................................................................... 24

5. PIN DESCRIPTION ....................... .... ... ... ... ... .... ... ....................................... ... ... ... .... ... ......................... 25

6. APPLICATIONS .................................................................................................................................. 28

6.1 Grounding and Power Supply Decoupling .................................................................................... 28

CS4362

®

FORMAT........................................... 11

2 DS257F2

CS4362

6.2 PCM Mode Select ......................................................................................................................... 28

6.3 Recommended Power-Up Sequence ........................................................................................... 28

6.4 Analog Output and Filtering .......................................................................................................... 28

6.5 Interpolation Filter ......................................................................................................................... 28

6.6 Clock Source Selection ................................................................................................................ 29

6.7 Using DSD Mode .......................................................................................................................... 29

6.8 Recommended Procedure for Switching Operational Modes ....................................................... 29

7. CONTROL PORT INTERFACE ........................ ... ... ... .... ...................................... .... ... ... ... ... ................ 30

7.1 Enabling the Control Port ............................................................................................................. 30

7.2 Format Selection .......................................................................................................................... 30

7.3 I²C Format .................................................................................................................................... 30

7.3.1 Writing in I²C Format . .... ... ... ... ... .... ...................................... .... ... ... ... ................................ 30

7.3.2 Reading in I²C Format ............................ .... ... ... ... .... ... ... ....................................... ... ... ...... 30

7.4 SPI Format ................................................................................................................................... 31

7.4.1 Writing in SPI ...................... ... ... .... ...................................... .... ... ... ... .... ............................ 31

7.5 Memory Address Pointer (MAP) ............................. ............................................................. .........32

7.5.1 INCR (Auto Map Increment Enable) ................................................................................ 32

7.5.2 MAP4-0 (Memory Address Pointer) ................................. ................................................ 32

8. FILTER PLOTS ........................................................................................................................... 33

9. DIAGRAMS ...................................................................................................................... 37

10. PARAMETER DEFINITIONS ............................................................................................................. 40

11. REFERENCES ................................................................................................................................... 40

12. PACKAGE DIMENSIONS ................................................................................................................. 41

13. ORDERING INFORMATION ............................................................................................................ 42

14. REVISION HISTORY ........................................................................................................................ 42

LIST OF FIGURES

Figure 1. Serial Mode Input Timing.............................................................................................................. 9

Figure 2. Direct Stream Digital - Serial Audio Input Timing........................................................................ 10

Figure 3. Control Port Timing - I²C Format................................................................................................. 11

Figure 4. Control Port Timing - SPI Format................................................................................................ 12

Figure 5. Typical Connection Diagram Control Port.......................... ...... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ...... 13

Figure 6. Typical Connection Diagram Stand-Alone.................................................................................. 14

Figure 7. Control Port Timing, I²C Format.................................................................................................. 31

Figure 8. Control Port Timing, SPI Format................................................................................................. 31

Figure 9. Single-Speed (fast) Stopband Rejection..................................................................................... 33

Figure 10. Single-Speed (fast) Transition Band......................................................................................... 33

Figure 11. Single-Speed (fast) Transition Band (detail).......................................................................... 33

Figure 12. Single-Speed (fast) Passband Ripple................................. ... ... ... ............................................. 33

Figure 13. Single-Speed (slow) Stopband Rejection ........... ... ... ... .... ... ... ....................................... ... ... ...... 33

Figure 14. Single-Speed (slow) Transition Band........................................................................................ 33

Figure 15. Single-Speed (slow) Transition Band (detail)........................................................................... 34

Figure 16. Single-Speed (slow) Passband Ripple...................................................................................... 34

Figure 17. Double-Speed (fast) Stopband Rejection ................................................................................. 34

Figure 18. Double-Speed (fast) Transition Band........................................................................................ 34

Figure 19. Double-Speed (fast) Transition Band (detail)............................................................................ 34

Figure 20. Double-Speed (fast) Passband Ripple...................................................................................... 34

Figure 21. Double-Speed (slow) Stopband Rejection................................................................................35

Figure 22. Double-Speed (slow) Transition Band................... ....................................... ... ... ... ... .... ............ 35

Figure 23. Double-Speed (slow) Transition Band (detail).................... ...................................... .... ... ... ... ... 35

Figure 24. Double-Speed (slow) Passband Ripple.................................................................................... 35

Figure 25. Quad-Speed (fast) Stopband Rejection....................... .... ... ...................................... .... ... ... ...... 35

Figure 26. Quad-Speed (fast) Transition Band .......................................................................................... 35

DS257F2 3

Figure 27. Quad-Speed (fast) Transition Band .......................................................................................... 36

Figure 28. Quad-Speed (fast) Passband Ripple........................................................................................ 36

Figure 29. Quad-Speed (slow) Stopband Rejection................................................................................... 36

Figure 30. Quad-Speed (slow) Transition Band......................................................................................... 36

Figure 31. Quad-Speed (slow) Transition Band (detail).......................................................................... 36

Figure 32. Quad-Speed (slow) Passband Ripple....................................................................................... 36

Figure 33. Format 0 - Left Justified up to 24-bit Data................................................................................. 37

Figure 34. Format 1 - I²S up to 24-bit Data................................................................................................ 37

Figure 35. Format 2 - Right Justified 16-bit Data ....................................................................................... 37

Figure 36. Format 3 - Right Justified 24-bit Data ....................................................................................... 37

Figure 37. Format 4 - Right Justified 20-bit Data ....................................................................................... 38

Figure 38. Format 5 - Right Justified 18-bit Data ....................................................................................... 38

Figure 39. De-Emphasis Curve.................................................................................................................. 38

Figure 40. Channel Pair Routing Diagram (x = Channel Pair 1, 2, or 3).................................................... 39

Figure 41. ATAPI Block Diagram (x = channel pair 1, 2, or 3) ................................................................... 39

Figure 42. Recommended Output Filter..................................................................................................... 39

LIST OF TABLES

Table 1. Digital Interface Formats - PCM Mode......................................................................................... 17

Table 2. Digital Interface Formats - DSD Mode ......................................................................................... 18

Table 3. ATAPI Decode ............................................................................................................................. 22

Table 4. Example Digital Volume Settings....... ... ....................................................................................... 23

Table 5. Common Clock Frequencies........................................................................................................ 27

Table 6. Digital Interface Format, Stand-Alone Mode Options................................................................... 27

Table 7. Mode Selection, Stand-Alone Mode Options ...............................................................................27

Table 8. Direct Stream Digital (DSD), Stand-Alone Mode Options............................................................ 27

CS4362

4 DS257F2

CS4362

1. CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS

(Full-Scale Output Sine Wave, 997 Hz; Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Test
load R
For Single-Speed Mode, Fs = 48 kHz, SCLK = 3.072 MHz, MCLK = 12.288 MHz;

For Double-Speed Mode, Fs = 96 kHz, SCLK = 6.144 MHz, MCLK = 12.288 MHz;
For Quad-Speed Mode, Fs = 192 kHz, SCLK = 12.288 MHz, MCLK = 24.576 MHz;
For Direct Stream Digital Mode, Fs = 128 x 48 kHz, DSD_SCLK = 6.144 MHz, MCLK = 12.288 MHz).

CS4362-KQZ Dynamic Performance - All PCM modes and DSD (Note 1)

Specified Temperature Range T
Dynamic Range (Note 2) 24-bit unweighted

Total Harmonic Distortion + Noise (Note 2)

Idle Channel Noise / Signal-to-noise ratio - 114 - dB
Interchannel Isolation (1 kHz) - 90 - dB

= 3 kΩ, CL = 100 pF, VA = 5 V, VD = 3.3 V (see Figure 5)

L

Parameters Symbol Min Typ Max Unit

A

A-Weighted

16-bit unweighted

(Note 3) A-Weighted

THD+N

24-bit 0 dB

-20 dB

-60 dB

16-bit 0 dB

(Note 3) -20 dB

-60 dB

-10 - 70 °C

105
108

-

-

-

-

-

-

-

-

111
114

94
97

-100

-91

-51

-94

-74

-34

-

-

-

-

-94

-

-

-

-

-

dB
dB
dB
dB

dB
dB
dB
dB
dB
dB

Notes:

1. CS4362-KQZ parts are tested at 25°C.

2. One-half LSB of triangular PDF dither is added to data.

3. Performance limited by 16-bit quantization noise.

DS257F2 5

CS4362

ANALOG CHARACTERISTICS

(Continued)

Parameters Symbol Min Typ Max Units

Analog Output - All PCM modes and DSD

Full Scale Differential Output Voltage (Note 4) V
Quiescent Voltage V
Max Current from V

Q

FS

I

QMAX

Q

Interchannel Gain Mismatch - 0.1 - dB
Gain Drift - 100 - ppm/°C
Output Impedance (Note 4) Z
AC-Load Resistance R
Load Capacitance C

OUT

L
L

86% V

A

91% V

A

96% V

A

Vpp

- 50% VA-VDC

-1 -μA

- 100 - Ω

3- -kΩ

- - 100 pF

POWER AND THERMAL CHARACTERISTICS

Parameters Symbol Min Typ Max Units

Power Supplies

Power Supply Current normal operation, VA= 5 V

(Note 5) V

V

= 5 V

D

= 3.3 V

D

Interface current, VLC=5 V (Notes 6, 7)

VLS=5 V

power-down state (all supplies) (Note 8)

Power Dissipation (Note 5)
VA = 5 V, VD = 3.3 V normal operation

power-down (Note 8)

VA = 5 V, VD = 5 V normal operation

power-down (Note 8)

Package Thermal Resistance multi-layer

dual-layer

Power Supply Rejection Ratio (Note 9) (1 kHz)

(60 Hz)

I

A

I

D

I

D

I

LC

I

LS

I

pd

θ

JA

θ

JA

θ

JC

PSRR -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

50
38
25

2

84

200

335

1

440

1

48
65
15

60
40

55
60
40

-

-

-

410

-

575

-

-

-

-

-

-

mA
mA
mA

μA
μA
μA

mW
mW
mW
mW

°C/Watt
°C/Watt
°C/Watt

dB
dB

Notes:

4. V

is tested under load RL and includes attenuation due to Z

FS

OUT

5. Current consumption increases with increasing FS within a given speed mode and is signal dependa nt.
Max values are based on highest FS and highest MCLK.

6. I

measured with no external loading on the SDA pin.

LC

7. This specification is violated when the VLC supply is greater than VD and when pin 16 (M1/SDA) is tied
or pulled low. Logic tied to pin 16 needs to be able to sink this current.

8. Power Down Mode is defined as RST

pin = Low with all clock and data lines held static.

9. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 5 and 6.

6 DS257F2

CS4362

ANALOG FILTER RESPONSE

Fast Roll-Off Slow Roll-Off (Note 10)

Parameter

Combined Digital and On-chip Analog Filter Response - Single-Speed Mode

Passband (Note 12) to -0.01 dB corner

to -3 dB corner00
Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 -0.01 - +0.01 dB
StopBand .547 - - .583 - - Fs
StopBand Attenuation (Note 13) 90 - - 64 - - dB
Group Delay - 12/Fs - - 6.5/Fs - s
Passband Group Delay Deviation 0 - 20 kHz - - ±0.41/Fs - ±0.14/Fs s
De-emphasis Error (Note 14) Fs = 32 kHz
(Relative to 1 kHz) Fs = 44.1 kHz

Fs = 48 kHz

-

-

-

-

-

-

-

-

.454
.499

±0.23
±0.14
±0.09

(Note 11)

0
0

-

-

-

-

-

-

-

-

0.417

0.499

±0.23
±0.14
±0.09

Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz (Note 11)

Passband (Note 12) to -0.01 dB corner

to -3 dB corner00
Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 -0.01 - 0.01 dB
StopBand .583 - - .792 - - Fs
StopBand Attenuation (Note 13) 80 - - 70 - - dB
Group Delay - 4.6/Fs - - 3.9/Fs - s
Passband Group Delay Deviation 0 - 20 kHz - - ±0.03/Fs - ±0.01/Fs s

-

-

.430
.499

0
0

-

-

.296
.499

Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz (Note 11)

Passband (Note 12) to -0.01 dB corner

to -3 dB corner00
Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 -0.01 - 0.01 dB
StopBand .635 - - .868 - - Fs
StopBand Attenuation (Note 13) 90 - - 75 - - dB
Group Delay - 4.7/Fs - - 4.2/Fs - s
Passband Group Delay Deviation 0 - 20 kHz - - ±0.01/Fs - ±0.01/Fs s

-

-

.105
.490

0
0

-

-

.104
.481

Combined Digital and On-chip Analog Filter Response - DSD Mode (Note 11)

Passband (Note 12) to -0.1 dB corner

to -3 dB corner
Frequency Response 10 Hz to 20 kHz - - - -.01 - 0.1 dB

-

-

-

-

-

-

0
0

-

-

20

120

UnitMin Typ Max Min Typ Max

Fs
Fs

dB
dB
dB

Fs
Fs

Fs
Fs

kHz
kHz

Notes:

10. Slow Roll-Off interpolation filter is only available in Control Port Mode.

11. Filter response is not tested but is guaranteed by design.

12. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 9 to 32) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

13. Single- and Double-Speed Mode Measurement Bandwidth is from stopband to 3 Fs.
Quad-Speed Mode Measurement Bandwidth is from stopband to 1.34 Fs.

14. De-emphasis is available only in Single-Speed Mode; Only 44.1 kHz De-emphasis is available in Stand­Alone Mode.

DS257F2 7

CS4362

DIGITAL CHARACTERISTICS

(For KQZ TA = -10°C to +70°C; VLC = VLS = 1.8V to 5.5V)

Parameters Symbol Min Typ Max Units

High-Level Input Voltage Serial Data Port

Control Port

Low-Level Input Voltage Serial Data Port

Control Port
Input Leakage Current (Note 7) I
Input Capacitance - 8 - pF
Maximum MUTEC Drive Current - 3 - mA
MUTEC High-Level Output Voltage V
MUTEC Low-Level Output Voltage V

V

IH

V

IH

V

IL

V

IL

in

OH
OL

70% VLS
70% VLC

-

-

--±10μA

-VA-V

-0-V

-

-

-

-

-

-

20% VLS
20% VLC

V
V

V
V

ABSOLUTE MAXIMUM RATINGS

(GND = 0 V; all voltages with respect to ground.)

Parameters Symbol Min Max Units

DC Power Supply Analog power

Digital internal power

Serial data port interface power

Control port interface powe r
Input Current, Any Pin Except Supplies I
Digital Input Voltage Serial data port interface

Control port interface
Ambient Operating Temperature (power applied) T
Storage Temperature T

WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

VLS
VLC

V

IND-S

V

IND-C

VA
VD

stg

-0.3

-0.3

-0.3

-0.3

in

A

-±10mA

-0.3

-0.3

-55 125 °C

-65 150 °C

6.0

6.0

6.0

6.0

VLS+ 0.4
VLC+ 0.4

V
V
V
V

V
V

RECOMMENDED OPERATING CONDITIONS

(GND = 0 V; all voltages with respect to ground.)

Parameters Symbol Min Typ Max Units

DC Power Supply Analog power

Digital internal power

Serial data port interface power

Control port interface powe r

8 DS257F2

VA

VD
VLS
VLC

4.5

3.0

1.8

1.8

5.0

3.3

5.0

5.0

5.5

5.5

5.5

5.5

V
V
V
V

CS4362

SWITCHING CHARACTERISTICS

(For KQZ TA = -10°C to +70°C; VLS = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 30 pF)

Parameters Symbol Min Typ Max Units

MCLK Frequency (Note 15)

Single-Speed Mode 1.024 - 51.2 MHz

Double-Speed Mode 6.400 - 51.2 MHz

Quad-Speed Mode 6.400 - 51.2 MHz
MCLK Duty Cycle 405060%
Input Sample Rate Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode
LRCK Duty Cycle 45 50 55 %
SCLK Pulse Width Low t
SCLK Pulse Width High t

SCLK Period

Fs
Fs
Fs

sclkl

sclkh

t

sclkw

4

50

100

-

-

-

50
100
200

20 - - ns
20 - - ns

2

-----------------

MCLK

--ns

kHz
kHz
kHz

(Note 16)

SCLK rising to LRCK edge delay t
SCLK rising to LRCK edge setup time t
SDATA valid to SCLK rising setup time t
SCLK rising to SDATA hold time t

t

sclkw

slrd
slrs

sdlrs

sdh

4

-----------------

MCLK

20 - - ns
20 - - ns
20 - - ns
20 - - ns

--ns

LRCK1 to LRCK2 frequency ratio (Note 17) 0.25 1.00 4.00

Notes:

15. See Table 5 on page 27 for suggested MCLK frequencies

16. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled.

17. The higher frequency LRCK must be an exact integer multiple (1, 2, or 4) of the lower frequency LRCK

.

LRCK

t

sclkl

t

sdh

t

sclkh

SCLK

t

slrd

t

sdlrs

t

slrs

SDATA

Figure 1. Serial Mode Input Timing

DS257F2 9

CS4362

DSD - SWITCHING CHARACTERISTICS

(TA=-10°C to 70°C; Logic 0 = GND; VLS = 1.8 V to 5.5 V; Logic 1 = VLS Volts; CL=30pF)

Parameter Symbol Min Typ Max Unit

Master Clock Frequency (Note 18) 4.096 - 38.4 MHz
MCLK Duty Cycle (All DSD

modes)
DSD_SCLK Pulse Width Low t
DSD_SCLK Pulse Width High t
DSD_SCLK Frequency (64x Oversam-

pled)

(128x Oversampled)
DSD_L / _R valid to DSD_SCLK rising setup time t
DSD_SCLK rising to DSD_L or DSD_R hold time t

Note:

18. Min is 4 times 64x DSD or 2 times 128x DSD, and Max is 12 times 64x DSD or 6 times 128x DSD. The
proper MCLK to DSD_SCLK ratio must be set either by the DIF registers or the M0:2 pins

sclkl

sclkh

sdlrs

sdh

40 50 60 %

20 - - ns
20 - - ns

1.024

2.048

20 - - ns
20 - - ns

t

sclkh

t

sclkl

-

-

3.2

6.4

MHz
MHz

DSD_SCLK

DSD_L, DSD_R

Figure 2. Direct Stream Digital - Serial Audio Input Timing

sdlrstsdh

t

10 DS257F2

CS4362

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C® FORMAT

(For KQZ TA = -10°C to +70°C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL=30pF)

Parameter Symbol Min Max Unit

SCL Clock Frequency f

Rising Edge to Start t

RST
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 19) t
SDA Setup time to SCL Rising t
Rise Time of SCL and SDA t
Fall Time SCL and SDA t
Setup Time for Stop Condition t
Acknowledge Delay from SCL Falling (Note 20) t

Notes:

19. Data must be held for sufficient time to bridge the transition time, t

20. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

15

---------------------

21. for Single-Speed Mode, for Double-Speed Mode, for Quad-Speed Mode.

256 Fs×

15

--------------------­128 Fs×

hdst

low
high
sust

hdd

sud

rc

fc

susp

ack

scl

irs

buf

, t
, t

rc
fc

- 100 kHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs
0-µs

250 - ns

-1µs

- 300 ns

4.7 - µs

- (Note 21) ns

, of SCL.

fc

15

-----------------­64 Fs×

RST

SDA

SCL

t

irs

Stop Sta rt

t

buf

t

hdst

t

t

high

low

t

hdd

t

sud

t

ack

Figure 3. Control Port Timing - I²C Format

Repeated

Start

t

sust

t

hdst

t

rd

t

fc

t

rc

Stop

t

fd

t

susp

DS257F2 11

CS4362

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT

(For KQZ TA = -10°C to +70°C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL=30pF)

Parameter Symbol Min Max Unit

CCLK Clock Frequency f
RST Rising Edge to CS Falling t

CCLK Edge to CS

High Time Between Transmissions t

CS
CS

Falling to CCLK Edge t

CCLK Low Time t
CCLK High Time
CDIN to CCLK Rising Setup Time t

CCLK Rising to DATA Hold Time (Note 23) t
Rise Time of CCLK and CDIN (Note 24) t
Fall Time of CCLK and CDIN (Note 24) t

Falling (Note 22) t

Notes:

22. t

only needed before first falling edge of CS after RST rising edge. t

spi

23. Data must be held for sufficient time to bridge the transition time of CCLK.

24. For F

< 1 MHz.

SCK

sclk

csh
css

t

sch
dsu

srs
spi

scl

dh

-

500 - ns
500 - ns

1.0 - µs

20 - ns

1

-----------------

MCLK

1

-----------------

MCLK

40 - ns
15 - ns

r2
f2

- 100 ns

- 100 ns

= 0 at all other times.

spi

MCLK

----------------­2

-ns

-ns

MHz

RST

CS

CCLK

CDIN

t

srs

t

t

spi

t

css

r2

t

t

scl

sch

t

f2

t

t

dsu

dh

Figure 4. Control Port Timing - SPI Format

t

csh

12 DS257F2

2. TYPICAL CONNECTION DIAGRAM

CS4362

+3.3 V to +5 V

+1.8 V to +5 V

Controller

PCM

Digital
Audio

Source

Source

Micro-

DSD

Audio

1 µF

+

0.1 µF

0.1 µF

6
7

9

10

12

8

11

13

43

3
2

1

48

47

46

42

19

15
16

17

VD

MCLK

LRCK1
SCLK1

LRCK2
SCLK2

SDIN1

SDIN2
SDIN3

VLS

DSDA1
DSDB1
DSDA2

DSDB2

DSDA3
DSDB3
DSD_SCLK

RST

SCL/CCLK

SDA/CDIN

ADO/CS

4

CS4362

32

VA

AOUTA1+

AOUTA1-

AOUTB1+

AOUTB1-

AOUTA2+

AOUTA2-

AOUTB2+

AOUTB2-

AOUTA3+

AOUTA3-

AOUTB3+

AOUTB3-

MUTEC1

MUTEC2

MUTEC3

MUTEC4

MUTEC5

MUTEC6

0.1 µF

39

40

38

37

35

36

34

33

29

30

28

27

41

26

25

24

23

22

+

1 µF

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Analog Conditioning

and Muting

Mute
Drive

+5 V

Note*

0.1 µF

Ω

2 K

18

VLC

GND

5

GND

31

FILT+

CMOUT

20

21

0.1 µ

+

47 µF

F

F

1 µF

+

0.1 µ

Ω

2 K

+1.8 V to + 5 V

Note*: Necessary for I2C
control port operation

Figure 5. Typical Connection Diagram Control Port

DS257F2 13