Cirrus Logic CS4354 User Manual

PCM Serial

Audio Port

Level Shifter

I²S Serial
Audio Input

Multibit

Modulator

Interpolation

Filters + HPF

Left Channel

Right Channel

Power-On

Reset

Auto Speed

Mode Detect

Analog Supply (VA)

+5 V

Inverting

Charge

Pump

1.8V reg

-VA

Interface Supply (VL)

+1.8V to +5V

Ground-Centered,
2 Vrms Line Level
Outputs

DAC

CS4354

5-V Stereo DAC with 2-V

Features

 Advanced multibit delta–sigma modulator
 101 dB A-weighted dynamic range
 –86 dB THD+N
 Single-ended ground-centered analog

architecture

– No DC-blocking capacitors required
– Integrated inverting charge pump
– Filtered line-level outputs
–2V

 Low-latency digital filtering
 Supports sample rates up to 192 kHz
 24-bit I²S input
 +5-V analog supply with integrated inverting

charge pump and regulator for core logic, and
+1.8-V to +5-V interface power supplies

 50-mW power consumption
 14-pin SOIC, lead-free assembly

full-scale output

RMS

RMS

Ground-Centered Output

Description

The CS4354 is a complete stereo digital-to-analog sys­tem including digital interpolation, third-order multi-bit
delta–sigma digital-to-analog conversion, digital de- em­phasis, analog filtering, and on-chip 2 V
driver from a 5 V supply.

The advantages of this architecture include ideal differ­ential linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and temper­ature, high tolerance to clock jitter, and a minimal set of
external components.

These features are ideal for cost-sensitive, two-channel
audio systems including video game consoles, Blu-Ray

®

Disc

and DVD players, set-top boxes, digital TVs, and

DAB/DMB devices.
The CS4354 is available in a 14-pin SOIC package in

Commercial (–40°C to +85°C) grade. The CDB4354
Customer Demonstration Board is also available for de­vice evaluation and implementation suggestions.
Please see “Ordering Information” on page 23 for com­plete details.

RMS

line-level

http://www.cirrus.com

Copyright  Cirrus Logic, Inc. 2011

(All Rights Reserved)

Sept '11

DS895F2

TABLE OF CONTENTS

1. PIN DESCRIPTIONS ...................................... ... ... ... .... ... .......................................... ... ... ..................... 4

2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 5

RECOMMENDED OPERATING CONDITIONS .................................................................................... 5

ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 5

DAC ANALOG CHARACTERISTICS .................................................................................................... 6

COMBINED DIGITAL AND ON-CHIP ANALOG FILTER CHARACTERISTICS ................................... 7

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE ......................................................... 8

DIGITAL INTERFACE CHARACTERISTICS ....... ... ... .... ... ... ... .... ............................................. ... ... ... ... 10

INTERNAL POWER-ON RESET THRESHOLD VOLTAGES ............................................................. 10

DC ELECTRICAL CHARACTERISTICS .............................................................................................. 11

2.1 Digital I/O Pin Characteristics ........................................................................................................ 11

3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 12

4. APPLICATIONS ................................................................................................................................... 13

4.1 Ground-Centered Line Outputs ............................ .... ... ... ... .... ............................................. ... ......... 13

4.2 Sample Rate Range/Operational Mode Detect ................. .... ......................................... .... ... ... ... ... 13

4.3 System Clocking ............................................................................................................................ 13

4.4 Serial Clock .................................................................................................................................... 14

4.4.1 External Serial Clock Mode ................................................................................................... 14

4.4.2 Internal Serial Clock Mode .................................................................................................... 14

4.4.2.1 De-Emphasis Control ................................................................................................. 14

4.5 Internal High-Pass Filter ................................................................................................................ 15

4.6 Digital Interface Format .................................................................................................................. 15

4.7 Internal Power-On Reset ............................................................................................................... 15

4.8 Initialization .................................................................................................................................... 16

4.9 Recommended Operational Sequences ........................................................................................ 18

4.9.1 Power-Up .... ... .......................................... ... .......................................... .... ... ......................... 18

4.9.2 Power-Down ................................... .... ... ... ... .... .......................................... ... ... ... ... ................ 18

4.9.3 Sample Rate Change ......... ... ... ... ... .... .......................................... ... ... ... .... ... ... ... ................... 18

4.10 Grounding and Power Supply Arrangements .............................................................................. 18

4.10.1 Capacitor Placement ........................................................................................................... 19

5. COMBINED DIGITAL AND ON-CHIP ANALOG FILTER RESPONSE PLOTS .............................. 20

6. PARAMETER DEFINITIONS ................................................................................................................ 22

7. PACKAGE INFORMATION .................................................................................................................. 23

7.1 Dimensions .................................................................................................................................... 23

7.2 Thermal Characteristics ................................................................................................................. 23

8. ORDERING INFORMATION ................................................................................................................ 23

9. REVISION HISTORY ............................................................................................................................ 24

CS4354

LIST OF FIGURES

Figure 1. External Serial Clock Mode Input Timing ..................................................................................... 9

Figure 2. Internal Serial Clock Mode Input Timing ................................. ..................................................... 9

Figure 3. Internal Serial Clock Generation .................................................................................................. 9

Figure 4. Power-On Reset Threshold Sequence ...................................................................................... 10

Figure 5. Typical Connection Diagram ...................................................................................................... 12

Figure 6. CS4354 Data Format (I²S) ......................................................................................................... 14

Figure 7. De-Emphasis Curve, Fs = 44.1 kHz .......................................................................................... 15

Figure 8. Internal Power-On Reset Circuit ................................................................................................ 15

Figure 9. Initialization and Power-Down Sequence Diagram .................................................................... 17

Figure 10. Single-Speed Stopband Rejection ........... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 20

Figure 11. Single-Speed Transition Band ................................. ... .... ... ...................................................... 20

Figure 12. Single-Speed Transition Band (detail) ..................................................................................... 20

Figure 13. Single-Speed Passband Ripple ............................................................................................... 20

2 DS895F2

Figure 14. Double-Speed Stopband Rejection ................................................................. ... ... ... .... ... ......... 20

Figure 15. Double-Speed Transition Band ................................................................................................ 20

Figure 16. Double-Speed Transition Band (detail) . ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 21

Figure 17. Double-Speed Passband Ripple .............................................................................................. 21

Figure 18. Quad-Speed Stopband Rejection ............................................................................................ 21

Figure 19. Quad-Speed Transition Band .................................................................................................. 21

Figure 20. Quad-Speed Transition Band (detail) ...................................................................................... 21

Figure 21. Quad-Speed Passband Ripple ................................................................................................ 21

LIST OF TABLES

Table 1. Power-On Reset Threshold Voltages .......................................................................................... 10

Table 2. Digital I/O Pin Characteristics ..................................................................... .... ... ... ... ... ................ 11

Table 3. CS4354 Operational Mode Auto-Detect ...................................................................................... 13

Table 4. Common MCLK and LRCK Frequencies .................................................................................... 13

Table 5. Internal SCLK Frequencies ......... ... ... ... .... ... ... ... .... ... ............................................. ... ... ... ............. 14

CS4354

DS895F2 3

1. PIN DESCRIPTIONS

VL -VFILT

SDIN FLYN

MCLK FLYP

LRCK VA

SCLK/DEM GND

GND AOUTB

FILT+ AOUTA

1
2
3
4
5
6
7

9

10

11

12

13

14

8

Pin Name Pin # Pin Description

VL 1 Serial Audio Interface Power (Input) - Positive power for the serial audio interface.
SDIN 2 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
MCLK 3 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

LRCK 4
SCLK/DEM 5 Serial Clock (Input) - Serial clock for the serial audio interface.

FILT+
AOUTA

AOUTB
GND 6, 10 Ground (Input) - Ground reference. See Section 4.10 on page 18 for layout considerations.

VA 11
FLYP

FLYN

-VFILT 14

Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial
audio data line.

Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

7

89Analog Outputs (Output) - The full-scale analog line output level is specified in the Analog Characteris-

tics table.

Analog, Charge Pump, and Regulator Power (Input) - Positive power supply for the analog, inverting
charge pump, and regulator for the digital core logic sections.

1213Inverting Charge Pump Cap Positive/Negative Nodes (Output) - Positive and Negative nodes for the

inverting charge pump’s flying capacitor.
Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge pump that

provides the negative rail for the output amplifiers.

CS4354

4 DS895F2

CS4354

2. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

GND = 0 V; all voltages with respect to ground.(Note 1)

Parameters Symbol Min Typ Max Units

DC power supply Analog power

Interface power

Ambient operating temperature (power applied) -CSZ T

VA
VL

4.75

1.4

A

-40 - +85 °C

5.0

1.8, 3.3, 5.0

5.25

5.25

V
V

Notes: 1. Device functional operation is guarante ed within these limits. Functionality is not guaranteed or implied

outside of these limits. Operation outside of these limits may adversely affect device reliability.

ABSOLUTE MAXIMUM RATINGS

GND = 0 V; all voltages with respect to ground.

Parameters Symbol Min Max Units

DC power supply Low voltage analog power

Interface power
Input current, any pin except supplies I
Digital input voltage (Note 2) Digital interface V
Ambient operating temperature (power applied) T
Storage temperature T

WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

Notes: 2. The maximum over/under voltage is limited by the input current except on the power supply pin.

VA
VL

IN-L

stg

-0.3

-0.3

in

A

-±10mA

-0.3 VL+ 0.4 V

-55 +125 °C

-65 +150 °C

6.0

6.0

V
V

DS895F2 5

CS4354

VRMS

Vpp

22

---------- -=

DAC ANALOG CHARACTERISTICS

Test conditions (unless otherwise specified): TA = 25 °C; VA = 5 V, VL = 3.3 V; GND = 0 V; FILT+, -VFILT, and
FLYP/N capacitors as shown in Figure 5 on page 12; input test signal is a 997 Hz sine wave at 0 dBFS; measure-

ment bandwidth 20 Hz to 20 kHz.

Parameter Symbol Min Typ Max Unit

Dynamic Performance, Fs = 48, 96, and 192 kHz (Notes 3, 5)

Dynamic range 24-bit A-weighted

unweighted

16-bit A-weighted

unweighted

Total harmonic distortion + noise 24-bit 0 dB

-20 dB

-60 dB

16-bit 0 dB

-20 dB

-60 dB
Idle channel noise/signal-to-noise ratio (A-weighted) - 101 - dB
Interchannel Isolation (1 kHz) - 100 - dB

THD+N

Analog Output (Note 4)

Full scale AOUTx output voltage (Notes 6, 7) 0.38•VA 0.40•VA 0.42•VA V

Interchannel gain mismatch - 0.1 - dB
Output offset - ±1 ±8 mV
Gain drift - 100 - ppm/°C
Output impedance Z
Load resistance R
Load capacitance C

OUT

L
L

95
92

-

-

-

-

-

-

-

-

1.07•VA 1.13•VA 1.19•VA V

-100-
3--k

--100pF

101

98
96
93

-86

-78

-38

-86

-73

-33

-

-

-

-

-80

-72

-32

-

-

-

dB
dB
dB
dB

dB
dB
dB
dB
dB
dB

RMS

pp

Notes: 3. Measured at the output of the external low-pass filter on AOUTx as shown in Figure 5 on page 12.

4. Measured between the AOUTx and GND pins.

5. One LSB of triangular PDF dither is added to data.

6. Does not include attenuation due to Z

. Additional impedance between the AOUTx pin and the load

OUT

will lower the voltage delivered to the load.

7. V

is the controlling specification. V

PP

specification valid for sine wave signals only.

RMS

Note that for sine wave signals:

6 DS895F2

CS4354

COMBINED DIGITAL AND ON-CHIP ANALOG FILTER CHARACTERISTICS

The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam­ple rate by multiplying the given characteristic by Fs. Reference level (0 dB) is set at 997 Hz. (Note 11)

Parameter Min Typ Max Unit

Single-Speed Mode - 48 kHz

Passband (Note 8) to -0.05 dB corner

to -3 dB corner
Frequency response 20 Hz to 20 kHz -0.05 - +0.05 dB
Stopband 0.550 - - Fs
Stopband attenuation (Note 9) 80 dB - - dB
High-pass filter settling time (input signal goes to 95% of its final value) - 2.452•10
Total group delay - 9.4/Fs - s
De-emphasis error (Note 10)(Relative to 1 kHz) Fs = 44.1 kHz - - ±0.14 dB

1.796•10

1.947•10

Double-Speed Mode - 96 kHz

Passband (Note 8) to -0.05 dB corner

to -3 dB corner
Frequency response 20 Hz to 20 kHz -0.05 - +0.05 dB
Stopband 0.583 - - Fs
Stopband attenuation (Note 9) 82 dB - - dB
High-pass filter settling time (input signal goes to 95% of its final value) - 4.903•10
Total group delay - 7.0/Fs - s

8.980•10

9.736•10

Quad-Speed Mode - 192 kHz

Passband (Note 8) to -0.05 dB corner

to -3 dB corner
Frequency response 20 Hz to 20 kHz -0.05 - +0.05 dB
Stopband 0.630 - - Fs
Stopband attenuation (Note 9) 85 dB - - dB
High-pass filter settling time (input signal goes to 95% of its final value) - 9.807•10
Total group delay - 4.9/Fs - s

4.490•10

4.868•10

Notes: 8. Response is clock-dependent and will scale with Fs.

9. For Single- and Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.

10. De-emphasis is available only in Single-Speed Mode.

11. Amplitude vs. frequency plots of this data are available in “Combined Digital and On-chip Analog Filter

Response Plots” on page 20.

-4

-5

-5

-6

-5

-6

-

-

4

/Fs - s

-

-

4

/Fs - s

-

-

4

/Fs - s

0.470

0.500

0.290

0.500

0.253

0.486

Fs
Fs

Fs
Fs

Fs
Fs

DS895F2 7

CS4354

50%

1

2MCLK



----------------------------

–

50%

1

2MCLK



----------------------------+

10

9

SCLK

----------------

109–

4MCLK

-------------------------- -

10

9

4MCLK

-------------------------- -

10

9

512 Fs

---------------------- - 10+

10

9

512 Fs

---------------------- - 15+

10

9

384 Fs

---------------------- - 15+

sclkr

t

sclkw

2

-----------------

10

9

2MCLK



-------------------------- -t

mclkf

++=

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE

Parameters Symbol Min Typ Max Units

MCLK frequency 7.6 - 55.3 MHz
MCLK duty cycle 35 - 65 %
Input sample rate All MCLK/LRCK ratios combined

(Note 12) (SSM) 256x, 384x, 512x, 768x, 1024x

(DSM) 128x, 192x, 256x, 384x, 512x

(QSM) 128x, 192x, 256x

External SCLK Mode

LRCK duty cycle 45 - 55 %
SCLK pulse width low t
SCLK pulse width hi gh t
SCLK duty cycle 45 - 55 %
SCLK rising to LRCK edge delay t
LRCK edge to SCLK rising delay t
SDIN valid to SCLK rising setup time t
SCLK rising to SDIN hold time t

Internal SCLK Mode

LRCK duty cycle

Fs 30

170

sclkl

sclkh

slrd
slrs

sdlrs

sdh

30
84

-

-

-

-

216

54
108
216

kHz
kHz
kHz
kHz

20 - - ns
20 - - ns

20 - - ns
20 - - ns
20 - - ns
20 - - ns

--

SCLK period (Note 13) t

MCLK falling to LRCK edge t

LRCK edge to SCLK rising t

SDIN valid to SCLK rising setup time t

SCLK rising to SDIN hold time

MCLK / LRCK = 1024, 512, 256, 128

MCLK / LRCK = 768, 384, 192 - -

12. Not all sample rates are supported for all clock ratios. See Section 4.2 “Sample Rate Range/Operational

Mode Detect” on page 13 for supported ratios and frequencies. SSM = Single-Speed Mode,

DSM = Double-Speed Mode, QSM = Quad-Speed Mode.

13. SCLK period is defined by the SCLK / LRCK ratio. The SCLK/LRCK ratio may be either 32, 48, or 64.
See Table 5 on page 14.

14.

sclkw

mclkf

sclkr

sdlrs

t

sdh

--ns

-ns

- (Note 14) -ns

--ns

-­ns

8 DS895F2