Cirrus Logic CS4353 User Manual

PCM Serial

Audio Port

Level Shifter

Serial Audio Input

Multibit

Modulator

Interpolation

Filters

Digital Core Logic and

Charge Pump Supply (VCP)

+3.3 V

Left Channel

Right Channel

Hardware Control

Power-On

Reset

Hardware

Control

Reset

Auto Speed

Mode Detect

Analog Supply (VA)

+3.3 V

Inverting

Step-Up

+VA_H

-VA_H

Interface Supply (VL)

+0.9 V to +3.3 V

Ground-Centered, 2 Vrms Line Level Outputs

DAC

Pseudo Diff. Input

CS4353

3.3 V Stereo Audio DAC with 2 V

Features

 Multi-bit Delta-Sigma Modulator  106 dB A-weighted Dynamic Range  -93 dB THD+N  Single-ended Ground Centered Analog

Architecture

– No DC-blocking Capacitors Required – Integrated Step-up/Inverting Charge Pump – Filtered Line-level Outputs – Selectable 1 or 2 V

 Low Clock-jitter Sensitivity  Low-latency Digital Filtering  Supports Sample Rates up to 192 kHz  24-bit Resolution  +3.3 V Charge Pump and Core Logic, +3.3 V

Analog, and +0.9 to 3.3 V Interface Power Supplies

 Low Power Consumption  24-pin QFN, Lead-free Assembly

Full-scale Output

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Description

The CS4353 is a complete stereo digital-to-analog system including digital interpolation, fifth-order multi-bit delta-sigma digital-to-analog conversion, digital de-emphasis, analog filtering, and on-chip 2 V driver from a 3.3 V supply.

The advantages of this architecture include ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature, high tolerance to clock jitter, and a minimal set of external components.

The CS4353 is available in a 24-pin QFN package in Commercial (-40°C to +85°C) grade. The CDB4353 Customer Demonstration Board is also available for device evaluation and implementation suggestions. Please see “Ordering Information” on page 25 for complete details.

These features are ideal for cost-sensitive, 2-channel audio systems including video game consoles, DVD players and recorders, A/V receivers, set-top boxes, digital TVs, mini-component systems, and mixing consoles.

RMS

Line Output

line-level

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http://www.cirrus.com

MAY ‘11

DS803F3

TABLE OF CONTENTS

1. PIN DESCRIPTIONS ............................................................................................................................. 4

2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6

RECOMMENDED OPERATING CONDITIONS .................................................................................... 6

ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6

DAC ANALOG CHARACTERISTICS .................................................................................................... 7

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................................ 8

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE ................................................... 9

DIGITAL INTERFACE CHARACTERISTICS ....... ... ... .... ... ... ... .... ......................................... .... ... ... ... ... 10

INTERNAL POWER-ON RESET THRESHOLD VOLTAGES ............................................................. 10

DC ELECTRICAL CHARACTERISTICS .............................................................................................. 11

3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 12

4. APPLICATIONS ................................................................................................................................... 13

4.1.1 Ground-centered Outputs ............................ .... .......................................... ... ... ...................... 13

4.1.2 Full-scale Output Amplitude Control ......................................................................................13

4.1.3 Pseudo-differential Outputs ... ... .......................................... ... ... .... ... ... ... .... ............................ 13

4.9.1 Power-up Sequences .. ... .... ... ... ... ... .... ... ................................................................................ 19

4.9.1.1 External RESET Power-up Sequence ....................................................................... 19

4.9.1.2 Internal Power-on Reset Power-up Sequence .......................................................... 19

4.9.2 Power-down Sequences .................... ................................................................................... 19

4.9.2.1 External RESET Power-down Sequence .................................................................. 19

4.9.2.2 Internal Power-on Reset Power-down Sequence ...................................................... 19

4.10.1 Capacitor Placement ........................................................................................................... 20

5. DIGITAL FILTER RESPONSE PLOTS ......................................................................................... 21

6. PARAMETER DEFINITIONS ................................................................................................................ 23

7. PACKAGE DIMENSIONS .................................................................................................................... 24

8. ORDERING INFORMATION ............................................................................................................... 25

9. REVISION HISTORY ........................................................................................................................... 25

CS4353

2 DS803F3

LIST OF FIGURES

Figure 1.Serial Input Timing ........................................................................................................................ 9

Figure 2.Power-on Reset Threshold Sequence . .... ... ... ... .......................................................................... 10

Figure 3.Typical Connection Diagram ....................................................................................................... 12

Figure 4.Stereo Pseudo-differential Output ............................................................................................... 13

Figure 5.I²S, up to 24-bit Data ................................................................................................................... 15

Figure 6.Left-justified up to 24-bit Data ..................................................................................................... 15

Figure 7.De-emphasis Curve, Fs = 44.1 kHz ............................................................................................ 16

Figure 8.Internal Power-on Reset Circuit .................................................................................................. 16

Figure 9.Initialization and Power-down Sequence Diagram ............... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 18

Figure 10.Single-speed Stopband Rejection ............................................................................................. 21

Figure 11.Single-speed Transition Band ................................................................................................... 21

Figure 12.Single-speed Transition Band (detail) ....................................................................................... 21

Figure 13.Single-speed Passband Ripple ................................................................................................. 21

Figure 14.Double-speed Stopband Rejection ........................................................................................... 21

Figure 15.Double-speed Transition Band ................................................................................................. 21

Figure 16.Double-speed Transition Band (detail) ..................................................................................... 22

Figure 17.Double-speed Passband Ripple ............................................................................................... 22

Figure 18.Quad-speed Stopband Rejection .............................................................................................. 22

Figure 19.Quad-speed Transition Band .................................................................................................... 22

Figure 20.Quad-speed Transition Band (detail) ........................................................................................ 22

Figure 21.Quad-speed Passband Ripple .. ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 22

CS4353

LIST OF TABLES

Table 1. Digital I/O Pin Characteristics .................. ... ... ... .... .......................................... ... ... ...................... 11

Table 2. CS4353 Operational Mode Auto-Detect ...................................................................................... 14

Table 3. Single-speed Mode Standard Frequencies .................... .... ... ... ... ... .... ... ...................................... 14

Table 4. Double-speed Mode Standard Frequencies ............................................................................... 14

Table 5. Quad-speed Mode Standard Frequencies ..................................................................................14

Table 6. Digital Interface Format ............... .......................................... ...................................................... 15

DS803F3 3

1. PIN DESCRIPTIONS

11 12

2021222324

Top-Down (Through Package) View

24-Pin QFN Package

SDIN

LRCK

I²S

/LJ

DEM

1_2VRMS

RESET

FLYP+

VFILT+

FLYN+

CPGND

FLYN-

SCLK

MCLK

DGND

FLYP-

VBIAS

AGND

AOUT_REF

AOUTB

Thermal Pad

VCP

VFILT-

AOUTA

CS4353

Pin Name Pin # Pin Description

SCLK 1 Serial Clock (Input) - Serial clock for the serial audio interface. MCLK 2 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. VL 3 Serial Audio Interface Power (Input) - Positive power for the serial audio interface DGND 4 Digital Ground (Input) - Ground reference for the digital section. FL YP+

FL YPVCP 6

VFILT+ 8 FLYN+

FLYNCPGND 10 Charge Pump Ground (Input) - Ground reference for the Charge Pump section.

VFILT- 12 AOUTB

AOUTA AOUT_REF 14 AGND 16 Analog Ground (Input) - Ground reference for the low voltage analog section.

4 DS803F3

75Step-up Charge Pump Cap Positive/Negative Nodes (Output) - Positive and Negative nodes for the

step-up charge pump’s flying capacitor. Charge Pump and Digital Core Logic Power (Input) - Positive power supply for the step-up and invert-

ing charge pumps as well as the digital core logic sections. Step-up Charge Pump Filter Connection (Output) - Power supply from the step-up charge pump that

provides the positive rail for the output amplifiers

911Inverting Charge Pump Cap Positive/Negative Nodes (Output) - Positive and Negative nodes for the

1315Analog Outputs (Output) - The full-scale analog line output level is specified in the Analog Characteris-

inverting charge pump’s flying capacitor.

Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge pump that provides the negative rail for the output amplifiers.

tics table. Pseudo Diff. Analog Output Reference (Input) - Ground reference for the analog output amplifiers.

This pin must be at the same nominal DC voltage as the AGND pin.

VA 17 Low Voltage Analog Power (Input) - Positive power supply for the analog section. VBIAS 18 Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC.

Reset (Input) - Optional connection for an external reset control. The device enters a powered-down

RESET

state when this pin is set low (GND) OR when the VCP supply falls below the V

“Internal Power-on Reset Threshold Voltages” on page 10.). This pin should be set high (VL) during nor-

threshold (see See

off

mal operation.

1_2VRMS 20

DEM 21

/LJ 22

I²S

LRCK 23

1 or 2 V

selects 1 V De-emphasis (Input) - Selects the standard 50 s/15 s digital de-emphasis filter response for 44.1 kHz

sample rates when enabled. Digital Interface Format (Input) - Selects the serial audio interface format. Setting this pin low (GND)

selects I²S, while setting it high (VL) selects Left-Justified. Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial

audio data line.

Select (Input) - Selects the analog output full-scale voltage. Setting this pin low (GND)

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, while setting it high (VL) selects 2 V

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SDIN 24 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. Thermal Pad -

Thermal Relief Pad - This pad may be soldered to the board, however it MUST be electrically isolated from all board connections.

CS4353

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CS4353

2. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

AGND = DNGD = CPGND = 0 V; all voltages with respect to ground.

Parameters Symbol Min Typ Max Units

DC Power Supply Charge Pump an d Digital Core power (Note 1)

Low Voltage Analog power (Note 1)

Interface power

Ambient Operating Temperature (Power Applied) T

VCP

VA VL

3.13

0.85

-40 - +85 °C

3.3

0.9 to 3.3

3.47

V V V

Note: 1. VCP and VA must be supplied with the same nominal voltage. Additional current draw will occur if the sup-

ply voltages applied to VCP and VA differ by more than 0.5 V.

ABSOLUTE MAXIMUM RATINGS

AGND = DNG D = C P GN D = 0V; all voltages with respect to ground.

Parameters Symbol Min Max Units

DC Power Supply Charge Pump and Digital Core Logic Power

Low Voltage Analog Power

Supply Voltage Difference

Interface Power Input Current, Any Pin Except Supplies I Digital Input Voltage Digital Interface V Analog Input Voltage AOUT_REF V Ambient Operating Temperature (Power Applied) T Storage Temperature T

WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

VCP

|VCP - VA|

in IN-L IN-A

stg

-0.3

-±10mA

-0.3 VL+ 0.4 V

-0.3 0.5 V

-55 +125 °C

-65 +150 °C

3.63

0.5

3.63

V V V V

6 DS803F3

CS4353

VRMS

Vpp

----------=

DAC ANALOG CHARACTERISTICS

Test conditions (unless otherwise specified): TA = 25 °C; VCP = VA = 3.3 V; AOUT_REF = AGND = DGND = CPGND = 0V; VBIAS, VFILT+/-, and FLYP/N+/- capacitors as shown in Figure 3 on page 12; input test signal is a

997 Hz sine wave at 0 dBFS; measurement bandwidth 10 Hz to 20 kHz.

1_2VRMS = 0 1_2VRMS = 1

Parameter Symbol Min Typ Max Min Typ Max Unit

Dynamic Performance, Fs = 48, 96, and 192 kHz (Notes 2, 3, 4)

Dynamic Range 24-bit A-Weighted

unweighted

16-bit A-Weighted

unweighted

Total Harmonic Distortion + Noise

24-bit 0 dB

-20 dB

-60 dB

16-bit 0 dB

-20 dB

-60 dB Idle Channel Noise / Signal-to-Noise Ratio (A-wt) - 100 - - 106 - dB Interchannel Isolation (1 kHz) - 115 - - 115 - dB

THD+N

Analog Output (Note 5)

Full Scale AOUTx Output Voltage (Notes 4, 6, 7) 1.021.081.132.042.152.26V

Max Current Draw from an AOUTx Pin I Interchannel Gain Mismatch - 0.1 - - 0.1 - dB Output Offset - ±5 ±8 - ±5 ±8 mV Gain Drift - 100 - - 100 - ppm/°C Output Impedance Z AC-Load Resistance R Load Capacitance C AOUT_REF Rejection (Notes 8, 9)AOR-40- -40-dB

Analog Reference Input

AOUT_REF Input Voltage (Note 10) --0.2--0.2Vpp

OUTmax

OUT

L L

94 91

2.89 3.05 3.20 5.78 6.09 6.40 V

5--5--k

100

-575- -575- A

-100- -100- 

- - 1000 - - 1000 pF

92 89

-93

-77

-37

-93

-75

-29

-87

-71

-31

100

106 103

98 95

-93

-83

-43

-93

-75

-35

-87

-77

-37

dB dB dB dB

dB dB dB dB dB dB

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Notes: 2. Measured at the output of the external LPF on AOUTx as shown in Figure 3 on page 12.

3. One LSB of triangular PDF dither is added to data.

4. Measured with the specified minimum AC-Load Resistance present on the AOUTx pins.

5. Measured between the AOUTx and AOUT_REF pins.

6. External impedance between the AOUTx pin and the load will lower the voltage delivered to the load.

7. V

is the controlling specification. V

specification valid for sine wave signals only.

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Note that for sine wave signals:

8. Measured with AOUT_REF connected directly to ground. External impedance between AOUT_REF and ground will lower the AOUT_REF rejection.

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CS4353

AOR

20 log

AOUT_REF

AOUT_REF A OUTx–

---------------------------------------------------------





=

9. SDIN = 0. AOUT_REF input test signal is a 60 Hz, 50 mVpp sine wave. Measured by applying the test signal into the AOUT_REF pin and measuring the resulting output amplitude on the AOUTx pin. Specification calculated by:

10. Applying a DC voltage on the AOUT_RE F pin will cause a DC offset on the DAC output. See Section

4.1.3 for more information.

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

The filter characteristics have been norma lized to th e sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.

Parameter Min Typ Max Unit

Single-Speed Mode - 48 kHz

Passband (Note 11) to -0.01 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB StopBand 0.547 - - Fs StopBand Attenuation (Note 12) 102 - - dB Total Group Delay (Fs = Sample Rate) - 9.4/Fs - s Intra-channel Phase Deviation - - ±0.56/Fs s Inter-channel Phase Deviation - - 0 s De-emphasis Error (Note 13) (Relative to 1 kHz) Fs = 44.1 kHz - - ±0.14 dB

Double-Speed Mode - 96 kHz

Passband (Note 11) to -0.01 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 dB StopBand .583 - - Fs StopBand Attenuation (Note 12) 80 - - dB Total Group Delay (Fs = Sample Rate) - 4.6/Fs - s Intra-channel Phase Deviation - - ±0.03/Fs s Inter-channel Phase Deviation - - 0 s

Quad-Speed Mode - 192 kHz

Passband (Note 11) to -0.01 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 dB StopBand .635 - - Fs StopBand Attenuation (Note 12) 90 - - dB Total Group Delay (Fs = Sample Rate) - 4.7/Fs - s

High-Pass Filter Characteristics

Passband (Note 11) to -0.05 dB corner

to -3 dB corner Passband Ripple - - 0.01 dB Phase Deviation @ 20 Hz - - 1.34 Deg Filter Settling Time (input signal goes to 95% of its final value) - 5x10

Notes: 11. Response is clock-dependent and will scale with Fs.

12. For Single- and Double-Speed Mode, the Measurement Bandwidth is from stop band to 3 Fs. For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.

13. De-emphasis is available only in Single-Speed Mode.

14. Amplitude vs. Frequency plots of this data are available in “Digital Filter Response Plots” on page 21.

0 0

9.00x10

9.74x10

-5

-6

/Fs - s

.454 .499

.430 .499

.105 .490

Fs Fs

8 DS803F3

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