Cirrus Logic CS4351 User Manual
u
CS4351
192 kHz Stereo DAC with 2 Vrms Line Out
Features
! Multi-Bit Delta-Sigma Modulator
! 24-Bit Conversion
! Up to 192 kHz Sample Rates
! 112 dB Dynamic Range
! -100 dB THD+N
! +3.3 V, +9 to 12 V, and VL Power Supplies
! 2 Vrms Output into 5 kΩ AC Load
! Digital Volume Control with Soft Ramp
– 119 dB Attenuation
– 1/2 dB Step Size
– Zero Crossing Click-Free Transitions
! ATAPI Mixing
! Low Clock Jitter Sensitivity
! Popguard
and Pops
®
Technology for Control of Clicks
Description
The CS4351 is a complete stereo digital-to-analog system including digital interpolation, fifth-order multi-bit
delta-sigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing, analog filtering,
and on-chip 2 Vrms line-level driver. The advantages of
this architecture include ideal differential linearity, no
distortion mechanisms due to resistor matching errors,
no linearity drift over time and tem perature, high tolerance to clock jitter, and a minimal set of external
components.
The CS4351 is available in a 20-pin TSSOP package in
both Commercial (-10°C - +70°C) and Automotive
grades (-40°C to +85°C). The CDB4351 Customer
Demonstration board is also available for device evaluation and implementation suggestions. Please see
“Ordering Information” on page 37 for complete details.
These features are ideal for cost-sensitive, 2-channel
audio systems including DVD players, A/V receivers,
set-top boxes, digital TVs and VCRs, mini-component
systems, and mixing consoles.
V to 3.3V
ware or I2C/SPI
Con t r ol Data
Reset
rial Audio Input
Level Translator
Register/Hardware
Configuration
PCM
Serial
Interfa ce
Auto Speed Mode
Detect
Interpolation
Fil ter wit h
Volume Contr ol
Interpolation
Fil ter wit h
Volume Cont r ol
3.3 V
Multibit
∆Σ Modulator
Multibit
∆Σ Modulator
DAC
DAC
Internal V oltage
Reference
9 V to 12 V
Amp
+
Filter
Amp
+
Filter
External
Mute
Contr ol
2 Vrms Line Level
Left Chann el Outp
2 Vrms Line Level
Right Channe l
Output
Left and Right
Mute Controls
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
DECEMBER '05
DS566F1
TABLE OF CONTENTS
1. PIN DESCRIPTION ............................. ... ... ....................................... ... ... .... ... ... ... .... ... ... ........................ 5
2. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 6
SPECIFIED OPERATING CONDITIONS.............................................................................................. 6
ABSOLUTE MAXIMUM RATINGS........................................................................................................6
DAC ANALOG CHARACTERISTICS .................................................................................................... 7
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .......................................8
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .......................................9
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE ...................................................... 10
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT......................................... 12
DIGITAL CHARACTERISTICS............................... ... .... ... ... .......................................... ... ... ................ 13
POWER AND THERMAL CHARACTERISTICS ................................................................................. 13
3. TYPICAL CONNECTION DIAGRAM ........... .... ... ... ... .... ... ... .......................................... ... ... ................ 14
4. APPLICATIONS .................................................................................................................................. 15
4.1 Sample Rate Range/Operational Mode Detect ................................... ......................................... 15
4.1.1 Auto-Detect Enabled ........................................................................................................ 15
4.1.2 Auto-Detect Disabled ....................................................................................................... 15
4.2 System Clocking ........................................................................................................................... 15
4.3 Digital Interface Format ................................................................................................................ 16
4.3.1 Stand-Alone Mode ........................................................................................................... 16
4.3.2 Control Port Mode ........................................................................................................... 16
4.4 De-Emphasis Control ................................................................................................................... 17
4.4.1 Stand-Alone Mode ........................................................................................................... 18
4.4.2 Control Port Mode ............................................................................................................ 18
4.5 Recommended Power-Up Sequence ........................................................................................... 18
4.5.1 Stand-Alone Mode ........................................................................................................... 18
4.5.2 Control Port Mode ............................................................................................................ 18
4.6 Popguard
4.6.1 Power-Up ......................................................................................................................... 18
4.6.2 Power-Down .................................................................................................................... 19
4.6.3 Discharge Time ................................................................................................................ 19
4.7 Mute Control ................................................................................................................................. 19
4.8 Grounding and Power Supply Arrangements ............................................................................... 19
4.8.1 Capacitor Placement ........................................................................................................ 19
4.9 Control Port Interface ................................................................................................................... 20
4.9.1 MAP Auto Increment ........................................................................................................ 20
4.9.2 I²C Mode .......................................................................................................................... 20
4.9.3 SPI Mode ......................................................................................................................... 21
4.10 Memory Address Pointer (MAP) .................... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ................................ 22
4.10.1 INCR (Auto Map Increment Enable) .............................................................................. 22
4.10.2 MAP (Memory Address Pointer) .................................................................................... 22
5. REGISTER QUICK REFERENCE .......................................... .... ... ... ... ... .... ... ... ................................... 23
6. REGISTER DESCRIPTION .......... .... .......................................... ... ... ................................................... 24
6.1 Chip ID - Register 01h .................................................................................................................. 24
6.2 Mode Control 1 - Register 02h ..................................................................................................... 24
6.2.1 Digital Interface Format (DIF2:0) Bits 6-4 ........................................................................ 24
6.2.2 De-Emphasis Control (DEM1:0) Bits 3-2. ........................................................................ 24
6.2.3 Functional Mode (FM) Bits 1-0 ............................ .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 25
6.3 Volume Mixing and Inversion Control - Register 03h ................................................................... 25
6.3.1 Channel A Volume = Channel B Volume (VOLB=A) Bit 7 ............................................... 25
6.3.2 Invert Signal Polarity (Invert_A) Bit 6 ............................................................................... 25
6.3.3 Invert Signal Polarity (Invert_B) Bit 5 ............................................................................... 25
®
Transient Control ....................................................................................................... 18
CS4351
®
FORMAT........................................... 11
2 DS566F1
CS4351
6.3.4 ATAPI Channel Mixing and Muting (ATAPI3:0) Bits 3-0 .................................................. 26
6.4 Mute Control - Register 04h ........... ... ... .... ... .......................................... ... ... ................................ 27
6.4.1 Auto-Mute (AMUTE) Bit 7 ................ ... ... .... ... ... ... .... ... ... ... ... .... ... ...................................... 27
6.4.2 AMUTEC = BMUTEC (MUTEC A=B) Bit 5 ...................................................................... 27
6.4.3 A Channel Mute (MUTE_A) Bit 4
B Channel Mute (MUTE_B) Bit 3 .................................................................................... 27
6.5 Channel A Volume Control - Register 05h
Channel B Volume Control - Register 06h ................................................................................ 27
6.5.1 Digital Volume Control (VOL7:0) Bits 7-0 ........................................................................ 28
6.6 Ramp and Filter Control - Register 07h ........................................................................................ 28
6.6.1 Soft Ramp and Zero Cross Control (SZC1:0) Bits 7-6 ..................................................... 28
6.6.2 Soft Volume Ramp-Up After Error (RMP_UP) Bit 5 ......................................................... 29
6.6.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN) Bit 4 ....................................... 29
6.6.4 Interpolation Filter Select (FILT_SEL) Bit 2 ..................................................................... 29
6.7 Misc Control - Register 08h .......................................................................................................... 29
6.7.1 Power Down (PDN) Bit 7 ................................................................................................. 30
6.7.2 Control Port Enable (CPEN) Bit 6 ....................................... .... ... ...................................... 30
6.7.3 Freeze Controls (Freeze) Bit 5 ......................................................................................... 30
7. DIGITAL FILTER RESPONSE PLOTS ............................................................................................. 31
8. PARAMETER DEFINITIONS ............................................................................................................... 35
9. PACKAGE DIMENSIONS .................................................................................................................. 36
10. ORDERING INFORMATION ............................................................................................................. 37
11. REVISION HISTORY ......................................................................................................................... 37
LIST OF FIGURES
Figure 1. Serial Input Timing..................................................................................................................... 10
Figure 2. Control Port Timing - I²C Format................................................................................................ 11
Figure 3. Control Port Timing - SPI Format (Write)................................................................................... 12
Figure 4. Typical Connection Diagram............................ .... ... ... ... .... ... ... ... ... .... ... ... ... .... ............................ 14
Figure 5. Left-Justified up to 24-Bit Data................................................................................................... 17
Figure 6. I²S, up to 24-Bit Data ................................................................................................................. 17
Figure 7. Right-Justified Data.................................................................................................................... 17
Figure 8. De-Emphasis Curve................................................................................................................... 17
Figure 9. Control Port Timing, I²C Mode................................................................................................... 21
Figure 10.Control Port Timing, SPI mode .................................................................................................. 22
Figure 11.De-Emphasis Curve................................................................................................................... 24
Figure 12.ATAPI Block Diagram ................................................................................................................ 26
Figure 13.Single-Speed (fast) Stopband Rejection.................................................................................... 31
Figure 14.Single-Speed (fast) Transition Band.......................................................................................... 31
Figure 15.Single-Speed (fast) Transition Band (detail).............................................................................. 31
Figure 16.Single-Speed (fast) Passband Ripple........................................................................................ 31
Figure 17.Single-Speed (slow) Stopband Rejection .................................................................................. 31
Figure 18.Single-Speed (slow) Transition Band......................................................................................... 31
Figure 19.Single-Speed (slow) Transition Band (detail)............................................................................. 32
Figure 20.Single-Speed (slow) Passband Ripple....................................................................................... 32
Figure 21.Double-Speed (fast) Stopband Rejection ......................... ......................................... .... ... ... ...... 32
Figure 22.Double-Speed (fast) Transition Band......................................................................................... 32
Figure 23.Double-Speed (fast) Transition Band (detail).......... ... ... .... ... ... ... ... .... ... ... ... ................................ 32
Figure 24.Double-Speed (fast) Passband Ripple....................................................................................... 32
Figure 25.Double-Speed (slow) Stopband Rejection................................................................................. 33
Figure 26.Double-Speed (slow) Transition Band....................................................................................... 33
Figure 27.Double-Speed (slow) Transition Band (detail)........................................................................... 33
Figure 28.Double-Speed (slow) Passband Ripple..................................................................................... 33
DS566F1 3
Figure 29.Quad-Speed (fast) Stopband Rejection..................................................................................... 33
Figure 30.Quad-Speed (fast) Transition Band ........................................................................................... 33
Figure 31.Quad-Speed (fast) Transition Band (detail) ............................................................................... 34
Figure 32.Quad-Speed (fast) Passband Ripple ......................................................................................... 34
Figure 33.Quad-Speed (slow) Stopband Rejection........................... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 34
Figure 34.Quad-Speed (slow) Transition Band.......................................................................................... 34
Figure 35.Quad-Speed (slow) Transition Band (detail).............................................................................. 34
Figure 36.Quad-Speed (slow) Passband Ripple............................... ... ... ... ... ............................................. 34
LIST OF TABLES
Table 1. CS4351 Auto-Detect.................................................................................................................... 15
Table 2. CS4351 Mode Select................................................................................................................... 15
Table 3. Single-Speed Mode Standard Frequencies.................................................................................16
Table 4. Double-Speed Mode Standard Frequencies................................................................................ 16
Table 5. Quad-Speed Mode Standard Frequencies .................................................................................. 16
Table 6. Digital Interface Format - Stand-Alone Mode............................................................................... 16
Table 7. Digital Interface Formats.............................................................................................................. 24
Table 8. ATAPI Decode ............................................................................................................................. 26
Table 9. Example Digital Volume Settings....... ... .................................................................................... ... 28
Table 10. Revision History......................................................................................................................... 37
CS4351
4 DS566F1
1. PIN DESCRIPTION
CS4351
SDIN VL
SCLK AMUTEC
LRCK AOUTA
MCLK VA_H
VD GND
GND AOUTB
DIF1(SCL/CCLK) BMUTEC
DIF0(SDA/CDIN) VQ
DEM(AD0/CS
) VBIAS
RST
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VA
Pin Name # Pin Description
SDIN 1 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
SCLK 2 Serial Clock (Input) - Serial clock for the serial audio interface.
LRCK 3
MCLK 4 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VD 5 Digital Power (Input) - Positive power supply for the digital section.
GND
RST
VA 11 Low Voltage Analog Power (Input) - Positive power supply for the analog section.
VBIAS 12 Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC.
VQ 13 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
VA_H 17 High Voltage Analog Power (Input) - Positive power supply for the analog section.
VL 20 Serial Audio Interface Power (Input) - Positive power for the serial audio interface
BMUTEC
AMUTEC
AOUTB
AOUTA
Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial
audio data line.
6
Ground (Input) - Ground reference.
16
Reset (Input) - Powers down device and resets all internal resisters to their default settings when
10
enabled.
14
Mute Control (Output) - Control signal for optional mute circuit.
19
1518Analog Outputs (Output) - The full scale analog line output level is specified in the Analog Character-
istics table.
Control Port Definitions
SCL/CCLK 7 Serial Control Port Clock (Input) - Serial clock for the control port inter fa ce.
SDA/CDIN 8 Serial Control Data (Input/Output) - Input/Output for I²C data. Input for SPI data.
AD0/CS
9 Address Bit 0 / Chip Select (Input) - Chip address bit in I²C Mode. Control Port enable in SPI Mode.
Stand-Alone Definitions
DIF0
DIF1
DEM 9
87Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock,
Serial Clock, and Serial Audio Data.
De-emphasis (Input) - Selects the standard 15 µs/50 µs digital de-emphasis filter response for 44.1
kHz sample rates
DS566F1 5
CS4351
2. CHARACTERISTICS AND SPECIFICATIONS
(Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions.
Typical specifications are derived from performance measurements at T
= 25 °C, VA_H = 12 V, VA = 3.3 V,
A
VD = 3.3 V.)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V; all voltages with respect to ground.)
Parameters Symbol Min Typ Max Units
DC Power Supply High Voltage Analog power
Low Voltage Analog power
Digital power
Interface power
Specified Temperature Range -CZZ
-DZZ
V
A_H
V
V
V
T
T
8.55
A
D
L
A
A
3.13
3.13
1.7
-10
-40
12
3.3
3.3
3.3
12.6
3.47
3.47
3.47
-
-
70
85
V
V
V
V
°C
°C
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V; all voltages with respect to ground.)
Parameters Symbol Min Max Units
DC Power Supply High Voltage Analog power
Low Voltage Analog power
Digital power
Interface power
Input Current, Any Pin Except Supplies I
Digital Input Voltage Digital Interface V
Ambient Operating Temperature (power applied) T
Storage Temperature T
Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
V
A_H
V
V
V
in
IN-L
stg
-0.3
A
D
L
A
-0.3
-0.3
-0.3
-±10mA
-0.3 VL+ 0.4 V
-55 125 °C
-65 150 °C
14
3.63
3.63
3.63
V
V
V
V
6 DS566F1
CS4351
DAC ANALOG CHARACTERISTICS
(Test conditions (unless otherwise specified): input test signal is a 997 Hz sine wave at 0 dBFS; measurement
bandwidth 10 Hz to 20 kHz)
Parameter Symbol Min Typ Max Unit
All Speed Modes Fs = 48, 96, and 192 kHz
Dynamic Range (Note 1) 24-bit unweighted
A-Weighted
16-bit unweighted
A-Weighted
Total Harmonic Distortion + Noise (Note 1)
24-bit 0 dB
-20 dB
-60 dB
16-bit 0 dB
-20 dB
-60 dB
All Speed Modes
Idle Channel Noise / Signal-to-noise ratio - 109 - dB
Interchannel Isolation (1 kHz) - 100 - dB
THD+N -
Analog Output - All Modes
Full Scale Output Voltage 1.85 2.00 2.15 Vrms
Common Mode Voltage V
Max DC Current draw from an AOUT pin I
Max Current draw from VQ I
Interchannel Gain Mismatch - 0.1 - dB
Gain Drift - -10 0 - ppm/°C
Output Impedance Z
AC-Load Resistance R
Load Capacitance C
Q
OUTmax
Qmax
OUT
L
L
99
102
-
-
-
-
-
-
-
-
-4-Vdc
-10-µA
-1-µA
-50-Ω
5--kΩ
--100pF
109
112
95
98
-100
-89
-49
-92
-75
-35
-90
-79
-39
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Notes:
1. One-half LSB of triangular PDF dither is added to data.
DS566F1 7
CS4351
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
(The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. See
Parameter
Combined Digital and On-Chip Analog Filter Response - Single-Speed Mode - 48 kHz
Passband (Note 3) to -0.01 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB
StopBand 0.547 - - Fs
StopBand Attenuation (Note 4) 102 - - dB
Total Group Delay (Fs = Output Sample Rate) - 9.4/Fs - s
Intra-channel Phase Deviation - - ±0.56/Fs s
Inter-channel Phase Deviation - - 0 s
De-emphasis Error (Note 5) Fs = 32 kHz
(Relative to 1 kHz) Fs = 44.1 kHz
Combined Digital and On-Chip Analog Filter Response - Double-Speed Mode - 96 kHz
Passband (Note 3) to -0.01 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 dB
StopBand .583 - - Fs
StopBand Attenuation (Note 4) 80 - - dB
Total Group Delay (Fs = Output Sample Rate) - 4.6/Fs - s
Intra-channel Phase Deviation - - ±0.03/Fs s
Inter-channel Phase Deviation - - 0 s
Combined Digital and On-Chip Analog Filter Response - Quad-Speed Mode - 192 kHz
Passband (Note 3) to -0.01 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 dB
StopBand .635 - - Fs
StopBand Attenuation (Note 4) 90 - - dB
Total Group Delay (Fs = Output Sample Rate) - 4.7/Fs - s
Intra-channel Phase Deviation - - ±0.01/Fs s
Inter-channel Phase Deviation - - 0 s
(Note 6)
to -3 dB corner
Fs = 48 kHz
to -3 dB corner
to -3 dB corner
0
0
-
-
-
0
0
0
0
Fast Roll-Off
-
-
-
-
-
-
-
-
-
.454
.499
±0.23
±0.14
±0.09
.430
.499
.105
.490
UnitMin Typ Max
Fs
Fs
dB
dB
dB
Fs
Fs
Fs
Fs
8 DS566F1
CS4351
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
(Continued)
Slow Roll-Off (Note 2)
Parameter
Single-Speed Mode - 48 kHz
Passband (Note 3) to -0.01 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB
StopBand .583 - - Fs
StopBand Attenuation (Note 4) 64 - - dB
Total Group Delay (Fs = Output Sample Rate) - 6.5/Fs - s
Intra-channel Phase Deviation - - ±0.14/Fs s
Inter-channel Phase Deviation - - 0 s
De-emphasis Error (Note 5) Fs = 32 kHz
(Relative to 1 kHz) Fs = 44.1 kHz
Fs = 48 kHz
0
0
-
-
-
-
-
-
-
-
0.417
0.499
±0.23
±0.14
±0.09
Double-Speed Mode - 96 kHz
Passband (Note 3)) to -0.01 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 dB
StopBand .792 - - Fs
StopBand Attenuation (Note 4) 70 - - dB
Total Group Delay (Fs = Output Sample Rate) - 3.9/Fs - s
Intra-channel Phase Deviation - - ±0.01/Fs s
Inter-channel Phase Deviation - - 0 s
0
0
-
-
.296
.499
Quad-Speed Mode - 192 kHz
Passband (Note 3)) to -0.0 1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 dB
StopBand .868 - - Fs
StopBand Attenuation (Note 4) 75 - - dB
Group Delay - 4.2/Fs - s
Intra-channel Phase Deviation - ±0.01/Fs s
Inter-channel Phase Deviation - - 0 s
0
0
-
-
.104
.481
UnitMin Typ Max
Fs
Fs
dB
dB
dB
Fs
Fs
Fs
Fs
Notes:
2. Slow Roll-off interpolation filter is only available in Control Port mode.
3. Response is clock dependent and will scale with Fs.
4. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.
5. De-emphasis is available only in Single-Speed Mode; Only 44.1 kHz De-emphasis is available in StandAlone Mode.
6. Amplitude vs. Frequency plots of this data are available in the “Digital Filter Response Plots” on
page 31.
DS566F1 9
CS4351
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
Parameters Symbol Min Max Units
MCLK Frequency 1.024 51.2 MHz
MCLK Duty Cycle 45 55 %
Input Sample Rate (Manual selection) Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Input Sample Rate (Auto selection) Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
LRCK Duty Cycle 40 60 %
SCLK Pulse Width Low t
SCLK Pulse Width High t
SCLK Period Single-Speed Mode t
Fs
Fs
Fs
Fs
Fs
Fs
sclkl
sclkh
sclkw
4
50
100
4
84
170
50
100
200
50
100
200
20 - ns
20 - ns
1
--------------------- 128()Fs
--
kHz
kHz
kHz
kHz
kHz
kHz
Double-Speed Mode t
Quad-Speed Mode t
SCLK rising to LRCK edge delay t
SCLK rising to LRCK edge setup time t
SDIN valid to SCLK rising setup time t
SCLK rising to SDIN hold time t
LRCK
t
t
slrd
slrs
t
sclkl
SCLK
t
sdlrs
t
sdh
sclkw
sclkw
slrd
slrs
sdlrs
sdh
t
sclkh
1
-----------------64()Fs
2
-----------------
MCLK
--
--
23 - ns
20 - ns
20 - ns
20 - ns
SDATA
Figure 1. Serial Input Timing
10 DS566F1
Switching Characteristics - Control Port - I²C® Format
p
(Inputs: Logic 0 = GND, Logic 1 = VL, CL=20pF)
Parameter Symbol Min Max Unit
SCL Clock Frequency f
Rising Edge to Start t
RST
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 7) t
SDA Setup time to SCL Rising t
Rise Time of SCL and SDA trc, t
Fall Time SCL and SDA t
Setup Time for Stop Condition t
Acknowledge Delay from SCL Falling t
Notes:
buf
hdst
low
high
sust
hdd
sud
fc
susp
ack
scl
irs
, t
rc
fc
CS4351
- 100 kHz
500 - ns
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
4.7 - µs
0-µs
250 - ns
-1µs
-300ns
4.7 - µs
300 1000 ns
7. Data must be held for sufficient time to bridge the transition time, t
RST
t
irs
Stop Sta rt
SDA
SCL
t
buf
t
hdst
t
low
t
t
high
hdd
t
sud
t
ack
Figure 2. Control Port Timing - I²C Format
, of SCL.
fc
Repeated
Start
t
t
sust
t
hdst
Stop
rd
t
t
rc
t
fd
fc
t
sus
DS566F1 11
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VL, CL=20pF)
Parameter Symbol Min Max Unit
CCLK Clock Frequency f
RST
Rising Edge to CS Falling t
CCLK Edge to CS
CS High Time Between Transmissions t
CS Falling to CCLK Edge t
CCLK Low Time t
CCLK High Time t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 9) t
Rise Time of CCLK and CDIN (Note 10) t
Fall Time of CCLK and CDIN (Note 10) t
Falling (Note 8) t
Notes:
sclk
srs
spi
csh
css
scl
sch
dsu
dh
r2
f2
-6MHz
500 - ns
500 - ns
1.0 - µs
20 - ns
66 - ns
66 - ns
40 - ns
17 - ns
- 100 ns
- 100 ns
CS4351
8. t
only needed before first falling edge of CS after RST rising edge. t
spi
= 0 at all other times.
spi
9. Data must be held for sufficient time to bridge the transition time of CCLK.
10. For F
< 1 MHz.
SCK
RST
t
srs
CS
t
t
spi
css
t
scl
t
sch
CCLK
t
r2
t
f2
CDIN
t
t
dsu
dh
t
csh
Figure 3. Control Port Timing - SPI Format (Write)
12 DS566F1
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