Cirrus Logic CS4350 User Manual
192-kHz Stereo DAC with Integrated PLL
PCM
Serial
Interface
Serial Audio Input
Right
Channel
Output
Left
Channel
Output
Reset
3.3 V to 5.0 V
Register/
Hardware
Configuration
Hardware or I2C/
SPI Control Data
3.3 V to 5.0 V
LRCK
RMCK
RMCK
Recovered MCLK
1.5 V to 5.0 V
Internal Voltage
Reference
and Regulation
Phase Locked Loop
Interpolation
Filter with
Volume
Control
Interpolation
Filter with
Volume
Control
Multibit
Modulator
Multibit
Modulator
Level Translator Level Translator
Amp
+
Filter
Amp
+
Filter
Left and
Right Mute
Controls
External
Mute
Control
DAC
DAC
Features
Advanced multibit delta-sigma architecture
109 dB dynamic range
-91 dB THD+N
24-bit conversion
Supports audio sample rates up to 192 kHz
Low-latency digital filtering
Single-ended or differential analog output
architecture
Integrated PLL locks to incoming left-right
clock
– Eliminates the need for external master-
clock routing
– Reduces interference and jitter sensitivity
– No external loop filter components required
Automatic sample-rate range detection
CS4350
Popguard
pops
Hardware popguard disable for fast startups
Supports all standard serial audio formats
including time-division multiplexed (TDM)
+1.5- to 5.0-V logic supplies for serial port
+3.3- to 5.0-V control port interface
Control Port Mode Features
SPI™ and I²C
ATAPI mixing
Mute control for individual channels
Digital volume control with soft ramp
– 127.5 dB attenuation
– 1/2 dB step size
– Zero-crossing click-free transitions
®
technology for control of clicks and
™
Modes
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2013
(All Rights Reserved)
APR ‘13
DS691F2
CS4350
Description
The CS4350 is a complete stereo digital-to-analog system including PLL-based master clock derivation, digital interpolation, 5th-order multibit delta-sigma digital-to-analog conversion, digital de-emphasis, volume control, channel
mixing, and analog filtering. The advantages of this architecture include ideal differential linearity, no distortion
mechanisms due to resistor matching errors, no linearity drift over time and temperature, high tolerance to clock jitter, and a minimal set of external components.
The CS4350 supports all standard digital audio interface formats, including TDM.
The CS4350 is available in a 24-pin TSSOP package in both Commercial (-40° to +85°C) and Automotive grades
(-40° to +105°C). The CDB4350 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on page 38 for complete ordering information.
These features are ideal for cost-sensitive, two-channel audio systems, including DVD players and recorders, settop boxes, digital TVs, mini-component systems, mixing consoles and automotive audio systems.
2 DS691F2
TABLE OF CONTENTS
1 PIN DESCRIPTION................................................................................................................................... 6
2 CHARACTERISTICS AND SPECIFICATIONS........................................................................................ 7
2.1 Recommended Operating Conditions ............................................................................................. 7
2.2 Absolute Maximum Ratings ............................................................................................................. 7
2.3 DAC Analog Characteristics - Commercial (-CZZ) .......................................................................... 8
2.4 DAC Analog Characteristics - Automotive (-DZZ) ........................................................................... 9
2.5 Combined Interpolation and On-Chip Analog Filter Response...................................................... 11
2.6 Switching Specifications - Serial Audio Interface...........................................................................12
2.7 Switching Characteristics - Control Port - I²C Format.................................................................... 13
2.8 Switching Characteristics - Control Port - SPI Format................................................................... 14
2.9 Digital Characteristics .................................................................................................................... 15
2.10 Power and Thermal Characteristics............................................................................................. 15
3 TYPICAL CONNECTION DIAGRAM ................................................................................................... 16
4 APPLICATIONS ..................................................................................................................................... 17
4.1 Sample Rate Range and Oversampling Mode Detect................................................................... 17
4.1.1 Sample Rate Auto-Detect .................................................................................................... 17
4.2 System Clocking ............................................................................................................................ 17
4.2.1 Recovered Master Clock (RMCK)........................................................................................ 17
4.3 Digital Interface Format ................................................................................................................. 18
4.3.1 Time-Division Multiplex (TDM) Mode ................................................................................... 19
4.4 De-Emphasis ................................................................................................................................. 20
4.5 Mute Control .................................................................................................................................. 20
4.6 Recommended Power-Up Sequence ............................................................................................ 20
4.6.1 Stand-Alone Mode ............................................................................................................... 20
4.6.2 Control Port Mode ................................................................................................................ 21
4.7 Popguard Transient Control .......................................................................................................... 21
4.7.1 Power-Up ............................................................................................................................. 21
4.7.2 Power-Down......................................................................................................................... 21
4.7.3 Discharge Time .................................................................................................................... 21
4.8 Analog Output and Filtering ........................................................................................................... 22
4.9 Grounding and Power Supply Arrangements ................................................................................ 22
4.9.1 Capacitor Placement............................................................................................................ 22
5 STAND-ALONE OPERATION................................................................................................................ 23
5.1 Serial Port Format Selection.......................................................................................................... 23
5.2 De-Emphasis Control .................................................................................................................... 23
5.3 Popguard Transient Control .......................................................................................................... 23
6 CONTROL PORT OPERATION ............................................................................................................. 23
6.1 MAP Auto Increment ..................................................................................................................... 23
6.2 I²C Mode........................................................................................................................................ 23
6.2.1 I²C Write ............................................................................................................................... 24
6.2.2 I²C Read............................................................................................................................... 24
6.3 SPI Mode....................................................................................................................................... 25
6.3.1 SPI Write .............................................................................................................................. 25
6.3.2 SPI Read.............................................................................................................................. 25
6.4 Memory Address Pointer (MAP) ................................................................................................... 26
6.4.1 INCR (Auto Map Increment Enable) .................................................................................... 26
6.4.2 MAP (Memory Address Pointer) .......................................................................................... 26
7 REGISTER QUICK REFERENCE .......................................................................................................... 27
8 REGISTER DESCRIPTION .................................................................................................................... 28
8.1 Device and Revision ID - Register 01h.......................................................................................... 28
8.2 Mode Control - Register 02h ......................................................................................................... 28
8.2.1 Digital Interface Format (DIF[2:0]) Bits 6-4 .......................................................................... 28
CS4350
DS691F2 3
CS4350
8.2.2 De-Emphasis Control (DEM[1:0]) Bits 3-2 ........................................................................... 29
8.2.3 Functional Mode (FM[1:0]) Bits 1-0...................................................................................... 29
8.3 Volume Mixing and Inversion Control - Register 03h .................................................................... 29
8.3.1 Channel A Volume = Channel B Volume (VOLB=A) Bit 7 ................................................... 29
8.3.2 Invert Signal Polarity (INVERT_A) Bit 6 ............................................................................... 29
8.3.3 Invert Signal Polarity (INVERT_B) Bit 5 ............................................................................... 30
8.3.4 ATAPI Channel Mixing and Muting (ATAPI[3:0]) Bits 3-0 .................................................... 30
8.4 Mute Control - Register 04h .......................................................................................................... 31
8.4.1 Auto-Mute (AMUTE) Bit 7 .................................................................................................... 31
8.4.2 AMUTEC = BMUTEC (MUTEC A=B) Bit 5 .......................................................................... 31
8.4.3 Channel A Mute (MUTE_A) Bit 4 & Channel B Mute (MUTE_B) Bit 3 ................................. 31
8.5 Channel A & B Volume Control - Register 05h & 06h ................................................................... 32
8.6 Ramp and Filter Control - Register 07h ......................................................................................... 32
8.6.1 Soft Ramp and Zero Cross Control (SZC[1:0]) Bits 7-6 ....................................................... 32
8.6.2 Soft Volume Ramp-Up after Error (RMP_UP) Bit 5 ............................................................. 33
8.6.3 Soft Ramp-Down before Filter Mode Change (RMP_DN) Bit 4 ........................................... 33
8.6.4 Interpolation Filter Select (FILT_SEL) Bit 2.......................................................................... 33
8.7 Misc. Control - Register 08h .......................................................................................................... 33
8.7.1 Power Down (PDN) Bit 7...................................................................................................... 33
8.7.2 Freeze Controls (FREEZE) Bit 5.......................................................................................... 34
8.7.3 Popguard Enable (POPG_EN) Bit 4 .................................................................................... 34
8.7.4 RMCK control (RMCK_CTRL[1:0]) Bits 3:2 ......................................................................... 34
8.7.5 RMCK Ratio Select (R_SELECT[1:0]) Bits 2:1 .................................................................... 34
9 FILTER PLOTS ................................................................................................................................... 35
10 PARAMETER DEFINITIONS................................................................................................................ 36
11 PACKAGE DIMENSIONS .................................................................................................................... 37
12 THERMAL CHARACTERISTICS ......................................................................................................... 37
13 ORDERING INFORMATION ................................................................................................................ 38
14 REVISION HISTORY ........................................................................................................................... 38
4 DS691F2
LIST OF FIGURES
Figure 1. Equivalent Output Load .............................................................................................................. 10
Figure 2. Maximum Loading....................................................................................................................... 10
Figure 3. THD+N vs Output Amplitude for VA = 5.0 V ............................................................................... 10
Figure 4. THD+N vs Output Amplitude for VA = 3.3 V ............................................................................... 10
Figure 5. THD+N vs Output Amplitude for VA = 3.14 V ............................................................................. 10
Figure 6. Serial Port Timing, Non-TDM Mode............................................................................................ 13
Figure 7. Serial Port Timing, TDM Mode.................................................................................................... 13
Figure 8. Control Port Timing - I²C Format................................................................................................. 13
Figure 9. Control Port Timing - SPI Mode .................................................................................................. 14
Figure 10. Typical Connection Diagram..................................................................................................... 16
Figure 11. Left-Justified up to 24-Bit Data.................................................................................................. 18
Figure 12. I²S, up to 24-Bit Data ................................................................................................................ 18
Figure 13. Right-Justified Data................................................................................................................... 18
Figure 14. TDM Mode Connection Diagram .............................................................................................. 19
Figure 15. TDM Mode Timing .................................................................................................................... 19
Figure 16. De-Emphasis Curve.................................................................................................................. 20
Figure 17. Differential to Single-Ended Output Filter ................................................................................. 22
Figure 18. Passive Single-Ended Output Filter .......................................................................................... 22
Figure 19. Control Port Timing, I²C Mode .................................................................................................. 25
Figure 20. Control Port Timing, SPI Mode ................................................................................................. 26
Figure 21. De-Emphasis Curve.................................................................................................................. 29
Figure 22. ATAPI Block Diagram ............................................................................................................... 30
Figure 23. Stopband Rejection (fast), all Modes ........................................................................................ 35
Figure 24. Stopband Rejection (slow), all Modes....................................................................................... 35
Figure 25. Single-Speed (fast) Passband Detail ........................................................................................ 35
Figure 26. Single-Speed (slow) Passband Detail....................................................................................... 35
Figure 27. Double-Speed (fast) Passband Detail....................................................................................... 35
Figure 28. Double-Speed (slow) Passband Detail ..................................................................................... 35
Figure 29. Quad-Speed (fast) Passband Detail ......................................................................................... 36
Figure 30. Quad-Speed (slow) Passband Detail........................................................................................ 36
CS4350
LIST OF TABLES
Table 1. Recommended Operating Conditions ............................................................................................ 7
Table 2. Absolute Maximum Ratings ........................................................................................................... 7
Table 3. DAC Analog Characteristics - Commercial (-CZZ).........................................................................8
Table 4. DAC Analog Characteristics - Automotive (-DZZ) .......................................................................... 9
Table 5. Combined Interpolation and On-Chip Analog Filter Response .................................................... 11
Table 6. Switching Specifications - Serial Audio Interface ......................................................................... 12
Table 7. Switching Characteristics - Control Port - I²C Format .................................................................. 13
Table 8. Switching Characteristics - Control Port - SPI Format ................................................................. 14
Table 9. Digital Characteristics .................................................................................................................. 15
Table 10. Power and Thermal Characteristics ........................................................................................... 15
Table 11. CS4350 Auto-Detect .................................................................................................................. 17
Table 12. Digital Interface Format - Stand-Alone Mode............................................................................. 23
Table 13. Digital Interface Formats ............................................................................................................ 28
Table 14. ATAPI Decode ........................................................................................................................... 30
Table 15. Example Digital Volume Settings ............................................................................................... 32
Table 16. Thermal Characteristics ............................................................................................................. 37
DS691F2 5
1 PIN DESCRIPTION
DIF2(AD1/CDOUT) RST
DEM(AD0/CS)AOUTB-
DIF0(SDA/CDIN) AOUTB+
DIF1(SCL/CCLK) BMUTEC
VLC VQ
VD_FILT GND
GND VA
RMCK VBIAS+
VLS AMUTEC
SCLK AOUTA+
SDIN AOUTA-
LRCK TSTO
2
3
4
5
6
7
8
17
18
19
20
21
22
23
9
10
11
12
13
14
15
16
24
1
CS4350
Pin Name # Pin Description
VLC
VD_FILT
GND
RMCK
VLS
SCLK
SDIN
LRCK
TSTO 13 Test Output - These pins need to be floating and not connected to any trace or plane.
AOUTA+,AOUTB+,-
AMUTEC
BMUTEC
VBIAS
VA
VQ
14, 15,
6 DS691F2
Control Interface Power (Input) - Positive power for the hardware/software control interface
5
Regulator Voltage (Output) - Filter connection for internal voltage regulator
6
Ground (Input) - Ground reference
7, 19
Recovered Master Clock (Output) - Outputs a master clock derived from LRCK
8
Serial Audio Interface Power (Input) - Positive power for the serial audio interface
9
Serial Clock (Input) - Serial bit-clock for the serial audio interface
10
Serial Audio Data Input (Input) - Input for two’s complement serial audio data
11
Left/Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial
12
audio data line
Differential Analog Outputs (Output) - The full scale differential output level is specified in “DAC Ana-
log Characteristics - Commercial (-CZZ)” on page 8.
22, 23
16, 21 Mute Control (Output) - Control signals for optional mute circuit.
Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC
17
Analog Power (Input) - Positive power supply for the analog section
18
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage
20
Pin Name # Pin Description
RST
Control Port Definitions
AD1/CDOUT
AD0/CS
SDA/CDIN
SCL/CCLK
Stand-Alone Definitions
DIF0
DIF1
DIF2
DEM
Reset (Input) - When pulled low, device will power down and reset all internal registers to their default
24
settings.
1 Address Bit 1/Serial Control Data Out (I/O) - Chip address bit 1 in I²C Mode or data output in SPI Mode
2 Address Bit 0/Chip Select (Input) - Chip address bit 0 in I²C Mode or Chip Select in SPI Mode
3 Serial Control Data In (I/O) - Input/Output for I²C data. Input for SPI data
Serial Control Port Clock (Input) - Serial clock for the control port interface
4
Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Serial
1, 3, 4
Clock, and Serial Audio Data
De-emphasis (Input) - Selects the standard 15 s/50 s digital de-emphasis filter response for
2
44.1 kHz sample rates
2 CHARACTERISTICS AND SPECIFICATIONS
2.1 Recommended Operating Conditions
GND = 0 V; all voltages with respect to ground.
Table 1. Recommended Operating Conditions
CS4350
Parameters Symbol Min Typ Max Units
DC Power Supply Analog power VA 4.75 5.0 5.25 V
3.14 3.3 3.46 V
Serial Audio Interface power
Control Interface power
Ambient Operating Temperature (Power Applied)
Commercial (-CZZ) T
Automotive (-DZZ) T
VLS 1.35 3.3 5.25 V
VLC 3.14 3.3 5.25 V
A
A
-40 - +85 °C
-40 - +105 °C
2.2 Absolute Maximum Ratings
GND = 0 V; all voltages with respect to ground (Note 1).
Table 2. Absolute Maximum Ratings
Parameters Symbol Min Max Units
DC Power Supply Analog power VA -0.3 6.0 V
Serial Audio Interface power
Control Interface power
Input Current (Note 2) I
Digital Input Voltage Serial Audio Interface V
Control Interface V
Ambient Operating Temperature (power applied) T
Storage Temperature T
Notes: 1. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
2. Any pin except supplies.
VLS -0.3 6.0 V
VLC -0.3 6.0 V
in
IN-LS
IN-LC
A
stg
-±10mA
-0.3 VLS+ 0.4 V
-0.3 VLC+ 0.4 V
-55 125 °C
-65 150 °C
DS691F2 7
CS4350
2.3 DAC Analog Characteristics - Commercial (-CZZ)
Test conditions (unless otherwise specified): VLS = VLC = 3.3 V; TA = 25° C; Input test signal is a 997 Hz
sine wave; Valid with the recommended capacitor values on VD_FILT, VQ, VBIAS (as shown in the typical
connection diagram in Figure 10) and output circuits as shown in Figure 17 and Figure 18; Fs = 48 kHz,
96 kHz, and 192 kHz; measurement bandwidth 10 Hz to 20 kHz.
Table 3. DAC Analog Characteristics - Commercial (-CZZ)
Parameter Symbol Min Typ Max Unit
VA= 5.0 V Single-ended/Differential
Dynamic Range (Note 3) 24-bit A-Weighted
unweighted
16-bit A-Weighted
unweighted
Total Harmonic Distortion + Noise (Note 3)
24-bit 0 dB
-20 dB
-60 dB
16-bit 0 dB
-20 dB
-60 dB
THD+N
VA= 3.3 V Single-ended/Differential
Dynamic Range (Note 3) 24-bit A-Weighted
unweighted
16-bit A-Weighted
unweighted
Total Harmonic Distortion + Noise (Note 3)
24-bit 0 dB
-2 dB
-20 dB
-60 dB
16-bit 0 dB
-20 dB
-60 dB
THD+N
VA= 3.3 to 5.0 V
Interchannel Isolation (1 kHz) - 100 - dB
DC Accuracy
Interchannel Gain Mismatch - 0.1 0.25 dB
Gain Drift - -400 - ppm/°C
Analog Output
Full Scale Output Voltage - Single Ended 2.61 2.78 2.96 Vpp
Full Scale Output Voltage - Differential 5.22 5.56 5.92 Vpp
Quiescent Voltage V
Max DC Current draw from an AOUT pin I
Max Current draw from VQ I
Max AC-Load Resistance (Note 4) R
Max Load Capacitance (Note 4) C
Output Impedance Z
Q
OUTmax
Qmax
L
L
OUT
Notes: 3. One LSB of triangular PDF dither is added to data
4. R
and CL represent the minimum resistance and maximum capacitance required for the CS4350’s in-
L
ternal op-amp to remain stable. See Figure 1 and Figure 2 for more details.
98/106
95/103
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-
-
-
-
-
-
-
-
98/106
95/103
-
-
-
-
-
-
-
-
-
-0.5•VA-VDC
-10-A
-100-A
-3-k
-100-pF
-100-
101/109
98/106
95/96
92/93
-91
-78/-86
-38/-46
-90
-72/-73
-32/-33
101/109
98/106
95/96
92/93
-86
-91/-93
-78/-86
-38/-46
-83
-72/-73
-32/-33
-
-
-
-
-86/-87
-
-35/-43
-
-
-
-
-
-
-
-77
-
-
-35/-43
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
8 DS691F2
CS4350
2.4 DAC Analog Characteristics - Automotive (-DZZ)
Test conditions (unless otherwise specified): VLS = 1.35 V to 5.25 V, VLC = 3.14 V to 5.25 V, TA = -40° C
to 105° C, input test signal is a 997 Hz sine wave; Valid with the recommended capacitor values on VFILT,
VQ, VBIAS (as shown in the typical connection diagram in Figure 10) and output circuits as shown in
Figure 17 and Figure 18; Fs = 48 kHz, 96 kHz, and 192 kHz; Measurement bandwidth 10 Hz to 20 kHz.
Table 4. DAC Analog Characteristics - Automotive (-DZZ)
Parameter Symbol Min Typ Max Unit
VA= 4.75 V to 5.25 V Single-ended/Differential
Dynamic Range (Note 3) 24-bit A-Weighted
unweighted
16-bit A-Weighted
unweighted
Total Harmonic Distortion + Noise (Note 3)
24-bit 0 dB
-20 dB
-60 dB
16-bit 0 dB
-20 dB
-60 dB
THD+N
VA= 3.14 V to 3.46 V Single-ended/Differential
Dynamic Range (Note 3) 24-bit A-Weighted
unweighted
16-bit A-Weighted
unweighted
Total Harmonic Distortion + Noise (Note 5)
24-bit -1 dB
-2 dB
-20 dB
-60 dB
16-bit 0 dB
-20 dB
-60 dB
THD+N
VA= 3.14 to 5.25 V
Interchannel Isolation (1 kHz) - 100 - dB
DC Accuracy
Interchannel Gain Mismatch - 0.1 0.25 dB
Gain Drift - -400 - ppm/°C
Analog Output
Full Scale Output Voltage - Single Ended 2.55 2.78 3.03 Vpp
Full Scale Output Voltage - Differential 5.10 5.56 6.06 Vpp
Quiescent Voltage V
Max DC Current draw from an AOUT pin I
Max Current draw from VQ I
Max AC-Load Resistance (Note 4) R
Max Load Capacitance (Note 4) C
Output Impedance Z
Q
OUTmax
Qmax
L
L
OUT
Note: 5. One-half LSB of triangular PDF dither is added to data. Also, see Figure 3, Figure 4, and Figure 5 for
more details on the CS4350-DZZ THD+N performance with 0dB input signal.
95/103
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94/103
91/100
-
-
-
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-
-
-
-
-
-0.5•VA-VDC
-10-A
- 100 - A
-3-k
- 100 - pF
- 100 -
101/109
98/106
95/96
92/93
-91
-78/-86
-38/-46
-90
-72/-73
-32/-33
101/109
98/106
95/96
92/93
-89
-91/-93
-78/-86
-38/-46
-83
-72/-73
-32/-33
-
-
-
-
-85
-
-32/-40
-
-
-
-
-
-
-
-83
-
-
-31/-40
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
DS691F2 9
CS4350
AOUTx
3.3 µF
Analog
Output
+
CS4350
GND
R
L
C
L
100
50
75
25
2.5
51015
Safe Operating
Region
Capacitive Load -- C (pF)
L
Resistive Load -- R (k)
L
125
3
20
Figure 1. Equivalent Output Load Figure 2. Maximum Loading
-3-2.5-2-1.5-1-0.50
-100
-90
-80
-70
-60
-50
-40
-30
Output A mplitude(d B)
THD+N (dB)
TA = -40° C
TA = 25° C
TA = 85° C
-3-2.5-2-1.5-1-0.50
-100
-90
-80
-70
-60
-50
-40
-30
Output Amplitude(dB)
THD+N (dB)
TA = -40° C
TA = 25° C
TA = 85° C
Figure 3. THD+N vs Output Amplitude for VA = 5.0 V Figure 4. THD+N vs Output Amplitude for VA = 3.3 V
-3-2.5-2-1.5-1-0.50
-100
-90
-80
-70
-60
-50
-40
-30
Output Amplitude(dB)
THD+N (dB)
TA = -40° C
TA = 25° C
TA = 85° C
Figure 5. THD+N vs Output Amplitude for VA = 3.14 V
Figures 3 through 5 show typical THD+N performance for CS4350 devices that exhibit the maximum full scale output voltages as specified in the DAC Analog Characteristics tables (see page 8 and 9). With decreasing VA,
THD+N performance is increasingly affected by the full scale output voltage and temperature, with higher full scale
output voltage and lower temperatures corresponding to lower THD+N performance.
10 DS691F2
CS4350
2.5 Combined Interpolation and On-Chip Analog Filter Response
The filter characteristics have been normalized to the sample rate (Fs) and is referenced to the desired sample rate by multiplying the given characteristic by Fs. Amplitude vs. Frequency plots of this data are available
in the “Filter Plots” on page 35.
Table 5. Combined Interpolation and On-Chip Analog Filter Response
Parameter Min Typ Max Unit
Fast Roll-Off
Passband (Note 6) -0.01 dB corner (Single Speed) 0 - .454 Fs
-0.1 dB corner (Double Speed) 0 - .42 Fs
-0.2 dB corner (Quad Speed) 0 - .27 Fs
-3 dB corner (All Speed Modes) 0 - .499 Fs
Frequency Response 10 Hz to 20 kHz Single Speed -0.01 - +0.01 dB
Double Speed, Quad Speed -0.02 - +0.02 dB
StopBand 0.547 - - Fs
Stop-Band Attenuation (Note 7) 102 - - dB
Total Group Delay (Fs - Output Sample Rate) TDM Slot 0 Channel B - 8.4/Fs - s
All Other Interface Formats and TDM Slots/Channels - 9.4/Fs - s
Intrachannel Phase Deviation - - ±0.56/Fs s
Interchannel Phase Deviation - - 0 s
De-emphasis Error (Note 8) Fs = 32 kHz - - ±0.23 dB
(Relative to 1 kHz) Fs = 44.1 kHz - - ±0.14 dB
Fs = 48 kHz
Slow Roll-Off (Note 9)
Passband (Note 6) -0.01 dB corner (Single Speed) 0 - 0.417 Fs
-0.1 dB corner (Double Speed) 0 - .37 Fs
-0.2 dB corner (Quad Speed) 0 - .27 Fs
-3 dB corner (All Speed Modes) 0 - .499 Fs
Frequency Response 10 Hz to 20 kHz Single Speed -0.01 - +0.01 dB
Double Speed, Quad Speed -0.02 - +0.02 dB
StopBand .583 - - Fs
Stop-Band Attenuation (Note 7) 64 - - dB
Total Group Delay (Fs - Output Sample Rate) TDM Slot 0 Channel B - 5.5/Fs - s
All Other Interface Formats and TDM Slots/Channels - 6.5/Fs - s
Intrachannel Phase Deviation - - ±0.14/Fs s
Interchannel Phase Deviation - - 0 s
De-emphasis Error (Note 8) Fs = 32 kHz - - ±0.23 dB
(Relative to 1 kHz) Fs = 44.1 kHz - - ±0.14 dB
Fs = 48 kHz
--±0.09dB
--±0.09dB
Notes: 6. Response is clock dependent.
7. The Measurement Bandwidth is from stopband to 3 Fs.
8. De-emphasis is available only in Single-Speed Mode; Only 44.1 kHz De-emphasis is available in StandAlone Mode.
9. Slow Roll-off interpolation filter is only available in Control Port Mode.
DS691F2 11
CS4350
2.6 Switching Specifications - Serial Audio Interface
Inputs: Logic 0 = GND; Logic 1 = VLS; CL=20pF.
Table 6. Switching Specifications - Serial Audio Interface
Parameters Symbol Min Max Units
3.14 V
RMCK Output Frequency (Note 10) 7.680 55.3 MHz
RMCK Output Duty Cycle 45 55 %
Input Sample Rate Single-Speed Mode 30 54
LRCK Duty Cycle (Non-TDM Mode) 40 60 %
SDIN Setup Time Before SCLK Rising Edge t
SDIN Hold Time After SCLK Rising Edge t
4.75 V VA 5.25 V and 3.14 V VLS 5.25 V
SCLK Frequency -55.3MHz
SCLK High Time t
SCLK Low Time t
Non-TDM Mode (refer to Figure 6)
LRCK Edge to SCLK Rising Edge t
SCLK Rising Edge to LRCK Edge t
TDM Mode (refer to Figure 7)
LRCK High Time t
SCLK Rising to LRCK Falling Edge t
LRCK Rising Edge to SCLK Rising Edge t
SCLK Frequency -27.7MHz
SCLK High Time t
SCLK Low Time t
Non-TDM Mode (refer to Figure 6)
LRCK Edge to SCLK Rising Edge t
SCLK Rising Edge to LRCK Edge t
TDM Mode (refer to Figure 7)
LRCK High Time t
SCLK Rising to LRCK Falling Edge t
LRCK Rising Edge to SCLK Rising Edge t
VA 5.25 V and 1.35 V VLS 5.25 V
Double-Speed Mode Fs 60 108 kHz
Quad-Speed Mode 120 216
ds
dh
sckh
sckl
lcks
lckd
lrckh
fsh
fss
3.14 V VA < 4.75 V or 1.35 V VLS < 3.14 V
sckh
sckl
lcks
lckd
lrckh
fsh
fss
1-ns
1-ns
6-ns
6-ns
11 - n s
1-ns
6-ns
3-ns
1-ns
11 - n s
11 - n s
16 - ns
1-ns
25 - ns
8-ns
1-ns
Note: 10. RMCK output frequency depends on the input LRCK frequency. See Section 4.1 and Section 4.2 for
more details.
12 DS691F2
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