Cirrus Logic CS4341 User Manual

CS4341

24-Bit, 96 kHz Stereo DAC with Volume Control

Features

! 101 dB Dynamic Range
! -91 dB THD+N
! +3.0 V or +5.0 V Power Supply
! Low Clock-Jitter Sensitivity
! Filtered Line-Level Outputs
! On-Chip Digital De-Emphasis for 32, 44.1

and 48 kHz

! ATAPI Mixing
! Digital Volume Control with Soft Ramp

– 94 dB Attenuation
– 1 dB Step Size
– Zero Crossing Click-Free Transitions

! Popguard

and Pops

! 33 mW with 3.0 V Supply

I

®

Technology for Control of Clicks

Description

The CS4341 is a complete stereo digital-to-analog sys­tem including digital interpolation, fourth-order Delta­Sigma digital-to-analog conversion, digital de-emphasis
and switched capacitor analog filtering. The advantages
of this architecture include: ideal differential linearity, no
distortion mechanisms due to resistor matching errors,
no linearity drift over time and temperature and a high
tolerance to clock jitter.

The CS4341 accepts data at audio sample rates from
4 kHz to 100 kHz, consumes very little power, and oper­ates over a wide power supply ran ge. The features of
the CS4341 are ideal for DVD players, CD players, set­top box and automotive systems.

ORDERING INFORMATION

CS4341-KS 16-pin SOIC, -10 to 70 °C
CS4341-CZZ, Lead Free 16-pin TSSOP, -10 to 70 °C
CDB4341 Evaluation Board

RST

SCLK

LRCK

SDATA

SCL/CCLK MUTECAD0/CS

Serial Port

SDA/CDIN

Control Port

Volume ControlInterpolation Fi lter Analog Filter

Volume ControlInterpolation Fi lter

Mixer

MCLK

External

Mute Control

÷2

∆Σ

∆Σ

DAC

DAC

Analog Filter

AOUTA

AOUTB

http://www.cirrus.com

Copyright © Cirrus Logic, Inc. 2005

(All Rights Reserved)

DECEMBER '05

DS298F5

1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 4

SPECIFIED OPERATING CONDITIONS.............................................................................................. 4

ABSOLUTE MAXIMUM RATINGS ........................................................................................................4

ANALOG CHARACTERISTICS (CS4341-KS/CZZ)............................................................................... 5

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE........................................ 7

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE........................................................ 10

SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK ..................................................... 11

SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (I²C®) ..................................... 12

SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (SPI™) ................................... 13

DC ELECTRICAL CHARACTERISTICS.............. ... ... .... ... ... ... .... ... ... .......................................... ... ... ... 14

DIGITAL INPUT CHARACTERISTICS ................................................................................................ 14

DIGITAL INTERFACE SPECIFICATIONS........................................................................................... 14

2. PIN DESCRIPTION ............................................................................................................................. 15

3. TYPICAL CONNECTION DIAGRAM ................................................................................................. 16

4. APPLICATIONS ................................................................................................................................... 17

4.1 Sample Rate Range/Operational Mode ........................................................................................ 17

4.2 System Clocking .................... .... ... ... ... ... .... ...................................... .... ... ... ... .... ... ......................... 17

4.2.1 Internal Serial Clock Mode ...............................................................................................17

4.2.2 External Serial Clock Mode .............................................................................................. 18

4.3 Digital Interface Format ................................................................................................................. 18

4.4 De-Emphasis .......................................................... ...................................................................... 19

4.5 Power-Up Sequence .......... ... .... ... .......................................... ... ................................................... 19

4.6 Popguard

4.6.1 Power-Up ............................................... .... ... ... ... ....................................... ... ... .... ............ 19

4.6.2 Power-Down .................. ... ....................................... ... ... ... ... .... ... ... ................................... 20

4.6.3 Discharge Time ............................................. ... ... .... ...................................... ... .... ... ......... 20

4.7 Mute Control ....................................................... .... ... ... ... .... ... ... ................................................... 20

4.8 Grounding and Power Supply Arrangements ............................................................................... 20

4.9 Control Port Interface .................................................................................................................... 20

4.9.1 Rise Time for Control Port Clock ...................................................................................... 21

4.9.2 Memory Address Pointer (MAP) ...................................................................................... 21

4.9.3 I²C Mode .......................................... ... ... .... ... ....................................... ... ... ... ... .... ............ 21

4.9.4 SPI Mode ............................................ ... .... ... ... ... .... ...................................... ... .... ............ 23

5. REGISTER QUICK REFERENCE ....................................................................................................... 24

6. REGISTER DESCRIPTION ................................................................................................................. 25

6.1 MCLK Control (address 00h)...................... ... ... ............................................................................. 25

6.2 Mode Control (address 01h)............................. ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ......................... 25

6.3 Transition and Mixing Control (address 02h).................................................................................27

6.4 Channel A Volume Control (address 03h)..................................................................................... 29

6.5 Channel B Volume Control (address 04h)..................................................................................... 29

®

Transient Control .............................. .... ... ... ... .... ... ... ... ... .... ... ... ... ................................ 19

4.9.2a INCR (Auto Map Increment) .............................................................................. 21

4.9.2b MAP0-3 (Memory Address Pointer) .................................................................. 21

4.9.3a I²C Write ............................................................................................................ 22

4.9.3b I²C Read ............................................................................................................ 22

4.9.4a SPI Write ........................................................................................................... 23

CS4341

7. PARAMETER DEFINITIONS ............................................................................................................... 31

8. PACKAGE DIMENSIONS .................................................................................................................... 32

2 DS298F5

8.1 SOIC ................... ... ... ....................................... ... .... ... ... ....................................... ..........................32

8.2 TSSOP ................................................................... ... ... ... .... ..........................................................33

9. PACKAGE THERMAL RESISTANCE .................................................................................................33

10. REFERENCES ................................ ... ... ... ... .... ... ... ... .... .......................................................................34

11. REVISION HISTORY ..........................................................................................................................34

LIST OF FIGURES

Figure 1. Output Test Load .........................................................................................................................6

Figure 2. Maximum Loading ........................................................................................................................6

Figure 3. Single-Speed Stopband Rejection ...............................................................................................8

Figure 4. Single-Speed Transition Band .....................................................................................................8

Figure 5. Single-Speed Transition Band (Detail) .........................................................................................8

Figure 6. Single-Speed Passband Ripple ...................................................................................................8

Figure 7. Double-Speed Stopband Rejection ..............................................................................................8

Figure 8. Double-Speed Transition Band ....................................................................................................8

Figure 9. Double-Speed Transition Band (Detail) .......................................................................................9

Figure 10. Double-Speed Passband Ripple ..................................................................................................9

Figure 11. Serial Input Timing (External SCLK) ............................................ .... ..........................................10

Figure 12. Internal Serial Mode Input Timing .................................................... ... ... ....................................11

Figure 13. Internal Serial Clock Generation ................................................................................................11

Figure 14. Control Port Timing - I²C Mode ..................................................................................................12

Figure 15. Control Port Timing - SPI Mode .................................................................................................13

Figure 16. Typical Connection Diagram .................................. ................................... .................................16

Figure 17. CS4341 Formats 0-1 - I²S up to 24-Bit Data ..............................................................................18

Figure 18. CS4341 Format 2 - Left Justified up to 24-Bit Data ...................................................................18

Figure 19. CS4341 Formats 3-6 - Right Justified ........................................................................................18

Figure 20. De-Emphasis Curve ...................................................................................................................19

Figure 21. I²C Buffer Example .....................................................................................................................21

Figure 22. I²C Write .....................................................................................................................................22

Figure 23. I²C Read .....................................................................................................................................23

Figure 24. Control Port Timing, SPI Mode ..................................................................................................23

Figure 25. ATAPI Block Diagram ................................................................................................................29

CS4341

LIST OF TABLES

Table 1. CS4341 Speed Modes.....................................................................................................................17

Table 2. Single-Speed Mode Standard Frequencies ................................. ... .......................................... .......17

Table 3. Double-Speed Mode Standard Frequencies....................................................................................17

Table 4. Internal SCLK/LRCK Ratio...............................................................................................................18

Table 5. Digital Interface Format....................................................................................................................26

Table 6. ATAPI Decode.......................... .... ... ... ... ... .... ....................................................................................28

Table 7. Example Digital Volume Settings .....................................................................................................30

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CS4341

1. CHARACTERISTICS AND SPECIFICATIONS

(Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions.
Typical performance characteristics are derived from measurements taken at T

SPECIFIED OPERATING CONDITIONS (All voltages with respect to AGND = 0 V.)

Parameters Symbol Min Nom Max Units

DC Power Supply

Nominal 3.3 V
Nominal 5.0 V

Specified Operating Temperature -KS/CZZ

VA
VA

T

A

(Power Applied)

ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to AGND. Operation beyond

these limits may result in permanent damage to the device. Normal opera tion is not guaranteed at these extremes.)

Parameters Symbol Min Max Units

DC Power Supply VA -0.3 6.0 V
Input Current
Digital Input Voltage V
Ambient Operating Temperature (power applied) T
Storage Temperature T

(Note 1) I

in

IND

A

stg

= 25°C.)

A

2.7

4.75

3.3

5.0

3.6

5.5

-10 - +70 °C

-±10mA

-0.3 VA+0.4 V

-55 125 °C

-65 150 °C

V
V

Notes: 1. Any pin except supplies.

4 DS298F5

CS4341

ANALOG CHARACTERISTICS (CS4341-KS/CZZ) (Test conditions (unless otherwise specified): Input

test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load R
= 10 pF (see Figure 1).)

VA = 5.0 V VA = 3.0 V

Parameter

Min Typ Max Min Typ Max Unit

Single-Speed Mode Fs = 48 kHz

Dynamic Range
18 to 24-Bit unweighted

16-Bit unweighted

Total Harmonic Distortion + Noise
18 to 24-Bit 0 dB

16-Bit 0 dB

(Note 2)

A-Weighted
A-Weighted

(Note 2)

-20 dB

-60 dB

-20 dB

-60 dB

93
96

89

98

101

-

-

-

-

-

-

-

-

92
95

-91

-78

-38

-90

-72

-32

-

-

-

-

-86

-

-

-

-

-

92

-

-

-

-

-

-

-

-

94
97
92
95

-94

-74

-34

-91

-72

-32

Double-Speed Mode Fs = 96 kHz

Dynamic Range
18 to 24-Bit unweighted

16-Bit unweighted

Total Harmonic Distortion + Noise
18 to 24-Bit 0 dB

16-Bit 0 dB

(Note 2)

A-Weighted
A-Weighted

(Note 2)

-20 dB

-60 dB

-20 dB

-60 dB

93
96

89

98

101

-

-

-

-

-

-

-

-

92
95

-91

-78

-38

-90

-72

-32

-

-

-

-

-86

-

-

-

-

-

92

-

-

-

-

-

-

-

-

94
97
92
95

-94

-74

-34

-91

-72

-32

=10kΩ, CL

L

-

-

-

-

-89

-

-

-

-

-

-

-

-

-

-89

-

-

-

-

-

dB
dB
dB
dB

dB
dB
dB
dB
dB
dB

dB
dB
dB
dB

dB
dB
dB
dB
dB
dB

DS298F5 5

CS4341

ANALOG CHARACTERISTICS (CS4341-KS/CZZ) (Continued)

Parameters Symbol Min Typ Max Units

Dynamic Performance for All Modes

Interchannel Isolation (1 kHz) - 100 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB
Gain Drift - ±100 - ppm/°C

Analog Output Characteristics and Specifications

Full-Scale Output Voltage 0.6•VA 0.7•VA 0.8•VA Vpp
Output Impedance - 100 - Ω
Minimum AC-Load Resistance
Maximum Load Capacitance

Notes: 2. One-half LSB of triangular PDF dither is added to data.

3. Refer to Figure 2.

.

3.3 µF

AOUTx

+

(Note 3) R
(Note 3) C

V

out

L
L

-3-kΩ

- 100 - pF

AGND

R

L

Figure 1. Output Test Load

C

L

125

100

L

75

50

25

Capacitive Load -- C (pF)

2.5

51015

3

Safe Operating

Region

Resistive Load -- R (kΩ)

L

20

Figure 2. Maximum Loading

6 DS298F5

CS4341

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The filter characteris-

tics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can be referenced to the
desired sample rate by multiplying the given characteristic by Fs.)

Parameter Min Typ Max Unit

Single-Speed Mode - (4 kHz to 50 kHz sample rates)

Passband

to -0.05 dB corner

to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.02 - +0.08 dB
StopBand 0.5465 - - Fs
StopBand Attenuation
Group Delay - 9/Fs - s
Passband Group Delay Deviation 0 - 20 kHz - ±0.36/Fs - s
De-emphasis Error (Relative to 1 kHz) Fs = 32 kHz

(Note 5) Fs = 44.1 kHz

Fs = 48 kHz

Double-Speed Mode - (50 kHz to 100 kHz sample rates)

Passband

to -0.1 dB corner

to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.06 - +0.2 dB
StopBand 0.577 - - Fs
StopBand Attenuation
Group Delay - 4/Fs - s
Passband Group Delay Deviation 0 - 40 kHz

0 - 20 kHz

0
0

(Note 4) 50 - - dB

-

-

-

0
0

(Note 4) 55 - - dB

-

-

-

-

-

-

-

-

-

±1.39/Fs
±0.23/Fs

0.4535

0.4998

+0.2/-0.1

+0.05/-0.14

+0/-0.22

0.4621

0.4982

-

-

Fs
Fs

dB
dB
dB

Fs
Fs

s
s

Notes: 4. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.

For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.

5. De-emphasis is only available in Single-Speed Mode.

DS298F5 7

CS4341

Figure 3. Single-Speed Stopband Rejection Figure 4. Single-Speed Transition Band

Figure 5. Single-Speed Transition Band (Detail) Figure 6. Single-Speed Passband Ripple

Figure 7. Double-Speed Stopband Rejection Figure 8. Double-Speed Transition Band

8 DS298F5

CS4341

Figure 9. Double-Speed Transition Band (Detail) Figure 10. Double-Speed Passband Ripple

DS298F5 9

CS4341

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE

Parameters Symbol Min Max Units

MCLK Frequency 1.024 51.2 MHz
MCLK Duty Cycle 45 55 %
Input Sample Rate Single-Speed Mode

Double-Speed ModeFsFs

4

50

50

100

kHz

kHz
LRCK Duty Cycle 40 60 %
SCLK Pulse Width Low t
SCLK Pulse Width High t
SCLK Frequency Single-Speed Mode

Double-Speed Mode
SCLK rising to LRCK edge delay t
SCLK rising to LRCK edge setup time t
SDIN valid to SCLK rising setup time t
SCLK rising to SDIN hold time t

LRCK

t

t

slrd

slrs

t

sclkl

sclkl

sclkh

slrd
slrs

sdlrs

sdh

t

sclkh

20 - ns
20 - ns

-

-

128xFs

64xFs

Hz

Hz
20 - ns
20 - ns
20 - ns
20 - ns

SCLK

t

sdh

SDATA

t

sdlrs

Figure 11. Serial Input Timing (External SCLK)

10 DS298F5

CS4341

SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK

Parameters Symbol Min Typ Max Units

MCLK Frequency 1.024 - 51.2 MHz
MCLK Duty Cycle 45 - 55 %
Input Sample Rate Single-Speed Mode

Double-Speed ModeFsFs
LRCK Duty Cycle
SCLK Period

(Note 7) t

sclkw

SCLK rising to LRCK edge

t

sclkr

SDATA valid to SCLK rising setup time t

SCLK rising to SDATA hold time

sdlrs

t

sdh

MCLK / LRCK = 512, 256 or 128

SCLK rising to SDATA hold time

t

sdh

MCLK / LRCK = 384 or 192

Notes: 6. The Duty Cycle must be 50% +/− 1/2 MCLK Period.

7. See section 4.2.1 for derived internal frequencies.

LRCK

t

sclkr

SDATA

4

50

1

---------------­SCLK

--s

1

--------------------- -10+
512()Fs

1

--------------------- -15+
512()Fs

1

--------------------- -15+
384()Fs

-

-

(Note 6)

50

100

kHz
kHz

%

--s

t

sclkw

------------- ­2

--ns

--ns

--ns

t

sclkw

t

sdlrstsdh

*INTERNAL SCLK

Figure 12. Internal Serial Mode Input Timing

*The SCLK pulses shown are internal to the CS4341.

LRCK

MCLK

*INTERNAL SCLK

SDATA

1

N
2

N

Figure 13. Internal Serial Clock Generation

* The SCLK pulses shown are internal to the CS4341. N equals MCLK divided by SCLK

DS298F5 11