Cirrus Logic CS43122 User Manual
CS43122
122 dB, 24-Bit, 192 kHz DAC for Digital Audio
Features
l 24 Bit Conversion
l Up to 192 kHz Sample Rates
l 122 dB Dynamic Range
l -102 dB THD+N
l Second-Order Dynamic-Element Matching
l Low Clock Jitter Sensitivity
l 102 dB Stop-band attenuation
l Single +5 V supply
l Soft Mute Control
l Digital De-Emphasis for 32, 44.1, and 48 kHz
l External Reference Input
l Pin-compatible wit h the CS4396
Description
The CS43122 is a complete high performance 24 bit192 kHz stereo digital-to-analog conversion system. The
device includes a digital interpolation filter followed by an
oversampled 5 bit delta-sigma modulator which drives
second generation dynamic-element-matching (DEM)
selection logic. The out put from the DEM block con trols
the input to a multi-element switched capacitor DAC/lowpass filter, with fully-differential outputs. This multi-bit architecture featur es significant ly lower out-of-band noise
and jitter sensitivity than traditional 1-bit designs, and the
advanced second generation DEM guarantees low noise
and distortion at all signal levels.
The CS43122 is the o ptimal D/A converter solution for
any application that requires the highest performance
and best possib le s oun d q ual ity i nclu ding high-end consumer and professional audio products such as
Universal DVD players, A/V receivers, Outboard D/A
Converters, CD Players, and Mixing Consoles.
ORDERING INFORMATION
CS43122-KS -10° to 70° C 28-pin SOIC
CDB43122 Evaluation Board
SCLK
LRCK
SDATA
MCLK
CLOCK
DIVIDER
M4
(AD0/CS)
M3 M2
(AD1/CDIN) (SCL/CCLK)
SERIAL INTERFACE
AND FORMAT SELECT
INTERPOLATION
INTERPOLATION
HARDWARE MODE CONTROL
Advance Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
DE-EMPHASIS
FILTER
SWITCHED
CAPACITOR-DAC
AND FILTER
SWITCHED
CAPACITOR-DAC
AND FILTER
VOLTAGE REFERENCE
FILT+
VREF CMOUTFILT-
FILTER
FILTER
(CONTROL PORT)
M1 M0
(SDA/CDOUT)
SOFT MUTE
MULTI-BIT
∆Σ
MODULATOR
MULTI-BIT
∆Σ
MODULATOR
RESET MUTEC MUTE
DYNAMIC
ELEMENT
MATCHING
LOGIC
DYNAMIC
ELEMENT
MATCHING
LOGIC
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2000
(All Rights Reserved)
AOUTL+
AOUTL-
AOUTR+
AOUTR-
DEC ‘00
DS526PP2
1
TABLE OF CONTENTS
1. CHARACTERISTICS/SPECIFICATIONS .................................................................................4
ANALOG CHARACTERISTICS................................................................................................ 4
DIGITAL CHARACTERISTICS................................................................................................. 8
ABSOLUTE MAXIMUM RATINGS ...........................................................................................8
RECOMMENDED OPERATING CONDITIONS.......................................................................8
SWITCHING CHARACTERISTICS . ...... ....... ...... ....... ...... ....................................... ...... ....... ..... 9
SWITCHING CHARACTERISTICS - CONTROL PORT.........................................................10
2. TYPICAL CONNECTION DIAGRAM ...................................................................................... 12
3. REGISTER DESCRIPTION .................................................................................................... 13
3.1 Mode Control Register (Address 01H)..............................................................................13
4. PIN DESCRIPTION ................................ ....... ...................................... ....... ...... ....... ...... .... ... ... 15
5. APPLICATIONS ......................................................................................................................19
5.1 Recommended Power-up Sequence ............................................................................... 19
6. CONTROL PORT INTERFACE .................................................................................... ....... ... 19
6.1 SPI Mode ......................................................................................................................... 19
6.2 2 Wire Mode ..................................................................................................................... 19
6.3 Memory Address Pointer (MAP) ..................................................................................... 20
7. PARAMETER DEFINITIONS ..................................................................................................25
8. REFERENCES ........................................................................................................................25
9. PACKAGE DIMENSIONS ....................................................................................................... 26
CS43122
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
Preliminary product inf o rmation describes products whi ch are i n production, but for whi ch f ul l characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document i s accurat e and reli able. However , t he infor mation is subje ct to chang e without noti ce and is provi d ed “AS IS” without warrant y of
any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warran t y , pa tent infringement, an d limitation of liability. No re s p onsibility is assumed b y Cirrus Logic, Inc. for the use of this informa tion, including
use of this inf orma t i on as the basis for manufacture or sale o f a ny i t e ms, nor for infrin gements of patents or other rights of third parties. This document i s the
property of Cirrus Logic, Inc. a nd by furni shing th is i nformati on, Cir rus L ogic, In c. grant s no l icense, express or i mpli ed under any patent s, mask work righ ts,
copyrights, trademarks, trad e secrets o r ot her i ntellect ual pro pert y right s of Cirrus L ogic, I nc. Ci rrus L ogic, In c., cop yright owner of the in forma tion co ntaine d
herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts
of Cirrus Logic, Inc. The same consent is gi ven for simi lar inf ormat ion con tai ned on a ny Cirru s Logic we bsite or disk. T his consent does not extend to othe r
copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic,
Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some
jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com
.
2
LIST OF FIGURES
Figure 1. Serial Audio Input Timing................................................................................................. 9
Figure 2. 2 Wire Mode Control Port Timing................................................................................... 10
Figure 3. SPI Control Port Timing ................ ....... ...................................... ....... ...... ....... ...... ..........11
Figure 4. Typical Connection Diagram...................... ....... ...... ...... ....... ...... ....... ............................. 1 2
Figure 5. Control Port Timing, SPI mode ...................................................................................... 20
Figure 6. Control Port Timing, 2 wire Mode................................................................................... 20
Figure 7. Operational Mode 0 Transition Band ............................................................................ 22
Figure 8. Operational Mode 0 Stopband Rejection ......................................................................22
Figure 9. Operational Mode 0 Transition Band ............................................................................ 22
Figure 10. Operational Mode 0 Frequency Response .................................................................22
Figure 11. Operational Mode 0 Stopband .....................................................................................22
Figure 12. Operational Mode 0 Transition Band ..........................................................................22
Figure 13. Operational Mode 0 Transition Band ..........................................................................22
Figure 14. Operational Mode 0 Frequency Response .................................................................22
Figure 15. Operational Mode 2 Stopband Rejection....................................................................23
Figure 16. Operational Mode 2 Transition Band ..........................................................................23
Figure 17. Operational Mode 2 Transition Band ..........................................................................23
Figure 18. Operational Mode 2 Frequency Response .................................................................23
Figure 19. De-Emphasis Curve.....................................................................................................23
Figure 20. Format 0, Left Justified................................................................................................24
Figure 21. Format 1, I
Figure 22. Format 2, Right Justified, 16-Bit Data .........................................................................24
Figure 23. Format 3, Right Justified, 24-Bit Data ..........................................................................24
CS43122
2
S..............................................................................................................24
LIST OF TABLES
Table 1. Operational Mode 0 (16 to 55 kHz sample rates) Common Clock Frequencies ................16
Table 2. Operational Mode 1 (45 to 105 kHz sample rates) Common Clock Frequencies .............16
Table 3. Operational Mode 2 (95 to 200 kHz sample rates) Common Clock Frequencies .............16
Table 4. Operational Mode 0 (16 to 55 kHz) Digital Interface Format Options................................. 21
Table 5. Operational Mode 0 (16 to 55 kHz) De-Emphasis Options ................................................ 21
Table 6. Operational Mode 1 (45 to 105 kHz) Sample Rate Mode Options .....................................21
Table 7. Operational Mode 2 (95 to 200 kHz) Sample Rate Mode Options .....................................21
3
1. CHARACTERISTICS/SPECIFICATIONS
CS43122
ANALOG CHARACTERISTICS (T
= DGND;Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; SCLK = 3.072 MHz; Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Test load = R
Parameter Symbol Min Typ Max Unit
= 25° C; Logic "1" = VD = 3 V; VA = 5.5 V;VREF=5.5 V Logic "0"
A
= 1kΩ, CL = 10 pF)
L
Dynamic Performance - Operational Mode 1 (Fs = 48 kHz)
Dynamic Range (Note 1)
24-Bit unweighted
A-Weighted
16-Bit unweighted
(Note 2) A-Weighted
Total Harmonic Distortion + Noise (Note 1)
24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
(Note 2) -20 dB
-60 dB
THD+N
TBD
TBD
-
-
-
-
-
-
-
-
119
122
95
98
-102
-99
-59
-95
-75
-35
-
-
-
-
TBD
TBD
TBD
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
4
ANALOG CHARACTERISTICS (CONTINUED)
Parameter Symbol Min T yp Max Unit
Dynamic Performance - Operational Mode 0 (Fs = 48 kHz)
Dynamic Range (Note 1)
24-Bit unweighted
A-Weighted
16-Bit unweighted
(Note 2) A-Weighted
Total Harmonic Distortion + Noise (Note 1)
24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
(Note 2) -20 dB
-60 dB
Dynamic Performance - Operational Mode 1 (Fs = 96 kHz)
Dynamic Range (Note 1)
24-Bit unweighted
A-Weighted
40 kHz bandwidth
unweighted
16-Bit unweighted
(Note 2) A-Weighted
Total Harmonic Distortion + Noise (Note 1)
24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
(Note 2) -20 dB
-60 dB
Dynamic Performance - Operational Mode 2 (Fs = 192 kHz)
Dynamic Range (Note 1)
24-Bit unweighted
A-Weighted
40 kHz bandwidth
unweighted
16-Bit unweighted
(Note 2) A-Weighted
Total Harmonic Distortion + Noise (Note 1)
24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
(Note 2) -20 dB
-60 dB
THD+N
THD+N
THD+N
TBD
TBD
-
-
-
-
-
-
-
-
TBD
TBD
TBD
-
-
-
-
-
-
-
-
TBD
TBD
TBD
-
-
-
-
-
-
-
-
117
120
95
98
-100
-97
-55
-95
-75
-35
117
120
114
92
98
-100
-97
-55
-95
-75
-35
117
120
114
95
98
-100
-97
-55
-95
-75
-35
CS43122
-
-
-
-
TBD
TBD
TBD
-
-
-
-
-
-
-
-
TBD
TBD
TBD
-
-
-
-
-
-
-
-
TBD
TBD
TBD
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
5
CS43122
ANALOG CHARACTERISTICS (CONTINUED)
Parameter Symbol VD = 3 V VD = 5 V Unit
Power Supplies
Supply Current normal operation
VA = 5 .0V normal operation
power-down state
I
I
ID + I
Power Dissipation normal operation
VA = 5 .0V power-down
Power Supply Rejection Ratio (1 kHz) (Note 3)
PSRR -
(120 Hz)
Parameter Symbol Min Typ Max Unit
Analog Output
Full Scale Differential Output Voltage TBD 1.33VREF TBD Vpp
Common Mode Voltage - 0.5VREF - VDC
Interchannel Gain Mismatch - 0.1 - dB
Gain Drift - 100 - ppm/°C
Differential DC Offset - 2.0 TBD mV
AC-Load Resistance R
Load Capacitance C
Interchannel Isolation (1 kHz) - 90 - dB
Min Typ Max Min Typ Max
-
17
A
D
-
-
A
-
-
-
L
L
1.0 - - kΩ
--100pF
27
60
166
0.3
60
40
TBD -
TBD--
-
-
-
-
-
-
-
17
24
30
205
0.3
60
40
TBD
mA
mA
-
µA
TBD-mW
mW
-
-
dB
dB
Notes: 1. Triangular PDF dithered data.
2. Performance limite d b y 16 -bi t qu an ti zation noise.
3. Valid with the recommended capacitor values on FILT+ and CMOUT as shown in Figure 1. Increasing
the capacitance will also increase the PSRR.
6
CS43122
ANALOG CHARACTERISTICS (Continued)
Parameter Symbol Min Typ Max Unit
Combined Digital and On-chip Analog Filter Response - Operational Mode 0
Passband (Note 4)
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -.020 - +0.015 dB
Passband Ripple - - ±0.0001 dB
StopBand .5465 - - Fs
StopBand Attenuation (Note 5) 102 - - dB
Group Delay (Note 6) tgd - 37/Fs - s
De-emphasis Error (Note 7)
Fs = 32 kHz
(Relative to 1 kHz) Fs = 44.1 kHz
Fs = 48 kHz
Combined Digital and On-chip Analog Filter Response - Operational Mode 1
Passband (Note 4)
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.017 - 0.035 dB
Passband Ripple - - ±0.0008 dB
StopBand .570 - - Fs
StopBand Attenuation (Note 5) 82 - - dB
Group Delay tgd - 20/Fs - s
Combined Digital and On-chip Analog Filter Response - Operational Mode 2
Passband (Note 4)
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz 0 - +0.015 dB
Passband Ripple - - ±0.00065 dB
StopBand 0.635 - - Fs
StopBand Attenuation (Note 5) 83 - - dB
Group Delay tgd - 11/Fs - s
-
-
-
-
-
0
0
-
-
-
-
-
-
-
-
-
-
-
0.470
0.492
±0.10
±0.10
±0.13
0.448
0.486
0.385
0.472
dB
dB
dB
Fs
Fs
Fs
Fs
Fs
Fs
Notes: 4. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 7-18) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
5. For Operational Mode 0, the Measurement Bandwidth is 0.5465 Fs to 1.4 Fs.
For Operational Mode 1, the Measurement Bandwidth is 0.570 Fs to 1.4 Fs.
For Operational Mode 2, the Measurement Bandwidth is 0.635 Fs to 1.3 Fs.
6. Group Delay for Fs=48 kHz 37/48 kHz=770 µs
7. De-em pha si s is availab le onl y in Op er ati ona l Mode 0.
7
CS43122
DIGITAL CHARACTERISTICS (T
= 25° C; VD = 3.0 V - 5.25 V)
A
Parameters Symbol Min Typ Max Units
High-Level Input Voltage VD = 5 V
VD = 3 V
Low-Level Input Voltage VD = 5 V
VD = 3 V
Input Leakage Current I
V
IH
2.0
2.0
V
IL
-
-
in
--±10µA
-
-
-
-
-
-
0.8
0.8
V
V
V
V
Input Capacitance - 8 - pF
Maximum MUTEC Drive Current - 3 - mA
ABSOLUTE MAXIMUM RATINGS (AGND = 0 V, all voltages with respect to ground.)
Parameter Symbol Min Max Unit
DC Power Supply: Positive Analog
Positive Digital
Reference Voltage
Input Current, Any Pin Except Supplies I
Digital Input Voltage V
Ambient Operating Temperature (power applied) T
Storage Temperature T
WARNING: WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal
operation is not guaranteed at these extremes.
VA
VD
VREF
in
IND
A
stg
-0.3
-0.3
-0.3
6.0
6.0
VA
V
V
V
-±10mA
-0.3 (VD)+0.4 V
-55 125 °C
-65 150 °C
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit
DC Power Supply: Positive Digital
Positive Analog
Reference Voltage
Specified Temperature Range T
VD
VA
VREF
(DGND = 0V; all voltages with respect to ground)
3.0
5.25
5.25
A
-10 - 70 °C
3.3
5.5
5.5
5.25
5.75
VA
V
V
V
8
CS43122
SWITCHING CHARACTERISTICS (T
1 = VD = 5.25 to 3.0 Volts; C
=20pF)
L
= -10 to 70° C; Logic 0 = AGND = DGND; Logic
A
Parameter Symbol Min Typ Max Unit
Input Sample Rate (Operational Mode 0)
(Operational Mode 1)
(Operational Mode 2)
Fs
Fs
Fs
16
45
95
-
-
-
55
105
200
kHz
kHz
kHz
LRCK Duty Cycle 45 50 55 %
MCLK Frequency (Operational Mode 0, 256 Fs)
(Operational Mode 1, 128 Fs)
4.096
- 14.08 MHz
(Operational Mode 2, 64 Fs)
MCLK Frequency (Operational Mode 0, 384 Fs)
(Operational Mode 1, 192 Fs)
6.144
- 21.12 MHz
(Operational Mode 2, 96 Fs)
MCLK Frequency (Operational Mode 0, 512 Fs)
(Operational Mode 1, 256 Fs)
8.192
- 28.16 MHz
(Operational Mode 2 , 128 Fs)
MCLK Frequency (Operational Mode 0, 768 Fs)
(Operational Mode 1, 384 Fs)
12.288
- 42.24 MHz
(Operational Mode 2 , 192 Fs)
MCLK Duty Cycle 40 50 60 %
SCLK Frequency (Operational
Mode 0) (Operational Mode 1)
(Operational Mode 2)
SCLK rising to LRCK edge delay t
SCLK rising to LRCK edge setup time t
SDATA valid to SCLK rising setup time t
SCLK rising to SDATA hold time t
slrd
slrs
sdlrs
sdh
-
-
-
-
-
-
256×Fs
128×Fs
64×Fs
20 - - ns
20 - - ns
20 - - ns
20 - - ns
Hz
Hz
Hz
LRCK
SCLK
SDATA
t
t
slrd
t
sdlrs
slrs
t
sclkl
Figure 1. Serial Audio Input Timing
t
sdh
t
sclkh
9
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