Cirrus Logic CS42L73 User Manual

Line Outputs

Pseudo Diff. Input

+VCP_FILT

-VCP_FILT

Digital Processing

Level Shifters

CS42L73

Decimator,

HPF, Noise Gate, ALC,

Volume,

Mute,

Swap/Mono

Volume, Mute, Limiter

MCLK

Stereo

Multi-bit  DAC

MCLK

Stereo

Multi-bit  DAC

LDO

VD_FILT

Headphone Outputs

Pseudo Diff. Input

+VCP_FILT

-VCP_FILT

Ear Speaker Output

Speakerphone Line Output (Right)

Speakerphone Output (Left)

Digital MIC Interface

MCLK

Stereo

Multi-bit  ADC

-6 to +12 dB,

0.5 dB steps

MIC 2

MIC 1

Pseudo Diff. Input

Line Input (Left)

Line Input (Right)

Pseudo Diff. Input

+10 or +20 dB

MIC 1 Bias

MIC 2 Bias

MIC Bias Short DetectMIC Bias

Audio Serial Port

Voice Serial Port

Auxiliary Serial Port

Audio

Serial Port

SDOUT

SDIN

ASRC

Voice

Serial Port

SDOUT

ASRC

Auxiliary

Serial Port

SDIN

ASRC

SDOUT

ASRC

SDIN

ASRC

-VCP_FILT

Inverting

Step-Down

VCP +VCP_FILT

+VCP_FILT

-VCP_FILT

MCLK

MCLK1

MCLK2

Control Port

VD_FILT

Digital Mixer

Volume, Mute, Limiter

MIC2_SDET

Audio Serial Port

Voice Serial Port

Auxiliary Serial Port

MIC/Line Input Path

CS42L73

Ultralow Power Mobile Audio and Telephony CODEC

Product Overview

 Stereo analog-to-digital converter (ADC)  Dual analog or digital mic support  Dual mic bias generators  Four digital-to-analog converters (DACs)

coupled to five outputs

– Ground-centered stereo headphone amp. – Ground-centered stereo line output – Mono ear speaker amplifier – Mono 1-W speakerphone amplifier – Mono speakerphone line output for stereo

speakerphone expansion

 Three serial ports with asynchronous sample

rate converters

 Digital audio mixing and routing

Ultralow Power Consumption

 3.8-mW quiescent headphone playback

Applications

 Smart phones, ultramobile PCs, and mobile

Internet devices

System Features

 Native (no PLL required) support for 6/12/

24 MHz, 13/26 MHz, and 19.2/38.4 MHz master clock rates and typical audio clock rates

 Integrated high-efficiency power management

reduces power consumption

– Internal LDO regulator to reduce internal

digital operating voltage to VL/2 V

– Step-down charge pump provides low

headphone/line out supply voltage

– Inverting charge pump accommodates low

system voltage by providing negative rail for HP and line amplifier

 Flexible speakerphone amplifier powering

– 3.00–5.25 V range – Independent cycling

 Power-down management

– Individual controls for ADCs, digital mic

interface, mic bias generators, serial ports, and output amplifiers and associated DACs

 Programmable thermal overload notification  High-speed I²C™ control port (400 kHz)

(Features continued on page 2)

http://www.cirrus.com

JULY '13 DS882F1

CS42L73

Stereo Analog-to-Digital Features

 91-db dynamic range (A-weighted)  -85 dB THD+N  Independent ADC channel control  2:1 stereo analog input MUX  Stereo line input: Shared pseudodifferential

reference input

 Dual analog mic inputs

– Pseudodifferential or single-ended – Two, independent, programmable, low-noise

mic bias outputs

– Mic short detect to support headset button

 Analog programmable gain amplifier (PGA)

(+12 to -6 dB in 0.5 dB steps)

 +10 dB or +20 dB analog mic boost in addition

to PGA gain settings

 Programmable automatic level control (ALC)

– Noise gate for noise suppression – Programmable threshold and attack/release

rates

Dual Digital Microphone Interface

 Programmable clock rate: Integer divide by 2 or

4 of internal MCLK

Stereo DAC to Headphone Amplifier

 94-dB dynamic range (A-weighted)  -81 dB THD+N into 32   Integrated step-down/inverting charge pump  Class H amplifier, automatic supply adjustment

– High efficiency –Low EMI

 Pseudodifferential ground-centered outputs  High HP power output at -70/-81 dB THD+N

– 2 x 16/8.1 mW into 16/32 @ 1.8 V

 Pop and click suppression  Analog volume control (+12 to -50 dB in 1 dB

steps; to -76 dB in 2 dB steps) with zero-cross transitions

 Digital volume control (+12 to -102 dB in 0.5 dB

steps) with soft-ramp transitions

 Programmable peak-detect and limiter

Stereo DAC to Line Outputs

 97 dB dynamic range (A-weighted)  -86 dB THD+N  Class-H amplifier  Pseudodifferential ground-centered outputs  1-V  Pop and click suppression  Analog volume control (+12 to -50 dB in 1 dB

line output @ 1.8 V

RMS

steps; to -76 dB in 2 dB steps) with zero-cross transitions

 Digital volume control (+12 to -102 dB in 0.5 dB

steps) with soft-ramp transitions

 Programmable peak-detect and limiter

Mono DAC to Ear Speaker Amplifier

 High-power output at -70 dB (0.032%) THD+N:

45 mW into 16  @ 1.8 V

 Pop and click suppression  Digital volume control (+12 to -102 dB in 0.5 dB

steps) with soft-ramp transitions

 Programmable peak-detect and limiter

Mono DAC to Speakerphone Amplifier

 High output power at 1% THD+N: 1.06/0.76/

0.59 W into 8  @ 5.0/4.2/3.7 V

 Direct battery-powered operation  Pop and click suppression  Digital volume control (+12 to -102 dB in 0.5 dB

steps) with soft-ramp transitions

 Programmable peak-detect and limiter

Mono DAC-to-Speakerphone Line Output

 84 dB dynamic range (A-weighted)  -65 dB THD+N  High voltage (2 V

@ VA = 1.8 V, VP =

RMS

3.7 V) line output to ensure maximum output from a wide variety of external amplifiers

 Pop and click suppression  Digital volume control (+12 to -102 dB in 0.5 dB

steps) with soft-ramp transitions

 Programmable peak-detect and limiter

Serial Ports

 Three independent serial ports: auxiliary serial

port (XSP), audio serial port (ASP), and voice serial port (VSP)

 8.00, 11.025, 12.00, 16.00, 22.05, 24.00,

32.00, 44.10, and 48.00 kHz sample rates

 All ports support master or slave operation with

I²S interface

 XSP and VSP support slave operation with

PCM interface

 XSP and ASP are stereo-input/stereo-output

to/from digital mixer

 VSP is mono-input/stereo-output to/from digital

mixer

 Integrated asynchronous sample rate

converters

2 DS882F1

CS42L73

General Description

The CS42L73 is a highly integrated, low-power, audio and telephony CODEC for portable applications such as smartphones and ultramobile personal computers.

The CS42L73 features a flexible clocking architecture, allowing the device to use reference clock frequencies of 6, 12, 24, 13, 26, 19.2, or 38.4 MHz, or any standard audio master clock. As many as two reference/master clock sources may be connected; either one can be selected to drive the internal clocks and processing rate of the CS42L73. Thus, multiple master clock sources within a system can be dynamically activated and deactivated to minimize system-level power consumption.

Three asynchronous bidirectional serial ports (auxiliary, audio, and voice serial ports (XSP, ASP, and VSP, respectively) support multiple clock domains of various digital audio sources or destinations. Three low-latency, fast-locking, integrated high-performance asynchronous sample rate converters synchronize and convert the audio samples to the internal processing rate of the CS42L73.

A stereo line input or two mono (one stereo) mic inputs are routed to a stereo ADC. The mic inputs may be selectively preamplified by +10 or +20 dB. Two independent, low-noise mic bias voltage supplies are also provided. A PGA is applied to the inputs before they reach the ADC.

The stereo input path that follows the stereo ADC begins with a multiplexer to selectively choose data from a digital mic interface. Following the multiplexer, the data is decimated, selectively DC high-pass filtered, channel-swapped or mono-to-stereo routed (fanned-out), and volume adjusted or muted. The volume levels can be automatically adjusted via a programmable ALC and noise gate.

A digital mixer is used to mix and route the CS42L73’s inputs (analog inputs to ADC, digital mic, or serial ports) to outputs (DAC-fed amplifiers or serial ports). There is independent attenuation on each mixer input for each output.

The processing along the output paths from the digital mixer to the two stereo DACs includes volume adjustment and mute control. A peak-detector can be used to automatically adjust the volume levels via a programmable limiter.

The first stereo DAC feeds the stereo headphone and line output amplifiers, which are powered from a dedicated positive supply. An integrated charge pump provides a negative supply. This allows a ground-centered analog output with a wide signal swing, and eliminates external DC-blocking capacitors while reducing pops and clicks. Tri-level Class H amplification is used to reduce power consumption under low-signal-level conditions. Analog volume controls are provided on the stereo headphone and line outputs.

The second stereo DAC feeds several mono outputs. The left channel of the DAC sources a mono,

differential-drive, speakerphone amplifier for driving the handset speakerphone. The right channel sources a mono, differential-drive, earphone amplifier for driving the handset earphone. The right channel is also routed to

a mono, differential-drive, speakerphone line output, which may be connected to an external amplifier to implement a stereo speakerphone configuration when it is used in conjunction with the integrated speakerphone amplifier.

The CS42L73 implements robust power management to achieve ultralow power consumption. High granularity in power-down controls allows individual functional blocks to be powered down when unused. The internal low-dropout regulator (LDO) saves power by running the internal digital circuits at half the logic interface supply voltage (VL/2).

A high-speed I

The CS42L73 is available in space-saving 64-ball WLCSP and 65-ball FBGA packages for the commercial (-40° to +85° C) grade.

C control port interface capable of up to 400 kHz operation facilitates register programming.

DS882F1 3

1. PACKAGE PIN/BALL ASSIGNMENTS AND CONFIGURATIONS ..................................................... 12

1.1 64-Ball Wafer-Level Chip Scale Package (WLCSP) ...................................................................... 12

1.2 65-Ball Fine-Pitch Ball Grid Array (FBGA) Package ...................................................................... 13

1.3 Pin/Ball Descriptions ...................................................................................................................... 14

1.4 Digital Pin/Ball I/O Configurations .................................................................................................. 16

2. TYPICAL CONNECTION DIAGRAM ................................................................................................... 17

2.1 Low-Profile Charge-Pump Capacitors ........................................................................................... 18

2.2 Ceramic Capacitor Derating ........................................................................................................... 18

3. CHARACTERISTIC AND SPECIFICATIONS ...................................................................................... 19

4. APPLICATIONS ................................................................................................................................... 41

4.1 Overview ........................................................................................................................................ 41

4.1.1 Basic Architecture ................................................................................................................. 41

4.1.2 Line and Microphone Inputs .................................................................................................. 41

4.1.3 Line and Headphone Outputs (Class H, Ground-Centered Amplifiers) ................................. 41

4.1.4 Digital Mixer ........................................................................................................................... 41

4.1.5 Power Management .............................................................................................................. 41

4.2 Internal Master Clock Generation .................................................................................................. 42

4.3 Thermal Overload Notification ....................................................................................................... 42

4.4 Pseudodifferential Outputs ............................................................................................................. 43

4.5 Class H Amplifier .......................................................................................................................... 44

4.5.1 Power Control Options .......................................................................................................... 44

4.5.1.1 Standard Class AB Operation (Mode 001, 010, and 011) ......................................... 45

4.5.1.2 Adapt-to-Volume Settings (Mode 000) ...................................................................... 45

4.5.1.3 Adapt-to-Output Signal (Mode 111) ........................................................................... 46

4.5.2 Power Supply Transitions ...................................................................................................... 46

4.5.3 Efficiency ............................................................................................................................... 49

4.6 DAC Limiter .................................................................................................................................... 49

4.7 Analog Output Current Limiter ....................................................................................................... 51

4.8 Serial Ports .................................................................................................................................... 51

4.8.1 Power Management .............................................................................................................. 51

4.8.2 I/O .......................................................................................................................................... 51

4.8.3 High-impedance Mode .......................................................................................................... 52

4.8.4 Master and Slave Timing ....................................................................................................... 52

4.8.4.1 SCLK = MCLK Modes ............................................................................................... 53

4.8.5 Serial Port Sample Rates and Master Mode Settings ........................................................... 53

4.8.6 Formats ................................................................................................................................. 54

4.8.6.1 I²S Format .................................................................................................................. 55

4.8.6.2 PCM Format .............................................................................................................. 55

4.8.7 Mono/Stereo .......................................................................................................................... 57

4.8.8 Data Bit Depths ..................................................................................................................... 57

4.8.8.1 I²S Format Bit Depths ................................................................................................ 57

4.8.8.2 PCM Format Bit Depths ............................................................................................. 58

4.9 Asynchronous Sample Rate Converters (ASRCs) ......................................................................... 59

4.10 Input Paths ................................................................................................................................... 59

4.10.1 Input Path Source Selection and Powering ......................................................................... 59

4.10.2 Digital Microphone (DMIC) Interface ................................................................................... 60

4.10.2.1 DMIC Interface Description ...................................................................................... 60

4.10.2.2 DMIC Interface Signaling ......................................................................................... 60

4.10.2.3 DMIC Interface Powering ......................................................................................... 60

4.10.2.4 DMIC Interface Clock Generation ............................................................................ 61

4.11 Digital Mixer ................................................................................................................................. 61

4.11.1 Mono and Stereo Paths ....................................................................................................... 63

CS42L73

4 DS882F1

CS42L73

4.11.2 Mixer Input Attenuation Adjustment .................................................................................... 63

4.11.3 Powered-Down Mixer Inputs ...............................................................................................64

4.11.4 Avoiding Mixer Clipping ....................................................................................................... 64

4.11.5 Mixer Attenuation Values .................................................................................................... 65

4.12 Recommended Operating Procedures ........................................................................................ 65

4.12.1 Initial Power-Up Sequence .................................................................................................. 65

4.12.2 Power-Up Sequence (xSP to HP/LO) ................................................................................. 66

4.12.3 Power-Down Sequence (xSP to HP/LO) ............................................................................. 67

4.12.4 Recommended Sequence for Modification of the MCLK Signal ......................................... 67

4.12.5 Microphone Enabling/Switching Sequence ......................................................................... 68

4.12.6 Final Power-Down Sequence .............................................................................................. 68

4.13 Using MIC2_SDET as Headphone Plug Detect ........................................................................... 69

4.14 Headphone Plug Detect and Mic Short Detect ............................................................................ 70

4.15 Interrupts ...................................................................................................................................... 70

4.16 Control Port Operation ................................................................................................................. 71

4.16.1 I²C Control ........................................................................................................................... 71

4.17 Fast Start Mode ........................................................................................................................... 73

4.18 Headphone High-Impedance Mode .............................................................................................75

5. REGISTER QUICK REFERENCE ........................................................................................................ 76

6. REGISTER DESCRIPTION .................................................................................................................. 81

6.1 Fast Mode Enable (Address 00h) .................................................................................................. 81

6.1.1 Test Bits ................................................................................................................................ 81

6.2 Device ID A and B (Address 01h), C and D (Address 02h), and E (Address 03h) (Read Only) . 81

6.2.1 Device I.D. (Read Only) ........................................................................................................ 81

6.3 Revision ID (Address 05h) (Read Only) ......................................................................................... 81

6.3.1 Alpha Revision (Read Only) .................................................................................................. 81

6.3.2 Metal Revision (Read Only) .................................................................................................. 81

6.4 Power Control 1 (Address 06h) ...................................................................................................... 82

6.4.1 Power Down ADC x ............................................................................................................... 82

6.4.2 Power Down Digital Mic x ...................................................................................................... 82

6.4.3 Discharge Filt+ Capacitor ...................................................................................................... 82

6.4.4 Power Down Device .............................................................................................................. 82

6.5 Power Control 2 (Address 07h) ...................................................................................................... 83

6.5.1 Power Down MICx Bias ......................................................................................................... 83

6.5.2 Power Down VSP .................................................................................................................. 83

6.5.3 Power Down ASP SDOUT Path ............................................................................................ 83

6.5.4 Power Down ASP SDIN Path ................................................................................................ 83

6.5.5 Power Down XSP SDOUT Path ............................................................................................ 83

6.5.6 Power Down XSP SDIN Path ................................................................................................

6.6 Power Control 3 and Thermal Overload Threshold Control (Address 08h) ................................... 84

6.6.1 Thermal Overload Threshold Settings ................................................................................... 84

6.6.2 Power Down Thermal Sense .................................................................................................84

6.6.3 Power Down Speakerphone Line Output .............................................................................. 84

6.6.4 Power Down Ear Speaker ..................................................................................................... 84

6.6.5 Power Down Speakerphone ..................................................................................................84

6.6.6 Power Down Line Output ...................................................................................................... 85

6.6.7 Power Down Headphone ...................................................................................................... 85

6.7 Charge Pump Frequency and Class H Configuration (Address 09h) ............................................ 85

6.7.1 Charge Pump Frequency ...................................................................................................... 85

6.7.2 Adaptive Power Adjustment .................................................................................................. 85

6.8 Output Load, Mic Bias, and MIC2 Short Detect Configuration (Address 0Ah) ............................... 86

6.8.1 VP Supply Minimum Voltage Setting ..................................................................................... 86

6.8.2 Speakerphone Light Load Mode Enable ............................................................................... 86

6.8.3 Mic Bias Output Control ........................................................................................................ 86

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CS42L73

6.8.4 Short Detect Automatic Mute Control .................................................................................... 86

6.9 Digital Mic and Master Clock Control (Address 0Bh) ..................................................................... 87

6.9.1 Digital Mic Shift Clock Divide Ratio ....................................................................................... 87

6.9.2 Master Clock Source Selection ............................................................................................. 87

6.9.3 Master Clock Divide Ratio ..................................................................................................... 87

6.9.4 Master Clock Disable ............................................................................................................ 87

6.10 XSP Control (Address 0Ch) ......................................................................................................... 88

6.10.1 Tristate XSP Interface ......................................................................................................... 88

6.10.2 XSP Digital Interface Format ............................................................................................... 88

6.10.3 XSP PCM Interface Mode ................................................................................................... 88

6.10.4 XSP PCM Format Bit Order ................................................................................................88

6.10.5 XSP SCLK Source Equals MCLK ....................................................................................... 88

6.11 XSP Master Mode Clocking Control (Address 0Dh) .................................................................... 89

6.11.1 XSP Master/Slave Mode ..................................................................................................... 89

6.11.2 XSP Master Mode Clock Control Dividers ........................................................................... 89

6.12 ASP Control (Address 0Eh) ......................................................................................................... 89

6.12.1 Tristate ASP Interface ......................................................................................................... 89

6.12.2 ASP Sample Rate ............................................................................................................... 90

6.12.3 ASP SCLK Source Equals MCLK ....................................................................................... 90

6.13 ASP Master Mode Clocking Control (Address 0Fh) ..................................................................... 90

6.13.1 ASP Master/Slave Mode ..................................................................................................... 90

6.13.2 ASP Master Mode Clock Control Dividers ........................................................................... 90

6.14 VSP Control (Address 10h) .......................................................................................................... 91

6.14.1 Tristate VSP Interface .................................................................................................

6.14.2 VSP Digital Interface Format ............................................................................................... 91

6.14.3 VSP PCM Interface Mode ................................................................................................... 91

6.14.4 VSP PCM Format Bit Order ................................................................................................91

6.14.5 VSP SDIN Location ............................................................................................................. 92

6.14.6 VSP SCLK Source Equals MCLK ....................................................................................... 92

6.15 VSP Master Mode Clocking Control (Address 11h) ..................................................................... 92

6.15.1 VSP Master/Slave Mode ..................................................................................................... 92

6.15.2 VSP Master Mode Clock Control Dividers ........................................................................... 92

6.16 VSP and XSP Sample Rate (Address 12h) ................................................................................. 93

6.16.1 VSP Sample Rate ............................................................................................................... 93

6.16.2 XSP Sample Rate ............................................................................................................... 93

6.17 Miscellaneous Input and Output Path Control (Address 13h) ...................................................... 94

6.17.1 Digital Swap/Mono .............................................................................................................. 94

6.17.2 Input Path Channel B=A ...................................................................................................... 94

6.17.3 PREAMP and PGA Channel B=A ....................................................................................... 94

6.17.4 PGA Soft-Ramp ................................................................................................................... 95

6.17.5 Analog Zero Cross .............................................................................................................. 95

6.17.6 Digital Soft-Ramp ................................................................................................................ 96

6.17.7 Analog Output Soft Ramp ................................................................................................... 96

6.18 ADC/Input Path Control (Address 14h) ........................................................................................ 97

6.18.1 PGA x Input Select .............................................................................................................. 97

6.18.2 Boost x ................................................................................................................................ 97

6.18.3 Invert ADCx Signal Polarity ................................................................................................. 97

6.18.4 Input Path x Digital Mute ..................................................................................................... 97

6.19 Mic PreAmp and PGA Volume Control: Channel A (Mic 1, Address 15h) and Channel B

(Mic 2, Address 16h) .......................................................................................................................... 98

6.19.1 Mic PREAMP x Volume ....................................................................................................... 98

6.19.2 PGAx Volume ...................................................................................................................... 98

6.20 Input Path x Digital Volume Control: Channel A (Address 17h) and B (Address 18h) ................. 99

6.20.1 Input Path x Digital Volume Control .................................................................................... 99

........ 91

6 DS882F1

CS42L73

6.21 Playback Digital Control (Address 19h) ..................................................................................... 100

6.21.1 Speakerphone [A], Ear Speaker/Speakerphone Line Output [B] (SES) Playback

Channels B=A ............................................................................................................................ 100

6.21.2 Headphone/Line Output (HL) Playback Channels B=A .................................................... 100

6.21.3 Limiter Soft-Ramp Disable ................................................................................................ 100

6.21.4 Ear Speaker/Speakerphone Line Output Digital Mute ...................................................... 100

6.21.5 Speakerphone Digital Mute ...............................................................................................101

6.21.6 Headphone/Line Output (HL) x Digital Mute ..................................................................... 101

6.22 Headphone/Line Output (HL) x Digital Volume Control: Channel A (Address 1Ah) and B

(Address 1Bh) .................................................................................................................................. 101

6.22.1 Headphone/Line Output (HL) x Digital Volume Control ..................................................... 101

6.23 Speakerphone Out [A] Digital Volume Control (Address 1Ch) .................................................. 102

6.23.1 Speakerphone Out [A] Digital Volume Control .................................................................. 102

6.24 Ear Speaker/Speakerphone Line Output (ESL) [B] Digital Volume Control (Address 1Dh) ...... 102

6.24.1 Ear Speaker/Speakerphone Line Output (ESL) [B] Digital Volume Control ...................... 102

6.25 Headphone Analog Volume Control: Channel A (Address 1Eh) and B (Address 1Fh) ............. 103

6.25.1 Headphone x Analog Mute ................................................................................................ 103

6.25.2 Headphone x Analog Volume Control ............................................................................... 103

6.26 Line Output Analog Volume Control: Channel A (Address 20h) and B (Address 21h) .............. 104

6.26.1 Line Output x Analog Mute ................................................................................................ 104

6.26.2 Line Output x Analog Volume Control ............................................................................... 104

6.27 Stereo Input Path Advisory Volume (Address 22h) ................................................................... 105

6.27.1 Stereo Input Path Advisory Volume .................................................................................. 105

6.28 XSP Input Advisory Volume (Address 23h) ............................................................................... 105

6.28.1 XSP Input Advisory Volume .............................................................................................. 105

6.29 ASP Input Advisory Volume (Address 24h) ............................................................................... 106

6.29.1 ASP Input Advisory Volume .............................................................................................. 106

6.30 VSP Input Advisory Volume (Address 25h) ............................................................................... 106

6.30.1 VSP Input Advisory Volume .............................................................................................. 106

6.31 Limiter Attack Rate Headphone/Line Output (HL) (Address 26h) .............................................. 107

6.31.1 Limiter Attack Rate HL ...................................................................................................... 107

6.32 Limiter Control, Release Rate Headphone/Line Output (HL) (Address 27h) ............................. 107

6.32.1 Peak Detect and Limiter HL ..............................................................................................107

6.32.2 Peak Signal Limit All Channels HL .................................................................................... 107

6.32.3 Limiter Release Rate HL ................................................................................................... 107

6.33 Limiter Min/Max Thresholds Headphone/Line Output (HL) (Address 28h) ................................ 108

6.33.1 Limiter Maximum Threshold HL ........................................................................................ 108

6.33.2 Limiter Cushion Threshold HL ........................................................................................... 108

6.34 Limiter Attack Rate Speakerphone [A] (Address 29h) ............................................................... 108

6.34.1 Limiter Attack Rate Speakerphone [A] .............................................................................. 108

6.35 Limiter Control, Release Rate Speakerphone [A] (Address 2Ah) .............................................. 109

6.35.1 Peak Detect and Limiter Speakerphone [A] ...................................................................... 109

6.35.2 Peak Signal Limit All Channels Speakerphone ................................................................. 109

6.35.3 Limiter Release Rate Speakerphone [A] ........................................................................... 109

6.36 Limiter Min/Max Thresholds Speakerphone [A] (Address 2Bh) ................................................. 110

6.36.1 Limiter Maximum Threshold Speakerphone [A] ................................................................ 110

6.36.2 Limiter Cushion Threshold Speakerphone [A] ................................................................... 110

6.37 Limiter Attack Rate Ear Speaker/Speakerphone Line Output (ESL) [B] .................................... 111

6.37.1 Limiter Attack Rate ESL [B] ............................................................................................... 111

6.38 Limiter Control, Release Rate Ear Speaker/Speakerphone Line Output (ESL) [B]

(Address 2Dh) .................................................................................................................................. 111

6.38.1 Peak Detect and Limiter ESL [B] ....................................................................................... 111

6.38.2 Limiter Release Rate ESL [B] ............................................................................................111

6.39 Limiter Min/Max Thresholds Ear Speaker/Speakerphone Line Output (ESL) [B] ...................... 112

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CS42L73

6.39.1 Limiter Maximum Threshold ESL [B] ................................................................................. 112

6.39.2 Limiter Cushion Threshold ESL [B] ................................................................................... 112

6.40 ALC Enable and Attack Rate AB (Address 2Fh) ........................................................................ 113

6.40.1 ALC for Channels A and B (ALCx) .................................................................................... 113

6.40.2 ALC Attack Rate for Channels A and B ............................................................................. 113

6.41 ALC Release Rate AB (Address 30h) ........................................................................................ 113

6.41.1 ALC Release Rate for Channels A and B ......................................................................... 113

6.42 ALC Threshold AB (Address 31h) .............................................................................................. 114

6.42.1 ALC Maximum Threshold for Channels A and B ............................................................... 114

6.42.2 ALC Minimum Threshold for Channels A and B ................................................................ 114

6.43 Noise Gate Control AB (Address 32h) .......................................................................................115

6.43.1 Noise Gate Enable for Channels A and B (NGx) .............................................................. 115

6.43.2 Noise gate Threshold and Boost for Channels A and B .................................................... 115

6.43.3 Noise Gate Delay Timing for Channels A and B ............................................................... 115

6.44 ALC and Noise Gate Misc Control (Address 33h) ..................................................................... 116

6.44.1 ALC Ganging of Channels A and B ................................................................................... 116

6.44.2 Noise Gate Ganging of Channels A and B ........................................................................ 116

6.44.3 ALCx Soft-Ramp Disable ..................................................................................................116

6.44.4 ALCx Zero Cross Disable .................................................................................................. 116

6.45 Mixer Control (Address 34h) ..................................................................................................... 117

6.45.1 VSP Mixer Output Stereo .................................................................................................. 117

6.45.2 XSP Mixer Output Stereo .................................................................................................. 117

6.45.3 Mixer Soft-Ramp Enable ................................................................................................... 117

6.45.4 Mixer Soft-Ramp Step Size/Period .................................................................................... 117

6.46 Stereo Mixer Input Attenuation (Addresses 35h through 54h) ................................................... 118

6.46.1 Stereo Mixer Input Attenuation ..........................................................................................119

6.47 Mono Mixer Controls (Address 55h) .......................................................................................... 120

6.47.1 Speakerphone (SPK) Mixer, ASP Select .......................................................................... 120

6.47.2 Speakerphone (SPK) Mixer, XSP Select .......................................................................... 120

6.47.3 Ear Speaker/Speakerphone Line Output (ESL) Mixer, ASP Select .................................. 120

6.47.4 ESL Mixer, Auxiliary Serial Port (XSP) Select ................................................................... 120

6.48 Mono Mixer Input Attenuation (Addresses 56h through 5Dh) .................................................... 121

6.48.1 Mono Mixer Input Attenuation ........................................................................................... 121

6.49 Interrupt Mask Register 1 (Address 5Eh) ...................................................................................122

6.50 Interrupt Mask Register 2 (Address 5Fh) ...................................................................................122

6.51 Interrupt Status Register 1 (Address 60h) .................................................................................122

6.51.1 MIC2 Short Detect ............................................................................................................. 122

6.51.2 Thermal Overload Detect .................................................................................................. 122

6.51.3 Digital Mixer Overflow ....................................................................................................... 123

6.51.4 Input Path x Overflow ........................................................................................................ 123

6.52 Interrupt Status Register 2 (Address 61h) .................................................................................123

6.52.1 Voice ASRC Data Out Lock .............................................................................................. 123

6.52.2 Voice ASRC Data In Lock .................................................................................................123

6.52.3 Audio ASRC Data Out Lock .............................................................................................. 124

6.52.4 Audio ASRC Data In Lock .................................................................................................124

6.52.5 Auxiliary ASRC Data Out Lock .......................................................................................... 124

6.52.6 Auxiliary ASRC Data In Lock .............................................................................................124

6.53 Fast Mode 1 (Address 7Eh) ....................................................................................................... 125

6.53.1 Fast Mode Bits 15:8 .......................................................................................................... 125

6.54 Fast Mode 2 (Address 7Fh) ....................................................................................................... 125

6.54.1 Fast Mode Bits 7:0 ............................................................................................................ 125

7. PCB LAYOUT CONSIDERATIONS ...................................................................................................125

7.1 Power Supply ............................................................................................................................... 125

7.2 Grounding .................................................................................................................................... 125

8 DS882F1

CS42L73

7.3 Layout With Fine-Pitch, Ball-Grid Packages ................................................................................ 125

8. PERFORMANCE DATA ..................................................................................................................... 126

8.1 Analog Input Path Attributes ........................................................................................................ 126

8.1.1 PGA Analog Volume Nonlinearity (DNL and INL) ............................................................... 126

8.2 Analog Mic/Line ADC and Digital Mic Input Path Attributes ......................................................... 127

8.2.1 Input Path Digital LPF Response ........................................................................................ 127

8.2.2 Input Path Digital HPF Response ........................................................................................ 128

8.3 Core Circuitry Attributes ............................................................................................................... 129

8.3.1 ASRC Attributes .................................................................................................................. 129

8.3.1.1 Response ................................................................................................................. 129

8.3.1.2 Group Delay ............................................................................................................. 130

8.3.1.3 Lock Time ................................................................................................................ 130

8.4 Analog Output Paths Attributes .................................................................................................... 131

8.4.1 DAC Digital LPF Response .................................................................................................131

8.4.2 DAC HPF Response ........................................................................................................... 132

8.4.3 Output Analog Volume Nonlinearity (DNL and INL) ............................................................ 132

8.4.4 Startup Times ...................................................................................................................... 133

9. PARAMETER DEFINITIONS .............................................................................................................. 134

10. PACKAGE DIMENSIONS ................................................................................................................ 135

10.1 WLCSP Package ....................................................................................................................... 135

10.2 FBGA Package .......................................................................................................................... 136

11. THERMAL CHARACTERISTICS ..................................................................................................... 137

12. ORDERING INFORMATION ............................................................................................................ 137

13. REFERENCES .................................................................................................................................. 137

14. REVISION HISTORY ........................................................................................................................ 138

LIST OF FIGURES

Figure 1.Typical Connection Diagram ....................................................................................................... 17

Figure 2.MICx Dynamic Range Test Configuration ................................................................................... 24

Figure 3.Analog Input CMRR Test Setup .................................................................................................. 24

Figure 4.LINEIN_REF/MICx_REF Input Voltage Test Setup .................................................................... 24

Figure 5.Headphone Output Test Configuration ....................................................................................... 28

Figure 6.Line Output Test Configuration ................................................................................................... 29

Figure 7.Ear Speaker Output Test Configuration ...................................................................................... 30

Figure 8.Speakerphone and Speakerphone Line Output Test Configuration ........................................... 32

Figure 9.Power Consumption Test Configuration ..................................................................................... 34

Figure 10.Power and Reset Sequencing .................................................................................................. 36

Figure 11.Digital Mic Interface Timing ....................................................................................................... 37

Figure 12.Serial Port Interface Timing—I²S Format .................................................................................. 39

Figure 13.Serial Port Interface Timing—PCM Format ..............................................................................39

Figure 14.I²C Control Port Timing ............................................................................................................. 40

Figure 15.Single-Ended Output Configuration .......................................................................................... 43

Figure 16.Pseudodifferential Output Configuration ................................................................................... 43

Figure 17.Class H Operation ..................................................................................................................... 44

Figure 18.Class H Control - Adapt-to-Volume Mode ................................................................................. 45

Figure 19.VCP_FILT Transitions ............................................................................................................... 47

Figure 20.VCP_FILT Hysteresis ............................................................................................................... 48

Figure 21.Input Power vs. Output Power .................................................................................................. 49

Figure 22.Peak Detect & Limiter ............................................................................................................... 50

Figure 23.HP Short Circuit Setup .............................................................................................................. 51

Figure 24.Line Short Circuit Setup ............................................................................................................ 51

Figure 25.Serial Port Busing when Mastering Timing ............................................................................... 52

Figure 26.Serial Port Busing When Slave Timed ...................................................................................... 52

DS882F1 9

CS42L73

Figure 27.I²S Format ................................................................................................................................. 55

Figure 28.PCM Format—Mode 0 .............................................................................................................. 56

Figure 29.PCM Format—Mode 1 .............................................................................................................. 56

Figure 30.PCM Format—Mode 2 .............................................................................................................. 57

Figure 31.Digital Mic Interface Signaling ................................................................................................... 60

Figure 32.Digital Mixer Diagram ................................................................................................................ 62

Figure 33.Connection Diagram for Using MIC2_SDET as Headphone Detect ......................................... 69

Figure 34.Flow Diagram Showing the INT

Figure 35.Connection Diagram for Headphone Detect with Additional Short Detect ................................ 70

Figure 36.Example of Rising-Edge Sensitive, Sticky, Interrupt Status Bit Behavior ................................. 71

Figure 37.Control Port Timing, I²C Writes with Autoincrement ................................................................. 72

Figure 38.Control Port Timing, I²C Reads with Autoincrement ................................................................. 72

Figure 39.Control Port Timing, I²C Reads with Preamble and Autoincrement .......................................... 73

Figure 40.Fast Start Pop ........................................................................................................................... 74

Figure 41.Start Up Transition Diagram ..................................................................................................... 75

Figure 42.PGA DNL ................................................................................................................................ 126

Figure 43.PGA INL .................................................................................................................................. 126

Figure 44.PGA + Preamp (+10 dB) DNL ................................................................................................. 126

Figure 45.PGA + Preamp (+10 dB) INL .................................................................................................. 126

Figure 46.PGA + Preamp (+20 dB) DNL ................................................................................................. 127

Figure 47.PGA + Preamp (+20 dB) INL .................................................................................................. 127

Figure 48.Input Path LPF Frequency Response ..................................................................................... 127

Figure 49.Input Path LPF Stopband Rejection ........................................................................................ 127

Figure 50.Input Path LPF Transition Band .............................................................................................. 128

Figure 51.Input Path LPF Transition Band Detail .................................................................................... 128

Figure 52.Input Path HPF Frequency Response ....................................................................................128

Figure 53.ASRC Frequency Response ................................................................................................... 129

Figure 54.ASRC Passband Frequency Response .................................................................................. 129

Figure 55.ASRC Group Delay vs. Serial Port and Internal Sample Rates .............................................. 130

Figure 56.DAC LPF Frequency Response .............................................................................................. 131

Figure 57.DAC LPF Stopband Rejection to 1x Fs ................................................................................... 131

Figure 58.DAC LPF Stopband Rejection to 3x Fs ................................................................................... 131

Figure 59.DAC HPF Frequency Response ............................................................................................. 132

Figure 60.HPOUTx DNL (-50 to +12 dB) ................................................................................................ 132

Figure 61.HPOUTx DNL (-76 to -52 dB) ................................................................................................. 132

Figure 62.HPOUTx INL (-50 to +12 dB) .................................................................................................. 132

Figure 63.HPOUTx INL (-76 to -52 dB) ................................................................................................... 132

Figure 64.LINEOUTx DNL (-50 to +12 dB) ............................................................................................. 133

Figure 65.LINEOUTx DNL (-76 to -52 dB) .............................................................................................. 133

Figure 66.LINEOUTx INL (-50 to +12 dB) ............................................................................................... 133

Figure 67.LINEOUTx INL (-76 to -52 dB) ................................................................................................ 133

Pin State in Response to MIC2_SDET State Changes .......... 69

LIST OF TABLES

Table 1. Internal Master Clock Generation ............................................................................................... 42

Table 2. Example of Impedance in Reference Path .................................................................................. 44

Table 3. Current through VCP with Varying Short Circuits .......................................................................51

Table 4. Supported MCLK1/MCLK2 Rates for Pre-MCLK Mode .............................................................. 53

Table 5. Serial Port Rates and Master Mode Settings .............................................................................. 53

Table 6. Actual xSP_LRCK Rate/Deviation Selector for Note 3 ............................................................... 54

Table 7. Supported Serial Port Formats .................................................................................................... 54

Table 8. Input Path Source Select and Digital Power States .................................................................... 59

Table 9. Digital Mic Interface Power States .............................................................................................. 60

Table 10. Digital Microphone Interface Clock Generation ......................................................................... 61

10 DS882F1

CS42L73

Table 11. Digital Mixer Soft Ramp Rates .................................................................................................. 63

Table 12. Digital Mixer Nonclipping Attenuation Settings ......................................................................... 64

Table 13. Start Up Times .......................................................................................................................... 73

Table 14. Start Up Transition Values ........................................................................................................ 75

Table 15. ASRC Lock Times ................................................................................................................... 130

Table 16. Analog Output Startup Times .................................................................................................. 133

Table 17. WLCSP Package Dimensions ................................................................................................. 135

Table 18. FBGA Package Dimensions .................................................................................................... 136

DS882F1 11

1. PACKAGE PIN/BALL ASSIGNMENTS AND CONFIGURATIONS

Top-Down

(Though Package)

View

SPK_VQ

XSP_SDIN

DGND

LINEINA

MIC1

HPOUTA

-VCP_FILT

XSP_SCLK

ASP_LRCK

XSP_SDOUT

H1 H2

B1 B2

A1 A2

H3 H4

EAROUT-

B3 B4

LINEIN_REF

LINEINB

H7 H8

ASP_SDOUT

MCLK1

ASP_SDIN

VD_FILT

Ball A1 Location Indicator

VP HPOUTB

DMIC_SCLK

PGND

MIC2

XSP_LRCK

DMIC_SD

C1 C2 C3 C4

MIC1_REF

VSP_SDOUT

ASP_SCLK

VSP_SDIN

SCL

MICB_FILT

THERM

D1 D2 D3 D4

MIC2_REF

VSP_SCLK

MCLK2

VSP_LRCK

ANA_VQ

THERM

E1 E2 E3 E4

MIC2_BIAS

VCP

E7 E8

FLYP

FILT+

LINEOUTB

SPKLINEO+

F1 F2 F3 F4

+VCP_FILT

LINEOUTA

FLYC

SPKLINEO-

AGND

LINEO_REF

SPKOUT+

G1 G2 G3 G4

EAROUT+

CPGND

HPOUT_REF

FLYN

SPKOUT-

SDA

INT

THERM

RESET

MIC2_SDET

MIC1_BIAS

VA I/O VL I/OVP I/O

VCP I/O Ground

1.1 64-Ball Wafer-Level Chip Scale Package (WLCSP)

CS42L73

12 DS882F1

1.2 65-Ball Fine-Pitch Ball Grid Array (FBGA) Package

Top-Down

(Though Package)

View

SPKLINEO-

ASP_LRCK

DMIC_SD

VSP_SDIN

MIC1_BIAS

MIC2_BIAS

ASP_SDOUT

XSP_SDIN

ASP_SCLK

H1 H2

B1 B2

A1 A2

H3 H4

-VCP_FILT

HPOUT_REF

B3 B4

VD_FILT

MCLK2

H7 H8

DMIC_SCLK

XSP_SDOUT

XSP_SCLK

XSP_LRCK

Ball A1 Location Indicator

SPKLINEO+

MCLK1

LINEO_REF

VSP_SDOUT

C1 C2

VSP_SCLK

LINEIN_REF

VSP_LRCK

GND

D1 D2 D4

VCP GND

LINEINA

FLYP

GND

E1 E2 E4

+VCP_FILT

MIC2_REF

FLYC

GND

F1 F2 F4

GND

MIC1_REF

FLYN

G1 G2

LINEOUTA

MIC1

VA I/O VL I/OVP I/O

ASP_SDIN

GND

LINEOUTB

SCL

FILT+

SDA

LINEINB

MIC2

MICB_FILT

ANA_VQ

EAROUT-

EAROUT+

J1 J2 J3 J4

HPOUTA

HPOUTB

J7 J8

SPKOUT+ SPKOUT-

SPK_VQ VA

INT

RESET

MIC2_SDET

VCP I/O Ground

CS42L73

DS882F1 13

1.3 Pin/Ball Descriptions

Name Location Description

WLCSP FBGA

MCLK1 MCLK2

RESET

SCL C3 A9 Serial Control Port Clock (Input)

B3B2High Speed Clock (Input). Potential clock sources for the converters and the device core. Clock

source for optional serial port mastering.

E6 C9 Reset (Input). The device enters a low-power mode when this pin is driven low.

. Serial clock for the I²C control interfaces.

CS42L73

SDA A3 B9 Serial Control Data (Input/Output)

INT

LINEINA LINEINB

LINEIN_REF A2 C8

MIC1 MIC2

MIC1_REF MIC2_REF

MIC1_BIAS MIC2_BIAS

D3 B8 Interrupt Request (Output). Open-drain active low interrupt request output.

A1 B2

D8D9Analog Line Inputs, A and B (LEFT and RIGHT) (Input)

Analog Input Characteristics specification table.

Analog Line Input Pseudodifferential Reference (Input) input buffers LINEINA and LINEINB.

B1 C1

C2 D2

E3 E2

G8E9Microphone Inputs 1 and 2 (Input)

inputs. The full-scale level is specified in the Analog Input Characteristics specification table.

F8E8Microphone Inputs 1 and 2 Pseudodifferential References (Input)

microphone inputs MIC1 and MIC2.

Microphone Bias Voltages 1 and 2 (Output)

Microphone 2 Short Detect (Input)

MIC2_SDET

F2 H6

interrupts that represent the pressing and releasing of a button that shorts the headset

. SDA is the bidirectional data pin for the I²C control interface.

. The full-scale level is specified in the

. Ground reference for the analog line

. The handset (MIC1) and headset (MIC2) microphone signal

. Ground references for the

. Bias voltage for the microphones MIC1 and MIC2.

. Transitions on this input can be configured to cause

microphone to ground.

DMIC_SCLK B3 B7 Digital Mic Serial Clock (Output). The high-speed clock output to the digital microphone(s).

DMIC_SD

XSP_SCLK

XSP_LRCK C5 A7

C4 A8

A4 A6

Digital Mic Serial Data (Input)

Auxiliary Serial Port (XSP), Serial Clock (Input/Output)

XSP, Left/Right Clock (Input/Output)

. The serialized data input from the digital microphone(s).

. Serial shift clock for the interface.

. Identifies the start of each serialized PCM data word. When

the I²S interface format is selected, this signal also indicates which channel, Left or Right, is currently active on the serial PCM audio data lines.

XSP_SDIN A5 B5 XSP, Data Input (Input)

XSP_SDOUT B4 B6 XSP, Data Output (Output)

. Input for two’s complement serial PCM audio data.

. Output for two’s complement serial PCM audio data.

ASP_SCLK C6 B4 Audio Serial Port (ASP), Serial Clock (Input/Output)

ASP_LRCK B5 A5

ASP_SDIN A7 A3 ASP, Data Input (Input)

ASP, Left/Right Clock (Input/Output) indicates which channel, Left or Right, is currently active on the serial PCM audio data lines.

. Input for two’s complement serial PCM audio data.

ASP_SDOUT B6 A4 ASP, Data Output (Output)

. Output for two’s complement serial PCM audio data.

. Identifies the start of each serialized PCM data word and

VSP_SCLK D7 C2 Voice Serial Port (VSP), Serial Clock (Input/Output)

Voice Serial Port, Left/Right Clock (Input/Output)

VSP_LRCK D8 D1

data word. When the I²S interface format is selected, this signal also indicates which channel, Left

. Serial shift clock for the interface.

. Identifies the start of each serialized PCM

or Right, is currently active on the serial PCM audio data lines.

VSP_SDIN C8 B1 VSP, Data Input (Input)

VSP_SDOUT C7 C1 VSP, Data Output (Output)

HPOUTA HPOUTB

HPOUT_REF G6 H2

H7 H6

J1J2Headphone Audio Output (Output)

Characteristics specification table.

Pseudodifferential Headphone Output Reference (Input) amplifiers.

. Input for two’s complement serial PCM audio data.

. Output for two’s complement serial PCM audio data.

. The full-scale output level is specified in the HP Output

. Ground reference for the headphone

14 DS882F1

Name Location Description

WLCSP FBGA

LINEOUTA LINEOUTB

F6 F5

G2F2Line Audio Output (Output). The full-scale output level is specified in the Line Output

Characteristics specification table.

LINEO_REF G5 H3 Pseudodifferential Line Output Reference (Input)

EAROUT+ EAROUT-

SPKOUT+ SPKOUT-

SPKLINEO+ SPKLINEO-

VA H1 J9 Analog Power (Input)

J8J7Ear Speaker Audio Output (Output)

J4J6Speakerphone Audio Output (Output)

H4H5Speakerphone Audio Line Output (Output)

H4 J5

Output Characteristics specification table.

Speakerphone Output Characteristics specification table.

Speakerphone Line Output Characteristics specification table.

. Power supply for the internal analog section.

Speakerphone Power (Input) generators.

VCP E7 D2 Step-down Charge Pump Power (Input)

VL B7 A1

+VCP_FILT F7 E2

-VCP_FILT

FLYP

H8 H1

E8 E1

FLYC F8 F1

FLYN G8 G1

VD_FILT B8 A2

Digital Interface/Core Power (Input) port, and digital mic interface. Power supply for the digital core logic step-down regulator.

Step-down Charge Pump Filter Connection (Output) pump that provides the positive rail for the headphone and line amplifiers.

Inverting Charge Pump Filter Connection (Output) pump that provides the negative rail for the headphone and line amplifiers.

Charge Pump Cap Positive Node (Output) step-down charge pump’s flying capacitor.

Charge Pump Cap Common Node (Output) amplifiers’ step-down and inverting charge pumps’ flying capacitors.

Charge Pump Cap Negative Node (Output) amplifiers’ inverting charge pump’s flying capacitor.

Regulator Filter Connection (Output) that provides the low voltage power to the digital section.

ANA_VQ E1 G9 Quiescent Voltage, Analog (Output)

. The full-scale output level is specified in the Ear Speaker

. The full-scale output level is specified in the

. Power supply for the speakerphone output amplifier and mic bias

. Power supply for the step-down charge pump.

. Power Supply for the serial PCM audio ports, I²C control

. Positive node for the headphone and line amplifiers’

. Common positive node for the headphone and line

. Negative node for the headphone and line

. Power supply filter connection for the step-down regulator

. Filter connection for the internal VA quiescent voltage.

CS42L73

. Ground reference for the line amplifiers.

. Power supply from the step-down charge

. Power supply from the inverting charge

SPK_VQ H5 J3 Quiescent Voltage, Speaker (Output)

FILT+ F1 H9 Positive Voltage Reference (Output)

MICB_FILT D1 F9

AGND G1 N/A Analog Ground (Input)

PGND H3 N/A

CPGND G7 N/A

DGND A8 N/A Digital Ground (Input)

D4, D5, D6, E4,

GND N/A

E5, E6,

F4, F5,

THERM

D4, D5,

E4, E5

NC - -

Microphone Bias Source Voltage Filter (Output) voltage used for the MICx_BIAS outputs.

. Ground reference for the internal analog section.

Speakerphone Ground (Input) output amplifiers. Connect to ground plane(s) on board to conduct heat away from the part.

Charge Pump Ground (Input) charge pump.

. Ground reference for the internal digital section.

Ground

. Ground reference for internal analog (AGND), speakerphone and speakerphone line

output amplifiers (PGND), internal headphone and line amplifiers (CPGND), and the internal digital section (DGND). These balls also provide thermal relief for the device. Connect to the Ground plane of the circuit board.

Thermal Relief Balls

N/A

are not electrically connected to the device.

No Connect. No connection is required for these pins.

. Connect to the Ground plane of the circuit board. The Thermal Relief Balls

. Filter connection for the internal VP quiescent voltage.

. Positive reference voltage for the internal sampling circuits.

. Filter connection for the internal quiescent

. Ground reference for the speakerphone and speakerphone line

. Ground reference for the internal headphone and line amplifiers

DS882F1 15

1.4 Digital Pin/Ball I/O Configurations

CS42L73

Power

Supply I/O Name Direction

MCLK1 Input Weak Pull-down

MCLK2

RESET

Input Weak Pull-down

Input -

SCL Input -

SDA Input/Output -

INT Output Weak Pull-up

XSP_SCLK Input/Output Weak Pull-down

XSP_LRCK Input/Output Weak Pull-down

XSP_SDIN Input Weak Pull-down

XSP_SDOUT Output Weak Pull-down

ASP_SCLK Input/Output Weak Pull-down

ASP_LRCK Input/Output Weak Pull-down

ASP_SDIN Input Weak Pull-down

ASP_SDOUT Output Weak Pull-down

VSP_SCLK Input/Output Weak Pull-down

VSP_LRCK Input/Output Weak Pull-down

VSP_SDIN Input Weak Pull-down

VSP_SDOUT Output Weak Pull-down

DMIC_SCLK Output -

DMIC_SD Input Weak Pull-down

Internal

Connections Configuration

Hysteresis on CMOS Input

Hysteresis on CMOS Input/

CMOS Open-drain Output

Hysteresis on CMOS Input/CMOS Output

Hysteresis on CMOS Input

Tristateable CMOS Output

Hysteresis on CMOS Input/

CMOS Output

Hysteresis on CMOS Input/CMOS Output

Hysteresis on CMOS Input

Tristateable CMOS Output

Hysteresis on CMOS Input/CMOS Output

Hysteresis on CMOS Input

Tristateable CMOS Output

CMOS Output

Hysteresis on CMOS Input

Notes:

• All outputs are disabled when RESET is active.

• Internal weak pull up/down minimum and typical resistances are 550 k and 1 M

• Typical hysteresis is 500 mV within the 650 mV to 1.15 V window.

• The xSP_SCLK, xSP_LRCK, and xSP_SDOUT (x = X, A, or V) outputs may be disabled via register controls as described in sections “High-impedance Mode” on page 52 and “Master and Slave Timing” on page 52.

• Refer to specification table “Digital Interface Specifications and Characteristics” on page 35 for details on the digital I/O DC characteristics (output voltages/load-capacity, input switching threshold voltages, etc.). Inputs without integrated pull-ups/downs must not be left floating. All inputs must be driven or pulled (internally and/or externally) to a valid high or low level, as defined in the specification table.

• Refer to specification tables “Switching Specifications—Serial Ports—I²S Format” on page 38 on page 47, “Switch-

ing Specifications—Serial Ports—PCM Format” on page 39, and “Switching Specifications—Control Port” on page 40 for digital I/O AC characteristics (timing specifications).

• I/O voltage levels must not exceed the I/O’s corresponding power supply voltage. I/O voltage levels must not exceed the voltage listed in “Absolute Maximum Ratings” on page 20.

16 DS882F1

2. TYPICAL CONNECTION DIAGRAM

Note 13

Optional

Bias Res.

Note 9

Note 4

DGND

SCL

SDA

ASP_LRCK

Applicati ons

Processor

ASP_SCLK

ASP_SDIN

ASP_SDOUT

CS42L73

MIC2_B IAS

Line Level Out Left & Right

SPKOUT+

SPKOUT-

MIC2

MIC2_R EF

2.2 µF

SPK_VQ

AGND

2.2 µF

FILT+

EAROUT+

EAROUT-

VBAT

LINEINA

Line In

Left

100 k

LINEINB

Line In

Right

100 k

0.1 µF 4.7 µF

Note 2

2.2 µF

Note 1

+VCP_FILT

FLYC

FLYN

-VCP_FILT

2.2 µF

VCP

VANA

FLYP

2.2 µF

HPOUTB

HPOUTA

100 

33 nF

HPOUT_REF

LINEOUTB

LINEOUTA

LINEIN_REF

INA

VSP_LRCK

Baseband Processor

MCLK1

VSP_SCLK

VSP_SDIN

VSP_SDOUT

2.2 µF

VD_FILT

1.0 µF

LINEO_RE F

CPGND

INA

PGND

MIC1_B IAS

MIC1

MIC1_R EF

ANA_VQ

4.7 µF

INT

RESET

INM

Note 7

1 µF

INM

Note 7

Note 8

Headphone Out Left & Right

100 

33 nF

Speakerphone (Left)

Ear Speake r (Receiver)

Note 6

***

Note 5

I_P

3300 pF

562 

3300 pF

Note 10

Optional

LPF

Ground Ring

***

Note 4

Note 3

0.1 µF

Note 11

Note 12

MCLK2

DMIC_SD

DMIC_SCLK

SPKLINEO+

SPKLINEO-

XSP_LRCK

XSP_SCLK

XSP_SDIN

XSP_SDOUT

MICB_F ILT

Note 4

4.7 µF

*!*

BIAS

Note 9

Headset

Microphone

Handset

Microphone

Note 9

1 µF

Note 8

Note 6

BIAS

MIC2_SDET

Speakerphone (Right)

L/R DATA

Bluetooth

Transceiver

Cellular

Voice

AEC

Right /Data2

Digit al

Microphone

Left/Data1

Digit al

Microphone

VANA

0.1 µF

PMU

USB +5 V

VBAT

LDO

Switching

Regulator

Reset

Generator

+1.8 V

VDIG

VBAT

Class-D

CS35L0x

*!*

Notes:

1. The headphone amplifier’s output power and distortion are rated using t he nominal capacitance shown.

Larger capacitanc e reduces the ripple on the inter nal amplifiers’ suppl ies and in turn reduces the amplif ier’s distort ion at high output power levels. Smaller capaci tance may not sufficiently r educe ripple to achieve the rated output power and distortion. Since the act ual value of typical X7R/X5R cer amic capacitors deviates fr om the nominal val ue by a percentage specified in the manufact urer’s data sheet, capacit ors should be selected based on the minimum output power and maximum dist ortion required.

2. The headphone amplifier’ s output power and distortion ar e rated using the nominal capacitance shown and using the defaul t charge pump switching frequency. The requi red capacitance follows an inver se relationship with the char ge pump’s switchi ng frequency. When increasing the switchi ng frequency, the capacitance may decrease; when lowering the switchi ng frequency, the capaci tance must increase. Since the actual val ue of typical X7R/X5R cerami c capacitors deviates from the nominal value by a percentage specified i n the manufacturer’ s data sheet, capacitors should be sel ected based on the minimum output power, maximum distort ion and maximum charge pump switching frequency required.

3. Lowering the capacitance below the value shown will affect PSRR, ADC-DAC isolation and intermodulation, interchannel isolation and intermodulati on and THD+N performance.

4. Additional bulk capacitance may be added to improve PSRR at low frequencies .

5. Series resi stance in the path of the power suppli es must be avoided. Any voltage drop on VCP direct ly affects

the negative char ge pump supply (-VHPFILT) and cl ips the audio output.

6. The mic cartri dge dictates the value of R

BIAS

, a bias resi stor used with electret condenser microphones.

7. The reference ter minal of the MICx inputs connects t o the ground pin of the microphone cartr idge. Gain is applied only t o the positive terminal.

8. The MICx_BIAS compensation capacitor must be 1 uF or greater . The capacitor’s gr ound terminal shoul d be connected to the same ground poi nt as the MICx_REF ground connection.

9. Analog signal i nputs (MICx & MICx_REF or LINEINx & LINEIN_REF) should be left f loating if unused.

10. An optional passi ve Low Pass Filter (LPF) may be used to reduce quant ization noise.

11. If tantal um capacitor use is desi red, 2 tantalum capacitors of value 2x C

INM

, configured i n series with both anodes or both cathodes connected , must be used to avoid potential ly damaging reverse voltages across the tantalum capacit ors.

12. If unused, t ie MIC2_SDET to VP.

13. Optional bias besi stors are used to minimize disturbances on the l ine inputs if their a/ c coupling capacitors are

left fl oating and then reconnected to signal (e.g. when the Line Input signal comes from a connector that is not always present). If the Line Input signal is always present, the Bias Resi stors are not required.

Key for Capacitor Types Required:

* Use low ESR, X7R/X5R capacitor s ** Use low ESR, X7 R/X5R capacitor s, or,

if improved micr ophonic performance is required, use t antalum capacitor s with equal or exceeding charact eristics

*** Use NPO/C0G capacitors *!* Use low ESR, X7R/X5R capacitor s, or,

if derati ng factors reduce the effecti ve capacitance si gnificantly, use tantal um capacitors wi th equal or exceeding characteristics If no type symbol i s shown next to a capacitor, any type may be used.

Note, one should be mindful of ceramic capacitor de- rating factors (e.g. percentage the effecti ve value reduced when d/c or small a/c voltages are appli ed) when selecting capacitor ty pe, brand, and size.

Figure 1. Typical Connection Diagram

Other Notes:

All external passive component values shown are nominal values.

P_I

and RP values are defined in section

“Digital Interface Specifications and Characteristics” on page 35.

For the spec. values listed in section “Charac-

teristic and Specifications” on page 19, a val-

ue of 1 F is used for C

INA

and a value of 0.1

F is used for C

INM

As required, add protection circuitry to ensure compliance with the Absolute Maximum Rat-

ings found on page 20.

CS42L73

DS882F1 17

CS42L73

2.1 Low-Profile Charge-Pump Capacitors

The “Typical Connection Diagram” on page 17 shows that the recommended capacitor values for the charge pump circuitry are all 2.2 itors may use the following parts with a nominal height of only 0.5 mm:

F and the types are all X7R/X5R. Applications that require low-profile versions of these capac-

Description: 2.2 Manufacturer, Part Number:

• KEMET, C0402C225M9PAC

F ±20%, 6.3 V, X5R, 0402, Height = 0.5 mm

2.2 Ceramic Capacitor Derating

The Typical Connection Diagram Capacitor Key highlights that ceramic capacitor derating factors can significantly affect the in-circuit capacitance value and thus the performance of the CS42L73.

As is noted on the Typical Connection Diagram, the 4.7 low-frequency PSRR performance. Numerous types and brands of ceramic capacitors, under typical conditions, exhibit effective capacitances well below their tolerance of ±20%, with some being derated by as much as -50%. These same capacitors, when tested by a multimeter, read much closer to their rated value. A similar derating effect has not been observed with tantalum capacitors.

The amount of derating observed varied with manufacturer and physical size; larger capacitors performed better as did ones from Kemet Electronics Corp. and TDK Corp. of any size. This derating effect is described in datasheets and applications notes from capacitor manufacturers. For instance, as DC and AC voltages are varied from the standard test points (applied DC and AC voltages for standard test points vs. PSRR test are 0 V and 1 V vs. 0.9 V and ~1 mV

Based on these tests, the following ANA_VQ/SPKR_VQ capacitor parts are recommended for applications that require ceramic capacitors with the smallest PCB footprint:

Description: 4.7 Manufacturer, Part Number:

• KEMET, C0603C475M9PAC

• TDK, C1608X5R0J475M

@ 20 Hz to 20 kHz), it is documented that the capacitance varies significantly.

RMS

F ±20%, 6.3V, X5R, 0603

F ceramic capacitors used for ANA_VQ or SPKR_VQ affect

@ 1 kHz

RMS

18 DS882F1

CS42L73

3. CHARACTERISTIC AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

Test Conditions: GND = AGND = PGND = CPGND = DGND = 0 V; all voltages are with respect to ground (GND).

Equivalent Tolerance

Parameters (Note 1) (Note 2) Symbol Min Nom Max Units

DC Power Supplies

Analog

Speakerphone Amplifiers, Mic Bias Generators (Note 3)

Mic Bias with High Voltage Selected and VP_MIN = 1b

Otherwise

Charge Pump (Headphone and Lineout Amplifiers)

Digital Core, Serial/Control/Digital-Mic Interfaces

Temperature

Ambient Temperature (local to device) Commercial: CWZR

VA 1.66 1.80 1.94 V ±7.8%

3.20

3.00--

VCP 1.66 1.80 1.94 V ±7.8%

VL 1.66 1.80 1.94 V ±7.8%

-40 - +85 C-

5.25

V-

Notes:

1. Device functional operation is guaranteed within these limits. Functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability.

2. “Parameter Definitions” on page 134 describes some parameters in detail.

3. The recommended operation range of the VP supply depends on how the CS42L73 is configured. If either mic bias is enabled (PDN_MIC1_BIAS = 0b or PDN_MIC2_BIAS = 0b) and the mic bias generators are set for their higher voltage (MIC_BIAS_CTRL = 1b), either VP must be held above 3.2 V or VP_MIN must be set to 0b. With this configuration and a VP level between 3.00 and 3.20 V, VP_MIN must be set to 0b to ensure the bias generators bypass one of their two LDO stages, ensuring there is enough headroom to avoid dropout. Refer to “Mic BIAS Characteristics” on page 26 for details on how much setting VP_MIN to 0b reduces PSRR performance.

from Nominal

DS882F1 19

ABSOLUTE MAXIMUM RATINGS

Test Conditions: GND = AGND = PGND = CPGND = DGND = 0 V; all voltages are with respect to ground (GND).

Parameters (Note 2) Symbol Min Max Units

DC Power Supply

Analog, Charge Pump, Digital Core (LDO fed),

Serial/Control/Digital-Mic Interfaces

Speakerphone Amplifiers, Mic Bias Generators

Input Current (Note 5)

Voltages Applied to I/Os

External Voltage Applied LINEINx, MICx, x_REF

to Analog Input (Note 6) MIC2_SDET

External Voltage HPOUT, LINEOUT Applied to Analog EAROUT Output (Note 7) SPKOUT, SPKLINEO, MICx_BIAS

External Voltage Applied to Digital Input (Note 6)

External Voltage Applied to Digital Output (Note 7)

Temperature

Ambient Operating Temperature Commercial: CWZR (local to device, power applied)

Storage Temperature (no power applied)

VA, VCP, VL

VP (Note 4)

IN-AI

IN-AI-SD

FLT-HP_LINE

FLT-EAR

FLT-SPK_MB

IN-DI

FLT-DO

stg

-0.3

-±10mA

AGND – 0.3

PGND – 0.3

-VCP_FILT – 0.3 AGND – 0.3 PGND – 0.3

2.22

5.6

VA + 0. 3

VP + 0.3

+VCP_FILT + 0.3

VA + 0. 3 VP + 0.3

-0.3 VL + 0.3 V

-50 +110 °C

-65 +150 °C

CS42L73

V V

V V V

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

Notes:

4. VP must be applied before VA is applied. VP must be removed after VA is removed.

5. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up.

6. The maximum over/under voltage is limited by the input current.

7. • V

• ±VCPFILT are specified in “DC Electrical Characteristics” on page 21.

• The specification applies to both the signal and pseudodifferential reference pins, where applicable.

is the applied voltage that causes a contention fault condition between its source and the CS42L73 output.

FLT-x

20 DS882F1

CS42L73

DC ELECTRICAL CHARACTERISTICS

Test Conditions: Connections to the CS42L73 are shown in the “Typical Connection Diagram” on page 17; GND = AGND =

PGND = CPGND = DGND = 0 V; all voltages are with respect to ground (GND); VA = VCP = 1.80 V, VP = 3.70 V; T

Parameters (Note 2) Min Typ Max Units

ANA_VQ Characteristics

Nominal Voltage

SPK_VQ Characteristics

Nominal Voltage

VCPFILT Characteristics (Note 8)

VCP Mode +VCPFILT

-VCPFILT

VCP/2 Mode +VCPFILT

-VCPFILT

VCP/3 Mode +VCPFILT

-VCPFILT

FILT+ Characteristics

Nominal Voltage

VD_FILT Characteristics

Nominal Voltage

MICB_FILT Characteristics

Nominal Voltage MIC_BIAS_CTRL = 0b

MIC_BIAS_CTRL = 1b

Analog Output Current Limiter Characteristics

Current Limiter On Threshold (Note 9)

-VA/2-V

- VP/2 - V

-VA-V

-0.9-V

100 120 150 mA

VCP

-VCP

VCP/2

-VCP/2

VCP/3

-VCP/3

2.00

2.75

= +25 C.

V V

Notes:

8. No load (from specification tables “Serial Port to Stereo HP Output Characteristics” on page 27 and “Serial Port to Ste-

reo Line Output Characteristics” on page 29, RL =  and CL = 0 pF) connected to Headphone and Line Outputs

(HPOUTx and LINEOUTx). Headphone Zobel Network remains connected.

9. See “Analog Output Current Limiter” on page 51.

DS882F1 21

CS42L73

ANALOG INPUT TO SERIAL PORT CHARACTERISTICS

Test Conditions (unless otherwise specified): Connections to the CS42L73 are shown in the “Typical Connection Diagram” on

page 17; Input is a 1-kHz sine wave through the passive input filter shown in Figure 1; GND = AGND = PGND = CPGND =

DGND = 0 V; all voltages are with respect to ground (GND); VA = 1.80 V; TA = +25 C; Measurement Bandwidth is 20 Hz to 20 kHz; Fs = 48 kHz (Note 10); ASP is used and is in slave mode with Fs 0 dB; Mixer Attenuation and Digital Volume = 0 dB, Digital Mute is disabled.

Parameters (Note 2) (Note 11) Min Typ Max Units

LINEINA/LINEINB to PGA to ADC

Dynamic Range PGA Setting: 0 dB A-weighted

PGA Setting: +12 dB A-weighted

Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS

PGA Setting: +12 dB -1 dBFS Common Mode Rejection (Note 12)

MIC1/MIC2 to PREAMP to PGA to ADC, MIC_PREAMPx = +10 dB Gain

Dynamic Range (Note 13) PGA Setting: 0 dB A-weighted

PGA Setting: +12 dB A-weighted

Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS PGA Setting: +12 dB -1 dBFS Common Mode Rejection (Note 12)

MIC1/MIC2 to PREAMP to PGA to ADC, MIC_PREAMPx = +20 dB Gain

Dynamic Range (Note 13) PGA Setting: 0 dB A-weighted

PGA Setting: +12 dB A-weighted

Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS PGA Setting: +12 dB -1 dBFS Common Mode Rejection (Note 12)

DC Accuracy

Interchannel Gain Mismatch Gain Drift Offset Error

= 48 kHz; MIC_PREAMPx = +10 dB, PGAxVOL =

ext

unweighted

-60 dBFS

unweighted

85 82

78 75

--81-75dB

-40-dB

--77- dB

--64- dB

-40-dB

--71- dB

--63- dB

-40-dB

-0.2-dB

- ±100 - ppm/°C

- 352 - LSB

91 88

84 81

-85

-28

88 86

78 75

82 79

70 67

-79

-22

dB dB

22 DS882F1

CS42L73

ANALOG INPUT TO SERIAL PORT CHARACTERISTICS (CONTINUED)

Test Conditions (unless otherwise specified): Connections to the CS42L73 are shown in the “Typical Connection Diagram” on

page 17; Input is a 1-kHz sine wave through the passive input filter shown in Figure 1; GND = AGND = PGND = CPGND =

Parameters (Note 2) (Note 11) Min Typ Max Units

Input

Interchannel Isolation (1 kHz) LINEINA to LINEINB, PGAxVOL = +12 dB

MIC1 to MIC2, MIC_PREAMPx = +20 dB, PGAxVOL = +12 dB HP Amp to Analog Input Isolation RL = 3 k

(Note 14) R

Full-scale Signal Input Voltage PGAxVOL = 0 dB LINEINA/LINEINB (Note 15) PGAxVOL = +12 dB

Full-scale Signal Input Voltage MIC_PREAMPx = +10 dB, PGAxVOL = +0 dB MIC1/MIC2 MIC_PREAMPx = +20 dB, PGAxVOL = +0 dB

(Note 15) MIC_PREAMPx = +10 dB, PGAxVOL = +12 dB

MIC_PREAMPx = +20 dB, PGAxVOL = +12 dB LINEIN_REF/MICx_REF Input Voltage (Note 16) Input Impedance (Note 17), LINEINA/LINEINB 1 kHz Input Impedance (Note 17), MIC1/MIC2 1 kHz DC Voltage at Analog Input (Pin Floating) LINEINA/LINEINAB PSRR

- 100 mV

- LINEINA and LINEINB connected to LINEIN_REF 1 kHz

- PGAxVOL = 0 dB 20 kHz MIC1/MIC2 PSRR

- 100 mV

- MICx connected to MICx_REF 1 kHz

- MIC_PREAMPx = +20 dB, PGAxVOL = +12 dB 20 kHz

signal AC-coupled to VA supply (Note 18) 217 Hz

= 48 kHz; MIC_PREAMPx = +10 dB, PGAxVOL =

ext

= 16 

84 77

0.78•VA-0.82•VA

90 80

90 83

0.198•VA

0.258•VA

0.081•VA

0.064•VA

0.020•VA

0.86•VA-V

V V

V V V

- - 0.300 V

-50-k

-1.0-M

- 0.50•VA - V

50 65 40

50 65 35

dB dB

dB dB dB

Notes:

10. Fs is the sampling frequency used by the core and the A/D and D/A converters. For specifications, a default value of 48 kHz is used. Refer to section “Applications” on page 41 for a description of how Fs relates to the CS42L73‘s clock inputs.

11. Measures are referred to the applicable typical full-scale voltages. Applies to all THD+N and dynamic range values in the table.

12. Refer to Figure 3 below.

13. Includes noise from MICx_BIAS output through series 2.21 kseries resistor to MICx. Refer to Figure 2 below. Input signal is -60 dB down from corresponding full-scale voltage.

14. Measurement taken with the following analog gain settings:

• LINEINA/LINEINB: PGAxVOL = +12 dB

• MIC1/MIC2: MIC_PREAMPx= + 20 dB, PGAxVOL = +12 dB

• HPxAVOL = +2 dB for R

= 3 k, -4 dB for RL = 16 

15. The full-scale input voltages given refer to the maximum voltage difference between the LINEINx/MICx and LINEIN_ REF/MICx_REF pins. Providing an input signal at these pins that exceeds the full-scale input voltage will result in the clipping of the analog signal.

16. The PGA output clips if the voltage difference between the LINEINx/MICx and LINEIN_REF/MICx_REF signals exceeds the full-scale voltage specification. If the LINEIN_REF/MICx_REF signal level exceeds the specified maximum value, PGA linearity may be degraded and analog input performance may be adversely affected. Refer to Figure 4 below.

17. Measured between LINEINx/MICy and AGND. Input impedance can vary from nominal value by ±20%.

18. The PGA is biased with ANA_VQ, created by a resistor divider from the VA supply. Increasing the capacitance on ANA_ VQ will increase the PSRR at low frequencies.

DS882F1 23

STEREO-ADC AND DUAL-DIGITAL-MIC DIGITAL FILTER

-60 dBFS, 1 kHz

0.1 µF

MICx

MICx_REF

100 

MICx_BIAS

2.21 k

0.1 µF

100 

2.21 k

1.0 µF

Figure 2. MICx Dynamic Range Test Configuration

100 mVPP,

25 Hz

100 

1 F

LINEINx or MICy

LINEINx_REF or MICy_REF

Figure 3. Analog Input CMRR Test Setup

0.1 µF

LINEINx or MICx

LINEIN_REF or MICx_REF

100 

300 mV

PP,

1 kHz

0.1 µF

100 

Figure 4. LINEIN_REF/MICx_REF Input Voltage Test Setup

CHARACTERISTICS

Test Conditions (unless otherwise specified): Fs = 48 kHz (Note 10), f

DMIC_SCLK

= 3.072 MHz (Note 19).

CS42L73

Parameters (Note 2) Min Typ Max Units

Low-Pass Filter Characteristics (Note 20)

Frequency Response (20 Hz to 20 kHz)

Passband to -0.05 dB corner

to -3.0 dB corner

Stopband (Note 21)

Stopband Attenuation

Total Input Path Digital Filter Group Delay

-0.07 - +0.02 dB

0.41

0.49

0.60 - - Fs

33 - - dB

- 4.3/Fs - s

High-Pass Filter Characteristics (Note 20) (Note 22)

Passband to -3.0 dB corner

to -0.05 dB corner

Passband Ripple

Phase Deviation @ 20 Hz

Filter Settling Time (input signal goes to 95% of its final value)

4.10x10

3.57x10

-5

-4

- - 0.01 dB

-5.30-Deg

- 12.2x10

/Fs - s

Notes:

19. Refer to section “Digital Microphone (DMIC) Interface” on page 60 for a description of how the digital mic shift clock frequency (f

DMIC_SCLK

20. Responses are clock-dependent and will scale with Fs. Note that the response plots (Figures 48 to 52 on pages 127 and

128) have been normalized to Fs and can be denormalized by multiplying the X-axis scale by Fs.

21. Measurement Bandwidth is from Stopband to 3 Fs.

22. High-pass filter is applied after low-pass filter.

) relates to the CS42L73‘s internal master clock rate.

Fs Fs

24 DS882F1

CS42L73

THERMAL OVERLOAD DETECT CHARACTERISTICS

Test Conditions: Connections to the CS42L73 are shown in the “Typical Connection Diagram” on page 17; GND = AGND = PGND = CPGND = DGND = 0 V; all voltages are with respect to ground (GND); VA = 1.80 V.

Parameters Min Typ Max Units

Thermal Overload Detect Threshold Characteristics

Threshold Junction Temperature (T

) (Note 23) THMOVLD_THLD[1:0] = 00b

THMOVLD_THLD[1:0] = 01b THMOVLD_THLD[1:0] = 10b THMOVLD_THLD[1:0] = 11b

150 132 115

°C °C °C °C

Notes:

23. The thermal overload detect threshold temperature level can vary from the nominal value by ±10 °C.

ASRC DIGITAL FILTER CHARACTERISTICS

Test Conditions (unless otherwise specified): Fs = 48 kHz (Note 10); Fs

Parameters (Note 2) (Note 25) Min Typ Max Units

Low-Pass Filter Characteristics (Note 24)

Frequency Response (0 Hz to 20 kHz)

Passband to -0.05 dB corner

to -3.0 dB corner

Stopband

Stopband Attenuation

Total ASRC Group Delay

= 48 kHz (Note 24).

ext

-0.07 - +0.04 dB

0.55 - - Fs

125 - - dB

- (Note 26) -s

0.48

0.50

ext

Notes:

24. Fs

25. Refer to Response plots in Figures 53 and 54 on page 129.

26. The equations for the group delay through the sample rate converters are:

is the sample rate of the serial port (XSP, ASP, or VSP) interface.

ext

• Input (from the serial ports to the core): 6.9/Fs

• Output (from the core to the serial ports): 2.6/Fs A plot of ASRC group delay values for the extreme supported internal sample rates (Fs) and standard audio sample rates is found in section “Group Delay” on page 130.

+ 3.0/Fs

ext

+ 14.1/Fs.

ext

DS882F1 25

CS42L73

MIC BIAS CHARACTERISTICS

Test Conditions (unless otherwise specified): Connections to the CS42L73 are shown in the “Typical Connection Diagram” on

page 17; GND = AGND = PGND = CPGND = DGND = 0 V; all voltages are with respect to ground (GND); VA = 1.80 V, VP =

3.70 V; TA = +25 C; I

MIC1_BIAS and MIC2_BIAS Characteristics

Output Voltage (Note 27) MIC_BIAS_CTRL = 0b

DC Output Current (I

(Note 28) Total for both outputs

Output Resistance (R

Dropout Voltage (Note 29)

= 500 A; only one bias output is powered up at a time; VP_MIN = 1b, MIC_BIAS_CTRL = 1b.

OUT

Parameters (Note 2) Min Typ Max Units

MIC_BIAS_CTRL = 1b

) Per output

OUT

)

OUT

1.85

2.59

-35-

- - 340 mV

2.00

2.75

2.15

2.89

3.0

5.0

V V

mA mA

PSRR with 100 mV

PSRR with 100 mV VP_MIN = 0b, VP = 3.10 V (Note 3) 217 Hz

PSRR with 1 V VP_MIN = 1b, VP = 3.70 V 217 Hz

signal AC-coupled to VA supply

signal AC-coupled to VP supply

217 Hz

1 kHz

20 kHz

1 kHz

20 kHz

1 kHz

20 kHz

105 100

90 90 70

110 105

Notes:

27. The output voltage includes attenuation due to the Mic Bias Output Resistance (R

28. Specifies use limits for the normal operation and MIC2 short conditions.

29. Dropout Voltage indicates the point where an output’s voltage starts to vary significantly with reductions to its supply voltage. When the VP supply voltage drops below the programmed MIC2_BIAS output voltage plus the Dropout Voltage, the MIC2_BIAS output voltage will progressively decrease as its supply decreases. Dropout Voltage is measured by reducing the VP supply until MIC2_BIAS drops 10 mV from its initial voltage with the default typical test condition VP voltage (= 3.80 V from table heading above). The difference between the VP supply voltage and the MIC2_BIAS voltage at this point is the dropout voltage. For instance, if the initial MIC2_BIAS output is 2.86 V when VP = 3.80 V and VP =

3.19 V when MIC2_BIAS drops to 2.85 V (-10mV), the Dropout Voltage is 340 mV (3.19 V – 2.85 V).

OUT

dB dB dB

26 DS882F1

CS42L73

SERIAL PORT TO STEREO HP OUTPUT CHARACTERISTICS

Test conditions (unless otherwise specified): “Typical Connection Diagram” on page 17 shows CS42L73 connections (including Zobel Networks on outputs); Input test signal is a 24-bit full-scale 997-Hz sine wave with 1 LSB of triangular PDF dither applied; GND = AGND = PGND = CPGND = DGND = 0 V; all voltages are with respect to ground (GND); VA = VCP = 1.80 V; T

C; VCP Mode; Measurement Bandwidth is 20 Hz to 20 kHz; Fs = 48 kHz (Note 10); ASP is used and is in slave mode with Fs = 48 kHz; test loading is configured as per Figure 5 on page 28 (R

and CL(= C

) as indicated in the table below); Mixer

L(Max)

Attenuation and Digital Volume = 0 dB, Digital and Analog Mutes are disabled.

Parameters (Note 2) Min Typ Max Units

Load RL = 16  (Analog Gain = -4 dB) (Note 30)

Dynamic Range

18 to 24-Bit A-weighted

unweighted

16-Bit A-weighted

unweighted

Total Harmonic Distortion + Noise (Note 31) (Note 32) 0 dBFS Full-scale Output Voltage (Note 32)

Output Power (Full-scale, Per Channel) (P

) (Note 32)

OUT

2 Channels Driven, THD+N  -60 dB (0.1%) Analog Vol. = -4 dB, Dig. Vol. = 0 dB 2 Channels Driven, THD+N  -40 dB (1%) Analog Vol. = -3 dB, Dig. Vol. = 0 dB 2 Channels Driven, THD+N  -20 dB (10%) Analog Vol. = -1 dB, Dig. Vol. = 0 dB 1 Channel Driven, THD+N  -60 dB (0.1%) Analog Vol. = -2 dB, Dig. Vol. = 0 dB 1 Channel Driven, THD+N  -40 dB (1%) Analog Vol. = -1 dB, Dig. Vol. = 0 dB 1 Channel Driven, THD+N  -20 dB (10%) Analog Vol. = +1 dB, Dig. Vol. = 0 dB

Load R

= 32  (Analog Gain = -4 dB) (Note 30)

Dynamic Range 18 to 24-Bit A-weighted

unweighted

16-Bit A-weighted

unweighted Total Harmonic Distortion + Noise (Note 31) (Note 32) 0 dBFS Full-scale Output Voltage (Note 32) Output Power (Full-scale, Per Channel) (P

) (Note 32)

OUT

2 Channels Driven, THD+N  -75 dB (0.018%) Analog Vol. = -4 dB, Dig. Vol. = 0 dB 2 Channels Driven, THD+N  -60 dB (0.1%) Analog Vol. = -1 dB, Dig. Vol. = 0 dB 2 Channels Driven, THD+N  -40 dB (1%) Analog Vol. = 0 dB, Dig. Vol. = -0.5 dB 2 Channels Driven, THD+N  -20 dB (10%) Analog Vol. = +2 dB, Dig. Vol. = -0.5 dB 1 Channel Driven, THD+N  -75 dB (0.018%) Analog Vol. = 0 dB, Dig. Vol. = 0 dB 1 Channel Driven, THD+N  -60 dB (0.1%) Analog Vol. = +1 dB, Dig. Vol. = -0.5 dB 1 Channel Driven, THD+N  -40 dB (1%) Analog Vol. = +1 dB, Dig. Vol. = 0 dB 1 Channel Driven, THD+N  -20 dB (10%) Analog Vol. = +3 dB, Dig. Vol. = -0.5 dB

Load R

= 3 k (Analog Gain = +2 dB) (Note 30)

Dynamic Range 18 to 24-Bit A-weighted

unweighted

16-Bit A-weighted

unweighted Total Harmonic Distortion + Noise (Note 31) (Note 32)

18 to 24-Bit 0 dBFS

-20 dBFS

-60 dBFS

16-Bit 0 dBFS

-20 dBFS

-60 dBFS

87 84 85 82

--70-60dB

0.73•VA 0.79•VA 0.85•VA V

88 85

86 83

93 90 91 88

16 20 27 25 32 44

94 91

92 89

--81-75dB

0.74•VA 0.80•VA 0.86•VA V

90 87

88 85

8.1 16 17 25 20 23 25 35

96 93

94 91

-85

-73

-33

-83

-71

-31

-79

-27

-77

-25

= +25

dB dB dB dB

mW mW mW mW mW mW

dB dB

mW mW mW mW mW mW mW mW

dB dB

dB dB dB

ext

DS882F1 27

CS42L73

Zobel

Network

Test Load

HPOUTx

CPGND/AGND

33 nF

100 

HPOUT_REF

Measurement

Device

Figure 5. Headphone Output Test Configuration

SERIAL PORT TO STEREO HP OUTPUT CHARACTERISTICS (CONTINUED)

C; VCP Mode; Measurement Bandwidth is 20 Hz to 20 kHz; Fs = 48 kHz (Note 10); ASP is used and is in slave mode with Fs = 48 kHz; test loading is configured as per Figure 5 on page 28 (R

and CL(= C

) as indicated in the table below); Mixer

L(Max)

Attenuation and Digital Volume = 0 dB, Digital and Analog Mutes are disabled.

Parameters (Note 2) Min Typ Max Units

Full-scale Output Voltage (Note 32)

Other Characteristics for RL = 16



, 32



or 3 k(Note 33)

Interchannel Isolation (Note 34) Interchannel Gain Mismatch (Note 34) Output Offset Voltage (DAC to HPOUTx) Analog mute enabled

0 dB analog gain Gain Drift Load Resistance (R

Load Capacitance (C

PSRR with 100 mV

) (Note 35)

signal AC-coupled to VA supply 217 Hz

- Analog Gain = 0 dB; Input test signal held low (all zeros data) 1 kHz

(Note 8) (Note 36) 20 kHz

PSRR with 100 mV

signal AC-coupled to VCP supply 217 Hz

- Analog Gain = 0 dB; Input test signal held low (all zeros data) 1 kHz

(Note 8) (Note 36) 20 kHz

Output Impedance High-Impedance Mode (Note 37)

1.56•VA 1.64•VA 1.73•VA V

-90-dB

- ±0.1 ±0.25 dB

±0.1 ±0.3

±1.0 ±2.0

- ±100 - ppm/°C

16 - - 

- - 150 pF

75 75 70

85 85 70

3.0 3.14 - k

= +25

mV mV

dB dB dB

ext

Notes:

30. Analog Gain setting (refer to “Headphone x Analog Volume Control” on page 103 or “Line Output x Analog Volume Con-

trol” on page 104) must be configured as indicated to achieve specified output characteristics.

31. If the VCP supply level is less than the VA supply level, clipping may occur as the audio signal is handed from the VA to the VCP powered circuits in the output amplifier. This clipping would occur as the audio signal approaches full-scale, maximum power output and could prevent achievement of THD+N performance.

32. Full-scale output voltage and power are determined by analog gain settings. Full-scale output voltage values here refer to the maximum voltage difference achievable on the analog output pins, measured between the HPOUTx/LINEOUTx and HPOUT_REF/LINEO_REF pins. Modifying internal gain settings to increase peak-to-peak voltage may cause analog output signal clipping, degrading THD+N performance.

33. Unless otherwise specified, measurement is taken for each load resistance test case with the gain set as indicated for the dynamic range, etc., performance specifications at the given load resistances.

34. Measured between stereo pairs (HPOUTA to HPOUTB or LINEOUTA to LINEOUTB).

35. Figure 5 on page 28 and Figure 6 on page 29 shows headphone and line output test configurations.

36. Valid with the recommended capacitor values on FILT+ and ANA_VQ. Increasing capacitance on FILT+ and ANA_VQ increases the PSRR at low frequencies.

37. High-impedance state enabled as described in Section 4.18.

28 DS882F1

CS42L73

Test Load

LINEOUTx

CPGND/AGND

LINEO_REF

Measurement

Device

Figure 6. Line Output Test Configuration

SERIAL PORT TO STEREO LINE OUTPUT CHARACTERISTICS

Test conditions (unless otherwise specified): Connections to the CS42L73 are shown in the “Typical Connection Diagram” on

page 17; Input test signal is a 24-bit full-scale 997 Hz sine wave with 1 LSB of triangular PDF dither applied; GND = AGND =

PGND = CPGND = DGND = 0 V; all voltages are with respect to ground (GND); VA = VCP = 1.80 V; T Measurement Bandwidth is 20 Hz to 20 kHz; Fs = 48 kHz (Note 10); ASP is used and is in slave mode with Fs loading is configured as per Figure 6 on page 29 (R

and CL as indicated in the table below for R

L(Min)

uation and Digital Volume = 0 dB, Analog Gain = +2 dB; Digital and Analog Mutes are disabled.

Parameters (Note 2) Min Typ Max Units

(Analog Gain = +2 dB) (Note 30)

Dynamic Range

18 to 24-Bit A-weighted unweighted

16-Bit A-weighted

unweighted

Total Harmonic Distortion + Noise (Note 31) (Note 32)

18 to 24-Bit 0 dBFS

-20 dBFS

-60 dBFS

16-Bit 0 dBFS

-20 dBFS

-60 dBFS

Full-scale Output Voltage (Note 32) (Note 38)

Other Characteristics

Interchannel Isolation (Note 34)

Interchannel Gain Mismatch (Note 34)

Output Offset Voltage (DAC to LINEOUTx) Analog mute enabled

0 dB analog gain

Gain Drift

Output Resistance (R

Load Resistance (R

Load Capacitances (C

PSRR with 100 mV

)

OUT

) (Note 35)

signal AC-coupled to VA supply 217 Hz

- Analog Gain = 0 dB; Input test signal held low (all zeros data) 1 kHz

(Note 8) (Note 36) 20 kHz

PSRR with 100 mV

signal AC-coupled to VCP supply 217 Hz

- Analog Gain = 0 dB; Input test signal held low (all zeros data) 1 kHz

(Note 8) (Note 36) 20 kHz

91 88

88 85

1.50•VA 1.58•VA 1.66•VA V

-90-dB

- ±0.1 ±0.25 dB

-±100-ppm/°C

-100- 

3--k

--150pF

= +25 C; VCP Mode;

and C

97 94

94 91

-86

-74

-34

-84

-71

-31

±0.1 ±0.3

70 70 70

85 85 65

= 48 kHz; test

ext

L(Max)

-80

-28

-78

-25

±0.5 ±1.0

); Mixer Atten-

dB dB

dB dB dB

mV mV

dB dB dB

Notes:

38. The full-scale output voltage includes attenuation due to the Stereo Line Output Resistance (R

DS882F1 29

OUT

CS42L73

Test Load

EAROUT+

AGND

EAROUT-

Measurement

Device

Figure 7. Ear Speaker Output Test Configuration

SERIAL PORT TO MONO EAR SPEAKER OUTPUT CHARACTERISTICS

Test conditions (unless otherwise specified): Connections to the CS42L73 are shown in the “Typical Connection Diagram” on

page 17; Input test signal is a 24-bit full-scale 997 Hz sine wave with 1 LSB of triangular PDF dither applied; GND = AGND =

PGND = CPGND = DGND = 0 V; all voltages are with respect to ground (GND); VA = 1.80 V; TA = +25 C; Measurement Bandwidth is 20 Hz to 20 kHz; Fs = 48 kHz (Note 10); ASP is used and is in slave mode with Fs as per Figure 7 on page 30 (R

, CL1, and CL2 as indicated in the table below for R

L(Min)

tion = 0 dB, Digital Volume = -2.5 dB, Digital Mute is disabled.

Parameters (Note 2) Min Typ Max Units

Dynamic Range 16 to 24-Bit A-weighted

unweighted

Total Harmonic Distortion + Noise (Note 39), 16 to 24-Bit

0 dBFS, P

Full-scale Output Voltage (Note 39) (Diff. EAROUT ±, see Note 40) Output Power (Full-scale) (P

) (Note 39)

OUT

THD+N -65 dB (0.056%) Dig. Vol. = -2.5 dB THD+N -60 dB (0.1%) Dig. Vol. = -2.0 dB THD+N -40 dB (1%) Dig. Vol. = -1.5 dB THD+N -20 dB (10%) Dig. Vol. = -0.5 dB

Other Characteristics

Output Offset Voltage (DC offset of diff. EAROUT ±, see Note 40) Gain Drift Load Resistance (R Load Capacitances C

(Note 41) C

PSRR with 100 mV

) (Note 41)

from each output to ground

signal AC-coupled to VA supply 217 Hz

- Input test signal held low (all zeros data) 1 kHz

(Note 36) 20 kHz

= 45 mW

OUT

across outputs

= 48 kHz; test loading is configured

ext

, C

82 79

L1(Max)

, and C

88 85

); Mixer Attenua-

L2(Max)

dB dB

--70-65dB

1.24•VA 1.34•VA 1.44•VA V

45 51 56 66

mW mW mW mW

-±2.5±4.0mV

- ±100 - ppm/°C

16 - - 

70 70 70

150

pF pF

dB dB dB

Notes:

39. Modifying internal gain settings to achieve a higher peak-to-peak voltage may result in clipping the analog output signal, degrading the THD+N performance.

40. Differential peak-to-peak voltage is measured from the extremes (peaks) of the waveform that represents the difference between the positive and negative signals of the differential pair [i.e. the voltage between the maximum and minimum

(= V+ – V-)].

of V

41. Refer to Figure 7 on page 30 and Figure 8 on page 32 to observe Ear-Speaker, Speakerphone, and Speakerphone

30 DS882F1

Diff

Line-Output test configurations.

+ 109 hidden pages

Cirrus Logic CS42L73 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

TABLE OF CONTENTS

LIST OF FIGURES

LIST OF TABLES

1. PACKAGE PIN/BALL ASSIGNMENTS AND CONFIGURATIONS

1.1 64-Ball Wafer-Level Chip Scale Package (WLCSP)

1.2 65-Ball Fine-Pitch Ball Grid Array (FBGA) Package

1.3 Pin/Ball Descriptions

1.4 Digital Pin/Ball I/O Configurations

2. TYPICAL CONNECTION DIAGRAM

2.1 Low-Profile Charge-Pump Capacitors

2.2 Ceramic Capacitor Derating

3. CHARACTERISTIC AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

ANALOG INPUT TO SERIAL PORT CHARACTERISTICS

THERMAL OVERLOAD DETECT CHARACTERISTICS

ASRC DIGITAL FILTER CHARACTERISTICS

MIC BIAS CHARACTERISTICS

SERIAL PORT TO STEREO HP OUTPUT CHARACTERISTICS

SERIAL PORT TO STEREO LINE OUTPUT CHARACTERISTICS

SERIAL PORT TO MONO EAR SPEAKER OUTPUT CHARACTERISTICS