Cirrus Logic CS42L56 User Manual

HPF

+1.62 V to +3.63 V

Interface Supply

Control Port

Serial Audio Port

Level Shifter

Multi-bit

 ADC

Beep

Multi-bit

 ADC

ALC

Multi-bit

 DAC

Mono mix, Limiter, Bass, Treble Adjust

Attenuator, Boost, Mix

Left Line Output

Right Line Output

Pseudo Diff. Input

I²S or Left Justified Serial Audio Input/

Output

I²C or SPI

Control

Digital Supply (VLDO)

+1.62 V to +2.75 V

Analog Supply (VA)

+1.62 V to +2.75 V

LDO Regulator

InvertingStep-Down

+VHP

-VHP

Charge Pump Supply (VCP)

+1.62 V to +2.75 V

Ground-Centered Amplifiers

Left Headphone Output

Right Headphone Output

Programmable Mic Bias

Mic Bias Output

Left Input 1

Pseudo Diff. Input /

Left Input 3

Right Input 1

Left Input 2

Pseudo Diff. Input /

Right Input 3

Right Input 2

0, +10, or +20 dB

-6 to +12 dB

0.5 dB Steps

Pseudo Diff. Input

CS42L56

Ultralow Power, Stereo Codec with Class H Headphone Amp

DIGITAL to ANALOG FEATURES

 5 mW Stereo Playback Power Consumption  99 dB Dynamic Range (A-wtd)  -86 dB THD+N  Digital Signal Processing Engine

– Bass & Treble Tone Control, De-emphasis – Master Volume Control (+12 to -102 dB in

0.5 dB steps) – Soft-ramp & Zero-cross Transitions – Programmable Peak-detect and Limiter – Beep Generator with Full Tone Control

Stereo Headphone and Line Amplifiers

 Step-down/Inverting Charge Pump  Class H Amplifier - Automatic Supply Adj.

– High Efficiency – Low EMI

 Pseudo-differential Ground-centered Outputs  High HP Power Output at -75 dB THD+N

– 2 x 20 mW Into 16  @ 1.8 V

 1V  Analog Vol. Ctl. (+12 to -60 dB in 1 dB steps)  Analog In to Analog Out Passthrough  Pop and Click Suppression

Line Output @ 1.8 V

RMS

ANALOG to DIGITAL FEATURES

 3.5 mW Stereo Record Power Consumption  95 dB Dynamic Range (A-wtd)  -87 dB THD+N  Configurable Analog Inputs

– Two Pseudo-differential Stereo Inputs or – One Pseudo-differential Stereo Inputs +

One Standard Stereo Input + One Standard

Mono Input or – Three Standard Stereo Inputs – Pseudo-differential Inputs Reduce

Common Mode Signal Noise – 3:1 Stereo Input MUX for ADC or

Passthrough

 Analog Programmable Gain Amplifier (PGA)

– +12 to -6 dB in 0.5 dB steps – +10 dB or +20 dB Additional Gain for

Microphone Inputs

 Programmable, Low-noise MIC Bias Output  Programmable Automatic Level Control (ALC)

– Noise Gate for Noise Suppression – Programmable Threshold &

Attack/Release Rates

 Independent ADC Channel Control  High-pass Filter Disable for DC Measurements

http://www.cirrus.com

FEB '14

DS851F2

CS42L56

SYSTEM FEATURES

 Audio (11.2896 MHz or 12.288 MHz) or USB

(12 MHz) Master Clock Input

 Low-power Operation

– Stereo Anlg. Passthrough: 3.3 mW @1.8 V – Stereo Rec. and Playback: 8.3 mW @1.8 V

 Headphone Detect Input  High Performance 24-bit Converters

– Multi-bit Delta–Sigma Architecture

 Integrated High Efficient Power Management

Reduces Power Consumption

– Step-down Charge Pump Improves

Efficiency

– Inverting Charge Pump Accommodates

Low System Voltage by Providing Negative Rail for HP/Line Amp

– LDO Reg. Provides Low Digital Supply

Voltage

 Digital Power Reduction

– Very Low ADC/DAC Oversampling Rate – Bursted Serial Clock Providing up to 24 Bits

per Sample

 Power Down Management

– ADC, DAC, CODEC, PGA, DSP

 Analog & Digital Routing/Mixes

– Line/Headphone Out = Analog In (ADC

Bypassed) – Line/Headphone Out = ADC Out – Internal Digital Loopback – Mono Mixes

 I²C or SPI™ Control Port  I²S or Left-justified Digital Interface Format

 Flexible Clocking Options

– Master or Slave Operation – Wide Range of Sample Rates Supported

APPLICATIONS

 HDD and Flash-based Portable Audio Players  PDAs  Personal Media Players  Portable Game Consoles  Digital Voice Recorders  MD Players/Recorders  Digital Camcorders  Digital Cameras

GENERAL DESCRIPTION

The CS42L56 is a highly integrated, 24-bit, ultra-lowpower stereo CODEC based on multi-bit delta-sigma modulation. Both the ADC and DAC offer many features suitable for low power portable system applications.

The analog input path allows independent channel control of a variety of features. The Programmable Gain Amplifier (PGA) provides analog gain with zero cross transitions. The ADC path includes a digital volume attenuator with soft ramp transitions and a programmable ALC and noise gate monitor the input signals and adjust the volume appropriately. An analog passthrough also exists, accommodating a lower noise, lower power analog in to analog out path to the headphone and line amplifiers, bypassing the ADC and DAC.

The DAC output path includes a fixed-function digital signal processing engine. Tone control provides bass and treble adjustment at four selectable corner frequencies. The digital mixer provides independent volume control for both the ADC output and PCM input signal paths, as well as a master volume control. Digital volume controls may be configured to change on soft ramp transitions while the analog controls can be configured to occur on every zero crossing. The DAC path also includes de-emphasis, limiting functions and a beep generator delivering tones selectable across a range of two full octaves.

The Class H stereo headphone amplifier combines the efficiency of an integrated step-down and inverting charge pump with the linearity and low EMI of a Class AB amplifier. A step-down/inverting charge pump operates in two modes: ±VCP mode or ±VCP/2) mode. Based on the amplifier’s output signal, internal logic automatically adjusts the output of the charge pump, +VHPFILT and –VHPFILT, to optimize efficiency. With these features, the amplifier delivers a ground-centered output with a large signal swing even at low voltages and eliminates the need for external DC-blocking capacitors.

These features make the CS42L56 the ideal solution for portable applications which require extremely low power consumption in a minimal amount of space.

The CS42L56 is available in a 40-pin QFN package for the Commercial (-40 to +85° C) grade. The CDB42L56 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please see “Ordering Information” on page 93 for complete details.

 Smart Phones

2 DS851F2

TABLE OF CONTENTS

1. PIN DESCRIPTIONS .............................................................................................................................. 8

1.1 I/O Pin Characteristics .................................................................................................................... 10

2. TYPICAL CONNECTION DIAGRAMS .................................................................................................11

3. CHARACTERISTIC AND SPECIFICATION TABLES ......................................................................... 14

RECOMMENDED OPERATING CONDITIONS ................................................................................... 14

ABSOLUTE MAXIMUM RATINGS .......................................................................................................14

ANALOG INPUT CHARACTERISTICS ................................................................................................ 14

ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 17

HP OUTPUT CHARACTERISTICS ......................................................................................................18

LINE OUTPUT CHARACTERISTICS ................................................................................................... 19

ANALOG PASSTHROUGH CHARACTERISTICS ............................................................................... 21

COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ...............................21

SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 22

SWITCHING SPECIFICATIONS - I²C CONTROL PORT ..................................................................... 23

SWITCHING CHARACTERISTICS - SPI CONTROL PORT ................................................................ 24

ANALOG OUTPUT ATTENUATION CHARACTERISTICS .................................................................. 25

DC CHARACTERISTICS ...................................................................................................................... 26

DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 27

POWER CONSUMPTION - ALL SUPPLIES = 1.8 V ............................................................................ 28

POWER CONSUMPTION - ALL SUPPLIES = 2.5 V ........................................................................... 29

4. APPLICATIONS ................................................................................................................................... 30

4.1 Overview ......................................................................................................................................... 30

4.1.1 Basic Architecture ................................................................................................................. 30

4.1.2 Line Inputs ............................................................................................................................. 30

4.1.3 Line and Headphone Outputs (Class H, Ground-Centered Amplifiers) ................................. 30

4.1.4 Fixed-function DSP Engine ................................................................................................... 30

4.1.5 Beep Generator ..................................................................................................................... 30

4.1.6 Power Management .............................................................................................................. 30

4.2 Analog Inputs .................................................................................................................................. 31

4.2.1 Pseudo-differential Inputs ...................................................................................................... 32

4.2.2 Large-scale Inputs ................................................................................................................. 32

4.2.3 Microphone Inputs ................................................................................................................. 34

4.2.3.1 External Passive Components ................................................................................... 34

4.2.4 Optional VCM Buffer ............................................................................................................. 34

4.2.5 Automatic Level Control (ALC) .............................................................................................. 34

4.2.5.1 Attack/Release Time Calculations: ............................................................................ 36

4.3 Analog In to Analog Out Passthrough ............................................................................................ 36

4.4 Analog Outputs .............................................................................................................................. 37

4.5 Class H Amplifier ............................................................................................................................ 38

4.5.1 Power Control Options .......................................................................................................... 39

4.5.1.1 Standard Class AB Mode (setting 01 and 10) ........................................................... 39

4.5.1.2 Adapt to Volume Mode (setting 00) ........................................................................... 39

4.5.1.3 Adapt to Output Mode (setting 11) ............................................................................. 42

4.5.2 Power Supply Transitions ...................................................................................................... 42

4.5.3 Efficiency ............................................................................................................................... 43

4.6 Beep Generator .............................................................................................................................. 44

4.7 Limiter ....................................................................................................................

4.8 Serial Port Clocking ........................................................................................................................ 46

4.9 Digital Interface Format .................................................................................................................. 49

4.10 Initialization ................................................................................................................................... 49

4.11 Recommended DAC to HP or Line Power Sequence .................................................................. 49

4.11.1 Power-Up Sequence ........................................................................................................... 49

CS42L56

...................... 45

...

DS851F2 3

CS42L56

4.11.2 Power-Down Sequence ....................................................................................................... 50

4.12 Recommended PGA to HP or Line Power Sequence (Analog Passthrough) .............................. 51

4.12.1 Power-Up Sequence ........................................................................................................... 51

4.12.2 Power-Down Sequence ....................................................................................................... 52

4.13 Control Port Operation .................................................................................................................. 53

4.13.1 SPI Control .......................................................................................................................... 53

4.13.2 I²C Control ........................................................................................................................... 53

4.13.3 Memory Address Pointer (MAP) .......................................................................................... 54

4.13.3.1 Map Increment (INCR) ............................................................................................. 54

5. REGISTER QUICK REFERENCE ........................................................................................................ 55

6. REGISTER DESCRIPTION .................................................................................................................. 57

6.1 Device I.D. Register (Address 01h) (Read Only) ............................................................................ 57

6.1.1 Device I.D. (Read Only) ........................................................................................................ 57

6.2 Device Revision Register (Address 02h) (Read Only) ................................................................... 57

6.2.1 Alpha Revision (Read Only) .................................................................................................. 57

6.2.2 Numeric Revision (Read Only) .............................................................................................. 57

6.3 Power Control 1 (Address 03h) ...................................................................................................... 57

6.3.1 Power Down VCM Bias Buffer .............................................................................................. 57

6.3.2 Power Down MIC Bias .......................................................................................................... 58

6.3.3 Power Down ADC Charge Pump .......................................................................................... 58

6.3.4 Power Down ADC x ............................................................................................................... 58

6.3.5 Power Down .......................................................................................................................... 58

6.4 Power Control 2 (Address 04h) ...................................................................................................... 58

6.4.1 Headphone Power Control .................................................................................................... 58

6.4.2 Line Power Control ................................................................................................................ 59

6.5 Clocking Control 1 (Address 05h) ................................................................................................... 59

6.5.1 Master/Slave Mode ............................................................................................................... 59

6.5.2 SCLK Polarity ........................................................................................................................ 59

6.5.3 SCLK Equals MCLK .............................................................................................................. 59

6.5.4 MCLK Pre-Divide ................................................................................................................... 59

6.5.5 MCLK Divide ......................................................................................................................... 60

6.5.6 MCLK Disable ....................................................................................................................... 60

6.6 Clocking Control 2 (Address 06h) ................................................................................................... 60

6.6.1 Clock Ratio Auto-Detect ........................................................................................................ 60

6.6.2 Clock Ratio ............................................................................................................................ 61

6.7 Serial Format (Address 07h) .......................................................................................................... 61

6.7.1 CODEC Digital Interface Format ...........................................................................................61

6.8 Class H Control (Address 08h) ....................................................................................................... 62

6.8.1 Adaptive Power Adjustment .................................................................................................. 62

6.8.2 Charge Pump Frequency ...................................................................................................... 62

6.9 Misc. Control (Address 09h) ........................................................................................................... 62

6.9.1 Digital MUX ........................................................................................................................... 62

6.9.2 Analog Soft Ramp ................................................................................................................. 63

6.9.3 Analog Zero Cross ................................................................................................................ 63

6.9.4 Digital Soft Ramp .................................................................................................................. 63

6.9.5 Freeze Registers ................................................................................................................... 63

6.10 Status (Address 0Ah) (Read Only) ............................................................................................... 64

................................................................................ 64

6.10.1 HPDETECT Pin Status (Read Only)

6.10.2 Serial Port Clock Error (Read Only) .................................................................................... 64

6.10.3 DSP Engine Overflow (Read Only) ..................................................................................... 64

6.10.4 MIXx Overflow (Read Only) ................................................................................................. 64

6.10.5 ADCx Overflow (Read Only) ...............................................................................................64

6.11 Playback Control (Address 0Bh) .................................................................................................. 65

6.11.1 Power Down DSP ................................................................................................................ 65

...

4 DS851F2

CS42L56

6.11.2 HP/Line De-Emphasis ......................................................................................................... 65

6.11.3 Playback Channels B=A ...................................................................................................... 65

6.11.4 Invert PCM Signal Polarity .................................................................................................. 65

6.12 DSP Mute Controls (Address 0Ch) ............................................................................................... 66

6.12.1 ADC Mixer Channel x Mute ................................................................................................. 66

6.12.2 PCM Mixer Channel x Mute ................................................................................................66

6.12.3 Master Playback Mute ......................................................................................................... 66

6.13 ADCx Mixer Volume: ADCA (Address 0Dh) & ADCB (Address 0Eh) ........................................... 66

6.13.1 ADC Mixer Channel x Volume ............................................................................................. 66

6.14 PCMx Mixer Volume: PCMA (Address 0Fh) & PCMB (Address 10h) .......................................... 67

6.14.1 PCM Mixer Channel x Volume ............................................................................................ 67

6.15 Analog Input Advisory Volume (Address 11h) .............................................................................. 68

6.15.1 Analog Input Advisory Volume ............................................................................................68

6.16 Digital Input Advisory Volume (Address 12h) ...............................................................................68

6.16.1 Digital Input Advisory Volume ............................................................................................. 68

6.17 Master Volume Control:

MSTA (Address 13h) & MSTB (Address 14h) ...................................................................................... 69

6.17.1 Master Volume Control ........................................................................................................ 69

6.18 Beep Frequency & On Time (Address 15h) ................................................................................. 69

6.18.1 Beep Frequency .................................................................................................................. 69

6.18.2 Beep On Time ..................................................................................................................... 70

6.19 Beep Volume & Off Time (Address 16h) ......................................................................................70

6.19.1 Beep Off Time ..................................................................................................................... 70

6.19.2 Beep Volume ....................................................................................................................... 71

6.20 Beep & Tone Configuration (Address 17h) ...................................................................................71

6.20.1 Beep Configuration .............................................................................................................. 71

6.20.2 Treble Corner Frequency .................................................................................................... 71

6.20.3 Bass Corner Frequency ...................................................................................................... 72

6.20.4 Tone Control Enable ........................................................................................................... 72

6.21 Tone Control (Address 18h) ......................................................................................................... 72

6.21.1 Treble Gain .......................................................................................................................... 72

6.21.2 Bass Gain ............................................................................................................................ 72

6.22 ADC & PCM Channel Mixer (Address 19h) .................................................................................. 73

6.22.1 PCM Mix Channel Swap ..................................................................................................... 73

6.22.2 ADC Mix Channel Swap ...................................................................................................... 73

6.23 AIN Reference Configuration, ADC MUX (Address 1Ah) ............................................................. 73

6.23.1 Analog Input 2 x Reference Configuration .......................................................................... 73

6.23.2 Analog Input 1 x Reference Configuration .......................................................................... 73

6.23.3 ADC x Input Select .............................................................................................................. 74

6.24 HPF Control (Address 1Bh) .......................................................................................................... 74

6.24.1 ADCx High-Pass Filter ........................................................................................................ 74

6.24.2 ADCx High-Pass Filter Freeze ............................................................................................74

6.24.3 HPF x Corner Frequency .................................................................................................... 74

6.25 Misc. ADC Control (Address 1Ch) ................................................................................................ 75

6.25.1 ADC Channel B=A .............................................................................................................. 75

6.25.2 PGA Channel B=A .............................................................................................................. 75

6.25.3 Digital Sum .......................................................................................................................... 75

6.25.4 Invert ADC Signal Polarity ................................................................................................... 75

6.25.5 ADC Mute ............................................................................................................................ 75

6.26 Gain & Bias Control (Address 1Dh) ........................................................................................

PGA

6.26.1

6.26.2 Boostx ................................................................................................................................. 76

6.26.3 Microphone Bias Output Level ............................................................................................76

6.27 PGA x MUX, Volume: PGA A (Address 1Eh) & PGA B (Address 1Fh) ........................................ 76

x Preamplifier Gain ..................................................................................................... 76

...... 76

DS851F2 5

CS42L56

6.27.1 PGA x Input Select .............................................................................................................. 76

6.27.2 PGAx Volume ...................................................................................................................... 77

6.28 ADCx Attenuator Control: ADCAATT (Address 20h) & ADCBATT (Address 21h) ....................... 77

6.28.1 ADCx Volume ...................................................................................................................... 77

6.29 ALC Enable & Attack Rate (Address 22h) ....................................................................................78

6.29.1 ALCx .................................................................................................................................... 78

6.29.2 ALC Attack Rate .................................................................................................................. 78

6.30 ALC Release Rate (Address 23h) ................................................................................................ 78

6.30.1 ALC Limit All Channels ........................................................................................................ 78

6.30.2 ALC Release Rate ............................................................................................................... 79

6.31 ALC Threshold (Address 24h) ...................................................................................................... 79

6.31.1 ALC Maximum Threshold .................................................................................................... 79

6.31.2 ALC Minimum Threshold ..................................................................................................... 80

6.32 Noise Gate Control (Address 25h) ............................................................................................... 80

6.32.1 Noise Gate All Channels ..................................................................................................... 80

6.32.2 Noise Gate Enable .............................................................................................................. 80

6.32.3 Noise Gate Threshold and Boost ........................................................................................ 81

6.32.4 Noise Gate Delay Timing .................................................................................................... 81

6.33 ALC and Limiter Soft Ramp, Zero Cross Disables (Address 26h) ................................................ 81

6.33.1 ALCx Soft Ramp Disable ..................................................................................................... 81

6.33.2 ALCx Zero Cross Disable .................................................................................................... 81

6.33.3 Limiter Soft Ramp Disable ................................................................................................... 81

6.34 Automute, Line & HP MUX (Address 27h) ................................................................................... 82

6.34.1 Auto Mute ............................................................................................................................ 82

6.34.2 Line Input Select .................................................................................................................. 82

6.34.3 Headphone Input Select ...................................................................................................... 82

6.35 Headphone Volume Control: HPA (Address 28h) & HPB (Address 29h) ..................................... 82

6.35.1 Headphone Channel x Mute ................................................................................................82

6.35.2 Headphone Volume Control ................................................................................................83

6.36 Line Volume Control: LINEA (Address 2Ah) & LINEB (Address 2Bh) .......................................... 83

6.36.1 Line Channel x Mute ........................................................................................................... 83

6.36.2 Line Volume Control ............................................................................................................ 83

6.37 Limiter Min/Max Thresholds (Address 2Ch) ................................................................................. 84

6.37.1 Limiter Maximum Threshold ................................................................................................ 84

6.37.2 Limiter Cushion Threshold .................................................................................................. 84

6.38 Limiter Control, Release Rate (Address 2Dh) .............................................................................. 85

6.38.1 Peak Detect and Limiter ...................................................................................................... 85

6.38.2 Peak Signal Limit All Channels ........................................................................................... 85

6.38.3 Limiter Release Rate ...................................................................................................

39 Limit

7. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 87

7.1 Power Supply ................................................................................................................................. 87

7.2 Grounding ....................................................................................................................................... 87

7.3 QFN Thermal Pad .......................................................................................................................... 87

8. ANALOG VOLUME NON-LINEARITY (DNL & INL) ............................................................................ 88

9. ADC & DAC DIGITAL FILTERS .......................................................................................................... 89

10. PARAMETER DEFINITIONS .............................................................................................................. 90

11. PACKAGE DIMENSIONS .................................................................................................................. 91

THERMAL CHARACTERISTICS .......................................................................................................... 91

12. ORDERING INFORMATION .............................................................................................................. 92

13. REFERENCES .................................................................................................................................... 92

14. REVISION HISTORY .......................................................................................................................... 92

er Attack Rate (Address 2Eh) ............................................................................................... 86

6.39.1 Limiter Attack Rate .............................................................................................................. 86

........ 85

6 DS851F2

LIST OF FIGURES

Figure 1.Typical Connection Diagram - Four Pseudo-Differential Analog Inputs ...................................... 11

Figure 2.Typical Connection Diagram - Two Pseudo-Differential / Three Single-Ended Analog Inputs ... 12

Figure 3.Typical Connection Diagram - Six Single-Ended Analog Inputs ................................................. 13

Figure 4.CMRR Test Configuration ........................................................................................................... 16

Figure 5.AINxREF Input Voltage Test Configuration ................................................................................ 16

Figure 6.HP Output Test Configuration ..................................................................................................... 20

Figure 7.Line Output Test Configuration ................................................................................................... 20

Figure 8.Serial Port Timing (Slave Mode) ................................................................................................. 22

Figure 9.Serial Port Timing (Master Mode) ............................................................................................... 22

Figure 10.I²C Control Port Timing ............................................................................................................. 23

Figure 11.Control Port Timing - SPI Format .............................................................................................. 24

Figure 12.Power Consumption Test Configuration ................................................................................... 27

Figure 13.Analog Input Signal Flow .......................................................................................................... 31

Figure 14.Stereo Pseudo-Differential Input ............................................................................................... 32

Figure 15.Analog Input Attenuation ........................................................................................................... 33

Figure 16.Example Analog Input Attenuation ............................................................................................ 33

Figure 17.MIC Input Mix w/Common Mode Rejection ............................................................................... 34

Figure 18.ALC Operation .......................................................................................................................... 35

Figure 19.DSP Engine Signal Flow ........................................................................................................... 37

Figure 20.Analog Output Stage ................................................................................................................. 38

Figure 21.Class H Volume-Adapt Paths ................................................................................................... 39

Figure 22.Volume Sum Effects ................................................................................................................. 40

Figure 23.Channel/Amp Effect .................................................................................................................. 40

Figure 24.HP/Line Channel Effects ........................................................................................................... 41

Figure 25.VHPFILT Transitions ................................................................................................................. 42

Figure 26.VHPFILT Hysteresis ................................................................................................................. 43

Figure 27.Class H Power to Load vs. Power from VCP Supply - 32 W .................................................... 43

Figure 28.Class H Power to Load vs. Power from VCP Supply - 16 W .................................................... 44

Figure 29.Beep Configuration Options ...................................................................................................... 45

Figure 30.Peak Detect & Limiter ............................................................................................................... 46

Figure 31.Serial Port Timing in Master Mode ............................................................................................ 48

Figure 32.I²S Format ................................................................................................................................. 49

Figure 33.Left-Justified Format ................................................................................................................. 49

Figure 34.Control Port Timing in SPI Mode .............................................................................................. 53

Figure 35.Control Port Timing, I²C Write ................................................................................................... 54

Figure 36.Control Port Timing, I²C Read ................................................................................................... 54

Figure 37.PGA Step Size vs. Volume Setting ........................................................................................... 88

Figure 38.PGA Output Volume vs. Volume Setting .................................................................................. 88

Figure 39.HP/Line Step Size vs. Volume Setting ...................................................................................... 88

Figure 40.HP/Line Output Volume vs. Volume Setting .............................................................................88

Figure 41.ADC Frequency Response ....................................................................................................... 89

Figure 42.ADC Stopband Rejection .......................................................................................................... 89

Figure 43.ADC Transition Band ................................................................................................................ 89

Figure 44.ADC Transition Band Detail ...................................................................................................... 89

Figure 45.DAC Frequency Response ....................................................................................................... 89

Figure 46.DAC Stopband .......................................................................................................................... 89

Figure 47.DAC Transition Band ....................................................................................................

Figure 48.DAC Transition Band (Detail) .................................................................................................... 89

CS42L56

......... 89

...

DS851F2 7

1. PIN DESCRIPTIONS

GND/Thermal Pad

VDFILT

SDOUT

MCLK

SDIN

SCLK

-VHPFILT

HPREF

HPOUTB

TSTN

LINEOUTB

AGND

AFILTB

SDA/CDIN

SCL/CCLK

AD0/CS

+VHPFILT

RESET

FLYC

FLYN

FILT+

AIN2A

MICBIAS

AIN1REF/AIN3A

AFILTA

AIN1A

AIN1B

FLYP

LRCK

VLDO

VCP

HPOUTA

TSTN

LINEOUTA

LINEREF

AIN2B

HPDETECT

AIN2REF/AIN3B

Top-Down (Through-Package) View

40-Pin QFN Package

CS42L56

Pin Name # Pin Description

SDIN 1 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

LRCK 2

SDA/CDIN

SCL/CCLK

AD0/CS

VCP 6 Step-Down Charge Pump Power (Input) - Power supply for the step-down charge pump.

FLYP 7

+VHPFILT 8

FLYC 9

FLYN 10

8 DS851F2

Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data lines. Serial Control Data (Input/Output) - SDA is the bidirectional data pin for the I²C control interface.

CDIN is the input data pin for the SPI control interface.

Serial Control Port Clock (Input) - Serial clock for the I²C and SPI control interfaces.

Chip Address (I²C) / Chip Select (SPI) (Input) - For I²C operation, this pin must remain static high

or low. For SPI, CS

Charge Pump Cap Positive Node (Output) - Positive node for the step-down charge pump’s flying capacitor.

Step-Down Charge Pump Filter Connection (Output) - Power supply from the step-down charge pump that provides the positive rail for the headphone and line amplifiers

Charge Pump Cap Common Node (Output) - Common positive node for the step-down and invert- ing charge pumps’ flying capacitors.

Charge Pump Cap Negative Node (Output) - Negative node for the inverting charge pump’s flying capacitor.

is the chip-select pin.

CS42L56

-VHPFILT 11

HPOUTA HPOUTB

HPREF 13

TSTN

LINEOUTA LINEOUTB

LINEREF 18 Pseudo Diff. Line Output Reference (Input) - Ground reference for the line amplifiers.

VA 20 Analog Power (Input) - Power supply for the internal analog section.

AGND 21 Analog Ground (Input) - Ground reference for the internal analog section.

FILT+ 22 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

VQ 23 Quiescent Voltage (Output) - Filter connection for the internal quiescent voltage.

AFILTA AFILTB

MICBIAS

AIN1A AIN1B AIN2A AIN2B

AIN1REF/AIN3A AIN2REF/AIN3B2831

HPDETECT 33

RESET

VLDO 35 Low Dropout Regulator (LDO) Power (Input) - Power supply for the LDO regulator.

VDFILT 36

VL 37

SDOUT 38 Serial Audio Data Output (Output) - Output for two’s complement serial audio data.

MCLK 39 Master Clock (Input) - Clock source for the delta-sigma modulators.

SCLK 40 Serial Clock (Input/Output) - Serial clock for the serial audio interface.

GND/ Thermal Pad

Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge pump that provides the negative rail for the headphone and line amplifiers.

1214Headphone Audio Output (Output) - The full-scale output level is specified in “HP Output Charac-

teristics” on page 19.

Pseudo Diff. Headphone Output Reference (Input) - Ground reference for the headphone amplifi- ers

Test Input (Input) - This pin is an input used for test purposes only and should be tied to ground for

normal operation.

1719Line Audio Output (Output) - The full-scale output level is specified in “Line Output Characteristics”

on page 20.

Antialias Filter Connection (Output) - Antialias filter connection for the ADC inputs.

Microphone Bias (Output) - Low noise bias supply for an external microphone. Electrical character-

istics are specified in the DC Electrical Characteristics table.

27 29

page 14.

Pseudo Differential Analog Input Reference/Analog Input 3 (Input) - Configurable as the ground reference for the programmable gain amplifiers (PGA) or as additional analog inputs. The full-scale level is specified in “Analog Input Characteristics” on page 14.

Headphone Detect (Input) - The HPDETECT circuit can be set to control the power down of the left and/or right channel of the line and/or headphone outputs as described in “Headphone Power Con-

trol” on page 59 and “Line Power Control” on page 60 and/or cause an interrupt. This pin is

debounced such that the signal must remain stable in the new state for approximately 10 ms before a change is passed on to the internal HPDETECT circuit.

34 Reset (Input) - The device enters a low power mode when this pin is driven low.

Low Dropout Regulator (LDO) Filter Connection (Output) - Power supply from the LDO regulator that provides the low voltage power to the digital section.

Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and I²C control port.

- Ground reference for the internal charge pump and digital section; thermal relief pad.

Inputs 1 & 2 (Input) - The full-scale level is specified in “Analog Input Characteristics” on

alog

DS851F2 9

1.1 I/O Pin Characteristics

Input and output levels and associated power supply voltage are shown in the table below. Logic levels should not exceed the corresponding power supply voltage.

CS42L56

Power Supply

VA HPDETECT Input - - 1.8 V - 2.5 V, with Hysteresis

Pin Name I/O Internal

Connections

RESET

SCL Input - - 1.8 V - 3.3 V, with Hysteresis SDA Input/Output - CMOS/Open Drain 1.8 V - 3.3 V, with Hysteresis AD0 Input - - 1.8 V - 3.3 V, with Hysteresis

CCLK Input - - 1.8 V - 3.3 V, with Hysteresis

CDIN Input - - 1.8 V - 3.3 V, with Hysteresis

MCLK Input - - 1.8 V - 3.3 V

LRCK Input/Output

SCLK Input/Output

SDOUT Output

SDIN Input - - 1.8 V - 3.3 V

Input - - 1.8 V - 3.3 V, with Hysteresis

Weak Pull-up

(~1 M

Weak Pull-up

(~1 M

Weak Pull-up

(~1 M

Driver Receiver

1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V

1.8 V - 3.3 V, CMOS -

10 DS851F2

2. TYPICAL CONNECTION DIAGRAMS

Note 1

Note 2

2.2 µF

Note 1

Analog Input 1

Analog Input 2

1 µF

GND/Thermal Pad

0.1 µF

+1.65 V to +3.63 V

RESET

LRCK

MCLK

SCLK

2.2 µF

+VHPF ILT

VDFILT

LINEREF

SDIN

SDOUT

1 µF

AIN2REF

AIN1A

1800 pF

100 k

100 

AIN1B

Digital Audio

Processor

AIN2A

1800 pF

AIN2B

FLYC

FLYN

-VHPFI LT

2. 2 µF

1 µF

100 k

100 

100 k

2.2 µ F

VCP

AIN1REF

1 µF

LINEOUTA

LINEOUTB

0.1 µF

+1.65 V to +2.75 V

0.1 µF

VLDO

2.2 µF

AGND

NPO /C0G dielect ric c apacit ors.

1000 pF

AFILT A AFILT B

1000 pF

2.2 µF

HPOUTB

HPOUTA

Headphone Out Left & Right

33 

0.1 µ F

HPDETECT

33 

0.1 µ F

47 k

HPREF

FILT+

+1.65 V to +2.75 V

FLYP

2.2 µ F

Note 1

Notes:

1. T he headphone amplif ier’s out put pow er and dist ortion are rat ed using t he nominal c apacit ance s hown. Larger capacit ance

reduces the ripple on the int ernal amplif iers’ s upplies and in turn redu ces the am plifier’s dist ortion at high outpu t pow er levels. Smaller c apacit ance m ay not suff icie ntly re duce ripple t o achiev e the rat ed output power and dis tort ion. Since the act ual val ue of ty pica l X7R/X5R c eramic capac itors deviat es f rom the nom inal va lue by a perc entage sp ecif ied in the m anufac turer’s data sheet , capacit ors shoul d be select ed based on the minim um out put pow er and max imum dist ortion required.

2. T he headphone amplif ier’s out put pow er and dist ortion are rat ed using t he nominal c apacit ance s hown and us ing the def ault charge pum p swi tchi ng frequenc y. The required capacit ance f ollows an invers e relations hip wit h the c harge pump’s sw itc hing frequenc y. When increasing t he sw itc hing frequenc y, the capacit ance m ay dec rease; when lowering the swit ching f requency, the c apacit ance m ust increas e. Since t he act ual value of ty pical X7R/ X5R c eramic capac itors deviat es f rom t he nom inal value by a perc entage s pecif ied in t he manuf actu rer’s dat a sheet, capac itors should b e selec ted bas ed on the m inimum outp ut power , max imum dis tort ion and max imum charge pum p sw itc hing frequenc y required.

3. Addit ional bulk c apacit ance m ay be added t o improv e PSRR at low f requenc ies.

4. T hese c apacit ors s erve as a charge res ervoir f or the int ernal sw itc hed capac itor AD C m odulators and should be plac ed as

clos e as pos sible t o the input s. They are only needed wh en the PGA (Program mable Gain Am plifier ) is bypass ed.

Note 4

Note 3

Low ESR, X7R/X5R dielec tric capac itors.

** **

562 

3300 pF

ext

LPF i s Opti onal

Line Level Out Left & Right

3300 pF

SCL\CCLK

SDA\CD IN

AD0\CS

TSTN

Figure 1. Typical Connection Diagram - Four Pseudo-Differential Analog Inputs

CS42L56

Notes:

1. The headphone amplifier’s output power and distortion are rated using the nominal capacitance shown. Larger capacitance reduces the ripple on the internal

amplifiers’ supplies and in turn reduces the amplifier’s distortion at high output power levels. Smaller capacitance may not sufficiently reduce ripple to achieve the rated output power and distortion. Since the actual value of typical X7R/X5R ceramic capacitors deviates from the nominal value by a percentage specified in the manufacturer’s data sheet, capacitors should be selected based on the minimum output power and maximum distortion required.

2. The headphone amplifier’s output power and distortion are rated using the nominal capacitance shown and using the default charge pump switching frequency. The required capacitance follows an inverse relationship with the charge pump’s switching frequency. When increasing the switching frequency, the capacitance may decrease; when lowering the switching frequency, the capacitance must increase. Since the actual value of typical X7R/X5R ceramic capacitors deviates from the nominal value by a percentage specified in the manufacturer’s data sheet, capacitors should be selected based on the minimum output power, maximum distortion and maximum charge pump switching frequency required.

3. Additional bulk capacitance may be added to improve PSRR at low frequencies.

4. These capacitors serve as a charge reservoir for the internal switched capacitor ADC modulators and should be placed as close as possible to the inputs. They

are only needed when the PGA (Programmable Gain Amplifier) is bypassed.

CS42L56

DS851F2 11

CS42L56

2.2 µF

Note 1

Note 2

2.2 µF

Note 1

1 µF

GND/Thermal Pad

0.1 µF

+1.65 V to +3.63 V

RESET

LRCK

MCLK

SCLK

+VHPF ILT

VDFI LT

LINEREF

SDIN

SDOUT

Digital Audio

Processor

FLYC

FLYN

-VHP FILT

2.2 µ F

2.2 µF

VCP

LINEOUTA

LINEOUTB

0.1 µF

+1.65 V to +2.75 V

0.1 µF

VLDO

2.2 µF

AGND

NPO /C0G dielect ric capac itors.

1000 pF

AFILT A AFILT B

1000 pF

2.2 µF

HPOUTB

HPOUTA

Headphone Out Left & Right

33 

0.1 µF

HPDETECT

33 

0.1 µF

47 k

HPREF

FILT+

+1.65 V to +2.75 V

FLYP

2.2 µF

Note 1

Notes:

1. The headphone amplif ier’s out put power and dis tort ion are rated us ing the nominal c apacit ance show n. Larger capacitance

reduces t he ripple on the int ernal amplifiers ’ supplies and in turn reduc es the am plifier’s distort ion at high out put pow er levels. Smaller capac itanc e may not suf ficient ly reduc e ripple to ac hieve the rat ed output power and dist ortion. Since the act ual value of ty pical X7R/X5R ceram ic capac itors deviates from the nom inal value by a perc entage s pecified in t he manuf act urer’s data sheet, capacitors should be selec ted bas ed on the minim um out put pow er and maxim um dis tortion requ ired.

2. The headphone amplif ier’s out put power and dis tort ion are rated us ing the nominal c apacit ance show n and using t he default charge pump s wit ching frequenc y. The required capacit ance f ollows an inv erse relat ionship wit h the c harge pump’s swit ching frequency . When increas ing the sw itc hing frequency, the capacitanc e may decrease; when lowering the swit ching f requency, the capac itanc e must increas e. Since the actual v alue of t ypical X7R/X5R c eramic c apacit ors deviat es f rom the nom inal value by a percent age spec ified in the m anufac turer’s dat a sheet, capacitors should be s elected bas ed on the m inimum out put power, maxim um dis tortion and m axim um charge pum p sw itc hing frequency required.

3. Additional bulk c apacit ance may be added to im prove PSR R at low frequenc ies.

4. These c apacit ors serv e as a c harge reservoir f or the int ernal sw itched c apacit or ADC m odulators and should be plac ed as

close as poss ible to the input s. T hey are only needed when t he PGA (Programmable Gain Amplifier ) is bypassed.

5. The value of R

, a current-limit ing resis tor used w ith elec tret c ondenser m icrophones, is dictated by the mic rophone

cartridge.

6. The negativ e term inal of the m icrophone input s connec ts to t he ground pin of the m icrophone c artridge. Gain is applied only to the pos itiv e terminal.

Note 3

Low ESR, X7R/X5R dielec tric c apacit ors.

** **

562 

3300 pF

ext

LPF i s Optional

Line Level Out Left & Right

3300 pF

SCL\CCLK

SDA\CDIN

MICBIAS

1 µF

AIN1A

AIN1REF

1 µF

Note 5

Note 6

Microphone 1

Microphone 2

AIN1B

Note 5

Left Analog Input 2

AIN2A

1800 pF

100 k

100 

AIN2B

1 µF

100 k

100 

Note 4

Analog Input 3

AIN3B

1800 pF

100 k

100 

1 µF

Note 4

Right Analog Input 2

AD0\CS

TSTN

1 µF

Figure 2. Typical Connection Diagram - Two Pseudo-Differential / Three Single-Ended Analog Inputs

CS42L56

Note 1

Note 2

2.2 µF

Note 1

Analog Input 1

Analog Input 2

1 µF

GND/Thermal Pad

0.1 µF

+1.65 V to +3.63 V

RESET

LRCK

MCLK

SCLK

2.2 µF

+VHPF ILT

VDFILT

LINEREF

SDIN

SDOUT

1 µF

AIN2REF

AIN1A

1800 pF

100 k

100 

AIN1B

Digital Audio

Processor

AIN2A

1800 pF

AIN2B

FLYC

FLYN

-VHPFI LT

2. 2 µF

1 µF

100 k

100 

100 k

2.2 µ F

VCP

AIN1REF

1 µF

LINEOUTA

LINEOUTB

0.1 µF

+1.65 V to +2.75 V

0.1 µF

VLDO

2.2 µF

AGND

NPO /C0G dielect ric c apacit ors.

1000 pF

AFILT A AFILT B

1000 pF

2.2 µF

HPOUTB

HPOUTA

Headphone Out Left & Right

33 

0.1 µ F

HPDETECT

33 

0.1 µ F

47 k

HPREF

FILT+

+1.65 V to +2.75 V

FLYP

2.2 µ F

Note 1

Notes:

1. T he headphone amplif ier’s out put pow er and dist ortion are rat ed using t he nominal c apacit ance s hown. Larger capacit ance

3. Addit ional bulk c apacit ance m ay be added t o improv e PSRR at low f requenc ies.

4. T hese c apacit ors s erve as a charge res ervoir f or the int ernal sw itc hed capac itor AD C m odulators and should be plac ed as

clos e as pos sible t o the input s. They are only needed wh en the PGA (Program mable Gain Am plifier ) is bypass ed.

Note 4

Note 3

Low ESR, X7R/X5R dielec tric capac itors.

** **

562 

3300 pF

ext

LPF i s Opti onal

Line Level Out Left & Right

3300 pF

SCL\CCLK

SDA\CD IN

AD0\CS

TSTN

Notes:

1. The headphone amplifier’s output power and distortion are rated using the nominal capacitance shown. Larger capacitance reduces the ripple on the internal amplifiers’ supplies and in turn reduces the amplifier’s distortion at high output power levels. Smaller capacitance may not sufficiently reduce ripple to achieve the rated output power and distortion. Since the actual value of typical X7R/X5R ceramic capacitors deviates from the nominal value by a percentage specified in the manufacturer’s data sheet, capacitors should be selected based on the minimum output power and maximum distortion required.

2. The headphone amplifier’s output power and distortion are rated using the nominal capacitance shown and using the default charge pump switching frequency. The required capacitance follows an inverse relationship with the charge pump’s switching frequency. When increasing the switching frequency, the capacitance may decrease; when lowering the switching frequency, the capacitance must increase. Since the actual value of typical X7R/X5R ceramic capacitors deviates from the nominal value by a percentage specified in the manufacturer’s data sheet, capacitors should be selected based on the minimum output power, maximum distortion and maximum charge pump switching frequency required.

3. Additional bulk capacitance may be added to improve PSRR at low frequencies.

4. These capacitors serve as a charge reservoir for the internal switched capacitor ADC modulators and should be placed as close as possible to the inputs. They are only needed when the PGA (Programmable Gain Amplifier) is bypassed.

5. The value of R

, a current-limiting resistor used with electret condenser microphones, is dictated by the microphone cartridge.

6. The negative terminal of the microphone inputs connects to the ground pin of the microphone cartridge. Gain is applied only to the positive terminal.

12 DS851F2

CS42L56

Note 1

Note 2

2.2 µF

Note 1

1 µF

GND/Thermal Pad

0.1 µF

+1.65 V to +3.63 V

RESET

LRCK

MCLK

SCLK

2.2 µF

+VHPFI LT

VDFI LT

LINEREF

SDIN

SDOUT

AIN1A

1800 pF

100 k

100 

AIN1B

Digital Audio

Processor

FLYC

FLYN

-VHP FILT

2.2 µ F

1 µF

100 k

100 

2.2 µF

VCP

LINEOUTA

LINEOUTB

0.1 µF

+1.65 V to +2.75 V

0.1 µF

VLDO

2.2 µ F

AGND

NPO /C0G dielectric c apacitors.

1000 pF

AFILT A

AFILT B

1000 pF

2.2 µF

HPOUTB

HPOUTA

Headphone Out Left & R ight

33 

0.1 µF

HPDETECT

33 

0.1 µF

47 k

HPREF

FILT+

+1.65 V to +2.75 V

FLYP

2.2 µF

Note 1

Notes:

1. The headphone amplifier’s out put power and dist ortion are rated using the nom inal capacitanc e shown. Larger capacitance

reduces the ripple on the int ernal amplifiers’ s upplies and in turn reduces t he amplifier’s distort ion at high output pow er levels. Smaller capacit ance may not suff iciently reduce ripple to achiev e the rated output power and distort ion. Since the act ual value of ty pical X7 R/ X5R ceram ic capac itors deviat es from the nominal v alue by a percentage spec ified in the m anufact urer’s data sheet, capacitors should be selec ted based on the m inimum out put power and max imum dis tortion required.

2. The headphone amplifier’s out put power and dist ortion are rated using the nom inal capacitanc e shown and using t he default charge pump sw itching f requency. The required capacitance f ollows an inv erse relationship w ith the c harge pump’s sw itching frequency. When increasing the sw itching f requency, the capacitance m ay decreas e; w hen lowering the s witc hing frequency, the capacit ance mus t increas e. Since the act ual value of t ypical X7R/X5R ceramic capacitors deviates from t he nominal value by a percentage s pecified in the m anufact urer’s data sheet, capacitors s hould be selected bas ed on the minimum output power, maximum distort ion and maximum charge pump s witc hing frequency required.

3. Additional bulk capacit ance may be added to improve PSRR at low f requencies.

4. These capac itors s erve as a charge res ervoir for the int ernal swit ched capacit or ADC m odulators and should be plac ed as

clos e as pos sible t o the inpu ts. They are only needed when t he PGA (Programmable Gain Amplif ier ) is by passed.

5. The value of R

, a current-limiting resis tor used w ith elect ret condenser m icrophones, is dictated by the mic rophone

cartridge.

6. The negative t erminal of the m icrophone inputs c onnects to the ground pin of the m icrophone cart ridge. Gain is applied only to the positive terminal.

Note 4

Note 3

Low ESR, X7R/X5R dielectric capacit ors.

** **

562 

3300 pF

ext

LPF is Optional

Line Level Out Left & Right

3300 pF

SCL\CCLK

SDA\CDIN

AD0\CS

AIN2A

1800 pF

100 k

100 

AIN2B

1 µF

100 k

100 

Note 4

Microphone 1

MICBIAS

1 µF

AIN3A

AIN3B

Microphone 2

1 µF

Note 5

Note 6

Left Analog Input 1

Right Analog Input 1

Left Analog Input 2

Right Analog Input 2

TSTN

Figure 3. Typical Connection Diagram - Six Single-Ended Analog Inputs

CS42L56

Notes:

2. The headphone amplifier’s output power and distortion are rated using the nominal capacitance shown and using the default charge pump switching frequency. The required capacitance follows an inverse relationship with the charge pump’s switching frequency. When increasing the switching frequency, the capacitance may decrease; when lowering the switching frequency, the capacitance must increase. Since the actual value of typical X7R/X5R ceramic capacitors deviates from the nominal value by a percentage specified in the manufacturer’s data sheet, capacitors should be selected based on the minimum output power, maximum distortion and maximum charge pump switching frequency required.

3. Additional bulk capacitance may be added to improve PSRR at low frequencies.

5. The value of R

, a current-limiting resistor used with electret condenser microphones, is dictated by the microphone cartridge.

6. The negative terminal of the microphone inputs connects to the ground pin of the microphone cartridge. Gain is applied only to the positive terminal.

DS851F2 13

CS42L56

3. CHARACTERISTIC AND SPECIFICATION TABLES

RECOMMENDED OPERATING CONDITIONS

GND = AGND = 0 V; all voltages with respect to ground.

Parameters Symbol Min Max Units

DC Power Supply Analog (Note 1) VA 1.62 2.75 V Charge Pump (Note 1) VCP 1.62 VA V LDO Regulator for Digital VLDO 1.62 2.75 V Serial/Control Port Interface VL 1.62 3.63 V Ambient Temperature Commercial - CNZ T

-40 +85 C

ABSOLUTE MAXIMUM RATINGS

GND = AGND = 0 V; all voltages with respect to ground.

Parameters Symbol Min Max Units

DC Power Supply Analog, Charge Pump, LDO

Serial/Control Port Interface Input Current (Note 2) I External Voltage Applied to Analog Input (Note 3)

External Voltage Applied to Analog Output (Note 4)

External Voltage Applied to Digital Input (Note 3) V Ambient Operating Temperature (power applied) T Storage Temperature T

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

VA, VCP, VLDO

IND

stg

-0.3

-±10mA

AGND-0.3 VA+0.3

-VHPFILT - 0.3 +VHPFILT + 0.3

-0.3 VL+ 0.3 V

-50 +115 °C

-65 +150 °C

3.0

4.0

V V

Notes:

1. Due to the existence of parasitic body diodes between VCP and VA, current flows from VCP to VA whenever the VA power supply is lower than VCP. This causes a “back-powering” effect on the VA power supply rails internal to the part; therefore, VA should be maintained at an equal or greater voltage than VCP at all times. While “back-powering” does not have any adverse effects on device operation with respect to performance and reliability, it does lead to extra power consumption and therefore should be avoided.

2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up.

3. The maximum over/under voltage is limited by the input current.

4. VHPFILT is specified in “DC Characteristics” on page 27.

ANALOG INPUT CHARACTERISTICS

Test Conditions (unless otherwise specified): Connections to the CS42L56 are shown in the “Typical Connection Diagrams” on

page 11; Input test signal is a 1 kHz sine wave through the passive input filter, PGA = 0 dB; All Supplies = VA;

GND = AGND = 0 V; T nal path is AINxx to SDOUT.

Parameter

Analog In to ADC (PGA bypassed)

=+25C; Measurement bandwidth is 20 Hz to 20 kHz; Sample Frequency = 48 kHz. Measurement sig-

VA = 2.5 V VA = 1.8 V

Min Typ Max Min Typ Max Unit

14 DS851F2

CS42L56

ANALOG INPUT CHARACTERISTICS (CONTINUED)

Test Conditions (unless otherwise specified): Connections to the CS42L56 are shown in the “Typical Connection Diagrams” on

page 11; Input test signal is a 1 kHz sine wave through the passive input filter, PGA = 0 dB; All Supplies = VA;

GND = AGND = 0 V; T nal path is AINxx to SDOUT.

Dynamic Range A-weighted

Total Harmonic Distortion + Noise -1 dBFS

Analog In to PGA to ADC, PREAMPx[1:0]=00 (0 dB Gain + PGA Setting)

Dynamic Range PGA Setting: 0 dB A-weighted

PGA Setting: +12 dB A-weighted

Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS

PGA Setting: +12 dB -1 dBFS - -83 -77 - -81 -75 dB Common Mode Rejection (Note 5) -66- -66-dB

Analog In to PGA to ADC, PREAMPx[1:0]=01 (+10 dB Gain + PGA Setting)

Dynamic Range PGA Setting: 0 dB A-weighted

PGA Settin

Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS - -77 - - -77 - dB PGA Setting: +12 dB -1 dBFS - -64 - - -64 - dB Common Mode Rejection (Note 5) -66- -66-dB

Analog In to PGA to ADC, PREAMPx[1:0]=10 (+20 dB Gain + PGA Setting)

Dynamic Range PGA Setting: 0 dB A-weighted

PGA Setting: +12 dB A-weighted

Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS - -71 - - -71 - dB PGA Setting: +12 dB -1 dBFS - -63 - - -63 - dB Common Mode Rejection (Note 5) -58- -58-dB DC Accuracy Interchannel Gain Mismatch - 0.2 - - 0.2 - dB Gain Drift - ±100 - - ±100 - ppm/°C Offset Error (Note 6) -352- -352-LSB Input Interchannel Isolation (1 kHz) (Note 7) -90- -90-dB HP Amp to Analog Input Isolation R

Full-scale Input Voltage ADC

+12 dB A-weighted

=+25C; Measurement bandwidth is 20 Hz to 20 kHz; Sample Frequency = 48 kHz. Measurement sig-

unweighted8986

-20 dBFS

-60 dBFS

unweighted8885

unweighted8178

-60 dBFS

unweighted

= 3 k

= 16 

PGA (-1.5 dB)

PGA (0 dB)

PGA (+12 dB)

0.76•VA

0.78•VA

95 92

-85

-72

-32

94 91

87 84

-87

-31

91 88

81 78

85 82

73 70

90 83

0.80•VA

0.95•VA

0.82•VA

0.198•VA

-79

-26

-81

-25

0.84•VA

0.86•VA

86 83

85 82

78 75

0.76•VA

0.78•VA

92 89

-85

-69

-29

91 88

84 81

-85

-28

88 86

78 75

82 79

70 67

90 83

0.80•VA

0.95•VA

0.82•VA

0.198•VA

-79

-23

-79

-22

0.84•VA

0.86•VA

dB dB

dB dB dB

dB dB

Vpp Vpp Vpp

DS851F2 15

CS42L56

100 mVPP,

25 Hz

100 

1 F

AINxA

AINxREF

Figure 4. CMRR Test Configuration

1 µF

AINxx

AINxREF

1 µF

300 mV

PP,

1 kHz

100 

Figure 5. AINxREF Input Voltage Test Configuration

ANALOG INPUT CHARACTERISTICS (CONTINUED)

Test Conditions (unless otherwise specified): Connections to the CS42L56 are shown in the “Typical Connection Diagrams” on

page 11; Input test signal is a 1 kHz sine wave through the passive input filter, PGA = 0 dB; All Supplies = VA;

GND = AGND = 0 V; TA=+25C; Measurement bandwidth is 20 Hz to 20 kHz; Sample Frequency = 48 kHz. Measurement sig- nal path is AINxx to SDOUT.

Full-scale Signal Input Voltage (Note 8)

ADC

0.76•VA

PGA=-1.5 dB, PREAMPx[1:0]=00

PGA=0 dB, PREAMPx[1:0]=00

PGA=+12 dB, PREAMPx[1:0]=00

PGA=0 dB, PREAMPx[1:0]=01

PGA=0 dB, PREAMPx[1:0]=10 PGA=+12 dB, PREAMPx[1:0]=01 PGA=+12 dB, PREAMPx[1:0]=10

AINxREF Input Voltage (Pseudo-Diff Mode)(Note 10) - - 0.300 - - 0.300 Vpp Input Impedance (Note 9) ADC

PGA, PREAMPx[1:0]=00 PGA, PREAMPx[1:0]=01 PGA, PREAMPx[1:0]=10

DC Voltage at Analog Input (Pin Floating) - VA/2 - - VA/2 - V

0.78•VA

Notes:

5. See Figure 4.

6. SDOUT Code with HPFx=1 and HPFRZx=0.

7. See “Parameter Definitions” on page 91.

8. The full scale input voltage values given in the table refers to the maximum voltage difference between the AINxx and AINxREF pins. Providing an input signal at these pins that exceeds the full scale input voltage may result in clipping the analog input.

9. Measured between AINxx and AGND.

10. Providing a signal level higher than 300 mVpp on the AINxREF pin may degrade the PGA linearity and adversely affect analog input performance. See Figure 5.

0.80•VA

0.95•VA

0.82•VA

0.198•VA

0.259•VA

0.082•VA

0.064•VA

0.020•VA

60 40

12.65 4

0.84•VA

0.86•VA

0.76•VA

0.78•VA

0.80•VA

0.95•VA

0.82•VA

0.198•VA

0.259•VA

0.082•VA

0.064•VA

0.020•VA

60 40

12.65 4

0.84•VA

0.86•VA

Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp

k k k k

16 DS851F2

CS42L56

ADC DIGITAL FILTER CHARACTERISTICS

Parameter (Note 11) Min Typ Max Unit

Frequency Response (20 Hz to 20 kHz) -0.07 - +0.02 dB Passband to -0.05 dB corner

to -3 dB corner-Stopband 0.52 - - Fs Stopband Attenuation 33 - - dB Total Group Delay - 4.3/Fs - s

High-Pass Filter Characteristics (48 kHz Fs) (Note 12)

Passband to -3.0 dB corner

to -0.05 dB corner-Frequency Response - - 0.15 dB Phase Deviation @ 20 Hz - 5.3 - Deg

Filter Settling Time (Note 13)

Notes:

11. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 41 to Note 44

on page 90) have been normalized to Fs and can be denormalized by multiplying the X-axis scale by Fs.

HPF parameters are for Fs = 48 kHz.

12. Characteristics are based on the default setting in register “HPF Control (Address 1Bh)” on page 75.

13. Settling time decreases at higher corner frequency settings.

0.421

0.495

1.87

17.15

/Fs

-s

DS851F2 17

CS42L56

HP OUTPUT CHARACTERISTICS

Test conditions (unless otherwise specified): Connections to the CS42L56 are shown in the “Typical Connection Diagrams” on

page 11; Input test signal is a full-scale 997 Hz sine wave; All Supplies = VA, VCP Mode; GND = AGND = 0 V; TA = +25C;

Measurement bandwidth is 20 Hz to 20 kHz; Sample Frequency = 48 kHz; Test load R and test load R HPOUTx.

=16  CL = 150 pF for a headphone load (See Figure 6 on page 21); Measurement signal path is SDIN to

VA = 2.5 V VA = 1.8 V

Parameter (Note 15)

Line Load RL = 10 k(+2 dB Analog Gain) (Note 14)

Dynamic Range 18 to 24-Bit A-weighted

unweighted 16-Bit A-weighted

unweighted Total Harmonic Distortion + Noise (Note 16) 18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

Full-scale Output Voltage (Note 17)

HP Load RL = 16 (-4 dB Analog Gain) (Note 14)

Dynamic Range 18 to 24-Bit A-weighted

unweighted 16-Bit A-weighted

unweighted Total Harmonic Distortion + Noise (Note 16) Full-scale Output Voltage (Note 17) Output Power (Note 16)

Other Characteristics for RL = 16 or 10 k

Interchannel Isolation 10 k

(Note 17) 16 

Interchannel Gain Mismatch (Note 17) Output Offset Mute

(Note 17) 0 dB Analog Gain

Gain Drift (Note 17) Load Resistance (R

Load Capacitance (C

) (Note 17)



Min Typ Max Min Typ Max Unit

92 89

1.56•VA 1.64•VA 1.73•VA 1.56•VA 1.64•VA 1.73•VA V

89 86

- -75 -69 - -75 -69 dB

0.76•VA 0.82•VA 0.88•VA 0.76•VA 0.82•VA 0.88•VA V

-32- -17-mW

- 0.1 0.28 - 0.1 0.28 dB

- ±100 - - ±100 - ppm/°C

16 - - 16 - - 

- - 150 - - 150 pF

98 95 96 94

-84

-75

-35

-82

-74

-34

95 92 93 90

90 90

0.5

3.9

±15.1

= 10 k CL=150 pFfor a line load,

-78

-30

1.0

90 87

88 85

96 93

94 92

-85

-73

-33

-83

-72

-32

94 91 92 89

90 90

0.5

3.1

-79

-28

1.0

±11.4

dB dB dB dB

dB dB dB dB dB dB

dB dB dB dB

dB dB

mV mV

18 DS851F2

CS42L56

LINE OUTPUT CHARACTERISTICS

Test conditions (unless otherwise specified): Connections to the CS42L56 are shown in the “Typical Connection Diagrams” on

page 11; Input test signal is a full-scale 997 Hz sine wave; All Supplies = VA, VCP Mode; GND = AGND = 0 V; TA = +25C;

Measurement bandwidth is 20 Hz to 20 kHz; Sample Frequency = 48 kHz; Test load R

page 21); Measurement signal path is SDIN to LINEOUTx.

VA = 2.5 V VA = 1 . 8 V

Parameter (Note 15)

(+2 dB Analog Gain) (Note 14)

Dynamic Range 18 to 24-Bit A-weighted

unweighted 16-Bit A-weighted

unweighted Total Harmonic Distortion + Noise (Note 16) 18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

Full-scale Output Voltage (Note 17)

Other Characteristics

Interchannel Isolation (Note 17) Interchannel Gain Mismatch (Note 17) Output Offset Mute

(Note 17) 0dB Analog Gain

Gain Drift (Note 17) Output Impedance Load Resistance (R

Load Capacitance (CL) (Note 17)

) (Note 17)

Min Typ Max Min Typ Max Unit

93 90

1.50•VA 1.58•VA 1.71•VA 1.50•VA 1.58•VA 1.71•VA V

-90- -90-dB

- 0.1 0.32 - 0.1 0.32 dB

-±100- -±100-ppm/°C

-100- -100- 

10 - - 10 - - k

- - 150 - - 150 pF

99 96 96 94

-84

-76

-36

-82

-74

-34

0.5

3.6

= 10 k CL = 150 pF (see Figure 6 on

-78

-30

1.0

±14.6

91 88

97 94

94 92

-86

-74

-34

-84

-72

-32

0.5

2.8

-80

-28

1.0

±10.6

dB dB dB dB

dB dB dB dB dB dB

mV mV

Notes:

14. The analog gain setting (“Headphone Volume Control” on page 84 or “Line Volume Control” on

page 84) must be configured as indicated to achieve the specified output characteristics.

15. One LSB of triangular PDF dither is added to data.

16. VCP settings lower than VA reduces the headroom of the headphone amplifier. As a result, the specified THD+N performance at full-scale output voltage and power may not be achieved.

17. See Figure 6 and Figure 7. Refer to “Parameter Definitions” on page 91.

18. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 45 to Note 48

on page 90) have been normalized to Fs and can be denormalized by multiplying the X-axis scale by Fs.

19. Measurement bandwidth is from Stopband to 3 Fs.

DS851F2 19

CS42L56

Figure 6. HP Output Test Configuration

Test Load

HPOUTx

GND/A GND

0.1 µF

33 

HPREF

Measurement

Device

Symbolized component values are specified in table “HP

Output Characteristics” on page 19

Test Load

LINEOUTx

GND/A GND

LINERE F

Measurement

Device

Figure 7. Line Output Test Configuration

Symbolized component values are specified in table “Line

Output Characteristics” on page 20

20 DS851F2

CS42L56

ANALOG PASSTHROUGH CHARACTERISTICS

Test Conditions (unless otherwise specified): Connections to the CS42L56 are shown in the “Typical Connection Diagrams” on

page 11; Input test signal is a 1 kHz sine wave through the passive input filter shown in Figure 1, PGA and HP/Line gain = 0 dB;

All Supplies = VA, VCP Mode; GND = AGND = 0 V; T quency = 48 kHz; Measurement signal path is AINxx to HPOUTx or LINEOUTx.

Parameter

Analog In to HP Amp (ADC is powered down)

= 10 k(+2 dB Output Analog Gain) (Note 14)

Dynamic Range A-weighted

Total Harmonic Distortion + Noise (Note 16)

Full-scale Input Voltage (Note 8) - 0.80•VA - - 0.80•VA - Vpp Full-scale Output Voltage (Note 17) - 0.93•VA - - 0.93•VA - Vpp Frequency Response - 0/-0.3 - - 0/-0.3 - dB

= 16 (-4 dB Output Analog Gain) (Note 14)

Dynamic Range A-weighted

Total Harmonic Distortion + Noise (Note 16)

-20 dB

Full-scale Input Voltage (Note 8) - 0.80•VA - - 0.80•VA - Vpp Output Power (Note 16) -12- -6.5-mW Frequency Response - 0/-0.3 - - 0/-0.3 - dB

Analog In to Line Amp (ADC is powered down)

= 10 k(+2 dB Output Analog Gain) (Note 14)

Dynamic Range A-weighted

Total Harmonic Distortion + Noise (Note 16)

Full-scale Input Voltage (Note 8) - 0.80•VA - - 0.80•VA - Vpp Full-scale Output Voltage (Note 17) - 0.89•VA - - 0.89•VA - Vpp Frequency Response - 0/-0.3 - - 0/-0.3 - dB

= +25C; Measurement bandwidth is 20 Hz to 20 kHz; Sample Fre-

VA = 2.5 V VA = 1.8 V

Min Typ Max Min Typ Max Unit

unweighted--

-1 dB

-20 dB

-60 dB

unweighted--

-1 dB

-60 dB

unweighted--

-1 dB

-20 dB

-60 dB

94 91

-70

-71

-31

94 91

-70

-71

-31

94 91

-70

-71

-31

91 88

-80

-68

-28

91 88

-80

-68

-28

91 88

-80

-68

-28

COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

Parameter (Note 18) Min Typ Max Unit

Frequency Response 20 Hz to 20 kHz Fs = 48.000 kHz

Fs = 44.118 kHz

Passband to -0.05 dB corner

to -3 dB corner Stopband 0.55 - - Fs Stopband Attenuation (Note 19) 49 - - dB Total Group Delay - 6.5/Fs - s De-emphasis Error Fs = 44.118 kHz - - +0.05/-0.25 dB

DS851F2 21

-0.007

-0.081

0.48

0.49

+0.007 +0.081

dB dB

Fs Fs

CS42L56

Figure 8. Serial Port Timing (Slave Mode) Figure 9. Serial Port Timing (Master Mode)

hs(SK-SDO)

ss(SD-SK)

MSB

LRCK

SCLK

SDOUT

SDIN

ss(LK-SK)

ss(SDO-SK)

hm(SK-SDO)

sm(SD-SK)

MSB

LRCK

SCLK

SDOUT

SDIN

sm(SDO-SK)

sm(LK-SK)

SWITCHING SPECIFICATIONS - SERIAL PORT

Inputs: Logic 0 = GND = AGND, Logic 1 = VL, LRCK, SCLK, SDOUT C

Parameters Symbol Min Max Units

RESET pin Low Pulse Width (Note 20) 1-ms

MCLK Frequency

MCLK Duty Cycle 45 55 %

Slave Mode (Figure 8)

Input Sample Rate (LRCK) F

LRCK Duty Cycle 45 55 %

SCLK Frequency 1/t

SCLK Duty Cycle 45 55 %

LRCK Setup Time Before SCLK Rising Edge t

SDOUT Setup Time Before SCLK Rising Edge t

SDOUT Hold Time After SCLK Rising Edge t

SDIN Setup Time Before SCLK Rising Edge t

SDIN Hold Time After SCLK Rising Edge t

Master Mode (Figure 9)

Output Sample Rate (LRCK)

LRCK Duty Cycle 45 55 %

SCLK Frequency SCLK = MCLK mode 1/t

All Other Modes 1/t

SCLK Duty Cycle RATIO[4:0] = ‘xxx00’ or ‘xxx11’ 45 55 %

RATIO[4:0] = ‘xxx01’ (Note 21) 33 66 %

LRCK Time Before SCLK Falling Edge t

SDOUT Setup Time Before SCLK Rising Edge t

SDOUT Hold Time After SCLK Rising Edge t

SDIN Setup Time Before SCLK Rising Edge t

SDIN Hold Time After SCLK Rising Edge t

LOAD

= 15 pF.

ss(LK-SK)

ss(SDO-SK)

hs(SK-SDO)

ss(SD-SK)

sm(LK-SK)

sm(SDO-SK)

hm(SK-SDO)

sm(SD-SK)

(See “Serial Port Clocking”

on page 47)

(See “Serial Port Clocking”

on page 47)

MHz

kHz

-68•FsHz

40 - ns

20 - ns

30 - ns

20 - ns

(See “Serial Port Clocking”

on page 47)

- 12.0000 MHz

-68•FsHz

-±2ns

20 - ns

30 - ns

20 - ns

Notes:

20. After powering up the CS42L56, RESET

should be held low after the power supplies and clocks are

settled. This specification is valid with the recommended capacitor on VDFILT.

21. When the RATIO[1:0] = ‘01’, the device will periodically extend the SCLK high time to compensate for the resulting fractional MCLK/SCLK ratio.

22 DS851F2

SWITCHING SPECIFICATIONS - I²C CONTROL PORT

buf

hdst

low

hdd

high

sud

sust

susp

Stop Start

Start

Stop

Repeated

SDA

SCL

irs

RESET

Figure 10. I²C Control Port Timing

Inputs: Logic 0 = GND = AGND, Logic 1 = VL (Note 22) .

Parameter Symbol Min Max Unit

CS42L56

RESET Rising Edge to Start t

SCL Clock Frequency f

Start Condition Hold Time (prior to first clock pulse) t

Clock Low Time t

Clock High Time t

Setup Time for Repeated Start Condition t

SDA Input Hold Time from SCL Falling (Note 23) t

SDA Output Hold Time from SCL Falling t

SDA Setup Time to SCL Rising t

Rise Time of SCL and SDA t

Fall Time SCL and SDA t

Setup Time for Stop Condition t

Bus Free Time Between Transmissions t

SDA Bus Capacitance C

SDA Pull-Up Resistance R

Notes:

22. All specifications are valid for the signals at the pins of the CS42L56 with the specified load capacitance.

23. Data must be held for sufficient time to bridge the transition time, t

irs

scl

hdst

low

high

sust

hddi

hddo

sud

susp

buf

, of SCL.

500 - ns

- 550 kHz

0.6 - µs

1.3 - µs

0.6 - µs

00.9µs

0.2 0.9 µs

100 - ns

-300ns

0.6 - µs

1.3 - µs

-400pF

500 - 

DS851F2 23

SWITCHING CHARACTERISTICS - SPI CONTROL PORT

CCLK

CDIN

RESET

srs

scl

sch

css

csh

dsu

Figure 11. Control Port Timing - SPI Format

Inputs: Logic 0 = GND = AGND, Logic 1 = VL, SDA CL=30pF.

Parameter Symbol Min Max Units

CCLK Clock Frequency

RESET Rising Edge to CS Falling

Falling to CCLK Edge

CS High Time Between Transmissions

CCLK Low Time

CCLK High Time

CDIN to CCLK Rising Setup Time

CCLK Rising to DATA Hold Time (Note 24)

Rise Time of CCLK and CDIN (Note 25)

Fall Time of CCLK and CDIN (Note 25)

Notes:

24. Data must be held for sufficient time to bridge the transition time of CCLK.

25. For f

<1 MHz.

sck

srs

css

csh

sch

dsu

scl

20 - ns

1.0 - s

66 - ns

40 - ns

15 - ns

CS42L56

06.0MHz

- 100 ns

24 DS851F2

CS42L56

ANALOG OUTPUT ATTENUATION CHARACTERISTICS

Test Conditions (unless otherwise specified): Connections to the CS42L56 are shown in the “Typical Connection Diagrams” on

page 11; GND = AGND = 0 V. Attenuation is referenced to the full-scale voltage for the given output. Test load RL = 3 k

= 150 pFfor a line load, and test load RL=16  CL = 150 pF for a headphone load (See Figure 6 and Figure 7 on page 21).

Power Status

Parameters

Headphone Mute Attenuation (HPxMUTE=1) (Note 26)

Line Mute Attenuation (LINExMUTE=1) (Note 26)

Notes:

26. Assumes no external impedance on HPREF or LINEREF. External impedance on HPREF or LINEREF will impact the attenuation.

Headphone Line

OFF OFF

ON ON

OFF OFF

ON ON

OFF

Min Typ Max Units

90 90 90 90

dB dB dB dB

DS851F2 25

CS42L56

DC CHARACTERISTICS

Test Conditions (unless otherwise specified): Connections to the CS42L56 are shown in the “Typical Connection Diagrams” on

page 11; GND = AGND = 0 V; all voltages with respect to ground.

Parameters Min Typ Max Units

VHPFILT Characteristics (Note 27)

VCP Mode +VHPFILT

-VHPFILT

VCP/2 Mode +VHPFILT

-VHPFILT

MIC BIAS Characteristics

Nominal Voltage BIAS_LVL[1:0] = 00

BIAS_LVL[1:0] = 01 BIAS_LVL[1:0] = 10

BIAS_LVL[1:0] = 11

DC Output Current (Note 28) - - 1.22 mA

Power Supply Rejection Ratio (PSRR) @ 1 kHz BIAS_LVL[1:0] = 00

BIAS_LVL[1:0] = 01 BIAS_LVL[1:0] = 10

BIAS_LVL[1:0] = 11

Misc. DC Filter Characteristics

FILT+

VDFILT

Power Supply Rejection Ratio (PSRR) Characteristics

PSRR with 100 mVpp, 1 kHz signal (Note 29) PGA to ADC

PGA (Pseudo Differential) to ADC

ADC

PGA to HP & Line Amps

PGA (Pseudo Differential) to HP & Line Amps

DAC to HP & Line Amps

SRR with 100 mVpp, 60 Hz signal (Notes 29, 30) PGA to ADC

ADC PGA to HP & Line Amps DAC to HP & Line Amps

VCP

-VCP

VCP/2

-VCP/2

0.9•VA

0.8•VA

0.7•VA

0.6•VA

45 50 50 50

VA/ 2

0.9

47 58 57 44 54 56

35 25 50 60

V V

V V V V

dB dB dB dB

V V V

dB dB dB dB dB dB

dB dB dB dB

Notes:

27. No load connected to HPOUTx and LINEOUTx.

28. VA = 2.71 V, BIAS_LVL[1:0] = 00, total equivalent external impedance to ground = 2 k.

29. Valid with the recommended capacitor values on FILT+ and VQ, no load on HP and Line. Increasing the capacitance on FILT+ and VQ will also increase the PSRR.

30. The PGA is biased with VQ, created by a resistor divider from the VA supply. Increasing the capacitance on FILT+ and VQ will also increase the PSRR at low frequencies. A 10 µF capacitor on VQ improves the PSRR to 42 dB.

26 DS851F2

CS42L56

VCP

GND/AGND

Voltmeter

1 

Power Supply

1 

VLDO

2.2 µF

0.1 µF

Note: Current is derived from the voltage drop across a 1  resistor in series with each supply input.

Figure 12. Power Consumption Test Configuration

DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS

Parameters (Note 31) Symbol Min Max Units

Input Leakage Current I

Input Capacitance -10pF

1.8 V - 3.3 V Logic

High-Level Output Voltage (I

Low-Level Output Voltage (I

= -100 A) V

= 100 A) V

High-Level Input Voltage VL = 1.65 V

VL = 1.8 V VL = 2.0 V

VL > 2.0 V

Low-Level Input Voltage V

HPDETECT Input

High-Level Input Voltage HPDV Low-Level Input Voltage HPDV

31. See “I/O Pin Characteristics” on page 10 for serial and control port power rails.

-±10A

VL - 0.2 - V

-0.2V

0.83•VL

0.76•VL

0.68•VL

0.65•VL

-0.30•VLV

0.65•VA - V

- 0.35•VA V

DS851F2 27

POWER CONSUMPTION - ALL SUPPLIES = 1.8 V

Power Ctl. Registers ADC, Line, HP

Sel. Registers

Operation Test Conditions (unless otherwise

specified): All zeros input, slave mode, sample rate = 48 kHz; No load. Refer to

Figure 12 on page 28.

Off (Note 32)

Standby (Note 33) MCLKDIS=1

MCLKDIS=0

(Note 34) MCLKDIS=x

Mono Record (Note 35) ADC

PGA to ADC

Stereo Record (Note 35) ADC

PGA to ADC

Mono Play to HP No Effects

Mono Play to Line No Effects

Stereo Play to HP No Effects

Stereo Play to Line No Effects

Stereo Passthrough to HP

Stereo Passthrough to Line

Mono Rec. & Play No Effects

PGA In, HP Out

Stereo Rec. & Play No Effects

PGA In, HP Out

Stereo Play to HP No Effects

16 load (Note 36)

02h

page 58

PDN_CHRG

PDN_ADCB

03h page 59 08h page 74

PDN_ADCA

PDN

PDN_HPB[1:0]

PDN_HPA[1:0]

PDN_LINB[1:0]

PDN_LINA[1:0]

ADCBMUX[1:0]

ADCAMUX[1:0]

xxxxx x x x x x xxxxx xxx1x x x x x x xxxxx xxx1x x x x x x xxxxx xxx1x x x x x x xxxxx 010011111111xx01xxxxx 010011111111xx00xxxxx 0000111111110101xxxxx 0000111111110000xxxxx 111011101111xxxxxxx01

Effects

111011101111xxxxxxx00

111011111110xxxxx0xx1

Effects

111011111110xxxxx0xx0

111010101111xxxxxx001

Effects

111010101111xxxxxx000

111011111010xxxx00xx1

Effects

111011111010xxxx00xx0

011010101111xxxxxx11x

011011111010xxxx11xxx

010011101111xx00xxx01

010011101111xx00xxx00

Effects

0000101011110000xx001

Effects

0000101011110000xx000

111010101111xxxxxx001

LINEBMUX

LINEAMUX

HPBMUX

HPAMUX

CS42L56

Typical Current (mA)

VCPiVAiVLDOiVL

Class

Mode

page

PDN_DSP - 0Fh page 66

- 0.001 0.001 0.007 0.002 0.02

- 0.001 0.001 0.053 0.007 0.11

- 0.001 0.010 0.292 0.007 0.56

- 0.001 0.001 0.020 0.001 0.04

- 0.001 0.915 0.671 0.018 2.89

- 0.001 1.056 0.672 0.017 3.14

- 0.001 1.207 0.824 0.023 3.70

- 0.002 1.469 0.826 0.022 4.17

VCP/2

0.407 1.100 0.718 0.007 4.02

VCP

0.949 1.107 0.718 0.007 5.01

VCP/2

0.407 1.100 1.050 0.007 4.62

VCP

0.948 1.107 1.050 0.007 5.60

VCP/2

0.392 1.101 0.719 0.007 3.99

VCP

0.844 1.107 0.717 0.007 4.82

VCP/2

0.392 1.101 1.046 0.007 4.58

VCP

0.844 1.107 1.046 0.007 5.41

VCP/2

0.604 1.587 0.720 0.007 5.25

VCP

1.420 1.594 0.717 0.007 6.73

VCP/2

0.604 1.587 1.090 0.007 5.92

VCP

1.419 1.594 1.090 0.007 7.40

VCP/2

0.570 1.589 0.718 0.007 5.19

VCP

1.205 1.597 0.719 0.007 6.35

VCP/2

0.570 1.589 1.089 0.007 5.86

VCP

1.205 1.597 1.088 0.007 7.01

VCP/2

0.565 1.180 0.213 0.007 3.54

VCP

1.198 1.188 0.213 0.007 4.69

VCP/2

0.571 1.183 0.213 0.007 3.55

VCP

1.205 1.190 0.213 0.007 4.71

VCP/2

0.408 1.921 1.084 0.018 6.18

VCP

0.950 1.928 1.089 0.018 7.17

VCP/2

0.408 1.921 1.415 0.018 6.77

VCP

0.952 1.928 1.412 0.018 7.76

VCP/2

0.604 2.820 1.239 0.023 8.43

VCP

1.422 2.827 1.240 0.023 9.92

VCP/2

0.604 2.820 1.613 0.023 9.11

VCP

1.424 2.827 1.612 0.023 10.59

VCP/2

2.725 1.579 0.737 0.008 9.09

Tota l

Power

(mW)

28 DS851F2

+ 64 hidden pages