Cirrus Logic CS42L52 User Manual

Serial Audio

Input/Output

I

2

C Control

+1.65 V to +3.47 V

Interface Supply

Control Port

Serial Audio Port

Level Shifter

Multi-bit

 ADC

Beep

+1.65 V to +2.63 V

Analog Supply

Multi-bit

 ADC

ALC

Left HP/Line
Output

Ground-Centered
Amps

Mono mix,
Limiter, Bass,
Treble Adjust

Volume, Mono

Swap, Mix

Right HP/Line
Output

Left
Inputs

Right
Inputs

+1.65 V to +2.63 V

Headphone Supply

Speaker/HP
Switch

+1.60 V to +5.25 V

Battery

Charge Pump

+VHP

-VHP

+1.65 V to +2.63 V

Digital Supply

+1.65 V to +2.63 V

Analog Supply

Pulse-Width

Modulator

(PWM)

Stereo/Mono
Full-Bridge
Speaker
Outputs

Battery Level Monitoring & Compensation

Multi-bit

 DAC

MIC Bias

HPF

Selectable
Bias Voltage





ALC

Summing
Programmable
Gain Amps

+16 to +32 dB Diff./
S.E. MIC Pre-Amps

Class D Amps

1
2
3
4

1
2
3
4

+

­+

-

Reset

DRAFTv1

3/1/13

CS42L52

Low-Power, Stereo CODEC with Headphone and Speaker Amps

Stereo CODEC

 High Performance Stereo ADC and DAC

– 99 dB (ADC), 98 dB (DAC) Dyn. Range (A-wtd)
– -88 dB THD+N

Flexible Stereo Analog Input Architecture



– 4:1 Analog Input MUX
– Analog Input Mixing
– Analog Passthrough with Volume Control
– Analog Programmable Gain Amplifier (PGA)



Programmable Automatic Level Control (ALC)

– Noise Gate for Noise Suppression
– Programmable Threshold and Attack/Release

Rates



Dual MIC Inputs

– Differential or Single-ended
– +16 dB to +32 dB with 1-dB step Mic Pre-

Amplifiers

– Programmable, Low-noise MIC Bias Levels



Digital Signal Processing Engine

– Bass and Treble Tone Control, De-emphasis
– Master Vol. and Independent PCM SDIN + ADC

SDOUT Mix Volume Control
– Soft-Ramp and Zero-Cross Transition s
– Programmable Peak-detect and Limiter
– Beep Generator w/Full Tone Control

Class D Stereo/Mono Speaker Amplifier

 No External Filter Required
 High-power Stereo Output at 10% THD+N

– 2 x 1.00 W into 8  @ 5.0 V
– 2 x 550 mW into 8  @ 3.7 V
– 2 x 230 mW into 8  @ 2.5 V



High-power Mono Output at 10% THD+N

– 1 x 1.90 W into 4  @ 5.0 V
– 1 x 1.00 W into 4  @ 3.7 V
– 1 x 350 mW into 4  @ 2.5 V



Direct Battery-powered Operation

– Battery Level Monitoring and Compensation

81% Efficiency at 800 mW



 Phase-aligned PWM Output Reduces Idle

Channel Current

 Spread Spectrum Modulation
 Low Quiescent Current

Stereo Headphone Amplifier

 Ground-centered Outputs

– No DC-Blocking Capacitors Required
– Integrated Negative Voltage Regulator



High-power Output at -75 dB THD+N

– 2 x 23 mW Into 16  @ 1.8 V
– 2 x 44 mW Into 16  @ 2.5 V

(Features continued on page 2)

http://www.cirrus.com

Copyright  Cirrus Logic, Inc. 2013

(All Rights Reserved)

MAR ’13

DS680F2

3/1/13

CS42L52

System Features

 12, 24, and 27 MHz Master Clock Support in

Addition to Typical Audio Clock Rates

 High-performance 24-bit Converters

– Multi-bit Delta-Sigma Architecture
– Very Low 64Fs Oversampling Clock Reduces

Power Consumption



Low-power Operation

– Stereo Analog Passthrough: 10 mW @ 1.8 V
– Stereo Playback: 14 mW @ 1.8 V
– Stereo Rec. and Playback: 23 mW @ 1.8 V



Variable Power Supplies

– 1.8 V to 2.5 V Digital and Analog
– 1.6 V to 5 V Class D Amplifier
– 1.8 V to 2.5 V Headphone Amplifier
– 1.8 V to 3.3 V Interface Logic



Power-down Management

– ADC, DAC, CODEC, MIC Pre-Amplifier, PGA,

Headphone Amplifier, Speaker Amplifier



Analog and Digital Routing/Mixes:

– Line/Headphone Out = Analog In (ADC

Bypassed)

– Line/Headphone/Speaker

Out = ADC + Digital In

– Digital Out = ADC + Digital In
– Internal Digital Loopback
– Mono Mixes



Flexible Clocking Options

– Master or Slave Operation
– High-impedance Digital Output Option (for easy

MUXing between CODEC and other data

sources)

– Quarter-speed Mode - (i.e. allows 8 kHz Fs

while maintaining a flat noise floor up to 16 kHz)

– 4 kHz to 96 kHz Sample Rates



I²C™ Control Port Operation

 Headphone/Speaker Detection Input
 Pop and Click Suppression

Applications

 Digital Voice Recorders, Digital Cameras, and

Camcorders

 PDA’s
 Personal Media Players
 Portable Game Consoles

General Description

The CS42L52 is a highly integrated, low-power stereo CO­DEC with headphone and Class D speaker amplifiers. The
CS42L52 offers many features suitable for low-power, porta­ble system applications.

The ADC input path allows independent channel control of a
number of features. Input summing amplifiers mix and select
line-level and/or microphone-level inputs for each channel.
The microphone input path includes a selectable programma­ble-gain pre-amplifier stage and a low-noise MIC bias voltage
supply. A PGA is available for line or microphone inputs and
provides analog gain with soft-ramp and zero-cross transi­tions. The ADC also features a digital volume control with soft
ramp transitions. A programmable ALC and Noise Gate mon­itor the input signals and adjust the volume levels
appropriately. To conserve power, the ADC may be bypassed
while still allowing full analog volume control.

The DAC output path includes a digital signal processing en­gine with various fixed-function controls. Tone Control
provides bass and treble adjustment of four selectable corner
frequencies. The Digital Mixer provides independent volume
control for both the ADC output and PCM input signal paths,
as well as a master volume control. Digital Volume controls
may be configured to change on soft-ramp transitions while
the analog controls can be configured to occur on every zero
crossing. The DAC also includes de-emphasis, limiting func­tions and a BEEP generator, delivering tones selectable
across a range of two full octaves.

The stereo hea dphone amplifier is powered from a separate
positive supply and the integrated charge pump provides a
negative supply. This allows a ground-centered, analog output
with a wide signal swing and eliminates external DC-blocking
capacitors.

The Class D stereo s peaker amplifier does not require an
external filter and provides the high-efficiency amplification re­quired by power-sensitive portable applications. The speaker
amplifier may be powered directly from a battery while the in­ternal DC supply monitoring and compensation provides a
constant gain level as the battery’s voltage decays.

In addition to its many features, the CS42L52 operates from a
low-voltage analog and digital core making it ideal for portable
systems that require extremely low power consumption in a
minimal amount of space.

The CS42L52 is available in a 40-pin QFN package in Com­mercial (-40 to +85 °C) grade. The CS42L52 Customer
Demonstration board is also available for device evaluation
and implementation suggestions. Refer to “Ordering Informa-

tion” on page 81 for complete ordering information.

2 DS680F2

TABLE OF CONTENTS

1. PIN DESCRIPTIONS .............................................................................................................................. 8

1.1 I/O Pin Characteristics ............................. .... ... ... ... .... ... ... ... .... ......................................................... 10

2. TYPICAL CONNECTION DIAGRAM ................................................................................................... 11

3. CHARACTERISTIC AND SPECIFICATIONS ...................................................................................... 12

RECOMMENDED OPERATING CONDITIONS ................................................................................... 12

ABSOLUTE MAXIMUM RATINGS .......................................................................................................12

ANALOG INPUT CHARACTERISTICS ................................................................................................ 13

ADC DIGITAL FILTER CHARACTERISTICS ....................................... ... .... ... ... ... ................................ 14

ANALOG OUTPUT CHARACTERISTICS ............................................................................................ 15

ANALOG PASSTHROUGH CHARACTERISTICS ............................................................................... 16

PWM OUTPUT CHARACTERISTICS ........................ .... ... ... ... .... ... ... ... .......................................... ... ... 17

HEADPHONE OUTPUT POWER CHARACTERISTICS ................................... ... .... ... ... ... ... .... ... ... ... ... 18

LINE OUTPUT VOLTAGE LEVEL CHARACTERISTICS ..................................................................... 19

COMBINED DAC INTERPOLATION AND ONCHIP ANALOG FILTER RESPONSE .......................... 19

SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 20

SWITCHING SPECIFICATIONS - I²C CONTROL PORT ..................................................................... 21

DC ELECTRICAL CHARACTERISTICS .............................................................................................. 22

DIGITAL INTERFACE SPECIFICATIONS AND CHARACTERISTICS ................................................ 22

POWER CONSUMPTION .................................................................................................................... 23

4. APPLICATIONS ................................................................................................................................... 24

4.1 Overview ......................................................................................................................................... 24

4.1.1 Basic Architecture ................................................................................................................. 24

4.1.2 Line and MIC Inputs .............................................................................................................. 24

4.1.3 Line and Headphone Outputs ...............................................................................................24

4.1.4 Speaker Driver Outputs ......................................................................................................... 24

4.1.5 Fixed Function DSP Engine .................................................................................................. 24

4.1.6 Beep Generator ..................................................................................................................... 24

4.1.7 Power Management .............................................................................................................. 24

4.2 Analog Inputs ................................................................................................................................. 25

4.2.1 MIC Inputs ............................................................................................................................. 26

4.2.2 Automatic Level Control (ALC) .............................................................................................. 26

4.2.3 Noise Gate ............................................................................................................................ 27

4.3 Analog Outputs .............................................................................................................................. 28

4.3.1 Beep Generator ..................................................................................................................... 29

4.3.2 Limiter .................................................................................................................................... 30

4.4 Analog In to Analog Out Passthrough ............................................................................................ 31

4.4.1 Overriding the ADC Power Down ... .... ... ... ... .... ... ... ................................................................ 31

4.4.2 Overriding the PGA Power Down ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ...................... 32

4.5 PWM Outputs ................................................................................................................................. 32

4.5.1 Mono Speaker Output Configuration ..................... .................................... ............................ 32

4.5.2 VP Battery Compensation ........... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ................................ 33

4.5.2.1 Maintaining a Desired Output Level ........................................................................... 33

4.6 Serial Port Clocking ........................................................................................................................ 33

4.7 Digital Interface Formats ................................................................................................................ 35

4.7.1 DSP Mode ............................................................................................................................. 35

4.8 Initialization ..................................................................................................................................... 36

4.9 Recommended Power-up Sequence ..............................................................................................37

4.10 Recommended Power-Down Sequence ...................................................................................... 37

4.11 Required Initialization Settings ..................................................................................................... 37

4.12 Control Port Operation .................................................................................................................. 38

4.12.1 I²C Control ................. ... .... .......................................... ... ... ... ... .... ... ...................................... 38

4.12.2 Memory Address Pointer (MAP) .................................... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 39

3/1/13

CS42L52

DS680F2 3

3/1/13

CS42L52

4.12.2.1 Map Increment (INCR) ............................................................................................. 39

5. REGISTER QUICK REFERENCE ........................................................................................................ 40

6. REGISTER DESCRIPTION .................................................................................................................. 42

6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 42

6.1.1 Chip I.D. (Read Only) ............................................................................................................ 42

6.1.2 Chip Revision (Read Only) .................................................................................................... 42

6.2 Power Control 1 (Address 02h) ...................................................................................................... 42

6.2.1 Power Down ADC Charge Pump .......................................................................................... 42

6.2.2 Power Down PGAx ................................................................................................................ 42

6.2.3 Power Down ADCx ................................................................................................................ 43

6.2.4 Power Down ................................................ .......................................... ................................ 43

6.3 Power Control 2 (Address 03h) ...................................................................................................... 43

6.3.1 Power Down ADC Override ................................................................................................... 43

6.3.2 Power Down MICx ................................................................................................................. 43

6.3.3 Power Down MIC Bias .......................................................................................................... 43

6.4 Power Control 3 (Address 04h) ...................................................................................................... 44

6.4.1 Headphone Power Control ....... ... .......................................... ... .... ... ... ... .... ... ......................... 44

6.4.2 Speaker Power Control ............... ... .... ... ... ... .......................................... .... ... ... ...................... 44

6.5 Clocking Control (Address 05h) ...................................................................................................... 44

6.5.1 Auto-Detect ........................ ... ... ... ... .... .......................................... ......................................... 44

6.5.2 Speed Mode ................................................ .......................................... ................................ 45

6.5.3 32kHz Sample Rate Group ................................................................................................... 45

6.5.4 27 MHz Video Clock .............................................................................................................. 45

6.5.5 Internal MCLK/LRCK Ratio ................................................................................................... 45

6.5.6 MCLK Divide By 2 .......... .......................................... .......................................... ................... 46

6.6 Interface Control 1 (Address 06h) .................................................................................................. 46

6.6.1 Master/Slave Mode ............................... ... ............................................................................. 46

6.6.2 SCLK Polarity .................................................. .......................................... ............................ 46

6.6.3 ADC Interface Format ........................... ... ... .... ... ... ... .... ... ... ... ................................................ 46

6.6.4 DSP Mode ................................................... .......................................... ................................ 46

6.6.5 DAC Interface Format ........................... ... ... .... ... ... ... .... ... ... ... ................................................ 47

6.6.6 Audio Word Length ................................................................................................................ 47

6.7 Interface Control 2 (Address 07h) .................................................................................................. 47

6.7.1 SCLK equals MCLK .............................................................................................................. 47

6.7.2 SDOUT to SDIN Digital Loopback ......................................................................................... 47

6.7.3 Tri-State Serial Port Interface ............................. ... ... .... ... ... ... ... ............................................. 48

6.7.4 Speaker/Headphone Switch Invert .................................. ... ... ... .... ... ... ... .... ... ... ... ... .... ............ 48

6.7.5 MIC Bias Level ............... .... ... ... .......................................... ................................................... 48

6.8 Input x Select: ADCA and PGAA (Address 08h), ADCB and PGAB (Address 09h) ....................... 48

6.8.1 ADC Input Select ... ... ... ... .... ................................................................................................... 48

6.8.2 PGA Input Mapping ........ .......................................... .... ... .......................................... ... ......... 49

6.9 Analog and HPF Control (Address 0Ah) ......................................................................................... 49

6.9.1 ADCx High-Pass Filter .......................................................................................................... 49

6.9.2 ADCx High-Pass Filter Freeze ..............................................................................................49

6.9.3 Ch. x Analog Soft Ramp . .... ... .......................................... ... ... ... ............................................. 49

6.9.4 Ch. x Analog Zero Cross .......... .......................................... ... ... ............................................. 49

6.10 ADC HPF Corner Frequency (Address 0Bh) ................................................................................ 50

6.10.1 HPF x Corner Frequency .................................................................................................

6.11 Misc. ADC Control (Address 0Ch) ................................................................................................ 50

6.11.1 Analog Front-End Volume Setting B=A ............................................................................... 50

6.11.2 Digital MUX ......................................................................................................................... 50

6.11.3 Digital Sum .......................................................................................................................... 50

6.11.4 Invert ADC Signal Polarity ................................................................................................... 51

6.11.5 ADC Mute ............................................................................................................................ 51

... 50

4 DS680F2

3/1/13

CS42L52

6.12 Playback Control 1 (Address 0Dh) ............................................................................................... 51

6.12.1 Headphone Analog Gain ..................................................................................................... 51

6.12.2 Playback Volume Setting B=A ............................................................................................ 51

6.12.3 Invert PCM Signal Polarity .................................................................................................. 52

6.12.4 Master Playback Mute ......................................................................................................... 52

6.13 Miscellaneous Controls (Address 0Eh) ..................... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 52

6.13.1 Passthrough Analog ............... ... .......................................... ... .... ... ... ... .... ... ... ... ... .... ... ......... 52

6.13.2 Passthrough Mute ..................... ... .... ... ... ... .... ... ... ... .... ... .......................................... ... ......... 52

6.13.3 Freeze Registers .... ... ... .... .......................................... ... ... ... ... .... ... ... ................................... 52

6.13.4 HP/Speaker De-emphasis ................................................................................................... 53

6.13.5 Digital Soft Ramp ................................................................................................................ 53

6.13.6 Digital Zero Cross ................................... ... .... ... ... ... .... ... .......................................... ............ 53

6.14 Playback Control 2 (Address 0Fh) ................................................................................................ 54

6.14.1 Headphone Mute ....... ... .... ... ... .......................................... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 54

6.14.2 Speaker Mute ................... ... ... .......................................... ... ... .... ... ... ... ................................ 54

6.14.3 Speaker Volume Setting B=A ..............................................................................................54

6.14.4 Speaker Channel Swap ....................................................................................................... 54

6.14.5 Speaker MONO Control ...................................................................................................... 54

6.14.6 Speaker Mute 50/50 Control ............................................................................................... 54

6.15 MICx Amp Control:MIC A (Address 10h) and MIC B (Address 11h) ............................................ 55

6.15.1 MIC x Select ........................................................................................................................ 55

6.15.2 MICx Configuration .............................. ... ... .... ... ... ... .... ... .......................................... ............ 55

6.15.3 MICx Gain ................................. ... .... ... ... ... .......................................... .... ... ... ...................... 55

6.16 PGAx Vol. and ALCx Transition Ctl.:

ALC, PGA A (Address 12h) and ALC, PGA B (Address 13h) .............................................................. 55

6.16.1 ALCx Soft Ramp Disable ..................................................................................................... 55

6.16.2 ALCx Zero Cross Disable .................................................................................................... 56

6.16.3 PGAx Volume .. .... ... ... ... .... ... ... ... ... .......................................... .... ... ... ... .... ... ... ...................... 56

6.17 Passthrough x Volume: PASSAVOL (Address 14h) and PASSBVOL (Address 15h) ................. 57

6.17.1 Passthrough x Volume ........................................................................................................ 57

6.18 ADCx Volume Control: ADCAVOL (Address 16h) and ADCBVOL (Address 17h) ....................... 57

6.18.1 ADCx Volume ...... .......................................... ... ... ... .... ... ... ... ................................................ 57

6.19 ADCx Mixer Volume: ADCA (Address 18h) and ADCB (Address 19h) ........................................ 58

6.19.1 ADC Mixer Channel x Mute ................................................................................................. 58

6.19.2 ADC Mixer Channel x Volume ............................................................................................. 58

6.20 PCMx Mixer Volume: PCMA (Address 1Ah) and PCMB (Address 1Bh) ...................................... 58

6.20.1 PCM Mixer Channel x Mute ................................................................................................58

6.20.2 PCM Mixer Channel x Volume ............................................................................................ 58

6.21 Beep Frequency and On Time (Address 1Ch) ............................................................................. 59

6.21.1 Beep Frequency ..................................................... .... ... ... ... ... .... ... ...................................... 59

6.21.2 Beep On Time ..................... ... ... ... .... ... ... ... .... ... ... ... .... ......................................... .... ............ 60

6.22 Beep Volume and Off Time (Address 1Dh) .................................................................................. 60

6.22.1 Beep Off Time ..................... ... ... ... .... ... ... ... .... .......................................... ... ... ... ... .... ............ 60

6.22.2 Beep Volume .......... ... ... .... ... .......................................... ... ... ... .... ... ... ... .... ... ... ... ... .... ............ 61

6.23 Beep and Tone Configuration (Address 1Eh) ............................................................................... 61

6.23.1 Beep Configuration ........................................... ... ... .... ... ... ... ................................................ 61

6.23.2 Beep Mix Disable ................................................................................................................ 61

6.23.3 Treble Corner Frequency ................. ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ................... 62

6.23.4 Bass Corner Frequency ......................... ... .... ... ... ... .......................................... ... .... ... ... ...... 62

6.23.5 Tone Control Enable .............................. ... .... ... ... ... .... ... ... ... ................................................ 62

6.24 Tone Control (Address 1Fh) ............................................ .... ... ... ... ... .... ... ... ... .... ... ... ... ................... 62

6.24.1 Treble Gain ............................................................................. .... ... ... ... .... ... ......................... 62

6.24.2 Bass Gain ......................................... .......................................... ......................................... 63

6.25 Master Volume Control: MSTA (Address 20h) and MSTB (Address 21h) .................................... 63

DS680F2 5

3/1/13

CS42L52

6.25.1 Master Volume Control ........................................................................................................ 63

6.26 Headphone Volume Control: HPA (Address 22h) and HPB (Address 23h) ................................. 63

6.26.1 Headphone Volume Control ................... ................................................................. ............63

6.27 Speaker Volume Control: SPKA (Address 24h) and SPKB (Address 25h) .................................. 64

6.27.1 Speaker Volume Control ..................................................................................................... 64

6.28 ADC and PCM Channel Mixer (Address 26h) ................................. .... ... ... ... .... ... ... ... ... .... ... ... ... ... 64

6.28.1 PCM Mix Channel Swap .....................................................................................................64

6.28.2 ADC Mix Channel Swap ...................................................................................................... 64

6.29 Limiter Control 1, Min/Max Thresholds (Address 27h) ................................................................. 65

6.29.1 Limiter Maximum Threshold ............................. ................................................................... 65

6.29.2 Limiter Cushion Threshold .................................................................................................. 65

6.29.3 Limiter Soft Ramp Disable ......................... ....... ...... ....... ...... ....... ...... ....... ...... ...... ....... ......... 65

6.29.4 Limiter Zero Cross Disable ..................... .................................... ................................... ...... 66

6.30 Limiter Control 2, Release Rate (Address 28h) ......................... ............................................. ......66

6.30.1 Peak Detect and Limiter ...................................................................................................... 66

6.30.2 Peak Signal Limit All Channels ........................................................................................... 66

6.30.3 Limiter Release Rate ...........................................................................................................66

6.31 Limiter Attack Rate (Address 29h) ................................................................................................ 67

6.31.1 Limiter Attack Rate .............................................................................................................. 67

6.32 ALC Enable and Attack Rate (Address 2Ah) ................ ... .... ... ... ... ... .......................................... ... 67

6.32.1 ALCx Enable ....................................................................................................................... 67

6.32.2 ALC Attack Rate .................................................................................................................. 67

6.33 ALC Release Rate (Address 2Bh) ...................... .......................................... ................................ 68

6.33.1 ALC Release Rate ............................................................................................................... 68

6.34 ALC Threshold (Address 2Ch) ..................................................................................................... 68

6.34.1 ALC Maximum Threshold .................................................................................................... 68

6.34.2 ALC Minimum Threshold ..................................................................................................... 69

6.35 Noise Gate Control (Address 2Dh) ......................... ... ................................................................... 69

6.35.1 Noise Gate All Channels ..................................................................................................... 69

6.35.2 Noise Gate Enable .............................................................................................................. 69

6.35.3 Noise Gate Threshold and Boost ........................................................................................ 70

6.35.4 Noise Gate Delay Timing ....................................................................................................70

6.36 Status (Address 2Eh) (Read Only) ..... ... .... .......................................... ... ... ... .... ... ... ... ... .... ... ... ...... 70

6.36.1 Serial Port Clock Error (Read Only) ....................................................................................70

6.36.2 DSP Engine Overflow (Read Only) ..................................................................................... 71

6.36.3 PCMx Overflow (Read Only) ...............................................................................................71

6.36.4 ADCx Overflow (Read Only) ...............................................................................................71

6.37 Battery Compensation (Address 2Fh) .......................................................................................... 71

6.37.1 Battery Compensation ......................... ................................... .................................... ......... 71

6.37.2 VP Monitor .................................... .... ... ... ... .... .......................................... ... ... ... ................... 71

6.37.3 VP Reference ...................................................................................................................... 72

6.38 VP Battery Level (Address 30h) (Read Only) ............................................................................... 72

6.38.1 VP Voltage Level (Read Only) ............................................................................................72

6.39 Speaker Status (Address 31h) (Read Only) ..................................................................... ... ... ... ... 72

6.39.1 Speaker Current Load Status (Read Only) ......................................................................... 72

6.39.2 SPKR/HP Pin Status (Read Only) ....................................................................................... 73

6.40 Charge Pump Frequency (Address 34h) ...................................................................................... 73

6.40.1 Charge Pump Frequency .................................................................................................... 73

7. ANALOG PERFORMANCE PLOTS .......... ... .... ... ... .......................................... ... .... ... ... ... ... .... ... ... ... ...74

7.1 Headphone THD+N versus Output Power Plots ............................................................................ 74

8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 76

8.1 Auto Detect Enabled .................................................................................................................... 76

8.2 Auto Detect Disabled .................................................................................................................... 76

9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 77

6 DS680F2

9.1 Power Supply and Grounding ......................................................................................................... 77

9.2 QFN Thermal Pad .......................................................................................................................... 77

10. ADC AND DAC DIGITAL FILTERS .................................................. ... .... ... ... ... .... ............................ 78

11. PARAMETER DEFINITIONS .............. ... ... ... .... ... ... ... .... ... .......................................... ... ... ... .... ............ 79

12. PACKAGE DIMENSIONS ........... .... ... ... ... ... .......................................... .... ... ... ................................... 80

THERMAL CHARACTERISTICS ....... ... ... ... ... .... ... ... ... .... ... ... ... .... ... .......................................... ... ... ...... 80

13. ORDERING INFORMATION ....... .... ... ... ... ... .... ... ... ... .... .......................................... ... ... ... ... .... ... ......... 81

14. REFERENCES ....................... ... ... .... ... ... ... ... .... ... ... .......................................... ... .... ............................ 81

15. REVISION HISTORY ................................ ... .... ... .......................................... ... ... ................................ 81

LIST OF TABLES

Table 1. MCLK, LRCK Quick Decode ....................................................................................................... 34

LIST OF FIGURES

Figure 1. Typical Connection Diagram ...................................................................................................... 11

Figure 2. Headphone Output Test Load .................................................................................................... 18

Figure 3. Serial Audio Interface Timing ..................................................................................................... 20

Figure 4. Control Port Timing - I²C ............................................................................................................ 21

Figure 5. Analog Input Signal Flow ........................................................................................................... 25

Figure 6. Single-Ended MIC Configuration ............................................................................................... 26

Figure 7. Differential MIC Configuration .................................................................................................... 26

Figure 8. ALC ............................................................................................................................................ 27

Figure 9. Noise Gate Attenuation .............................................................................................................. 27

Figure 10. DSP Engine Signal Flow .......................................................................................................... 28

Figure 11. PWM Output Stage .................................................................................................................. 29

Figure 12. Analog Output Stage ................................................................................................................ 29

Figure 13. Beep Configuration Options ..................................................................................................... 30

Figure 14. Peak Detect and Limiter ........................................................................................................... 31

Figure 15. Battery Compensation ............................................................................................................. 33

Figure 16. I²S Format ................................................................................................................................ 35

Figure 17. Left-Justified Format ................................................................................................................ 35

Figure 18. Right-Justified Format (DAC only) ........................................................................................... 35

Figure 19. DSP Mode Format) .................................................................................................................. 36

Figure 20. Control Port Timing, I²C Write .................................................................................................. 38

Figure 21. Control Port Timing, I²C Read .................................................................................................. 39

Figure 22. THD+N vs. Output Power per Channel at 1.8 V (16  load) .......................... ... ...................... 74

Figure 23. THD+N vs. Output Power per Channel at 2.5 V (16  load) .......................... ... ...................... 74

Figure 24. THD+N vs. Output Power per Channel at 1.8 V (32  load) .......................... ... ...................... 75

Figure 25. THD+N vs. Output Power per Channel at 2.5 V (32  load) .......................... ... ...................... 75

Figure 26. ADC Passband Ripple ............................................................................................................. 78

Figure 27. ADC Stopband Rejection ......................................................................................................... 78

Figure 28. ADC Transition Band ............................................................................................................... 78

Figure 29. ADC Transition Band (Detail) ................................................................................................... 78

Figure 30. DAC Passband Ripple ............................................................................................................. 78

Figure 31. DAC Stopband ......................................................................................................................... 78

Figure 32. DAC Transition Band ............................................................................................................... 78

Figure 33. DAC Transition Band (Detail) ................................................................................................... 78

3/1/13

CS42L52

DS680F2 7

1. PIN DESCRIPTIONS

12

11

13

14

15

16

17

18

19

20

29

30

28
27
26
25
24
23
22
21

39

40

38

37

36

35

34

33

32

31

2

1

3
4
5
6
7
8
9

10

GND/Thermal Pad

SDOUT

MCLK

SCLK

SDIN

SDA

LRCK

FLYN

+VHP

HP/LINE_OUTB

HP/LINE_OUTA

VQ

MICBIAS

AIN4A/MIC1+/MIC2A

AIN2A

AD0

SPKR_OUTA+

VP

VP

VD

SPKR_OUTB-

-VHPFILT

AIN4B/MIC2+/MIC2B

AIN1B

AIN2B

AFILTB

AIN3B/MIC2-/MIC1B

AFILTA

AIN1A

AIN3A/MIC1-/MIC1A

SPKR_OUTB+

SCL

DGND

SPKR_OUTA-

FLYP

VA

AGND

FILT+

RESET

VL

SPKR/HP

Top-Down (Through-Package) View

40-Pin QFN Package

3/1/13

CS42L52

Pin Name # Pin Description

SDA 1 Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode.
SCL 2 Serial Control Port Clock (Input) - Serial clock for the serial control port.

AD0 3
SPKR_OUTA+

SPKR_OUTA­SPKR_OUTB+
SPKR_OUTB-

VP

-VHPFILT 10

FLYN 11

FLYP 12

+VHP 13
HP/LINE_OUTB, A 14,15 Headphone/Line Audio Output (Output) - Stereo headphone or line level analog outputs.

VA 16 Analog Power (Input) - Positive power for the internal analog section.

8 DS680F2

Address Bit 0 (Input) - Chip address bit 0.

4
6

PWM Speaker Output (Output) - Full-bridge amplified PWM speaker outputs.

7
9

5

Power for PWM Drivers (Input) - Power supply for the PWM output driver stages.

8

Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge
pump that provides the negative rail for the headphone/line amplifi e rs.

Charge Pump Cap Negative Node (Output) - Negative node for the inverting charge pump’s fly-
ing capacitor.
Charge Pump Cap Positive Node (Output) - Positive node for the inverting charge pump’s flying
capacitor.
Positive Analog Power for Headphone (Input) - Positive voltage rail and power for the internal
headphone amplifiers and inverting charge pump.

3/1/13

CS42L52

AGND 17 Analog Ground (Input) - Ground reference for the internal analog section.
FILT+ 18
VQ 19 Quiescent Voltage (Output) - Filter connection for the internal quiescent voltage.
MICBIAS 20
AIN4A,B

AIN3A,B
MIC1+,­MIC2+,­MIC2A,B

MIC1A,B
AIN2A,B

AIN1A,B
AFILTA,B 27,28 Anti-alias Filter Connection (Output) - Anti-alias filter connection for the ADC inputs.

SPKR/HP 31
RESET

VL 33
VD 34 Digital Power (Input) - Positive power for the internal digital section.

DGND 35 Digital Ground (Input) - Ground reference for the internal digital section.
SDOUT 36 Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
MCLK 37 Master Clock (Input) - Clock source for the delta-sigma modulators.
SCLK 38 Serial Clock (Input/Output) - Serial clock for the serial audio interface.
SDIN 39 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

LRCK 40

GND/Thermal Pad -

Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir-
cuits.

Microphone Bias (Output) - Low noise bias supply for an external microphone. Electrical charac­teristics are specified in the DC Electrical Characteristics table.

21,22

Line-Level Analog Inputs (Input) - Single-ended stereo line-level analog inputs.

23,24
21,23

Differential Microphone Inputs (Input) - Differential stereo microphone inputs.

22,24
21,22

Single-Ended Microphone Inputs (Input) - Single-ended stereo microphone inputs.

23,24
25,26

Line-Level Analog Inputs (Input) - Single-ended stereo line-level analog inputs.

29,30

Speaker/Headphone Switch (Input) - Powers down the left and/or right channel of the speaker
and/or headphone outputs.

32 Reset (Input) - The device enters a low power mode when this pin is driven low.

Digital Interface Power (Input) - Determines the required signal level for the serial audio inter­face and host control port.

Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on
the serial audio data line.

Ground reference for PWM power FETs and charge pump; thermal relief pad for optimized heat
dissipation.

DS680F2 9

1.1 I/O Pin Characteristics

Input and output levels and associated power supply voltage are shown in the table below. Logic levels
should not exceed the corresponding power supply voltage.

3/1/13

CS42L52

Power

Supply

VL

VA SPKR/HP Input - - 1.65 V - 2.63 V

VP

Pin Name I/O Internal

Driver Receiver

Connections

RESET Input - - 1.65 V - 3.47 V, with Hysteresis

AD0 Input - - 1.65 V - 3.47 V, with Hysteresis
SCL Input - - 1.65 V - 3.47 V, with Hysteresis
SDA Input/

Output
MCLK Input - - 1.65 V - 3.47 V
LRCK Input/

Output
SCLK Input/

Output

SDOUT Output Weak Pullup

SDIN Input - - 1.65 V - 3.47 V

SPKR_OUTA+ Output - 1.6 V - 5.25 V Power MOSFET -

SPKR_OUTA- Output - 1.6 V - 5.25 V Power MOSFET -

SPKR_OUTB+ Output - 1.6 V - 5.25 V Power MOSFET -

SPKR_OUTB- Output - 1.6 V - 5.25 V Power MOSFET -

- 1.65 V - 3.47 V, CMOS/Open
Drain

Weak Pullup

(~1 M)

Weak Pullup

(~1 M)

(~1 M)

1.65 V - 3.47 V, CMOS 1.65 V - 3.47 V

1.65 V - 3.47 V, CMOS 1.65 V - 3.47 V

1.65 V - 3.47 V, CMOS

1.65 V - 3.47 V, with Hysteresis

10 DS680F2

2. TYPICAL CONNECTION DIAGRAM

Note 4

Note 3

Note 2

Note 1

1 µF

+1.8 V to +2.5 V

0.1 µF

1 µF

DGND

VL

0.1 µF

+1.8 V to + 3 .3 V

SCL
SDA

RESET

2 k



LRCK

Digital Audio

Processor

MCLK
SCLK

VD

MIC1-

AIN3A/MIC1A

Microphone 1

SDIN
SDOUT

CS42L52

2 k



MICBIAS

+1.8 V to + 2 .5 V

HP/LIN E_OUTB

HP/LINE_OUTA

AIN1A

Left 1

1800 pF

1800 pF

100 k

100 

AIN1B

Right 1

*

*

R

L

0.1 µF

VA

Headphone Out
Left & Right

Line Level Out
Left & Right

FLYP
FLYN

-VHPFILT

0.1 µF

51.1 

0.022 µF

100 k

100 

SPKR_OUTA+

SPKR_OUTA-

SPKR/HP

51.1 

0.022 µF

MIC1+

AIN4A/MIC2A

MIC2+

AIN4B/MIC2B

Microphone 2

MIC2-

AIN3B/MIC1B

100 k

R

L

100 k

1 µF

1 µF

0.1 µF

+VHP

1 µF

10 µF

VQ

AGND

* Capacitors must be C0G or equivalent

150 pF

AFILTA
AFILTB

150 pF

1 µF

**

FILT+

1 µF

1 µF

1 µF

1 µF

* *Use low ESR ceramic capacitors.

**

**

See Note 5

SPKR_OUTB+

SPKR_OUTB-

1 µF

VP

VP

+1.6 V to

+5 V

Stereo Speakers

AIN2A

Left 2

1800 pF

1800 pF

100 k

100 

AIN2B

Right 2

*

*

100 k

100 

1 µF

1 µF

0.1 µF

0.1 µF

Analog
Input 1

Analog
Input 2

10 µF

Mic-Level
Inputs

47 k

Notes:

1. Recommended values for the default charge pump switching
frequency. The required capacitance follows an inverse
relationship with the charge pump’s switching frequency. When
increasing the switching frequency, the capacitance may
decrease; when lowering the switching frequency, the
capacitance must increase.

2. Larger capacitance reduces the ripple on the internal
amplifier’s supply. This may reduce the distortion at higher
output power levels.

3. Additional bulk capacitance may be added to improve PSRR
at low frequencies.

4. These capacitors serve as a charge reservoir for the internal
switched capacitor ADC modulators. They are only needed
when the PGA (Programmable Gain Amplifier) is bypassed.

5. Series resistance in the path of the power supplies must be
avoided. Any voltage drop on VHP will dire c tly impact the
negative charge pump supply (-VHPFILT) and clip the audio
output.

6. The value of R

L

, a current-limiting resistor used with electret
condenser microphones, is dictated by the microphone
cartridge.

7. The negative terminal of the MICx inputs connects to the
ground pin of the microphone cartridge. Gain is applied only to
the positive te rminal.

Note 6

Note 7

Note 7

AD0

Figure 1. Typical Connection Diagram

3/1/13

CS42L52

DS680F2 11

3/1/13

CS42L52

3. CHARACTERISTIC AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

AGND=DGND=0 V, All voltages with respect to ground.

Parameters Symbol Min Max Units

DC Power Supply
Analog VA 1.65 2.63 V
Headphone Amplifier +VHP 1.65 2.63 V
Speaker Amplifier VP 1.60 5.25 V
Digital VD 1.65 2.63 V
Serial/Control Port Interface VL 1.65 3.47 V
Ambient Temperature Commercial - CNZ T

A

-40 +85 C

ABSOLUTE MAXIMUM RATINGS

AGND = DGND = 0 V; All voltages with respect to ground.

Parameters Symbol Min Max Units

DC Power Supply Analog

Speaker

Digital

Serial/Control Port Interface
Input Current (Note 1) I
External Voltage Applied to Analog Input (Note 2)

External Voltage Applied to Analog Output
External Voltage Applied to Digital Input (Note 2) V

Ambient Operating Temperature (power applied) T
Storage Temperature T

WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

VA, VHP

VP
VD

VL

in

V

IN

V

IN

IND

A

stg

-0.3

-0.3

-0.3

-0.3

-±10mA

AGND-0.3 VA+0.3

-VHP - 0.3 +VHP + 0.3

-0.3 VL+ 0.3 V

-50 +115 °C

-65 +150 °C

3.0

6.0

3.0

4.0

V
V
V
V

V
V

Notes:

1. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.

2. The maximum over/under voltage is limited by the input current.

12 DS680F2

3/1/13

CS42L52

ANALOG INPUT CHARACTERISTICS

Test Conditions (unless otherwise specified): Input sine wave (relative to digital full scale): 1 kHz through passive input filter; All
Supplies = VA; T

fied; “Required Initialization Settings” on page 37 written on power up.

Analog In to ADC (PGA bypassed)

Dynamic Range A-weighted
Total Harmonic Distortion + Noise -1 dBFS

Analog In to PGA to ADC

Dynamic Range
PGA Setting: 0 dB A-weighted

PGA Setting: +12 dB A-weighted
Total Harmonic Distortion + Noise

PGA Setting: 0 dB -1 dBFS

-60 dBFS
PGA Setting: +12 dB -1 dBFS - -85 -79 - -83 -77 dB

Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC

Dynamic Range
PGA Setting: 0 dB A-weighted

Total Harmonic Distortion + Noise
PGA Setting: 0 dB -1 dBFS - -76 - - -74 - dB

Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC

Dynamic Range
PGA Setting: 0 dB A-weighted

Total Harmonic Distortion + Noise
PGA Setting: 0 dB -2 dBFS - -74 - - -71 - dB

Other Characteristics

DC Accuracy
Interchannel Gain Mismatch - 0.2 - - 0.2 - dB
Gain Drift - ±100 - - ±100 - p pm/°C
Offset Error SDOUT Code with HPF On - 352 - - 352 - LSB
Input
Interchannel Isolation - 90 - - 90 - dB
HP Amp to Analog Input Isolation R

(Note 3) R

Speaker Amp to Analog Input Isolation - 60 - - 60 - dB
Full-scale Input Voltage ADC

Input Impedance (Note 4) ADC

3. Measured with DAC delivering full-scale output into specified load.

4. Measured between analog input and AGND.

= +25C; Sample Frequency = 48 kHz; Measurement Bandwidth is 20 Hz to 20 kHz unless otherwise speci-

A

VA = 2.5V VA = 1.8V

Parameters Min Typ Max Min Typ Max Unit

unweighted9390

-20 dBFS

-60 dBFS

unweighted9289
unweighted8582

unweighted

unweighted

= 10 k

L

= 16 

L

PGA (0 dB)

PGA (+12 dB)

MIC (+16 dB)
MIC (+32 dB)

PGA

MIC

-

-

-

-

-

-

-

-

-

-

-

0.73•VA

0.73•VA

-

-

-

99
96

-86

-76

-36

96
93
91
88

-88

-33

86
83

76
73

100

70

0.769•VA

0.770•VA

0.194•VA

0.115•VA

0.019•VA
20
39
50

-

-

-80

-

-30

-

-

-

-

-82

-27

-

-

-

-

-

-

0.83•VA

0.83•VA

-

-

-

90
87

-

-

-

89
86
82
79

-

-

-

-

-

-

-

-

0.73•VA

0.73•VA

-

-

-

96
93

-84

-73

-33

95
92
88
85

-86

-32

83
80

74
71

100

70

0.769•VA

0.770•VA

0.194•VA

0.1 15•VA

0.019•VA
20
39
50

-

-

-78

-

-27

-

-

-

-

-80

-26

-

-

-

-

-

-

0.83•VA

0.83•VA

-

-

-

dB
dB
dB
dB
dB

dB
dB
dB
dB

dB
dB

dB
dB

dB
dB

dB
dB

Vpp
Vpp
Vpp
Vpp
Vpp

k
k
k

DS680F2 13

3/1/13

CS42L52

ADC DIGITAL FILTER CHARACTERISTICS

Parameters (Note 5) Min Typ Max Unit

Passband (Frequency Response) to -0.1 dB corner 0 - 0.4948 Fs
Passband Ripple -0.09 - 0.17 dB
Stopband 0.6 - - Fs
Stopband Attenuation 33 - - dB
Total Group Delay -7.6/Fs- s

High-Pass Filter Characteristics (48 kHz Fs)

Frequency Response -3.0 dB

-0.13 dB
Phase Deviation @ 20 Hz - 10 - Deg
Passband Ripple - - 0.17 dB
Filter Settling Time -10

5. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 26 to 29 on

page 78) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

HPF parameters are for Fs = 48 kHz.

-

-

3.6

24.2

5

/Fs 0 s

-

-

Hz
Hz

14 DS680F2

3/1/13

CS42L52

ANALOG OUTPUT CHARACTERISTICS

Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; All Supplies = VA; TA = +25C;
Sample Frequency = 48 kHz; Measurement bandwidth is 20 Hz to 20 kHz; Test load R
(see Figure 2); Test load RL = 16  CL = 10 pF (see Figure 2) for the headphone output; HP_GAIN[2:0] = 011; “Required Initial-

ization Settings” on page 37 written on power up.

VA = 2.5 V VA = 1.8 V

Parameters

R

= 10 k

L

Dynamic Range

18- to 24-Bit A-weighted
unweighted
16-Bit A-weighted

Total Harmonic Distortion + Noise

18- to 24-Bit 0 dB

16-Bit 0 dB

RL = 16

Dynamic Range

18- to 24-Bit A-weighted
16-Bit A-weighted

Total Harmonic Distortion + Noise

18- to 24-Bit 0 dB

16-Bit 0 dB

Other Characteristics for R

Output Parameters Modulation Index (MI)

(Note 7) Analog Gain Multiplier (G)

Full-scale Output Voltage (2•G•MI•VA) (Note 7) See “Line Output Voltage Level Characteristics” on

Full-scale Output Power (Note 7) See “Headphone Output Power Characteristics” on page 18
Interchannel Isolation (1 kHz) 16 

Speaker Amp to HP Amp Isolation - 80 - - 80 - dB
Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB
Gain Drift - ±100 - - ±100 - ppm/°C
AC Load Resistance (R

Load Capacitance (C





L

) (Note 8) - - 150 - - 150 pF

L

(Note 6) Min Typ Max Min Typ Max Unit

92
89

-

unweighted

-20 dB

-60 dB

-20 dB

-60 dB

unweighted
unweighted

-20 dB

-60 dB

-20 dB

-60 dB

= 16  or 10 k

L

) (Note 8) 16 - - 16 - - 



10 k

-

-

-

-

-

-

-

92
89

-

-

-

-

-

-

-

-

-

-

page 19

-

-

98
95
96
93

-86

-75

-35

-86

-73

-33

98
95
96
93

-75

-75

-35

-75

-73

-33

0.6787

0.6047

80
95

= 10 k CL = 10 pFfor the line output

L

-

-

-

-

-80

-

-29

-

-

-

-

-

-

-

-69

-

-29

-

-

-

-

-

-

-

89
86

89
86

95
92

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

93
90

-88

-72

-32

-88

-70

-30

95
92
93
90

-75

-72

-32

-75

-70

-30

0.6787

0.6047

80
93

-

-

-

-

-82

-

-26

-

-

-

-

-

-

-

-69

-

-26

-

-

-

-

-

-

-

dB
dB
dB
dB

dB
dB
dB
dB
dB
dB

dB
dB
dB
dB

dB
dB
dB
dB
dB
dB

Vpp

dB
dB

6. One (least-significant bit) LSB of triangular PDF dither is added to data.

7. Full-scale output voltage and power is determined by the gain setting, G, in register “Headphone Analog

Gain” on page 51. High gain settings at certain VA and VHP supply levels may cause clipping when the

audio signal approaches full-scale, maximum power output, as shown in Figures 22 - 25 on page 75.

DS680F2 15

3/1/13

CS42L52

8. See Figure 2. RL and CL reflect the recommended minimum resistance and maximum capacitance re­quired for the internal op-amp's stability and signal integrity. In this circuit topology, C

will effectively

L

move the band-limiting pole of the amp in the output stage. Increasing this value beyond the recom­mended 150 pF can cause the internal op-amp to become unstable.

ANALOG PASSTHROUGH CHARACTERISTICS

Test Conditions (unless otherwise specified): Input sine wave (relative to full-scale): 1 kHz through passive input filter; PGA and
HP/Line Gain = 0 dB; All Supplies = VA; T

“Required Initialization Settings” on page 37 written on power up.

Parameters Min Typ Max Min Typ Max Unit

Analog In to HP/Line Amp (ADC is powered down)
R

= 10 k

= 16





L

Dynamic Range A-weig hted

Total Harmonic Distortion + Noise -1 dBFS

-20 dBFS

Full-scale Input Voltage - 0.91•VA - - 0.91•VA - Vpp
Full-scale Output Voltage - 0.84•VA - - 0.84•VA - Vpp
Passband Ripple - 0/-0.3 - - 0/-0.3 - dB

R

L

Dynamic Range A-weig hted

Total Harmonic Distortion + Noise -1 dBFS

-20 dBFS

Full-scale Input Voltage - 0.91•VA - - 0.91•VA - Vpp
Full-scale Output Voltage - 0.84•VA - - 0.84•VA - Vpp
Output Power - 32 - - 17 - mW
Passband Ripple - 0/-0.3 - - 0/-0.3 - dB

= +25C; Sample Frequency = 48 kHz; Measurement Bandwidth is 20 Hz to 20 kHz;

A

VA = 2.5 V VA = 1.8 V

unweighted

-60 dBFS

unweighted

-60 dBFS

-

-

-

-

-

-

-

-

-

-

-96

-93

-70

-73

-33

-96

-93

-70

-73

-33

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-94

-91

-70

-71

-31

-94

-91

-70

-71

-31

-

-

-

-

-

-

-

-

-

-

dB
dB

dB
dB
dB

dB
dB

dB
dB
dB

16 DS680F2

3/1/13

CS42L52

PWM OUTPUT CHARACTERISTICS

Test conditions (unless otherwise specified): Input test signal is a full scale 997 Hz signal; MCLK = 12.2880 MHz; Measurement
Bandwidth is 20 Hz to 20 kHz; Sample Frequency = 48 kHz; Test load R

full-bridge; VD = VL = VA = VHP = 1.8 V; PWM Modulation Index of 0.85; PWM Switch Rate = 384 kHz; “Required Initialization

Settings” on page 37 written on power up.

(Note 9)

Parameters (Note 10) Symbol Conditions Min Typ Max Units

VP = 5.0 V
Power Output per Channel P

Stereo Full-Bridge THD+N < 10%

Mono Parallel Full-Bridge THD+N < 10%

Total Harmonic Distortion + Noise THD+N

Stereo Full-Bridge P

Mono Parallel Full-Bridge PO = -3 dBFS = 0.75 W

Dynamic Range DR

Stereo Full-Bridge P

Mono Parallel Full-Bridge P

VP = 3.7 V
Power Output per Channel P

Stereo Full-Bridge THD+N < 10%

Mono Parallel Full-Bridge THD+N < 10%

Total Harmonic Distortion + Noise THD+N

Stereo Full-Bridge P

Mono Parallel Full-Bridge P

Dynamic Range DR

Stereo Full-Bridge P

Mono Parallel Full-Bridge PO = -60 dBFS, A-Weighted

VP =2.5 V
Power Output per Channel P

Stereo Full-Bridge THD+N < 10%

Mono Parallel Full-Bridge THD+N < 10%

Total Harmonic Distortion + Noise THD+N

Stereo Full-Bridge P

Mono Parallel Full-Bridge PO = -3 dBFS = 0.17 W

Dynamic Range DR

Stereo Full-Bridge P

Mono Parallel Full-Bridge P

MOSFET On Resistance R

O

O

O

DS(ON)

P

= -60 dBFS, A-Weighted

O

PO = -60 dBFS, Unweighted

= -60 dBFS, A-Weighted

O

PO = -60 dBFS, Unweighted

PO = 0 dBFS = 0.81 W

= -60 dBFS, A-Weighted

O

= -60 dBFS, Unweighted

P

O

= -60 dBFS, Unweighted

P

O

P

= -60 dBFS, A-Weighted

O

PO = -60 dBFS, Unweighted

= -60 dBFS, A-Weighted

O

PO = -60 dBFS, Unweighted

= 8 for stereo full-bridge, RL = 4 for mono parallel

L

-

1.00

THD+N < 1%

THD+N < 1%

= 0 dBFS = 0.8W - 0.52 - %

O

= 0 dBFS = 1.5 W

O

THD+N < 1%

THD+N < 1%

= 0 dBFS = 0.43 W - 0.54 - %

O

= -3 dBFS = 0.41 W

O

THD+N < 1%

THD+N < 1%

= 0 dBFS = 0.18 W - 0.50 - %

O

= 0 dBFS = 0.35 W

O

-

0.80

-

1.90

-

1.50

-

0.10

-

0.50

-

91

-

88

-

91

-

88

-

0.55

-

0.45

-

1.00

-

0.84

-

0.09

-

0.45

-

91

-

88

-

95

-

92

-

0.23

-

0.19

-

0.44

-

0.35

-

0.08

-

0.43

-

91

-

88

-

94

-

91

--W
W

--W
W

-

-

-

-

-

-

--W
W

--W
W

-

-

-

-

-

-

--W
W

--W
W

-

-

-

-

-

-

rms
rms

rms
rms

%
%

dB
dB

dB
dB

rms
rms

rms
rms

%
%

dB
dB

dB
dB

rms
rms

rms
rms

%
%

dB
dB

dB
dB

VP = 5.0V, Id = 0.5 A - 600 - m

DS680F2 17

3/1/13

AOUTx

AGND

R

L

C

L

0.022 F

51 

Figure 2. Headphone Output Test Load

CS42L52

Parameters (Note 10) Symbol Conditions Min Typ Max Units

MOSFET On Resistance R
MOSFET On Resistance R

DS(ON)
DS(ON)

Efficiency  VP = 5.0 V, P
Output Operating Peak Current I
VP Input Current During Reset I

PC
VP

VP = 3.7V, Id = 0.5 A - 640 - m
VP = 2.5V, Id = 0.5 A - 760 - m

= 2 x 0.8 W, RL = 8  -81-%

O

--1.5A

RESET, pin 32, is held low

-0.85.0µA

9. The PWM driver should be used in captive speaker systems only.

10. Optimal PWM performance is achieved when MCLK > 12 MHz.

HEADPHONE OUTPUT POWER CHARACTERISTICS

Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; Sample Frequency = 48 kHz;
Measurement Bandwidth is 20 Hz to 20 kHz; Test load RL = 16  CL = 10 pF (see Figure 2); “Required Initialization Settings”

on page 37 written on power up.

Parameters VA = 2.5V

AOUTx Power Into R

= 16

L



Min Typ Max

Min Typ Max

VA = 1.8V

Unit

HP_GAIN[2:0] Analog Gain (G) VHP

000 0.3959 1.8 V - 14 - - 7 - mW

2.5 V - 14 - - 7 - mW

001 0.4571 1.8 V - 19 - - 10 - mW

2.5 V - 19 - - 10 - mW

010 0.5111 1.8 V - 23 - - 12 - mW

2.5 V - 23 - - 12 - mW

011 (default) 0.6047 1.8 V (Note 11) -17 -mW

2.5 V - 32 - - 17 - mW

100 0.7099 1.8 V (Note 11) -23 -mW

2.5 V - 44 - - 23 - mW

101 0.8399 1.8 V (Note 7), Figure 22 on page 74 mW

2.5 V -32 -mW

110 1.0000 1.8 V (Note 7, 11) See Figures 22 an d 23 on page 74 mW

2.5 V mW

111 1.1430 1.8 V mW

2.5 V mW

rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms
rms

11. VHP settings lower than VA reduces the headroom of the headphone amplifier. As a result, the DAC
may not achieve the full THD+N performance at full-scale output voltage and power.

18 DS680F2

3/1/13

CS42L52

LINE OUTPUT VOLTAGE LEVEL CHARACTERISTICS

Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 20 Hz
to 20 kHz; Sample Frequency = 48 kHz; Test load R

page 37 written on power up.

Parameters VA = 2.5V

AOUTx Voltage Into RL = 10 k

HP_GAIN[2:0] Analog

Gain (G)

000 0.3959 1.8 V - 1.34 - - 0.97 - V

001 0.4571 1.8 V - 1.55 - - 1.12 - V

010 0.5111 1.8 V - 1.73 - - 1.25 - V

011 (default) 0.6047 1.8 V - 2.05 - 1.41 1.48 1.55 V

100 0.7099 1.8 V - 2.41 - - 1.73 - V

101 0.8399 1.8 V - 2.85 - 2.05 V

1 1 0 1.0000 1.8 V - 3.39 - - 2.44 - V

111 1.1430 1.8 V (See (Note 11) -2.79-V



VHP

2.5 V - 1.34 - - 0.97 - V

2.5 V - 1.55 - - 1.12 - V

2.5 V - 1.73 - - 1.25 - V

2.5 V 1.95 2.05 2.15 - 1.48 - V

2.5 V - 2.41 - - 1.73 - V

2.5 V - 2.85 - - 2.05 - V

2.5 V - 3.39 - - 2.44 - V

2.5 V - 3.88 - - 2.79 - V

= 10 k CL = 10 pF (see Figure 2); “Required Initialization Settings” on

L

Min Typ Max

VA = 1.8V

Min Typ Max

Unit

pp
pp
pp
pp
pp
pp
pp
pp
pp
pp
pp
pp
pp
pp
pp
pp

COMBINED DAC INTERPOLATION AND ONCHIP ANALOG FILTER RESPONSE

Parameters (Note 12) Min Typ Max Unit

Frequency Response 10 Hz to 20 kHz -0.01 - +0.08 dB
Passband to -0.05 dB corner

to -3 dB corner
StopBand 0.5465 - - Fs
StopBand Attenuation (Note 13) 50 - - dB
Group Delay - 9/Fs - s
De-emphasis Error Fs = 32 kHz

Fs = 44.1 kHz

Fs = 48 kHz

12. Response is clock dependent and scales with Fs. Note that the response plots (Figures 30 and 33 on

page 78) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

13. Measurement Bandwidth is from Stopband to 3 Fs.

0
0

-

-

-

-

-

-

-

-

0.4780

0.4996

+1.5/+0

+0.05/-0.25

-0.2/-0.4

Fs
Fs

dB
dB
dB

DS680F2 19

3/1/13

t

h(SK-SDO)

//

//

//

//

//

//

//

//

t

s(SD-SK)

MSB

MSB

MSB-1

MSB-1

LRCK

SCLK

SDOUT

SDIN

t

d(MSB)

t

s(LK-SK)

t

P

t

h

t

s(SDO-SK)

Figure 3. Serial Audio Interface Timing

SWITCHING SPECIFICATIONS - SERIAL PORT

Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT C

Parameters Symbol Min Max Units

RESET

MCLK Frequency (Note 15)
MCLK Duty Cycle

pin Low Pulse Width (Note 14)

Slave Mode

Input Sample Rate (LRCK)
LRCK Duty Cycle

SCLK Frequency
SCLK Duty Cycle
LRCK Setup Time Before SCLK Rising Edge
LRCK Edge to SDOUT MSB Output Delay
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge

Master Mode

Output Sample Rate (LRCK) All Speed Modes

LRCK Duty Cycle
SCLK Frequency SCLK=MCLK mode

SCLK Duty Cycle
LRCK Edge to SDOUT MSB Output Delay
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge

14. After powering up the CS42L52, RESET should be held low after the power supplies and clocks are
settled.

15. See “Example System Clock Frequencies” on page 76 for typical MCLK frequencies.

LOAD

= 15 pF.

MCLK=12.0000 MHz

all other modes

F

s

1/t

P

t

s(LK-SK)

t

d(MSB)

t

s(SDO-SK)

t

h(SK-SDO)

t

s(SD-SK)

t

h

F

s

1/t

P

1/t

P

1/t

P

t

d(MSB)

t

s(SDO-SK)

t

h(SK-SDO)

t

s(SD-SK)

t

h

CS42L52

1-ms

(See “Serial Port Clock-

ing” on page 33)

45 55 %

(See “Serial Port Clock-

ing” on page 33)

45 55 %

-64•FsHz
45 55 %
40 - ns

-52ns
20 - ns
30 - ns
20 - ns
20 - ns

(See “Serial Port Clock-

ing” on page 33)

45 55 %

- 12.0000 MHz

-68•FsHz

-64•FsHz
45 55 %

-52ns
20 - ns
30 - ns
20 - ns
20 - ns

MHz

kHz

Hz

20 DS680F2

3/1/13

t

buf

t

hdst

t

hdst

t

low

t

r

t

f

t

hdd

t

high

t

sud

t

sust

t

susp

Stop Start

Start

Stop

Repeated

SDA

SCL

t

irs

RST

Figure 4. Control Port Timing - I²C

SWITCHING SPECIFICATIONS - I²C CONTROL PORT

Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL=30pF.

Parameters Symbol Min Max Unit

SCL Clock Frequency

RESET Rising Edge to Start

Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 16)
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling

16. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

f
t

t

t

hdst

t

low

t

high

t

sust

t

hdd

t

sud

t
t

t

susp

t

ack

scl
irs

buf

rc
fc

CS42L52

- 100 kHz

550 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs
0-µs

250 - ns

-1µs

- 300 ns

4.7 - µs

300 1000 ns

DS680F2 21

3/1/13

CS42L52

DC ELECTRICAL CHARACTERISTICS

AGND = 0 V; All voltages with respect to ground.

Parameters Min Typ Max Units

VQ Characteristics

Nominal Voltage
Output Impedance
DC Current Source/Sink

MIC BIAS Characteristics

Nominal Voltage BIASLVL[2:0] = 000

BIASLVL[2:0] = 001
BIASLVL[2:0] = 010
BIASLVL[2:0] = 011
BIASLVL[2:0] = 100

BIASLVL[2:0] = 101
DC Output Current
Power Supply Rejection Ratio (PSRR) 1 kHz

Power Supply Rejection Ratio Characteristics

PSRR @1 kHz (Note 17) PGA to ADC

ADC

DAC (HP and Line Amps)

PSRR @60 Hz (Note 17) PGA to ADC

DAC (HP and Line Amps)

PSRR @217 Hz Full-Bridge PWM Outputs - 56 - dB

(Note 18)

ADC

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

0.5•VA
23

-

0.5•VA

0.6•VA

0.7•VA

0.8•VA

0.83•VA

0.91•VA

-

50

44
60
60

22
42
60

-

-

1

-

-

-

-

-

-

1

-

-

-

-

-

-

-

V
k
A

V

V

V

V

V

V

mA

dB

dB
dB
dB

dB
dB
dB

17. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also
increase the PSRR.

18. The PGA is biased with VQ, created from a resistor divider from the VA supply. Increasing the capaci­tance on VQ will also increase the PSRR at low frequencies. A 10 µF capacitor on VQ improves the
PSRR to 42 dB.

DIGITAL INTERFACE SPECIFICATIONS AND CHARACTERISTICS

Parameters (Note 19) Symbol Min Max Units

Input Leakage Current I
Input Capacitance -10pF

1.8 V - 3.3 V Logic

High-Level Output Voltage (I
Low-Level Output Voltage (I
High-Level Input Voltage VL = 1.65 V

Low-Level Input Voltage V

= -100 A) V

OH

= 100 A) V

OL

VL = 1.8 V
VL = 2.0 V
VL > 2.0 V

in

OH

OL

V

IH

IL

19. See “I/O Pin Characteristics” on page 10 for serial and control port power rails.

-±10A

VL - 0.2 - V

-0.2V

0.85•VL

0.77•VL

0.68•VL

0.65•VL

- 0.30•VL V

-

-

-

-

V
V
V
V

22 DS680F2

3/1/13

POWER CONSUMPTION See (Note 20).

Power Ctl. Registers Typical Current (mA)

Operation

1

Off (Note 21)

Standby (Note 22) xxxx1xxxx x x x

2

Mono Record ADC 1 110011111111111

3

PGA to ADC1010011111111111

MIC to PGA to ADC

MIC to PGA to ADC

Stereo Record ADC1100011111111111

4

MIC to PGA to ADC

Mono Playback to Headphone 1 111011110111111

5

Mono Playback to Speaker 1 111011111111010

6

Stereo Playback to Headphone 1 111011110101111

7

Stereo Playback to Speaker 1111011111111010

8

Stereo Passthrough to Head-

9

phone
Mono Record and Playback

10

PGA in (no MIC) to Mono HP
Phone Monitor

11

MIC (w/bias) in to Mono Out
Stereo Record and Playback

12

PGA in (no MIC) to St. HP Out
Stereo Rec. and Full Playback

13

PGA (no MIC) to St. HP and SPK

(with Bias)

(no Bias)

PGA to ADC0000011111111111

(no Bias)

02h 03h 04h

PDN_PGAB

PDN_PGAA

PDN_ADCB

PDN_ADCA

PDN

PDN_MICB

PDN_MICA

PDN_MICBIAS

PDN_HPB[1:0]

xxxxxxxxx x x x

1010010011111111

1010010111111111

0000000111111111

1111011110101111

1010011111101111

1010010011101111

0000011110101111

0000011110101010

PDN_HPA[1:0]

i

VHPiVA

PDN_SPKB[1:0]

PDN_SPKA[1:0]

V

1.8 0.00 0.00 0.00

2.5 0.00 0.00 0.00 0.00

1.8 0.00 0.00 0.01

2.5 0.00 0.00 0.02 0.05

1.8 0.00 1.67 2.32

2.5 0.00 1.87 3.72 14.05

1.8 0.00 2.1 2.31

2.5 0.00 2.3 3.72 15.13

1.8 0.00 3.48 2.32

2.5 0.00 3.71 3.72 18.65

1.8 0.00 3.15 2.32

2.5 0.00 3.37 3.73 17.83

1.8 0.00 2.31 2.37

2.5 0.00 2.53 3.82 15.95

1.8 0.00 3.18 2.37

2.5 0.00 3.42 3.81 18.15

1.8 0.00 5.32 2.37

2.5 0.00 5.57 3.81 23.53

1.8 1.59 1.99 2.72

2.5 2.07 2.62 4.27 22.43

1.8 0.00 0.20 4.42

2.5 0.00 0.22 6.77 21.21

1.8 2.77 2.00 2.91

2.5 3.27 2.63 4.28 25.48

1.8 0.00 0.20 4.38

2.5 0.00 0.22 6.80 21.28

1.8 2.79 1.91 1.06

2.5 3.18 2.14 1.81 17.85

1.8 1.77 3.95 4.28

2.5 2.13 4.77 6.63 33.90

1.8 1.76 5.33 4.28

2.5 2.15 6.19 6.69 37.65

1.8 2.76 5.05 4.64

2.5 3.21 5.90 7.17 40.78

1.8 3.49 5.24 7.20

2.5 3.95 6.10 10.46 55.07

i

VD

i

VL

VL=3.3V

(Note 23)

0.00 0.00

0.00 0.00

0.03 0.00

0.03 0.00

0.03 0.00

0.03 0.00

0.03 0.00

0.03 0.00

0.03 0.00

0.01 0.00

0.01 1.00

0.01 0.00

0.01 1.00

0.01 0.00

0.03 0.00

0.03 0.00

0.03 0.00

0.03 1.00

CS42L52

i

VP

VP=3.7V

Total

Power

(mW

0.00

0.02

7.24

7.99

10.49

9.90

8.48

10.04

13.90

11.36

12.05

13.84

11.98

10.39

18.05

20.52

22.46

32.47

rms

)

20. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample
rate = 48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode
and master/slave operation. “Required Initialization Settings” on page 37 written on power up.

21. RESET

22. RESET

pin 25 held LO, all clocks and data lines are held LO.
pin 25 held HI, all clocks and data lines are held HI.

23. VL current will slightly increase in master mode.

DS680F2 23

4. APPLICATIONS

4.1 Overview

4.1.1 Basic Architecture

The CS42L52 is a highly integrated, low-power, 24-bit audio CODEC comprised of a stereo analog-to­digital converter (ADC), a stereo digital-to-analog converter (DAC), a digital PWM modulator and two full­bridge power back-ends. The ADC and DAC are designed using multibit delta-sigma techniques - the
DAC operates at an oversampling ratio of 128Fs and the ADC oper ates at 64Fs, where Fs is equal to the
system sample rate.

The different clock rates maximize power savings while maintaining high performance. The PWM modu­lator operates at a fixed frequency of 384 kHz. The power FETs are configure d for either stereo full-bridge
or mono parallel full-bridge output. The CODEC operates in one of four sample rate speed modes: Quar ­ter, Half, Single, and Double. It accepts and is capable of generating serial port clocks (SCLK, LRCK) de­rived from an input Master Clock (MCLK).

4.1.2 Line and MIC Inputs

The analog input portion of the CODEC allows selection from and configuration of multiple combinations
of stereo and microphone (MIC) sources. Eight line inputs with an option for two balanced MIC inputs, a
MIC bias output, and a Programmable Gain Amplifier (PGA) comprise the analog front- end.

3/1/13

CS42L52

4.1.3 Line and Headphone Outputs

The analog output portion of the CODEC includes a headphone amplifier capable of driving headphone
and line-level loads. An on-chip charge pump creates a negative headphone supply allowing a full-scale
output swing centered around groun d. Th is elim in at es the need for large DC-Blocking capacitors and al­lows the amplifier to deliver more power to headphone loads at lower supply voltages.

4.1.4 Speaker Driver Outputs

The Class D power amplifiers drive 8 ohm (stereo) and 4 ohm (mono ) speakers d irectly, without the ne ed
for an external filter. The power MOSFETS are powered directly from a battery eliminating the efficiency
loss associated with an external regulator. Battery level monitoring and compensation maintains a stead y
output as battery levels fall. NOTE: The CS42L52 should only be used in captive speaker systems where
the outputs are permanently tied to the speaker terminals.

4.1.5 Fixed Function DSP Engine

The fixed-function digital signal processing engine processes both the PCM serial input data and ADC
output data, allowing a mix between the two. Independent volume control, le ft/right channel swaps, mono
mixes, tone control, and limiting functions also comprise the DSP engine.

4.1.6 Beep Generator

The beep generator delivers tones at select frequencies across approximately two octave major scales.
With independent volume control, beeps may be configured to occur continuously, perio dically, or at sin­gle time intervals.

4.1.7 Power Management

Three control registers provide independent power-down control of the ADC, DAC, PGA, MIC pre-amp,
MIC bias, Headphone, and Speaker outputs, allowing operation in select applications with minimal power
consumption.

24 DS680F2

4.2 Analog Inputs

`

AIN4A/ MIC1+/
MIC2A

Gain A d jus t

ALC

PDN_PGAA
PGAA VOL[5:0]
ADCB=A
ANLGSFTA
ANLGZCA

HPFRZA
HPFA
HPFA_CF[1:0]

PDN_ADCA
INV_ADCA
PDN_CHRG

ALCB
ALCBSRDIS
ALCBZCDIS

MICBIAS

BIASLVL[2:0]
PDN_BIAS

PCM Serial Interface

TO DSP Engine

ALCARATE[5:0]
ALCRRATE[5:0]

MAX[2:0]

MIN[2:0]

ALCA
ALCASRDIS
ALCAZCDIS

AIN1A
AIN2A

= PGAASEL[5:1]

ADC

PDN_PGAB
PGAB VOL[5:0]
ADCB=A
ANLGSFTB
ANLGZCB

ADCBMUTE
DIGSFT
DIGZC
ADCBVOL[7:0]
+24/-96dB
1dB steps

HPFRZB
HPB
HPFB_CF[1:0]

PDN_ADCB
INV_ADCB
PDN_CHRG

Noise Gate

NGALL
NG
THRESH[3:0 ]
NGDELAY[1:0]

Gain Adjust

FROM DSP ENGINE

DIGMIX

AIN3A/MIC1-/
MIC1A

AIN4B/ MIC2+/
MIC2B

AIN1B

AIN2B

AIN3B/MIC2-/
MIC1B

ANALOG PASS THRU TO
HEADPHONE AMPLIFIER MU X

Swap/

Mix

DIGSUM[1:0]

ADCAMUTE
DIGSFT
DIGZC
ADCAVOL[7:0]
+24/-96dB
1dB steps

Refer to

“MIC Inp uts ”

ADC



ADCASEL[2:0]

ADCBSEL[2:0]

= PGABSEL[5:1]

Refer to

“MIC Inp uts ”



Figure 5. Analog Input Signal Flow

3/1/13

CS42L52

Referenced Control Register Location

Analog Front End

PDN_PGAx .........................

PGAxVOL[5:0].....................

ADCB=A..............................

ANLGSFTx..........................

ANLGZCx............................

ADCxSEL[2:0].....................

PGAxSEL5,4,3,2,1..............

BIASLVL[2:0].......................

PDN_BIAS...........................

PDN_ADCx .........................

PDN_CHRG........................

INV_ADCx...........................

HPFRZx...............................

HPFx ...................................

HPFx_CF[1:0]......................

ADCxOVFL..........................

Digital Volume

ADCxMUTE.........................

ADCxVOL............................

ALCx....................................

ALCxSRDIS.........................

ALCxZCDIS.........................

ALCARATE[5:0]...................

ALCRRATE[5:0]..................

MAX[2:0]..............................

MIN[2:0]...............................

NGALL.................................

NG.......................................

THRESH[3:0].......................

NGDELAY[1:0]....................

Miscellaneous

DIGSUM[1:0].......................

DIGMUX..............................

DS680F2 25

“Power Down PGAx” on page 42
“PGAx Volume” on page 56
“Analog Front-End Volume Setting B=A” on page 50
“Ch. x Analog Soft Ramp” on page 49
“Ch. x Analog Zero Cross” on page 49
“ADC Input Select” on page 48
“PGA Input Mapping” on page 49
“MIC Bias Level” on page 48
“Power Down MIC Bias” on page 43
“Power Down ADCx” on page 43
“Power Down ADC Charge Pump” on page 42
“Invert ADC Signal Polarity” on page 51
“ADCx High-Pass Filter Freeze” on page 49
“ADCx High-Pass Filter” on page 49
“HPF x Corner Frequency” on page 50
“ADCx Overflow (Read Only)” on page 71

“ADC Mute” on page 51
“ADCx Volume” on page 57
“ALCx Enable” on page 67
“ALCx Soft Ramp Disable” on page 55
“ALCx Zero Cross Disable” on page 56
“ALC Attack Rate” on page 67
“ALC Release Rate” on page 68
“ALC Maximum Threshold” on page 68
“ALC Minimum Threshold” on page 69
“Noise Gate All Channels” on page 69
“Noise Gate Enable” on page 69
“Noise Gate Threshold and Boost” on page 70
“Noise Gate Delay Timing” on page 70

“Digital Sum” on page 50
“Digital MUX” on page 50