Cirrus Logic CS4270 User Manual

Internal Voltage

Reference

Software or Stand-Alone

Configuration

Analog Out A

(Left) PCM Ser ial Audio Input

Volume Control

ADC

Digital

Filter

Multi- bit

Modulator

External Mute

Control

Mute Signals

PCM Ser ial

Audio Output

Configuration

Registers

Serial Audio

Input

Level

Translators

Volume Control

Serial Audio

Output

High Pass

Filter

High Pass

Filter

Multi- bit

Modulator

ADC

Digital

Filter

Switch -Cap

DAC and

Analog Filter

Switch -Cap

DAC and

Analog Filter

____ RST

VLC

1.8 V to 5 V

Switch-Cap

ADC

Switch-Cap

ADC

DAC

Digital

Filter

DAC

Digital

Filter

3.3 V to 5 V

Analog Out B

(Right)

Analog Input A

(Left)

Analog Input B

(Right)

CS4270

24-Bit, 192-kHz Stereo Audio CODEC

D/A Features

 High Performance

– 105 dB Dynamic Range

– -87 dB THD+N

 Selectable Serial Audio Interface Formats

– Left-Justified up to 24 bits – I²S up to 24 bits – Right-Justified 16, and 24 bits

 Control Output for External Muting

 Digital De-Emphasis

 Popguard

 Multi-bit  Conversion

 Digital Volume Control

 Single-Ended Output

Technology

A/D Features

 High Performance

– 105 dB Dynamic Range – -95 dB THD+N

 Multi-bit Conversion



High-Pass Filter to Remove DC Offsets

 Selectable Serial Audio Interface Formats

– Left-Justified up to 24 bits – I²S up to 24 bits

 Single-Ended Input

System Features

 Direct Interface with Logic Levels 1.8 V to 5 V

 Internal Digital Loopback

 Stand-Alone or Serial Control Port Functionality

 Single-Ended Analog Architecture

 Supports all Audio Sample Rates from 4 kHz to

216 kHz

 3.3- or 5-V Core Supply

http://www.cirrus.com

AUGUST '10

DS686F1

CS4270

Stand-Alone Mode Feature Set

 System Features

– Master or Slave Serial Audio Interface

– Single-, Double-, or Quad-Speed Operation



D/A Features

– Auto-Mute on Static Samples

– 44.1 kHz 50/15 s De-emphasis Available

– Selectable Serial Audio Interface Formats

• Left-Justified up to 24-bit

• I²S up to 24-bit



A/D Features

– High-Pass Filter

– Selectable Serial Audio Interface Formats

• Left-Justified up to 24-bit

• I²S up to 24-bit

Software Mode Feature Set

 System Features

– Master or Slave Serial Audio Interface

– Single-, Double-, or Quad-Speed Operation

– Internal Digital Loopback Available

General Description

The CS4270 is a high-performance, integrated audio CODEC. The CS4270 performs stereo analog-to-digital (A/D) and digital-to-analog (D/A) conversion of up to 24-bit serial values at sample rates up to 216 kHz.

Standard 50/15 s de-emphasis is available for sampling rates of 44.1 kHz for compatibility with digital audio programs mastered using the 50/15 s pre-emphasis technique.

Integrated level translators allow easy interfacing between the CS4270 and other devices operating over a wide range of logic levels.

Independently addressable high-pass filters are available for the right and left channel of the A/D. This allows the A/D to be used in a wide variety of applications where one audio channel and one DC measurement channel is desired.

The CS4270 is available in a 24-pin TSSOP package (-10° to +70° C). The CDB4270 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to “Ordering

Information” on page 44 for complete ordering

information.

The CS4270’s wide dynamic range, negligible distortion, and low noise make it ideal for applications such as DVD recorders, digital televisions, set-top boxes, and effects processors.



D/A Features

– Selectable Auto-mute

– 44.1-kHz 50/15 s De-emphasis Available

– Configurable Muting Controls

– Volume Control

– Selectable Serial Audio Interface Formats

• Left-Justified up to 24-bit

• I²S up to 24-bit

• Right-Justified 16, and 24-bit



A/D Features

– Selectable High-Pass Filter or DC Offset

Calibration

– Selectable Serial Audio Interface Formats

• Left-Justified up to 24-bit

• I²S up to 24-bit

2 DS686F1

TABLE OF CONTENTS

1. PIN DESCRIPTIONS .............................................................................................................................. 4

1.1 Software Mode ................................................................................................................................ 4

1.2 Stand-Alone Mode ........................................................................................................................... 5

2. DIGITAL I/O PIN CHARACTERISTICS .................................................................................................. 6

3. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 7

4. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8

SPECIFIED OPERATING CONDITIONS ............................................................................................... 8

ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 8

DAC ANALOG CHARACTERISTICS .....................................................................................................9

DAC COMBINED INTERPOLATION & ANALOG FILTER RESPONSE .............................................. 10

ADC ANALOG CHARACTERISTICS ................................................................................................... 11

ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 12

DC ELECTRICAL CHARACTERISTICS .............................................................................................. 13

DIGITAL SWITCHING CHARACTERISTICS ....................................................................................... 13

SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE .................................................... 14

SWITCHING CHARACTERISTICS - SOFTWARE MODE - I²C FORMAT ........................................... 17

SWITCHING CHARACTERISTICS - SOFTWARE MODE - SPI FORMAT .......................................... 18

5. APPLICATIONS ................................................................................................................................... 19

5.1 Stand-Alone Mode ......................................................................................................................... 19

5.2 Serial Control Port Mode ............................................................................................................... 21

5.3 Popguard Transient Control .......................................................................................................... 24

5.4 De-Emphasis Filter (Single-Speed Mode Only) ............................................................................ 24

5.5 Analog Connections ...................................................................................................................... 25

5.6 Mute Control .................................................................................................................................. 27

5.7 Synchronization of Multiple Devices .............................................................................................. 28

5.8 Grounding and Power Supply Decoupling .................................................................................... 28

6. SOFTWARE MODE .............................................................................................................................. 28

6.1 Software Mode - I²C Control Port .................................................................................................. 28

6.2 Software Mode - SPI Control Port ................................................................................................. 29

7. REGISTER QUICK REFERENCE ........................................................................................................ 31

8. REGISTER DESCRIPTION .................................................................................................................. 32

8.1 Device ID - Address 01h ............................................................................................................... 32

8.2 Power Control - Address 02h ........................................................................................................ 32

8.3 Mode Control - Address 03h ......................................................................................................... 33

8.4 ADC and DAC Control - Address 04h ........................................................................................... 34

8.5 Transition Control - Address 05h ................................................................................................... 35

8.6 Mute Control - Address 06h .......................................................................................................... 36

8.7 DAC Channel A Volume Control - Address 07h ............................................................................ 36

8.8 DAC Channel B Volume Control - Address 08h ............................................................................ 37

9. FILTER PLOTS ................................................................................................................................ 38

10. PARAMETER DEFINITIONS .............................................................................................................. 42

11. PACKAGE DIMENSIONS .................................................................................................................. 43

THERMAL CHARACTERISTICS .......................................................................................................... 43

12. ORDERING INFORMATION .............................................................................................................. 44

13. REVISION HISTORY .......................................................................................................................... 44

CS4270

DS686F1 3

SDIN

LRCK

MCLK

SCLK

DGND

SDOUT

VLC

SDA/CDOUT

SCL/CCLK

AD0/CS

AD1/CDIN

MUTEB AOUTB AOUTA MUTEA AGND VA FILT+ VQ AINB AINA RST AD2

CS4270

1. PIN DESCRIPTIONS

1.1 Software Mode

Pin Name # Pin Description

SDIN 1 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

LRCK 2

MCLK 3 Master Clock (Input) - Clock for the delta-sigma modulator and the digital filters.

SCLK 4 Serial Bit Clock (Input/Output) - Serial bit clock for the serial audio interface.

VD 5 Digital Power (Input) - Positive power for the digital section.

DGND 6 Digital Ground (Input) - Ground reference for the digital section.

SDOUT 7 Serial Audio Data Output (Output) - Output for two’s complement serial audio data.

VLC 8 Serial Control Port Power (Input) - Positive power for the Serial Control Port.

SDA/CDOUT 9

SCL/CCLK 10

AD0/CS

AD1/CDIN 12

AD2 13 Address Bit 2 (I²C) (Input) - AD2 is a chip address pin in I²C format.

RST

AINA AINB

VQ 17 Quiescent Voltage (Output) - Filter connection for the internal quiescent voltage.

FILT+ 18 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

VA 19 Analog Power (Input) - Positive power for the analog section.

AGND 20 Analog Ground (Input) - Ground reference for the analog section.

MUTEA MUTEB

AOUTA AOUTB

4 DS686F1

Left Right Clock (Input/Output) - Determines which channel, left or right, is currently active on the serial audio

data line. The frequency of the left/right clock must be at the audio sample rate, Fs.

Serial Control Data (Input/Output) - SDA is a data I/O line in I²C Mode. CDOUT is the output data line for the Serial Control Port in SPI format.

Serial Control Port Clock (Input) - SCL is the serial input Clock for the Serial Control Port in I²C format. CCLK is the serial input Clock for the Serial Control Port in SPI format.

Address Bit 0 (I²C)/Serial Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C format.

CS is the chip select signal for SPI format.

Address Bit 1 (I²C)/Serial Control Data (Input) - AD1 is a chip address pin in I²C Mode. CDIN is the input data line for the Serial Control Port in SPI

Reset (Input) - Input for resetting all internal registers to their default settings and for placing the device in a

low-power mode.

Analog Audio Input (Input) - Analog inputs to the ADC.

2124Mute Control (Output) - Mute control signal used to control the state of the optional external analog muting

22 23

circuitry. See Section 5.6 on page 27.

Analog Audio Output (Output) - Analog outputs from the DAC.

format.

1.2 Stand-Alone Mode

SDIN

LRCK

MCLK

SCLK

DGND

SDOUT

VLC

M1 M0

I²S/LJ

MDIV1

MUTEB AOUTB AOUTA MUTEA AGND VA FILT+ VQ AINB AINA RST MDIV2

Pin Name # Pin Description

SDIN 1 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

LRCK 2

MCLK 3 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serialaudio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.

CS4270

SCLK 4 Serial Bit Clock (Input/Output) - Serial bit clock for the serial audio interface.

VD 5 Digital Power (Input) - Positive power for the digital section.

DGND 6 Digital Ground (Input) - Ground reference for the digital section.

SDOUT

)

(M/S

VLC 8 Serial Control Port Power (Input) - Positive power for the Serial Control Port.

M1 M0

I²S/LJ

MDIV1 MDIV2

RST

AINA AINB

VQ 17 Quiescent Voltage (Output) - Filter connection for the internal quiescent voltage

FILT+ 18 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

VA 19 Analog Power (Input) - Positive power for the analog section.

AGND 20 Analog Ground (Input) - Ground reference for the analog section.

MUTEA MUTEB

AOUTA AOUTB

DS686F1 5

Serial Audio Data Output (Output) - Output for two’s complement serial audio data. This pin must be

pulled up or down through a 47-k resistor to select Master or Slave Mode.

Mode Selection (Input) - Determines the system sampling frequency range of the device.

Serial Audio Interface Select (Input) - Selects either the Left-Justified or

Interface.

MCLK Divide (Input) - Configures the device to divide MCLK by 1, 1.5, 2, or 4.

Reset (Input) - Input for resetting all internal registers to their default settings and for placing the device

in a low-power mode.

Analog Input (Input) - Analog inputs to the ADC.

2124Mute Control (Output) - Mute control signal used to control the state of the optional external analog mut-

ing circuitry. See Section 5.6 on page 27.

Analog Audio Output (Output) - Analog outputs for the DAC.

I²S format for the Serial Audio

CS4270

2. DIGITAL I/O PIN CHARACTERISTICS

The level for each input is set by its corresponding power supply and should not exceed the maximum ratings.

Power

Supply

Number

Software Mode

9 SDA/CDOUT Input/Output 1.8 V-5.0 V, Open Drain 1.8 V-5.0 V, with hysteresis

10 SCL/CCLK Input - 1.8 V-5.0 V, with hysteresis

VLC

11 AD0/ CS Input - 1.8 V-5.0 V

12 AD1/CDIN Input - 1.8 V-5.0 V

13 AD2 Input - 1.8 V-5.0 V

Stand-Alone Mode

9 M1 Input - 1.8 V-5.0 V

10 M0 Input - 1.8 V-5.0 V

VLC

11 I²S /LJ Input - 1.8 V-5.0 V

12 MDIV1 Input - 1.8 V-5.0 V

13 MDIV2 Input - 1.8 V-5.0 V

All Modes

1 SDIN Input - 3.3 V-5.0 V

2 LRCK Input/Output 3.3 V-5.0 V, CMOS 3.3 V-5.0 V

3 MCLK Input - 3.3 V-5.0 V

4 SCLK Input/Output 3.3 V-5.0 V, CMOS 3.3 V-5.0 V

7 SDOUT Output 3.3 V-5.0 V, CMOS -

14 RST

21 MUTEA Output 3.3 V-5.0 V, CMOS -

24 MUTEB

Pin Name I/O Driver Receiver

Input - 1.8 V-5.0 V

Output 3.3 V-5.0 V, CMOS -

Table 1. Digital I/O Pin Power Rails

6 DS686F1

3. TYPICAL CONNECTION DIAGRAM

Figure 1. CS4270 Typical Connection Diagram

CS (I2S/LJ) /AD0 SDA/CDOUT (M1)

SCL/CCLK (M0)

AINA

AINB

RST

Power

Down

and Mode

Settings

(Control Port)

AOUTA

MUTEA

AOUTB

MUTEB

Analog Output

Network

and Mute

LRCK

SCLK

MCLK

Timing Logic

and

Clocks

SDIN

)S(M/SDOUT

Audio Data

Processor

DGND

FILT+

AGND

+3.3 V to 5 V

CS4270

GND or VD

47 k

5.1

Analog Input

Network

47 µF 0.1 µF

10 µF

0.1 µF

1 µF0.1 µF

1 µF

If using separate supplies for VA and VD, 5.1 resistor not

needed. See "Grounding and Power Supply Decoupling."

VLC

+1.8 V to 5 V

Use pull-up resistors in Software Mode. In Stand-Alone Mode, use pull-up or pull-down. See "Mode Selection & De-Emphasis."

2 k



2 k

In Stand-Alone mode, use a 47 kO pull-down to select Slave Mode or 47 kO pull-up to VD to select Master Mode. See "Master/Slave Mode Selection."

AD1/CDIN (MDIV2)

AD2 (MDIV1)

0.1 µF

CS4270

DS686F1 7

4. CHARACTERISTICS AND SPECIFICATIONS

SPECIFIED OPERATING CONDITIONS

AGND = DGND= 0 V; all voltages with respect to ground.

Parameters Symbol Min Nom Max Units

DC Power Supplies: Analog

Digital

Serial Control Port

Ambient Operating Temperature (Power Applied) T

VA VD

VLC

ABSOLUTE MAXIMUM RATINGS

AGND = DGND = 0 V, All voltages with respect to ground.(Note 1)

Parameter Symbol Min Typ Max Units

DC Power Supplies: Analog

Digital

Serial Control Port

Input Current (Note 2) I

Analog Input Voltage V

Digital Input Voltage Serial Control Port

Digital

Ambient Operating Temperature (Power Applied) T

Storage Temperature T

VLC

V V

VA VD

IND-C IND-D

stg

CS4270

3.14

1.71

-40 - +85 C

-0.3

-10 - 10 mA

AGND-0.7 - VA+0.7 V

-0.3

-50 - +95 C

-65 - +150 C

5.0

3.3

5.25

+6.0 +6.0 +6.0

VLC+0.3

VD+0.3

V V V

V V

Notes: 1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not

guaranteed at these extremes.

2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up.

8 DS686F1

CS4270

AOUTx

AGND

3.3 µF

out

100

2.5

51015

Safe Operating

Region

Capacitive Load -- C (pF)

Resistive Load -- R (k)

125

Figure 2. Output Test Load Figure 3. Maximum Loading

DAC ANALOG CHARACTERISTICS

Test Conditions (unless otherwise specified): VD = VL = 3.3 V, AGND = DGND = 0 V; TA = +25° C; Full-Scale Output Sine Wave, 997 Hz (Note 3). Decoupling capacitors, filter capacitors, and recommended output filter as shown

in Figure 1 on page 7. Fs = 48/96/192 kHz; Synchronous Mode; Test load R Measurement Bandwidth 10 Hz to 20 kHz.

VA = 5 V VA = 3.3 V

Parameter Symbol

Dynamic Range 18 to 24 bit A-weighted

unweighted

16 Bit A-weighted

unweighted

Total Harmonic Distortion + Noise

18 to 24 bit 0 dB

-20 dB

-60 dB

16 Bit 0 dB

-20 dB

-60 dB

THD+N

99 96 90 87

105 102

96 93

-87

-82

-42

-85

-76

-36

DAC Performance across Full VA Range

Parameter Symbol Min Typ Max Unit

Interchannel Isolation (1 kHz) - 100 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 0.25 dB

Gain Drift -100 - +100 ppm/°C

Analog Output

Full Scale Output Voltage 0.6•VA 0.65•VA 0.7•VA Vpp

Max DC Current draw from AOUTA or AOUTB I

Max AC-Load Resistance (see Figure 3)R

Max Load Capacitance (see Figure 3)C

Output Impedance of AOUTA and AOUTB Z

OUTmax

OUT

-10-A

-3-k

-100-pF

-100-

= 3 k, CL = 10 pF (see Figure 2).

UnitMin Typ Max Min Typ Max

-83

-81

103

100

96 93

-83

-80

-40

-81

-76

-36

-79

-77

dB dB dB dB

dB dB dB

dB dB

Note: 3. One LSB of triangular PDF dither added to data.

DS686F1 9

CS4270

DAC COMBINED INTERPOLATION & ANALOG FILTER RESPONSE

The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. (See Note 4)

Parameter Symbol Min Typ Max Unit

Single-Speed Mode

Passband (Note 5) to -0.1 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz -.175 - +.01 dB

StopBand .5465 - - Fs

StopBand Attenuation (Note 6) 50 - - dB

Group Delay tgd - 10/Fs - s

De-emphasis Error (Note 8) Fs = 32 kHz

Fs = 44.1 kHz

Fs = 48 kHz

Double-Speed Mode

Passband (Note 5) to -0.1 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz -.15 - +.15 dB

StopBand .5770 - - Fs

StopBand Attenuation (Note 6) 55 - - dB

Group Delay tgd - 5/Fs - s

Quad-Speed Mode

Passband (Note 5) to -0.1 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz -.12 - +0 dB

StopBand 0.7 - - Fs

StopBand Attenuation (Note 6) 51 - - dB

Group Delay tgd - 2.5/Fs - s

0 0

.35

.4992

+1.5/+0

+.05/-.25

-.2/-.4

.22

.501

0.110

0.469

Fs Fs

dB dB dB

Fs Fs

Notes: 4. Amplitude vs. Frequency plots of this data are available in Section 9. “Filter Plots” on page 38. See

Figures 23 through 46.

5. Response is clock dependent and will scale with Fs.

6. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs. For Quad-Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs.

7. De-emphasis is available only in Single-Speed Mode.

10 DS686F1

CS4270

ADC ANALOG CHARACTERISTICS

Test Conditions (unless otherwise specified): VD = VL = 3.3 V, DGND = AGND = 0 V; TA = 25° C; 997 Hz Input Sine Wave. Figure 15 on page 26 shows the test circuit; Fs = 48/96/192 kHz; Synchronous Mode; Measurement

Bandwidth 10 Hz to 20 kHz.

Dynamic Performance

Single-Speed Mode Fs = 48 kHz

Dynamic Range A-weighted

unweighted

Total Harmonic Distortion + Noise (Note 8)

-1 dB

-20 dB

-60 dB

Double-Speed Mode Fs = 96 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

Total Harmonic Distortion + Noise (Note 8)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth unweighted Quad-Speed Mode Fs = 192 kHz Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 8)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

Symbol Min Typ Max Min Typ Max Unit

THD+N

Dynamic Performance - All Sampling Speed Modes

Parameter

Interchannel Isolation - 100 - dB DC Accuracy Interchannel Gain Mismatch - 0.1 - dB Gain Error -3 - +3 % Gain Drift - 100 - ppm/°C Analog Input Characteristics Full-Scale Input Voltage 0.53*VA 0.56*VA 0.58*VA Vpp Input Impedance - 300 - k

VA = 5 V VA = 3.3 V

9996105

102

-95

-82

-42

105

102

-95

-82

-42

-93

105

102

-95

-82

-42

-93

Min

9693102

-90

96 93

Typ M ax Uni t

-92

-79

-39

102

99 96

-92

-79

-39

-89

102

99 96

-92

-79

-39

-89

-87

dB dB

dB dB dB

dB dB dB dB

dB dB dB

dB dB dB dB

Note: 8. Referred to the typical full-scale input voltage.

DS686F1 11

CS4270

ADC DIGITAL FILTER CHARACTERISTICS

Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. (Note 9)

Parameter Symbol Min Typ Max Unit

Single-Speed Mode

Passband (-0.1 dB) (Note 10) 0-0.49Fs

Passband Ripple - - 0.035 dB

Stopband (Note 10) 0.57 - - Fs

Stopband Attenuation 70 - - dB

Group Delay t

Double-Speed Mode

Passband (-0.1 dB) (Note 10) 0-0.49Fs

Passband Ripple - - 0.05 dB

Stopband (Note 10) 0.56 - - Fs

Stopband Attenuation 69 - - dB

Group Delay t

Quad-Speed Mode

Passband (-0.1 dB) (Note 10) 0-0.26Fs

Passband Ripple - - 0.05 dB

Stopband (Note 10) 0.50 - - Fs

Stopband Attenuation 60 - - dB

Group Delay t

High-Pass Filter Characteristics

Frequency Response -3.0 dB

-0.13 dB (Note 11)

Phase Deviation @ 20 Hz (Note 11) - 10 - deg

Passband Ripple --0dB

- 12/Fs - s

-9/Fs- s

-5/Fs- s

Hz Hz

Notes: 9. Plots of this data are contained in Section 9. “Filter Plots” on page 38. See Figures 23 through 46.

10. The filter frequency response scales precisely with Fs.

11. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.

12 DS686F1

CS4270

DC ELECTRICAL CHARACTERISTICS

TA = 25° C; AGND = DGND = 0 V, all voltages with respect to 0 V; MCLK = 12.288 MHz; Master Mode).

Parameter Symbol Min Typ Max Unit

Power Supply

Power Supply Current VA = 5 V (Normal Operation) VA = 3.3 V

VD, VLC = 5 V

VD, VLC = 3.3 V

Power Supply Current VA = 5 V (Power-Down Mode) (Note 12) VD, VLC = 5 V

Power Consumption VA = 5 V, VD = VLC= 3.3 V Normal Operation VA = 5 V, VD = VLC = 5 V Normal Operation

Power-Down Mode (Note 12)

Power Supply Rejection Ratio(1 kHz) (Note 13) PSRR - 55 - dB

Common Mode Voltage

Nominal Common Mode Voltage VQ - VA/2 - VDC

Maximum DC Current Source/Sink from VQ - 1 - A

VQ Output Impedance - 25 - k

Positive Voltage Reference

FILT+ Nominal Voltage FILT+ - VA - VDC

Maximum DC Current Source/Sink from FILT+ - 10 - A

FILT+ Output Impedance - 10 - k

Mute Control

Maximum MUTEA & MUTEB Drive Current - 3 - mA

37 24 32 13

224 345 365

42 30 38 20

270 400

mA mA mA mA

A A

mW mW

W

Notes: 12. Power Down Mode is defined as RST

= Low with all clocks and data lines held static.

13. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram.

DIGITAL SWITCHING CHARACTERISTICS

Parameter (Note 14) Symbol Min Typ Max Units

High-Level Input Voltage Serial Audio Interface

Serial Control Port

Low-Level Input Voltage Serial Audio Interface

Serial Control Port

High-Level Output Voltage at Io = 2 mA Serial Audio Interface

Serial Control Port

MUTEA

Low-Level Output Voltage at I

Input Leakage Current I

= 2 mA

, MUTEB

Notes: 14. Serial Audio Port signals include: SCLK, LRCK, SDOUT, SDIN

Serial Control Port signals include: SDA/CDOUT, SCL/CCLK, AD1/CDIN, AD0/CS

0.7xVD

0.7xVLC

VD - 1.0

VLC - 1.0

VA - 1.0

--0.4V

-10 - 10 A

0.2xVD

0.2xVLC

V V

V V V

, RST

DS686F1 13

CS4270

64Fs

------------------

128Fs

---------------------

64Fs

------------------

64Fs

------------------

SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE

Logic "0" = DGND = AGND = 0 V; Logic "1" = VD, CL = 20 pF.

Parameter Symbol Min Typ Max Unit

Sample Rate Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

MCLK Specifications

MCLK Frequency Stand-Alone Mode

(Note 15) Serial Control Port Mode

MCLK Duty Cycle 405060ns

Master Mode

LRCK Duty Cycle - 50 - %

Fs Fs Fs

fmclk fmclk

100

1.024

54 108 216

55.296

kHz kHz kHz

MHz MHz

SCLK Period (Note 16) t

sclkw

--s

SCLK Duty Cycle - 50 - %

SCLK falling to LRCK edge t

SCLK falling to SDOUT valid t

SDIN valid to SCLK rising setup time t

SCLK rising to SDIN hold time t

mslr

sdo

sdis

sdih

-20 - 20 ns

- - 32 ns

16 - - ns

20 - - ns

Slave Mode

LRCK Duty Cycle 40 50 60 %

SCLK Period

(Note 15) Single-Speed Mode

sclkw

Double-Speed Mode

sclkw

Quad-Speed Mode

sclkw

SCLK Duty Cycle 455055ns

SCLK falling to LRCK edge t

SDOUT valid before SCLK rising t

SDOUT valid after SCLK rising t

SDIN valid to SCLK rising setup time t

SCLK rising to SDIN hold time t

slrd

stp

hld

sdis

sdih

-20 - 20 ns

10 - - ns

5--ns

16 - - ns

20 - - ns

Notes: 15. In Control Port Mode, MCLK Frequency, and Functional Mode Select bits must be configured according

to Table 7 on page 22, Table 9 on page 33, and Table 13 on page 35.

16. t

sclkw = tsclkh + tsclkl

in Figures 5 and 7.

14 DS686F1

+ 31 hidden pages