Cirrus Logic CS4265 User Manual
1.8 V to 5 V
Multibit
Modulator
Multibit
Modulator
Low-Latency
Anti-Alias Filter
Interpolation
Filter
Interpolation
Filter
Left DAC Output
Right DAC Output
Switched Capacitor
DAC and Filter
Multibit
Oversampling
ADC
Multibit
Oversampling
ADC
Low-Latency
Anti-Alias Filter
High Pass
Filter
High Pass
Filter
Stereo
Line Input
Serial
Audio
Input
Serial
Audio
Output
3.3 V to 5 V 3.3 V to 5 V
Switched Capacitor
DAC and Filter
MUX
PGA
Volume
Control
Volume
Control
PCM Serial Interface / Loopback
Mute
Control
Level Translator Level Translator
Reset
I2C Control
Data
Mute Control
Mic Input
1 & 2
PGA
+32 dB
+32 dB
Internal Voltage
Reference
IEC60958-3 Transmitter
Mic Bias
Microphone Bias
Transmitter Output
Register Configuration
CS4265
104 dB, 24-Bit, 192 kHz Stereo Audio CODEC
D/A Features
Multi-Bit Delta Sigma Modulator
104 dB Dynamic Range
-90 dB THD+N
Up to 192 kHz Sampling Rates
Single-Ended Analog Architecture
Volume Control with Soft Ramp
– 0.5 dB Step Size
– Zero Crossing, Click-Free Transitions
Popguard
– Minimizes the Effects of Output Transients
Filtered Line-Level Outputs
Selectable Serial Audio Interface Formats
– Left-Justified up to 24-bit
– I²S up to 24-bit
– Right-Justified 16-, 18-, 20-, and 24-bit
Selectable 50/15 µs De-Emphasis
®
Technology
A/D Features
Multi-Bit Delta Sigma Modulator
104 dB Dynamic Range
-95 dB THD+N
Stereo 2:1 Input Multiplexer
Programmable Gain Amplifier (PGA)
– ± 12 dB Gain, 0.5 dB Step Size
– Zero Crossing, Click-Free Transitions
Pseudo-Differential Stereo Line Inputs
Stereo Microphone Inputs
– +32 dB Gain Stage
– Low-Noise Bias Supply
Up to 192 kHz Sampling Rates
Selectable Serial Audio Interface Formats
– Left-Justified up to 24-bit
– I²S up to 24-bit
High-Pass Filter or DC Offset Calibration
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2012
(All Rights Reserved)
AUG '12
DS657F3
CS4265
System Features
Synchronous IEC60958-3 Transmitter
– Up to 192 kHz Sampling Rates
– 75 Drive Capability
Serial Audio Data Input Multiplexer
Internal Digital Loopback
Supports Master or Slave Operation
Mute Output Control
Power-Down Mode
– Available for A/D, D/A, CODEC, Mic
Preamplifier
+3.3 V to +5 V Analog Power Supply
+3.3 V to +5 V Digital Power Supply
Direct Interface with 1.8 V to 5 V Logic Levels
Supports I²C
®
Control Port Interface
General Description
The CS4265 is a highly integrated stereo audio CODEC. The CS4265 performs stereo analog-to-digital
(A/D) and digital-to-analog (D/A) conversion of up to
24-bit serial values at sample rates up to 192 kHz.
A 2:1 stereo input multiplexer is included for s electing
between line-level or microphone-level inputs. The microphone input path includes a +32 dB gain stage and
a low noise bias voltage supply. The PGA is available
for line or microphone inputs and provides gain or attenuation of 12 dB in 0.5 dB steps.
The output of the PGA is followed by an advanced 5thorder, multi-bit delta sigma modulator and digital filtering/decimation. Sampled data is transmitted by the
serial audio interface at rates from 4 kHz to 192 kHz in
either Slave or Master Mode.
The D/A converter is based on a 4th-order multi-bit delta
sigma modulator with an ultra-linear low-pass filter and
offers a volume control that operates with a 0.5 dB step
size. It in corporates selectable soft ramp and zero
crossing transition functions to eliminate clicks and
pops.
Standard 50/15 s de-emphasis is availa ble for a
44.1 kHz sample rate for compatibility with digital audio
programs mastered using the 50 /15 s pre-emphasis
technique.
Integrated level translators allow ea sy interfacing between the CS4265 and other devices operating over a
wide range of logic levels.
The CS4265 is available in a 32-pin QFN package for
both Commercial (-10° to +70° C) and Automotive (-40°
to +105° C) grade. The CDB4265 is also available for
device evaluation and implementation suggestions.
Please refer to “Ordering Information” on page 57 for
complete details.
2 DS657F3
TABLE OF CONTENTS
1. PIN DESCRIPTIONS .......................................................................................................................... 7
2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 9
SPECIFIED OPERATING CONDITIONS ............................................................................................. 9
ABSOLUTE MAXIMUM RATINGS .......................................................................................................9
DAC ANALOG CHARACTERISTICS ................................................................................................. 10
DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ............................ 11
ADC ANALOG CHARACTERISTICS ................................................................................................. 13
ADC ANALOG CHARACTERISTICS ................................................................................................. 15
ADC DIGITAL FILTER CHARACTERISTICS ..................................................................................... 16
DC ELECTRICAL CHARACTERISTICS ............................................................................................. 17
DIGITAL INTERFACE CHARACTERISTICS ...................................................................................... 18
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................. 19
SWITCHING CHARACTERISTICS - I²C CONTROL PORT ............................................................... 22
3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 23
4. APPLICATIONS ................................................................................................................................... 24
4.1 Recommended Power-Up Sequence ............................................................................................. 24
4.2 System Clocking ............................................................................................................................. 24
4.2.1 Master Clock ......................................................................................................................... 24
4.2.2 Master Mode ......................................................................................................................... 25
4.2.3 Slave Mode ........................................................................................................................... 25
4.3 High-Pass Filter and DC Offset Calibration .................................................................................... 25
4.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................................27
4.5 Input Connections ........................................................................................................................... 27
4.5.1 Pseudo-Differential Input ....................................................................................................... 27
4.6 Output Connections ........................................................................................................................ 28
4.7 Output Transient Control ................................................................................................................ 28
4.7.1 Power-Up .............................................................................................................................. 28
4.7.2 Power-Down .......................................................................................................................... 28
4.7.3 Serial Interface Clock Changes ............................................................................................. 28
4.8 DAC Serial Data Input Multiplexer .................................................................................................. 29
4.9 De-Emphasis Filter ......................................................................................................................... 29
4.10 Internal Digital Loopback .............................................................................................................. 29
4.11 Mute Control ................................................................................................................................. 30
4.12 AES3 Transmitter ......................................................................................................................... 30
4.12.1 TxOut Driver ........................................................................................................................ 30
4.12.2 Mono Mode Operation ......................................................................................................... 31
4.13 I²C Control Port Description and Timing ....................................................................................... 31
4.14 Status Reporting ........................................................................................................................... 32
4.15 Reset ............................................................................................................................................ 33
4.16 Synchronization of Multiple Devices ............................................................................................. 33
4.17 Grounding and Power Supply Decoupling .................................................................................... 33
4.18 Package Considerations ............................................................................................................... 33
5. REGISTER QUICK REFERENCE ........................................................................................................ 34
6. REGISTER DESCRIPTION .......................................................................................................
ID
6.1 Chip
6.2 Power Control - Address 02h ......................................................................................................... 36
6.2.1 Freeze (Bit 7) ......................................................................................................................... 36
6.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 36
6.2.3 Power-Down ADC (Bit 2) ....................................................................................................... 36
6.2.4 Power-Down DAC (Bit 1) ....................................................................................................... 37
6.2.5 Power-Down Device (Bit 0) ................................................................................................... 37
6.3 DAC Control - Address 03h ............................................................................................................ 37
- Register 01h .................................................................................................................... 36
CS4265
........... 36
DS657F3 3
CS4265
6.3.1 DAC Digital Interface Format (Bits 5:4) ................................................................................. 37
6.3.2 Mute DAC (Bit 2) ................................................................................................................... 37
6.3.3 De-Emphasis Control (Bit 1) .................................................................................................. 38
6.4 ADC Control - Address 04h ............................................................................................................ 38
6.4.1 Functional Mode (Bits 7:6) .................................................................................................... 38
6.4.2 ADC Digital Interface Format (Bit 4) ...................................................................................... 38
6.4.3 Mute ADC (Bit 2) ................................................................................................................... 39
6.4.4 ADC High-Pass Filter Freeze (Bit 1) ..................................................................................... 39
6.4.5 Master / Slave Mode (Bit 0) ................................................................................................... 39
6.5 MCLK Frequency - Address 05h .................................................................................................... 39
6.5.1 Master Clock Dividers (Bits 6:4) ............................................................................................ 39
6.6 Signal Selection - Address 06h ...................................................................................................... 40
6.6.1 DAC SDIN Source (Bit 7) ...................................................................................................... 40
6.6.2 Digital Loopback (Bit 1) ......................................................................................................... 40
6.7 Channel B PGA Control - Address 07h .......................................................................................... 40
6.7.1 Channel B PGA Gain (Bits 5:0) ............................................................................................. 40
6.8 Channel A PGA Control - Address 08h .......................................................................................... 40
6.8.1 Channel A PGA Gain (Bits 5:0) ............................................................................................. 40
6.9 ADC Input Control - Address 09h ................................................................................................... 41
6.9.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3) .................................................................. 41
6.9.2 Analog Input Selection (Bit 0) ................................................................................................ 41
6.10 DAC Channel A Volume Control - Address 0Ah ........................................................................... 41
6.11 DAC Channel B Volume Control - Address 0Bh ........................................................................... 42
6.11.1 Volume Control (Bits 7:0) .................................................................................................... 42
6.12 DAC Control 2 - Address 0Ch ...................................................................................................... 42
6.12.1 DAC Soft Ramp or Zero Cross Enable (Bits 7:6) ................................................................ 42
6.12.2 Invert DAC Output (Bit 5) .................................................................................................... 43
6.13 Status - Address 0Dh ................................................................................................................... 43
6.13.1 E to F C-Buffer Transfer ...................................................................................................... 43
6.13.2 Clock Error (Bit 3) ................................................................................................................ 43
6.13.3 ADC Overflow (Bit 1) ........................................................................................................... 43
6.13.4 ADC Underflow (Bit 0) ......................................................................................................... 43
6.14 Status Mask - Address 0Eh .......................................................................................................... 44
6.15 Status Mode MSB - Address 0Fh ................................................................................................. 44
6.16 Status Mode LSB - Address 10h .................................................................................................. 44
6.17 Transmitter Control 1 - Address 11h ............................................................................................ 44
6.17.1 E to F C-Data Buffer Transfer Inhibit (Bit 6) ........................................................................ 44
6.17.2 C-Data Access Mode (Bit 5) ................................................................................................ 44
6.18 Transmitter Control 2 - Address 12h ............................................................................................ 45
6.18.1 Transmitter Digital Interface Format (Bits 7:6) .................................................................... 45
6.18.2 Transmitter Output Driver Control (Bit 5) ............................................................................. 45
6.18.3 Transmitter Mute Control (Bit 4) .......................................................................................... 45
6.18.4 Transmitted Validity Bit Control (Bit 3) ...............................................................................
18.5
6.
6.18.6 Mono Mode CS Data Source (Bit 1) .................................................................................... 45
6.18.7 Mono Mode Channel Selection (Bit 0) ................................................................................. 46
7. PARAMETER DEFINITIONS ................................................................................................................ 47
8. DAC FILTER PLOTS .................................................................................................................... 48
9. ADC FILTER PLOTS ......................................................................................................................... 50
10. EXTERNAL IEC60958-3 TRANSMITTER COMPONENTS ............................................................... 52
10.1 IEC60958-3 Transmitter External Components ............................................................................ 52
10.2 Isolating Transformer Requirements ............................................................................................ 52
11. CHANNEL STATUS BUFFER MANAGEMENT ................................................................................ 53
11.1 IEC60958-3 Channel Status (C) Bit Management ........................................................................ 53
Transmitter Mono/Stereo Operation Control (Bit 2) ............................................................. 45
.45
4 DS657F3
11.1.1 Accessing the E Buffer ........................................................................................................ 54
11.2 Serial Copy Management System (SCMS) .................................................................................. 54
11.3 Channel Status Data E Buffer Access .......................................................................................... 54
11.3.1 One-Byte Mode ................................................................................................................... 55
11.3.2 Two-Byte Mode ................................................................................................................... 55
12. PACKAGE DIMENSIONS ............................... ... ... ... .... ... ... ....................................... ... ... ... .... ............ 56
13. THERMAL CHARACTERISTICS AND SPECIFICATIONS ............................................................... 56
14. ORDERING INFORMATION ........................................................................................................ 57
15. REVISION HISTORY ................................................ ....................................... ... .... ... ... ... ................... 57
LIST OF FIGURES
Figure 1.DAC Output Test Load ................................................................................................................ 12
Figure 2.Maximum DAC Loading .............................................................................................................. 12
Figure 3.Master Mode Serial Audio Port Timing ....................................................................................... 20
Figure 4.Slave Mode Serial Audio Port Timing ......................................................................................... 20
Figure 5.Format 0, Left-Justified up to 24-Bit Data ................................................................................... 21
Figure 6.Format 1, I²S up to 24-Bit Data ................................................................................................... 21
Figure 7.Format 2, Right-Justified 16-Bit Data.
Format 3, Right-Justified 24-Bit Data. ....................................................................................................... 21
Figure 8.Control Port Timing - I²C Format ................................................................................................. 22
Figure 9.Typical Connection Diagram ....................................................................................................... 23
Figure 10.Master Mode Clocking .............................................................................................................. 25
Figure 11.Analog Input Architecture .......................................................................................................... 27
Figure 12.Pseudo-Differential Input Stage ................................................................................................ 28
Figure 13.De-Emphasis Curve .................................................................................................................. 29
Figure 14.Suggested Active-Low Mute Circuit .......................................................................................... 30
Figure 15.Control Port Timing, I²C Write ................................................................................................... 32
Figure 16.Control Port Timing, I²C Read ................................................................................................... 32
Figure 17.De-Emphasis Curve .................................................................................................................. 38
Figure 18.DAC Single-Speed Stopband Rejection ................................................................................... 48
Figure 19.DAC Single-Speed Transition Band .......................................................................................... 48
Figure 20.DAC Single-Speed Transition Band .......................................................................................... 48
Figure 21.DAC Single-Speed Passband Ripple ........................................................................................ 48
Figure 22.DAC Double-Speed Stopband Rejection ..................................................................................48
Figure 23.DAC Double-Speed Transition Band ........................................................................................ 48
Figure 24.DAC Double-Speed Transition Band ........................................................................................ 49
Figure 25.DAC Double-Speed Passband Ripple ...................................................................................... 49
Figure 26.DAC Quad-Speed Stopband Rejection ..................................................................................... 49
Figure 27.DAC Quad-Speed Transition Band ........................................................................................... 49
Figure 28.DAC Quad-Speed Transition Band ........................................................................................... 49
Figure 29.DAC Quad-Speed Passband Ripple ......................................................................................... 49
Figure 30.ADC Single-Speed Stopband Rejection ................................................................................... 50
Figure 31.ADC Single-Speed Stopband Rejection ................................................................................... 50
Figure 32.ADC Single-Speed Transition Band (Detail) ............................................................................. 50
Figure 33.ADC Single-Speed Passband Ripple ........................................................................................ 50
Figure 34.ADC Double-Speed Stopband Rejection ..................................................................................50
Figure 35.ADC Double-Speed Stopband Rejection ..................................................................................50
Figure 36.ADC Double-Speed Transition Band (Detail) ............................................................................51
Figure 37.ADC Double-Speed Passband Ripple ...................................................................................... 51
Figure 38.ADC Quad-Speed Stopband Rejection ..................................................................................... 51
Figure 39.ADC Quad-Speed Stopband Rejection ..................................................................................... 51
Figure 40.ADC Quad-Speed Transition Band (Detail) ..............................................................................51
Figure 41.ADC Quad-Speed Passband Ripple ......................................................................................... 51
CS4265
DS657F3 5
Figure 42.Consumer Output Circuit (VD = 5 V) ........................................................................................ 52
Figure 43.TTL/CMOS Output Circuit ......................................................................................................... 52
Figure 44.Channel Status Data Buffer Structure ....................................................................................... 53
Figure 45.Flowchart for Writing the E Buffer ............................................................................................. 54
LIST OF TABLES
Table 1. Speed Modes .............................................................................................................................. 24
Table 2. Common Clock Frequencies ....................................................................................................... 24
Table 3. MCLK Dividers ............................................................................................................................ 25
Table 4. Slave Mode Serial Bit Clock Ratios ............................................................................................. 25
Table 5. Device Revision .......................................................................................................................... 36
Table 6. Freeze-able Bits .......................................................................................................................... 36
Table 7. DAC Digital Interface Formats .................................................................................................... 37
Table 8. De-Emphasis Control .................................................................................................................. 38
Table 9. Functional Mode Selection .......................................................................................................... 38
Table 10. ADC Digital Interface Formats .................................................................................................. 39
Table 11. MCLK Frequency ...................................................................................................................... 39
Table 12. DAC SDIN Source Selection ..................................................................................................... 40
Table 13. Example Gain and Attenuation Settings ................................................................................... 40
Table 14. PGA Soft Cross or Zero Cross Mode Selection ........................................................................ 41
Table 15. Analog Input Selection .............................................................................................................. 41
Table 16. Digital Volume Control Example Settings ................................................................................. 42
Table 17. DAC Soft Cross or Zero Cross Mode Selection ........................................................................ 43
Table 18. Transmitter Digital Interface Formats ........................................................................................ 45
CS4265
6 DS657F3
1. PIN DESCRIPTIONS
109
8
7
6
5
4
3
2
1
11
12
13 14 15 16
17
18
19
20
21
22
23
24
25
262728
29
303132
Top-Down (Through Package) View
32-Pin QFN Package
TXOUT
VD
DGND
MCLK
LRCK
SCLK
SDOUT
SDIN1
SGND
AFILTA
AFILTB
VQ
FILT+
MICIN1
MICIN2
MICBIAS
SDA
SCL
VLC
RESET
VA
AGND
AINA
AINB
SDIN2
TXSDIN
VLS
MUTEC
AOUTB
AOUTA
AGND
VA
Thermal Pad
CS4265
Pin Name # Pin Description
SDA 1 Serial Control Data (Input/Output) - Bidirectional data line for the I²C control port.
SCL 2 Serial Control Port Clock (Input) - Serial clock for the I²C control port.
VLC
RESET
VA 5 Analog Power (Input) - Positive power for the internal analog section.
AGND 6 Analog Ground (Input) - Ground reference for the internal analog section.
AINA
AINB
SGND 9 Signal Ground (Input) - Ground reference for the analog line inputs.
AFILTA
AFILTB
VQ 12 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
FILT+ 13 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
MICIN1
MICIN2
MICBIAS
3 Control Port Power (Input) - Determines the required signal level for the control port interface. Refer to
the Recommended Operating Conditions for appropriate voltages.
4 Reset (Input) - The device enters a low-power mode when this pin is driven low.
7,
Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification
8
table.
10,
Antialias Filter Connection (Output) - Antialias filter connection for the ADC inputs.
11
14,
Microphone Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specifica-
15
tion table.
16 Microphone Bias (Output) - Low noise bias supply for external microphone. Electrical characteristics
are specified in the DC Electrical Characteristics table.
DS657F3 7
VA 17 Analog Power (Input) - Positive power for the internal analog section.
AGND 18 Analog Ground (Input) - Ground reference for the internal analog section.
AOUTA
AOUTB
MUTEC
VLS
TXSDIN 23 Transmitter Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
SDIN2 24 Serial Audio Data Input 2 (Input) - Input for two’s complement serial audio data.
SDIN1 25 Serial Audio Data Input 1 (Input) - Input for two’s complement serial audio data.
SDOUT 26 Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
SCLK 27 Serial Clock (Input/Output) - Serial clock for the serial audio interface.
LRCK
MCLK 29 Master Clock (Input) - Clock source for the delta-sigma modulators.
DGND 30 Digital Ground (Input) - Ground reference for the internal digital section.
VD 31 Digital Power (Input) - Positive power for the internal digital section.
TXOUT 32 Transmitter Line Driver Output (Output) - IEC60958-3 driver output.
Thermal Pad - Thermal Pad - Thermal relief pad for optimized heat dissipation.
19, 20 Analog Audio Output (Output) - The full scale output level is specified in the DAC Analog Characteris-
tics specification table.
21 Mute Control (Output) - This pin is active during power-up initialization, reset, muting, when master
clock left/right clock frequency ratio is incorrect, or power-down.
22 Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio inter-
face. Refer to the Recommended Operating Conditions for appropriate voltages.
28 Lef t Righ t Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
CS4265
8 DS657F3
2. CHARACTERISTICS AND SPECIFICATIONS
SPECIFIED OPERATING CONDITIONS
AGND = DGND = 0 V; All voltages with respect to ground.
Parameters Symbol Min Nom Max Units
DC Power Supplies: Analog
Digital
Logic - Serial Port
Logic - Control Port
Ambient Operating Temperature (Power Applied) T
VA
VD
VLS
VLC
Notes: 1. Maximum of VA+0.25 V or 5.25 V, whichever is less.
ABSOLUTE MAXIMUM RATINGS
AGND = DGND = 0 V All voltages with respect to ground. (Note 2)
Parameter Symbol Min M ax Units
DC Power Supplies: Analog
Digital
Logic - Serial Port
Logic - Control Port
Input Current (Note 3)
Analog Input Voltage
Digital Input Voltage Logic - Serial Port
Logic - Control Port
Ambient Operating Temperature (Power Applied)
Storage Temperature
VLS
VLC
V
V
V
A
VA
VD
I
in
INA
IND-S
IND-C
T
A
T
stg
CS4265
3.13
3.13
1.71
1.71
-10 - +70 C
AGND-0.3 VA+0.3 V
5.0
3.3
3.3
3.3
-0.3
-0.3
-0.3
-0.3
- 10 mA
-0.3
-0.3
-50 +125 C
-65 +150 C
5.25
(Note 1)
5.25
5.25
+6.0
+6.0
+6.0
+6.0
VLS+0.3
VLC+0.3
V
V
V
V
V
V
V
V
V
V
2. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
3. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
DS657F3 9
CS4265
DAC ANALOG CHARACTERISTICS
Test Conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V
or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; T
+85° C for Automotive; Output test signal: 997 Hz full-scale sine wave; Test load R
Figure 1), Fs = 48/96/192 kHz. Measurement Bandwidth 10 Hz to 20 kHz; All Connections as shown in Figure 9 on
page 23.
Commercial Grade Automotive Grade
Parameter
Symbol Min Typ Max Min Typ Max Unit
Dynamic Performance for VA = 4.75 V to 5.25 V
Dynamic Range (Note 4)
18 to 24-Bit A-Weighted
unweighted
16-Bit A-Weighted
unweighted
Total Harmonic Distortion + Noise (Note 4)
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
THD+N
98
95
90
87
-
-
-
-
-
-
Dynamic Performance for VA = 3.13 V to 3.46 V
Dynamic Range (Note 4)
18 to 24-Bit A-Weighted
unweighted
16-Bit A-Weighted
unweighted
Total Harmonic Distortion + Noise (Note 4)
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
Interchannel Isolation (1 kHz) - 100 - - 100 - dB
THD+N
95
92
88
85
-
-
-
-
-
-
DC Accuracy
Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB
Gain Drift - 100 - - 100 - ppm/°C
Analog Output
Full Scale Output Voltage 0.60*VA 0.65*VA 0.70*VA 0.60*VA 0.65*VA 0.70*VA V
DC Current draw from an AOUT pin (Note 5) I
AC-Load Resistance (Note 6) R
Load Capacitance (Note 6) C
Output Impedance Z
OUT
L
L
OUT
--10--10A
3--3- -k
- - 100 - - 100 pF
-150- -150-
= -10° to +70° C for Commercial or -40° to
104
101
96
93
-90
-81
-41
-93
-73
-33
101
98
93
90
-87
-78
-38
-90
-70
-30
A
-
-
-
-
-84
-
-
-87
-
-
-
-
-
-
-79
-
-
-82
-
-
= 3 k, CL = 10 pF (see
L
96
93
88
85
-
-
-
-
-
-
93
90
86
83
-
-
-
-
-
-
104
101
96
93
-90
-81
-41
-93
-73
-33
101
98
93
90
-87
-78
-38
-90
-70
-30
-
-
-
-
-82
-
-
-85
-
-
-
-
-
-
-77
-
-
-80
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
pp
4. One-half LSB of triangular PDF dither added to data.
5. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin
due to typical leakage through the electrolytic DC blocking capacitors.
10 DS657F3
CS4265
6. Guaranteed by design. See Figure 2. RL and CL reflect the recommended minimum resistance and
maximum capacitance required for the internal op-amp’s stability. C
internal output amp; increasing C
beyond 100 pF can cause the internal op-amp to become unstable.
L
affects the dominant pole of the
L
DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Parameter (Note 7,10) Symbol Min Typ Max Unit
Combined Digital and On-chip Analog Filter Response Single-Speed Mode
Passband (Note 7) to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.175 - +0.01 dB
StopBand 0.5465 - - Fs
StopBand Attenuation (Note 8) 50 - - dB
Group Delay tgd - 10/Fs - s
De-emphasis Error (Note 9) Fs = 44.1 kHz - - +0.05/-0.25 dB
0
0
-
-
0.35
0.4992
Fs
Fs
Combined Digital and On-chip Analog Filter Response Double-Speed Mode
Passband (Note 7) to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.15 - +0.15 dB
StopBand 0.5770 - - Fs
StopBand Attenuation (Note 8) 55 - - dB
Group Delay tgd - 5/Fs - s
0
0
-
-
0.22
0.501
Fs
Fs
Combined Digital and On-chip Analog Filter Response Quad-Speed Mode
Passband (Note 7) to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.12 - 0 dB
StopBand 0.7 - - Fs
StopBand Attenuation (Note 8) 51 - - dB
Group Delay tgd - 2.5/Fs - s
0
0
-
-
0.110
0.469
Fs
Fs
7. Filter response is guaranteed by design.
8. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs.
9. De-emphasis is available only in Single-Speed Mode.
10. Response is clock dependent and will scale with Fs. Note that the amplitude vs. frequency plots of this
data (Figures 18 to 27) have been normalized to Fs and can be de-normalized by multiplying the X-axis
scale by Fs.
DS657F3 11
AOUTx
AGND
3.3µF
V
out
R
L
C
L
Figure 1. DAC Output Test Load Figure 2. Maximum DAC Loading
100
50
75
25
2.5
51015
Safe Operating
Region
Capacitive Load -- C (pF)
L
Resistive Load -- R (k)
L
125
3
20
CS4265
12 DS657F3
CS4265
ADC ANALOG CHARACTERISTICS
Test conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V
or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; T
+85° C for Automotive; Input test signal: 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz;
Fs = 48/96/192 kHz.; All connections as shown in Figure 9 on page 23.
Line-Level Inputs
Parameter Symbol Min Typ Max Unit
Dynamic Performance for VA = 4.75 V to 5.25 V
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
(Note 13) 40 kHz bandwidth unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
(Note 13) 40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise (Note 12)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
(Note 13) 40 kHz bandwidth -1 dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
(Note 13) 40 kHz bandwidth -1 dB
THD+N
Dynamic Performance for VA = 3.13 V to 3.46 V
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
(Note 13) 40 kHz bandwidth unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
(Note 13) 40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise (Note 12)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
(Note 13) 40 kHz bandwidth -1 dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
(Note 13) 40 kHz bandwidth -1 dB
THD+N
Line-Level Inputs
Parameter Symbol
Interchannel Isolation - 90 - dB
= -10° to +70° C for Commercial or -40° to
A
98
95
-
92
89
-
-
-
-
-
-
-
-
-
93
90
-
89
86
-
-
-
-
-
-
-
-
-
104
101
98
98
95
92
-95
-81
-41
-92
-92
-75
-35
-89
101
98
95
95
92
89
-92
-78
-38
-84
-89
-72
-32
-81
-89
-86
-86
-83
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Commercial Grade
UnitMin Typ Max
DS657F3 13
CS4265
DC Accuracy
Gain Error --10 %
Gain Drift - 100 - ppm/°C
Line-Level Input Characteristics
Full-scale Input Voltage 0.51*VA 0.57*VA 0.63*VA V
Input Impedance (Note 11) 6.12 6.8 7.48 k
Maximum Interchannel Input Impedance
Mismatch
-5-%
Line-Level and Microphone-Level Inputs
Commercial Grade
Parameter Symbol
DC Accuracy
Interchannel Gain Mismatch - 0.1 - dB
Programmable Gain Characteristics
Gain Step Size - 0.5 - dB
Absolute Gain Step Error - - 0.4 dB
11. Valid when the line-level inputs are selected.
pp
UnitMin Typ Max
14 DS657F3
ADC ANALOG CHARACTERISTICS
(Continued)
Microphone-Level Inputs
Parameter Symbol Min Typ Max Unit
Dynamic Performance for VA = 4.75 V to 5.25 V
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 12)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB
-1 dB
Dynamic Performance for VA = 3.13 V to 3.46 V
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
THD+N
77
74
65
62
77
74
CS4265
83
80
71
68
-
-
-
-
-80
-60
-20
-68
83
80
-74
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 12)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB
-1 dB
Interchannel Isolation - 80 - dB
THD+N
65
62
71
68
-
-
-
-
-80
-60
-20
-68
-74
-
-
-
-
-
dB
dB
dB
dB
dB
dB
DC Accuracy
Gain Error - 5 -%
Gain Drift - 300 - ppm/°C
Microphone-Level Input Characteristics
Full-scale Input Voltage 0.013*VA 0.017*VA 0.021*VA V
Input Impedance (Note 14) -60-k
pp
12. Referred to the typical line-level full-scale input voltage
13. Valid for Double- and Quad-Speed Modes only.
14. Valid when the microphone-level inputs are selected.
DS657F3 15
CS4265
ADC DIGITAL FILTER CHARACTERISTICS
Parameter (Notes 15, 17) Symbol Min Typ Max Unit
Single-Speed Mode
Passband (-0.1 dB) 0 - 0.4896 Fs
Passband Ripple - - 0.035 dB
Stopband 0.5688 - - Fs
Stopband Attenuation 70 - - dB
Total Group Delay (Fs = Output Sample Rate) t
gd
Double-Speed Mode
Passband (-0.1 dB) 0 - 0.4896 Fs
Passband Ripple - - 0.025 dB
Stopband 0.5604 - - Fs
Stopband Attenuation 69 - - dB
Total Group Delay (Fs = Output Sample Rate) t
gd
Quad-Speed Mode
Passband (-0.1 dB) 0 - 0.2604 Fs
Passband Ripple - - 0.025 dB
Stopband 0.5000 - - Fs
Stopband Attenuation 60 - - dB
Total Group Delay (Fs = Output Sample Rate) t
gd
High-Pass Filter Characteristics
Frequency Response -3.0 dB
-0.13 dB (Note 16)
Phase Deviation @ 20 Hz (Note 16) -10 -Deg
Passband Ripple -- 0dB
Filter Settling Time
-12/Fs - s
-9/Fs - s
-5/Fs - s
-120-
5
10
/Fs s
-
Hz
Hz
15. Filter response is guaranteed by design.
16. Response shown is for Fs = 48 kHz.
17. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 30 to 41) are
normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
16 DS657F3
CS4265
DC ELECTRICAL CHARACTERISTICS
AGND = DGND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Fs=48 kHz; Master Mode.
Parameter Symbol Min Typ Max Unit
Power Supply Current VA = 5 V
(Normal Operation) VA = 3.3 V
VD, VLS, VLC = 5 V
VD, VLS, VLC = 3.3 V
Power Supply Current VA = 5 V
(Power-Down Mode) (Note 18) VLS, VLC, VD=5 V
Power Consumption
(Normal Operation) VA, VD, VLS, VLC = 5 V
VA, VD, VLS, VLC = 3.3 V
(Power-Down Mode) VA, VD, VLS, VLC = 5 V
Power Supply Rejection Ratio (1 kHz) (Note 19) PSRR - 55 - dB
VQ Characteristics
Quiescent Voltage VQ - 0.5 x VA - VDC
DC Current from VQ (Note 20) I
VQ Output Impedance Z
FILT+ Nominal Voltage FILT+ - VA - VDC
Microphone Bias Voltage MICBIAS - 0.8 x VA - VDC
Current from MICBIAS I
I
I
I
I
I
I
MB
A
A
D
D
A
D
-
-
-
Q
Q
-
-
-
-
-
-
-
-
-
-- 1A
-4.5 -k
-- 2mA
41
37
39
23
0.50
0.54
400
198
4.2
50
45
47
28
-
-
485
241
-
mA
mA
mA
mA
mA
mA
mW
mW
mW
18. Power-Down Mode is defines as RESET
= Low with all clock and data lines held static and no analog
input.
19. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection
Diagram.
20. Guaranteed by design. The DC current draw represents the allowed current draw due to typical leakage
through the electrolytic de-coupling capacitors.
DS657F3 17
CS4265
DIGITAL INTERFACE CHARACTERISTICS
Test conditions (unless otherwise specified): AGND = DGND = 0 V; VLS = VLC = 1.71 V to 5.25 V.
Parameters (Note 21) Symbol Min Typ Max Units
High-Level Input Voltage
VL = 1.71 V Serial Port
Control Port
VL > 2.0 V Serial Port
Control Port
Low-Level Input Voltage Serial Port
Control Port
High-Level Output Voltage at I
= 2 mA Serial Port
o
Control Port
MUTEC
TXOUT
Low-Level Output Voltage at I
= 2 mA Serial Port
o
Control Port
MUTEC
TXOUT
Input Leakage Current I
Input Capacitance (Note 22) --1pF
Maximum MUTEC Drive Current - 3 - mA
21. Serial Port signals include: MCLK, SCLK, LRCK, SDIN1, SDIN2, TXSDIN, SDOUT.
Control Port signals include: SCL, SDA, RESET
22. Guaranteed by design.
V
IH
V
IH
V
IH
V
IH
V
IL
V
IL
V
OH
V
OH
V
OH
V
OH
V
OL
V
OL
V
OL
V
OL
in
0.8xVLS
0.8xVLC
0.7xVLS
0.7xVLC
-
-
VLS-1.0
VLC-1.0
VA- 1.0
VD-1.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.2xVLS
0.2xVLC
-
-
-
-
0.4
0.4
0.4
0.4
--±10A
V
V
V
V
V
V
V
V
V
V
V
V
V
V
.
18 DS657F3
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