Cirrus Logic CS42526 User Manual
RST
RXP0
RXP1/GPO1
AD0/CS
SCL/CCLK
SDA/CDOUT
AD1/CDIN
VLC
AOUTA1+
AOUTA1-
AOUTB1+
AOUTA3+
AOUTA3-
AOUTA2-
AOUTB2-
AOUTA2+
AOUTB2+
AOUTB1-
AOUTB3+
AOUTB3-
AINL+
AINL-
AINR+
AINR-
FILT+
REFGND
VQ
Ref
ADC#1
ADC#2
Digital Filter
Digital Filter
Gain & Clip
Gain & Clip
CX_SCLK
CX_LRCK
CX_SDIN3
CX_SDIN2
CX_SDIN1
DGND VDLPFLTTXP
INT
Rx
Clock/Data
Recovery
S/PDIF
Decoder
Control
Port
DAC#1
DAC#2
DAC#3
DAC#4
DAC#5
DAC#6
Digital Filter
Volume Control
DGND
RXP2/GPO2
RXP3/GPO3
RXP4/GPO4
RXP5/GPO5
RXP6/GPO6
RXP7/GPO7
VD
MUTEC
GPO
Analog Filter
VARX AGND
AGND
VA
CODEC
Serial
Port
CX_SDOUT
ADCIN1
ADCIN2
VLS
SAI_LRCK
SAI_SCLK
SAI_SDOUT
OMCK
RMCK
Serial
Audio
Interface
Port
ADC
Serial
Data
Internal MCLK
Mult/Div
DEM
C&U Bit
Data Buffer
Format
Detector
MUTE
CS42526
114 dB, 192-kHz 6-Ch CODEC with S/PDIF Receiver
Features
Six 24-bit D/A, two 24-bit A/D Converters
114 dB DAC / 114 dB ADC Dynamic Range
-100 dB THD+N
System Sampling Rates up to 192 kHz
S/PDIF Receiver Compatible with EIAJ
CP1201 and IEC-60958
Recovered S/PDIF Clock or System Clock
Selection
8:2 S/PDIF Input MUX
ADC High-Pass Filter for DC Offset Calibration
Expandable ADC Channels and One-Line
Mode Support
Digital Output Volume Control with Soft Ramp
Digital ±15 dB Input Gain Adjust for ADC
Differential Analog Architecture
Supports Logic Levels between 1.8 V and 5 V
General Description
The CS42526 provides two analog-to-digital and six
digital-to-analog delta-sigma converters, as well as an
integrated S/PDIF receiver.
The CS42526 integrated S/PDIF receiver supports up
to eight inputs, clock recovery circuitry and format autodetection. The internal stereo ADC is capable of independent channel gain control for single-ended or
differential analog inputs. All six channels of DAC provide digital volume control and differential analog
outputs. The general-purpose outputs may be driven
high or low, or mapped to a variety of DAC mute controls or ADC overflow indicators.
The CS42526 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such
as A/V receivers, DVD receivers, and digital speakers.
The CS42526 is available in a 64-pin LQFP package in
Commercial (-10° to +70° C) grades. The CDB42528
Customer Demonstration board is also available for device evaluation. Refer to “Ordering Information” on
page 90.
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2014
(All Rights Reserved)
MAR '14
DS585F2
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6
SPECIFIED OPERATING CONDITIONS ............................................................................................... 6
ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 6
ANALOG INPUT CHARACTERISTICS .................................................................................................. 7
A/D DIGITAL FILTER CHARACTERISTICS .......................................................................................... 8
ANALOG OUTPUT CHARACTERISTICS .............................................................................................. 9
D/A DIGITAL FILTER CHARACTERISTICS ........................................................................................ 10
SWITCHING CHARACTERISTICS ......................................................................................................11
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C™ FORMAT ........................................... 12
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 14
DIGITAL INTERFACE CHARACTERISTICS ....................................................................................... 15
2. PIN DESCRIPTIONS ............................................................................................................................ 16
3. TYPICAL CONNECTION DIAGRAM ............................................................................................. 19
4. APPLICATIONS ................................................................................................................................... 20
4.1 Overview ......................................................................................................................................... 20
4.2 Analog Inputs .................................................................................................................................. 20
4.2.1 Line-Level Inputs ................................................................................................................... 20
4.2.2 High-Pass Filter and DC Offset Calibration ........................................................................... 21
4.3 Analog Outputs ............................................................................................................................... 21
4.3.1 Line-Level Outputs and Filtering ........................................................................................... 21
4.3.2 Interpolation Filter .................................................................................................................. 21
4.3.3 Digital Volume and Mute Control ........................................................................................... 22
4.3.4 ATAPI Specification ............................................................................................................... 22
4.4 S/PDIF Receiver ............................................................................................................................. 23
4.4.1 8:2 S/PDIF Input Multiplexer ................................................................................................. 23
4.4.2 Error Reporting and Hold Function ........................................................................................23
4.4.3 Channel Status Data Handling .............................................................................................. 23
4.4.4 User Data Handling ............................................................................................................... 23
4.4.5 Non-Audio Auto-Detection ..................................................................................................... 23
4.5 Clock Generation ............................................................................................................................ 24
4.5.1 PLL and Jitter Attenuation ..................................................................................................... 24
4.5.2 OMCK System Clock Mode ...................................................................................................25
4.5.3 Master Mode ......................................................................................................................... 25
4.5.4 Slave Mode ........................................................................................................................... 25
4.6 Digital Interfaces ............................................................................................................................. 26
4.6.1 Serial Audio Interface Signals ............................................................................................... 26
4.6.2 Serial Audio Interface Formats .............................................................................................. 28
4.6.3 ADCIN1/ADCIN2 Serial Data Format .................................................................................... 31
4.6.4 One-Line Mode (OLM) Configurations .................................................................................. 32
4.6.4.1 OLM Config #1 ........................................................................................................... 32
4.6.4.2 OLM Config #2 ........................................................................................................... 33
4.6.4.3 OLM Config #3 ........................................................................................................... 34
4.6.4.4 OLM Config #4 ........................................................................................................... 35
4.6.4.5 OLM Config #5 ........................................................................................................... 36
4.7 Control Port Description and Timing ............................................................................................... 37
4.7.1 SPI Mode ............................................................................................................................... 37
4.7.2 I²C Mode ................................................................................................................................ 38
4.8 Interrupts ........................................................................................................................................ 39
4.9 Reset and Power-Up ...................................................................................................................... 39
4.10 Power Supply, Grounding, and PCB Layout ................................................................................ 39
5. REGISTER QUICK REFERENCE ........................................................................................................ 41
CS42526
™
FORMAT .......................................... 13
2 DS585F2
CS42526
6. REGISTER DESCRIPTION .................................................................................................................. 45
6.1 Memory Address Pointer (MAP) ..................................................................................................... 45
6.2 Chip I.D. and Revision Register (address 01h) (Read Only) .......................................................... 45
6.3 Power Control (address 02h) .......................................................................................................... 46
6.4 Functional Mode (address 03h) ...................................................................................................... 47
6.5 Interface Formats (address 04h) .................................................................................................... 49
6.6 Misc Control (address 05h) ............................................................................................................ 50
6.7 Clock Control (address 06h) ........................................................................................................... 52
6.8 OMCK/PLL_CLK Ratio (address 07h) (Read Only) ....................................................................... 53
6.9 RVCR Status (address 08h) (Read Only) ....................................................................................... 54
6.10 Burst Preamble PC and PD Bytes (addresses 09h - 0Ch)(Read Only) ........................................ 55
6.11 Volume Transition Control (address 0Dh) .................................................................................... 56
6.12 Channel Mute (address 0Eh) ........................................................................................................ 58
6.13 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h) ...................................................... 58
6.14 Channel Invert (address 17h) ....................................................................................................... 58
6.15 Mixing Control Pair 1 (Channels A1 & B1) (address 18h)
Mixing Control Pair 2 (Channels A2 & B2) (address 19h)
Mixing Control Pair 3 (Channels A3 & B3) (address 1Ah) ............................................................ 58
6.16 ADC Left Channel Gain (address 1Ch) ........................................................................................ 61
6.17 ADC Right Channel Gain (address 1Dh) ......................................................................................61
6.18 Receiver Mode Control (address 1Eh) ......................................................................................... 61
6.19 Receiver Mode Control 2 (address 1Fh) ...................................................................................... 63
6.20 Interrupt Status (address 20h) (Read Only) ................................................................................. 63
6.21 Interrupt Mask (address 21h) ....................................................................................................... 64
6.22 Interrupt Mode MSB (address 22h)
Interrupt Mode LSB (address 23h) ...............................................................................................65
6.23 Channel Status Data Buffer Control (address 24h) ...................................................................... 65
6.24 Receiver Channel Status (address 25h) (Read Only) .................................................................. 66
6.25 Receiver Errors (address 26h) (Read Only) .................................................................................67
6.26 Receiver Errors Mask (address 27h) ............................................................................................ 68
6.27 Mutec Pin Control (address 28h) .................................................................................................. 69
6.28 RXP/General-Purpose Pin Control (addresses 29h to 2Fh) ......................................................... 69
6.29 Q-Channel Subcode Bytes 0 to 9 (addresses 30h to 39h) (Read Only) ....................................... 71
6.30 C-Bit or U-Bit Data Buffer (addresses 3Ah to 51h) (Read Only) .................................................. 71
7. PARAMETER DEFINITIONS ................................................................................................................ 72
8. APPENDIX A: EXTERNAL FILTERS ................................................................................................... 73
8.1 ADC Input Filter .............................................................................................................................. 73
8.2 DAC Output Filter ........................................................................................................................... 73
9. APPENDIX B: S/PDIF RECEIVER ....................................................................................................... 74
9.1 Error Reporting and Hold Function ................................................................................................. 74
9.2 Channel Status Data Handling ....................................................................................................... 74
9.2.1 Channel Status Data E Buffer Access ................................................................................... 75
9.2.1.1 One-Byte Mode ..........................................................................................................75
9.2.1.2 Two-Byte Mode ..........................................................................................................75
9.2.2 Serial Copy Management System (SCMS) ........................................................................... 76
9.3 User (U) Data E Buffer Access ....................................................................................................... 76
9.3.1 Non-Audio Auto-Detection ..................................................................................................... 76
9.3.1.1 Format Detection .......................................................................................................76
10. APPENDIX C: PLL FILTER ....................................................................................................
10.1 External Filter Components .......................................................................................................... 77
10.1.1 General ................................................................................................................................ 77
10.1.2 Jitter Attenuation ................................................................................................................. 79
10.1.3 Capacitor Selection ............................................................................................................. 80
10.1.4 Circuit Board Layout ............................................................................................................ 81
............ 77
DS585F2 3
11. APPENDIX D: EXTERNAL AES3-S/PDIF-IEC60958 RECEIVER COMPONENTS .......................... 82
11.1 AES3 Receiver External Components .......................................................................................... 82
12. APPENDIX E: ADC FILTER PLOTS .................................................................................................. 83
13. APPENDIX F: DAC FILTER PLOTS .................................................................................................. 85
14. PACKAGE DIMENSIONS ............................................................................................................... 89
THERMAL CHARACTERISTICS .......................................................................................................... 89
15. ORDERING INFORMATION .............................................................................................................. 90
16. REFERENCES .................................................................................................................................... 90
17. REVISION HISTORY ......................................................................................................................... 91
LIST OF FIGURES
Figure 1. Serial Audio Port Master Mode Timing ...................................................................................... 11
Figure 2. Serial Audio Port Slave Mode Timing ........................................................................................ 11
Figure 3. Control Port Timing - I²C Format ................................................................................................ 12
Figure 4. Control Port Timing - SPI Format ............................................................................................... 13
Figure 5. Typical Connection Diagram ...................................................................................................... 19
Figure 6. Full-Scale Analog Input .............................................................................................................. 20
Figure 7. Full-Scale Output ....................................................................................................................... 21
Figure 8. ATAPI Block Diagram (x = channel pair 1, 2, or 3) ....................................................................22
Figure 9. CS42526 Clock Generation ....................................................................................................... 24
Figure 10. I²S Serial Audio Formats .......................................................................................................... 28
Figure 11. Left-Justified Serial Audio Formats .......................................................................................... 29
Figure 12. Right-Justified Serial Audio Formats ........................................................................................ 29
Figure 13. One Line Mode #1 Serial Audio Format ................................................................................... 30
Figure 14. One Line Mode #2 Serial Audio Format ................................................................................... 30
Figure 15. ADCIN1/ADCIN2 Serial Audio Format ..................................................................................... 31
Figure 16. OLM Configuration #1 .............................................................................................................. 32
Figure 17. OLM Configuration #2 .............................................................................................................. 33
Figure 18. OLM Configuration #3 .............................................................................................................. 34
Figure 19. OLM Configuration #4 .............................................................................................................. 35
Figure 20. OLM Configuration #5 .............................................................................................................. 36
Figure 21. Control Port Timing in SPI Mode ............................................................................................. 37
Figure 22. Control Port Timing, I²C Write .................................................................................................. 38
Figure 23. Control Port Timing, I²C Read .................................................................................................. 38
Figure 24. Recommended Analog Input Buffer ......................................................................................... 73
Figure 25. Recommended Analog Output Buffer ...................................................................................... 73
Figure 26. Channel Status Data Buffer Structure ...................................................................................... 75
Figure 27. PLL Block Diagram .................................................................................................................. 77
Figure 28. Jitter-Attenuation Characteristics of PLL - Configurations 1 & 2 .............................................. 79
Figure 29. Jitter-Attenuation Characteristics of PLL - Configuration 3 ...................................................... 79
Figure 30. Recommended Layout Example .............................................................................................. 81
Figure 31. Consumer Input Circuit ............................................................................................................ 82
Figure 32. S/PDIF MUX Input Circuit ........................................................................................................ 82
Figure 33. TTL/CMOS Input Circuit ........................................................................................................... 82
Figure 34. Single-Speed Mode Stopband Rejection ................................................................................. 83
Figure 35. Single-Speed Mode Transition Band ....................................................................................... 83
Figure 36. Single-Speed Mode Transition Band (Detail) ........................................................................... 83
Figure 37. Single-Speed Mode Passband Ripple ..................................................................................... 83
Figure 38. Double-Speed Mode Stopband Rejection ................................................................................83
Figure 39. Double-Speed Mode Transition Band ...................................................................................... 83
Figure 40. Double-Speed Mode Transition Band (Detail) ......................................................................... 84
Figure 41. Double-Speed Mode Passband Ripple .................................................................................... 84
Figure 42. Quad-Speed Mode Stopband Rejection ..................................................................................84
CS42526
4 DS585F2
CS42526
Figure 43. Quad-Speed Mode Transition Band ........................................................................................ 84
Figure 44. Quad-Speed Mode Transition Band (Detail) ............................................................................84
Figure 45. Quad-Speed Mode Passband Ripple ...................................................................................... 84
Figure 46. Single-Speed (fast) Stopband Rejection .................................................................................. 85
Figure 47. Single-Speed (fast) Transition Band ........................................................................................ 85
Figure 48. Single-Speed (fast) Transition Band (detail) ............................................................................ 85
Figure 49. Single-Speed (fast) Passband Ripple ...................................................................................... 85
Figure 50. Single-Speed (slow) Stopband Rejection ................................................................................ 85
Figure 51. Single-Speed (slow) Transition Band ....................................................................................... 85
Figure 52. Single-Speed (slow) Transition Band (detail) ........................................................................... 86
Figure 53. Single-Speed (slow) Passband Ripple ..................................................................................... 86
Figure 54. Double-Speed (fast) Stopband Rejection ................................................................................ 86
Figure 55. Double-Speed (fast) Transition Band ....................................................................................... 86
Figure 56. Double-Speed (fast) Transition Band (detail) ........................................................................... 86
Figure 57. Double-Speed (fast) Passband Ripple ..................................................................................... 86
Figure 58. Double-Speed (slow) Stopband Rejection ............................................................................... 87
Figure 59. Double-Speed (slow) Transition Band ..................................................................................... 87
Figure 60. Double-Speed (slow) Transition Band (detail) ......................................................................... 87
Figure 61. Double-Speed (slow) Passband Ripple ................................................................................... 87
Figure 62. Quad-Speed (fast) Stopband Rejection ................................................................................... 87
Figure 63. Quad-Speed (fast) Transition Band ......................................................................................... 87
Figure 64. Quad-Speed (fast) Transition Band (detail) ............................................................................. 88
Figure 65. Quad-Speed (fast) Passband Ripple ....................................................................................... 88
Figure 66. Quad-Speed (slow) Stopband Rejection .................................................................................. 88
Figure 67. Quad-Speed (slow) Transition Band ........................................................................................ 88
Figure 68. Quad-Speed (slow) Transition Band (detail) ............................................................................ 88
Figure 69. Quad-Speed (slow) Passband Ripple ...................................................................................... 88
LIST OF TABLES
Table 1. Common OMCK Clock Frequencies ............................................................................................ 25
Table 2. Common PLL Output Clock Frequencies..................................................................................... 25
Table 3. Slave Mode Clock Ratios ............................................................................................................. 26
Table 4. Serial Audio Port Channel Allocations ......................................................................................... 27
Table 5. DAC De-Emphasis ....................................................................................................................... 48
Table 6. Receiver De-Emphasis ................................................................................................................ 48
Table 7. Digital Interface Formats .............................................................................................................. 49
Table 8. ADC One-Line Mode.................................................................................................................... 49
Table 9. DAC One-Line Mode.................................................................................................................... 49
Table 10. RMCK Divider Settings .............................................................................................................. 52
Table 11. OMCK Frequency Settings ........................................................................................................ 52
Table 12. Master Clock Source Select....................................................................................................... 53
Table 13. AES Format Detection ............................................................................................................... 54
Table 14. Receiver Clock Frequency Detection......................................................................................... 55
Table 15. Example Digital Volume Settings ............................................................................................... 58
Table 16. ATAPI Decode ........................................................................................................................... 60
Table 17. Example ADC Input Gain Settings ............................................................................................. 61
Table 18. TXP Output Selection................................................................................................................. 63
Table 19. Receiver Input Selection ............................................................................................................ 63
Table 20. Auxiliary Data Width Selection ................................................................................................... 66
Table 21. External PLL Component Values & Locking Modes .................................................................. 77
DS585F2 5
CS42526
1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltages
and T
= 25° C.)
A
SPECIFIED OPERATING CONDITIONS
(AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz; Master Mode)
Parameter Symbol Min Typ Max Units
DC Power Supply Analog
Digital
Serial Port Interface
Control Port Interface
Ambient Operating Temperature (power applied)
VA / VARX
VD
VLS
VLC
T
A
4.75
3.13
1.8
1.8
-10 - +70 C
5.0
3.3
5.0
5.0
5.25
5.25
5.25
5.25
V
V
V
V
ABSOLUTE MAXIMUM RATINGS
(AGND = DGND = 0 V; all voltages with respect to ground.)
Parameters Symbol Min Max Units
DC Power Supply Analog
Digital
Serial Port Interface
Control Port Interface
Input Current (Note 1)
Analog Input Voltage (Note 2)
Digital Input Voltage Serial Port Interface
(Note 2) Control Port Interface
S/PDIF interface
Ambient Operating Temperature(power applied)
Storage Temperature
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
VA / VA R X
VD
VLS
VLC
I
in
V
IN
V
IND-S
V
IND-C
V
IND-SP
T
A
T
A
T
stg
-0.3
-0.3
-0.3
-0.3
-±10mA
6.0
6.0
6.0
6.0
V
V
V
V
AGND-0.7 VA+0.7 V
-0.3
-0.3
-0.3
-20
-50
-65 +150 °C
VLS+ 0.4
VLC+ 0.4
VAR X+0.4
+85
+95
V
V
V
°C
°C
Notes:
1. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
2. The maximum over/under voltage is limited by the input current.
6 DS585F2
CS42526
ANALOG INPUT CHARACTERISTICS
(TA = 25° C; VA =VARX= 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5 V; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Full-scale input sine wave, 997 Hz.;
PDN_RCVR = 1; SW_CTRL[1:0] = ‘01’; OMCK = 12.288 MHz; Single-Speed Mode CX_SCLK = 3.072 MHz; Double-Speed Mode CX_SCLK = 6.144 MHz; Quad-Speed Mode CX_SCLK = 12.288 MHz.)
Parameter Symbol Min Typ Max Unit
Single-Speed Mode (Fs=48 kHz)
Dynamic Range A-weighted
unweighted
Total Harmonic Distortion + Noise
(Note 3) -1 dB
-20 dB
-60 dB
Double-Speed Mode (Fs=96 kHz)
Dynamic Range A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
(Note 3) -1 dB
-20 dB
-60 dB
40 kHz bandwidth -1 dB
Quad-Speed Mode (Fs=192 kHz)
Dynamic Range A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion+ Noise
(Note 3) -1 dB
-20 dB
-60 dB
40 kHz bandwidth -1 dB
Dynamic Performance for All Modes
Interchannel Isolation
Interchannel Phase Deviation
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
Offset Error HPF_FREEZE disabled
HPF_FREEZE enabled
Analog Input
Full-scale Differential Input Voltage
Input Impedance (Differential) (Note 4)
Common Mode Rejection Ratio
THD+N
THD+N
THD+N
CMRR - 82 - dB
108
105
-
-
-
108
105
-
-
-
-
-
108
105
-
-
-
-
-
-110- dB
- 0.0001 - Degree
-0.1-dB
- +/-100 - ppm/°C
-
-
1.05 VA 1.10 VA 1.16 VA Vpp
17 - - k
114
111
-100
-91
-51
114
111
108
-100
-91
-51
-97
114
111
108
-100
-91
-51
-97
0
100
-94
-94
-94
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
LSB
LSB
Notes:
3. Referred to the typical full-scale voltage.
4. Measured between AIN+ and AIN-
DS585F2 7
A/D DIGITAL FILTER CHARACTERISTICS
Parameter Symbol Min Typ Max Unit
Single-Speed Mode (2 to 50 kHz sample rates)
Passband (-0.1 dB) (Note 5)
Passband Ripple
Stopband (Note 5)
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
Group Delay Variation vs. Frequency
Double-Speed Mode (50 to 100 kHz sample rates)
Passband (-0.1 dB) (Note 5)
Passband Ripple
Stopband (Note 5)
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
Group Delay Variation vs. Frequency
Quad-Speed Mode (100 to 192 kHz sample rates)
Passband (-0.1 dB) (Note 5)
Passband Ripple
Stopband (Note 5)
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
Group Delay Variation vs. Frequency
High-Pass Filter Characteristics
Frequency Response -3.0 dB
-0.13 dB (Note 6)
Phase Deviation @ 20 Hz (Note 6)
Passband Ripple
Filter Setting Time
t
t
t
CS42526
0 - 0.47 Fs
--0.035 dB
0.58 - - Fs
-95 - - dB
t
gd
gd
t
gd
gd
t
gd
gd
-12/Fs- s
--0.0s
0 - 0.45 Fs
--0.035 dB
0.68 - - Fs
-92 - - dB
-9/Fs- s
--0.0s
0 - 0.24 Fs
--0.035 dB
0.78 - - Fs
-97 - - dB
-5/Fs- s
--0.0s
-120-
-
-10-Deg
--0dB
-10
5
/Fs - s
Hz
Hz
Notes:
5. The filter frequency response scales precisely with Fs.
6. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.
8 DS585F2
CS42526
ANALOG OUTPUT CHARACTERISTICS
(TA = 25° C; VA =VARX= 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5V; Measure-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
=
L
ment Bandwidth 10 Hz to 20 kHz unless otherwise specified.; Full-scale output 997 Hz sine wave, Test load R
3k, C
= 30 pF; PDN_RCVR = 1; SW_CTRL[1:0] = ‘01’; OMCK = 12.288 MHz; Single-Speed Mode, CX_SCLK =
L
3.072 MHz; Double-Speed Mode, CX_SCLK = 6.144 MHz; Quad-Speed Mode, CX_SCLK = 12.288 MHz.)
Parameter Symbol Min Typ Max Unit
Dynamic performance for all modes
Dynamic Range (Note 7)
24-bit A-Weighted
unweighted
16-bit A-Weighted
(Note 8) unweighted
Total Harmonic Distortion + Noise
24-bit 0 dB
-20 dB
-60 dB
16-bit 0 dB
(Note 8) -20 dB
-60 dB
Idle Channel Noise/Signal-to-Noise Ratio (A-Weighted)
Interchannel Isolation (1 kHz)
THD+N
108
105
-
-
-
-
-
-
-
-
-114 - dB
-90 -dB
114
111
97
94
-100
-91
-51
-94
-74
-34
-
-
-
-
-94
-
-
-
-
Analog Output Characteristics for all modes
Unloaded Full-Scale Differential Output Voltage
Interchannel Gain Mismatch
Gain Drift
Output Impedance
AC-Load Resistance
Load Capacitance
Z
V
OUT
R
C
.89 VA .94 VA .99 VA Vpp
FS
-0.1 - dB
- 300 - ppm/°C
- 150 -
L
L
3- -k
- - 30 pF
Notes:
7. One LSB of triangular PDF dither is added to data.
8. Performance limited by 16-bit quantization noise.
DS585F2 9
D/A DIGITAL FILTER CHARACTERISTICS
Fast Roll-Off Slow Roll-Off
Parameter
Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz
Passband (Note 9) to -0.01 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation (Note 10)
Group Delay
Passband Group Delay Deviation 0 - 20 kHz
De-emphasis Error (Note 11) Fs = 32 kHz
(Relative to 1 kHz) Fs = 44.1 kHz
Fs = 48 kHz
Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz
Passband (Note 9) to -0.01 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation (Note 10)
Group Delay
Passband Group Delay Deviation 0 - 20 kHz
Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz
Passband (Note 9) to -0.01 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation (Note 10)
Group Delay
Passband Group Delay Deviation 0 - 20 kHz
0
0
-0.01 - +0.01 -0.01 - +0.01 dB
0.5465 - - 0.5834 - - Fs
90 - - 64 - - dB
- 12/Fs - - 6.5/Fs - s
- - ±0.41/Fs - ±0.14/Fs s
-
-
-
0
0
-0.01 - 0.01 -0.01 - 0.01 dB
0.5834 - - 0.7917 - - Fs
80 - - 70 - - dB
- 4.6/Fs - - 3.9/Fs - s
- - ±0.03/Fs - ±0.01/Fs s
0
0
-0.01 - 0.01 -0.01 - 0.01 dB
0.6355 - - 0.8683 - - Fs
90 - - 75 - - dB
- 4.7/Fs - - 4.2/Fs - s
- - ±0.01/Fs - ±0.01/Fs s
-
-
-
-
-
-
-
-
-
0.4535
0.4998
±0.23
±0.14
±0.09
0.4166
0.4998
0.1046
0.4897
0
0
-
-
-
0
0
0
0
CS42526
UnitMin Typ Max Min Typ Max
-
-
-
-
-
-
-
-
-
0.4166
0.4998FsFs
±0.23
±0.14
±0.09
0.2083
0.4998FsFs
0.1042
0.4813FsFs
dB
dB
dB
Notes:
9. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 46 to 69) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
10. Single- and Double-Speed Mode Measurement Bandwidth is from stopband to 3 Fs.
Quad-Speed Mode Measurement Bandwidth is from stopband to 1.34 Fs.
11. De-emphasis is available only in Single-Speed Mode.
10 DS585F2
CS42526
CX_SCLK
SAI_SCLK
(output)
RMCK
t
smd
t
lmd
CX_LRCK
SAI_LRCK
(output)
sckh
sckl
t
t
MSB
MSB-1
t
dpd
CX_SDOUT
SAI_SDOUT
CX_SDINx
dh
t
ds
t
lrpd
t
lrck
t
CX_SCLK
SAI_SCLK
(input)
CX_LRCK
SAI_LRCK
(input)
Figure 1. Serial Audio Port Master Mode Timing Figure 2. Serial Audio Port Slave Mode Timing
SWITCHING CHARACTERISTICS
(TA = -10 to +70° C; VA=VARX = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 =
VLS, C
RST Pin Low Pulse Width (Note 12)
PLL Clock Recovery Sample Rate Range
RMCK Output Jitter (Note 14)
RMCK Output Duty Cycle (Note 15)
OMCK Frequency (Note 13)
OMCK Duty Cycle (Note 13)
CX_SCLK, SAI_SCLK Duty Cycle
CX_LRCK, SAI_LRCK Duty Cycle
Master Mode
RMCK to CX_SCLK, SAI_SCLK active edge delay
RMCK to CX_LRCK, SAI_LRCK delay
Slave Mode
CX_SCLK, SAI_SCLK Falling Edge to CX_SDOUT,
SAI_SDOUT Output Valid
CX_LRCK, SAI_LRCK Edge to MSB Valid
CX_SDIN Setup Time Before CX_SCLK Rising Edge
CX_SDIN Hold Time After CX_SCLK Rising Edge
CX_SCLK, SAI_SCLK High Time
CX_SCLK, SAI_SCLK Low Time
CX_SCLK, SAI_SCLK falling to CX_LRCK, SAI_LRCK
Edge
= 30 pF)
L
Parameters Symbol Min Typ Max Units
1--ms
30 - 200 kHz
- 200 - ps RMS
45 50 55 %
1.024 - 25.600 MHz
40 50 60 %
45 50 55 %
45 50 55 %
t
smd
t
lmd
t
dpd
t
lrpd
t
ds
t
dh
t
sckh
t
sckl
t
lrck
0-15ns
0-15ns
- (Note 16) ns
-26.5ns
10 - - ns
30 - - ns
20 - - ns
20 - - ns
-25 - +25 ns
Notes:
12. After powering-up the CS42526, RST
should be held low after the power supplies and clocks are set-
tled.
13. See Table 1 on page 25 for suggested OMCK frequencies
14. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz.
15. Not valid when RMCK_DIV in “Clock Control (address 06h)” on page 52 is set to Multiply by 2.
16. 76.5 ns for Single-Speed and Double-Speed modes, 23 ns for Quad-Speed Mode.
DS585F2 11
CS42526
15
256 Fs
---------------------
15
128 Fs
---------------------
15
64 Fs
------------------
t
buf
t
hdst
t
low
t
hdd
t
high
t
sud
Stop Start
SDA
SCL
t
irs
RST
t
hdst
t
rc
t
fc
t
sust
t
susp
Start
Stop
Repeated
t
rd
t
fd
t
ack
Figure 3. Control Port Timing - I²C Format
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C™ FORMAT
(TA = -10 to +70° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic
1=VLC, C
SCL Clock Frequency
Rising Edge to Start
RST
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 17)
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling (Note 18)
=30pF)
L
Parameter Symbol Min Max Unit
f
scl
t
t
buf
t
hdst
t
low
t
high
t
sust
t
hdd
t
sud
t
t
t
susp
t
ack
irs
rc
fc
- 100 kHz
500 - ns
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
4.7 - µs
0-µs
250 - ns
-1µs
- 300 ns
4.7 - µs
- (Note 19) ns
Notes:
17. Data must be held for sufficient time to bridge the transition time, t
, of SCL.
fc
18. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
19. for Single-Speed Mode, for Double-Speed Mode, for Quad-Speed Mode
12 DS585F2
CS42526
t
r2
t
f2
t
dsu
t
dh
t
sch
t
scl
CS
CCLK
CDIN
t
css
t
pd
CDOUT
t
csh
Figure 4. Control Port Timing - SPI Format
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT
(TA = -10 to +70° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic
1=VLC, C
CCLK Clock Frequency (Note 20)
High Time Between Transmissions
CS
Falling to CCLK Edge
CS
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time (Note 21)
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN (Note 22)
Fall Time of CCLK and CDIN (Note 22)
Notes:
=30pF)
L
Parameter Symbol Min Typ Max Units
f
t
t
t
t
t
t
t
sck
csh
css
scl
sch
dsu
dh
pd
t
r1
t
f1
t
r2
t
f2
0-6.0MHz
1.0 - - s
20 - - ns
66 - - ns
66 - - ns
40 - - ns
15 - - ns
--50ns
--25ns
--25ns
--100ns
--100ns
20. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is
dictated by the timing requirements necessary to access the Channel Status and User Bit buffer
memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum
allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz should
be safe for all possible conditions.
21. Data must be held for sufficient time to bridge the transition time of CCLK.
22. For f
<1 MHz.
sck
DS585F2 13
DC ELECTRICAL CHARACTERISTICS
(TA = 25° C; AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz; Master Mode)
Parameter Symbol Min Typ Max Units
Power Supply Current normal operation, VA = VARX = 5 V
(Note 23) VD = 5 V
VD = 3.3 V
Interface current, VLC=5 V (Note 24)
VLS=5 V
power-down state (all supplies) (Note 25)
Power Consumption (Note 23)
VA=VARX=5 V, VD=VLS=VLC=3.3 V normal operation
power-down (Note 25)
VA=VARX=5 V, VD=VLS=VLC=5 V normal operation
power-down (Note 25)
Power Supply Rejection Ratio (Note 26) (1 kHz)
(60 Hz)
VQ Nominal Voltage
VQ Output Impedance
VQ Maximum allowable DC current
FILT+ Nominal Voltage
FILT+ Output Impedance
FILT+ Maximum allowable DC current
I
A
I
D
I
D
I
LC
I
LS
I
pd
PSRR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
75
85
51
250
13
250
587
1.25
866
1.25
60
40
2.7
50
0.01
5.0
35
0.01
-
-
-
-
-
-
650
-
960
-
-
-
-
-
-
-
-
-
CS42526
mA
mA
mA
A
mA
A
mW
mW
mW
mW
dB
dB
V
k
mA
V
k
mA
Notes:
23. Current consumption increases with increasing FS and increasing OMCK. Max values are based on
highest FS and highest OMCK. Variance between speed modes is negligible.
24. I
25. Power-Down Mode is defined as RST
measured with no external loading on the SDA pin.
LC
pin = Low with all clock and data lines held static.
26. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 5.
14 DS585F2
DIGITAL INTERFACE CHARACTERISTICS
(TA = +25° C)
Parameters (Note 27) Symbol Min Typ Max Units
High-Level Input Voltage Serial Port
Control Port
Low-Level Input Voltage Serial Port
Control Port
High-Level Output Voltage at I
Low-Level Output Voltage at I
Serial Port, Control Port, MUTEC, GPOx,TXP
High-Level Output Voltage at I
Low-Level Output Voltage at I
Input Sensitivity, RXP[7:0]
Input Leakage Current
Input Capacitance
MUTEC Drive Current
=2 mA (Note 28)Serial Port
o
Control Port
MUTEC, GPOx
TXP
=2 mA (Note 28)
o
=100 A (Note 28)Serial Port
o
Control Port
MUTEC, GPOx
TXP
=100 A (Note 28)Serial Port
o
Control Port
MUTEC, GPOx
TXP
CS42526
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
V
TH
I
in
0.7xVLS
0.7xVLC
-
-
VLS-1.0
VLC-1.0
VA- 1.0
VD-1.0
-
-
-
-
-
-
-
-
-
-
0.2xVLS
0.2xVLC
-
-
-
-
V
V
V
V
V
V
V
V
--0.4V
0.8xVLS
0.8xVLC
0.8xVA
0.8xVD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.2xVLS
0.2xVLC
0.2xVA
0.2xVD
V
V
V
V
V
V
V
V
- 150 200 mVpp
--±10A
-8-pF
-3-mA
Notes:
27. Serial Port signals include: RMCK, OMCK, SAI_SCLK, SAI_LRCK, SAI_SDOUT, CX_SCLK, CX_LRCK, CX_SDOUT, CX_SDIN1-3, ADCI N 1/2 Con t rol
Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS
, AD1/CDIN, INT, RST S/PDIF-
GPO Interface signals include: RXP0, RXP/GPO[1:7]
28. When operating RMCK above 24.576 MHz, limit the loading on the signal to 1 CMOS load.
DS585F2 15
2. PIN DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CX_SDIN1
SAI_SCLK
SAI_LRCK
VD
DGND
VLC
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS
INT
RST
AINR-
AINR+
AINL+
AINL-
VQ
FILT+
REFGND
NCNCNC
NC
VA
AGND
AOUTB3-
AOUTB3+
AOUTA3+
AOUTA3-
AOUTB2-
AOUTB2+
AOUTA2+
AOUTA2-
AOUTB1-
AOUTB1+
AOUTA1+
AOUTA1-
MUTEC
AGND
VARX
RXP7/GPO7
RXP6/GPO6
RXP5/GPO5
RXP4/GPO4
RXP3/GPO3
RXP2/GPO2
RXP1/GPO1
LPFLT
RXP0
TXP
VD
DGND
VLS
SAI_SDOUT
RMCK
CX_SDOUT
ADCIN2
ADCIN1
OMCK
CX_LRCK
CX_SCLK
TEST
CX_SDIN3
CX_SDIN2
CS42518
CS42526
Pin Name # Pin Description
CX_SDIN1
CX_SDIN2
CX_SDIN3
CX_SCLK
CX_LRCK
VD
DGND
VLC
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS
16 DS585F2
1
Codec Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
64
63
CODEC Serial Clock (Input/Output) - Serial clock for the CODEC serial audio interface.
2
3
CODEC Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on
the CODEC serial audio data line.
4
Digital Power (Input) - Positive power supply for the digital section.
51
5
Digital Ground (Input) - Ground reference. Should be connected to digital ground.
52
6
Control Port Power (Input) - Determines the required signal level for the control port.
Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up
7
resistor to the logic interface voltage in I²C mode as shown in the Typical Connection Diagram.
Serial Control Data (Input/Output) - SDA is a data I/O line in I²C mode and requires an external pull-up
8
resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDOUT is the output
data line for the control port interface in SPI mode.
Address Bit 1 (I²C)/Serial Control Data (SPI) (Input) - AD1 is a chip address pin in I²C mode; CDIN is
9
the input data line for the control port interface in SPI mode.
Address Bit 0 (I²C)/Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C mode; CS
10
is the chip select signal in SPI mode.
INT
RST
AINRAINR+
AINL+
AINL-
VQ
FILT+
REFGND
NC
AOUTA1 +,AOUTB1 +,AOUTA2 +,AOUTB2 +,AOUTA3 +,AOUTB3 +,-
VA
VAR X
AGND
MUTEC
LPFLT
RXP7/GPO7
RXP6/GPO6
RXP5/GPO5
RXP4/GPO4
RXP3/GPO3
RXP2/GPO2
RXP1/GPO1
RXP0
TXP
VLS
SAI_SDOUT
RMCK
CX_SDOUT
Interrupt (Output) - The CS42526 will generate an interrupt condition as per the Interrupt Mask register.
11
See “Interrupts” on page 39 for more details.
Reset (Input) - The device enters a low power mode and all internal registers are reset to their default
12
settings when low.
13
Differential Right Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma
14
modulators via the AINR+/- pins.
15
Differential Left Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma
16
modulators via the AINL+/- pins.
17
Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
18
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
19
Reference Ground (Input) - Ground reference for the internal sampling circuits.
20
21
No Connect Pins - Do not make any connection to these pins.
22
23
36,37
35,34
32,33
Differential Analog Output (Output) - The full-scale differential analog output level is specified in the
31,30
Analog Characteristics specification table.
28,29
27,26
24
Analog Power (Input) - Positive power supply for the analog section.
41
25
Analog Ground (Input) - Ground reference. Should be connected to analog ground.
40
Mute Control (Output) - The Mute Control pin outputs high impedance following an initial power-on con-
dition or whenever the PDN bit is set to a ‘1’, forcing the codec into power-down mode. The signal will
remain in a high impedance state as long as the part is in power-down mode. The Mute Control pin goes
38
to the selected “active” state during reset, muting, or if the master clock to left/right clock frequency ratio
is incorrect. This pin is intended to be used as a control for external mute circuits to prevent the clicks
and pops that can occur in any single supply system. The use of external mute circuits are not manda-
tory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops.
39
PLL Loop Filter (Output) - An RC network should be connected between this pin and ground.
42
S/PDIF Receiver Input/ General Purpose Output (Input/Output) - Receiver inputs for S/PDIF encoded
43
data. The CS42526 has an internal 8:2 multiplexer to select the active receiver port, according to the
44
Receiver Mode Control 2 register. These pins can also be configured as general purpose output pins,
45
ADC Overflow indicators or Mute Control outputs according to the RXP/General Purpose Pin Control
46
registers.
47
48
S/PDIF Receiver Input (Input) - Dedicated receiver input for S/PDIF encoded data.
49
S/PDIF Transmitter Output (Output) - S/PDIF encoded data output, mapped directly from one of the
50
receiver inputs as indicated by the Receiver Mode Control 2 register.
53
Serial Port Interface Power (Input) - Determines the required signal level for the serial port interfaces.
Serial Audio Interface Serial Data Output (Output) - Output for two’s complement serial audio PCM
54
data from the S/PDIF incoming stream. This pin can also be configured to transmit the output of the inter-
nal and external ADCs.
Recovered Master Clock (Output) - Recovered master clock output from the External Clock Reference
55
(OMCK, pin 59) or the PLL which is locked to the incoming S/PDIF stream or CX_LRCK.
CODEC Serial Data Output (Output) - Output for two’s complement serial audio data from the internal
56
and external ADCs.
CS42526
DS585F2 17
ADCIN1
ADCIN2
OMCK
TEST
SAI_LRCK
SAI_SCLK
CS42526
External ADC Serial Input (Input) - The CS42526 provides for up to two external stereo analog to digital
58
converter inputs to provide a maximum of six channels on one serial data output line when the CS42526
57
is placed in One-Line Mode.
External Reference Clock (Input) - External clock reference that must be within the ranges specified in
59
the register “OMCK Frequency (OMCK Freqx)” on page 52.
62
Test Pin (Input) - This pin must be connected to DGND.
Serial Audio Interface Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is
60
currently active on the serial audio data line.
Serial Audio Interface Serial Clock (Input/Output) - Serial clock for the Serial Audio Interface.
61
18 DS585F2
3. TYPICAL CONNECTION DIAGRAM
VD
AOUTA1+
24
0.1 µF
+
10 µF
100 µF
0.1 µF
+
+
17
18
VQ
FILT+
36
37
0.1 µF
4.7 µF
VA
+
10 µF
51
AOUTA1-
AOUTB1+
35
34
AOUTB1-
AOUTA2+
32
33
AOUTA2-
AOUTB2+
31
30
AOUTB2-
AOUTA3+
28
29
AOUTA3-
AOUTB3+
27
26
AOUTB3-
MUTEC
38
25
DGND
DGND
5
REFGND
19
41
4
VAVD
0.1 µF
AGNDAGND
52 40
LPFLT
39
AINL+
AINL-
AINR+
AINR-
15
16
14
13
Connect DGN D and AG ND at single point near Codec
0.01 µF
0.1 µF
+
10 µF
+5 V
0.01 µF
0.01 µF
+3.3 V to +5 V
+
10 µF
0.1 µF 0.01 µF
VLS
0.1 µF
+2.5 V
to + 5 V
53
VLC
0.1 µF
+1.8 V
to + 5 V
6
3
60
59
1
64
61
2
63
8
7
SCL/CCLK
SDA/CDOUT
AD1/CDIN
RST
12
9
OMCK
CX_SDIN1
SAI_LRCK
SAI_S CLK
CX_SDIN3
CX_SDIN2
CX_LRCK
CX_SCLK
AD0/CS
10
INT
11
Digital Audio
Processor
Micro-
Controller
55
RMCK
58
ADCIN1
57
ADCIN2
CS5361
A/D Converter
CS5361
A/D Converter
56
CX_SDOUT
54
SAI_SDOUT
48
46
49
44
45
47
RXP0
RXP1/GPO1
S/PDIF
Inte rfac e
50
TXP
Driver
Up to 8
Sources
43
RXP2/GPO2
RXP3/GPO3
RXP4/GPO4
RXP5/GPO5
RXP6/GPO6
RXP7/GPO7
42
OSC
Analog Output Buffer
2
and
Mute Circuit (optional)
Mute
Drive
(optional)
2700 pF*
2700 pF*
Left Analog Input
Right Analog Input
Analog
Input
Buffer
1
Analog
Input
Buffer
1
+VA
*
* Pull up or dow n as
required on startup if the
M ute Co n trol is us ed .
*
Analog Output Buffer
2
and
Mute Circuit (optional)
Analog Output Buffer
2
and
Mute Circuit (optional)
Analog Output Buffer
2
and
Mute Circuit (optional)
Analog Output Buffer
2
and
Mute Circuit (optional)
Analog Output Buffer
2
and
Mute Circuit (optional)
2 k 2 k
** **
CFILT
3
RFILT
3
CRIP
3
** Resistors are required for
I
2
C control port operation
1. See the ADC Input Filter section in the Appendix.
2. See the DAC O utput Filter section in the A ppendix.
3. See the PLL Filter section in the Appendix.
62
TEST
Figure 5. Typical Connection Diagram
CS42518
CS42526
DS585F2 19
4. APPLICATIONS
AIN+
AIN-
Full-Scale Input Level= (AIN+) - (AIN-)= 5.6 Vpp
4.1 V
2.7 V
1.3 V
4.1 V
2.7 V
1.3 V
Figure 6. Full-Scale Analog Input
4.1 Overview
The CS42526 is a highly integrated mixed-signal 24-bit audio codec comprised of 2 analog-to-digital converters (ADC), implemented using multi-bit delta-sigma techniques, 6 digital-to-analog converters (DAC)
and a 192 kHz digital audio S/PDIF receiver. Other functions integrated within the codec include independent digital volume controls for each DAC, digital de-emphasis filters for DAC and S/PDIF, digital gain control for ADC channels, ADC high-pass filters, an on-chip voltage reference, and an 8:2 mux for S/PDIF
sources. All serial data is transmitted through two configurable serial audio interfaces with standard serial
interface support as well as enhanced one-line modes of operation, allowing up to 6 channels of serial audio
data on one data line. All functions are configured through a serial control port operable in SPI mode or in
I²C mode. 5 show the recommended connections for the CS42526.
The CS42526 operates in one of three oversampling modes based on the input sample rate. Mode selection
is determined by the FM bits in register “Functional Mode (address 03h)” on page 47. Single-Speed Mode
(SSM) supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed Mode
(DSM) supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed
Mode (QSM) supports input sample rates up to 192 kHz and uses an oversampling ratio of 32x.
Using the receiver clock recovery PLL, a low-jitter clock is recovered from the incoming S/PDIF data stream.
The recovered clock or an externally supplied clock attached to the OMCK pin can be used as the System
Clock.
CS42526
4.2 Analog Inputs
4.2.1 Line-Level Inputs
AINR+, AINR-, AINL+, and AINL- are the line-level differential analog inputs. The analog signal must be
externally biased to VQ, approximately 2.7 V, before being applied to these inputs. The level of the signal
can be adjusted for the left and right ADC independently through the ADC Left and Right Channel Gain
Control Registers on page 61. The ADC output data is in two’s complement binary format. For inputs
above positive full scale or below negative full scale, the ADC will output 7FFFFFH or 800000H, respectively and cause the ADC Overflow bit in the register “Interrupt Status (address 20h) (Read Only)” on
page 63 to be set to a ‘1’. The RXP/GPO pins may also be configured to indicate an overflow condition
has occurred in the ADC. See “RXP/General-Purpose Pin Control (addresses 29h to 2Fh)” on page 69
for proper configuration. Figure 6 shows the full-scale analog input levels. See “ADC Input Filter” on
page 73 for a recommended input buffer.
20 DS585F2
4.2.2 High-Pass Filter and DC Offset Calibration
AOUT+
AOUT-
Full-Scale Output Level= (AIN+) - (AIN-)= 5 Vpp
3.95 V
2.7 V
1.45 V
3.95 V
2.7 V
1.45 V
Figure 7. Full-Scale Output
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. The high-pass filter can be independently enabled and disabled. If the HPF_Freeze bit is set during
normal operation, the current value of the DC offset for the corresponding channel is frozen and this DC
offset will continue to be subtracted from the conversion result. This feature makes it possible to perform
a system DC offset calibration by:
1. Running the CS42526 with the high-pass filter enabled until the filter settles. See the Digital Filter
Characteristics for filter settling time.
2. Disabling the high-pass filter and freezing the stored DC offset.
The high-pass filters are controlled using the HPF_FREEZE bit in the register “Misc Control (address
05h)” on page 50.
4.3 Analog Outputs
4.3.1 Line-Level Outputs and Filtering
The CS42526 contains on-chip buffer amplifiers capable of producing line-level differential outputs. These
amplifiers are biased to a quiescent DC level of approximately VQ.
The delta-sigma conversion process produces high-frequency noise beyond the audio passband, most of
which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using
an off-chip low-pass filter. See “DAC Output Filter” on page 73 for a recommended output buffer. This filter
configuration accounts for the normally differing AC loads on the AOUT+ and AOUT- differential output
pins. It also shows an AC coupling configuration which minimizes the number of required AC coupling capacitors. Figure 7 shows the full-scale analog output levels.
CS42526
4.3.2 Interpolation Filter
To accommodate the increasingly complex requirements of digital audio systems, the CS42526 incorporates selectable interpolation filters for each mode of operation. A “fast” and a “slow” roll-off filter is avail-
DS585F2 21
able in Single-, Double-, and Quad-Speed Modes. These filters have been designed to accommodate a
variety of musical tastes and styles. The FILT_SEL bit found in the register “Misc Control (address 05h)”
on page 50 selects which filter is used. Filter response plots can be found in Figures 46 to 69.
4.3.3 Digital Volume and Mute Control
A Channel
Volume
Control
AOUTAx
AOUTBx
Left Channel
Audio Data
Right Channel
Audio Data
BChannel
Volume
Control
MUTE
MUTE
CX_SDINx
Figure 8. ATAPI Block Diagram (x = channel pair 1, 2, or 3)
Each DAC’s output level is controlled via the Volume Control registers operating over the range of 0 to
-127 dB attenuation with 0.5 dB resolution. See “Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h,
14h)” on page 58. Volume control changes are programmable to ramp in increments of 0.125 dB at the
rate controlled by the SZC[1:0] bits in the Digital Volume Control register. See “Volume Transition Control
(address 0Dh)” on page 56.
Each output can be independently muted via mute control bits in the register “Channel Mute (address
0Eh)” on page 58. When enabled, each XX_MUTE bit attenuates the corresponding DAC to its maximum
value (-127 dB). When the XX_MUTE bit is disabled, the corresponding DAC returns to the attenuation
level set in the Volume Control register. The attenuation is ramped up and down at the rate specified by
the SZC[1:0] bits.
The Mute Control pin, MUTEC, is typically connected to an external mute control circuit. The Mute Control
pin outputs high impedance during Power-Up or in Power-Down Mode by setting the PDN bit in the register “Power Control (address 02h)” on page 46 to a ‘1’. Once out of Power-Down Mode, the pin can be
controlled by the user via the control port, or automatically asserted high when zero data is present on all
DAC inputs, or when serial port clock errors are present. To prevent large transients on the output, it is
desirable to mute the DAC outputs before the Mute Control pin is asserted. Please see the MUTEC pin
in the Pin Descriptions section for more information.
Each of the RXP1/GPO1-RXP7/GPO7 can be programmed to provide a hardware MUTE signal to individual circuits. When not used as an S/PDIF input, each pin can be programmed as an output, with specific muting capabilities as defined by the function bits in the register “RXP/General-Purpose Pin Control
(addresses 29h to 2Fh)” on page 69.
CS42526
4.3.4 ATAPI Specification
The CS42526 implements the channel-mixing functions of the ATAPI CD-ROM specification. The
ATAPI functions are applied per A-B pair. Refer to Table 16 on page 60 and Figure 8 for additional information.
22 DS585F2
4.4 S/PDIF Receiver
The CS42526 includes an S/PDIF digital audio receiver. The S/PDIF receiver accepts and decodes digital
audio data according to the IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. The receiver consists of an 8:2 multiplexer input stage driven through pins RXP0 and RXP1/GPO1 - RXP7/GPO7, a PLL
based clock recovery circuit, and a decoder which separates the audio data from the channel status and
user data. A comprehensive buffering scheme provides read access to the channel status and user data.
External components are used to terminate and isolate the incoming data cables from the CS42526. These
components and required circuitry are detailed in the CDB42528.
4.4.1 8:2 S/PDIF Input Multiplexer
The CS42526 contains an 8:2 S/PDIF Input Multiplexer to accommodate up to eight channels of input digital audio data. Digital audio data is single-ended and input through the RXP0 and
RXP1/GPO1-RXP7/GPO7 pins. Any one of these inputs can be multiplexed to the input of the S/PDIF
receiver and to the S/PDIF output pin TXP.
When any portion of the multiplexer is implemented, unused RXP0 and RXPx/GPOx pins should be tied
to a 0.01uF capacitor to ground. The receiver multiplexer select line control is accessed through bits
RMUX2:0 in the Receiver Mode Control 2 register on page 63. The TXP multiplexer select line control is
accessed through bits TMUX2:0 in the same register. The multiplexer defaults to RXP0 for both functions.
CS42526
4.4.2 Error Reporting and Hold Function
While decoding the incoming S/PDIF data stream, the CS42526 can identify several kinds of error, indicated in the register “Receiver Errors (address 26h) (Read Only)” on page 67. See “Error Reporting and
Hold Function” on page 74 for more information.
4.4.3 Channel Status Data Handling
The first 2 bytes of the Channel Status block (C data) are decoded into the Receiver Channel Status register (See “Receiver Channel Status (address 25h) (Read Only)” on page 66). See “Channel Status Data
Handling” on page 74 for more information.
4.4.4 User Data Handling
The incoming User (U) data is buffered in a user accessible buffer. If the U data bits have been encoded
as Q-channel subcode, the data is decoded and presented in 10 consecutive register locations, address
30h to 39h. The user can configure the Interrupt Mask Register to cause interrupts to indicate the decoding of a new Q-channel block, which may be read through the control port. See “User (U) Data E Buffer
Access” on page 76 for more information.
4.4.5 Non-Audio Auto-Detection
A S/PDIF data stream may be used to convey non-audio data, thus it is important to know whether the
incoming data stream is digital PCM audio samples or not. This information is typically conveyed in channel status bit 1 (AUDIO
however, such as AC-3
properly set. See “Non-Audio Auto-Detection” on page 76 for more information including details for inter-
face format detection.
), which is extracted automatically by the CS42526. Certain non-audio sources,
or MPEG encoders, may not adhere to this convention, and the bit may not be
DS585F2 23
4.5 Clock Generation
SAI_LRCK
(slave mode)
Recovered
S/PDIF Clock
0
1
PLL (256Fs)
8.192 -
49.152 MHz
00
01
PLL_LRCK bit
SW_CTRLx bits
(manual or auto
switch)
OMCK
Auto Detect
Input Clock
1,1.5, 2, 4
single
speed
256
double
speed
128
quad
speed
64
single
speed
4
double
speed
2
quad
speed
1
00
01
10
00
01
10
00
01
10
00
01
10
not OLM
OLM #1
CODEC_FMx bits
SAI_FMx bits
DAC_OLx
or ADC_OLx bits
ADC_OLx and
ADC_SP SELx bits
SAI_SCLK
CX_SCLK
CX_LRCK
SAI_LRCK
RMCK
OLM #2
not OLM
OLM #1
OLM #2
128FS
256FS
128FS
256FS
Internal
MCLK
00
01
10
11
RMCK_DIVx bits
2
4
X2
Figure 9. CS42526 Clock Generation
The clock generation for the CS42526 is shown in the figure below. The internal MCLK is derived from the
output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by the SW_CTRLx bits and can be configured to manual switch mode only, or automatically switch on loss of PLL lock
to the other source input.
CS42526
4.5.1 PLL and Jitter Attenuation
An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming S/PDIF data stream.
There are some applications where low jitter in the recovered clock, presented on the RMCK pin, is important. For this reason, the PLL has been designed to have good jitter attenuation characteristics as
shown in Figure 28 on page 79.
The PLL can be configured to lock onto the incoming SAI_LRCK signal from the Serial Audio Interface
Port and generate the required internal master clock frequency. By setting the PLL_LRCK bit to a ‘1’ in
the register “Clock Control (address 06h)” on page 52, the PLL will lock to the incoming SAI_LRCK and
generate an output master clock (RMCK) of 256Fs. Table 2 shows the output of the PLL with typical input
Fs values for SAI_LRCK.
See “Appendix C: PLL Filter” on page 77 for more information concerning PLL operation, required filter
components, optimal layout guidelines, and jitter-attenuation characteristics.
24 DS585F2
4.5.2 OMCK System Clock Mode
Sample
Rate
(kHz)
OMCK (MHz)
Single-Speed
(4 to 50 kHz)
Double-Speed
(50 to 100 kHz)
Quad-Speed
(100 to 192 kHz)
256x 384x 512x 128x 192x 256x 64x 96x 128x
48 12.2880 18.4320 24.5760 - - - - - 96 - - - 12.2880 18.4320 24.5760 - - -
192 - - - - - - 12.2880 18.4320 24.5760
Table 1. Common OMCK Clock Frequencies
Sample
Rate
(kHz)
PLL Output (MHz)
Single Speed
(4 to 50 kHz)
Double Speed
(50 to 100 kHz)
Quad Speed
(100 to 192 kHz)
256x 256x 256x
32 8.1920 - -
44.1 11.2896 - 48 12.2880 - 64 - 16.3840 -
88.2 - 22.5792 96 - 24.5760 -
176.4 - - 45.1584
192 - - 49.1520
Table 2. Common PLL Output Clock Frequencies
A special clock-switching mode is available that allows the clock that is input through the OMCK pin to be
used as the internal master clock. This feature is controlled by the SW_CTRLx bits in register “Clock Con-
trol (address 06h)” on page 52. An advanced auto-switching mode is also implemented to maintain mas-
ter clock functionality. The clock auto-switching mode allows the clock input through OMCK to be used as
a clock in the system without any disruption when the PLL loses lock, for example, when the input is removed from the receiver. This clock-switching is done glitch-free. A clock adhering to the specifications
detailed in the Switching Characteristics table on page 11 must be applied to the OMCK pin at all times
that the FRC_PLL_LK bit is set to ‘0’ (See “Force PLL Lock (FRC_PLL_LK)” on page 53).
4.5.3 Master Mode
In Master Mode, the serial interface timings are derived from an external clock attached to OMCK or from
the output of the PLL with an input reference to either the S/PDIF Receiver recovered clock or the SAI_LRCK input from the Serial Audio Interface Port. Master clock selection and operation is configured with
the SW_CTRL1:0 bits in the Clock Control Register (See “Clock Control (address 06h)” on page 52).The
supported PLL output frequencies are shown in Table 2 below.
CS42526
4.5.4 Slave Mode
In Slave Mode, CX_LRCK, CX_SCLK and/or SAI_LRCK, SAI_SCLK operate as inputs. The Left/Right
clock signal must be equal to the sample rate, Fs, and must be synchronously derived from the supplied
DS585F2 25
master clock, OMCK, or the output of the PLL. The serial bit clock, CX_SCLK and/or SAI_SCLK, must be
synchronously derived from the master clock and be equal to 128x, 64x, 48x or 32x Fs, depending on the
interface format selected and desired speed mode.
When the device is clocked from OMCK, the frequency of OMCK must be at least twice the frequency of
the fastest Slave Mode, SCLK. For example, if both serial ports are in Slave Mode with one SCLK running
at 32x Fs and the other at 64x Fs, the slowest OMCK signal that can be used to clock the device is
128x Fs.
When either serial port is in Slave Mode, its respective LRCK signal must be present for proper device
operation.
In Slave Mode, One-Line Mode #1 is supported; One-Line Mode #2 is not.
The sample rate to OMCK ratios and OMCK frequency requirements for Slave Mode operation are shown
in Table 1. Refer to Table 3 for required clock ratios.
Single-Speed Double-Speed Quad-Speed One-Line Mode #1
OMCK/LRCK Ratio
SCLK/LRCK Ratio
256x, 384x, 512x 128x, 192x, 256x 64x, 96x, 128x 256x
32x, 48x, 64x, 128x 32x, 48x, 64x 32x, 48x, 64x 128x
Table 3. Slave Mode Clock Ratios
4.6 Digital Interfaces
4.6.1 Serial Audio Interface Signals
The CS42526 interfaces to an external Digital Audio Processor via two independent serial ports, the
CODEC serial port, CODEC_SP and the Serial Audio Interface serial port, SAI_SP. The digital output of
the internal ADCs can be configured to use either the CX_SDOUT pin or the SAI_SDOUT pin and the
corresponding serial port clocking signals. These configuration bits and the selection of Single-, Doubleor Quad-Speed Mode for CODEC_SP and SAI_SP are found in register “Functional Mode (address 03h)”
on page 47.
CS42526
The serial interface clocks, SAI_SCLK for SAI_SP and CX_SCLK for CODEC_SP, are used for transmitting and receiving audio data. Either SAI_SCLK or CX_SCLK can be generated by the CS42526 (Master
Mode), or it can be input from an external source (Slave Mode). Master or Slave Mode selection is made
using bits CODEC_SP M/S
The Left/Right clock (SAI_LRCK or CX_LRCK) is used to indicate left and right data frames and the start
of a new sample period. It may be an output of the CS42526 (Master Mode), or it may be generated by
an external source (Slave Mode). As described in later sections, particular modes of operation do allow
the sample rate, Fs, of the SAI_SP and the CODEC_SP to be different, but must be multiples of each
other.
The serial data interface format selection (Left/Right-Justified, I²S or One-Line Mode) for the Serial Audio
Interface serial port data out pin, SAI_SDOUT, the CODEC serial port data out pin, CX_SDOUT, and the
CODEC input pins, CX_SDIN1:3, is configured using the appropriate bits in the register “Interface For-
mats (address 04h)” on page 49. The serial audio data is presented in two's complement binary form with
the MSB first in all formats.
CX_SDIN1, CX_SDIN2, and CX_SDIN3 are the serial data input pins supplying the associated internal
DAC. CX_SDOUT, the ADC data output pin, carries data from the two internal 24-bit ADCs and, when
configured for one-line mode, up to four additional ADC channels attached externally to the signals ADCIN1 and ADCIN2 (typically two CS5361 stereo ADCs). When operated in One-Line Mode, 6 channels of
DAC data are input on CX_SDIN1 and 6 channels of ADC data are output on CX_SDOUT. Table 4 on
page 27 outlines the serial port channel allocations.
and SAI_SP M/S in register “Misc Control (address 05h)” on page 50.
26 DS585F2
Serial Inputs / Outputs
CX_SDIN1 left channel
right channel
One-Line Mode
CX_SDIN2 left channel
right channel
One-Line Mode
CX_SDIN3 left channel
right channel
One-Line Mode
CX_SDOUT left channel
right channel
One-Line Mode
SAI_SDOUT left channel
right channel
One-Line Mode
ADCIN1 left channel
right channel
ADCIN2 left channel
right channel
CS42526
DAC #1
DAC #2
DAC channels 1,2,3,4,5,6
DAC #3
DAC #4
not used
DAC #5
DAC #6
not used
ADC #1
ADC #2
ADC channels 1,2,3,4,5,6
S/PDIF Left or ADC #1
S/PDIF Right or ADC #2
ADC channels 1,2,3,4,5,6
External ADC #3
External ADC #4
External ADC #5
External ADC #6
Table 4. Serial Audio Port Channel Allocations
DS585F2 27
4.6.2 Serial Audio Interface Formats
Left Channel
Right Channel
CX_SDINx
CX_SDOUT
SAI_SDOUT
+3 +2 +1+5 +4
-1 -2 -3 -4 -5
+3 +2 +1+5 +4
-1 -2 -3 -4
MSB
MSB
LSB LSB
CX_LRCK
SAI_LRCK
CX_SCLK
SAI_SCLK
Figure 10. I²S Serial Audio Formats
I²S Mode, Data Valid on Rising Edge of SCLK
Bits/Sample
SCLK Rate(s)
Notes
Master Slave
16
64 48, 64, 128 Fs Single-Speed Mode
64 Fs 64 Fs Double-Speed Mode
64 Fs 64 Fs Quad-Speed Mode
18 to 24
64, 128, 256 Fs 48, 64, 128 Fs Single-Speed Mode
64 Fs 48, 64 Fs Double-Speed Mode
64 Fs 48, 64 Fs Quad-Speed Mode
The CODEC_SP and SAI_SP digital audio serial ports support five formats with varying bit depths from
16 to 24 as shown in Figures 10 to 14. These formats are selected using the configuration bits in the registers, “Functional Mode (address 03h)” on page 47 and “Interface Formats (address 04h)” on page 49.
For the diagrams below, Single-Speed Mode is equivalent to Fs = 32, 44.1, 48 kHz; Double-Speed Mode
is for Fs = 64, 88.2, 96 kHz; and Quad-Speed Mode is for Fs = 176.4, 196 kHz.
CS42526
28 DS585F2
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