–0.5 dB Step Size
–Zero Crossing, Click-Free Transitions
Popguard
–Minimizes the Effects of Output Transients
Filtered Line-Level Outputs
Selectable Serial Audio Interface Formats
–Left-Justified up to 24-bit
–I²S up to 24-bit
–Right-Justified 16-, 18-, 20-, and 24-bit
Selectable 50/15 µs De-Emphasis
Control Output for External Muting
®
Technology
A/D Features
Multi-bit Delta Sigma Modulator
104 dB Dynamic Range
-95 dB THD+N
Stereo 6:1 Input Multiplexer
Programmable Gain Amplifier (PGA)
–± 12 dB Gain, 0.5 dB Step Size
–Zero Crossing, Click-Free Transitions
Stereo Microphone Inputs
–+32 dB Gain Stage
–Low-Noise Bias Supply
Up to 192 kHz Sampling Rates
Selectable Serial Audio Interface Formats
–Left-Justified up to 24-bit
–I²S up to 24-bit
High-Pass Filter or DC Offset Calibration
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2012
(All Rights Reserved)
AUG '12
DS656F3
CS4245
System Features
Direct Interface with 1.8 V to 5 V Logic Levels
Optional Asynchronous Serial Port Operation
–Each Serial Port Supports Master or Slave
Operation
Selectable Auxiliary Analog Output
–Allows Analog Monitoring of Either the ADC
Input Signal after PGA or DAC Output
Signal
Internal Digital Loopback
Power-Down Mode
–Available for A/D, D/A, CODEC, Mic
Preamplifier
+3.3 V to +5 V Analog Power Supply
+3.3 V to +5 V Digital Power Supply
Supports I²C
Interfaces
Pin-Compatible with CS5345
®
and SPITM Control Port
General Description
The CS4245 is a h ighly integrated stereo audio
CODEC. The CS4245 performs stereo analog-to-digital
(A/D) and digital-to-analog (D/A) conversion of up to
24-bit serial values at sample rates up to 192 kHz.
A 6:1 stereo input multiplexer is included for s electing
between line-level or microphone-level inputs. The microphone input path includes a +32 dB gain stage and
a low-noise bias voltage supply. The PGA is available
for line or microphone inputs and provides gain/attenuation of 12 dB in 0.5 dB steps.
The output of the PGA is followed by an advanced 5thorder, multi-bit delta sigma modulator and digital filtering/decimation. Sampled data is transmitted by the
serial audio interface at rates from 4 kHz to 192 kHz in
either Slave or Master Mode.
The D/A converter is based on a 4th-order multi-bit delta
sigma modulator with an ultra-linear low-pass filter and
offers a volume control that operates with a 0.5 dB step
size. It in corporates selectable soft ramp and zero
crossing transition functions to eliminate clicks and
pops.
Standard 50/15 s de-emphasis is availa ble for a
44.1 kHz sample rate for compatibility with digital audio
programs mastered using the 50 /15 s pre-emphasis
technique.
Integrated level translators allow easy interfacing between the CS4245 and other devices operating over a
wide range of logic levels.
The CS4245 is available in a 48-pin LQFP package in
both Commercial (-10° to +70° C) and Automotive (-40°
to +105° C) grade. The CDB4245 Customer Demonstration board is also available for device evaluation and
implementation suggestions. Please see “Ordering In-
Table 15. Example Gain and Attenuation Settings ................................................................................... 47
Table 16. PGA Soft Cross or Zero Cross Mode Selection ........................................................................ 48
Table 17. Analog Input Multiplexer Selection ............................................................................................ 48
Table 18. Digital Volume Control Example Settings ................................................................................. 49
Table 19. DAC Soft Cross or Zero Cross Mode Selection ........................................................................ 49
6DS656F3
1. PIN DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
VLSSDA/CDOUT
AGND
OVFL
SCL/CCLK
AD0/CS
AD1/CDIN
VLC
RESET
AIN3A
AIN3B
AIN2A
AIN2B
AIN1A
AIN1B
VA
AFILTB
VQ1
VQ2
FILT1+
FILT2+
AIN4A/MICIN1
AIN4B/MICIN2
AIN5A
AIN5B
AFILTA
MUTEC
AOUTB
AOUTA
AGND
AGND
VA
AUXOUTB
AUXOUTA
AIN6B
AIN6A
MICBIAS
INTVDDGND
MCLK1
LRCK1
SCLK1
SDOUT
MCLK2
LRCK2
SCLK2
SDIN
CS4245
CS4245
Pin Name#Pin Description
SDA/CDOUT1
SCL/CCLK2Serial Control Port Clock (Input) - Serial clock for the serial control port.
AD0/CS
AD1/CDIN4
VLC5
RESET
AIN3A
AIN3B
AIN2A
AIN2B
AIN1A
AIN1B
DS656F37
Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode. CDOUT is the output data line for
the control port interface in SPI Mode.
Address Bit 0 (I²C) / Control Port Chip Select (SPI)(Input) - AD0 is a chip address pin in I²C Mode;
3
CS
Address Bit 1 (I²C) / Serial Control Data Input (SPI)(Input) - AD1 is a chip address pin in I²C Mode;
CDIN is the input data line for the control port interface in SPI Mode.
Control Port Power (Input) - Determines the required signal level for the control port interface. Refer
to the Recommended Operating Conditions for appropriate voltages.
6Reset (Input) - The device enters a low power mode when this pin is driven low.
Stereo Analog Input 3 (Input) - The full-scale level is specified in the ADC Analog Characteristics
7, 8
specification table.
Stereo Analog Input 2 (Input) - The full-scale level is specified in the ADC Analog Characteristics
9, 10
specification table.
Stereo Analog Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics
11, 1 2
specification table.
is the chip-select signal for SPI format.
CS4245
AGND13Analog Ground (Input) - Ground reference for the internal analog section.
VA14Analog Power (Input) - Positive power for the internal analog section.
AFILTA15Antialias Filter Connection (Output) - Antialias filter connection for the channel A ADC input.
AFILTB16Antialias Filter Connection (Output) - Antialias filter connection for the channel B ADC input.
VQ117Quiescent Voltage 1 (Output) - Filter connection for the internal quiescent reference voltage.
VQ218Quiescent Voltage 2 (Output) - Filter connection for the internal quiescent reference voltage.
FILT1+19Positive Voltage Reference 1 (Output) - Positive reference voltage for the internal sampling circuits.
FILT2+20Positive Voltage Reference 2 (Output) - Positive reference voltage for the internal sampling circuits.
AIN4A/MICIN1
AIN4B/MICIN2
AIN5A
AIN5B
MICBIAS25
AIN6A
AIN6B
AUXOUTA
AUXOUTB
VA30Analog Power (Input) - Positive power for the internal analog section.
AGND31, 32 Analog Ground (Input) - Ground reference for the internal analog section.
AOUTA
AOUTB
MUTEC
VLS36
SDIN37Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
SCLK238Serial Port 2 Serial Bit Clock (Input/Output) - Serial bit clock for serial audio interface 2.
LRCK239
MCLK240Master Clock 2 (Input) - Optional asynchronous clock source for the DAC’s delta-sigma modulators.
SDOUT41Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
SCLK142Serial Port 1 Serial Bit Clock (Input/Output) - Serial bit clock for serial audio interface 1.
LRCK143
MCLK144
DGND45Digital Ground (Input) - Ground reference for the internal digital section.
VD46Digital Power (Input) - Positive power for the internal digital section.
INT47Interrupt (Output) - Indicates an interrupt condition has occurred.
OVFL48ADC Overflow (Output) - Indicates an ADC overflow condition is present.
Stereo Analog Input 4 / Micropho ne Inp ut 1 & 2 (Input) - The full-scale level is specified in the ADC
21, 22
Analog Characteristics specification table.
Stereo Analog Input 5 (Input) - The full-scale level is specified in the ADC Analog Characteristics
teristics are specified in the DC Electrical Characteristics specification table.
Stereo Analog Input 6 (Input) - Th
26, 27
specification table.
Auxiliary Analog Au dio Ou tput (Output) - Analog output from either the DAC, the PGA block, or high
28, 29
impedance. See “Auxiliary Output Source Select (Bits 6:5)” on page 46.
DAC Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Char-
33, 34
acteristics specification table.
Mute Control (Output) - This pin is active during power-up initialization, reset, muting, when master
35
clock to left/right clock frequency ratio is incorrect, or power-down.
Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio inter-
face. Refer to the Recommended Operating Conditions for appropriate voltages.
Serial Port 2 Left Right Clock(Input/Output) - Determines which channel, Left or Right, is currently
active on the serial audio input data line.
Serial Port 1 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently
active on the serial audio output data line.
Master Clock 1 (Input) - Clock source for the ADC’s delta-sigma modulators. By default, this signal
also clocks the DAC’s delta-sigma modulators.
e full-scale level is specified in the ADC Analog Characteristics
8DS656F3
2. CHARACTERISTICS AND SPECIFICATIONS
SPECIFIED OPERATING CONDITIONS
AGND = DGND = 0 V; All voltages with respect to ground.
ParametersSymbol Min NomMaxUnits
DC Power Supplies:Analog
Digital
Logic - Serial Port
Logic - Control Port
Ambient Operating Temperature (Power Applied)T
VA
VD
VLS
VLC
Notes: 1. Maximum of VA+0.25 V or 5.25 V, whichever is less.
ABSOLUTE MAXIMUM RATINGS
AGND = DGND = 0 V All voltages with respect to ground. (Note 2)
ParameterSymbolMinMaxUnits
DC Power Supplies:Analog
Digital
Logic - Serial Port
Logic - Control Port
Input Current(Note 3)
Analog Input Voltage
Digital Input VoltageLogic - Serial Port
Logic - Control Port
Ambient Operating Temperature (Power Applied)
Storage Temperature
VLS
VLC
V
V
V
A
VA
VD
I
in
INA
IND-S
IND-C
T
A
T
stg
CS4245
3.13
3.13
1.71
1.71
-10-+70C
AGND-0.3VA+0.3V
5.0
3.3
3.3
3.3
-0.3
-0.3
-0.3
-0.3
-10mA
-0.3
-0.3
-50+125C
-65+150C
5.25
(Note 1)
5.25
5.25
+6.0
+6.0
+6.0
+6.0
VLS+0.3
VLC+0.3
V
V
V
V
V
V
V
V
V
V
2. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
3. Any pin except s upplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
DS656F39
CS4245
DAC ANALOG CHARACTERISTICS
Test Conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V
or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; T
+85° C for Automotive; Output test signal: 997 Hz full-scale sine wave; Test load R
Figure 1), Fs = 48/96/192 kHz. Measurement Bandwidth 10 Hz to 20 kHz Synchronous mode; All Connections as
shown in Figure 12 on page 29.
Commercial GradeAutomotive Grade
Parameter
SymbolMinTypMaxMinTypMaxUnit
Dynamic Performance for VA = 4.75 V to 5.25 V
Dynamic Range(Note 4)
18 to 24-BitA-Weighted
unweighted
16-BitA-Weighted
unweighted
Total Harmonic Distortion + Noise(Note 4)
18 to 24-Bit0 dB
-20 dB
-60 dB
16-Bit0 dB
-20 dB
-60 dB
THD+N
98
95
90
87
-
-
-
-
-
-
Dynamic Performance for VA = 3.13 V to 3.46 V
Dynamic Range(Note 4)
18 to 24-BitA-Weighted
unweighted
16-BitA-Weighted
unweighted
Total Harmonic Distortion + Noise(Note 4)
18 to 24-Bit0 dB
-20 dB
-60 dB
16-Bit0 dB
-20 dB
-60 dB
Interchannel Isolation(1 kHz)-100--100-dB
THD+N
95
92
88
85
-
-
-
-
-
-
DC Accuracy
Interchannel Gain Mismatch-0.10.25-0.10.25dB
Gain Drift-100--100-ppm/°C
Analog Output
Full Scale Output Voltage0.60*VA 0.65*VA 0.70*VA 0.60*VA 0.65*VA 0.70*VAV
DC Current draw from an AOUT pin(Note 5)I
AC-Load Resistance(Note 6)R
Load Capacitance(Note 6)C
Output ImpedanceZ
OUT
L
L
OUT
--10--10A
3--3- -k
--100--100pF
-150- -150-
= -10° to +70° C for Commercial or -40° to
104
101
96
93
-90
-81
-41
-93
-73
-33
101
98
93
90
-87
-78
-38
-90
-70
-30
A
-
-
-
-
-84
-
-
-87
-
-
-
-
-
-
-79
-
-
-82
-
-
= 3 k, CL = 10 pF (see
L
96
93
88
85
-
-
-
-
-
-
93
90
86
83
-
-
-
-
-
-
104
101
96
93
-90
-81
-41
-93
-73
-33
101
98
93
90
-87
-78
-38
-90
-70
-30
-
-
-
-
-82
-
-
-85
-
-
-
-
-
-
-77
-
-
-80
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
pp
4. One-half LSB of triangular PDF dither added to data.
5. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin
due to typical leakage through the electrolytic DC blocking capacitors.
10DS656F3
CS4245
6. Guaranteed by design. See Figure 2. RL and CL reflect the recommended minimum resistance and
maximum capacitance required for the internal op-amp’s stability. C
internal output amp; increasing C
beyond 100 pF can cause the internal op-amp to become unstable.
L
affects the dominant pole of the
L
DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Parameter (Note 7,10)SymbolMinTypMaxUnit
Combined Digital and On-chip Analog Filter Response Single-Speed Mode
Combined Digital and On-chip Analog Filter Response Double-Speed Mode
Passband (Note 7)to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz-0.15-+0.15dB
StopBand0.5770--Fs
StopBand Attenuation(Note 8)55--dB
Group Delaytgd-5/Fs-s
0
0
-
-
0.22
0.501
Fs
Fs
Combined Digital and On-chip Analog Filter Response Quad-Speed Mode
Passband (Note 7)to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz-0.12-0dB
StopBand0.7--Fs
StopBand Attenuation(Note 8)51--dB
Group Delaytgd-2.5/Fs-s
0
0
-
-
0.110
0.469
Fs
Fs
7. Filter response is guaranteed by design.
8. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs.
9. De-emphasis is available only in Single-Speed Mode.
10. Response is clock dependent and will scale with Fs. Note that the amplitude vs. frequency plots of this
data (Figures 21 to 30) have been normalized to Fs and can be de-normalized by multiplying the X-axis
scale by Fs.
DS656F311
AOUTx
AGND
3.3µF
V
out
R
L
C
L
Figure 1. DAC Output Test LoadFigure 2. Maximum DAC Loading
100
50
75
25
2.5
51015
Safe Operating
Region
Capacitive Load -- C (pF)
L
Resistive Load -- R (k)
L
125
3
20
CS4245
12DS656F3
CS4245
ADC ANALOG CHARACTERISTICS
Test conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V
or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; T
+85° C for Automotive; Input test signal: 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz;
Fs = 48/96/192 kHz. Synchronous mode; All connections as shown in Figure 12 on page 29.
Line-Level Inputs
ParameterSymbolMinTyp Max Unit
Dynamic Performance for VA = 4.75 V to 5.25 V
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
(Note 13)40 kHz bandwidth unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
(Note 13) 40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise(Note 12)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
(Note 13) 40 kHz bandwidth -1 dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
(Note 13) 40 kHz bandwidth -1 dB
THD+N
Dynamic Performance for VA = 3.13 V to 3.46 V
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
(Note 13) 40 kHz bandwidth unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
(Note 13)40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise (Note 12)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
(Note 13) 40 kHz bandwidth -1 dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
(Note 13) 40 kHz bandwidth -1 dB
THD+N
Line-Level Inputs
ParameterSymbol
Interchannel Isolation-90-dB
= -10° to +70° C for Commercial or -40° to
A
98
95
-
92
89
-
-
-
-
-
-
-
-
-
93
90
-
89
86
-
-
-
-
-
-
-
-
-
104
101
98
98
95
92
-95
-81
-41
-92
-92
-75
-35
-89
101
98
95
95
92
89
-92
-78
-38
-84
-89
-72
-32
-81
-89
-86
-86
-83
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Commercial Grade
UnitMinTyp Max
DS656F313
CS4245
DC Accuracy
Gain Error--10%
Gain Drift-100-ppm/°C
Line-Level Input Characteristics
Full-scale Input Voltage0.51*VA0.57*VA0.63*VAV
Input Impedance(Note 11)6.126.87.48k
Maximum Interchannel Input Impedance
Mismatch
-5-%
Line-Level and Microphone-Level Inputs
Commercial Grade
ParameterSymbol
DC Accuracy
Interchannel Gain Mismatch-0.1-dB
Programmable Gain Characteristics
Gain Step Size-0.5-dB
Absolute Gain Step Error--0.4dB
12. Referred to the typical line-level full-scale input voltage
13. Valid for Double- and Quad-Speed Modes only.
14. Valid when the microphone-level inputs are selected.
DS656F315
CS4245
ADC DIGITAL FILTER CHARACTERISTICS
Parameter (Notes 15, 17)SymbolMinTypMaxUnit
Single-Speed Mode
Passband(-0.1 dB)0-0.4896Fs
Passband Ripple--0.035dB
Stopband0.5688--Fs
Stopband Attenuation70--dB
Total Group Delay (Fs = Output Sample Rate)t
gd
Double-Speed Mode
Passband(-0.1 dB)0-0.4896Fs
Passband Ripple--0.025dB
Stopband0.5604--Fs
Stopband Attenuation69--dB
Total Group Delay (Fs = Output Sample Rate)t
gd
Quad-Speed Mode
Passband(-0.1 dB)0-0.2604Fs
Passband Ripple--0.025dB
Stopband0.5000--Fs
Stopband Attenuation60--dB
Total Group Delay (Fs = Output Sample Rate)t
gd
High-Pass Filter Characteristics
Frequency Response-3.0 dB
-0.13 dB(Note 16)
Phase Deviation@ 20 Hz(Note 16)-10 -Deg
Passband Ripple-- 0dB
Filter Settling Time
-12/Fs -s
-9/Fs - s
-5/Fs - s
-120-
5
10
/Fss
-
Hz
Hz
15. Filter response is guaranteed by design.
16. Response shown is for Fs = 48 kHz.
17. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 33 to 44) are
normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
16DS656F3
CS4245
AUXILIARY OUTPUT ANALOG CHARACTERISTICS
Test conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V
or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; T
+85° C for Automotive; Input test signal: 1 kHz sine wave; Measurement bandwidth: 10 Hz to 20 kHz;
Fs = 48/96/192 kHz; Synchronous mode; All connections as shown in Figure 12 on page 29.
VA = 4.75 V to 5.25 V
Commercial GradeAutomotive Grade
ParameterSymbol
Dynamic Performance with PGA Output Selected, Line Level Input
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
Total Harmonic Distortion + Noise(Note 19)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
THD+N
98
95
92
89
-
-
-
-
-
-
Dynamic Performance with PGA Output Selected, Mic Level Input
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise(Note 19)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB
-1 dB
THD+N
77
74
65
62
-
-
-
-
Dynamic Performance with DAC Output Selected
Dynamic Range(Notes 18)
18 to 24-BitA-weighted
unweighted
16-BitA-Weighted
unweighted
Total Harmonic Distortion + Noise (Notes 18, 20)
18 to 24-Bit0 dB
-20 dB
-60 dB
16-Bit0 dB
-20 dB
-60 dB
THD+N
98
95
90
87
-
-
-
-
-
-
= -10° to +70° C for Commercial or -40° to
A
104
101
98
95
-80
-81
-41
-80
-75
-35
83
80
71
68
-74
-60
-20
-68
104
101
96
93
-80
-81
-41
-80
-73
-33
-74
-74
-68
-74
-74
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
96
93
90
87
75
72
63
60
96
93
88
85
104
101
98
95
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-80
-81
-41
-80
-75
-35
83
80
71
68
-74
-60
-20
-68
104
101
96
93
-80
-81
-41
-80
-73
-33
-
-
-
-
-72
-
-
-72
-
-
-
-
-
-
-66
-
-
-
-
-
-
-
-72
-
-
-72
-
-
UnitMinTyp MaxMinTyp Max
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
DS656F317
AUXILIARY OUTPUT ANALOG CHARACTERISTICS
(Continued)
VA = 3.13 V to 3.46 V
Commercial GradeAutomotive Grade
ParameterSymbol
Dynamic Performance with PGA Output Selected, Line Level Input
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
Total Harmonic Distortion + Noise(Note 19)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
THD+N
Dynamic Performance with PGA Output Selected, Mic Level Input
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 19)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB
-1 dB
THD+N
Dynamic Performance with DAC Output Selected
Dynamic Range(Notes 18)
18 to 24-BitA-Weighted
unweighted
16-BitA-Weighted
unweighted
Total Harmonic Distortion + Noise (Notes 18, 20)
18 to 24-Bit0 dB
-20 dB
-60 dB
16-Bit0 dB
-20 dB
-60 dB
THD+N
93
90
89
86
77
74
65
62
95
92
88
85
101
98
95
92
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-80
-78
-38
-80
-72
-32
83
80
71
68
-74
-60
-20
-68
101
98
93
90
-80
-78
-38
-80
-70
-30
-
-
-
-
-74
-
-
-74
-
-
-
-
-
-
-68
-
-
-
-
-
-
-
-74
-
-
-74
-
-
91
88
87
84
75
72
63
60
93
90
86
83
CS4245
UnitMinTyp MaxMinTyp Max
101
98
95
92
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-80
-78
-38
-80
-72
-32
83
80
71
68
-74
-60
-20
-68
101
98
93
90
-80
-78
-38
-80
-70
-30
-72
-72
-66
-72
-72
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
18. One-half LSB of triangular PDF dither added to data.
19. Referred to the typical Line-Level Full-Scale Input Voltage.
18DS656F3
CS4245
20. Referred to the typical DAC Full-Scale Output Voltage.
AUXILIARY OUTPUT ANALOG CHARACTERISTICS
(Continued)
VA = 3.13 V to 5.25 V
Commercial GradeAutomotive Grade
ParameterSymbol
DC Accuracy with PGA Output Selected, Line Level Input
Interchannel Gain Mismatch-0.1--0.1-dB
Gain Error-5- -5- %
Gain Drift-
100--100-ppm/°C
DC Accuracy with PGA Output Selected, Mic Level Input
Interchannel Gain Mismatch-0.3--0.3-dB
Gain ErrorGain Drift-300--300-ppm/°C
5- -5- %
DC Accuracy with DAC Output Selected
Interchannel Gain Mismatch-0.1--0.1-dB
Gain Drift-
100--100-ppm/°C
Analog Output
Frequency Response 10 Hz to 20 kHz(Note 22)-0.1dB-+0.1dB -0.1dB-+0.1dBdB
Analog In to Analog Out Phase Shift(Note 21)-180--180-deg
DC Current draw from an AUXOUT pinI
AC-Load ResistanceR
Load CapacitanceC
OUT
L
L
--1--1A
100--100--k
--20--20pF
UnitMinTyp MaxMinTyp Max
21. Valid only when PGA output is selected.
22. Guaranteed by design.
DS656F319
CS4245
DC ELECTRICAL CHARACTERISTICS
AGND = DGND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Fs=48 kHz; Master Mode.
ParameterSymbolMinTypMaxUnit
Power Supply CurrentVA = 5 V
(Normal Operation)VA = 3.3 V
VD, VLS, VLC = 5 V
VD, VLS, VLC = 3.3 V
Power Supply CurrentVA = 5 V
(Power-Down Mode) (Note 23)VLS, VLC, VD=5 V
Power Consumption
(Normal Operation)VA, VD, VLS, VLC = 5 V
VA, VD, VLS, VLC = 3.3 V
(Power-Down Mode)VA, VD, VLS, VLC = 5 V
Power Supply Rejection Ratio (1 kHz)(Note 24)PSRR-55-dB
VQ Characteristics
Quiescent Voltage 1VQ1-0.5 x VA-VDC
DC Current from VQ1(Note 25)I
VQ1 Output ImpedanceZ
Quiescent Voltage 2VQ2-0.5 x VA-VDC
DC Current from VQ2(Note 25)I
VQ2 Output ImpedanceZ
FILT1+ Nominal VoltageFILT1+-VA-VDC
FILT2+ Nominal VoltageFILT2+-VA-VDC
Microphone Bias VoltageMICBIAS-0.8 x VA-VDC
Current from MICBIASI
I
I
I
I
I
I
Q1
Q1
Q2
Q2
MB
A
A
D
D
A
D
-
-
-
-
-
-
-
-
-
-
-
-
-- 1A
-23 -k
-- 1A
-4.5 -k
-- 2mA
41
37
39
23
0.50
0.54
400
198
4.2
50
45
47
28
-
-
485
241
-
mA
mA
mA
mA
mA
mA
mW
mW
mW
23. Power-Down Mode is defines as RESET
= Low with all clock and data lines held static and no analog
input.
24. Valid with the recommended capacitor values on FILT1+, FILT2+, VQ1 and VQ2 as shown in the Typical Connection Diagram.
25. Guaranteed by design. The DC current draw represents the allowed current draw due to typical leakage
through the electrolytic de-coupling capacitors.
20DS656F3
CS4245
10
6
LRCK1
--------------------
DIGITAL INTERFACE CHARACTERISTICS
Test conditions (unless otherwise specified): AGND = DGND = 0 V; VLS = VLC = 1.71 V to 5.25 V.
Parameters (Note 26)Symbol Min TypMaxUnits
High-Level Input Voltage
VL = 1.71 VSerial Port
Control Port
VL > 2.0 VSerial Port
Control Port
Low-Level Input VoltageSerial Port
Control Port
High-Level Output Voltage at I
= 2 mASerial Port
o
Control Port
MUTEC
Low-Level Output Voltage at I
= 2 mASerial Port
o
Control Port
MUTEC
Input Leakage CurrentI
V
IH
V
IH
V
IH
V
IH
V
IL
V
IL
V
OH
V
OH
V
OH
V
OL
V
OL
V
OL
in
Input Capacitance(Note 27)--1pF
Maximum MUTEC Drive Current-3-mA
Minimum OVFL Active Time--s
0.8xVLS
0.8xVLC
0.7xVLS
0.7xVLC
-
-
VLS-1.0
VLC-1.0
VA- 1.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.2xVLS
0.2xVLC
-
-
-
0.4
0.4
0.4
--±10A
V
V
V
V
V
V
V
V
V
V
V
V
26. Serial Port signals include: MCLK1, MCLK2, SCLK1, SCLK2, LRCK1, LRCK2, SDIN, SDOUT.
Control Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS
, AD1/CDIN, RESET, INT, OVFL.
27. Guaranteed by design.
DS656F321
CS4245
10
9
128Fs
---------------------
10
9
64Fs
------------------
10
9
64Fs
------------------
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 1
Logic ‘0’ = DGND = AGND = 0 V; Logic ‘1’ = VL, C
ParameterSymbolMinTypMaxUnit
Sample RateSingle Speed Mode
Double Speed Mode
Quad Speed Mode
MCLK Specifications
MCLK1 Input Frequency fmclk1.024-51.200MHz
MCLK1 Input Pulse Width High/Lowt
Master Mode
LRCK1 Duty Cycle-50-%
SCLK1 Duty Cycle-50-%
SCLK1 falling to LRCK1 edget
SCLK1 falling to SDOUT validt
Slave Mode
LRCK1 Duty Cycle405060%
SCLK1 Period
Single-Speed Mode
= 20 pF. (Note 28)
L
Fs
Fs
Fs
clkhl8--ns
slr
sdo
t
sclkw
4
50
100
-
-
-
50
100
200
kHz
kHz
kHz
-10-10ns
0-36ns
-
-
ns
Double-Speed Mode
Quad-Speed Mode
SCLK1 Pulse Width Hight
SCLK1 Pulse Width Lowt
SCLK1 falling to LRCK1 edget
SCLK1 falling to SDOUT validt
28. See Figure 3 and Figure 4 on page 23.
t
sclkw
t
sclkw
sclkh
sclkl
sdo
-
-
-
-
ns
ns
30--ns
48--ns
slr
-10-10ns
0-36ns
22DS656F3
slr
t
SDOUT
SCLK1
Output
LRCK1
Output
sdo
t
slr
t
SDOUT
SCLK1
Input
LRCK1
Input
sdo
t
sclkh
t
sclkl
t
sclkw
t
Figure 3. Master Mode Timing - Serial Audio Port 1
32. Data must be held for sufficient time to bridge the transition time of CCLK.
33. For f
<1 MHz.
sck
28DS656F3
3. TYPICAL CONNECTION DIAGRAM
VLS
0.1 µF
+1.8V
to +5V
MUTEC
Mute
Drive
DGND
VLC
0.1 µF
+1.8V
to +5V
SCL/CCLK
SDA/CDOUT
AD1/CDIN
RESET
2 k
See Note 1
LRCK2
SDIN
AGND
AD0/CS
Note 1: Res istors are required for I²C control
port operation
Digital Audio
Playback
Micro-
Controller
MCLK2
SCLK2
* Capacitors must be C0G or equivalent
Digital Audio
Capture
LRCK1
SDOUT
MCLK1
SCLK1
AUXOUTA
AUXOUTB
2.2nF
AFILTA
AFILTB
OVFL
2.2nF
3.3 µF
3.3 µF
47 µF
0.1 µF
VQ1
FILT1+
10 µF
AGND
**
AOUTA
AOUTB
470
470
3.3 µF
C
Optional
Analog
Muting
2 k
3.3 µF
INT
47 µF
10 k
10 k
C
R
ext
R
ext
See Note 2
For best res ponse to F s/2 :
4704
470
ext
ext
RFs
R
C
This circuitry is intended for applications where
the CS4245 connects directly to an unbalanced
output of the design. For internal routing
applications please see the DAC Analog O utput
Characte ristics section for loa ding limitations .
Note 2 :
AIN1A
Left Analog Input 1
10 µF
10 µF
1800 pF
1800 pF
100 k
100 k
100
100
AIN1B
Right Analog Input 1
AIN2A
Left Analog Input 2
10 µF
10 µF
1800 pF
1800 pF
100 k
100 k
100
100
AIN2B
Right Analog Input 2
AIN3A
Left Analog Input 3
10 µF
10 µF
1800 pF
1800 pF
100 k
100 k
100
100
AIN3B
Right Analog Input 3
AIN4A/MICIN1
Left Analog Input 4
10 µF
10 µF
1800 pF
1800 pF
100 k
100 k
100
100
AIN4B/MICIN2
Right Analog Input 4
AIN5A
Left Analog Input 5
10 µF
10 µF
1800 pF
1800 pF
100 k
100 k
100
100
AIN5B
Right Analog Input 5
AIN6A
Left Analog Input 6
10 µF
10 µF
1800 pF
1800 pF
100 k
100 k
100
100
AIN6B
Right Analog Input 6
MICBIAS
AGND
0.1 µF
47 µF
0.1 µF
VQ2
FILT2+
10 µF
0.1 µF
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0.1 µF
VA
10 µF
+3.3V to +5V
0.1 µF
10 µF
0.1 µF
VAVD
+3.3V to +5V
R
L
Note 3
Note 3: The value of RL is dictated by the
microphone carteridge.
CS4245
Figure 12. Typical Connection Diagram
CS4245
DS656F329
4. APPLICATIONS
4.1Recommended Power-Up Sequence
1. Hold RESET low until the power supply, MCLK1, MCLK2 (if used), LRCK1 and LRCK2 are stable. In
this state, the Control Port is reset to its default settings.
2. Bring RESET
trol port will be accessible.
3. The desired register settings can be loaded while the PDN bit remains set.
4. Clear the PDN bit to initiate the power-up sequence.
4.2System Clocking
The CS4245 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three
speed modes as shown in Table 1.
high. The device will remain in a low power state with the PDN bit set by default. The con-
The CS4245 has two serial ports which may be operated synchronously or asynchronously. Serial port 1
consists of the SCLK1 and LRCK1 signals and clocks the serial audio output, SDOUT. Serial port 2 consists
of the SCLK2 and LRCK2 signals and clocks the serial audio input, SDIN.
Each serial port may be independently placed into Single, Double, or Quad Speed mode. The serial ports
may also be independently placed into Master or Slave mode.
4.2.1Synchronous / Asynchronous Mode
By default, the CS4245 operates in Synchronous Mode with both serial ports synchronous to MCLK1. In
this mode, the serial ports may operate at different synchronous rates as set by the ADC_FM and
DAC_FM bits, and MCLK2 does not need to be provided (the MCLK2 pin may be left unconnected).
If the Asynch bit is set (see “Asynchronous Mode (Bit 0)” on page 46), the CS4245 will operate in asynchronous mode. The serial ports will operate asynchronously with Serial Port 1 clocked from MCLK1 and
Serial Port 2 clocked from MCLK2. In this mode, the serial ports may operate at different asynchronous
rates.
4.2.2Master Clock
In Asynchronous Mode, MCLK1/LRCK1 and MCLK2/LRCK2 must maintain an integer ratio. In synchronous mode MCLK1/LRCK1 and MCLK1/LRCK2 must maintain an integer ratio. Some common ratios are
shown in Table 2.The LRCK frequency is equal to Fs, the frequency at which audio samples for each
channel are clocked into or out of the device. The ADC_FM and DAC_FM bits and the MCLK Freq bits
(See “MCLK Frequency - Address 05h” on page 45.) configure the device to generate the proper clocks
30DS656F3
CS4245
in Master Mode, and receive the proper clocks in Slave Mode. Table 2 illustrates several standard audio
sample rates and the required MCLK and LRCK frequencies.
LRCK
(kHz)
32
44.1
48
64
88.2
96
128
176.4
192
Mode
MCL
K (MHz)
64x96x128x192x256x384x512x768x1024x
----8.192012.288016.384024.576032.7680
----11.289616.934422.579233.868045.1584
----12.288018.432024.576036.864049.1520
--8.192012.288016.384024.576032.7680--
--11.289616.934422.579233.868045.1584--
--12.288018.432024.576036.864049.1520--
8.192012.288016.384024.576032.7680----
11.289616.934422.579233.868045.1584----
12.288018.432024.576036.864049.1520----
QSM
Table 2. Common Clock Frequencies
In both Master and Slave Mo
ratio to achieve a post-divider MCLK/LRCK ratio of 256x for SSM, 128x for DSM, or 64x for QSM. Table 3
lists the appropriate dividers.
des, the external MCLK must be divided down based on the MCLK/LRCK
DSMQSM
DSM
SSM
Table 3. MCLK Dividers
DS656F331
4.2.3Master Mode
÷256
÷128
÷64
÷4
÷2
÷1
00
01
10
00
01
10
LRCK1
SCLK1
000
001
010
÷1
÷1.5
÷2
011
100
÷3
÷4
MCLK1
÷256
÷128
÷64
÷4
÷2
÷1
00
01
10
00
01
10
000
001
010
÷1
÷1.5
÷2
011
100
÷3
÷4
MCLK2
LRCK2
SCLK2
0
1
DAC_FM Bits
ADC_FM Bits
ASynch Bit
MCLK1 Freq Bits
MCLK2 Freq Bits
Figure 13. Master Mode Clocking
As a clock master, LRCK and SCLK will operate as outputs. The two serial ports may be independently
placed into Master or Slave mode. Each LRCK and SCLK is internally derived from its respective MCLK
with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in Figure 13.
CS4245
4.2.4Slave Mode
In Slave Mode, SCLK and LRCK operate as inputs. Each serial port may be independently placed into
Slave Mode. The Left/Right clock signal must be equal to the sample rate, Fs. If operating in Asynchronous Mode, LRCK1 must be synchronously derived from MCLK1 and LRCK2 must be synchronously derived from MCLK2. If operating in Synchronous Mode, LRCK1, and LRCK2 must be synchronously
derived from MCLK1. For more information on Synchronous and Asynchronous Modes, see “Synchro-
nous / Asynchronous Mode” on page 30.
For each serial port, the serial bit clock must be equal to 128x, 64x, 48x or 32x Fs, depending on the desired speed mode. If operating in Asynchronous Mode, the serial bit clock SCLK1 must be synchronously
derived from MCLK1 and SCLK2 must be synchronously derived from MCLK2. If operating in Synchronous Mode, SCLK1, and SCLK2 must be synchronously derived from MCLK1. Refer to Table 4 for re-
4.3High-Pass Filter and DC Offset Calibration
32DS656F3
quired serial bit clock to Left/Right clock ratios.
When using operational amplifiers in the input circuitry driving the CS4245, a small DC offset may be driven
into the A/D converter. The CS4245 includes a high-pass filter after the decimator to remove any DC offset
which could result in recording a DC level, possibly yielding clicks when switching between devices in a multichannel system.
Single-SpeedDouble-SpeedQuad-Speed
Table 4. Slave Mode Serial Bit Clock Ratios
CS4245
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the HPFFreeze bit (See “ADC High-Pass Filter Freeze (Bit 1)” on page 45.) is set during normal operation, the current value of the DC offset for the each channel is frozen and this DC offset will continue to
be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by:
1. Running the CS4245 with the high-pass filter enabled until the filter settles. See the ADC Digital Filter
Characteristics section for filter settling time.
2. Disabling the high-pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the
calibration point and the CS4245.
DS656F333
4.4Analog Input Multiplexer, PGA, and Mic Gain
PGA
MUX
+32 dB
AIN1A
AIN2A
AIN3A
AIN4A/MICIN1
AIN5A
AIN6A
PGA
MUX
+32 dB
AIN1B
AIN2B
AIN3B
AIN4B/MICIN2
AIN5B
AIN6B
Analog Input
Selection Bi ts
Channel A
PGA Gain Bits
Channel B
PGA Gain Bits
Out to ADC
Channel A
Out to ADC
Channel B
Figure 14. Analog Input Architecture
The CS4245 contains a stereo 6-to-1 analog input multiplexer followed by a programmable gain amplifier
(PGA). The input multiplexer can select one of six possible stereo analog input sources and route it to the
PGA. Analog inputs 4A and 4B are able to insert a +32 dB gain stage before the input multiplexer, allowing
them to be used for microphone-level signals without the need for any external gain. The PGA stage provides 12 dB of gain or attenuation in 0.5 dB steps. Figure 14 shows the architecture of the input multiplexer, PGA, and microphone gain stages. .
CS4245
The “Analog Input Selection (Bits 2:0)” on page 48 outlines the bit settings n ecessary to control the input
multiplexer and mic gain. “Channel B PGA Control - Address 07h” on page 47 and “Channel A PGA Control
- Address 08h” on pa ge 47 outline the register settings necessary to control the PGA. By de fault, line-
level input 1 is selected, and the PGA is set to 0 dB.
4.5Input Connections
The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject signals within the stopb and of the f ilter. However, there is no rejection for input signals which a re
6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to the Typical Connection Diagram
(n
for the recommended analog input circuit that will attenuate noise energy at 6.144 MHz. The use of capacitors which ha ve a large voltage coefficient (such as general-purpose ceramics) must be avoid ed since
these can degrade signal linearity. Any unused analog input pairs should be left unconnected.
4.6Output Connections
The CS4245 DACs implement a switched-capacitor filter, followed by a continuous time low-pass filter. Its
response, combined with tha t of the digital interpolator, is sh own in Section 8. “DAC Filter Plots” on
page 53”. The recommended external analog circuitry is shown in the Typical Connection Diagram.
The CS4245 DAC does not include phase or amplitude compensation for an external filter. Therefore, the
DAC system phase and amplitude response is dependent on the external analog circuitry.
34DS656F3
4.7Output Transient Control
The CS4245 uses Popguard® technology to minimize the effects of output transients during power-up and
power-down. This technique eliminates the audio transients commonly produced by single-ended, singlesupply converters when it is implemented with external DC-blocking capacitors connected in series with the
audio outputs. To make best use of this feature, it is necessary to understand its operation.
4.7.1Power-Up
When the device is initially powered-up, the audio outputs AOUTA and AOUTB are clamped to VQ2,
which is initially low. After the PDN bit is released (set to ‘0’), the DAC outputs begin to ramp with VQ2
towards the nominal quiescent voltage. This ramp takes approximately 200 ms to complete. The gradual
voltage ramping allows time for the external DC-blocking capacitors to charge to VQ2, effectively blocking
the quiescent DC voltage. Audio output will begin after approximately 2000 sample periods.
4.7.2Power-Down
To prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turning off the power. In order to do this, either the PDN bit should be set or the device should be reset about
250 ms before removing power. During this time, the voltage on VQ2 and the DAC outputs discharge
gradually to GND. If power is removed before this 250 ms time period has passed, a transient will occur
when the VA supply drops below that of VQ2. There is no minimum time for a power cycle; power may be
re-applied at any time.
CS4245
4.7.3Serial Interface Clock Changes
When changing the DAC clock ratio or sample rate, it is recommended that zero data (or near zero data)
be present on SDIN for at least 10 LRCK samples before the change is made. During the clocking change,
the DAC outputs will always be in a zero data state. If non-zero serial audio input is present at the time of
switching, a slight click or pop may be heard as the DAC output automatically goes to its zero data state.
4.8Auxiliary Analog Output
The CS4245 includes an auxiliary analog output through the AUXOUT pins. These pins can be configured
to output the analog input to the ADC as se lected with the input MUX and gained or attenuated with the
PGA, the analog output of the DAC, or alternatively they may be set to high-impedance. See “Section 6.6.1
“Auxiliary Output Source Select (Bits 6:5)” on page 46” for information on configuring the auxiliary analog
output.
The auxiliary analog output can source very little current. As current from the AUXOUT pins increases, distortion will increase. For this reason, a high input impedance buffer must be used on the AUXOUT pins to
achieve full performance. Refer to the table in “Auxiliary Output Analog Characteristics” on page 17 for acceptable loading conditions.
4.9De-Emphasis Filter
The CS4245 includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter response is shown in Figure 15. The frequency response of the de-emphasis curve scales proportionally with
changes in sample rate, Fs. Please see Section 6.3.4 “De-Emphasis Control (Bit 1)” on page 44 for de-em-
phasis control.
The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 s pre-emphasis
equalization as a means of noise reduction.
DS656F335
De-emphasis is only available in Single-Speed Mode.
Gain
dB
-10dB
0dB
Frequency
T2 = 15 µs
T1=50 µs
F1F2
3.183 kHz10.61 kHz
Figure 15. De-Emphasis Curve
4.10Internal Digital Loopback
The CS4245 supports an internal digital loopback mode in which the output of the ADC is routed to the input
of the DAC. This mode may be activated by setting the LOOP bit in the Signal Selection register (See Sec-
tion 6.6 “Signal Selection - Address 06h” on page 46). To use this mode, the ADC and DAC must be oper-
ating at the same synchronous sample rate.
CS4245
When this bit is set, the status of the DAC_DIF[1:0] bits in register 03h will be disregarded by the CS4245.
Any changes made to the DAC_DIF[1:0] bits while the LOOP bit is set will have no impact on operation until
the LOOP bit is cleared, at which time the Digital Interface Format of the DAC will operate according to the
format selected by the DAC_DIF[1:0] bits. While the LOOP bit is set, data will be present on the SDOUT pin
in the format selected by the ADC_DIF bit in register 04h.
4.11Mute Control
The MUTEC pin becomes active during power-up initialization, reset, and muting if the MCLK2 to LRCK2
ratio is incorrect in Asynchronous Mode or the MCLK1 to LRCK2 ratio is incorrect in Synchronous Mode,
and during power-down. The MUTEC
order to add off-chip mute capability.
Use of the M ute Control function is not mandatory, but recommended, for designs requiring the absolute
minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system de-
pin is intended to be used as control for an external mute circuit in
36DS656F3
CS4245
LPF
+V
EE
-V
EE
560
Audio
Out
2 k
10 k
-V
EE
+V
A
MMUN2111LT1
AOUT
MUTEC
AC
Couple
47 k
Figure 16. Suggested Active-Low Mute Circuit
CS4245
signer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.
The MUTEC
pin is an active-low CMOS driver. See Figure 16 for a suggested active-low mute circuit.
4.12Control Port Description and Timing
The control port is used to access the registers, allowing the CS4245 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect
to the audio sample rates. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port has two modes: SPI and I²C, with the CS4245 acting as a slave device. SPI Mode is selected if there is a high-to-low transition on the AD0/CS
Mode is selected by connecting the AD0/CS
selecting the desired AD0 bit address state.
4.12.1SPI Mode
In SPI Mode, CS is the CS4245 chip-select signal; CCLK is the control port bit clock (input into the CS4245
from the microcontroller); CDIN is the input data line from the microcontroller; CDOUT is the output data
line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.
Figure 17 shows the operation of the control port in SPI Mode. To write to a register, bring CS
first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indi-
), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
high) immediately after the MAP byte. To begin a read, bring CS low, send out the chip ad-
cator (R/W
which is set to the address of the register that is to be updated. The next eight bits are the data that will
be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z
state. It may be externally pulled high or low with a 47 k resistor, if desired.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle which
finishes (CS
pin, after the RESET pin has been brought high. I²C
pin through a resistor to VLC or DGND, thereby permanently
low. The
DS656F337
CS4245
MAP
MSB
LSB
DATA
byte 1
byte n
R/W
R/W
ADDRESS
CHIP
ADDRESS
CHIP
CDIN
CCLK
CS
CDOUT
MSB
LSB
MSB
LSB
1001111
1001111
MAP = Memory Address Pointer, 8 bits, MSB first
High Impedance
Figure 17. Control Port Timing in SPI Mode
4 5 6 7 24 25
SCL
CHIP ADDRESS (WRITE)MAP BYTEDATA
DATA +1
START
ACK
STOP
ACKACKACK
1 0 0 1 1 AD1 AD0 0
SDA
6 6 5 4 3 2 1 0 7 6 1 07 6 1 07 6 1 0
0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28
26
DATA +n
Figure 18. Control Port Timing, I²C Write
dress and set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the
addressed register (CDOUT will leave the high-impedance state).
For both read and write cycles, the memory address pointer will automatically increment following each
data byte in order to facilitate block reads and writes of successive registers.
4.12.2I²C Mode
In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS
be connected through a resistor to VLC or DGND as desired. The state of the pins is sensed while the
CS4245 is being reset.
The signal timings for a read and write cycle are shown in Figure 18 and Figure 19. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS4245
after a Start condition consists of a 7-bit chip address field and a R/W
The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS4245, the chip
address field, which is the first byte sent to the CS4245, should match 10011 followed by the settings of
the AD1 and AD0. The eighth bit of the address is the R/W
the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a
read, the contents of the register pointed to by the MAP will be output. Following each data byte, the memory address pointer will automatically increment to facilitate block reads and writes of successive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS4245 after each
input byte is read, and is input to the CS4245 from the microcontroller after each transmitted byte.
pin. Pins AD0 and AD1 form the two least-significant bits of the chip address and should
bit (high for a read, low for a write).
bit. If the operation is a write, the next byte is
38DS656F3
CS4245
SCL
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
START
ACK
STOP
ACK
ACK
ACK
1 0 0 1 1 AD1 AD0 0
SDA
1 0 0 1 1 AD1 AD0 1
CHIP ADDRESS (READ)
START
7 6 5 4 3 2 1 0
7 07 07 0
NO
16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24
26 27 28
2 3 10 11 17 18 19 25
ACK
DATA + n
STOP
Figure 19. Control Port Timing, I²C Read
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 19, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 10011xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10011xx1 (chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
4.13Interrupts and Overflow
The CS4245 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt
input pin on the host microcontroller. The INT pin may function as either an active high CMOS driver or an
active low open-drain driver (see “Active High/Low (Bit 0)” on page 50). When configured as active low
open-drain, the INT pin has no active pull-up transistor, allowing it to be used for wired-OR hook-ups with
multiple peripherals connected to the microcontroller interrupt input pin. In this configuration, an external
pull-up resistor must be placed on the INT pin for proper operation.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions (see “Interrupt
Status - Address 0Dh” on page 50). Each source may be masked off through mask register bits. In addition,
each source may be set to rising edge, falling edge, or level-sensitive. Combined with the option of levelsensitive or edge-sensitive modes within the microcontroller, many different configurations are possible, depending on the needs of the equipment designer.
The CS4245 also has a de dicated overflow output. The OVFL pin functions as active low open drain and
has no active pull-up transistor, thereby requiring an external pull-up resistor. The OVFL pin outputs an OR
of the ADCOverflow and ADCUnderflow conditions available in the Interrupt Status register; however, these
conditions do not need to be unmasked for proper operation of the OVFL pin.
DS656F339
4.14Reset
When RESET is low, the CS4245 enters a low-power mode and all internal states are reset, including the
control port and registers, the outputs are muted. When RESET
al, and the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Power Control register will then cause the part to leave the low-power state and begin operation.
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either
through the application of power or by setting the RESET
much longer to reach a final value due to the presence of external capacitance on the FILT1+ and FILT2+
pins. During this voltage reference ramp delay, both SDOUT and DAC outputs will be automatically muted.
CS4245
is high, the control port becomes operation-
pin high. However, the voltage reference will take
It is recommended that RESET
operating condition to prevent power-glitch-related issues.
be activated if the analog or digital supplies drop below the recommended
4.15Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To
ensure synchronous sampling, the mast er clocks and left/ right clocks must be the same f or all of the
CS4245s in the system. If only one master clock source is needed, one solution is to place one CS4245 in
Master Mode, and slave all of the other CS4245s to the one master. If multiple master clock sources are
needed, a possible solution would be to supply all cl ocks from the same external source and time the
CS4245 reset with the inactive edge of master clock. This will ensure that all converters begin sampling on
the same clock edge.
4.16Grounding and Power Supply Decoupling
As with any high-resolution converter, the CS4245 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 12 shows the recommended power arrangements, with VA connected to a clean supply. VD, which powers the digital filter, may be run from the
system logic supply (VLS or VLC) or may be po wered from the analog supply (VA) via a resistor. In this
case, no additional devices should be powered from VD. Power supply decoupling capacitors should be as
near to the CS4245 as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT1+, FILT2+, VQ1 and VQ2 pins in order to avoid unwanted
coupling into the modulators. The FILT1+, FILT2+, VQ1 and VQ2 decoupling capacitors, particularly the
0.1 µF, must be positioned to minimize the electrical path from FILT1+ and FILT2+ and AGND. The CS4245
evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital
noise, connect the CS4245 digital outputs only to CMOS inputs.
40DS656F3
CS4245
5. REGISTER QUICK REFERENCE
This table shows the register names and their associated default values.
AddrFunction76543210
01h Chip IDPART3PART2PART1PART0REV3REV2REV1REV0
110 0 0 0 0 1
02h Power ControlFreezeReserved Reserved ReservedPDN_MICPDN_ADCPDN_DACPDN
000 0 0 0 0 1
03h DAC Control 1 DAC_FM1 DAC_FM0 DAC_DIF1 DAC_DIF0ReservedMuteDACDeEmphDAC_M/S
This register is Read-Only. Bits 7 through 4 are the part number ID, which is 1100b (0Ch), and the remaining
bits (3 through 0) indicate the device revision as shown in Table 5 below.
This function allows modifications to be made to certain control port bits without the changes taking effect
until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the
Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed
in Table 6.
NameRegisterBit(s)
MuteDAC03h2
MuteADC04h2
Gain[5:0]07h5:0
Gain[5:0]08h5:0
Vol[7:0]0Ah7:0
Vol[7:0]0Bh7:0
6.2.2Power-Down MIC (Bit 3)
Function:
The microphone preamplifier block will enter a low-power state whenever this bit is set.
6.2.3Power-Down ADC (Bit 2)
Function:
Table 6. Freeze-able Bits
The ADC pair will remain in a reset state whenever this bit is set.
42DS656F3
CS4245
6.2.4Power-Down DAC (Bit 1)
Function:
The DAC pair will remain in a reset state whenever this bit is set.
6.2.5Power-Down Device (Bit 0)
Function:
The device will enter a low-power state whenever this bit is set. The power-down bit is set by default and
must be cleared before normal operation can occur. The contents of the control registers are retained
when the device is in power-down.
The required relationship between LRCK, SCLK and SDIN for the DAC is defined by the DAC Digital Interface Format and the options are detailed in Table 8 and Figures 7-9.
DAC_DIF1 DAC_DIF0DescriptionFormatFigure
00Left Justified, up to 24-bit data (default)07
01I²S, up to 24-bit data18
10Right-Justified, 16-bit Data29
11Right-Justified, 24-bit Data39
T able 8. DAC Digital Interface Formats
6.3.3Mute DAC (Bit 2)
Function:
The DAC outputs will mute and the MUTEC
active high, it should be noted that the MUTEC
will be retained when this bit is set. The muting function is effected, similar to attenuation changes, by the
DACSoft and DACZero bits in the DAC Control 2 register.
pin will become active when this bit is set. Though this bit is
pin is active low. The common mode voltage on the outputs
DS656F343
6.3.4De-Emphasis Control (Bit 1)
Gain
dB
-10dB
0dB
Frequency
T2 = 15 µs
T1=50 µs
F1F2
3.183 kHz10.61 kHz
Figure 20. De-Emphasis Curve
Function:
The standard 50/15 s digital de-emphasis filter response, Figure 20, may be implemented for a sample
rate of 44.1 kHz when the DeEmph bit is configured as shown in Table 9. NOTE: De-emphasis is available
only in Single-Speed Mode.
DeEmphDescription
0Disabled (default)
144.1 kHz de-emphasis
Table 9. De-Emphasis Control
CS4245
6.3.5DAC Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for serial audio port 2. Setting this bit will select Master
Mode, while clearing this bit will select Slave Mode.
Selects the required range of output sample rates.
ADC_FM1ADC_FM0Mode
00Single-Speed Mode: 4 to 50 kHz sample rates
01Double-Speed Mode: 50 to 100 kHz sample rates
10Quad-Speed Mode: 100 to 200 kHz sample rates
11Reserved
T a ble 10. Fu nctio nal Mod e Selection
44DS656F3
6.4.2ADC Digital Interface Format (Bit 4)
Function:
The required relationship between LRCK1, SCLK1 and SDOUT is defined by the ADC Digital Interface
Format bit. The options are detailed in Table 11 and may be seen in Figure 7 and Figure 8.
ADC_DIFDescriptionFormatFigure
0Left-Justified, up to 24-bit data (default)07
1I²S, up to 24-bit data18
Table 11. ADC Digital Interface Formats
6.4.3Mute ADC (Bit 2)
Function:
When this bit is set, the serial audio output of the both ADC channels is muted.
6.4.4ADC High-Pass Filter Freeze (Bit 1)
Function:
When this bit is set, the internal high-pass filter is disabled. The current DC offset value will be frozen and
continue to be subtracted from the conversion result. See “High-Pass Filter and DC Offset Calibration” on
page 32.
CS4245
6.4.5ADC Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for serial audio port 1. Setting this bit selects Master
Mode, while clearing this bit selects Slave Mode.
6.5MCLK Frequency - Address 05h
76543210
Reserved
MCLK1
Freq2
MCLK1
Freq1
MCLK1
Freq0
Reserved
MCLK2
Freq2
MCLK2
Freq1
MCLK2
Freq0
6.5.1Master Clock 1 Frequency (Bits 6:4)
Function:
Sets the frequency of the supplied MCLK1 signal. See Table 12 for the appropriate settings.
MCLK1 DividerMCLK1 Freq2 MCLK1 Freq1 MCLK1 Freq0
÷1000
÷1.5001
÷2010
÷3011
÷4100
Reserved101
Reserved11x
Table 12. MCLK 1 Frequency
DS656F345
CS4245
6.5.2Master Clock 2 Frequency (Bits 2:0)
Function:
These bits set the frequency of the supplied MCLK2 signal. See Table 13 for the appropriate settings.
When this bit is set, an internal digital loopback from the ADC to the DAC are enabled. Please refer to
“Internal Digital Loopback” on page 36.
6.6.3Asynchronous Mode (Bit 0)
Function:
When this bit is set, the DAC and ADC may be operated at independent asynchronous sample rates derived from MCLK1 and MCLK2. When this bit is cleared, the DAC and ADC must operate at synchronous
sample rates derived from MCLK1.
46DS656F3
CS4245
6.7Channel B PGA Control - Address 07h
76543210
ReservedReservedGain5Gain4Gain3Gain2Gain1Gain0
6.7.1Channel B PGA Gain (Bits 5:0)
Function:
See “Channel A PGA Gain (Bits 5:0)” on page 47.
6.8Channel A PGA Control - Address 08h
76543210
ReservedReservedGain5Gain4Gain3Gain2Gain1Gain0
6.8.1Channel A PGA Gain (Bits 5:0)
Function:
Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to
+12 dB in 0.5 dB steps. The gain bits are in two’s complement with the Gain0 bit set for a 0.5 dB step.
Register settings outside of the ±12 dB range are reserved and must not be used. See Table 15 for example settings.
6.9.1PGA Soft Ramp or Zero Cross Enable (Bits 4:3)
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
See Table 16.
Zero Cross Enable
Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel. See Table 16.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal-level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
DS656F347
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 16.
PGASoftPGAZeroCrossMode
00Changes to affect immediately
01Zero Cross enabled
10Soft Ramp enabled
11Soft Ramp and Zero Cross enabled (default)
Table 16. PGA Soft Cross or Zero Cross Mode Selection
6.9.2Analog Input Selection (Bits 2:0)
Function:
These bits are used to select the input source for the PGA and ADC. Please see Table 17.
Sel2Sel1Sel0PGA/ADC Input
000Microphone-Level Inputs (+32 dB Gain Enabled)
001Line-Level Input Pair 1
010Line-Level Input Pair 2
011Line-Level Input Pair 3
100Line-Level Input Pair 4
101Line-Level Input Pair 5
110Line-Level Input Pair 6
111Reserved
CS4245
Table 17. Analog Input Multiplexer Selection
6.10DAC Channel A Volume Control - Address 0Ah
See 6.11DAC Channel B Volume Control - Address 0Bh.
6.11DAC Channel B Volume Control - Address 0Bh
76543210
Vol7Vol6Vol5Vol4Vol3Vo l2Vol1Vol0
6.11.1Volume Control (Bits 7:0)
Function:
The digital volume control allows the user to attenuate the signal in 0.5 dB increments from 0 to -127 dB.
The Vol0 bit activates a 0.5 dB attenuation when set, and no attenuation when cleared. The Vol[7:1] bits
activate attenuation equal to their decimal equivalent (in dB). Example volume settings are decoded as
48DS656F3
CS4245
shown in Table 18. The volume changes are implemented as dictated by the DACSoft and DACZeroCross bits in the DAC Control 2 register (see Section 6.12.1).
Binary CodeVolume Setting
000000000 dB
00000001-0.5 dB
00101000-20 dB
00101001-20.5 dB
6.12.1DAC Soft Ramp or Zero Cross Enable (Bits 7:6)
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
See Table 19.
Zero Cross Enable
Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel. See Table 19.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal-level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 19.
DACSoftDACZeroCrossMode
00Changes to affect immediately
01Zero Cross enabled
10Soft Ramp enabled
11Soft Ramp and Zero Cross enabled (default)
Table 19. DAC Soft Cross or Zero Cross Mode Selection
6.12.2Invert DAC Output (Bit 5)
Function:
When this bit is set, the output of the DAC is inverted.
DS656F349
CS4245
6.12.3Active High/Low (Bit 0)
Function:
When this bit is set, the INT pin functions as an active high CMOS driver.
When this bit is cleared, the INT pin functions as an active low open drain driver and will require an external pull-up resistor for proper operation.
For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since
the register was last read. A ‘0’ me ans the associated interrupt condition has NOT occurred since the last
reading of the register. Status bits that are masked off in the associated mask register will always be ‘0’ in
this register. This register defaults to 00h.
6.13.1ADC Clock Error (Bit 3)
Function:
Indicates the occurrence of an ADC clock error condition.
6.13.2DAC Clock Error (Bit 2)
Function:
Indicates the occurrence of a DAC clock error condition.
6.13.3ADC Overflow (Bit 1)
Function:
Indicates the occurrence of an ADC overflow condition.
6.13.4ADC Underflow (Bit 0)
Function:
Indicates the occurrence of an ADC underflow condition.
The bits of this register serve as a mask for the Status sources found in the register “Interrupt Status - Ad-
dress 0Dh” on page 50. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect
the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence
will not affect the INT pin or the status register. The bit positions align with the corresponding bits in the Status register.
The two Inter rupt Mode registers form a 2-bit code for each Interrupt Status register function. There are
three ways to set the INT pin active in accordance with the interrupt condition. In the Rising-Edge Active
Mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling-Edge Active Mode,
the INT pin becomes active on the removal of the interrupt condition. In Level-Active Mode, the INT pin remains active during the interrupt condition.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
DS656F351
7. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full scale. This
technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Au dio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.
CS4245
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
– Removed the MAP auto-increment functional description from the Control Port Description and Timing section
beginning on page 37.
F1
F2
F3
– Added device revision information to the Chip ID - Register 01h description on page 42.
– Updated the VQ1 Output Impedance specification in the DC Electrical Characteristics table on page 20.
– Updated the Microphone Interchannel Isolation specification in the ADC Analog Characteristics table on page 15.
– Added Automotive Grade
– Changed MCLK1 and MCLK2 to input only in the Pin Descriptions table on page 7.
– Updated the DAC Analog Characteristics table on page 10.
– Updated the ADC Analog Characteristics table on page 13.
– Updated the Auxiliary Output Analog Characteristics table on page 17.
– Updated the DC Electrical Characteristics table on page 20.
– Updated the Digital Interface Characteristics table on page 21.
– Updated the Switching Characteristics - Serial Audio Port 1 table on page 22.
– Updated the Switching Characteristics - Control Port - SPI Format table on page 28.
– Updated the Typical Connection Diagram on page 29.
– Switched Channel B PGA Control - Address 07h on page 47 and Channel A PGA Control - Address 08h on
page 47.
– Added Table 3.
58DS656F3
CS4245
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY A PPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD
TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED
IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER
AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH
THESE USES.
Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be
trademarks or service marks of their respective owners.
I²C is a registered trademark of Philips Semiconductor.
SPI is a trademark of Motorola, Inc.
DS656F359
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