Cirrus Logic CS4245 User Manual
1.8 V to 5 V
Multibit
Modulator
Multibit
Modulator
Low-Latency
Anti-Alias Filter
Internal Voltage
Reference
Interpolation
Filter
Interpolation
Filter
Left DAC Output
Right DAC Output
Switched Capacito r
DAC and Filter
Multibit
Oversampling
ADC
Multibit
Oversampling
ADC
Low-Latency
Anti-Alias Filter
High Pass
Filter
High Pass
Filter
Stereo Input 1
Serial
Audio
Input
Serial
Audio
Output
3.3 V to 5 V 3.3 V to 5 V
Switched Capacito r
DAC and Filter
MUX
PGA
MUX
Volume
Control
Volume
Control
PCM Serial InterfacePCM Serial Interface
Mute
Control
Register Configuration
Level
Translator
Level Translator
Level
Translator
Reset
I2C/SPI
Control Data
Mute Control
Left Aux Output
Right Aux Output
Stereo Input 2
Stereo Input 3
Stereo Input 4 /
Mic Input 1 & 2
Stereo Input 5
Stereo Input 6
PGA
+32 dB
+32 dB
Interrupt
ADC Overflow
CS4245
104 dB, 24-Bit, 192 kHz Stereo Audio CODEC
D/A Features
Multi-bit Delta Sigma Modulator
104 dB Dynamic Range
-90 dB THD+N
Up to 192 kHz Sampling Rates
Single-Ended Analog Architecture
Volume Control with Soft Ramp
– 0.5 dB Step Size
– Zero Crossing, Click-Free Transitions
Popguard
– Minimizes the Effects of Output Transients
Filtered Line-Level Outputs
Selectable Serial Audio Interface Formats
– Left-Justified up to 24-bit
– I²S up to 24-bit
– Right-Justified 16-, 18-, 20-, and 24-bit
Selectable 50/15 µs De-Emphasis
Control Output for External Muting
®
Technology
A/D Features
Multi-bit Delta Sigma Modulator
104 dB Dynamic Range
-95 dB THD+N
Stereo 6:1 Input Multiplexer
Programmable Gain Amplifier (PGA)
– ± 12 dB Gain, 0.5 dB Step Size
– Zero Crossing, Click-Free Transitions
Stereo Microphone Inputs
– +32 dB Gain Stage
– Low-Noise Bias Supply
Up to 192 kHz Sampling Rates
Selectable Serial Audio Interface Formats
– Left-Justified up to 24-bit
– I²S up to 24-bit
High-Pass Filter or DC Offset Calibration
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2012
(All Rights Reserved)
AUG '12
DS656F3
CS4245
System Features
Direct Interface with 1.8 V to 5 V Logic Levels
Optional Asynchronous Serial Port Operation
– Each Serial Port Supports Master or Slave
Operation
Selectable Auxiliary Analog Output
– Allows Analog Monitoring of Either the ADC
Input Signal after PGA or DAC Output
Signal
Internal Digital Loopback
Power-Down Mode
– Available for A/D, D/A, CODEC, Mic
Preamplifier
+3.3 V to +5 V Analog Power Supply
+3.3 V to +5 V Digital Power Supply
Supports I²C
Interfaces
Pin-Compatible with CS5345
®
and SPITM Control Port
General Description
The CS4245 is a h ighly integrated stereo audio
CODEC. The CS4245 performs stereo analog-to-digital
(A/D) and digital-to-analog (D/A) conversion of up to
24-bit serial values at sample rates up to 192 kHz.
A 6:1 stereo input multiplexer is included for s electing
between line-level or microphone-level inputs. The microphone input path includes a +32 dB gain stage and
a low-noise bias voltage supply. The PGA is available
for line or microphone inputs and provides gain/attenuation of 12 dB in 0.5 dB steps.
The output of the PGA is followed by an advanced 5thorder, multi-bit delta sigma modulator and digital filtering/decimation. Sampled data is transmitted by the
serial audio interface at rates from 4 kHz to 192 kHz in
either Slave or Master Mode.
The D/A converter is based on a 4th-order multi-bit delta
sigma modulator with an ultra-linear low-pass filter and
offers a volume control that operates with a 0.5 dB step
size. It in corporates selectable soft ramp and zero
crossing transition functions to eliminate clicks and
pops.
Standard 50/15 s de-emphasis is availa ble for a
44.1 kHz sample rate for compatibility with digital audio
programs mastered using the 50 /15 s pre-emphasis
technique.
Integrated level translators allow easy interfacing between the CS4245 and other devices operating over a
wide range of logic levels.
The CS4245 is available in a 48-pin LQFP package in
both Commercial (-10° to +70° C) and Automotive (-40°
to +105° C) grade. The CDB4245 Customer Demonstration board is also available for device evaluation and
implementation suggestions. Please see “Ordering In-
formation” on page 58 for complete details.
2 DS656F3
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ........................................................................................................................ 7
2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 9
SPECIFIED OPERATING CONDITIONS ............................................................................................. 9
ABSOLUTE MAXIMUM RATINGS .......................................................................................................9
DAC ANALOG CHARACTERISTICS ................................................................................................. 10
DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ............................ 11
ADC ANALOG CHARACTERISTICS ................................................................................................. 13
ADC ANALOG CHARACTERISTICS ................................................................................................. 15
ADC DIGITAL FILTER CHARACTERISTICS ..................................................................................... 16
AUXILIARY OUTPUT ANALOG CHARACTERISTICS ...................................................................... 17
AUXILIARY OUTPUT ANALOG CHARACTERISTICS ...................................................................... 18
AUXILIARY OUTPUT ANALOG CHARACTERISTICS ...................................................................... 19
DC ELECTRICAL CHARACTERISTICS ............................................................................................. 20
DIGITAL INTERFACE CHARACTERISTICS ...................................................................................... 21
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 1 .......................................................... 22
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 2 .......................................................... 24
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ............................................ 27
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ........................................... 28
3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 29
4. APPLICATIONS ................................................................................................................................... 30
4.1 Recommended Power-Up Sequence ............................................................................................. 30
4.2 System Clocking ............................................................................................................................. 30
4.2.1 Synchronous / Asynchronous Mode ...................................................................................... 30
4.2.2 Master Clock ......................................................................................................................... 30
4.2.3 Master Mode ......................................................................................................................... 32
4.2.4 Slave Mode ........................................................................................................................... 32
4.3 High-Pass Filter and DC Offset Calibration .................................................................................... 32
4.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................................34
4.5 Input Connections ........................................................................................................................... 34
4.6 Output Connections ........................................................................................................................ 34
4.7 Output Transient Control ................................................................................................................ 35
4.7.1 Power-Up .............................................................................................................................. 35
4.7.2 Power-Down .......................................................................................................................... 35
4.7.3 Serial Interface Clock Changes ............................................................................................. 35
4.8 Auxiliary Analog Output .................................................................................................................. 35
4.9 De-Emphasis Filter ......................................................................................................................... 35
4.10 Internal Digital Loopback .............................................................................................................. 36
4.11 Mute Control ................................................................................................................................. 36
4.12 Control Port Description and Timing ............................................................................................. 37
4.12.1 SPI Mode ............................................................................................................................. 37
4.12.2 I²C Mode .............................................................................................................................. 38
4.13 Interrupts and Overflow ................................................................................................................ 39
4.14 Reset ............................................................................................................................................ 40
4.15 Synchronization of Multiple Devices ............................................................................................. 40
4.16 Grounding and Power Supply Decoupling .................................................................................... 40
5. REGISTER QUICK REFERENCE ........................................................................................................ 41
6. REGISTER DESCRIPTION .................................................................................................................. 42
6.1 Chip ID - Register 01h .................................................................................................................... 42
6.2 Power Control - Address 02h ......................................................................................................... 42
6.2.1 Freeze (Bit 7) ......................................................................................................................... 42
6.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 42
6.2.3 Power-Down ADC (Bit 2) .............................
CS4245
.......................................................................... 42
DS656F3 3
CS4245
6.2.4 Power-Down DAC (Bit 1) ....................................................................................................... 43
6.2.5 Power-Down Device (Bit 0) ................................................................................................... 43
6.3 DAC Control - Address 03h ............................................................................................................ 43
6.3.1 DAC Functional Mode (Bits 7:6) ............................................................................................ 43
6.3.2 DAC Digital Interface Format (Bits 5:4) ................................................................................. 43
6.3.3 Mute DAC (Bit 2) ................................................................................................................... 43
6.3.4 De-Emphasis Control (Bit 1) .................................................................................................. 44
6.3.5 DAC Master / Slave Mode (Bit 0) ..........................................................................................44
6.4 ADC Control - Address 04h ............................................................................................................ 44
6.4.1 ADC Functional Mode (Bits 7:6) ............................................................................................ 44
6.4.2 ADC Digital Interface Format (Bit 4) ...................................................................................... 45
6.4.3 Mute ADC (Bit 2) ................................................................................................................... 45
6.4.4 ADC High-Pass Filter Freeze (Bit 1) ..................................................................................... 45
6.4.5 ADC Master / Slave Mode (Bit 0) ..........................................................................................45
6.5 MCLK Frequency - Address 05h .................................................................................................... 45
6.5.1 Master Clock 1 Frequency (Bits 6:4) ..................................................................................... 45
6.5.2 Master Clock 2 Frequency (Bits 2:0) ..................................................................................... 46
6.6 Signal Selection - Address 06h ...................................................................................................... 46
6.6.1 Auxiliary Output Source Select (Bits 6:5) .............................................................................. 46
6.6.2 Digital Loopback (Bit 1) ......................................................................................................... 46
6.6.3 Asynchronous Mode (Bit 0) ................................................................................................... 46
6.7 Channel B PGA Control - Address 07h .......................................................................................... 47
6.7.1 Channel B PGA Gain (Bits 5:0) ............................................................................................. 47
6.8 Channel A PGA Control - Address 08h .......................................................................................... 47
6.8.1 Channel A PGA Gain (Bits 5:0) ............................................................................................. 47
6.9 ADC Input Control - Address 09h ................................................................................................... 47
6.9.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3) .................................................................. 47
6.9.2 Analog Input Selection (Bits 2:0) ........................................................................................... 48
6.10 DAC Channel A Volume Control - Address 0Ah ........................................................................... 48
6.11 DAC Channel B Volume Control - Address 0Bh ........................................................................... 48
6.11.1 Volume Control (Bits 7:0) .................................................................................................... 48
6.12 DAC Control 2 - Address 0Ch ...................................................................................................... 49
6.12.1 DAC Soft Ramp or Zero Cross Enable (Bits 7:6) ................................................................ 49
6.12.2 Invert DAC Output (Bit 5) .................................................................................................... 49
6.12.3 Active High/Low (Bit 0) ........................................................................................................ 50
6.13 Interrupt Status - Address 0Dh ..................................................................................................... 50
6.13.1 ADC Clock Error (Bit 3) ....................................................................................................... 50
6.13.2 DAC Clock Error (Bit 2) ....................................................................................................... 50
6.13.3 ADC Overflow (Bit 1) ........................................................................................................... 50
6.13.4 ADC Underflow (Bit 0) ......................................................................................................... 50
6.14 Interrupt Mask - Address 0Eh ....................................................................................................... 50
6.15 Interrupt Mode MSB - Address 0Fh .............................................................................................. 51
6.16 Interrupt Mode LSB - Address 10h .........................................................................................
ARAMETER DEFINITIONS ................................................................................................................ 52
7. P
8. DAC FILTER PLOTS .................................................................................................................... 53
9. ADC FILTER PLOTS ......................................................................................................................... 55
10. PACKAGE DIMENSIONS .................................................................................................................. 57
11. THERMAL CHARACTERISTICS AND SPECIFICATIONS ............................................................. 57
12. ORDERING INFORMATION ..................................................................................................... 58
13. REVISION HISTORY .......................................................................................................................... 58
...... 51
4 DS656F3
LIST OF FIGURES
Figure 1.DAC Output Test Load ................................................................................................................ 12
Figure 2.Maximum DAC Loading .............................................................................................................. 12
Figure 3.Master Mode Timing - Serial Audio Port 1 .................................................................................. 23
Figure 4.Slave Mode Timing - Serial Audio Port 1 .................................................................................... 23
Figure 5.Master Mode Timing - Serial Audio Port 2 .................................................................................. 25
Figure 6.Slave Mode Timing - Serial Audio Port 2 .................................................................................... 25
Figure 7.Format 0, Left-Justified up to 24-Bit Data ................................................................................... 26
Figure 8.Format 1, I²S up to 24-Bit Data ................................................................................................... 26
Figure 9.Format 2, Right-Justified 16-Bit Data.
Format 3, Right-Justified 24-Bit Data. ....................................................................................................... 26
Figure 10.Control Port Timing - I²C Format ............................................................................................... 27
Figure 11.Control Port Timing - SPI Format .............................................................................................. 28
Figure 12.Typical Connection Diagram ..................................................................................................... 29
Figure 13.Master Mode Clocking .............................................................................................................. 32
Figure 14.Analog Input Architecture .......................................................................................................... 34
Figure 15.De-Emphasis Curve .................................................................................................................. 36
Figure 16.Suggested Active-Low Mute Circuit .......................................................................................... 37
Figure 17.Control Port Timing in SPI Mode .............................................................................................. 38
Figure 18.Control Port Timing, I²C Write ................................................................................................... 38
Figure 19.Control Port Timing, I²C Read ................................................................................................... 39
Figure 20.De-Emphasis Curve .................................................................................................................. 44
Figure 21.DAC Single-Speed Stopband Rejection ................................................................................... 53
Figure 22.DAC Single-Speed Transition Band .......................................................................................... 53
Figure 23.DAC Single-Speed Transition Band .......................................................................................... 53
Figure 24.DAC Single-Speed Passband Ripple ........................................................................................ 53
Figure 25.DAC Double-Speed Stopband Rejection ..................................................................................53
Figure 26.DAC Double-Speed Transition Band ........................................................................................ 53
Figure 27.DAC Double-Speed Transition Band ........................................................................................ 54
Figure 28.DAC Double-Speed Passband Ripple ...................................................................................... 54
Figure 29.DAC Quad-Speed Stopband Rejection ..................................................................................... 54
Figure 30.DAC Quad-Speed Transition Band ........................................................................................... 54
Figure 31.DAC Quad-Speed Transition Band ........................................................................................... 54
Figure 32.DAC Quad-Speed Passband Ripple ......................................................................................... 54
Figure 33.ADC Single-Speed Stopband Rejection ................................................................................... 55
Figure 34.ADC Single-Speed Stopband Rejection ................................................................................... 55
Figure 35.ADC Single-Speed Transition Band (Detail) ............................................................................. 55
Figure 36.ADC Single-Speed Passband Ripple ........................................................................................ 55
Figure 37.ADC Double-Speed Stopband Rejection ..................................................................................55
Figure 38.ADC Double-Speed Stopband Rejection ..................................................................................55
Figure 39.ADC Double-Speed Transition Band (Detail) ............................................................................56
Figure 40.ADC Double-Speed Passband Ripple ...................................................................................... 56
Figure 41.ADC Quad-Speed Stopband Rejection ..................................................................................... 56
Figure 42.ADC Quad-Speed Stopband Rejection ..................................................................................... 56
Figure 43.ADC Quad-Speed Transition Band (Detail) ..............................................................................56
Figure 44.ADC Quad-Speed Passband Ripple ......................................................................................... 56
CS4245
LIST OF TABLES
Table 1. Speed Modes .............................................................................................................................. 30
Table 2. Common Clock Frequencies ....................................................................................................... 31
Table 3. Slave Mode MCLK Dividers ........................................................................................................ 31
Table 4. Slave Mode Serial Bit Clock Ratios ............................................................................................. 32
Table 5. Device Revision .......................................................................................................................... 42
DS656F3 5
CS4245
Table 6. Freeze-able Bits .......................................................................................................................... 42
Table 7. Functional Mode Selection ......................................................................................................... 43
Table 8. DAC Digital Interface Formats .................................................................................................... 43
Table 9. De-Emphasis Control .................................................................................................................. 44
Table 10. Functional Mode Selection ........................................................................................................ 44
Table 11. ADC Digital Interface Formats .................................................................................................. 45
Table 12. MCLK 1 Frequency ................................................................................................................... 45
Table 13. MCLK 2 Frequency ................................................................................................................... 46
Table 14. Auxiliary Output Source Selection ............................................................................................. 46
Table 15. Example Gain and Attenuation Settings ................................................................................... 47
Table 16. PGA Soft Cross or Zero Cross Mode Selection ........................................................................ 48
Table 17. Analog Input Multiplexer Selection ............................................................................................ 48
Table 18. Digital Volume Control Example Settings ................................................................................. 49
Table 19. DAC Soft Cross or Zero Cross Mode Selection ........................................................................ 49
6 DS656F3
1. PIN DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
VLSSDA/CDOUT
AGND
OVFL
SCL/CCLK
AD0/CS
AD1/CDIN
VLC
RESET
AIN3A
AIN3B
AIN2A
AIN2B
AIN1A
AIN1B
VA
AFILTB
VQ1
VQ2
FILT1+
FILT2+
AIN4A/MICIN1
AIN4B/MICIN2
AIN5A
AIN5B
AFILTA
MUTEC
AOUTB
AOUTA
AGND
AGND
VA
AUXOUTB
AUXOUTA
AIN6B
AIN6A
MICBIAS
INTVDDGND
MCLK1
LRCK1
SCLK1
SDOUT
MCLK2
LRCK2
SCLK2
SDIN
CS4245
CS4245
Pin Name # Pin Description
SDA/CDOUT 1
SCL/CCLK 2 Serial Control Port Clock (Input) - Serial clock for the serial control port.
AD0/CS
AD1/CDIN 4
VLC 5
RESET
AIN3A
AIN3B
AIN2A
AIN2B
AIN1A
AIN1B
DS656F3 7
Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode. CDOUT is the output data line for
the control port interface in SPI Mode.
Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode;
3
CS
Address Bit 1 (I²C) / Serial Control Data Input (SPI) (Input) - AD1 is a chip address pin in I²C Mode;
CDIN is the input data line for the control port interface in SPI Mode.
Control Port Power (Input) - Determines the required signal level for the control port interface. Refer
to the Recommended Operating Conditions for appropriate voltages.
6 Reset (Input) - The device enters a low power mode when this pin is driven low.
Stereo Analog Input 3 (Input) - The full-scale level is specified in the ADC Analog Characteristics
7, 8
specification table.
Stereo Analog Input 2 (Input) - The full-scale level is specified in the ADC Analog Characteristics
9, 10
specification table.
Stereo Analog Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics
11, 1 2
specification table.
is the chip-select signal for SPI format.
CS4245
AGND 13 Analog Ground (Input) - Ground reference for the internal analog section.
VA 14 Analog Power (Input) - Positive power for the internal analog section.
AFILTA 15 Antialias Filter Connection (Output) - Antialias filter connection for the channel A ADC input.
AFILTB 16 Antialias Filter Connection (Output) - Antialias filter connection for the channel B ADC input.
VQ1 17 Quiescent Voltage 1 (Output) - Filter connection for the internal quiescent reference voltage.
VQ2 18 Quiescent Voltage 2 (Output) - Filter connection for the internal quiescent reference voltage.
FILT1+ 19 Positive Voltage Reference 1 (Output) - Positive reference voltage for the internal sampling circuits.
FILT2+ 20 Positive Voltage Reference 2 (Output) - Positive reference voltage for the internal sampling circuits.
AIN4A/MICIN1
AIN4B/MICIN2
AIN5A
AIN5B
MICBIAS 25
AIN6A
AIN6B
AUXOUTA
AUXOUTB
VA 30 Analog Power (Input) - Positive power for the internal analog section.
AGND 31, 32 Analog Ground (Input) - Ground reference for the internal analog section.
AOUTA
AOUTB
MUTEC
VLS 36
SDIN 37 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
SCLK2 38 Serial Port 2 Serial Bit Clock (Input/Output) - Serial bit clock for serial audio interface 2.
LRCK2 39
MCLK2 40 Master Clock 2 (Input) - Optional asynchronous clock source for the DAC’s delta-sigma modulators.
SDOUT 41 Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
SCLK1 42 Serial Port 1 Serial Bit Clock (Input/Output) - Serial bit clock for serial audio interface 1.
LRCK1 43
MCLK1 44
DGND 45 Digital Ground (Input) - Ground reference for the internal digital section.
VD 46 Digital Power (Input) - Positive power for the internal digital section.
INT 47 Interrupt (Output) - Indicates an interrupt condition has occurred.
OVFL 48 ADC Overflow (Output) - Indicates an ADC overflow condition is present.
Stereo Analog Input 4 / Micropho ne Inp ut 1 & 2 (Input) - The full-scale level is specified in the ADC
21, 22
Analog Characteristics specification table.
Stereo Analog Input 5 (Input) - The full-scale level is specified in the ADC Analog Characteristics
23, 24
specification table.
Microphone Bias Supply (Output) - Low-noise bias supply for external microphone. Electrical charac-
teristics are specified in the DC Electrical Characteristics specification table.
Stereo Analog Input 6 (Input) - Th
26, 27
specification table.
Auxiliary Analog Au dio Ou tput (Output) - Analog output from either the DAC, the PGA block, or high
28, 29
impedance. See “Auxiliary Output Source Select (Bits 6:5)” on page 46.
DAC Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Char-
33, 34
acteristics specification table.
Mute Control (Output) - This pin is active during power-up initialization, reset, muting, when master
35
clock to left/right clock frequency ratio is incorrect, or power-down.
Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio inter-
face. Refer to the Recommended Operating Conditions for appropriate voltages.
Serial Port 2 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently
active on the serial audio input data line.
Serial Port 1 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently
active on the serial audio output data line.
Master Clock 1 (Input) - Clock source for the ADC’s delta-sigma modulators. By default, this signal
also clocks the DAC’s delta-sigma modulators.
e full-scale level is specified in the ADC Analog Characteristics
8 DS656F3
2. CHARACTERISTICS AND SPECIFICATIONS
SPECIFIED OPERATING CONDITIONS
AGND = DGND = 0 V; All voltages with respect to ground.
Parameters Symbol Min Nom Max Units
DC Power Supplies: Analog
Digital
Logic - Serial Port
Logic - Control Port
Ambient Operating Temperature (Power Applied) T
VA
VD
VLS
VLC
Notes: 1. Maximum of VA+0.25 V or 5.25 V, whichever is less.
ABSOLUTE MAXIMUM RATINGS
AGND = DGND = 0 V All voltages with respect to ground. (Note 2)
Parameter Symbol Min Max Units
DC Power Supplies: Analog
Digital
Logic - Serial Port
Logic - Control Port
Input Current (Note 3)
Analog Input Voltage
Digital Input Voltage Logic - Serial Port
Logic - Control Port
Ambient Operating Temperature (Power Applied)
Storage Temperature
VLS
VLC
V
V
V
A
VA
VD
I
in
INA
IND-S
IND-C
T
A
T
stg
CS4245
3.13
3.13
1.71
1.71
-10 - +70 C
AGND-0.3 VA+0.3 V
5.0
3.3
3.3
3.3
-0.3
-0.3
-0.3
-0.3
- 10 mA
-0.3
-0.3
-50 +125 C
-65 +150 C
5.25
(Note 1)
5.25
5.25
+6.0
+6.0
+6.0
+6.0
VLS+0.3
VLC+0.3
V
V
V
V
V
V
V
V
V
V
2. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
3. Any pin except s upplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
DS656F3 9
CS4245
DAC ANALOG CHARACTERISTICS
Test Conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V
or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; T
+85° C for Automotive; Output test signal: 997 Hz full-scale sine wave; Test load R
Figure 1), Fs = 48/96/192 kHz. Measurement Bandwidth 10 Hz to 20 kHz Synchronous mode; All Connections as
shown in Figure 12 on page 29.
Commercial Grade Automotive Grade
Parameter
Symbol Min Typ Max Min Typ Max Unit
Dynamic Performance for VA = 4.75 V to 5.25 V
Dynamic Range (Note 4)
18 to 24-Bit A-Weighted
unweighted
16-Bit A-Weighted
unweighted
Total Harmonic Distortion + Noise (Note 4)
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
THD+N
98
95
90
87
-
-
-
-
-
-
Dynamic Performance for VA = 3.13 V to 3.46 V
Dynamic Range (Note 4)
18 to 24-Bit A-Weighted
unweighted
16-Bit A-Weighted
unweighted
Total Harmonic Distortion + Noise (Note 4)
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
Interchannel Isolation (1 kHz) - 100 - - 100 - dB
THD+N
95
92
88
85
-
-
-
-
-
-
DC Accuracy
Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB
Gain Drift - 100 - - 100 - ppm/°C
Analog Output
Full Scale Output Voltage 0.60*VA 0.65*VA 0.70*VA 0.60*VA 0.65*VA 0.70*VA V
DC Current draw from an AOUT pin (Note 5) I
AC-Load Resistance (Note 6) R
Load Capacitance (Note 6) C
Output Impedance Z
OUT
L
L
OUT
--10--10A
3--3- -k
- - 100 - - 100 pF
-150- -150-
= -10° to +70° C for Commercial or -40° to
104
101
96
93
-90
-81
-41
-93
-73
-33
101
98
93
90
-87
-78
-38
-90
-70
-30
A
-
-
-
-
-84
-
-
-87
-
-
-
-
-
-
-79
-
-
-82
-
-
= 3 k, CL = 10 pF (see
L
96
93
88
85
-
-
-
-
-
-
93
90
86
83
-
-
-
-
-
-
104
101
96
93
-90
-81
-41
-93
-73
-33
101
98
93
90
-87
-78
-38
-90
-70
-30
-
-
-
-
-82
-
-
-85
-
-
-
-
-
-
-77
-
-
-80
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
pp
4. One-half LSB of triangular PDF dither added to data.
5. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin
due to typical leakage through the electrolytic DC blocking capacitors.
10 DS656F3
CS4245
6. Guaranteed by design. See Figure 2. RL and CL reflect the recommended minimum resistance and
maximum capacitance required for the internal op-amp’s stability. C
internal output amp; increasing C
beyond 100 pF can cause the internal op-amp to become unstable.
L
affects the dominant pole of the
L
DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Parameter (Note 7,10) Symbol Min Typ Max Unit
Combined Digital and On-chip Analog Filter Response Single-Speed Mode
Passband (Note 7) to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.175 - +0.01 dB
StopBand 0.5465 - - Fs
StopBand Attenuation (Note 8) 50 - - dB
Group Delay tgd - 10/Fs - s
De-emphasis Error (Note 9) Fs = 44.1 kHz - - +0.05/-0.25 dB
0
0
-
-
0.35
0.4992
Fs
Fs
Combined Digital and On-chip Analog Filter Response Double-Speed Mode
Passband (Note 7) to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.15 - +0.15 dB
StopBand 0.5770 - - Fs
StopBand Attenuation (Note 8) 55 - - dB
Group Delay tgd - 5/Fs - s
0
0
-
-
0.22
0.501
Fs
Fs
Combined Digital and On-chip Analog Filter Response Quad-Speed Mode
Passband (Note 7) to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz -0.12 - 0 dB
StopBand 0.7 - - Fs
StopBand Attenuation (Note 8) 51 - - dB
Group Delay tgd - 2.5/Fs - s
0
0
-
-
0.110
0.469
Fs
Fs
7. Filter response is guaranteed by design.
8. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs.
9. De-emphasis is available only in Single-Speed Mode.
10. Response is clock dependent and will scale with Fs. Note that the amplitude vs. frequency plots of this
data (Figures 21 to 30) have been normalized to Fs and can be de-normalized by multiplying the X-axis
scale by Fs.
DS656F3 11
AOUTx
AGND
3.3µF
V
out
R
L
C
L
Figure 1. DAC Output Test Load Figure 2. Maximum DAC Loading
100
50
75
25
2.5
51015
Safe Operating
Region
Capacitive Load -- C (pF)
L
Resistive Load -- R (k)
L
125
3
20
CS4245
12 DS656F3
CS4245
ADC ANALOG CHARACTERISTICS
Test conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V
or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; T
+85° C for Automotive; Input test signal: 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz;
Fs = 48/96/192 kHz. Synchronous mode; All connections as shown in Figure 12 on page 29.
Line-Level Inputs
Parameter Symbol Min Typ Max Unit
Dynamic Performance for VA = 4.75 V to 5.25 V
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
(Note 13) 40 kHz bandwidth unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
(Note 13) 40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise (Note 12)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
(Note 13) 40 kHz bandwidth -1 dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
(Note 13) 40 kHz bandwidth -1 dB
THD+N
Dynamic Performance for VA = 3.13 V to 3.46 V
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
(Note 13) 40 kHz bandwidth unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
(Note 13) 40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise (Note 12)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
(Note 13) 40 kHz bandwidth -1 dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
(Note 13) 40 kHz bandwidth -1 dB
THD+N
Line-Level Inputs
Parameter Symbol
Interchannel Isolation - 90 - dB
= -10° to +70° C for Commercial or -40° to
A
98
95
-
92
89
-
-
-
-
-
-
-
-
-
93
90
-
89
86
-
-
-
-
-
-
-
-
-
104
101
98
98
95
92
-95
-81
-41
-92
-92
-75
-35
-89
101
98
95
95
92
89
-92
-78
-38
-84
-89
-72
-32
-81
-89
-86
-86
-83
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Commercial Grade
UnitMin Typ Max
DS656F3 13
CS4245
DC Accuracy
Gain Error --10 %
Gain Drift - 100 - ppm/°C
Line-Level Input Characteristics
Full-scale Input Voltage 0.51*VA 0.57*VA 0.63*VA V
Input Impedance (Note 11) 6.12 6.8 7.48 k
Maximum Interchannel Input Impedance
Mismatch
-5-%
Line-Level and Microphone-Level Inputs
Commercial Grade
Parameter Symbol
DC Accuracy
Interchannel Gain Mismatch - 0.1 - dB
Programmable Gain Characteristics
Gain Step Size - 0.5 - dB
Absolute Gain Step Error - - 0.4 dB
11. Valid for the selected input pair.
pp
UnitMin Typ Max
14 DS656F3
ADC ANALOG CHARACTERISTICS
(Continued)
Microphone-Level Inputs
Parameter Symbol Min Typ Max Unit
Dynamic Performance for VA = 4.75 V to 5.25 V
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 12)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB
-1 dB
Dynamic Performance for VA = 3.13 V to 3.46 V
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
THD+N
77
74
65
62
77
74
CS4245
83
80
71
68
-
-
-
-
-80
-60
-20
-68
83
80
-74
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 12)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB
-1 dB
Interchannel Isolation - 80 - dB
THD+N
65
62
71
68
-
-
-
-
-80
-60
-20
-68
-74
-
-
-
-
-
dB
dB
dB
dB
dB
dB
DC Accuracy
Gain Error - 5 -%
Gain Drift - 300 - ppm/°C
Microphone-Level Input Characteristics
Full-scale Input Voltage 0.013*VA 0.017*VA 0.021*VA V
Input Impedance (Note 14) -60-k
pp
12. Referred to the typical line-level full-scale input voltage
13. Valid for Double- and Quad-Speed Modes only.
14. Valid when the microphone-level inputs are selected.
DS656F3 15
CS4245
ADC DIGITAL FILTER CHARACTERISTICS
Parameter (Notes 15, 17) Symbol Min Typ Max Unit
Single-Speed Mode
Passband (-0.1 dB) 0 - 0.4896 Fs
Passband Ripple - - 0.035 dB
Stopband 0.5688 - - Fs
Stopband Attenuation 70 - - dB
Total Group Delay (Fs = Output Sample Rate) t
gd
Double-Speed Mode
Passband (-0.1 dB) 0 - 0.4896 Fs
Passband Ripple - - 0.025 dB
Stopband 0.5604 - - Fs
Stopband Attenuation 69 - - dB
Total Group Delay (Fs = Output Sample Rate) t
gd
Quad-Speed Mode
Passband (-0.1 dB) 0 - 0.2604 Fs
Passband Ripple - - 0.025 dB
Stopband 0.5000 - - Fs
Stopband Attenuation 60 - - dB
Total Group Delay (Fs = Output Sample Rate) t
gd
High-Pass Filter Characteristics
Frequency Response -3.0 dB
-0.13 dB (Note 16)
Phase Deviation @ 20 Hz (Note 16) -10 -Deg
Passband Ripple -- 0dB
Filter Settling Time
-12/Fs - s
-9/Fs - s
-5/Fs - s
-120-
5
10
/Fs s
-
Hz
Hz
15. Filter response is guaranteed by design.
16. Response shown is for Fs = 48 kHz.
17. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 33 to 44) are
normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
16 DS656F3
CS4245
AUXILIARY OUTPUT ANALOG CHARACTERISTICS
Test conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V
or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; T
+85° C for Automotive; Input test signal: 1 kHz sine wave; Measurement bandwidth: 10 Hz to 20 kHz;
Fs = 48/96/192 kHz; Synchronous mode; All connections as shown in Figure 12 on page 29.
VA = 4.75 V to 5.25 V
Commercial Grade Automotive Grade
Parameter Symbol
Dynamic Performance with PGA Output Selected, Line Level Input
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 19)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
THD+N
98
95
92
89
-
-
-
-
-
-
Dynamic Performance with PGA Output Selected, Mic Level Input
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 19)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB
-1 dB
THD+N
77
74
65
62
-
-
-
-
Dynamic Performance with DAC Output Selected
Dynamic Range (Notes 18)
18 to 24-Bit A-weighted
unweighted
16-Bit A-Weighted
unweighted
Total Harmonic Distortion + Noise (Notes 18, 20)
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
THD+N
98
95
90
87
-
-
-
-
-
-
= -10° to +70° C for Commercial or -40° to
A
104
101
98
95
-80
-81
-41
-80
-75
-35
83
80
71
68
-74
-60
-20
-68
104
101
96
93
-80
-81
-41
-80
-73
-33
-74
-74
-68
-74
-74
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
96
93
90
87
75
72
63
60
96
93
88
85
104
101
98
95
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-80
-81
-41
-80
-75
-35
83
80
71
68
-74
-60
-20
-68
104
101
96
93
-80
-81
-41
-80
-73
-33
-
-
-
-
-72
-
-
-72
-
-
-
-
-
-
-66
-
-
-
-
-
-
-
-72
-
-
-72
-
-
UnitMin Typ Max Min Typ Max
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
DS656F3 17
AUXILIARY OUTPUT ANALOG CHARACTERISTICS
(Continued)
VA = 3.13 V to 3.46 V
Commercial Grade Automotive Grade
Parameter Symbol
Dynamic Performance with PGA Output Selected, Line Level Input
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 19)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
THD+N
Dynamic Performance with PGA Output Selected, Mic Level Input
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 19)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB
-1 dB
THD+N
Dynamic Performance with DAC Output Selected
Dynamic Range (Notes 18)
18 to 24-Bit A-Weighted
unweighted
16-Bit A-Weighted
unweighted
Total Harmonic Distortion + Noise (Notes 18, 20)
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
THD+N
93
90
89
86
77
74
65
62
95
92
88
85
101
98
95
92
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-80
-78
-38
-80
-72
-32
83
80
71
68
-74
-60
-20
-68
101
98
93
90
-80
-78
-38
-80
-70
-30
-
-
-
-
-74
-
-
-74
-
-
-
-
-
-
-68
-
-
-
-
-
-
-
-74
-
-
-74
-
-
91
88
87
84
75
72
63
60
93
90
86
83
CS4245
UnitMin Typ Max Min Typ Max
101
98
95
92
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-80
-78
-38
-80
-72
-32
83
80
71
68
-74
-60
-20
-68
101
98
93
90
-80
-78
-38
-80
-70
-30
-72
-72
-66
-72
-72
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
18. One-half LSB of triangular PDF dither added to data.
19. Referred to the typical Line-Level Full-Scale Input Voltage.
18 DS656F3
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