How it Works
Cirrus Logic
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CS4244
User Manual
63 pgs2.07 Mb0
Table of contents
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Cirrus Logic CS4244 User Manual

AIN4 (± )
AIN3 (± )
AIN2 (± )
AIN1 (± )
I2C Control
Data
Cont rol Port
Level Trans lat or
VL
1 .8 to 5.0 VD C
RST
INT
SDOU T1
LDO Analog Supply
2.5 V
VA
5.0 VDC
VDREG
Serial Audio Inter face
SDOU T2
AOUT 1 ( ±) AOUT 2 ( ±) AOUT 3 ( ±) AOUT 4 ( ±)
Serial Cloc k
In/Out
Master Clock In
Fr ame Sync
Clock / LRCK
SDIN 1SDIN 2
Di gital Fi lter s
Multi-bit  ADC
Inter polati on
Filter
Multi-bit 
Modul ators
Channel Volum e ,
Mute , Invert ,
Noise Gate
DAC &
Analog
Filters
Master
Volume
Cont rol
CS4244
4 In/4 Out Audio CODEC with PCM and TDM Interfaces
DAC Features
Advanced multibit delta-sigma modulator
24-bit resolution
Differential or single-ended outputs
– -109 dB differential
– -105 dB single-ended
THD+N
– -90 dB differential
– -88 dB single ended
2 Vrms full-scale output into 3-k AC load
Rail-to-rail operation
ADC Features
Advanced multibit delta-sigma modulator
24-bit resolution
Differential inputs
-105 dB dynamic range (A-weighted)
-88 dB THD+N
2 Vrms full-scale input
System Features
TDM, left justified, and I²S serial inputs and outputs
TM
I²C
host control port
Supports logic levels between 5 and 1.8 VSupports sample rates up to 96 kHz
Common Applications
Automotive audio systemsAV, Blu-RayAudio interfaces, mixing consoles, and effects
processors
®
, and DVD receivers
General Description
The CS4244 provides four multibit analog-to-digital and four multi-bit digital-to-analog - converters and is compatible with differential inputs and either differential or single-ended outputs. Digital volume control, noise gating, and muting is provided for each DAC path. A se­lectable high-pass filter is provided for the 4 ADC inputs. The CS4244 supports master and slave modes and TDM, left-justified, and I²S modes.
This product is available in a 40-pin QFN package in Automotive (-40°C to +85°C) and Commercial (0°C to +70°C) temperature grades. The CDB4244 Customer Demonstration Board is also available for device evalu­ation and implementation suggestions. See “Ordering
Information” on page 63 for complete details.
http://www.cirrus.com
Copyright  Cirrus Logic, Inc. 2012
(All Rights Reserved)
MAR ‘12
DS900F1

TABLE OF CONTENTS

1. PIN DESCRIPTIONS ............................................................................................................................ 5
1.1 I/O Pin Characteristics ..................................................................................................................... 6
2. TYPICAL CONNECTION DIAGRAM ................................................................................................... 7
3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8
RECOMMENDED OPERATING CONDITIONS .................................................................................... 8
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 8
DC ELECTRICAL CHARACTERISTICS ................................................................................................ 9
TYPICAL CURRENT CONSUMPTION ............................................................................................... 10
ANALOG INPUT CHARACTERISTICS (COMMERCIAL GRADE) ...................................................... 11
ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE GRADE) ...................................................... 12
ADC DIGITAL FILTER CHARACTERISTICS ...................................................................................... 14
ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL GRADE) .................................................. 15
ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE GRADE) .................................................. 16
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ............................. 17
DIGITAL I/O CHARACTERISTICS ...................................................................................................... 18
SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE .................................................... 19
SWITCHING SPECIFICATIONS - CONTROL PORT .......................................................................... 21
4. APPLICATIONS ................................................................................................................................... 22
4.1 Power Supply Decoupling, Grounding, and PCB Layout ............................................................... 22
4.2 Recommended Power-up & Power-down Sequence ..................................................................... 22
4.3 I²C Control Port .............................................................................................................................. 24
4.4 System Clocking ............................................................................................................................ 26
4.5 Serial Port Interface ....................................................................................................................... 28
4.6 Internal Signal Path ....................................................................................................................... 31
4.7 Reset Line ...................................................................................................................................... 42
4.8 Error Reporting and Interrupt Behavior .......................................................................................... 42
5. REGISTER QUICK REFERENCE ........................................................................................................ 45
6. REGISTER DESCRIPTIONS ................................................................................................................ 47
6.1 Device I.D. A–F (Address 01h–03h) (Read Only) ....................................................................... 47
6.2 Revision I.D. (Address 05h) (Read Only) ....................................................................................... 47
6.3 Clock & SP Select (Address 06h) .................................................................................................. 48
6.4 Sample Width Select (Address 07h) .............................................................................................. 49
6.5 Serial Port Control (Address 08h) .................................................................................................. 49
6.6 Serial Port Data Select (Address 09h) ........................................................................................... 50
6.7 ADC Control 1 (Address 0Fh) ........................................................................................................ 51
6.8 ADC Control 2 (Address 10h) ........................................................................................................ 51
6.9 DAC Control 1 (Address 12h) ........................................................................................................ 52
6.10 DAC Control 2 (Address 13h) ...................................................................................................... 52
6.11 DAC Control 3 (Address 14h) ...................................................................................................... 53
6.12 DAC Control 4 (Address 15h) ...................................................................................................... 53
6.13 Volume Mode (Address 16h) ....................................................................................................... 54
6.14 Master and DAC1-4 Volume Control (Address 17h, 18h, 19h, 1Ah, & 1Bh) ................................ 55
6.15 Interrupt Control (Address 1Eh) ................................................................................................... 55
6.16 Interrupt Mask 1 (Address 1Fh) ................................................................................................... 56
6.17 Interrupt Mask 2 (Address 20h) ................................................................................................... 57
6.18 Interrupt Notification 1 (Address 21h) (Read Only) ...................................................................... 57
6.19 Interrupt Notification 2 (Address 22h) (Read Only) ...................................................................... 58
7. ADC FILTER PLOTS ............................................................................................................................ 59
8. DAC FILTER PLOTS ............................................................................................................................ 60
9. PACKAGE DIMENSIONS ................................................................................................................... 62
10. ORDERING INFORMATION .............................................................................................................. 63
11. REVISION HISTORY .......................................................................................................................... 63
CS4244
DS900F1 2

LIST OF FIGURES

Figure 1. CS4244 Pinout ............................................................................................................................. 5
Figure 2. Typical Connection Diagram ........................................................................................................ 7
Figure 3. Test Circuit for ADC Performance Testing ................................................................................. 13
Figure 4. PSRR Test Configuration ........................................................................................................... 13
Figure 5. Equivalent Output Test Load ..................................................................................................... 16
Figure 6. TDM Serial Audio Interface Timing ............................................................................................ 20
Figure 7. PCM Serial Audio Interface Timing ............................................................................................ 20
Figure 8. I²C Control Port Timing .............................................................................................................. 21
Figure 9. System Level Initialization and Power-Up/Down Sequence ...................................................... 23
Figure 10. DAC DC Loading ..................................................................................................................... 24
Figure 11. Timing, I²C Write ...................................................................................................................... 25
Figure 12. Timing, I²C Read ...................................................................................................................... 25
Figure 13. Master Mode Clocking ............................................................................................................. 27
Figure 14. TDM System Clock Format ...................................................................................................... 28
Figure 15. 32-bit Receiver Channel Block ................................................................................................. 28
Figure 16. Serial Data Coding and Extraction Options within the TDM Streams ...................................... 29
Figure 17. Left Justified Format ................................................................................................................ 30
Figure 18. I²S Format ................................................................................................................................ 30
Figure 19. Audio Path Routing .................................................................................................................. 31
Figure 20. Conventional SDOUT (Left) vs. Sidechain SDOUT (Right) Configuration ............................... 32
Figure 21. DAC1-4 Serial Data Source Selection ..................................................................................... 33
Figure 22. Example Serial Data Source Selection .................................................................................... 34
Figure 23. ADC Path ................................................................................................................................. 35
Figure 24. Single-Ended to Differential Active Input Filter ........................................................................ 36
Figure 25. Single-Ended to Differential Active Input Filter - DC Coupled Input Signal (VA/2 Centered) ... 36
Figure 26. DAC1-4 Path ............................................................................................................................ 37
Figure 27. De-emphasis Curve ................................................................................................................. 38
Figure 28. Passive Analog Output Filter ................................................................................................... 38
Figure 29. Volume Implementation for the DAC1-4 Path .......................................................................... 39
Figure 30. Soft Ramp Behavior ................................................................................................................. 40
Figure 31. Interrupt Behavior and Example Interrupt Service Routine ...................................................... 44
Figure 32. ADC Stopband Rejection ......................................................................................................... 59
Figure 33. ADC Transition Band ............................................................................................................... 59
Figure 34. ADC Transition Band (Detail) ................................................................................................... 59
Figure 35. ADC Passband Ripple ............................................................................................................. 59
Figure 36. ADC HPF (48 kHz) ................................................................................................................... 59
Figure 37. ADC HPF (96 kHz) ................................................................................................................... 59
Figure 38. SSM DAC Stopband Rejection ................................................................................................ 60
Figure 39. SSM DAC Transition Band ...................................................................................................... 60
Figure 40. SSM DAC Transition Band (Detail) .......................................................................................... 60
Figure 41. SSM DAC Passband Ripple .................................................................................................... 60
Figure 42. DSM DAC Stopband Rejection ................................................................................................ 61
Figure 43. DSM DAC Transition Band ...................................................................................................... 61
Figure 44. DSM DAC Transition Band (Detail) .......................................................................................... 61
Figure 45. DSM DAC Passband Ripple ............................................................................................
Figure 46. Package Drawing ..................................................................................................................... 62
CS4244
........ 61
DS900F1 3

LIST OF TABLES

Table 1. Speed Modes .............................................................................................................................. 26
Table 2. Common Clock Frequencies ....................................................................................................... 26
Table 3. Master Mode Left Justified and I²S Clock Ratios ........................................................................ 27
Table 4. Slave Mode Left Justified and I²S Clock Ratios .......................................................................... 27
Table 5. Slave Mode TDM Clock Ratios ................................................................................................... 27
Table 6. Soft Ramp Rates ......................................................................................................................... 41
Table 7. Noise Gate Bit Depth Settings .................................................................................................... 41
Table 8. Error Reporting and Interrupt Behavior Details ........................................................................... 42
CS4244
DS900F1 4

1. PIN DESCRIPTIONS

AD0
AD2/SDOUT2
TST O1
VA
AIN3+
AIN4-
AIN3-
AIN2+
AIN2-
AIN1-
AIN1+
FILT+
SDA
MCLK
SDOUT 1
VL
GND
SDIN1
SDIN2
12
11
13
14
15
16
17
18
19
20
29
30
28
27
26
25
24
23
22
21
394038
37
36
35
34
33
32
31
2
1
3
4
5
6
7
8
9
10
AOUT1+
SCLK
VDREG
AOUT2+
AOUT2-
AOUT3+
AOUT3-
AOUT4-
AOUT4+
VBIAS
VREF
VQ
GND
TST O2
AOUT1-
SCL
FS/LRCK
AD1
INT
RST
AIN4+
Top-Down
(Though Package)
View
CS4244
Figure 1. CS4244 Pinout
Pin Name Pin # Pin Description
SDA 1 Serial Control Data (Input/Output) - Bi-directional data I/O for the I²C control port. SDINx 2,3 Serial Data Input (Input) - Input channels serial audio data.
FS/LRCK 4
MCLK 5 Master Clock (Input) -Clock source for the internal logic, processing, and modulators. SCLK 6 Serial Clock (Input/Output) -Serial Clock for the serial data port.
SDOUT1 7
VL 8 Interface Power (Input) - Positive power for the digital interface level shifters.
GND 9,21
VDREG 10 Digital Power (Output) - Internally generated positive power supply for digital section.
AINx+
AINx-
FILT+ 19 Positive Voltage Reference (Output) - Positive reference voltage for the internal ADCs.
DS900F1 5
11,13,15,
12,14,16,
Frame Synchronization Clock/Left/Right Clock (Input/Output) - Determines which channel or
frame is currently active on the serial audio data line.
Serial Data Output 1 (Output) - ADC data output into a multi-slot TDM stream or AIN1 and AIN2
ADC data output in Left Justified and I²S modes.
Ground (Input) - Ground reference for the I/O and digital, analog sections.
Positive Analog Input (Input) - Positive input signals to the internal analog to digital converters. The
full scale analog input level is specified in the Analog Input Characteristics tables on pages 11 and
17
12.
Negative Analog Input (Input) - Negative input signals to the internal analog to digital converters.
The full scale analog input level is specified in the Analog Input Characteristics tables on pages 11
18
and 12.
VA 20 Analog Power (Input) - Positive power for the analog sections. VQ 22 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VREF 23 Analog Power Reference (Input) - Return pin for the VBIAS cap. VBIAS 24 Positive Voltage Reference (Output) - Positive reference voltage for the internal DACs.
AOUTx-
AOUTx+
TSTOx 33,34 Test Outputs (Output) - Test outputs. These pins should be left unconnected.
RST
INT
AD2/SDOUT2 37
AD1 38 I²C Address Bit 1 (Input) - Sets the I²C address bit 1. AD0 39 I²C Address Bit 0 (Input) - Sets the I²C address bit 0. SCL 40 Serial Control Port Clock (Input) - Serial clock for the I²C control port.
GND -
25,27,29,
26,28,30,
Negative Analog Output (Output) - Negative output signals from the internal digital to analog con-
verters. The full scale analog output level is specified in the
31
on pages 15 and 16
Positive Analog Output (Output) - Positive output signals from the internal digital to analog convert- ers. The full scale analog output level is specified in the Analog Output Characteristics tables on
32
pages 15 and 16
35 Reset (Input) - Applies reset to the internal circuitry when pulled low. 36 Interrupt (Output) - Sent to DSP to indicate an interrupt condition has occurred.
I²C Address Bit 2/Serial Data Output 2 (Input/Output) - Sets the I²C address bit 2 at reset. Func-
tions as Serial Data Out 2 for AIN3 and AIN4 ADC data output in Left Justified and I²S modes. High impedance in TDM mode. See Section 4.3 I²C Control Port for more details concerning this mode of operation.
Thermal Pad - The thermal pad on the bottom of the device should be connected to the ground plane via an array of vias.
.
.
Analog Output Characteristics tables
CS4244

1.1 I/O Pin Characteristics

Input and output levels and associated power supply voltage are shown in the table below. Logic levels should not exceed the corresponding power supply voltage.
Power Supply Pin Name I/O Driver
SCL Input - Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis
SDA Input/Output
NT Output
I
RST
VL
Notes:
1. Internal connection valid when device is in reset.
2. This pin has no internal pull-up or pull-down resistors. External pull-up or pull-down resistors should be added in accordance with Figure 2.
MCLK Input - Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis
FS/LRCK Input/Output 5.0 V CMOS Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis
SCLK Input/Output 5.0 V CMOS Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis
SDOUT1 Output 5.0 V CMOS Weak Pull-down (~500k
SDINx Input - Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis AD0,1 Input - (Note 2) 5.0 V CMOS
AD2/SDOUT2 Input/Output 5.0 V CMOS (Note 2) 5.0 V CMOS
Internal Connections
(Note 1)
CMOS/Open
Drain
CMOS/Open
Drain
Input - (Note 2) 5.0 V CMOS, with Hysteresis
Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis
(Note 2) -
Receiver
DS900F1 6

2. TYPICAL CONNECTION DIAGRAM

CS4244
AIN4-
AIN3+
AIN2-
AIN3-
VA
FILT+
AIN1+
AIN1-
AIN2+
AIN4+
SDOU T1
VL
GND
FS/LRCK
MCLK
SDIN 2
SDIN 1
SDA
VDREG
SCLK
AD2/ SDOUT 2
INT
AOUT 1-
TSTO2
AOUT 1+
TSTO1
RST
AD0
AD1
SCL
35
AOUT 3 -
AOUT 4 +
GND
VREF
VQ
VBIAS
AOUT 4 -
AOUT 2 -
AOUT 3 +
AOUT 2 +
32 31
+1.8 V to +5.0 V
0. 1uF
Pull U p or Down Based upon Desired
Address
***
0.1 uF
10 uF
Rp (x4)
40 38 37 3639
Digital Signal
Processor
1
3
2
6
4
5
7
8
VL
3334
30
28
27
26
25
22
29
23
0 .1uF 10 uF
+3 .3 V to
+5.0 V
1uF
20
24
10 uF
0 .1uF
10
9
19
21
Analog Output F ilter *
Analog Output F ilter *
Analog Output F ilter *
Analog In pu t
Filter **
11 12 1413
Analog In pu t
Filter **
Analog In pu t
Filter **
Analog In pu t
Filter **
17 1815 16
Analog Output F ilter *
10 uF
****
* See Section 4.6.4 ** See Section 4.6.2.2 *** See Section 4.3 **** See Switching Specifications - Control Port
CS4244
DS900F1 7
Figure 2. Typical Connection Diagram
CS4244

3. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

GND = 0 V; all voltages with respect to ground. (Note 3)
Parameters Symbol Min Typ Max Units
DC Power Supply
Analog Core VA
Level Translator VL 1.71 - 5.25 V
3.135
4.75
3.3 5
3.465
5.25
Temperature
Ambient Operating Temperature - Power Applied Automotive
Commercial
Junction Temperature T
T
A
J
-40 0
-40 - +150 C
-
-
+85 +70
CC
Notes: 3. Device functional operation is guaranteed within these limits. Functionality is not guaranteed or
implied outside of these limits. Operation outside of these limits may adversely affect device reliability.

ABSOLUTE MAXIMUM RATINGS

GND = 0 V; all voltages with respect to ground.
V V
Parameters Symbol Min Max Units
DC Power Supply
Analog Core VA -0.3 5.5 V
Level Translator VL -0.3 5.5 V
VDREG Current (Note 4) I
VDREG
-10A
Inputs
Input Current (Note 5) I
Analog Input Voltage (Note 6) V
Logic Level Input Voltage (Note 6) V
in
INA
IND
-±10mA
- 0.3 VA + 0.4 V
-0.3 VL + 0.4 V
Temperature
Ambient Operating Temperature - Power Applied T
Storage Temperature T
WARNING:
OPERATION BEYOND THESE LIMITS MAY RESULT IN PERMANENT DAMAGE TO THE DEVICE.
A
stg
-55 +125 °C
-65 +150 °C
Notes: 4. No external loads should be connected to the VDREG pin. Any connection of a load to this point may
result in errant operation or performance degradation in the device.
5. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up.
6. The maximum over/under voltage is limited by the input current.
DS900F1 8

DC ELECTRICAL CHARACTERISTICS

GND = 0 V; all voltages with respect to ground.
Parameters Min Typ Max Units
VDREG (Note 7)
Nominal Voltage Output Impedance
FILT+
Nominal Voltage Output Impedance DC Current Source/Sink
VQ
Nominal Voltage Output Impedance DC Current Source/Sink
Notes:
7. No external loads should be connected to the VDREG pin. Any connection of a load to this point may result in errant operation or performance degradation in the device.
CS4244
-
-
-
-
-
-
-
-
2.5
0.5
VA
23
-
0.5•VA 77
-
-
-
-
-
1
-
-
0
V
V k A
V k A
DS900F1 9
CS4244

TYPICAL CURRENT CONSUMPTION

This table represents the power consumption for individual circuit blocks within the CS4244. CS4244 is configured as shown in Figure 2 on page 7. VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC; F
DAC load is 3 k; All input signals are zero (digital zero for SDINx inputs and AC coupled to ground for AINx inputs) .
Functional Block
Reset Overhead
1
(All lines held static, RST
Power Down Overhead
2
(All lines clocks and data lines active, RST
PLL (Note 10)
3
(Current drawn resulting from PLL being active. PLL is active for 256x and 384x)
DAC Overhead
4
(Current drawn whenever any of the four DACs are powered up.)
DAC Channel (Note 8)
5
(Current drawn per each DAC powered up.)
ADC Overhead
6
(Current drawn whenever any of the four ADCs are powered up.)
ADC Group
7
(Current drawn due to an ADC “group” being powered up. See
ADC Channel
8
(Current drawn per each ADC powered up.)
line pulled low.)
line pulled high, All PDNx bits set high.)
(Note 11))
= 100 kHz; MCLK = 25.6 MHz;
S
Typical Current [mA]
(unless otherwise noted)
(Note 9), (Note 12)
VA/ VL
5 0.030 0.001
3.3 0.020 0.001 5 5 0.101
3.3 5 0.101 51 -
3.3 1 ­550 -
3.3 45 ­55 -
3.3 4 ­511 -
3.3 11 ­52 -
3.3 2 ­5 2 0.109
3.3 2 0.066
i
VA
i
VL
Notes:
8. Full-scale differential output signal.
9. Current consumption increases with increasing F
and increasing MCLK. Values are based on FS of
S
100 kHz and MCLK of 25.6 MHz. Current variance between speed modes is small.
10. PLL is activated by setting the MCLK RATE bit to either 000 (operating in 256x mode) or 001 (operating in 384kHz).
11. Internal to the CS4244, the analog to digital converters are grouped together in stereo pairs. ADC1 and ADC2 are grouped together as are ADC3 and ADC4. The ADC group current draw is the current that is drawn whenever one of these groups become active.
12. To calculate total current draw for an arbitrary amount of ADCs or DACs, the following equations apply:
Total Running Current Draw from VA Supply = Power Down Overhead + PLL (If Applicable)+ DAC Current Draw + ADC Current Draw
where
ADC Current Draw = ADC Overhead + (Number of active ADC Groups x ADC Group) + (Number of active ADC Channels x ADC Channel)
Total Running Current Draw from V
DAC Current Draw = DAC Overhead + (Number of DACs x DAC Channel)
and
L Supply = PDN Overhead + (Number of active ADC Channels x ADC Channel)
DS900F1 10
CS4244

ANALOG INPUT CHARACTERISTICS (COMMERCIAL GRADE)

Test Conditions (unless otherwise specified): Device configured as shown in Section 2. on page 7. Input sine wave: 1 kHz; VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.; T
20 kHz unless otherwise specified; Sample Rate = 48 kHz; all Power Down ADCx bits = 0.
VA, VREF = 3.3 V VA, VREF = 5.0 V
Parameter
Dynamic Range
Total Harmonic Distortion + Noise
Other Analog Characteristics
Interchannel Gain Mismatch - 0.2 - - 0.2 - dB Gain Drift - ±100 - - ±100 ­Offset Error (Note 13)
Interchannel Isolation - 90 - - 90 - dB Full-scale Input Voltage
(Differential Inputs) 1.58•VA 1.66•VA 1.74•VA 1.58•VA 1.66•VA 1.74•VA Vpp Input Impedance - 40 - - 40 - k Common Mode Rejection
(Differential Inputs) PSRR (Note 14) 1 kHz
High Pass Filter On High Pass Filter Off
A-weighted
unweighted
-1 dBFS
-60 dBFS
60 Hz
Min Typ Max Min Typ Max Unit
95 92
-
-
-
-
-60- -60- dB
-
-
101
98
-95
-38
0.0001
0.25
45 20
= 25 C; Measurement Bandwidth is 20 Hz to
A
-
-
-89
-32
-
-
-
-
99 96
105 102
-
-
-
-
-
-
-88
-42
0.0001
0.25
45 20
-
-
-82
-36
-
-
-
-
dB dB
dB dB
ppm/°C
% Full Scale % Full Scale
dB dB
DS900F1 11
CS4244

ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE GRADE)

Test Conditions (unless otherwise specified): Device configured as shown in Section 2. on page 7. Input sine wave: 1 kHz; VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.; T
20 Hz to 20 kHz unless otherwise specified; Sample Rate = 48 kHz; all Power Down ADCx bits = 0.
VA, VREF = 3.3 V VA, VREF = 5.0 V
Parameter
Dynamic Range
Total Harmonic Distortion + Noise
Other Analog Characteristics
Interchannel Gain Mismatch - 0.2 - - 0.2 - dB Gain Drift - ±100 - - ±100 ­Offset Error (Note 13)
Interchannel Isolation - 90 - - 90 - dB Full-scale Input Voltage
(Differential Inputs) 1.58•VA 1.66•VA 1.74•VA 1.58•VA 1.66•VA 1.74•VA Vpp Input Impedance - 40 - - 40 - k Common Mode Rejection
(Differential Inputs) PSRR (Note 14) 1 kHz
High Pass Filter On High Pass Filter Off
A-weighted
unweighted
-1 dBFS
-60 dBFS
60 Hz
Min Typ Max Min Typ Max Unit
93 90
-
-
-
-
-60- -60- dB
-
-
101
98
-95
-38
0.0001
0.25
45 20
-87
-30
= -40 to +85 C; Measurement Bandwidth is
A
-
-
-
-
-
-
97 94
105 102
-
-
-
-
-
-
-88
-42
0.0001
0.25
45 20
-
-
-80
-34
-
-
-
-
dB dB
dB dB
ppm/°C
% Full Scale % Full Scale
dB dB
Notes:
13. AINx+ connected to AINx-.
14. Valid with the recommended capacitor values on FILT+ and VQ. See Figure 4 for test configuration.
DS900F1 12
CS4244
100 k
4.7 uF
100 k
100 k
470 pF
634
90 .9
Analog Signal +
+
-
100 k
4.7 uF
100 k
100 k
470 pF
634
90 .9
Analog S ignal -
+
-
VA
VA
2700 pF
CS4244 AINx +
CS4244 AINx -
Operational
Amplifier
OUT
GND
Power DAC
Analog
Out
GND
PWR
DUT
+Vcc
+Vcc
+
-
OUT
Test Equipment
Analog Generator Analyzer
-Vcc
Digital
Out
+
-
+
-
+
-
Figure 3. Test Circuit for ADC Performance Testing
Figure 4. PSRR Test Configuration
DS900F1 13
CS4244

ADC DIGITAL FILTER CHARACTERISTICS

Test Conditions (unless otherwise specified): Device configured as shown in Section 2. on page 7. Input sine wave: 1 kHz; VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.; Measurement Bandwidth is 20 Hz to 20 kHz unless otherwise specified. See filter plots in Section 7. on page 59.
Parameter (Note 15) Min Typ Max Unit
Passband (Frequency Response) to -0.1 dB corner 0 - 0.4535 Fs
Passband Ripple -0.09 - 0.17 dB
Stopband 0.6 - - Fs
Stopband Attenuation 70 - - dB
Single-Speed Mode
ADC Group Delay (Note 16) - 9.5/Fs - s
High-Pass Filter Characteristics (48 kHz Fs)
Frequency Response -3.0 dB
-0.13 dB
Phase Deviation @ 20 Hz - 10 - Deg
Passband Ripple -0.09 - 0.17 dB
Filter Settling Time (Note 17) -
Double-Speed Mode
ADC Group Delay (Note 16) - 9.5/Fs - s
High-Pass Filter Characteristics (96 kHz Fs)
Frequency Response -3.0 dB
-0.13 dB
Phase Deviation @ 20 Hz - 10 - Deg
Passband Ripple -0.15 - 0.17 dB
Filter Settling Time (Note 17)
-
-
-
-
-
2
11
25000/Fs
4
22
25000/Fs
-
-
0s
-
-
0s
Hz Hz
Hz Hz
Note:
15. Response is clock-dependent and will scale with Fs.
16. The ADC group delay is measured from the time the analog inputs are sampled on the AINx pins to the FS/LRCK transition (rising or falling) after the last bit of that (group of) sample(s) has been transmitted on SDOUTx.
17. The amount of time from input of half-full-scale step function until the filter output settles to 0.1% of full scale.
DS900F1 14
CS4244

ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL GRADE)

Test Conditions (unless otherwise specified). Device configured as shown in Section 2. on page 7. VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.; T
surement Bandwidth is 20 Hz to 20 kHz; Specifications apply to all channels unless otherwise indicated; all Power
Down DACx bits = 0. See (Note 19) on page 16.
= 25 C; Full-scale 1 kHz input sine wave; Sample Rate = 48 kHz; Mea-
A
VA, VREF= 3.3 V
(Differential/Single-ended)
Parameter Min Typ Max Min Typ Max Unit
Dynamic Performance
Dynamic Range 18 to 24-Bit A-weighted
unweighted
16-Bit A-weighted
unweighted
Total Harmonic Distortion + Noise - -90/-88 -84/-82 - -90/-88 -84/-82 dB
Full-scale Output Voltage
Interchannel Isolation (1 kHz) - 100 - - 100 - dB
Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB
Gain Drift - ±100 - - ±100 - ppm/°C
AC-Load Resistance (R
Load Capacitance (C
Parallel DC-Load Resistance(Note 20) 10 - - 10 - - k
Output Impedance - 100 - - 100 -
PSRR (Note 21) 1 kHz
)(Note 19) 3- -3- -k
L
)(Note 19) - - 100 - - 100 pF
L
60 Hz
100/96
97/93
89 86
1.48•VA/
0.74•VA
-
-
106/102
103/99
95 92
1.56•VA/
0.78•VA
60 60
-
-
-
-
1.64•VA/
0.82•VA
-
-
VA, VREF= 5.0 V
(Differential/Single-ended)
103/99 100/96
89 86
1.48•VA/
0.74•VA
-
-
109/105 106/102
95 92
1.56•VA/
0.78•VA
60 60
1.64•VA/
0.82•VA
-
-
-
-
-
-
dB dB dB dB
Vpp
dB dB
DS900F1 15
CS4244
AOUTx
GND
22 µF
V
OUT
R
L
C
L

ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE GRADE)

Test Conditions (unless otherwise specified): Device configured as shown in Section 2. on page 7. VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.; T
Measurement Bandwidth is 20 Hz to 20 kHz; Specifications apply to all channels unless otherwise indicated; all
Power Down DACx bits = 0. See (Note 19).
= -40 to +85 C; Full-scale 1 kHz input sine wave; Sample Rate = 48 kHz;
A
VA, VREF= 3.3 V
(Differential/Single-ended)
VA, VREF= 5.0 V
(Differential/Single-ended)
Parameter Min Typ Max Min Typ Max Unit
Dynamic Performance
Dynamic Range 18 to 24-Bit A-weighted
unweighted
16-Bit A-weighted
unweighted
98/94 95/91
87 84
106/102
103/99
95 92
-
-
-
-
101/97
98/94
87 84
109/105 106/102
95 92
-
-
-
-
dB dB dB dB
Total Harmonic Distortion + Noise - -90/-88 -82/-80 - -90/-88 -82/-80 dB
Full-scale Output Voltage
1.48•VA/
0.74•VA
1.56•VA/
0.78•VA
1.64•VA/
0.82•VA
1.48•VA/
0.74•VA
1.56•VA/
0.78•VA
1.64•VA/
0.82•VA
Vpp
Interchannel Isolation (1 kHz) - 100 - - 100 - dB
Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB
Gain Drift - ±100 - - ±100 - ppm/°C
AC-Load Resistance (R
Load Capacitance (C
)(Note 19) 3- -3--k
L
)(Note 19) - - 100 - - 100 pF
L
Parallel DC-Load Resistance(Note 20) 10 - - 10 - - k
Output Impedance - 100 - - 100 -
PSRR (Note 21) 1 kHz
60 Hz
-
-
60 60
-
-
-
-
60 60
-
-
dB dB
Notes:
18. One LSB of triangular PDF dither added to data.
19. Loading configuration is given in Figure 5 below.
Figure 5. Equivalent Output Test Load
20. Parallel combination of all DAC DC loads. See Section 4.2.3.
21. Valid with the recommended capacitor values on FILT+ and VQ. See Figure 4 for test configuration.
DS900F1 16
CS4244

COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

Test Conditions (unless otherwise specified): VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC. The filter charac­teristics have been normalized to the sample rate (F
plying the given characteristic by F
.
S
Parameter Min Typ Max Unit
Single-Speed Mode
Passband (Note 22) to -0.05 dB corner
Frequency Response 20 Hz to 20 kHz -0.01 - +0.12 dB StopBand 0.5465 - - F StopBand Attenuation (Note 23) 102 - - dB DAC1-4 Group Delay (Note 24) -11/Fs-s
Double-Speed Mode
Passband (Note 22) to -0.1 dB corner
Frequency Response 20 Hz to 20 kHz -0.05 - +0.2 dB StopBand 0.5770 - - F StopBand Attenuation (Note 23) 80 - - dB DAC1-4 Group Delay (Note 24) -7/Fs-s
) and can be referenced to the desired sample rate by multi-
S
to -3 dB corner
to -3 dB corner
0 0
0 0
-
-
-
-
0.4780
0.4996
0.4650
0.4982
F
S
F
S
S
F
S
F
S
S
Notes:
22. Response is clock-dependent and will scale with F
23. For Single-Speed Mode, the measurement bandwidth is 0.5465 F For Double-Speed Mode, the measurement bandwidth is 0.577 F
.
S
to 3 FS.
S
to 1.4 FS.
S
24. The DAC group delay is measured from the FS/LRCK transition (rising or falling) before the first bit of a (group of) sample(s) is transmitted on the SDINx pins to the time it appears on the AOUTx pins.
DS900F1 17
CS4244

DIGITAL I/O CHARACTERISTICS

Parameters Symbol Min Typ Max Units
High-Level Input Voltage (all input pins except
(VL=1.8V)
High-Level Input Voltage (all input pins except
(VL=2.5V, 3.3V, or 5V)
Low-Level Input Voltage (all input pins except
High-Level Input Voltage (
Low-Level Input Voltage (
High-Level Output Voltage at I
Low-Level Output Voltage at I
RST pin) V
RST pin) V
=2mA (% of VL) V
o
=2mA (% of VL) V
o
Input Leakage Current I
Input Capacitance - 8 - pF
RST)(% of VL)
RST)(% of VL)
RST)(% of VL)V
V
IH
V
IH
IL
IH
IL
OH
OL
in
75% - - V
70% - - V
--30%V
1.2 - - V
--0.3V
80% - - V
--20%V
--±10A
DS900F1 18
CS4244

SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE

VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.
Parameters Symbol Min Max Units
RST pin Low Pulse Width (Note 25) 1
MCLK Frequency
(Note 26) 7.68 25.6 MHz
MCLK Duty Cycle 45 55 % SCLK Duty Cycle 45 55 % Input Sample Rate (FS/LRCK pin) Single-Speed Mode
Double-Speed Mode SCLK Falling Edge to SDOUTx Valid (VL = 1.8 V) t SCLK Falling Edge to SDOUTx Valid (VL = 2.5 V) t SCLK Falling Edge to SDOUTx Valid (VL = 3.3 V or 5 V) t
F F
dh2
dh2
dh2
S
S
30 60
-31ns
-22ns
-17ns
TDM Slave Mode
SCLK Frequency
FS/LRCK High Time Pulse (Note 28)
FS/LRCK Rising Edge to SCLK Rising Edge t SDINx Setup Time Before SCLK Rising Edge t SDINx Hold Time After SCLK Rising Edge t
(Note 27) 256x 512x F
t
lpw
lcks
dh1
ds
1/f
SCLK
5-ns 3-ns 5-ns
PCM Slave Mode
SCLK Frequency 32x 64x F FS/LRCK Duty Cycle 45 55 % FS/LRCK Edge to SCLK Rising Edge t SDINx Setup Time Before SCLK Rising Edge t SDINx Hold Time After SCLK Rising Edge t
lcks
ds
dh1
5-ns 3-ns 5-ns
PCM Master Mode
SCLK Frequency 64x 64x F FS/LRCK Duty Cycle 45 55 % FS/LRCK Edge to SCLK Rising Edge t SDINx Setup Time Before SCLK Rising Edge t SDINx Hold Time After SCLK Rising Edge
(VL=1.8V)
SDINx Hold Time After SCLK Rising Edge
(VL=2.5V, 3.3V, or 5V)
lcks
t
dh1
t
dh1
ds
5-ns 5-ns
11 - ns
10 - ns
-ms
50
100
(n-1)/f
SCLK
(Note 29)
kHz kHz
S
ns
S
S
Notes:
25. After applying power to the
CS4244, RST should be held low until after the power supplies and MCLK
are stable.
26. MCLK must be synchronous to and scale with F
.
S
27. The SCLK frequency must remain less than or equal to the MCLK frequency. For this reason, SCLK may range from 256x to 512x only in single speed mode. In double speed mode, 256x is the only ratio supported.
28. The MSB of CH1 is always aligned with the second SCLK rising edge following FS/LRCK rising edge.
29. Where “n” is equal to the MCLK to LRCK ratio (set by the Master Clock Rate register bits), i.e. in 256x mode, n = 256, in 512x mode, n = 512, etc.
DS900F1 19
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