Challenger LT-32HLFH LCD Schematic

Page 1
COLOR TFT-LCD TV SERVICE MANUAL
MODEL : LT-32HLFH
SERVICE MANUAL
Page 2
CONTENTS
Contents ------------------------------------------------------------------------- 2
Safety precautions ----------------------------------------------------------- 3
Servicing precautions ------------------------------------------------------- 4
Specifications ------------------------------------------------------------------ 5
Location of control ----------------------------------------------------------- 9
Trouble Shooting ------------------------------------------------------------- 12
Deassembly procedure ---------------------------------------------------- 14
Exploded Drawing ----------------------------------------------------------- 19
Wire dressing ------------------------------------------------------------------ 21
Adjustment instruction with Default Factory Data----------------- 22
Inspection instruction ------------------------------------------------------ 24
PCB Layout --------------------------------------------------------------------- 28
Schematic Diagram -----------------------------------------------------------31
Replacement part list -------------------------------------------------------- 32
Block Diagram ----------------------------------------------------------------- 40
Circuit descriptions ---------------------------------------------------------- 41
SERVICE MANUAL
Page 3
SAFETY PRECAUTIONS
!! Important Safety Notice !!
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and Replacement Parts List. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer.
Leakage Current Hot Check (See below Figure)
Plug the AC cord directly into the AC outlet. Do not use a line Isolation Transformer during this check. Connect 1.5K/10watt resistor in parallel with a 0.15uF capacitor between a known good earth ground (Water Pipe, Conduit, etc.) and the exposed metallic parts. Measure the AC voltage across the resistor using AC voltmeter with 1000 ohms/volt or more sensitivity. Reverse plug of the AC cord into the AC outlet and repeat AC voltage measurements for each exposed metallic part. Any voltage measured must not exceed 0.75 volt RMS, which is, corresponds to 0.5mA. In case any measurement is out of the limits specified, there is possibility of shock hazard and the set must be checked and repaired before it is returned to the customer.
Leakage Current Hot Check circuit
SERVICE MANUAL
Page 4
SERVICING PRECAUTIONS
CAUTION!!
Before servicing receivers covered by this service manual, read and follow the SAFETY PRECAUTIONS on page 2 of this publication.
General Servicing Precautions
1.Always unplug the receiver AC power cord from AC power source before;
Removing or reinstalling any component, circuit board module or any other receiver assembly. Disconnecting or reconnecting any receiver electrical plug or other electrical connection. Connecting a test substitute in parallel with an electrolytic capacitor in the receiver.
CAUTION!! A wrong part substitution or incorrect polarity installation of electrolytic capacitors may result in an explosion harzard.
2.Do not spray chemicals on or near this receiver or any of its assemblies.
3.Do not defect any plug/socket voltage interlocks with which receivers covered by this service manual might be equipped.
4.Always connect the test receiver ground lead to the receiver chassis ground before connecting the test receiver positive lead. Always remove the test receiver ground lead last.
5.Do not connect the test fixture ground strap to power supply heatsink in this receiver
Electrostatically Sensitive(ES) Devices
Some semiconductor(solid state) devices can be damaged easily by static electricity. Such components commonly are called Electrostatically Sensitive(ES) Device.Examples
Circuit Board Foil Repair
Excessive heat applied to the copper foil of any printed circuit board will weaken the adhesive that bonds the foil to the circuit board causing the foil th separate from or “lift-off” the board. The following guidelines and procedures should be flollowed whenever this condition is encountered.
At IC Connections
To repair a defective copper pattern at IC connections use the following procedure to install a jumper wire on the copper pattern side of the circuit board.(Use this technique only on IC connections.)
1.Carefully remove the damaged copper pattern with a sharp knife. (Remove only as much copper as absolutely necessary.)
2.Carefully scratch away the solder resist and acrylic coating(if used) from the end of the remaining coopper pattern.
3.Bend a small “U” in one end of a small guage jumper wire and carefully crimp it around the IC pin.
4.Route the jumper wire along the path of the out-away copper pattern and let it overlap the previously scraped end of the good copper pattern. Solder the overlapped area and clip off any excess jumper wire.
SERVICE MANUAL
Page 5
SPECIFICATIONS
Note: Specifications and others are subject to change without notice for improvement.
1.Scope.
This document is the specification of 32” TFT-LCD Color TV.
2.Power
1) Power requirement 150W
2) AC / DC SMPS.
Input Frequency : 50 / 60
Input Voltage: AC 100V- 240V 2.5A ~1.5A Output Voltage: DC 12V, 24V
3) Power cord Use UL listed and CSA certified detachable power cord type; SVT, 3-conductors, 18AWG For AC 120V area. Use VDE listed detachable power cord type; HO5VV-F, 3-conductors,
18AWG for AC 220 240V area.
3.Tuning system
FVS 100 Program
4.Sound output
10W+10Wrms Stereo (Max)
5.Antenna input impedance
VHF / UHF at 75ohm
6.OSD Type (On Screen Display)
Windows type (Center)
7.External in/output
HDMI INPUT, PC ANALOG INPUT, PC AUDIO INPUT, HEADPHONE OUTPUT, SVC port S-VIDEO AUDIO INPUT, S- VIDEO INPUT, COMPONEN INPUT, COAXIAL OUT, SCART 1(FULL), SCART 2(HALF), TUNER
8. Function
CATV/Hyper band Auto Program Manual Program Auto Sleep Quick view ACMS(Auto channel Memory System) PSM(Picture Status memory) SSM(Sound Status memory) PIP : COMPONET, PC-ANALOG, HDMI(Main) – Tuner, SCART 1, SCART 2, S-Video(Sub)
TUNER, SCART1, SCART2, S-Video(Main) – PC ANALOG, HDMI, COMPONET(Sub) ARC(ASPECT RATIO CONTROL)
SERVICE MANUAL
Page 6
9.Receiving RF TV system
NO
Model System 1 PAL-B 2 PAL-G 3 PAL-I, I /I 4 PAL-D 5 PAL-K 6 SECAM-B 7 SECAM-G 8 SECAM-D 9 SECAM-K
10 SECAM-K1 11 SECAM-I (6.0) 12 NTSC-3.58 / 4.5 13 NTSC-3.58 / 5.5 14 NTSC-3.58 / 6.0 15 NTSC-3.58 / 6.5 16 NTSC-3.58 / 4.5(5.0) 17 NTSC-4.43 / 5.5 18 NTSC-4.43 / 6.0 19 NTSC-4.43 / 6.5 20 PAL 5.5 / 60Hz 21 PAL 6.0 / 60Hz 22 PAL 6.5 / 60Hz 23 SECAM 5.5 / 60Hz 24 SECAM 6.0 / 60Hz 25 SECAM 6.5 / 60Hz 26 SECAM L / L'
TOTAL SYSTEM 18
SPECIFICATIONS
LT-32HLFH / /
○/ / ○/ / ○/ / ○/ / ○/ / ○/ / ○/ / ○/ / ○/ / ○/ / ○/ /
X// X// X// X// X// X// X//
X// ○/ / ○/ / ○/ / ○/ / ○/ / ○/ / ○/ /
//
SERVICE MANUAL
Page 7
SPECIFICATIONS
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10. PC Mode Scan Frequency & Timing
1) Scan Freq: H: 3156 kHz / V: 56~75㎐
2) Preset Timing Chart
Note!! :
If the set is cold, there may be a small “flicker” when the set is switched on. This is
Normal, there is nothing wrong with the set.
If possible, use the XGA 1024 x 768@60HZ video mode to obtain the best image quality
for your LCD monitor. If used under the other resolutions, some scaled or processed
pictures may appear on the screen.
Some dot defects may appear on the screen, like Red, Green or Blue spot. However, this
will have no impact or effect on the monitor performance.
SERVICE MANUAL
Page 8
SPECIFICATIONS
11. TFT – LCD Panel Character
Description
LTA320W2-L03 is a color active matrix TFT(Thin Film Transistor) liquid crystal display(LCD) that uses amorphous silicon TFTs as a switching devices. This model is composed of a TFT LCD panel, a driver circuit and a back-light system. The resolution of a 32.0" contains 1366 X 768 pixels and can display up to 16.7 million colors with wide viewing anale of
85˚or higher in all directions.
Features
- High contrast ratio, high aperture structure
- APVA(Advanced Patterned Vertical Align) mode
- Wide verwing anale(±170°)
- High speed response
- WXGA(1366 X 768 pixels) resolution(16:9)
- Low Power consumption
- Dyrect Type 16 CCFL(Cold Cathode Fluorescent Lamp)
- DE only mode
- LVDS(Low-Voltage Differential Signal) interface.(1pixel/clock)
Applications
- Home-alone Multimedia TFT-LCD TV
- Display terminals for AV applications products
- High Definition TV(HD TV)
Feature
Size 32.0 inches
Driver element a-si TFT Active Matrix
Display area 697.6845mm(H) X 392.256mm(V)
Display colors 16.7M(true)
Number of Pixels 1366 X 768 Pixel(16:9)
Pixel arrangement RGB Vertical Stripe
Pixel Pitch 0.51075mm (H) x 0.51075mm(W)
Display mode
Surface treatment
SERVICE MANUAL
Normally Black
Haze 44%, Hard-Coating(3H)
Page 9
LOCATION OF CONTROL
LOCATION OF CONTROL
All the functions can be controlled with the remote controller. Some functions can also be adjusted with the buttons on the side panel of the set.
Remote controller
Before you use the remote controller, please install the batteries.
1. POWER
Turns the TV on from standby or off to standby mode.
2. MUTE
Turns the sound on and off.
3. NUMBER buttons
Selects programme numbers.
4. TV/AV
Selects TV, RADIO(Only when the set is Radio On.), COMPONENT, PC ANALOG, HDMI mode. Clears the menu from the screen.
SCART1,SCART2
, S-VIDEO,
5. MENU
Displays a main menu.
6. LIST
Displays the programme list menu.
7. I/II
Selects the language during dual language broadcast. Selects the sound output.
8. SLEEP
Sets the sleep timer.
9. PÏP
Returns to the previously viewed programme.
10. PRx/PRy (Programme Up/Down)
Selects next programme or a menu item.
11. OK
Accepts your selection or displays the current mode.
12. VOLÏ/VOLq (Volume Up/Down)
Adjusts the sound level.
13. TV/PC
Selects TV or PC mode directly.
SERVICE MANUAL
Page 10
LOCATION OF CONTROL
LOCATION OF CONTROL
14. PICTURE( )
Recalls your preferred picture setting
15. SOUND( )
Recalls your preferred sound setting
16. ARC( )
You can watch TV in various picture formats;
16:9, 14:9, 4:3, 16:9 Zoom, 14:9 Zoom, 4:3 Zoom.
Repeatedly press the ARC button to select your desired picture format.
Note. 16:9 and 4:3 in PC mode are available.
Auto,
17. TELETEXT buttons
These buttons are used for Teletext. For further details, see the ‘Teletext’ section.
18. INPUT( )
Selects the AV source of sub picture in PIP mode.
19. PIP( )
Displays a PIP(Picture In Picture) screen.
20. POSITION( )
Selects a position of PIP screen.
21. SWAP( )
Switches a main picture to sub picture in PIP mode.
22. MODE( )
Selects a PIP screen mode. – 16:1, 9:1 and 3:1 mode.
23. PIP PRx/PIP PRy
Selects a programme when RF signal is displayed in PIP mode.
24. Ïq
Adjusts menu settings.
SERVICE MANUAL
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1-3. Controller of Panel
< SIDE VIEW>
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󰼿 󰼿 󰼿
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󰼿 󰼿 󰼿 󰼿
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6
7
SERVICE MANUAL
LOCATION OF CONTROL
1.ON/OFF:
Switches TV set on or off.
2.MENU:
Display a menu.
1
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3.+ PR - ( Programme Up/Down):
Selects a programme or a menu item.
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2
󰼿
4.+ VOL -( Volume Up/Down):
Adjusts the volume. Adjusts menu settings.
3
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5.TV/AV:
Selects input signal source. Clears the menu from the screen.
6:POWER INDICATOR:
Illuminates red when the TV is in-
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power standby mode.
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Illuminates green when the TV is­switched power on mode. Illuminates amber when the TV is­switched power saving mode.
7.REMOTE CONTROL SENSOR:
Accepts the IR signal of remote controller.
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5
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No Raster
TROUBLE SHOOTING
Check P803 (8~12) : 24V? P804 (6~10) : 24V
N
Check Q804 (3) : 24V?
Y
Replace
Q800
N
Check Q804 (3) : 24V?
:
Y
Check
Y
P303 (25~27) : 5V?
Check IC805 (3) : 5V?
Check IC821 (3) : 5V?
Replace IC804
N
N
N
Replace LCD Panel.
Y
(If possible, replace inverter module.)
Y
Replace IC805
:
Y
Replace IC821
:
Replace Q804
Replace SMPS
N
SERVICE MANUAL
Page 13
No Sound & Picture OK
TROUBLE SHOOTING
IC601 (4,7,12,15) = 24V?
N
Check 24V Line
No Operation
IC601 (25-Mute)
Y
<
0.7V?
(L:Mute/ H:On)
IC101 (123/124 L/R) Q104/105 (E) Sound Wave ?
Replace IC101
N
N
ZD601 (C)
Y
< 1V?
Replace ZD601
N
IC202 (10)
Y
= 0V?
Replace IC202
N
No LED
Y
Resistance : 0 ? IC804 (4) <-> GND
Y
Replace IC804 / D850
LED blinking
Y
Check All SCL/SDA TTL Level ?
N
Replace Non-Operation IC.
Y
IC01 (69~75) Scaler Communic ation Lines) TTL Level ?
N
Replace IC01
SERVICE MANUAL
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DEASSEMBLY PROCEDURE
1. Disassembly procedure
1).Back cover
Removal of Backcover
Remove 4 screws
Remove 16crews
SERVICE MANUAL
Page 15
DEASSEMBLY PROCEDURE
2).Metal plate & Rear chassis
Slide away the metal plate
Removal of rear metal chassis...
Remove 5 screws
Remove 2 screws
SERVICE MANUAL
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DEASSEMBLY PROCEDURE
3).Metal plate & Rear chassis
Remove Main PCB 10 screws
Removal of Main PCB
Remove 6 connector
SERVICE MANUAL
Page 17
4).LCD Panel chassis
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SERVICE MANUAL
DEASSEMBLY PROCEDURE
Remove 22 screws, then take LCD-BRKT
Removal of LCD Module take LCD-BRKT
Removal of LCD Module
Page 18
5).LCD Module
DEASSEMBLY PROCEDURE
Remove 8 screws, then take LCD-BRKT
Front mask remains after removing LCD Module
SERVICE MANUAL
Page 19
,
MECHANICAL EXPLODED VIEW
NO PART NO DESCRI P T I ON MAT E RKAL COL OR F INISH Q'T Y
1 - DECO F RONT PM M A BLACK 1 2 610-006A SPEAKER
400-021C FRONT COVER PC+ABSSILVER,BLACK1
3 4 408-002D LENS S E NS OR PC TRA NS P A RE NCE 1 5IR PCB--1
AYCOLT40A01A
6CONTROL PCB--1 7 404-004B BLOCK KNOB ABS SILIVER 1 8 450-001Z CONT ROL P LA TE AL SI LI VER 1
9 PANV320W2L01 PANEL SAMSUNG - 1 10 407-005F BRKT L,R EGI - 2 11 407-001Z LCD BRKT EGI - 1 12 620-005D SMPS - - 1 13 AYMALT52A01A MAIN PCB ASS'Y - - 1 14 407-007S,T JACK SHIELD SPTH - 1 15 407-002L REAR SHIELD EGI - 1 16 407-003F BACK COVER PC+ABS DARK GRAY 1 17 401-0032 BOTTOM BRKT EGI - 1 18 450-001Y DECO STAND PMMA BLACK 1 19 450-004F,G,H REAR PLATE PVC BLACK 1 20 402-004W STAND BOTTOM ABS SILVER 1 21 402-004C STAND FRONT ABS DARK GRAY 1 22 401-0016 STAND BRKT EGI - 1 23 402-004D STAND REAR ABS DARK GRAY 1 24 410-001Q BTB 4*12 39 25 410-001K TTB 3*8 8 26 410-001L TTB 3*10 5 27 410-003R PBTB 4*10 4 28 410-002R PP 4*12 4 29 410-001R PB 4*8 13 30 410-001N FTB 3*6 18
SCREW TAPPING
SCREW MACHI NE
10W
10
-2
SZN
25
31
31
13
31
29
24
26
23
22
21
20
25
19
18
3
25
2
1
16
17
27
27
31
28
32
15
31
14
12
31
25
11
TITLE
SET Exploded Draw ing
DRAWING NO.
MA05-005
4 5
26
10
9
25
6
7
8
MATERIAL DATA
2005. 04. 18
THIS ENGR
D. H. KIM
TREATMENT GHK
MODEL APPD SCALE SHEET
LT32H - 1 / 1
Page 20
1. Wire Dressing
Note: Using acetate
Using Copper (Conducted tape)
Using Ferrite Cpre
WIRE DRESSING
SERVICE MANUAL
Page 21
ADJUSTMENT INSTRUCTION
(
)
(L)
p
y
g
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
WITH DEFAULT FACTORY DATA
1.SVC mode data Adjustment
NOTE!! When the EEPROM has been replaced, the SVC data should be restored as the
function of individual system and specification. When the EEPROM has been replaced White Blance Checking.
[ Enter and exit SVC mode ] Note: into the SVC mode, Initialize with default data.
1) Press 5 Seconds MENU buttons on both TV set and Remote Controller at the same time to get into SVC mode.
2) Press the PR ▲▼ button several times to find SVC Data.
3) Input the corresponding SVC data referring to Table below with the VOL ◀▶, key.
4) Press TV/AV button to exit SVC mode
1-1. Factory outgoing setting & Initialize with default data (into the SVC mode)]
Main menu Change value Sub menu Change value
Model
Language Option EU 14EA
(TV White Balance)
Option 1
Audio Options
DRX
NVM Edit
Hotel Option
Reset TV-set
TV White Balance
Sub-menu
Option 1
Sub-menu
Audio Options
Sub-menu
Sub-menu Sub-menu Sub-menu Sub-menu
Settings ALL
Start
PC Yes
System BG/I/DK/L
China/Australia No
AV1 RGB Text WEST_EU
To
VPS/PDC YES
Data Service Text
ATS Dela
QURAN No
BG/I/DK + 21
FM Radio + 10
Scart Volume + 118
Surround 0
Mute if no carrier Yes
Hi
h Deviation No
STEREO Yes
Time 60
Game No
DVI Yes
DTV No
M+ 42
NICAM + 26
DUAL No
MONO No
YES
Waring: Do not change the “( )” item…
SERVICE MANUAL
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ADJUSTMENT INSTRUCTION WITH DEFAULT FACTORY DATA
2. White Blance Checking
1. Panel : SSLTA320W2-L03-10K 2. MODEL : L
6. Setting : All Start Click
9. Pattern Generator : MSPG-3420 PATTEN : Patten No. : 33 MODE : 1024*768(13)
7. PC White Balance Setting中
10. Equipment : MSPG-925FS MODE : 1024*768
3. La nguage Option : EU 14E A
8. White Balance Setting Verify
4. PC Pattern Generator 1024 x 768, 60Hz (Pattern Generator : MSPG-3420)
5. Setting : All
SERVICE MANUAL
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INSPECTION INSTRUCTION
1. Supplied Accessories
Note: Make Sure the following accessories are provided with Product.
SERVICE MANUAL
Page 24
INSPECTION INSTRUCTION
L
2. Packing condition
PACKING BOTTOM
SET FRONT
BOX FRONT
<picture 1> PACKING insert in BOX
ACCESSORY BOX
*
SET FRONT
BOX FRONT
<picture2> SET insert in BOX
PACKING TOP
SET FRONT
SET BACK
SET FRONT
<picture3> Accessory Box insert
1 POINT 1 POINT
SET/BOX FRONT
<Picture 1>Staping <Picture 2>Taping TOP of SET box with OPP TAPE
<picture4> TOP PACKING insert in BOX
2 1 3
SET/BOX FRONT
SERVICE MANUAL
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NO PART NO DESCRIP T I O N MATERKAL CO LOR Q 'T Y
1 - LCD CO LO R TV - - 1 2 321-006A POLY VINLY PE - 1 3 310- 021A ,B PACK ING B OT TOM (L, R) EP S WHITE 2 4 300-012B SET BO X PAPER - 1 5 - ACCESSORY - - 1 6 310- 022A , B PA CK I NG T OP (L,R) E P S WHITE 2 7 499-002A T APE O PP - - -
1
2
3
4
5
6
7
MATERIAL DATA
2005. 10. 26
THIS ENGR
D. H. KIM
TREATMENT GHK
MODEL APPD SCALE SHEET
LT32H - 1 / 1
TITLE
SET Packing E x ploded D rawg
DRAWING NO.
MA05-006
Page 26
PCB LAYOUT
1. CONTROL PCB
2. Tuner PCB 3. SUB PCB
SERVICE MANUAL
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Page 28
Page 29
Page 30
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REPLACEMENT PART LIST
1. Parts List (Assemble process)
LEVEL PART NO PART NAME DESCRIPTION Q,TY
300-003R 40 ACCESSORY BOX BOX, ACCESSORY 1
1 1
300-012B NO BRAND BOX, CARTON 1
310-021A 32"H-MODEL PACKING, BOTTOM "L" 1
1
310-021B 32"H-MODEL PACKING, BOTTOM "R" 1
1
310-022A 32"H-MODEL PACKING, TOP "L" 1
1
310-022B 32"H-MODEL PACKING, TOP "R" 1
1
320-001A ACCESSORY PACKING BAG, VINYL 1
1
321-006A 30 SET PACKING BAG, PACKING 1
1
404-004J H, C/KEY,SILVER BLOCK KNOB 1
1
407-001Z 32",LCD BRKT,SS SHIELD, FRONT 1
1
407-002L 32" SHIELD PCB,SS SHIELD, REAR 1
1
407-005F 32"SS FIX BRKT L/R SHIELD,SUPPORT(SS) 2
1
407-007S VCTI-32"(HD/DVB-T) SHIELD, JACK (SCART) 1
1
410-001K TTB 3*8 SCREW 6
1
410-001L TTB 3*10 SCREW 5
1
410-001N FTB 3*6 SCREW 18
1
410-001Q BTB 4*12 SCREW 49
1
410-001R PB 4*8 SCREW 10
1
410-002R PP 4*12 SCREW 4
1
490-001M 7ITS FK10-2-104-13 FORM, SHIELD 2
1
490-001R 7ITS FK 6-4-35-13 FORM, SHIELD 2
1
490-011C 71TS-FK 20-2-34-13-S FORM, SHIELD 1
1
490-011L MSF15-20-30-00K FORM, SHIELD 1
1
490-011W MK-7-03-325-11 FORM, SHIELD 1
1
490-011X MK-15-15-310-00K FORM, SHIELD 2
1
490-021C MK-15-20-90-11 FORM, SHIELD 1
1
490-021E MK-15-5-55 FORM, SHIELD 1
1
491-001A W40mm,L20mm, COPPER TAPE, CONDUCTIVE 11
1
492-001A CLIP, ZCAT1325-0530 FERRITE CORE 2
1
492-001B CLIP, ZCHT1730-0730 FERRITE CORE 1
1
492-001D CLIP, ZCAT2035-0930 FERRITE CORE 1
1
499-002A W:70mm TAPE, OPP 4000
1
499-004A W:20mm, L:30m TAPE, ACETATE 400
1 1
500-084D NO BRAND, ENG/TUR OWNERS MANUAL 1
1
501-001H WEEE LABEL, WARNING 1
1
501-003O COMMON LABEL,SERIAL 1
1
501-018G DIBOSS STICKER, LOGO 1
1
501-113E DIBOSS LABEL, ID 1
1
502-001O COMMON LABEL, BOX ID 1
1
509-009W DIBOSS LABEL, BRAND 2
SERVICE MANUAL
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REPLACEMENT PART LIST
2. Parts List (Assemble process)
LEVEL PART NO PART NAME DESCRIPTION Q,TY
510-320A NO BRAND,(PR),symbol REMOCON (WEE),L-GRAY 1
1
520-001A 1.5V, AAA SIZE BATTERY 2
1
610-006A 10W,8Ohm(CT156B03K) SPEAKER 2
1
620-005D 32",SMPS,HNE,150W AD/DC ADAPTER 1
1
621-001B VDE KKP-4819R (EU) POWER CORD 1
1
626-002C IVORY,1.8M,15P,SHORT CABLE, PC RGB 1
1
627-001A 1.8M, BK CABLE, PC-SOUND 1
1 1 AYBCLT32A01R 32H, DVBT, SCART BACK COVER ASSY 1
AYCALT43A02A 32H, HDMI,PR+,- NO/B Front body,32inch 1
1
AYCOLT40A01A VCTI N/F CONTROL CONTROL PCB ASSY 1
1
AYMALT52A01A HD READ_SCART_32(5V) MAIN PCB ASSY 1
1
AYSTLT32A01F 30", H-MODEL,REV.01 STAND ASSY 1
1
CON02P200AOU 30.1 SPK,2P 700MMH/- LEAD ASSY 1
1
CON03P200AOY 301 SPK,3P 900MM H/- LEAD ASSY 1
1
CON05P200ABH 301 LED,5P 200MM H/H LEAD ASSY 1
1 1
CON07P200AD3 VCTI-232627,7P-10P LEAD ASSY, 1000CTRL 1 CON12P200ACL 32,W2,IVT,12P,300MM LEAD ASSY 1
1
CON12P250ACX 32" SMPS 12P 850MM LEAD ASSY 1
1
CON30P125ACF 32,SS,CORE&GND,150MM LEAD ASSY(VCTi-32") 1
1 1
PANLTA320W02 32",SS,LTA320W2-L03 PANEL, LCD COLOR 1
SERVICE MANUAL
Page 34
REPLACEMENT PART LIS
T
AYMALT52A01A
GRLT51AM001B GR, SCART MANUAL
LAVEL P/N VENDOR P/N Description Q'ty Circuit No.
GRLT51AA001B GR, SCART AUTO
LAVEL P/N VENDOR P/N Description Q'ty Circuit No.
GRLT51AS001B GR, SCART SMD
LAVEL P/N VENDOR P/N Description Q'ty Circuit No.
P/N
HD READ_SCART_32(5V)
1 0JASCART001D JACK, SCART SCART/AV-6P 2 J401,J403
2 0CESS100CMTR CESSL1C100M0511AD 10U 2 C240,C241 2 0CESS220CMTR CESSL1C220M0511AD 22U/16V 2 C207,C208
3 0CHSS080DCTS 8P 8P 1 C202 3 0CHSS101DJTS CL10C101JBNC 100P 3 C203,C212,C214 3 0CHSS104DZTS CL10F104ZANC 0.1U 1 C242 3 0CHSS471DJTS CL10C471JBNC 470P 2 C209,C210 3 0DHKEKDS226S KDS226 KDS226 1 D253 3 0LHSS120EJTS INDUCTOR, CHIP 12UH/2012 3 L202,L205,L206
3 0RHSS000DJTS RC1608J000CS 0 11
3 0RHSS102DJTS RC1608J102CS 1K 2 R210,R240 3 0RHSS103DJTS RC1608J103CS 10K 1 R243 3 0RHSS273DJTS RC1608J273CS 27K 1 R242 3 0RHSS393DJTS RESISTOR, CHIP 39K 1 R219 3 0RHSS151DJTS Resistor, chip 150 ohm 3 0RHSS471DJTS RC1608J471CS 470 2 R241 3 0RHSS513DJTS RC1608J513CS 51K 1 R220 3 0RHSS750DJTS RC1608J750CS 75 3 R206,R208,R209 3 0RHSS821DJTS RC1608J821CS 820 1 R244 3 0TRKE1504STS KTA1504S Y A1504 1 Q201 3 0TRKE3875STS C3875 C3875 1 Q202
3 1DZSC5231BTS MMSZ5231BS 5.1VZ 5
Description
150
R227,R231,R269,R271,R272 R520,R521,R522,R83,R84 R85
1 R205
ZD201,ZD203,ZD207,ZD208,Z D209
GRLT51AM001A GR, HD-READY COMMON M/I
LAVEL P/N VENDOR P/N Description Q'ty Circuit No.
1 0CESH471FMBD 470UF 35V 1 0ICKE78080AD IC, KIA7808 1 0ISSY32P00BD DIP 32P
0JAHDD15S0SD HDD-15S, VERTICAL D-SUB-15P
1 1 0JAGE14060BD RCA-1406(W/R) 2열 1 0JAH19SRJ2BD HDMI-19SR-J2(DIP) JACK, HDMI 1 J201 1 0JAPK6046GBD S-VHS, PJ6046G JACK, S-VHS 1 J406 1 0XTKI143180D 14.318MHZ 1 0XTKI184320D 18.432MHZ 1 0XTKI202500D Crystal, 20.25MHZ 1
1ICIPAP5T5TD 1 1ICSY49F040D ATMEL AT49F040 1 0JAUG0624NSD COM(3*2), UJB0624N JACK, AV YPBPR 1 J402 1 WA1YH10200SD 10P, P2.0mm STRAIGHT 1 WA1YH12200SD 12P, STRAIGHT 1 WAFLG04250SD Pin wafer, 4-PIN 1 WAFML07200SD WAFER, PIN 1 WAFYH02200SD Pin wafer, 2-PIN 1 WAFYH03200SD Pin wafer, 3-PIN 1 WAFYH10200SD 10P, P2.0mm STRAIGHT 1 111-A84B MAIN PCB 1 1 420-001J TSC020018,STA515
GRLT51AA001A GR,HD-READY COMMON AUTO
LAVEL P/N VENDOR P/N Description Q'ty Circuit No.
2 0CESS010HMTR 1UF 50V
2 0CESS100HMTR 10UF 50V
2 0CESS101CMTR Capacitor, 100UF 16V
2 0CESS101EMTR 100UF 25V 2 0CESS220CMTR Capacitor, 22UF 16V 2 0CESS221AMTR 220UF 10V
AP1501A-50T5,5V,5A
470U KIA7808AP AT49F040
AUDIO-LR
14.318M
18.432M
20.25M AC1501A-5.0 AT49F040
10P 12P 4P-2.5 7-PIN 2P-SPKL 3P-SPKR 10P
HEAT SINK
1U
10U
100U
100U/25V 22U/16V 220U/10V
5 C837,C851,C650,C836,C852 1 IC800 1 IC109 1 J202 1 J407
1 X01 1 X601 1 X100 1 IC804 1 IC109
1 P804 1 P803 2 P101,P110 1 P111 1 P601 1 P602 1 P115
1 IC603
1 C618
C173,C174,C216,C219,C853
14
C239,C253,C674,C688,C81 C82,C83,C84,C86 C01,C160,C169,C170,C36
15
C501,C610,C617,C620,C654
C87,C89,C92,C841,C108 1 C839 2 C222,C227 2 C175,C190
Page 35
REPLACEMENT PART LIS
T
GRLT51AA001A GR,HD-READY COMMON AUTO
LAVEL P/N VENDOR P/N Description Q'ty Circuit No.
2 0CESS2R2HMTR Capacitor, 2.2UF 50V 2 0CESS3R3HMTR Capacitor, 3.3UF 50V
2 0CESS470CMTR Capacitor, 47UF 16V 2 0CESS471CMTR 470UF 16V
2 0CESS4R7HMTR Capacitor, 4.7UF 50V 2 0CESS684HMTR Capacitor, 0.68UF 50V 2 0CQSS104KKTR 0.1UF 100V
2 0LBSS3580RTR BEAD CORE, RADIAL 2 0LRSU221KKTR INDUCTOR
2 0LRSU220KKTR 22U/RAD,5MM RADIAL 2 0RNSS391FFTA 390 ohm 1/6W, 1% 2 1DZSSHZT33TA 33V 2 1ICFC2N700TR IC, 2N7000
0QCSS474KKTR 0.47UF 100V 0.47u
3
GRLT51AS001A GR, HD-READY COMMON SMD
LAVEL P/N VENDOR P/N Description Q'ty Circuit No.
3 0CHSS030DCTS 3PF,1608 3 0CHSS080DCTS 8P 3 0CHSS100DJTS Capacitor, chip 10PF,1608
3 0CHSS101DJTS Capacitor, chip 100PF
3 0CHSS102DKTS Capacitor, chip 1000PF 3 0CHSS103DKTS Capacitor, chip 0.01UF
3 0CHSS104DZTS Capacitor, chip 0.1UF
3 0CHSS104HZTS 0.1U, 50V, 2012 3 0CHSS105EKTS 1U, 25V, 2012
3 0CHSS152DKTS 1500PF,1608
2.2U
3.3U 47U 470U/16V
4.7U/50V
0.68U/50V
0.1U/MYL FB-RAD-2P 220U/RAD,5MM RADIAL
22U/RAD 390/RN HZT33 2N7000
3p 8P 10P
100P
1000P
0.01
0.1U
0.1u 1UF
1500p
5 C178,C179,C187,C615,C619 2 C165,C677
C121,C151,C185,C254,C514
10
C622,C671,C693,C697C844 3 C80,C802,C122 2 C106,C197 1 C823 2 C806,C817
L24,L631,L632,L633,L634 7
L807,L808 1 L198 5 L604,L605,L606,L607,L172 1 R48 1 ZD802 2 Q120,Q121 2 C633,C645
2 C694,C695 2 C215,C255 2 C702,C703
C188,C189,C211,C213,C218
15
C221,C224,C226,C229,C232
C233,C247,C248,C256,C846
C112,C113,C114,C115,C149
10
C150,C601,C602,C675,C676 4 C192,C193,C502,C51
C02,C03,C04,C05,C06
C09,C10,C104,C105,C107
C109,C11,C12,C120,C124
C128,C133,C136,C137,C138
C142,C147,C148,C152,C158
C159,C161,C162,C163,C166
101
C171,C172,C180,C181,C182
C183,C191,C186,C195,C196
C217,C236,C250,C27,C28
C29,C30,C31,C32,C33
C34,C35,C37,C38,C39
C
C631,C634,C635,C637,C639
10
C641,C642,C643,C644,C652 2 C636,C638 4 C606,C672,C692,C698
GRLT51AS001A GR, HD-READY COMMON SMD
LAVEL P/N VENDOR P/N Description Q'ty Circuit No.
3 0CHSS220DJTS Capacitor, Chip, 22PF 3 0CHSS221DJTS CAPACITOR, CHIP 3 0CHSS222DKTS Capacitor, chip 2200PF,1608 3 0CHSS224DZTS Capacitor, chip 0.22UF 3 0CHSS330DJTS Capacitor, Chip, 33PF
0CHSS331HZTS CAPACITOR, CHIP 330P, 50V, 2012 2 C640,C651
3 0CHSS331DJTS Capacitor, chip 330PF 3 0CHSS334DZTS Capacitor, chip,0.33UF,1608
3 0CHSS471DJTS Capacitor, chip 470PF
3 0CHSS472DKTS 4700PF,1608
3 0CHSS473DKTS Capacitor, chip 0.047UF
3 0CHSS474DZTS 0.47UF,1608
3 0DHKEKDS181S Diode, chip KDS181 3 0DHKEKDS226S Diode, chip KDS226 3 0ICHN28322QS HY5DU283222Q, 128Mb 3 0ICKE7027FTS IC, KIA7027 3 0ICKE7805ATS KIA7805AF 5.0V 1A 3 0ICSS6X8008S SS,K6X8008T2B,SDRAM
22P 220p 2200p
0.22U 33P
330P
0.33U
470P
4700p
0.047U
0.47u
KDS181 KDS226 HY5DU283222Q KIA7027 KIA7805AF K6X8008T2B
2 C07,C08 1 C699 2 C616,C621 2 C139,C605 2 C145,C146
2 C153,C154
C116,C117,C118,C119,C131 6
C132
C200,C201,C205,C206,C220
15
C223,C225,C228,C230,C231
C245,C246,C604,C673,C691 3 C249,C257,C259
C13,C14,C15,C16,C17
11
C18,C19,C21,C23,C24
C26
C679,C680,C681,C682,C683
11
C684,C685,C686,C689,C690
C625 2 D250,D251 5 D101,D201,D202,D203,D204 1 IC03 1 IC104 3 IC102,IC203,IC609 1 IC105
Page 36
REPLACEMENT PART LIS
T
GRLT51AS001A GR, HD-READY COMMON SMD
LAVEL P/N VENDOR P/N Description Q'ty Circuit No.
3 0ICVI4925DTS DUAL P-CHANNEL 30V MOSFET 3 0LBSS101DJTS 100 OHM, 2012
3 0LBSS601FJTS 600 OHM, 3216
3 0LHSS120EJTS 12UH, 2012
3 0LRSL10100BS INDUCTOR
3 0RHSS000DJTS Resistor, chip 0 ohm
GRLT51AS001A GR, HD-READY COMMON SMD
LAVEL P/N VENDOR P/N Description Q'ty Circuit No.
3 0RHSS000EJTS 0 OHM, 2012 J
0RHSS000FJTS 0 OHM, 3216 J
3 0RHSS100DJTS Resistor, chip 10 ohm
3 0RHSS101DJTS Resistor, chip 100 ohm
3 0RHSS102DJTS Resistor, chip 1K
3 0RHSS103DJTS Resistor, chip 10K
3 0RHSS123DJTS 12K OHM, 1608 J 3 0RHSS104DJTS Resistor, chip 100K 3 0RHSS105DJTS 1M OHM, 1608 J
3 0RHSS122DJTS Resistor, chip 1.2K 3 0RHSS151DJTS Resistor, chip 150 ohm 3 0RHSS153DJTS 15K OHM, 1608 J 3 0RHSS181DJTS 180 OHM, 1608 J
3 0RHSS220DJTS Resistor, chip 22 ohm
3 0RHSS223DJTS Resistor, chip 22K 3 0RHSS272DJTS Resistor, chip 2.7K
3 0RHSS273DJTS Resistor, chip 27K 3 0RHSS330DJTS 33 OHM, 1608 J
3 0RHSS332DJTS Resistor, chip 3.3K 3 0RYSS100FJTS 10 OHM, *8 J
3 0RYSS330FJTS RESISTOR, ARRAY CHIP
SI4925 101/2012
601/3216
12UH/2012
33UH
0
0/2012
0/3216 10
100
1K
10K
12K 100K 1M
1.2K 150 15K 180
22
22K
2.7K 27K 33
3.3K 10
33 OHM, 3216
2 IC805,IC821
L207,L208,L209L701,L702 7
L703,L502
L01,L03,L04,L05,L07
13
L08,L09,L104,L160,L23
L610,L501,L95,L603
L200,L201,L203,L204,L210
L211,L212,L213,L214,L215
16
L216,L217,L218,L220,L221
L222 1 L850
C135,R01,R06,R07,R09
R10,R108,R109,R11,R110
R118,R12,R128,R152,R16
R161,R164,R165,R166,R167
R178,R179,R180,R188,R196
R197,R198,R199,R224,R225
75
R23,R238,R239,R24,R25
R251,R30,R40,R41,R42
R501,R513,R54,R545,R548
R55,R556,R58,R59,R60
R603,R61,R626,R67,R678
R6
L15,L16,L17,L18,L19
L20,L21,L22,R159,R223
19
R160,R173,R174,R221,R222
L219,L505,L506,L507 2 R852,R853 2 R168,R93
R08,R105,R106,R107,R130
R131,R132,R133,R135,R137
R138,R139,R140,R141,R142
R143,R147,R148,R149,R150
R151,R162,R163,R17,R194
55
R195,R288,R289,R291,R292
R293,R294,R295,R296,R297
R298,R36,R561,R91,R719
R562,R563,R564,R601,R602
R604,R605,R606,R672,R673
R676,R703
R117,R254,R39,R56,R660
11
R712,R713,R717,R94,R96
R276
R190,R232,R233,R234,R235
R236,R237,R255,R256,R27
25
R278,R290,R611,R612,R674
R677,R704,R705,R706,R707
R72,R825,R847,R860,R861 1 R871
R620,R621,R659,R802,R804 6
R821 1 R02 2 R805,R809 5 R113,R114,R115,R53,R280 2 R618,R623 1 R95
R04,R05,R120,R129,R154
R155,R192,R193,R211,R212
R213,R252,R253,R32,R33
30
R34,R44,R45,R50,R51
R52,R528,R529,R65,R66
R701,R702,R80,R81,R82 1 R156 1 R204
R260,R274,R675,R803,R816 7
R818,R92 4 R70,R71,R73,R74 5 R03,R134,R247,R526,R527 2 AR26,AR27
AR01,AR02,AR03,AR13,AR14
14
AR15,AR16,AR17,AR18,AR19
AR22,AR23,AR24,AR25
Page 37
REPLACEMENT PART LIS
T
GRLT51AS001A GR, HD-READY COMMON SMD
LAVEL P/N VENDOR P/N Description Q'ty Circuit No.
3 0RHSS392DJTS Resistor, chip 3.9K 3 0RHSS393DJTS Resistor, chip 39K 3 0RHSS3R0DJTS 3 OHM, 1608 J 3 0RHSS470DJTS Resistor, chip 47 ohm 3 0RHSS471DJTS Resistor, chip 470 ohm
3 0RHSS472DJTS Resistor, chip 4.7K
3 0RHSS473DJTS Resistor, chip 47K
3 0RHSS474DJTS Resistor, chip 470K
3 0RHSS512DJTS RESISTOR, CHIP
3 0RHSS622DJTS RESISTOR, CHIP
3 0RHSS750DJTS Resistor, chip 75 ohm
3 0RHSS821DJTS Resistor, chip 820 ohm
3 0RYSS220FJTS 22 OHM, *8 J
3 0TRKE1504STS Transistor, chip A1504
3 0TRKE3875STS Transistor, chip
3 1DHSTS1545GS D2PAK, 45V 15A
3.9K 39K 3 47 470
4.7K
47K
470K
5.1K
6.2K
75
820
22
A1504
C3875
STPS1545G
2 R124,R125 2 R619,R622 1 R43 2 R257,R258 3 R104,R275,R519
R119,R121,R122,R123,R177
R181,R182,R183,R184,R207
R246,R26,R28,R530,R867
22
R709,R710,R720,R819,R859
R865,R866
R103,R126,R245,R551,R552
12
R817,R826,R872,R873,R874
R875,R876 2 R202,R203
R191,R200,R201,R217,R218
11
R266,R267,R282,R283,R284
R285 2 R624,R625
R214,R215,R216,R259,R279
15
R281,R286,R287,R502,R503
R560,R567,R714,R715,R716 1 R277
AR07,AR08,AR101,AR102,AR1 7
1
AR12,AR21 3 Q203,Q104,Q105
Q01,Q106,Q11,Q12,Q13
15
Q204,Q205,Q210,Q601,Q602
Q632,Q800,Q802,Q803,Q814 1 D850
GRLT51AS001A GR, HD-READY COMMON SMD
LAVEL P/N VENDOR P/N Description Q'ty Circuit No.
D700,D701,ZD191,ZD192,ZD20
2
ZD204,ZD205,ZD206,ZD210,Z
D211
ZD212,ZD213,ZD214,ZD215,Z
3 1DZSC5231BTS 5.1V, MMSZ5231BS-7
3 1ICMI49X3RF2 IC,V/S DECODER 3 1ICMS5151ABS MST5151A 3 1ICPH74F08TS IC, N74F08D 3 1ICPH8574ATS IC, I/O EXPANDER
111-A84B 3 1ICR03V512BS IC, INPUT RGBHV S/W 3 1ICSE24C16TS IC, 24C16 3 1ICST24C02WS 24C02W 3 1ICST3232CDS ST3232-RS232C 3 1ICST80PF55S STB80PF55 3 1ICSTLD18TTS LD1117S18TR 3 1ICSTLD25TTS LD1117S25TR 3 1ICSTLD33TTS LD1117S33TR 3 1ICSTTS482TS TS482IST, MINI08 3 WAFYH30125AS WAFER, PIN
0RHSS620DJTS 6.2 OHM, 3216 6.2
3
0RHSS200DJTS 20 OHM, 3216 20
3
0RHSS362DJTS 3.6K OHM, 1608J 3.6K
3
1DHPR0514MOS 514M 514M
3
0ICKE7808ATS KIA7808AF KIA7808AF
3
1ICMIMAP46DS MAP46XX MAP46XX
3
1ICST51500BS STA515 STA515
3
MAIN PCB MAIN PCB
5.1VZ
VCT49XX MST5151A 74F08 PCF8574TS
PI3V512 24C16 24C02W ST3232CD STB80PF55 LD1117S-18TR LD1117S-25TR LD1117S-33TR TS482-MINISO8 30PLVDS
D216
30
ZD217,ZD218,ZD219,ZD220,Z D221 ZD222,ZD223,ZD224,ZD225,Z D601 ZD702,ZD703,ZD704,ZD705,Z D706
1 IC101 1 IC01 1 IC702 1 IC202
1 IC501 1 IC103 2 IC201,IC701 1 IC106 1 Q804 2 IC832,IC10
IC09 5 IC107,IC108,IC606,IC06,IC08 1 IC602 1 P303 4 R613,R615,R631,R632 2 R614,R616 1 R97 2 D261,D262 1 IC608 1 IC610 1 IC603
GRLT51AM001F GR, HD-READY TUNER M/I HD-READY TUNER(PAL)
LAVEL P/N VENDOR P/N Description Q'ty Circuit No.
1 0TULGG083DBD TAEM-G083D Tuner 1 1 111-A90A HDMI ANALOG TUNER PCB, TUNER 1
1 1SFEPX6966MD X6966M SAW FILTER 1 SF101 1 WAFYH10200AD WAFER, PIN Pin wafer, 10-Pin 1 P115
Page 38
REPLACEMENT PART LIS
T
GRLT41AM001H GR, LL' MANUAL
LAVEL P/N VENDOR P/N Description Q'ty Circuit No.
1TPMU40R9MTD MKTGA40M9AAHP00A03
GRLT41DS001G GR, LL' SMD
LAVEL P/N VENDOR P/N Description Q'ty Circuit No.
3 0TRKE3875STS KTC3875S 3 0RHSS472DJTS Resistor, chip 4.7K
GRLT51AS001G HD-READY 32 PANEL S/I (5V)
LAVEL P/N VENDOR P/N Description Q'ty Circuit No.
3 0RHSS000EJTS 0 OHM, 2012 J
GRLT10AM002A GR, HEAT SINK M/I AP1501A-50T5,25*16
LAVEL P/N VENDOR P/N Description Q'ty Circuit No.
1 410-001J SCREW 1 1 420-001F HEAT SINK 1 1 498-001A Silicon Grease 0.15
GRLT51AM001D GR, HP+RJ45 M/I HD-READY,HP+RJ45(PCB, SUB)
LAVEL P/N VENDOR P/N Description Q'ty Circuit No.
WAFET08250SD WAFER, PIN
1 1 0JAKKST215BD ST-215 Jack, PC-AUDIO,HP 2 J601,J602 1 111-A92A HD-READY,HP+RJ45 PCB PCB, SUB 1 1 0JAAR823PDBD JACK, RJ-45 RJ-45, 8PIN 1 J405
GRLT51AM001J GR, ONLY 32" MANUAL HD-READY ONLY 32"
LAVEL P/N VENDOR P/N Description Q'ty Circuit No.
1 WA1YH12250AD 12P, P2.5mm ANGLE
GRLT51AS001J GR, ONLY 32" SMD HD-READY ONLY 32"
LAVEL P/N VENDOR P/N Description Q'ty Circuit No.
3 0ICVI4925DTS DUAL P-CHANNEL 30V MOSFET 3 0TRKE3875STS C3875 C3875 1 Q820,Q821
VCTI 15/17 동일I
40.9M
V2327 신규
C3875
4.7K
0/2012
8P 2 P203,P204
12P
SI4925
1 T101
1 Q106 1 R177
1 R822
1 P813
1 IC806
Page 39
1. Block Diagram
32 Block Diagram
(INVERTER)
BLOCK DIAGRAM
DC-IN
POWER
26/32
DC-IN 24V
DC-IN
Power
(Inverter/Scaler/
ADC/VCTI)
Power IIC
LCD PANEL
PANEL DRIVE LVDS
IC01
SCALER
DVI Receiver
ADC
PIP
De-Interlacer
H
P
D
C
M
-
I
R G B
AMP
SPEAKER
H/P AMP
Power IIC
I F
HEADPHONE
Power
V C T
I R G B
, H
S , V S
SOUND
Processor
D T V
L / R
Video Processor
Sound Processor
A
R
V
G
-
B
I
,
N
F
/
B
O U T
I 2
L/R
C S
IC101 VCTI
u-Com
TEXT/Caption
IF Processor
Y
A V
P
-
b
I
P
N
R
/
(
O
D
U
V
T
D )
L/R
Y C
SC2 L/R PC L/R
ITU-6 5 6
Power IIC
Y P b P
r
( D
- T V )
HDMI-RGB PC-RGB RGB,FB
HDMI D-SUB SCART1 SCART2S-VIDEO TUNER
YC
YPbPr(DVD) YPbPr(D-TV)
YPbPr(DVD)
YPbPr(D-TV)
YPbPr(DVD)
YPbPr(D-TV)
PAL(EU)
NTSC/MULTI
AV-IN/OUT
AV-IN/OUT
AV-IN/OUT
IF
SERVICE MANUAL
Page 40
CIRCUIT DESCRIPTIONS
General Description for 26.0” color TFT LCD TV.
The TFT LCD TV described in the followings is based on a Multi TV system, digital Control display, 26.0" diagonal. The TFT LCD TV is intended to be a finished product, Basically a display device mounted inside an enclosure which will provide the safety Requirements. With the exception of LCD Panel, the display device shall be composed entirely of solid state components. These components shall have a history of reliable service in identity applications and shall be applied in the circuits.
1. SCALER SECTION.
2. VCT 49xxi SECTION.
3. Video A/D Converter
SERVICE MANUAL
Page 41
CIRCUIT DESCRIPTIONS
1.SCALER SECTION.
Device : MST5151A
Features: LCD TV controller with PC & multimedia display functions
Input supports up to UXGA & 1080P
Supports up to SXGA panels
Integrated two-port triple-ADC/PLL
Integrated DVI/HDCP/HDMI compliant receiver YUV422 digital video input ports Dual high-quality scaling engines Dual 3-D video de-interlacers Full function PIP/POP MStarACE picture/color processing engine Embedded On-screen display controller (OSD) engine Digital audio I/O & sync processor Built-in dual-link LVDS transmitter 5 Volt tolerant inputs Low EMI and power saving features Supports PWM & GPO controls 208-pin PQFP package
Analog RGB/YPbPr Input Ports
Dual analog ports support up to 165Mhz Supports PC RGB input up to UXGA@60Hz Supports HDTV RGB/YPbPr/YCbCr up to 1080P On-chip high-performance PLLs Supports Composite Sync and SOG (Sync-on-Green) separator Automatic color calibration
DVI/HDCP/HDMI Compliant Input Port
Operates up to 165 MHz (up to UXGA @60Hz) Single link on-chip DVI 1.0 compliant receiver High-bandwidth Digital Content Protection (HDCP) 1.1 compliant receiver
High Definition Multimedia Interface (HDMI)
1.0 compliant receiver with I2S and S/PDIF digital audio outputs Long-cable tolerant robust receiving
Video Input Port
Two 4:2:2 ITU656 8-bit digital video input ports One 4:2:2 ITU601 16-bit digital video input port Supports 16-bit YUV 4:2:2 interlaced/ progressive video input up to 1080i/720P
Auto-Configuration/Auto-Detection
Auto input signal format (SOG, Composite,Separated HSYNC, VSYNC, and DE), and input mode (all PC & TV modes) detection Auto-tuning function including phasing, positioning, offset, gain, and jitter detection
Sync Detection for H/V Sync
Dual High-Performance Scaling Engines
Fully programmable shrink/zoom capabilities Nonlinear video scaling supports various modes including Panorama
Video Processing & Conversion
Dual 3-D motion adaptive video de-interlacers with upgraded edge-oriented adaptive
algorithm for smooth low-angle edges Automatic 3:2 pull-down & 2:2 pull-down detection and recovery PIP/POP with programmable size and location, supports multi-video applications Video-over-graphic overlay MStar 2
On-Screen OSD Controller
nd Generation Advanced Color Engine
SERVICE MANUAL
Page 42
1) Description
The MST5151A is a high performance and fully integrated graphics processing IC solution for multi-function LCD monitor/TV with resolutions up to SXGA. It is configured with an integrated triple-ADC/PLL, an integrated DVI/HDCP/HDMI receiver, two video de-interlacers, two high quality scaling engines, an on-screen display controller, and a built-in output clock generator. By use of external frame buffer, PIP/POP is provided for multimedia applications. It supports de-interlaced full-screen video, video-on-graphic overlay, split screen, frame rate conversion, and aspect ratio conversion for various video sources. To further reduce system costs, the MST5151A also integrates intelligent power management control capability for green-mode requirements and spread-spectrum support for EMI management.
.
SERVICE MANUAL
Page 43
CIRCUIT DESCRIPTIONS
PIN DIAGRAM (MST5151A)
GND
AVDD_MPLL
XIN
XOUT
PWM1
PWM0
AIWS
AISCK
VDDC
SPDIFO
AISD
AIMCK
GND
AUMUTE
196
195
192
194
193
69
67
68
INT
ALE
GND
VDDP
HWRESET
GND
DVI_G+
DVI_G-
AVDD_DVI
DVI_B+
DVI_B-
GND
DVI_CK+
DVI_CK-
AVDD_DVI
REXT
AVDD_PLL
GND
DDCD_DA
DDCD_CK
GND
AVDD_ADC
HSYNC1 VYSNC1
BIN1P
BIN1M
SOGIN1
GIN1P
GIN1M
RIN1P RIN1M BIN0M
BIN0P
GIN0M
GIN0P
SOGIN0
RIN0M
RIN0P
AVDD_ADC
GND HSYNC0 VSYNC0
RMID
REFP
REFM VI_DATA[8] VI_DATA[9]
VI_DATA[10] VI_DATA[11] VI_DATA[12] VI_DATA[13] VI_DATA[14] VI_DATA[15]
AVDD_APLL
GND GPO[5] GPO[4]
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
DVI_R-
DVI_R+
GND
208
207
206
205
Pin 1
5354555657
VI_CK
VI_DATA[0]
VI_DATA[1]
VI_DATA[2]
204
202
200
203
58
VI_DATA[3]
VI_DATA[4]
198
201
199
197
59
61
636566
60
62
64
GND
VDDC
VCTRL
VI_DATA[7]
VI_DATA[5]
VI_DATA[6]
AUWS
AUSCK
191
190
70
717274
RDZ
WRZ
AUSD
LVB0M
VDDC
GND
LVB0P
186
75
DBUS[3]
185
XXXXX
76
GPO[3]
VDDP
GND
184
182
183
XXXXXXXXXXX
777980
78
VDDC
GPO[2]
GPO[1]
MST5151A
LVB1M
LVB1P
LVB2M
LVB2P
LVBCKM
LVBCKP
LVB3M
LVB3P
VDDC
GND
LVA0M
LVA0P
LVA1M
LVA1P
LVA2M
LVA2P
LVACKM
LVACKP
GND
VDDP
LVA3M
LVA3P
GND
BYPASS
GND
181
179
177
175
173
170
168
180
178
176
174
172
171
82
84
86
81
83
GND
DQS[3]
MDATA[31]
MDATA[30]
88
85
878990
GND
VDDM
MDATA[29]
MDATA[28]
MDATA[27]
MDATA[26]
MDATA[25]
169
91
92
MDATA[24]
MDATA[23]
166
167
165
93
95
9496979899
MDATA[22]
MDATA[21]
MDATA[20]
MDATA[19]
164
163
162
161
159
158
157
160
156
VDDC
155
GND
154
VDDM
153
DQS[0]
152
MDATA[0]
151
MDATA[1]
150
MDATA[2]
149
MDATA[3]
148
MDATA[4]
147
MDATA[5]
146
MDATA[6]
145
MDATA[7]
144
MDATA[8]
143
MDATA[9]
142
MDATA[10]
141
MDATA[11]
140
GND
139
VDDM
138
MDATA[12]
137
MDATA[13]
136
MDATA[14]
135
MDATA[15]
134
DQS[1]
133
DQM[0]
132
GND
131
VDDC
130
MADR[11]
129
MADR[10]
128
MADR[9]
127
MADR[8]
126
GND
125
VDDM
124
MADR[7]
123
MADR[6]
122
MADR[5]
121
MADR[4]
120
MADR[3]
119
MADR[2]
118
MADR[1]
117
MADR[0]
116
WEZ
115
CASZ
114
GND
113
VDDM
112
RASZ
111
BADR[0]
110
BADR[1]
109
AVDD_PLL2
108
GND
107
MCLK
106
MCLKZ
105
MCLKE
100
102
103
104
101
GND
VDDM
MVREF
DQS[2]
DQM[1]
MDATA[18]
MDATA[17]
MDATA[16]
AUMCK
188
189
187
73
DBUS[0]
DBUS[1]
DBUS[2]
Page 44
CIRCUIT DESCRIPTIONS
PIN DESCRIPTION
MCU Interface
Pin Name Pin Type Function Pin
HWRESET Schmitt Trigger Input
w/ 5V-tolerant DBUS[3:0] I/O w/ 5V-tolerant MCU 4-bit DDR Direct bus; 4mA driving strength 75-72 ALE I w/ 5V-tolerant MCU Bus ALE, active high 69 RDZ I w/ 5V-tolerant MCU Bus RDZ, active high 70 WRZ I w/ 5V-tolerant MCU Bus WDZ, active high 71 INT Output MCU Bus Interrupt; 4mA driving strength 68
Hardware Reset, active high 67
Analog Interface
Pin Name Pin Type Function Pin
RMID Mid-Scale Voltage Bypass 38 REFP Internal ADC Top De-coupling Pin 39 REFM Internal ADC Bottom De-coupling Pin 40 REXT Analog Input External Resister 390 ohm to AVDD_DVI 11 HSYNC0 Schmitt Trigger Input
w/ 5V-tolerant
Analog HSYNC Input from Channel 0 36
VSYNC0 Schmitt Trigger Input
w/ 5V-tolerant BIN0M Analog Input Reference Ground for Analog Blue Input from Channel 0 27 BIN0P Analog Input Analog Blue Input from Channel 0 28 GIN0M Analog Input Reference Ground for Analog Green Input from Channel 0 29 GIN0P Analog Input Analog Green Input from Channel 0 30 SOGIN0 Analog Input Sync On Green Input from Channel 0 31 RIN0M Analog Input Reference Ground for Analog Red Input from Channel 0 32 RIN0P Analog Input Analog Red Input from Channel 0 33 HSYNC1 Schmitt Trigger Input
w/ 5V-tolerant VSYNC1 Schmitt Trigger Input
w/ 5V-tolerant BIN1P Analog Input Analog Blue Input from Channel 1 20 BIN1M Analog Input Reference Ground for Analog Blue Input from Channel 1 21 SOGIN1 Analog Input Sync On Green Input from Channel 1 22 GIN1P Analog Input Analog Green Input from Channel 1 23
Analog VSYNC Input from Channel 0 37
Analog HSYNC Input from Channel 1 18
Analog VSYNC Input from Channel 1 19
Page 45
CIRCUIT DESCRIPTIONS
Pin Name Pin Type Function Pin
GIN1M Analog Input Reference Ground for Analog Green Input from Channel 1 24 RIN1P Analog Input Analog Red Input from Channel 1 25 RIN1M Analog Input Reference Ground for Analog Red Input from Channel 1 26
DVI Interface
Pin Name Pin Type Function Pin
DVI_R+ Input DVI Input Channel Red + 207 DVI_R- Input DVI Input Channel Red - 208 DVI_G+ Input DVI Input Channel Green + 2 DVI_G- Input DVI Input Channel Green - 3 DVI_B+ Input DVI Input Channel Blue + 5 DVI_B- Input DVI Input Channel Blue - 60 DVI_CK+ Input DVI Input Clock + 8 DVI_CK- Input DVI Input Clock - 9
Video Interface
Pin Name Pin Type Function Pin
VI_CK Input w/ 5V-tolerant Digital Video Input Clock 66 VI_DATA[15:0] Input w/ 5V-tolerant Digital Video Input Data[15:0] 48-41, 61-54
Digital Audio Interface
Pin Name Pin Type Function Pin
AUMCK Output Audio Master Clock Output 188 AUSD Output Audio Serial Data Output; 4mA driving strength 189 AUSCK Output Audio Serial Clock Output; 4mA driving strength 190 AUWS Output Word Select Output; 4mA driving strength 191 AUMUTE Output Audio Output Mute Control 192 SPDIFO Output S/PDIF Audio Output; 4mA driving strength 193 AIMCK Input Audio Master Clock Input 196 AISD Input Audio Serial Data Input 197 AISCK Input Audio Serial Clock Input 198 AIWS Input Word Select Input 199
Page 46
CIRCUIT DESCRIPTIONS
LVDS Interface
Pin Name Pin Type Function Pin
LVA0M Output A-Link Negative LVDS Differential Data Output 171 LVA0P Output A-Link Positive LVDS Differential Data Output 170 LVA1M Output A-Link Negative LVDS Differential Data Output 169 LVA1P Output A-Link Positive LVDS Differential Data Output 168 LVA2M Output A-Link Negative LVDS Differential Data Output 167 LVA2P Output A-Link Positive LVDS Differential Data Output 166 LVA3M Output A-Link Negative LVDS Differential Data Output 161 LVA3P Output A-Link Positive LVDS Differential Data Output 160 LVACKM Output A-Link Negative LVDS Differential Data Output 165 LVACKP Output A-Link Positive LVDS Differential Data Output 164 LVB0M Output B-Link Negative LVDS Differential Data Output 187 LVB0P Output B-Link Positive LVDS Differential Data Output 186 LVB1M Output B-Link Negative LVDS Differential Data Output 181 LVB1P Output B-Link Positive LVDS Differential Data Output 180 LVB2M Output B-Link Negative LVDS Differential Data Output 179 LVB2P Output B-Link Positive LVDS Differential Data Output 178 LVB3M Output B-Link Negative LVDS Differential Data Output 175 LVB3P Output B-Link Positive LVDS Differential Data Output 174 LVBCKM Output B-Link Negative LVDS Differential Data Output 177 LVBCKP Output B-Link Positive LVDS Differential Data Output 176
GPO Interface
Pin Name Pin Type Function Pin
PWM0 Output GPO with PWM Function; 4mA driving strength 200 PWM1 Output GPO with PWM Function; 4mA driving strength 201 GPO[1] I/O GPO / FIELD input; 4mA driving strength 78 GPO[2] I/O GPO / Digital VSYNC Input; 4mA driving strength 77 GPO[3] I/O GPO / DE Input; 4mA driving strength 76 GPO[4] I/O GPO / Secondary Video Clock Input; 4mA driving strength 52 GPO[5] I/O GPO / Digital HSYNC Input; 4mA driving strength 51
Page 47
CIRCUIT DESCRIPTIONS
DRAM Interface
Pin Name Pin Type Function Pin
MVREF Input Reference Voltage for DDR SDRAM Interface 104 MCLKE Output DRAM Memory Clock Enable 105 MCLKZ Output DRAM Memory clock Complementary /Input
(for differential clocks) MCLK Output DRAM Memory Clock 107 RASZ Output Row Address Strobe, active low 112 CASZ Output Column Address Strobe, active low 115 WEZ Output Write Enable, active low 116 DQM[1:0] Output Data Mask Byte Enable 101, 133 DQS[3:0] Output Data Strobe 81, 100, 134, 153 BADR[1:0] Output Memory Bank Address 110, 111 MADR[11:0] Output Memory Address 130-127, 124-117 MDATA[31:0] I/O Memory Data 82-85, 88-99,
106
135-138, 141-152
Misc. Interface
Pin Name Pin Type Function Pin
XIN Crystal Oscillator Input Crystal Oscillator Input 203 XOUT Crystal Oscillator Output Crystal Oscillator Output 202 DDCD_DA I/O w/ 5V-tolerant HDCP Serial Bus Data / DDC data of DVI port; 4mA driving
strength DDCD_CK Input w/ 5V-Tolerant HDCP Serial Bus Clock / DDC Clock of DVI Port 15 BYPASS For External Bypass Capacitor 158 VCTRL Output Regulator Control 62
14
Power Pins
Pin Name Pin Type Function Pin
AVDD_DVI 3.3V Power DVI Power 4, 10 AVDD_ADC 3.3V Power ADC Power 17, 34 AVDD_PLL 3.3V Power PLL Power 12 AVDD_PLL2 3.3V Power PLL Power 109 AVDD_APLL 1.8V Power Audio PLL Power 49 AVDD_MPLL 3.3V Power PLL Power 204
Page 48
CIRCUIT DESCRIPTIONS
Pin Name Pin Type Function Pin
VDDM 3.3V Power (SDR SDRAM) /
2.5V Power (DDR SDRAM) VDDP 3.3V Power Digital Output Power 66, 162, 182 VDDC 1.8V Power Digital Core Power 63, 79, 131, 156, 173,
GND Ground Ground 1, 7, 13, 16, 35, 50, 64,
DRAM Interface Power 86, 102, 113, 125, 139,
154
185, 195
65, 80, 87, 103, 108, 114, 126, 132, 140, 155, 157, 159, 163, 172, 183, 184, 194, 205, 206
Page 49
CIRCUIT DESCRIPTIONS
MECHANICAL DIMENSIONS
E
E1
E2
D D1 D2
A2
A
A1
θ2
Gage Plane
Symbol
0.25mm
L
Millimeter Inch
Min. Nom. Max. Min. Nom. Max.
A - - 4.10 - - 0.161 A1 0.25 - - 0.010 - ­A2 3.20 3.32 3.60 0.126 0.131 0.142
D 31.20 1.228 D1 28.00 1.102 D2 25.50 1.004
E 31.20 1.228 E1 28.00 1.102 E2 25.50 1.004
R1 0.13 - - 0.005 - -
b
e
θ1
R1 R2
θ
Seating Plane
Symbol
θ θ1 θ2
b 0.17 0.20 0.27 0.007 0.008 0.011
c 0.11 0.15 0.23 0.004 0.006 0.009
e 0.50 BSC. 0.020 BSC.
L 0.73 0.88 1.03 0.029 0.035 0.041 L1 1.60 Ref 0.063 Ref
S 0.20 - - 0.008 - -
Millimeter Inch
Min. Nom. Max. Min. Nom. Max.
0° - 7° 0° - 7° 0° - - 0° - -
8° Ref 8° Ref
S
L1
c
R2 0.13 - 0.30 0.005 - 0.012
Page 50
CIRCUIT DESCRIPTIONS
General Description
Introduction
The VCT 49xxI is an IC family of high-quality single­chip TV processors. Modular design and deep-submi­cron technology allow the economic integration of fea­tures in all classes of single-scan TV sets. The VCT 49xxI family is based on functional blocks con­tained and approved in existing products like DRX 396xA, MSP 34x5G, VSP 94x7B, DDP 3315C, and SDA 55xx.
Each member of the family contains the entire IF, audio, video, display, and deflection processing for 4:3 and 16:9 50/60-Hz mono and stereo TV sets. The inte­grated microcontroller is supported by a powerful OSD generator with integrated Teletext & CC acquisition including on-chippage memory.
Video & Sound IF
DRX 396xA
Audio Processing
MSP 34x5G
Video Processing
VSP 94x7B
VCT 49xyI
Display & Deflection
DDP 3315C
Control, OSD, Text
SDA 55xx
Fig.:Single-chipVCT49xxI
Features
The VCT 49xxI family offers a rich feature set, cover­ing the whole range of state-of-the-ar t 50/60-Hz TV applications.
– PSSDIP88-1/-2 package – PMQFP144-2 package – Submicron CMOS technology – Low-power standby mode – Single 20.25-MHz reference crystal – 8-bit 8051 instruction set compatible CPU – Up to 256 kB on-chip program ROM – WST,PDC,VPS,andWSSacquisition – ClosedCaptionandV-chipacquisition – Up to 10 pages on-chip teletext memory – Multi-standard QSS IF processing with single SAW – FM Radio and RDS with standard TV tuner – TV-sound demodulation:
• all A2 standards
• all NICAM standards
• BTSC/SAP with MNR (DBX optional)
•EIA-J
– Baseband sound processing for loudspeaker chan-
nel:
• volume
• bass and treble
• loudness
• balance
• spatial effect (e.g. pseudo stereo)
• Micronas AROUND (virtual Dolby optional)
• Micronas BASS – CVBS, S-VHS, YC – 4H adaptive comb filter (P AL/NTSC) – multi-standard color decoder (PAL/NTSC/SECAM) – Nonlinear horizontal scaling “panorama vision” – Luma and chroma transient improvement (LTI, CTI) – Non-linear color space enhancement (NCE) – Dynamic black level expander (BLE) – Scan velocity modulation output – Soft start/stop of H-drive – Vertical angle and bow correction – Average and peak beam curr ent limiter
and RGB inputs
rCb
– Nonlinear and dynamic EHT compensation – Black switch off procedure (BSO)
Page 51
CIRCUIT DESCRIPTIONS
ChipArchitecture
IFIN+
IFIN-
CVBS in
YCrCb in
RGB in
CVBS out
Fig.:BlockdiagramoftheVCT49xxI
IF
Frontend
Video
Frontend
Slicer
24kB
Char ROM
20kB XRAM
Processor
Prog ROM
C G A T
IF
Comb
Filter
Bus
Arbiter
256kB
F
I S
Decoder
Component
Interface
Sound
Demodulator
Color
Panorama
Display
Generator
CPU
8051
Memory
Interface
ADB, DB, PSENQ,
PSWEQ, WRQ, RDQ
Scaler
T U
N
O
I
A
A
Audio
Processor
Display & Deflection Processor
I2C Master/
Slave
Timer
CRT
PWM
ADC
UART
Watchdog
RTC
I/O-Ports
Pxy
R E K A E P S
PROT HOUT HFLB
VERT
Video
Backend
Reset & Test
Logic
Clock
Generator
EW SVM RGB out RGB in
SENSE RSW
I2C
RESETQ TEST
XTAL1 XTAL2
Page 52
CIRCUIT DESCRIPTIONS
PinConnectionsandShortDescriptions
NC = not connected LV = if not used, leave vacant OBL = obligatory; connect as described in circuit diagram IN = Input Pin OUT = Output Pin SUPPLY = Supply Pin
Pin No. Pin Name Type Connection Short Description
PSSDIP 88-pin
1 128 GND SUPPLY OBL Ground Platform 2 129 VSUP5.0BE SUPPLY OBL Supply Voltage Analog Video Back-end, 5.0 V 3 130 TEST IN GND Test Input, reserved for Test 4 131 VERT+ OUT LV Differential Vertical Sawtooth Output 5 132 VERT- OUT LV Differential Vertical Sawtooth Output 6 133 EW OUT LV Vertical Parabola Output
PMQFP-2 144-pin
(If not used)
7 134 RSW2 OUT LV Range Switch 2 Output 8 135 RSW1 OUT LV Range Switch 1 Output 9 136 SENSE IN GND Sense ADC Input 10 137 GNDM IN GND Reference Ground for Sense ADC 11 138 FBIN IN GND Fast Blank Input,Back-end 12 139 RIN IN GND Analog Red Input, Back-end 13 140 GIN IN GND Analog Green Input, Back-end 14 141 BIN IN GND Analog Blue Input, Back-end 15 142 SVMOUT OUT VSUP5.0BE Scan Velocity Modulation Output 16 143 ROUT OUT VSUP5.0BE Analog Red Output 17 144 GOUT OUT VSUP5.0BE Analog Green Output 18 1 BOUT OUT VSUP5.0BE Analog Blue Output 19 2 VRD OBL Reference Voltage for RGB DACs 20 3 XREF OBL Reference Current for RGB DACs 21 4 VSUP3.3BE SUPPLY OBL Supply Voltage Analog Video Back-end, 3.3 V 22 5 GND SUPPLY OBL Ground Platform 23 6 GND SUPPLY OBL Ground Platform 24 7 VSUP3.3IO SUPPLY OBL Supply Voltage I/O Ports, 3.3 V 25 8 VSUP3.3DAC SUPPLY OBL Supply Voltage Video DACs, 3.3 V 26 9 GNDDAC SUPPLY OBL Ground Video DACs 27 10 SAFETY IN GND Safety Input
Page 53
CIRCUIT DESCRIPTIONS
Pin No. Pin Name Type Connection Short Description
PSSDIP 88-pin
28 11 HFLB IN HOUT Horizontal Flyback Input 29 12 HOUT OUT LV Horizontal DriveOutput 30 13 VPROT IN GND Vertical Protection Input
31 39 SDA IN/OUT OBL I 32 40 SCL IN/OUT OBL I 33 41 P21 IN/OUT LV Port 2, Bit 1 Input/Output 34 42 P20 IN/OUT LV Port 2, Bit 0 Input/Output 35 43 P17 IN/OUT LV Port 1, Bit 7 Input/Output 36 44 P16 IN/OUT LV Port 1, Bit 6 Input/Output 37 45 P15 IN/OUT LV Port 1, Bit 5 Input/Output 38 46 P14 IN/OUT LV Port 1, Bit 4 Input/Output 39 47 P13 IN/OUT LV Port 1, Bit 3 Input/Output 40 48 P12 IN/OUT LV Port 1, Bit 2 Input/Output 41 49 P11 IN/OUT LV Port 1, Bit 1 Input/Output 42 50 P10 IN/OUT LV Port 1, Bit 0 Input/Output 43 53 VSUP3.3FE SUPPLY OBL Supply Voltage Analog Video Front-end, 3.3 V 44 54 GND SUPPLY OBL Ground Platform 45 55 GND SUPPLY OBL Ground Platform 46 56 VSUP1.8FE SUPPLY OBL Supply Voltage Analog Video Front-end, 1.8 V 47 57 VOUT3 OUT LV Analog Video 3 Output 48 58 VOUT2 OUT LV Analog Video 2 Output 49 59 VOUT1 OUT LV Analog Video 1 Output 50 60 VIN1 IN GND Analog Video 1 Input 51 61 VIN2 IN GND Analog Video 2 Input 52 62 VIN3 IN GND Analog Video 3 Input 53 63 VIN4 IN GND Analog Video 4 Input 54 64 VIN5 IN GND Analog Video 5 Input 55 65 VIN6 IN GND Analog Video 6 Input 56 66 VIN7 IN GND Analog Video 7 Input
PMQFP-2 144-pin
(If not used)
37 PWMV OUT LV PWM Vertical Output 38 DFVBL OUT LV Dynamic Focus Vertical Blanking Output
2
C Bus Data Input/Output
2
C Bus Clock Input/Output
57 67 VIN8 IN GND Analog Video 8 Input 58 68 VIN9 IN GND Analog Video 9 Input
Page 54
CIRCUIT DESCRIPTIONS
Pin No. Pin Name Type Connection Short Description
PSSDIP 88-pin
59 69 VIN10 IN GND Analog Video 10 Input 60 70 VIN11 IN GND Analog Video 11 Input 61 98 P23 IN/OUT LV Port 2, Bit 3 Input/Output 62 99 P22 IN/OUT LV Port 2, Bit 2 Input/Output 63 100 XTAL2 OUT OBL Analog Crystal Output 64 101 XTAL1 IN OBL Analog Crystal Input 65 102 VSUP1.8DIG SUPPLY OBL Supply Voltage Digital Core, 1.8 V
66 103 GND SUPPLY OBL Ground Platform 67 104 GND SUPPLY OBL Ground Platform 68 105 VSUP3.3DIG SUPPLY OBL Supply Voltage Digital Core, 3.3 V
69 106 VSUP5.0IF SUPPLY OBL Supply Voltage Analog IF Front-end, 5.0 V 70 107 GNDIF SUPPLY OBL Ground Analog IF Front-end 71 108 RESETQ IN/OUT OBL Reset 72 109 IFIN+ IN VREF 73 110 IFIN- IN VREF 74 111 VREFIF OBL Reference Voltage, IF ADC 75 112 TAGC OUT LV Tuner AGC Output 76 113 AIN1R /
77 114 AIN1L IN GND Analog Audio 1 Input, Left 78 115 AIN2R IN GND Analog Audio 2 Input, Right 79 116 AIN2L IN GND Analog Audio 2 Input, Left
80
81
82 121 AOUT1R OUT LV Analog Audio 1 Output, Right
PMQFP-2 144-pin
(If not used)
(main and standby supply)
(main and standby supply)
IF
IF
Input/Output
Differential IF Input Differential IF Input
SIF
IN/OUT GND Analog Audio 1 Input, Right
Analog 2nd Sound IF Output
117 AIN3R IN GND Analog Audio 3 Input, Right 118 AIN3L IN GND Analog Audio 3 Input, Left 119 AOUT2R OUT LV Analog Audio 2 Output, Right 120 AOUT2L OUT LV Analog Audio 2 Output, Left
AIN3R / AOUT2R
AIN3L / AOUT2L
IN / OUT
IN / OUT
LV Analog Audio 3 Input, Right
Analog Audio 2 Output, Right
LV Analog Audio 3 Input, Left
Analog Audio 2 Output, Left
83 122 AOUT1L OUT LV Analog Audio 1 Output, Left 84 123 SPEAKERR OUT LV Analog Loudspeaker Output, Right
Page 55
CIRCUIT DESCRIPTIONS
Pin No. Pin Name Type Connection Short Description
PSSDIP 88-pin
85 124 SPEAKERL OUT LV Analog Loudspeaker Output, Left 86 125 VREFAU OBL Reference Voltage, Audio 87 126 VSUP8.0AU SUPPLY OBL Supply Voltage Analog Audio, 8.0 V 88 127 GND SUPPLY OBL Ground Platform
PMQFP-2 144-pin
(If not used)
71 P37 /
656IO7
72 P36 /
656IO6
73 P35 /
656IO5
74 P34 /
656IO4
IN/OUT LV Port 3, Bit 7 Input/Output
Digital 656 Bus 7 Input/Output
IN/OUT LV Port 3, Bit 6 Input/Output
Digital 656 Bus 6 Input/Output
IN/OUT LV Port 3, Bit 5 Input/Output
Digital 656 Bus 5 Input/Output
IN/OUT LV Port 3, Bit 4 Input/Output
Digital 656 Bus 4 Input/Output
75 P33 /
656IO3
76 GNDEIO SUPPLY OBL Ground Extended I/O Ports
IN/OUT LV Port 3, Bit 3 Input/Output
Digital 656 Bus 3 Input/Output
77 VSUP3.3EIO SUPPLY OBL Supply Voltage Extended I/O Ports, 3.3 V 78 P32 /
656IO2
79 P31 /
656IO1
IN/OUT LV Port 3, Bit 2 Input/Output
Digital 656 Bus 2 Input/Output
IN/OUT LV Port 3, Bit 1 Input/Output
Digital 656 Bus 1 Input/Output
80 P30 /
656IO0
81 P26 /
656VIO
82 P25 /
656HIO
83 P24 /
656CLKIO
IN/OUT LV Port 3, Bit 0 Input/Output
Digital 656 Bus 0 Input/Output
IN/OUT LV Port 2, Bit 6 Input/Output
Digital 656 Vsync Input/Output
IN/OUT LV Port 2, Bit 5 Input/Output
Digital 656 Hsync Input/Output
IN/OUT LV Port 2, Bit 4 Input/Output
Digital 656 Clock Input/Output 31 ADB19 OUT LV Address Bus 19 Output 21 ADB18 OUT LV Address Bus 18 Output 19 ADB17 OUT LV Address Bus 17 Output 22 ADB16 OUT LV Address Bus 16 Output 23 ADB15 OUT LV Address Bus 15 Output 18 ADB14 OUT LV Address Bus 14 Output 17 ADB13 OUT LV Address Bus 13 Output 26 ADB12 OUT LV Address Bus 12 Output 14 ADB11 OUT LV Address Bus 11 Output
Page 56
CIRCUIT DESCRIPTIONS
Pin No. Pin Name Type Connection Short Description
PSSDIP 88-pin
PMQFP-2 144-pin
96 ADB10 OUT LV Address Bus 10 Output 15 ADB9 OUT LV Address Bus 9 Output
(If not used)
16 ADB8 OUT LV Address Bus 8 Output 27 ADB7 OUT LV Address Bus 7 Output 28 ADB6 OUT LV Address Bus 6 Output 29 ADB5 OUT LV Address Bus 5 Output 30 ADB4 OUT LV Address Bus 4 Output 84 ADB3 OUT LV Address Bus 3 Output 85 ADB2 OUT LV Address Bus 2 Output 86 ADB1 OUT LV Address Bus 1 Output 87 ADB0 OUT LV Address Bus 0 Output 88 DB0 IN/OUT LV Data Bus 0 Input/Output 89 DB1 IN/OUT LV Data Bus 1 Input/Output 90 DB2 IN/OUT LV Data Bus 2 Input/Output 91 DB3 IN/OUT LV Data Bus 3 Input/Output 92 DB4 IN/OUT LV Data Bus 4 Input/Output 93 DB5 IN/OUT LV Data Bus 5 Input/Output 94 DB6 IN/OUT LV Data Bus 6 Input/Output 95 DB7 IN/OUT LV Data Bus 7 Input/Output 32 RDQ OUT LV Data Read Enable Output 33 WRQ OUT LV Data Write Enable Output 34 OCF OUT LV Opcode Fetch Output 35 ALE OUT LV Address Latch Enable Output 36 RSTQ OUT LV Internal CPU Reset Output 97 PSENQ OUT LV Program Store Enable Output 20 PSWEQ OUT LV Program Store Write Enable Output 51 XROMQ IN OBL External ROM Enable Input 52 EXTIFQ IN LV Enable External Interface Input 24 STOPQ IN LV Stop CPU Input 25 ENEQ IN LV Enable Emulation Input
Page 57
CIRCUIT DESCRIPTIONS
CIRCUIT DESCRIPTIONS
CIRCUIT DESCRIPTIONS
CIRCUIT DESCRIPTIONS
CIRCUIT DESCRIPTIONS
PinDescriptions SupplyPins VSUP1.8DIG
This pin is main and standby supply for the digital core logic of controller, video, display and deflection pro­cessing.
VSUP1.8FE − Supply Voltage 1.8 V
This pin is main supply for the analog video front-end.
VSUP3.3FE − Supply Voltage 3.3 V
This pin is main supply for the analog video front-end.
VSUP3.3IO − Supply Voltage 3.3 V
This pin is main and standby supply for the digital I/O­ports.
VSUP3.3DIG − Supply Voltage 3.3 V
This pin is main supply for the digital core logic of IF and audio processing and digital video back-end.
VSUP3.3BE − Supply Voltage3.3 V
This pin is main supply for the analog video back-end.
VSUP5.0BE − Supply Voltage5.0 V
This pin is main supply for the analog video back-end.
VSUP8.0AU − Supply Voltage 8.0 V
This pin is main supply for the analog audio process­ing.
GND − Ground Platform
This pin is main ground for all above supplies.
VSUP3.3DAC − Supply Voltage 3.3 V
This pin is main supply for the video DACs.
GNDDAC Ground for 3.3 V Video DAC Supply VSUP5.0IF Supply Voltage 5.0 V
This pin is main supply for the analog IF front-end.
GNDIF Ground for 5.0 V IF Supply VSUP3.3EIO Supply Voltage 3.3 V
This pin is main and standby supply for the extended digital I/O-ports available in QFP package only. It is internally connected to
GNDEIO
It is internally connected to GND.
Application Note:
All GND pins must be connected to a low-resistive ground plane underneath the IC. All supply pins must be connected separately with shor t and low-resistive lines to the power supply. Decoupling capacitors from
VSUPxx to GND have to be placed as closely as pos-
sible to these pins. It is recommended to use more
Supply Voltage 1.8 V
VSUP3.3IO.
Ground for 3.3 V Extended I/O Supply
than one capacitor. By choosing different values, the frequency range of activedecoupling can be extended.
IFPins VREFIF
This pin must be connected to according to the application circuit. Low inductance caps are necessary.
IFIN+, IFIN- − Balanced IF Input (Fig. 4–6)
These pins must be connected to the SAW filter out­put. The SAW filter hastobeplaced as close as possi­ble. The layout of the IF input should be symmetrical with respect to
SIF − 2nd Sound IF Output (Fig. 4–8)
Output level is set via I processor (e.g. MSP) can be connected to this pin. This pin is also configurable as audio input (see Fig. 4–10).
TAGC − Tuner AGC Output (Fig. 4–7)
This pin controls the delayed tuner AGC. As it is a noise-shaped-I-DAC output, it has to be connected according to the applicationcircuit.
AudioPins VREFAU
4–14) This pin serves as the internal ground connection for the analog audio circuitry. It must be connected to the
GND pinwitha3.3µF and a 100 nF capacitor in paral-
lel. This pins shows a DC level of typically 3.77 V.
AIN1 L – Audio 1 Inputs (Fig. 4–10)
The analog input signal for audio 1 is fed to this pin. Analog input connection must be AC coupled.
AIN1 R – Audio 1 Inputs (Fig. 4–10)
The analog input signal for audio 1 is fed to this pin. Analog input connection must be AC coupled. This pin is also configurable as sound IF output (see Fig. 4–8).
AIN2 R/L – Audio 2 Inputs (Fig. 4–10)
The analog input signal for audio 2 is fed to this pin. Analog input connection must be AC coupled.
AIN3 R/L – Audio 3 Inputs (Fig. 4–10)
The analog input signal for audio 3 is fed to this pin. Analog input connection must be AC coupled.
Reference Voltage for Analog IF (Fig. 4–9)
GNDIF via a circuitry
GNDIF.
2
C-Bus. An appropriate sound
– Reference Voltage for Analog Audio (Fig.
Page 58
GeneralDescription
CIRCUIT DESCRIPTIONS
AOUT1 R/L – Audio 1 Outputs (Fig. 4–11)
Output of the analog audio 1 signal. Connections to these pins are intended to be AC coupled.
AOUT2 R/L – Audio 2 Outputs (Fig. 4–11)
Output of the analog audio 2 signal. Connections to these pins are intended to be AC coupled.
SPEAKER R/L – Loudspeaker Outputs (Fig. 4–13)
Output of the loudspeaker signal. A 1 nF capacitor to
GND must be connected to these pins. Connections to
these pins are intended to be AC-coupled.
VideoPins VIN 1–11
These are the analog video inputs. A CVBS, S-VHS, YCrCb or RGB/FB signal is converted using the luma, chroma and component AD converters. The input sig­nals must be AC-coupled by 100nF. In case of an ana­log fast blank signal carryingalphablending information the input signal must be DC-coupled.
VOUT 1-3 − Analog Video Output (Fig. 4–16)
The analog video inputs that are selected by the video source select matrix are output at these pins.
Analog Video Input (Fig.4–15)
RIN, GIN, BIN − Analog RGB Input (Fig. 4–17)
These pins are used to insert an external analog RGB signal, e.g. from a SCART connector which can be switchedto the analogRGB outputswith the fastblank signal. Separate brightness and contrast settings for the external analog signals are provided.
FBIN − Fast Blank Input (Fig. 4–18)
This pin is used to switch the RGB outputs to the exter­nal analog RGB inputs. The active level (low or high) can be selected by software.
ROUT, GOUT, BOUT − Analog RGB Output (Fig. 4–
19) These pins are the analog Red/Green/Blue outputs of the back-end. The outputs are current sinks.
SVMOUT − Scan Velocity Modulation Output (Fig. 4–
19) This output delivers the analog SVM signal. The D/A converter is a current sink like the RGB D/A convert­ers. At zero signal the output current is 50% of the maximum output current.
VRD − DAC Reference Decoupling (Fig. 4–20)
Via this pin the RGB-DAC reference voltage is decou­pled by an external capacitor. The DAC output cur­rents depend on this voltage, therefore a pulldown transistor can be used to shut off all beam currents. A decoupling capacitor of 4.7 µF in parallel to 100 nF (low inductance) is required.
XREF − DAC Current Reference (Fig. 4–20)
External reference resistor for DAC output currents, typical 10 kto adjust the output current of the D/A converters. (see recommended operating conditions). This resistor has to be connected to ground as closely as possible to the pin.
CRTPins VPROT
The vertical protection circuitry prevents the picture tube from burn-in in the event of a malfunction of the vertical deflection stage. If the peak-to-peak value of the sawtooth signal from the vertical deflection stage is too small, the RGB output signals are blanked.
SAFETY − Safety Input (Fig. 4–22)
This input has two thresholds. A signal between the lower and upper threshold means normal function. A signal below the lower threshold or above the upper threshold is detected as malfunction and the RGB sig­nals will be blanked.
HOUT − Horizontal Drive Output (Fig. 4–21)
This open source output supplies the drive pulse for the horizontal output stage. An external pulldown resistor has to be used. The polarity and gating with the flyback pulse are selectable by software.
HFLB − Horizontal Flyback Input (Fig. 4–22)
Via this pin the horizontal flyback pulse is supplied to the VCT 49xxI.
VERT+, VERT−−Vertical Sawtooth Output (Fig. 4–23)
These pins supply the symmetrical drive signal for the vertical output stage. The drive signal is generated with 15-bit precision. The analog voltage is generated by a 4 bit current-DAC with an external resistor of
6.8 kand uses digital noise shaping.
EW − East-West Parabola Output (Fig. 4–24)
This pin supplies the parabola signal for the East-West correction. The drive signal is generated with 15 bit precision. The analog voltage is generated by a 4 bit current-DAC with an external resistor of 6.8 kand uses digital noise shaping.
PWMV − PWM Vertical Output (Fig. 4–35)
This pin provides an adjustable vertical parabola with 7 bit resolution and appr. 79.4 kHz PWM frequency.
DFVBL − Dynamic Focus Vertical Blanking (Fig. 4–35)
This pin supplies the blank pulse for dynamic focus during vertival blanking period or a free programmable horizontal pulse for horizontal dynamic focus genera­tion.
Vertical Protection Input (Fig. 4–22)
Page 59
GeneralDescription
CIRCUIT DESCRIPTIONS
SENSE − Measurement ADC Input (Fig. 4–27)
This is the input of the analog to digital converter for the picture and tube measurement. Three measure­ment ranges are selectable with RSW1 and RSW2.
GNDM − Meas urement ADC Reference Input
This is the reference ground for the measurement A/D converter. Connect this pin to GND.
RSW1 − Range Switch1 for Measuring ADC (Fig. 4–
25) These pin is an open drain pulldown output. During cutoff and white drive measurement the switch is off. Duringtherestoftimeitison.TheRSW1pincanbe used as second measurement ADC input for picture beam current measurement.
RSW2 − Range Switch2 for Measuring ADC (Fig. 4–
26) These pin is an open drain pulldown output. During cutoff measurement the switch is off. During white drive measurement the switch is on. Also during the rest of time it is on. It is used to set the range for white drive current measurement.
ControllerPins XTAL1
4–28) These pins connect a 20.25 MHz crystaltothe internal oscillator. An external clock can be fed into XTAL1.
Crystal Input and XTAL2 Crystal Output (Fig.
RESETQ − Reset Input/Output (Fig. 4–29)
A low level on this pin resets the VCT 49xxI. The inter­nal CPU can pull down this pin to reset external devices connected to this pin.
TEST − T est Input (Fig. 4–30)
This pin enables factorytest modes. For normal opera­tion, it must be connected to ground.
SCL − I
This pin delivers the I be pulled down by external slave ICs to slow down data transfer.
SDA − I
This pin delivers the I
2
C Bus Clock (Fig. 4–31)
2
C bus clock line. The signal can
2
C Bus Dat a(Fig. 4–31)
2
C bus data line.
P10P13, P20P23 − I/O Port (Fig. 4–32)
These pins provide CPU controlled I/O ports.
P14P17 − I/O Port (Fig. 4–33)
These pins provide CPU controlled I/O ports. Addition­ally they can be used as analog inputs for the control­ler ADC.
P24P26, P30P37 − I/O Port (Fig. 4–34)
These pins provide CPU controlled I/O ports.
ADB0ADB19 − Address Bus Output (Fig. 4–35)
These 20 lines provide the CPU address bus output to access external memory.
DB0DB7 − Data Bus Input/Output (Fig. 4–36)
These 8 lines provide the bidirectional CPU data bus to access external memory.
WRQ − Data Write Enable Output (Fig. 4–35)
This pin controls the direction of data exchange between the CPU and the external data memory device (SRAM).
RDQ − Data Read Enable Output (Fig. 4–35)
Thispinisusedtoenabletheoutputdriverofthe external data memory device (SRAM) for read access.
PSENQ − Program Store Enable Output (Fig. 4–35)
Thispinisusedtoenabletheoutputdriverofthe external program memory device (ROM/FLASH) for read access.
PSWEQ − Program Store Write Enable Output (Fig. 4–
35) This pin is used to write into the externalprogram flash memory device.
XROMQ − External ROM Enable Input (Fig. 4–37)
This pin must be pulled low to access the external pro­gram memory. tor.
EXTIFQ − Enable External Memory Interface Input
(Fig. 4–37) This pin must be pulled low to enable the external memory interface. resistor.
STOPQ − Stop CPU Input (Fig. 4–37)
Applying a lowlevel during the inputphase freezes the realtime relevant internal peripherals such as timers and interrupt controller. resistor.
ENEQ − Enable Emulation Input (Fig. 4–37)
Only if this pin is set tolow level, STOPQ and OCF are operational.
ALE − Address Latch Enable Output (Fig. 4–35)
This signal indicates changes on the address bus.
OCF − Opcode Fetch Output (Fig. 4–35)
A high level driven by the CPU during output phase indicates the beginning of a new instruction.
RSTQ − Internal CPU Reset Input/Output (Fig. 4–38)
This pin is used for emulation purpose only. A low level on this pin resets the CPU. It also indicates an internal reset of the CPU.
XROMQ has an internal pull-up resis-
EXTIFQ has an internal pull-up
STOPQ has an internal pull-up
ENEQ has an internal pull-up resistor.
Page 60
GeneralDescription
GNDIF
IFIN+
IFIN-
VREFIF
TAGC
AIN1R / SIF
AIN1L AIN2R AIN2L AIN3R AIN3L
AOUT2R
AOUT2L
AOUT1R
AOUT1L
SPEAKERR
SPEAKERL
VREFAU
VSUP8.0AU
GND GND
VSUP5.0BE
TEST
VERT+
VERT-
EW RSW2 RSW1
SENSE
GNDM
FBIN
RIN GIN BIN
SVMOUT
ROUT GOUT
RESETQ
108
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138
139 140 141 142
143 144
123456789101112131415161718192021
BOUT
Fig.PMQFP144-2package
107
VRD
VSUP3.3DIG
VSUP5.0IF
105
106
XREF
VSUP3.3BE
104
CIRCUIT DESCRIPTIONS
P25 / 656HIO
P26 / 656VIO
P30 / 656IO0
P31 / 656IO1
P32 / 656IO2
VSUP3.3EIO
GNDEIO
P33 / 656IO3
P34 / 656IO4
GND
GND
VSUP1.8DIG
XTAL1
XTAL2
P22
P23
PSENQ
ADB10
DB7
DB6
DB5
DB4
DB3
DB2
103
102
101
100
DB1
DB0
88
90
91
96
97
98
99
92
93
94
95
89
ADB3
ADB2
ADB0
ADB1
P24 / 656CLKIO
80
81
84
86
87
82
83
85
78
79
77
VCT 49xyI
242526
27
30
22
23
GND
GND
VSUP3.3IO
HFLB
SAFETY
GNDDAC
VSUP3.3DAC
HOUT
ADB9
ADB8
ADB11
ADB13
ADB14
ADB18
ADB16
VPROT
ADB17
ADB15
PSWEQ
STOPQ
ENEQ
ADB7
ADB12
28
ADB6
29
ADB5
ADB4
3132333435
RDQ
ADB19
P35 / 656IO5
74
75
76
73
72
P36 / 656IO6
71
P37 / 656IO7
70
VIN11
69
VIN10
68
VIN9
67
VIN8
66
VIN7 VIN6
65 64
VIN5 VIN4
63
VIN3
62 61
VIN2
60
VIN1
59
VOUT1 VOUT2
58
VOUT3
57
VSUP1.8FE
56
GND
55
GND
54
VSUP3.3FE
53 52
EXTIFQ
51
XROMQ P10
50
P11
49
P12
48
P13
47
P14
46
P15
45
P16
44
P17
43
P20
42
P21
41 40
SCL
39
SDA
38
DFVBL
37
PWMV
36
ALE
OCF
WRQ
RSTQ
Page 61
CIRCUIT DESCRIPTIONS
Advance Information Supplement
Subject: Data Sheet Concerned:
Supplement: Edition:
Changes to the previous revision are indicated by change bars. Please note section 2.1.1.2., which is of importance for the use of the VCT-I F1 in combination with NICAM-audio modes.
1. VCT 49xyI Version History
1.1. Field Problems
Field test results are available for the VCT 49xyI versions C7 to D5. The versions F1 and F2 are intended to solve all listed field problems.
Table 1–1: History of field problems
No. Field Problem C7 D2 D4 D5 F1 F2 Comment
FP01 Streaky Noise x x x x Problem solved in F1 FP02 Modulator Imbalance
x x x x Problem solved in F1 FP03 FM Modulation FP04 Color Clipping x x x x x Problem to be solved in F2 FP05 Closed Caption Performance FP06 VSP-AGC performance FP07 Sync/H-PLL performance x x x x x Problem to be solved in F2
x x x x Problem solved in F1
x x x x Problem to be solved in F1
x x x x x Problem to be solved in F2
1.2. Functional Problems
For a more detailed description and workarounds of the functional problems please refer to the list of the particular VCT 49xyI version in the next sections. The problem numbers are consistent throughout the whole document. The versions F1 and F2 are intended to solve the remaining problems.
Table 1–2: History of functional problems
No. Functional Problem C6 C7 D2 D4 D5 F1 F2 Comment
18 Vertical Synchronisation
x x Problem solved in D2
Additional Info for VCT49xyI VCT49xyI
6251-573-1AI, Edition Feb. 18, 2004 Version History Dec. 16, 2004
26 Picture Frame Blanked 34 Reset after Read x x Problem solved in D2
x x Problem solved in D2
Page 62
CIRCUIT DESCRIPTIONS
Table 1–2: History of functional problems, continued
No. Functional Problem C6 C7 D2 D4 D5 F1 F2 Comment
39 Peaking Filter x x Problem solved in D2 40 Bandwidth of Antialias Filter
x x Problem solved in D2 41 SVM Overflow x x Problem solved in D2 42 ADC Ini tia lis at ion 43 a) Clock Noise
b) IF-Nonlinearity
x x Problem solved in D2
! ! ! ! ! ! ! ! = Applicative methods
solve the problem to a large extent
x x x
*)
x x x
*)
slight degradation in comparison to C6/7, D4/5. Problem to be solved in F2
45 DRX Video-DAC Headroom 46 HORPOS changes color multi-
plex 47 Preframe Generator 48 DRX AGC Hangup x x Problem solved in D2 50 Fastblank Monitor
x Problem solved in C7 x x Problem solved in D2
x x Problem solved in D2
x x x x x Problem solved in F1
51 East/West Glitch
52 OSD Jitter
53 MSP Automatic Standard
Detection for EIA-J 54 MSP Standard Toggle in HDEV-
Mode fails
x x x Problem solved in D4
x x x Problem solved in D4
! ! ! Problem appeared in D2,
Problem solved in F1 ! = workaround available
x x Problem appeared in D2,
Problem solved in D5
55 OSD Offset Compensation 56 ESD Induced Reset
57 White Blanking Line in OSD
x x x x x Problem solved in F1
! ! ! Problem appeared in D2,
Problem solved in F1 ! = workaround available
! ! ! ! ! Problem solved in F1
! = workaround available
58 EHT
! ! ! Problem appeared in D2,
Problem solved in F1 ! = workaround available
60 VCR detection “TVMODE”
61 Vertical flywheel mode
(VFLYWHLMD)
x x ! ! ! ! ! ! = Workaround available
no redesign planned
! ! ! ! ! ! ! ! = Workaround available
no redesign planned
62 BLE
! ! ! ! ! Problem solved in F1
! = workaround available
Page 63
CIRCUIT DESCRIPTIONS
Table 1–2: History of functional problems, continued
No. Functional Problem C6 C7 D2 D4 D5 F1 F2 Comment
63 ODC-Modes: FHPULLIN/
64 Safety Pin 65 13.5MHz Backend Mode
SHPULLIN
66 ITU656 Interference
67 Audio EIA-J: Plop from stereo to
68 BSO
mono
69 H-Out Jitter ! ! x x x Problem solved in F1
70 SCE Luma Input
71 YUV ECO Mode 72 Scaler Bondoption 73 FM rad io not working
74 ITU656 Biterror
! ! ! ! ! ! ! ! = Workaround available
no redesign planned
x x x x x Problem solved in F1
- - x x x - = new feature in D2, Problem solved in F1
- - x x x - = new feature in D2, Problem solved in F1
x x x x x x under investigation
Problem to be solved in F2
x x x x x Problem solved in F1
! = workaround available
- - x x x - = new feature in D2, Problem solved in F1
x x x x x Problem solved in F1 x x x x x Problem solved in F1
! Problem appeared in F1,
Problem to be solved in F2 ! = workaround available
x Problem appeared in F1,
Problem to be solved in F2
Page 64
CIRCUIT DESCRIPTIONS
7. VCT49xyI-C7
The VCT 49xyI-C7 is pin-compatible to VCT 49xyI-C6 and VCT 49xyI-C4. Problem 45 has been solved. Problem 43 is partly solved: Improved internal clock suppression leads to reduced
noise floor and better video snr. Problems 53 and 54 have not been detected before D2. VCT 49xyI-C7 includes functionality of DRX396xA-H8.
Table 7–1: Functional problems of VCT 49xyI-C7:
No. Problem Description Comment OK
18 Vertical Synchr oni sa -
tion
26 Picture Frame Blanked Left side of picture frame is blanked
34 Reset after Read All I2C register with "reset by read"
39 Peaking Filter In case of PKCF=2,3, the dynamic
40 Bandwidth of Antialias
Filter
41 SVM Overflow The SVM output signal is not lim-
42 ADC Initialisation Wrong initialisation of RGB ADCs
43 Clock Noise Induced harmonics of the system
46 HORPOS changes
color multiplex
47 Preframe Generator The preframe generator cannot
Vertical pull-in after channel change takes too long
if HORPOSG<180.
are not functional (NMSTATUS, LBDSTATUS, FBLACTIVE, FBFALL, FBRISE, PFBL/G/R/B).
peaking adaption doesn’t work. Thus the peaking signal is limited only.
The bandwidth adjustment of the antialias filter 1-6 is disturbed. This causes wrong filter settings after reset and/or after a modification of TRIM_FILTER1-6
ited correctly over the full range of SVLIM.
after power-on causes color mis­match.
clock generate visible interf erenc e on weak IF input signals.
When picture is shifted to the right via HORPOS the color multiplex is inverted.
produce full screen background color.
hardware redesign D1 workaround:
increase LPFOPOFF hardware redesign D1 D1
hardware redesign D1 D1
hardware redesign D1 D1
hardware redesign D1 workaround:
<0xb0 0x2f 0x00 0x01>
hardware redesign D1 workaround: SVLIM = 31
hardware redesign D1 workaround:
<0xb0 0x37 0x00 0xe4>
hardware redesign D1
hardware redesign D1 workaround: HORPOS+HORWIDTH < 1287
hardware redesign D1 D1
D1
D1
D1
D1
D1
Page 65
CIRCUIT DESCRIPTIONS
No. Problem Description Comment OK
48 DRX AGC Hangup If VAGC_REDUC>0 and positive
signal jumps above top level, AGC hangup may occur and CVBS out­put level is reduced.
53 MSP Automatic Stan-
dard Detection
Automatic standard detection fails, if EIA-J is selected as preferred
4.5MHz-sound carrier.
54 MSP Standard Toggle
in HDEV-Mode fails
T oggling between S tandard 3 and 8 while Mod_HDEV_A = 1 leads to occasional sound impairments
firmware redesign D1 workaround: KI_CHANGE_TH = 19 after stan-
dard change firmware redesign D4
workaround: avoid Mod_4_5MHz[1:0]=[1,0]. If
Mod_ASS and Mod_Dis_Std_Chg = 1, EIA-J is detected anyhow
firmware redesign D4 workaround: not available
D2
D4
D4
Page 66
CIRCUIT DESCRIPTIONS
2. VCT49xyI-F1
The VCT 49xyI-F1 is targeted to solve field and functional problems of the earlier VCT-I versions. For that purpose some new registers were implemented. In addition workarounds used for VCT-I versions prior to F1 may not be compatible.
The VCT 49xyI-F1 is pin-compatible to VCT 49xyI-D5. Functional problems 50, 56, 57 and 58, 62, 64, 65, 66, 68, 69, 70, 71 have been solved. Problem 55 has been
solved but requires software initialisation. Field problems FP01, FP02 and FP03 have been solved, FP06 and FP07 are still under inverstigation. New features F19 and F20 have been successfully implemented.
Table 2–1: New features of VCT 49xyI-F1:.
No. Feature Description Ok
F19 Vertical Peaking Additional mode for vertical peaking in 4H-combfilter allows switching
F20 Fastblank Output The fastblank signal of the TVT display generator is availbale as output
Table 2–2: Field problems of VCT 49xyI-F1:
No. Problem Description Comment Ok
FP06 VSP-AGC performance Poor performance with some non
FP07 Sync/H-PLL perfor-
Table 2–3: Functional problems of VCT 49xyI-F1:
No. Problem Description Comment Ok
73 FM Radio not working root causes:
74 ITU656 Biterror Bit errors on ITU656 output data
mance
between 2H and 1H peaking filter. See new register VPM in section
2.1.2.
signal for LCD-Scaler applications. It can be programmed to the pin PWMV, P11 and P21.
hardware redesign in F2
standard signals Poor performance with some VCR
tapes
a) fast carrier recovery is automati­cally always ON, but should be OFF for FM-Radio mode
b) When switching to FM-Radio mode the output frequency some­times will not be set correctly
produce noisy and unstable picture.
hardware redesign in F2
firmware redesign F2 workaround: s. 2.1.1.4. W3 & W4
metal fix F1 no workaround available
F1
F1
F2
Page 67
CIRCUIT DESCRIPTIONS
2.1. Register Changes on VCT 49xyI-F1
2.1.1. DRX Part
The major improvement of the VCT 49xyI-F1 DRX-performance is based on the speed up of the Tuner-AGC, the Video AGC and the Carrier Recovery. While the faster Tuner and Video AGC help to improve significantly the Streaky Noise and Airplane Flutter issues, the extended Carrier Recovery removes all remaining field test matters. Although the fast modes are activated by default, some new registers are introduced to enable the configuration of the modified functions if necessary.
Table 2–4: New DRX Registers
Name Sub Addr Dir Reset Range Function
Advanced Settings
MOD_ACCU_BS[9:0] h10 h100E[10:1] RW 0 -512..511 Modulator imbalance value
MOD_UPDATE h10 h100E[0] W 0 0,1 Update modulator imbalan c e
MOD_TH[3:0] h10 h100F[11:8] W 5 0..15 Imbalance control threshold
MOD_MODE h10 h100F[7] W 1 0,1 Imbalance Control estimation mode
MOD_If[3:0] h10 h100F[6:3] W 6 0..15 Imbalanc e control integral part (falling)
MOD_Ir[2:0] h10 h100F[2:0] W 1 0..7 Imbalance control integral part (rising)
NOISE_BS[3:0] h10 h1013[3:0] W 15 0..15 Maximum deviation for noise reduction PHAC_BP h10 h1015[9] W 0 0,1 Phase correction bypass
FAST_VAGC_EN h10 h1023[8] W 1 0,1 Enable Fast VAGC
COMP_DC_MUX[2:0] h10 h10B3[11:9] W 7 0..7 Multiplexer for DC estimation during compensation
COMP_FREQ_BS[8:0] h10 h10B3[8:0] W 93 0..511 Increment for reference signal generation
Firmware
BP_KI_MIN_BS[5:0] h10 h10A5[5:0] W 21 0..63 Minimum KI setting
2.1.1.1. Comments to the Tuner and Video-AGCs
The fast mode of the Video AGC is enabled by default and can be switched off by FAST_VAGC_EN = 0. Neverthe­less, switching off this new AGC is not recommended.
In earlier versions the VAGC_KI and TAGC_KI values had to be continuously updated to prevent the adaptive KI control from setting them too low. In the new version a minimum limit register is implemented: BP_KI_MIN_BS allows to determine the minimum allowed KIs.
For example : BP_KI_MIN_BS = 0x15 means: TAGC_KI must not be lower than 2 and VAGC_KI must not be lower than 5.
Write:set manual imbalance value (with MOD_IF=0, MOD_IR=0, for take-over set MO D_UPDATE=1) Read:compensated imbalance value
1: write Modulator imbalance value into hardware
Selects the edge sensitivity
0: trigger estimation on rising edges 1: trigger estimation on rising and falling edges
The control uses this value for decreasing i mbalance
The control uses this value for increasing imbalance
0: active phase correction 1: byp ass phase correction
0: Fast VAGC disabled 1: Fast VAGC enabled
The reference signal is attenuated with the following filter H(z) = 0.5*(1+z^-(4+COMP_DC_MUX)) @fs=40.5MHz
19.7kHz<fref<10.1MHz COMP_FREQ_BS = (fref*2048/40.5MHz)
TAGC_KI and VAGC_KI will not be set below this values
BP_KI_MIN_BS is set to 0x15 by default. Should there be a need for further improving Streaky Noise, 0x16 or 0x17 can be user selected. With the new algorithm VAGC_KI = 6 or 7 are also stable settings and do not produce any stripes.
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CIRCUIT DESCRIPTIONS
All controller software workarounds used at former versions which write the KIs will no longer be needed and should be removed (see also next section).
2.1.1.2. Comments to the Carrier Recovery in Connection with NICAM Audio Performance
The speed up of the carrier recovery to optimize the performance at non standard RF signals (caused by FM modu­lation and modulator imbalance) is mainly based on a significant extension of the PLL-bandwith. However as a mat­ter of principle any extension of the PLL bandwith increases the system noise sensitivity.
Since the NICAM audio system is basically highly sensitive to phase noise, the fast carrier recovery may reduce the NICAM sensitivity, depending on the RF-signal condition. To avoid any reduction of the NICAM sound quality it is recommended to switch off th e carrier recovery speed up in case of NICAM reception setting the register
to 1 (see also section 2.1.1.4., WP5).
2.1.1.3. Status of VCT 49xyI-F1 and how to deal with currently used workarounds
The following table gives recommendations how to deal with workarounds used at C7/Dx:
No. Problem Countries Workaround
FP1 Streaky Noise Korea T1-Coefficients for M/N
for C7 / Dx
Speed up DRX video AGC:
- write VAGC_KI=5 every 20ms
FP2 Modulator Imbal-
ance
Korea, China, Thailand, Brazil
- write TAGC_KI=2 every 20ms
Adaptively (AFC_LOCK_QUAL):
- CR_AMP_TH 16 -> 64
FP3 FM Modulation India,
Flicker, Airplane Flutter
RC: default AGC setting too slow
Vietnam
Pakistan, Korea
Asia, France,
Czech
Adaptively (NLPFLD):
- CLMPST1 28 -> 45
- CLMPD1 11-> 3
- CR_P 3-> 4 Speed up DRX video AGC:
- write VAGC_KI=5 every 20ms
- write TAGC_KI=2 every 20ms
PHAC_BP
Side-Effect Status in F1 Recommen-
dation for F1
Could not solve prob­lem com­pletely
Reduced FM
sound S/N
Could not solve prob­lem com­pletely
SW code overhead
adaptive functional­ity not usablex
significantly improved
significantly improved
significantly improved
significantly improved, previously forced va l­ues now default
remove WA
remove WA
remove WA
remove WA
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CIRCUIT DESCRIPTIONS
No. Problem Countries Workaround
Hsync Distortion Malaysia Speed up DRX video AGC:
Color Sensitivity, bar edge distortion
RC: default NOISE_BS=15 too high
India, Malaysia
for C7 / Dx
- KI_CHANGE_TH=1
- VAGC_REDUC=1 Reduce NOISE_BS to 8
(partly adaptively when chroma level is small)
Side-Effect Status in F1 Recommen-
dation fo r F1
none previously
forced val­ues now default
Measured Video S/N 1-2dB smaller
unchanged (0xF still default)
remove WA
keep WA
2.1.1.4. Recommended Workarounds for VCT 49xyI-F1
Although the field problems have been fixed successfully, there are recommendations for specific input-signals. Please consider the following table.
No. Issue Workaround for F1 Side-Effect Plan for F2
W1 Imbalance control can cause prob-
lems when changing from high to low RF signal levels
W2 MOD_ACCU_BS must be written
several times until value is accepted
W3 FM radio not working; root cause:
fast carrier recovery is automatically ON in FM radio mode, should be OFF
W4 When switching to FM-Radio mode
the output frequency sometimes will not be set correctly
W5 Reduction of NICAM sensitivity at
weak RF signal conditions
If TAGC_I = 0:
- set MOD_Ir = 0
- set MOD_If = 0
- write MOD_ACCU_BS = 0 (consider also W2)
Write MOD_ACCU_BS until readback value matches written value (remember that MOD_UPDATE has to be 1 for writ­ing MOD_ACCU_BS)
Set PHAC_PB to 1 in FM radio mode only, to 0 in TV modes
Repeat switching to FM-Radio mode and subsequently read out AFC_DEV until the value is 0
Set PHAC_PB to 1 in NICAM audio mode
none under inves-
tigation
none firmware
redesign
none firmware
redesign
none firmware
redesign
none under inves-
tigation
Page 70
2.1.2. VSP Part Table 2–5: New VSP Registers
CIRCUIT DESCRIPTIONS
Name Sub Dir Sync Reset Range Function
CD
LPCDEL[2:0] h07[2:0] RW VS_CD 0 -8..7 Window Shift For Fine Error Calculation
THRSEL[1:0] h07[13:12] RW VS_CD 0 0,1,2,3 H Slicing Level Threshold
CVBSLPBW[1:0] hB4[5:4] RW VS_CD 0 0..3 CVBSLP Bandwidth
CVBSFEBW[1:0] hB4[3:2] RW VS_CD 0 0..3 CVBSFE Bandwidth
PDTHD[1:0] hB4[1:0] RW VS_CD 0 0,1,2,3 AGC Peak Dark Threshold
MINVWIN hB5[15] RW VS_CD 0 0,1 Calculate MINV
THRELIM hB5[14] RW VS_CD 0 0,1 Limit Threshold to MINV
CETHD[1:0] hB5[13:12] RW VS_CD 0 0,1,2,3 Coarse Error Threshold
THRELP[1:0] hB5[11:10] RW VS_CD 0 0..3 Lowpass Coeff for Threshold Value
FECA[1:0] hB5[4:3] RW VS_CD 0 0..3 Fine Error Calculation
PWREDLIM[2:0] hB5[2:0] RW VS_CD 0 0..7 Peak White Reduction Limit
NSREDTHD[1:0] hB6[1:0] RW VS_CD 0 0,1,2,3 Noise Reduction Threshold
100: -4 clock cycles 000: no offset 011: +3 clock cycles
00: 50% 01: 31% 10: 37% 11: 25%
00: very small 01: small 10: wide 11: very wide
00: very small 01: small 10: wide 11: very wide
00: 140 01: 124 10: 104 11: 70
0: every line 1: over 4 lines Note: set to '0' for standard CVBS and '1' for component input
0: no limitation 1: limit
00: +-255 01: +-192 10: +-160 11: +-128
00: very strong 01: strong 10: weak 11: filter off
00: normal syncs 01: short syncs 10: new algorithm 11: fine error disabled
000: 63 001: 48 010: 32 011: 24 100: 16 101: 12 110: 8 111: 4
00: 256 01: 384 10: 512 11: 640
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CIRCUIT DESCRIPTIONS
Table 2–5: New VSP Registers, continued
Name Sub Dir Sync Reset Range Function
COMB
VPM h1F[4] RW VS_COMB00,1 Vertical Peaking Mode
MACROVISION
MVRESULT[1:0] h26[1:0] R VS_CD 0,1, 2, 3 Macrovision Detection
ITU
ITUOUTSTR h55[10] RW VS_ITU 0 0,1 ITU656 Output Pad Strength
Table 2–6: Extended VSP Registers
Name Sub Dir Sync Reset Range Function
CD
AGCMD[1:0] h0B[7:6] RW VS_CD 0 0,1,2,3 AGC Method (ADC1)
I2C
REV[4:0] hFC[4:0] R 1,2,3,4,5,6VCTH Revision
Table 2–7: Wrongly Documented VSP Registers
Name Sub Dir Sync Reset Range Function
ITU
EN_656[1:0] h50[ 1:0] RW VS_ITU 0 0,1,2,3 Enable ITU656 Interface
Table 2–8: Deleted VSP Registers
Sub Data Bits Reset
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
h20 LINELENH50[3:0] LINELENH60[3:0] REM
h21
DEL 2
0: 2H PAL, 1H NTSC (old mode) 1: 1H PAL, 2H NTSC (new mode)
00: nothing present 01: AGC process present and colorstripe process not present 10: AGC process present and colorstripe process type 2 present 11: AGC process present and colorstripe process type 3 present
0: normal 1: weak
00: sync amplitude and peak white 01: sync amplitude only 10: sync amplitude, peak white and peak dark 11: fixed to value AGCADJ1
h01: VCTH-01-01 h02: VCTH-02-01 h03: VCTH-03-01 h04: VCTJ-01-01 h05: VCTJ-02-01 h06: VCTH-04-01
00: input & output disabled
01: output enabled 10: input enabled
11: input & output enabled
VCR-
REM DEL 1
INCOMB[1:0]
DET HD
YCT­COM B
TVM ODE
hC300
Page 72
2.1.3. DPS Part Table 2–9: New DPS Registers
CIRCUIT DESCRIPTIONS
Name Sub Dir Sync Re set Range Function
DEFL
FBOUTEN hD3[0] RW VS_DEFL 0 0,1 FBOUT Enable at PWMV pin
0: PWMV to Port Mux 1: FBOUT to Port Mux
Table 2–10: Undocumented DPS Registers (already available in Dx versions)
Name Sub Dir Sync Re set Range Function
LLPLL
IICINCR[18:3] h00[15:0] RW load_iicincr32768 0..65535 HDTO Increment High
IICINCR[2:0] h01[2:0] RW load_iicincr00..7 HDTO Increment Low
PPLIP[11:0] h02[11:0] RW 1296 0..4095 Pixel per Line Input Processing
ODC
PPLOP[11:0] h17[11:0] RW upd_pplop 1296 0..4095 Pixel Per Line Output
BLE
MINRED h3E[ 13] RW VS_DP 0 0,1 Enable Entropy Adaption
LUMAMIX
LMIXMODE h47[14] RW VS_DP 1 0,1 Luminance Mixer Mode
LMIXCOF[5:0] h47[13:8] RW VS_DP 0 0..63 Luminance Mixer Coefficient
PIXMIX
PATTSIZE h60[11] RW VS_DP 1 0,1 Test Pa ttern Size
controls center frequency of LLPLL
clkhll = IICINCR* 648*10**6/1048576
beclk = clkhll / 8 16384: beclk = 1.27 MHz 174763: beclk = 13.5MHz 262144: beclk = 20.25 MHz 349525: beclk = 27MHz 524287: beclk = 40.5 MHz
must be equal to PPLOP !!!
must be equal to PPLIP !!!
0: entropy adaption off 1: entropy adaption on
0: static mixer 1: amplitude adaptive mixer
static mixer coefficient (used if LMIXMODE=0) 0: 100% peaking ... 63: 100% LTI
0: 720 pixel/line 1: 1080 pixel/line
2.1.4. XDFP Part Table 2–11: New XDFP Registers
Name Sub Dir Sync Reset Range Function
Measurement
HVBLKDIS hF2 h01C2[11] RW 0 0,1 Horizontal & Vertical Blanking Disable
Analog RGB
NEWCALIB hF2 h01DE[11] RW 1 0, 1 New Calibration Method
for compatibility of different MSPH and VCTH versions 0: use old VCTH with new MSPH 1: any other combination
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CIRCUIT DESCRIPTIONS
Table 2–12: Undocumented XDFP Registers (already available in Dx versions)
Name Sub Dir Sync Reset Range Function
Horizontal Deflection
PER_MIN[10:0] hF2 h0183[10:0] RW 1140 0..2047 HS ync Perio d Minimum PER_MAX[10:0] hF2 h0184[10:0] RW 1426 0..2047 HS ync Period Maximu m
2.1.5. TVT Part Table 2–13: Wrongly Documented TVT Registers
Name Addr Dir Reset Range Function
RTC
RTCRW h8F[4] RW 0 0,1 RTC Read/Write RTCSUB[3:0] h8F[3:0] RW 0 0..15 RTC Subaddress
MEMORY
INTSRC0 hE8[5] RW 0 0,1 Interr u pt 0 Source
INTSRC1 hE8[4] RW 0 0,1 Interr u pt 1 Source
PATCH hE8[3] RW 0 0,1 Patch Modul
0: Int0 is source 1: CRT is source
0: Int1 is source 1: CRT is source
0: enable 1: disable
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