Many electrical and mechanical parts in this chassis have special safety-related
characteristics.
These parts are identified by in the Schematic Diagram and Replacement Parts List.
It is essential that these special safety parts should be replaced with the same components
as recommended in this manual to prevent Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
Leakage Current Hot Check (See below Figure)
Plug the AC cord directly into the AC outlet.
Do not use a line Isolation Transformer during this check.
Connect 1.5K/10watt resistor in parallel with a 0.15uF capacitor between a known good earth
ground (Water Pipe, Conduit, etc.) and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter with 1000 ohms/volt or more
sensitivity.
Reverse plug of the AC cord into the AC outlet and repeat AC voltage measurements for each
exposed metallic part. Any voltage measured must not exceed 0.75 volt RMS, which is,
corresponds to 0.5mA.
In case any measurement is out of the limits specified, there is possibility of shock hazard and
the set must be checked and repaired before it is returned to the customer.
Leakage Current Hot Check circuit
SERVICE MANUAL
Page 4
SERVICING PRECAUTIONS
CAUTION!!
Before servicing receivers covered by this service manual, read and follow the SAFETY
PRECAUTIONS on page 2 of this publication.
General Servicing Precautions
1.Always unplug the receiver AC power cord from AC power source before;
ⓐRemoving or reinstalling any component, circuit board module or any other receiver assembly.
ⓑDisconnecting or reconnecting any receiver electrical plug or other electrical connection.
ⓒConnecting a test substitute in parallel with an electrolytic capacitor in the receiver.
CAUTION!! A wrong part substitution or incorrect polarity installation of electrolytic capacitors
may result in an explosion harzard.
2.Do not spray chemicals on or near this receiver or any of its assemblies.
3.Do not defect any plug/socket voltage interlocks with which receivers covered by this service
manual might be equipped.
4.Always connect the test receiver ground lead to the receiver chassis ground before
connecting the test receiver positive lead. Always remove the test receiver ground lead last.
5.Do not connect the test fixture ground strap to power supply heatsink in this receiver
Electrostatically Sensitive(ES) Devices
Some semiconductor(solid state) devices can be damaged easily by static electricity. Such
components commonly are called Electrostatically Sensitive(ES) Device.Examples
Circuit Board Foil Repair
Excessive heat applied to the copper foil of any printed circuit board will weaken the adhesive
that bonds the foil to the circuit board causing the foil th separate from or “lift-off” the board.
The following guidelines and procedures should be flollowed whenever this condition is
encountered.
At IC Connections
To repair a defective copper pattern at IC connections use the following procedure to install a
jumper wire on the copper pattern side of the circuit board.(Use this technique only on IC
connections.)
1.Carefully remove the damaged copper pattern with a sharp knife.
(Remove only as much copper as absolutely necessary.)
2.Carefully scratch away the solder resist and acrylic coating(if used) from the end of the
remaining coopper pattern.
3.Bend a small “U” in one end of a small guage jumper wire and carefully crimp it around the
IC pin.
4.Route the jumper wire along the path of the out-away copper pattern and let it overlap the
previously scraped end of the good copper pattern. Solder the overlapped area and clip off
any excess jumper wire.
SERVICE MANUAL
Page 5
SPECIFICATIONS
Note: Specifications and others are subject to change without notice for improvement.
1.Scope.
This document is the specification of 32” TFT-LCD Color TV.
2.Power
1) Power requirement
150W
2) AC / DC SMPS.
Input Frequency : 50 / 60㎐
Input Voltage: AC 100V- 240V 2.5A ~1.5A
Output Voltage: DC 12V, 24V
3) Power cord
Use UL listed and CSA certified detachable power cord type; SVT, 3-conductors, 18AWG
For AC 120V area. Use VDE listed detachable power cord type; HO5VV-F, 3-conductors,
18AWG for AC 220240V area.~
3.Tuning system
FVS 100 Program
4.Sound output
10W+10Wrms Stereo (Max)
5.Antenna input impedance
VHF / UHF at 75ohm
6.OSD Type (On Screen Display)
Windows type (Center)
7.External in/output
HDMI INPUT, PC ANALOG INPUT, PC AUDIO INPUT, HEADPHONE OUTPUT, SVC port
S-VIDEO AUDIO INPUT, S- VIDEO INPUT, COMPONEN INPUT, COAXIAL OUT,
SCART 1(FULL), SCART 2(HALF), TUNER
8. Function
CATV/Hyper band
Auto Program
Manual Program
Auto Sleep
Quick view
ACMS(Auto channel Memory System)
PSM(Picture Status memory)
SSM(Sound Status memory)
PIP : COMPONET, PC-ANALOG, HDMI(Main) – Tuner, SCART 1, SCART 2, S-Video(Sub)
TUNER, SCART1, SCART2, S-Video(Main) – PC ANALOG, HDMI, COMPONET(Sub)
ARC(ASPECT RATIO CONTROL)
SERVICE MANUAL
Page 6
9.Receiving RF TV system
NO
Model System
1PAL-B
2PAL-G
3PAL-I, I /I
4PAL-D
5PAL-K
6SECAM-B
7SECAM-G
8SECAM-D
9SECAM-K
If the set is cold, there may be a small “flicker” when the set is switched on. This isⓐ
Normal, there is nothing wrong with the set.
If possible, use the XGA 1024 x 768@60HZ video mode ⓑto obtain the best image quality
for your LCD monitor. If used under the other resolutions, some scaled or processed
pictures may appear on the screen.
Some dot defects may appear on the screen, like Red, Green or Blue spot. However, thisⓒ
will have no impact or effect on the monitor performance.
SERVICE MANUAL
Page 8
SPECIFICATIONS
11. TFT – LCD Panel Character
Description
LTA320W2-L03 is a color active matrix TFT(Thin Film Transistor) liquid crystal display(LCD)
that uses amorphous silicon TFTs as a switching devices. This model is composed of a
TFT LCD panel, a driver circuit and a back-light system. The resolution of a 32.0" contains
1366 X 768 pixels and can display up to 16.7 million colors with wide viewing anale of
85˚or higher in all directions.
Features
- High contrast ratio, high aperture structure
- APVA(Advanced Patterned Vertical Align) mode
- Wide verwing anale(±170°)
- High speed response
- WXGA(1366 X 768 pixels) resolution(16:9)
- Low Power consumption
- Dyrect Type 16 CCFL(Cold Cathode Fluorescent Lamp)
4. PC Pattern Generator
1024 x 768, 60Hz
(Pattern Generator : MSPG-3420)
5. Setting : All
SERVICE MANUAL
Page 23
INSPECTION INSTRUCTION
1. Supplied Accessories
Note: Make Sure the following accessories are provided with Product.
SERVICE MANUAL
Page 24
INSPECTION INSTRUCTION
L
2. Packing condition
PACKING BOTTOM
SET FRONT
BOX FRONT
<picture 1> PACKING insert in BOX
ACCESSORY BOX
*
SET FRONT
BOX FRONT
<picture2> SET insert in BOX
PACKING TOP
SET FRONT
SET BACK
SET FRONT
<picture3> Accessory Box insert
1 POINT 1
POINT
SET/BOX FRONT
<Picture 1>Staping <Picture 2>Taping TOP of SET box with OPP TAPE
<picture4> TOP PACKING insert in BOX
2 1 3
SET/BOX FRONT
SERVICE MANUAL
Page 25
NOPART NODESCRIP T I O NMATERKAL CO LOR Q 'T Y
1-LCD CO LO R TV--1
2321-006APOLY VINLYPE-1
3310- 021A ,BPACK ING B OT TOM (L, R)EP SWHITE2
4300-012BSET BO XPAPER-1
5-ACCESSORY--1
6310- 022A , BPA CK I NG T OP (L,R)E P SWHITE2
7499-002AT APE O PP---
The TFT LCD TV described in the followings is based on a Multi TV system, digital
Control display, 26.0" diagonal. The TFT LCD TV is intended to be a finished product,
Basically a display device mounted inside an enclosure which will provide the safety
Requirements. With the exception of LCD Panel, the display device shall be composed
entirely of solid state components.
These components shall have a history of reliable service in identity applications
and shall be applied in the circuits.
1. SCALER SECTION.
2. VCT 49xxi SECTION.
3. Video A/D Converter
SERVICE MANUAL
Page 41
CIRCUIT DESCRIPTIONS
1.SCALER SECTION.
Device : MST5151A
Features: LCD TV controller with PC & multimedia display functions
Input supports up to UXGA & 1080P
Supports up to SXGA panels
Integrated two-port triple-ADC/PLL
Integrated DVI/HDCP/HDMI compliant receiver
YUV422 digital video input ports
Dual high-quality scaling engines
Dual 3-D video de-interlacers
Full function PIP/POP
MStarACE picture/color processing engine
Embedded On-screen display controller (OSD) engine
Digital audio I/O & sync processor
Built-in dual-link LVDS transmitter
5 Volt tolerant inputs
Low EMI and power saving features
Supports PWM & GPO controls
208-pin PQFP package
Analog RGB/YPbPr Input Ports
Dual analog ports support up to 165Mhz
Supports PC RGB input up to UXGA@60Hz
Supports HDTV RGB/YPbPr/YCbCr up to 1080P
On-chip high-performance PLLs
Supports Composite Sync and SOG (Sync-on-Green) separator
Automatic color calibration
DVI/HDCP/HDMI Compliant Input Port
Operates up to 165 MHz (up to UXGA @60Hz)
Single link on-chip DVI 1.0 compliant receiver
High-bandwidth Digital Content Protection
(HDCP) 1.1 compliant receiver
High Definition Multimedia Interface (HDMI)
1.0 compliant receiver with I2S and S/PDIF digital audio outputs
Long-cable tolerant robust receiving
Video Input Port
Two 4:2:2 ITU656 8-bit digital video input ports
One 4:2:2 ITU601 16-bit digital video input port
Supports 16-bit YUV 4:2:2 interlaced/ progressive video input up to 1080i/720P
Auto-Configuration/Auto-Detection
Auto input signal format (SOG, Composite,Separated HSYNC, VSYNC, and DE),
and input mode (all PC & TV modes) detection
Auto-tuning function including phasing, positioning, offset, gain, and jitter detection
Sync Detection for H/V Sync
Dual High-Performance Scaling Engines
Fully programmable shrink/zoom capabilities Nonlinear video scaling supports various modes including Panorama
Video Processing & Conversion
Dual 3-D motion adaptive video de-interlacers with upgraded edge-oriented adaptive
algorithm for smooth low-angle edges
Automatic 3:2 pull-down & 2:2 pull-down detection and recovery
PIP/POP with programmable size and location, supports multi-video applications
Video-over-graphic overlay
MStar 2
On-Screen OSD Controller
nd Generation Advanced Color Engine
SERVICE MANUAL
Page 42
1) Description
The MST5151A is a high performance and fully integrated graphics processing IC solution for multi-function
LCD monitor/TV with resolutions up to SXGA. It is configured with an integrated triple-ADC/PLL, an integrated
DVI/HDCP/HDMI receiver, two video de-interlacers, two high quality scaling engines, an on-screen display
controller, and a built-in output clock generator. By use of external frame buffer, PIP/POP is provided for
multimedia applications. It supports de-interlaced full-screen video, video-on-graphic overlay, split screen,
frame rate conversion, and aspect ratio conversion for various video sources. To further reduce system costs,
the MST5151A also integrates intelligent power management control capability for green-mode requirements
and spread-spectrum support for EMI management.
w/ 5V-tolerant
DBUS[3:0] I/O w/ 5V-tolerant MCU 4-bit DDR Direct bus; 4mA driving strength 75-72
ALE I w/ 5V-tolerant MCU Bus ALE, active high 69
RDZ I w/ 5V-tolerant MCU Bus RDZ, active high 70
WRZ I w/ 5V-tolerant MCU Bus WDZ, active high 71
INT Output MCU Bus Interrupt; 4mA driving strength 68
Hardware Reset, active high 67
Analog Interface
Pin Name Pin Type Function Pin
RMID Mid-Scale Voltage Bypass 38
REFP Internal ADC Top De-coupling Pin 39
REFM Internal ADC Bottom De-coupling Pin 40
REXT Analog Input External Resister 390 ohm to AVDD_DVI 11
HSYNC0 Schmitt Trigger Input
w/ 5V-tolerant
Analog HSYNC Input from Channel 0 36
VSYNC0 Schmitt Trigger Input
w/ 5V-tolerant
BIN0M Analog Input Reference Ground for Analog Blue Input from Channel 0 27
BIN0P Analog Input Analog Blue Input from Channel 0 28
GIN0M Analog Input Reference Ground for Analog Green Input from Channel 0 29
GIN0P Analog Input Analog Green Input from Channel 0 30
SOGIN0 Analog Input Sync On Green Input from Channel 0 31
RIN0M Analog Input Reference Ground for Analog Red Input from Channel 0 32
RIN0P Analog Input Analog Red Input from Channel 0 33
HSYNC1 Schmitt Trigger Input
w/ 5V-tolerant
VSYNC1 Schmitt Trigger Input
w/ 5V-tolerant
BIN1P Analog Input Analog Blue Input from Channel 1 20
BIN1M Analog Input Reference Ground for Analog Blue Input from Channel 1 21
SOGIN1 Analog Input Sync On Green Input from Channel 1 22
GIN1P Analog Input Analog Green Input from Channel 1 23
Analog VSYNC Input from Channel 0 37
Analog HSYNC Input from Channel 1 18
Analog VSYNC Input from Channel 1 19
Page 45
CIRCUIT DESCRIPTIONS
Pin Name Pin Type Function Pin
GIN1M Analog Input Reference Ground for Analog Green Input from Channel 1 24
RIN1P Analog Input Analog Red Input from Channel 1 25
RIN1M Analog Input Reference Ground for Analog Red Input from Channel 1 26
DVI Interface
Pin Name Pin Type Function Pin
DVI_R+ Input DVI Input Channel Red + 207
DVI_R- Input DVI Input Channel Red - 208
DVI_G+ Input DVI Input Channel Green + 2
DVI_G- Input DVI Input Channel Green - 3
DVI_B+ Input DVI Input Channel Blue + 5
DVI_B- Input DVI Input Channel Blue - 60
DVI_CK+ Input DVI Input Clock + 8
DVI_CK- Input DVI Input Clock - 9
Video Interface
Pin Name Pin Type Function Pin
VI_CK Input w/ 5V-tolerant Digital Video Input Clock 66
VI_DATA[15:0] Input w/ 5V-tolerant Digital Video Input Data[15:0] 48-41, 61-54
Digital Audio Interface
Pin Name Pin Type Function Pin
AUMCK Output Audio Master Clock Output 188
AUSD Output Audio Serial Data Output; 4mA driving strength 189
AUSCK Output Audio Serial Clock Output; 4mA driving strength 190
AUWS Output Word Select Output; 4mA driving strength 191
AUMUTE Output Audio Output Mute Control 192
SPDIFO Output S/PDIF Audio Output; 4mA driving strength 193
AIMCK Input Audio Master Clock Input 196
AISD Input Audio Serial Data Input 197
AISCK Input Audio Serial Clock Input 198
AIWS Input Word Select Input 199
Page 46
CIRCUIT DESCRIPTIONS
LVDS Interface
Pin Name Pin Type Function Pin
LVA0M Output A-Link Negative LVDS Differential Data Output 171
LVA0P Output A-Link Positive LVDS Differential Data Output 170
LVA1M Output A-Link Negative LVDS Differential Data Output 169
LVA1P Output A-Link Positive LVDS Differential Data Output 168
LVA2M Output A-Link Negative LVDS Differential Data Output 167
LVA2P Output A-Link Positive LVDS Differential Data Output 166
LVA3M Output A-Link Negative LVDS Differential Data Output 161
LVA3P Output A-Link Positive LVDS Differential Data Output 160
LVACKM Output A-Link Negative LVDS Differential Data Output 165
LVACKP Output A-Link Positive LVDS Differential Data Output 164
LVB0M Output B-Link Negative LVDS Differential Data Output 187
LVB0P Output B-Link Positive LVDS Differential Data Output 186
LVB1M Output B-Link Negative LVDS Differential Data Output 181
LVB1P Output B-Link Positive LVDS Differential Data Output 180
LVB2M Output B-Link Negative LVDS Differential Data Output 179
LVB2P Output B-Link Positive LVDS Differential Data Output 178
LVB3M Output B-Link Negative LVDS Differential Data Output 175
LVB3P Output B-Link Positive LVDS Differential Data Output 174
LVBCKM Output B-Link Negative LVDS Differential Data Output 177
LVBCKP Output B-Link Positive LVDS Differential Data Output 176
MVREF Input Reference Voltage for DDR SDRAM Interface 104
MCLKE Output DRAM Memory Clock Enable 105
MCLKZ Output DRAM Memory clock Complementary /Input
(for differential clocks)
MCLK Output DRAM Memory Clock 107
RASZ Output Row Address Strobe, active low 112
CASZ Output Column Address Strobe, active low 115
WEZ Output Write Enable, active low 116
DQM[1:0] Output Data Mask Byte Enable 101, 133
DQS[3:0] Output Data Strobe 81, 100, 134, 153
BADR[1:0] Output Memory Bank Address 110, 111
MADR[11:0] Output Memory Address 130-127, 124-117
MDATA[31:0] I/O Memory Data 82-85, 88-99,
106
135-138, 141-152
Misc. Interface
Pin Name Pin Type Function Pin
XIN Crystal Oscillator Input Crystal Oscillator Input 203
XOUT Crystal Oscillator Output Crystal Oscillator Output 202
DDCD_DA I/O w/ 5V-tolerant HDCP Serial Bus Data / DDC data of DVI port; 4mA driving
strength
DDCD_CK Input w/ 5V-Tolerant HDCP Serial Bus Clock / DDC Clock of DVI Port 15
BYPASS For External Bypass Capacitor 158
VCTRL Output Regulator Control 62
14
Power Pins
Pin Name Pin Type Function Pin
AVDD_DVI 3.3V Power DVI Power 4, 10
AVDD_ADC 3.3V Power ADC Power 17, 34
AVDD_PLL 3.3V Power PLL Power 12
AVDD_PLL2 3.3V Power PLL Power 109
AVDD_APLL 1.8V Power Audio PLL Power 49
AVDD_MPLL 3.3V Power PLL Power 204
Page 48
CIRCUIT DESCRIPTIONS
Pin Name Pin Type Function Pin
VDDM 3.3V Power (SDR SDRAM) /
2.5V Power (DDR SDRAM)
VDDP 3.3V Power Digital Output Power 66, 162, 182
VDDC 1.8V Power Digital Core Power 63, 79, 131, 156, 173,
The VCT 49xxI is an IC family of high-quality singlechip TV processors. Modular design and deep-submicron technology allow the economic integration of features in all classes of single-scan TV sets. The
VCT 49xxI family is based on functional blocks contained andapproved inexisting productslike
DRX 396xA, MSP 34x5G, VSP 94x7B, DDP 3315C,
and SDA 55xx.
Each member of the family contains the entire IF,
audio, video, display, and deflection processing for 4:3
and 16:9 50/60-Hz mono and stereo TV sets. The integrated microcontroller is supported by a powerful OSD
generator with integrated Teletext & CC acquisition
including on-chippage memory.
Video & Sound IF
DRX 396xA
Audio Processing
MSP 34x5G
Video Processing
VSP 94x7B
VCT 49xyI
Display & Deflection
DDP 3315C
Control, OSD, Text
SDA 55xx
Fig.:Single-chipVCT49xxI
Features
The VCT 49xxI family offers a rich feature set, covering the whole range of state-of-the-ar t 50/60-Hz TV
applications.
– PSSDIP88-1/-2 package
– PMQFP144-2 package
– Submicron CMOS technology
– Low-power standby mode
– Single 20.25-MHz reference crystal
– 8-bit 8051 instruction set compatible CPU
– Up to 256 kB on-chip program ROM
– WST,PDC,VPS,andWSSacquisition
– ClosedCaptionandV-chipacquisition
– Up to 10 pages on-chip teletext memory
– Multi-standard QSS IF processing with single SAW
– FM Radio and RDS with standard TV tuner
– TV-sound demodulation:
• all A2 standards
• all NICAM standards
• BTSC/SAP with MNR (DBX optional)
•EIA-J
– Baseband sound processing for loudspeaker chan-
nel:
• volume
• bass and treble
• loudness
• balance
• spatial effect (e.g. pseudo stereo)
• Micronas AROUND (virtual Dolby optional)
• Micronas BASS
– CVBS, S-VHS, YC
– 4H adaptive comb filter (P AL/NTSC)
– multi-standard color decoder (PAL/NTSC/SECAM)
– Nonlinear horizontal scaling “panorama vision”
– Luma and chroma transient improvement (LTI, CTI)
– Non-linear color space enhancement (NCE)
– Dynamic black level expander (BLE)
– Scan velocity modulation output
– Soft start/stop of H-drive
– Vertical angle and bow correction
– Average and peak beam curr ent limiter
and RGB inputs
rCb
– Nonlinear and dynamic EHT compensation
– Black switch off procedure (BSO)
Page 51
CIRCUIT DESCRIPTIONS
ChipArchitecture
IFIN+
IFIN-
CVBS in
YCrCb in
RGB in
CVBS out
Fig.:BlockdiagramoftheVCT49xxI
IF
Frontend
Video
Frontend
Slicer
24kB
Char ROM
20kB XRAM
Processor
Prog ROM
C
G
A
T
IF
Comb
Filter
Bus
Arbiter
256kB
F
I
S
Decoder
Component
Interface
Sound
Demodulator
Color
Panorama
Display
Generator
CPU
8051
Memory
Interface
ADB, DB, PSENQ,
PSWEQ, WRQ, RDQ
Scaler
T
U
N
O
I
A
A
Audio
Processor
Display &
Deflection
Processor
I2C Master/
Slave
Timer
CRT
PWM
ADC
UART
Watchdog
RTC
I/O-Ports
Pxy
R
E
K
A
E
P
S
PROT
HOUT
HFLB
VERT
Video
Backend
Reset & Test
Logic
Clock
Generator
EW
SVM
RGB out
RGB in
SENSE
RSW
I2C
RESETQ
TEST
XTAL1
XTAL2
Page 52
CIRCUIT DESCRIPTIONS
PinConnectionsandShortDescriptions
NC = not connected
LV = if not used, leave vacant
OBL = obligatory; connect as described in circuit diagram
IN = Input Pin
OUT = Output Pin
SUPPLY = Supply Pin
Pin No.Pin NameTypeConnectionShort Description
PSSDIP
88-pin
1128GNDSUPPLYOBLGround Platform
2129VSUP5.0BESUPPLYOBLSupply Voltage Analog Video Back-end, 5.0 V
3130TESTINGNDTest Input, reserved for Test
4131VERT+OUTLVDifferential Vertical Sawtooth Output
5132VERT-OUTLVDifferential Vertical Sawtooth Output
6133EWOUTLVVertical Parabola Output
PMQFP-2
144-pin
(If not used)
7134RSW2OUTLVRange Switch 2 Output
8135RSW1OUTLVRange Switch 1 Output
9136SENSEINGNDSense ADC Input
10137GNDMINGNDReference Ground for Sense ADC
11138FBININGNDFast Blank Input,Back-end
12139RININGNDAnalog Red Input, Back-end
13140GININGNDAnalog Green Input, Back-end
14141BININGNDAnalog Blue Input, Back-end
15142SVMOUTOUTVSUP5.0BEScan Velocity Modulation Output
16143ROUTOUTVSUP5.0BEAnalog Red Output
17144GOUTOUTVSUP5.0BEAnalog Green Output
181BOUTOUTVSUP5.0BEAnalog Blue Output
192VRDOBLReference Voltage for RGB DACs
203XREFOBLReference Current for RGB DACs
214VSUP3.3BESUPPLYOBLSupply Voltage Analog Video Back-end, 3.3 V
225GNDSUPPLYOBLGround Platform
236GNDSUPPLYOBLGround Platform
247VSUP3.3IOSUPPLYOBLSupply Voltage I/O Ports, 3.3 V
258VSUP3.3DACSUPPLYOBLSupply Voltage Video DACs, 3.3 V
269GNDDACSUPPLYOBLGround Video DACs
2710SAFETYINGNDSafety Input
3139SDAIN/OUTOBLI
3240SCLIN/OUTOBLI
3341P21IN/OUTLVPort 2, Bit 1 Input/Output
3442P20IN/OUTLVPort 2, Bit 0 Input/Output
3543P17IN/OUTLVPort 1, Bit 7 Input/Output
3644P16IN/OUTLVPort 1, Bit 6 Input/Output
3745P15IN/OUTLVPort 1, Bit 5 Input/Output
3846P14IN/OUTLVPort 1, Bit 4 Input/Output
3947P13IN/OUTLVPort 1, Bit 3 Input/Output
4048P12IN/OUTLVPort 1, Bit 2 Input/Output
4149P11IN/OUTLVPort 1, Bit 1 Input/Output
4250P10IN/OUTLVPort 1, Bit 0 Input/Output
4353VSUP3.3FESUPPLYOBLSupply Voltage Analog Video Front-end, 3.3 V
4454GNDSUPPLYOBLGround Platform
4555GNDSUPPLYOBLGround Platform
4656VSUP1.8FESUPPLYOBLSupply Voltage Analog Video Front-end, 1.8 V
4757VOUT3OUTLVAnalog Video 3 Output
4858VOUT2OUTLVAnalog Video 2 Output
4959VOUT1OUTLVAnalog Video 1 Output
5060VIN1INGNDAnalog Video 1 Input
5161VIN2INGNDAnalog Video 2 Input
5262VIN3INGNDAnalog Video 3 Input
5363VIN4INGNDAnalog Video 4 Input
5464VIN5INGNDAnalog Video 5 Input
5565VIN6INGNDAnalog Video 6 Input
5666VIN7INGNDAnalog Video 7 Input
5767VIN8INGNDAnalog Video 8 Input
5868VIN9INGNDAnalog Video 9 Input
Page 54
CIRCUIT DESCRIPTIONS
Pin No.Pin NameTypeConnectionShort Description
PSSDIP
88-pin
5969VIN10INGNDAnalog Video 10 Input
6070VIN11INGNDAnalog Video 11 Input
6198P23IN/OUTLVPort 2, Bit 3 Input/Output
6299P22IN/OUTLVPort 2, Bit 2 Input/Output
63100XTAL2OUTOBLAnalog Crystal Output
64101XTAL1INOBLAnalog Crystal Input
65102VSUP1.8DIGSUPPLYOBLSupply Voltage Digital Core, 1.8 V
66103GNDSUPPLYOBLGround Platform
67104GNDSUPPLYOBLGround Platform
68105VSUP3.3DIGSUPPLYOBLSupply Voltage Digital Core, 3.3 V
69106VSUP5.0IFSUPPLYOBLSupply Voltage Analog IF Front-end, 5.0 V
70107GNDIFSUPPLYOBLGround Analog IF Front-end
71108RESETQIN/OUTOBLReset
72109IFIN+INVREF
73110IFIN-INVREF
74111VREFIFOBLReference Voltage, IF ADC
75112TAGCOUTLVTuner AGC Output
76113AIN1R /
77114AIN1LINGNDAnalog Audio 1 Input, Left
78115AIN2RINGNDAnalog Audio 2 Input, Right
79116AIN2LINGNDAnalog Audio 2 Input, Left
80
81
82121AOUT1ROUTLVAnalog Audio 1 Output, Right
PMQFP-2
144-pin
(If not used)
(main and standby supply)
(main and standby supply)
IF
IF
Input/Output
Differential IF Input
Differential IF Input
SIF
IN/OUTGNDAnalog Audio 1 Input, Right
Analog 2nd Sound IF Output
117AIN3RINGNDAnalog Audio 3 Input, Right
118AIN3LINGNDAnalog Audio 3 Input, Left
119AOUT2ROUTLVAnalog Audio 2 Output, Right
120AOUT2LOUTLVAnalog Audio 2 Output, Left
AIN3R /
AOUT2R
AIN3L /
AOUT2L
IN /
OUT
IN /
OUT
LVAnalog Audio 3 Input, Right
Analog Audio 2 Output, Right
LVAnalog Audio 3 Input, Left
Analog Audio 2 Output, Left
83122AOUT1LOUTLVAnalog Audio 1 Output, Left
84123SPEAKERROUTLVAnalog Loudspeaker Output, Right
Page 55
CIRCUIT DESCRIPTIONS
Pin No.Pin NameTypeConnectionShort Description
PSSDIP
88-pin
85124SPEAKERLOUTLVAnalog Loudspeaker Output, Left
86125VREFAUOBLReference Voltage, Audio
87126VSUP8.0AUSUPPLYOBLSupply Voltage Analog Audio, 8.0 V
88127GNDSUPPLYOBLGround Platform
PMQFP-2
144-pin
(If not used)
71P37 /
656IO7
72P36 /
656IO6
73P35 /
656IO5
74P34 /
656IO4
IN/OUTLVPort 3, Bit 7 Input/Output
Digital 656 Bus 7 Input/Output
IN/OUTLVPort 3, Bit 6 Input/Output
Digital 656 Bus 6 Input/Output
IN/OUTLVPort 3, Bit 5 Input/Output
Digital 656 Bus 5 Input/Output
IN/OUTLVPort 3, Bit 4 Input/Output
Digital 656 Bus 4 Input/Output
75P33 /
656IO3
76GNDEIOSUPPLYOBLGround Extended I/O Ports
IN/OUTLVPort 3, Bit 3 Input/Output
Digital 656 Bus 3 Input/Output
77VSUP3.3EIOSUPPLYOBLSupply Voltage Extended I/O Ports, 3.3 V
78P32 /
656IO2
79P31 /
656IO1
IN/OUTLVPort 3, Bit 2 Input/Output
Digital 656 Bus 2 Input/Output
IN/OUTLVPort 3, Bit 1 Input/Output
Digital 656 Bus 1 Input/Output
80P30 /
656IO0
81P26 /
656VIO
82P25 /
656HIO
83P24 /
656CLKIO
IN/OUTLVPort 3, Bit 0 Input/Output
Digital 656 Bus 0 Input/Output
IN/OUTLVPort 2, Bit 6 Input/Output
Digital 656 Vsync Input/Output
IN/OUTLVPort 2, Bit 5 Input/Output
Digital 656 Hsync Input/Output
IN/OUTLVPort 2, Bit 4 Input/Output
Digital 656 Clock Input/Output
31ADB19OUTLVAddress Bus 19 Output
21ADB18OUTLVAddress Bus 18 Output
19ADB17OUTLVAddress Bus 17 Output
22ADB16OUTLVAddress Bus 16 Output
23ADB15OUTLVAddress Bus 15 Output
18ADB14OUTLVAddress Bus 14 Output
17ADB13OUTLVAddress Bus 13 Output
26ADB12OUTLVAddress Bus 12 Output
14ADB11OUTLVAddress Bus 11 Output
Page 56
CIRCUIT DESCRIPTIONS
Pin No.Pin NameTypeConnectionShort Description
PSSDIP
88-pin
PMQFP-2
144-pin
96ADB10OUTLVAddress Bus 10 Output
15ADB9OUTLVAddress Bus 9 Output
(If not used)
16ADB8OUTLVAddress Bus 8 Output
27ADB7OUTLVAddress Bus 7 Output
28ADB6OUTLVAddress Bus 6 Output
29ADB5OUTLVAddress Bus 5 Output
30ADB4OUTLVAddress Bus 4 Output
84ADB3OUTLVAddress Bus 3 Output
85ADB2OUTLVAddress Bus 2 Output
86ADB1OUTLVAddress Bus 1 Output
87ADB0OUTLVAddress Bus 0 Output
88DB0IN/OUTLVData Bus 0 Input/Output
89DB1IN/OUTLVData Bus 1 Input/Output
90DB2IN/OUTLVData Bus 2 Input/Output
91DB3IN/OUTLVData Bus 3 Input/Output
92DB4IN/OUTLVData Bus 4 Input/Output
93DB5IN/OUTLVData Bus 5 Input/Output
94DB6IN/OUTLVData Bus 6 Input/Output
95DB7IN/OUTLVData Bus 7 Input/Output
32RDQOUTLVData Read Enable Output
33WRQOUTLVData Write Enable Output
34OCFOUTLVOpcode Fetch Output
35ALEOUTLVAddress Latch Enable Output
36RSTQOUTLVInternal CPU Reset Output
97PSENQOUTLVProgram Store Enable Output
20PSWEQOUTLVProgram Store Write Enable Output
51XROMQINOBLExternal ROM Enable Input
52EXTIFQINLVEnable External Interface Input
24STOPQINLVStop CPU Input
25ENEQINLVEnable Emulation Input
Page 57
CIRCUIT DESCRIPTIONS
CIRCUIT DESCRIPTIONS
CIRCUIT DESCRIPTIONS
CIRCUIT DESCRIPTIONS
CIRCUIT DESCRIPTIONS
PinDescriptions
SupplyPins
VSUP1.8DIG
This pin is main and standby supply for the digital core
logic of controller, video, display and deflection processing.
VSUP1.8FE − Supply Voltage 1.8 V
This pin is main supply for the analog video front-end.
VSUP3.3FE − Supply Voltage 3.3 V
This pin is main supply for the analog video front-end.
VSUP3.3IO − Supply Voltage 3.3 V
This pin is main and standby supply for the digital I/Oports.
VSUP3.3DIG − Supply Voltage 3.3 V
This pin is main supply for the digital core logic of IF
and audio processing and digital video back-end.
VSUP3.3BE − Supply Voltage3.3 V
This pin is main supply for the analog video back-end.
VSUP5.0BE − Supply Voltage5.0 V
This pin is main supply for the analog video back-end.
VSUP8.0AU − Supply Voltage 8.0 V
This pin is main supply for the analog audio processing.
GND − Ground Platform
This pin is main ground for all above supplies.
VSUP3.3DAC − Supply Voltage 3.3 V
This pin is main supply for the video DACs.
GNDDAC − Ground for 3.3 V Video DAC Supply
VSUP5.0IF − Supply Voltage 5.0 V
This pin is main supply for the analog IF front-end.
GNDIF − Ground for 5.0 V IF Supply
VSUP3.3EIO − Supply Voltage 3.3 V
This pin is main and standby supply for the extended
digital I/O-ports available in QFP package only. It is
internally connected to
GNDEIO
It is internally connected to GND.
Application Note:
All GND pins must be connected to a low-resistive
ground plane underneath the IC. All supply pins must
be connected separately with shor t and low-resistive
lines to the power supply. Decoupling capacitors from
VSUPxx to GND have to be placed as closely as pos-
sible to these pins. It is recommended to use more
− Supply Voltage 1.8 V
VSUP3.3IO.
− Ground for 3.3 V Extended I/O Supply
than one capacitor. By choosing different values, the
frequency range of activedecoupling can be extended.
IFPins
VREFIF
This pin must be connected to
according to the application circuit. Low inductance
caps are necessary.
IFIN+, IFIN- − Balanced IF Input (Fig. 4–6)
These pins must be connected to the SAW filter output. The SAW filter hastobeplaced as close as possible. The layout of the IF input should be symmetrical
with respect to
SIF − 2nd Sound IF Output (Fig. 4–8)
Output level is set via I
processor (e.g. MSP) can be connected to this pin.
This pin is also configurable as audio input (see
Fig. 4–10).
TAGC − Tuner AGC Output (Fig. 4–7)
This pin controls the delayed tuner AGC. As it is a
noise-shaped-I-DAC output, it has to be connected
according to the applicationcircuit.
AudioPins
VREFAU
4–14)
This pin serves as the internal ground connection for
the analog audio circuitry. It must be connected to the
GND pinwitha3.3µF and a 100 nF capacitor in paral-
lel. This pins shows a DC level of typically 3.77 V.
AIN1 L – Audio 1 Inputs (Fig. 4–10)
The analog input signal for audio 1 is fed to this pin.
Analog input connection must be AC coupled.
AIN1 R – Audio 1 Inputs (Fig. 4–10)
The analog input signal for audio 1 is fed to this pin.
Analog input connection must be AC coupled. This pin
is also configurable as sound IF output (see Fig. 4–8).
AIN2 R/L – Audio 2 Inputs (Fig. 4–10)
The analog input signal for audio 2 is fed to this pin.
Analog input connection must be AC coupled.
AIN3 R/L – Audio 3 Inputs (Fig. 4–10)
The analog input signal for audio 3 is fed to this pin.
Analog input connection must be AC coupled.
− Reference Voltage for Analog IF (Fig. 4–9)
GNDIF via a circuitry
GNDIF.
2
C-Bus. An appropriate sound
– Reference Voltage for Analog Audio (Fig.
Page 58
GeneralDescription
CIRCUIT DESCRIPTIONS
AOUT1 R/L – Audio 1 Outputs (Fig. 4–11)
Output of the analog audio 1 signal. Connections to
these pins are intended to be AC coupled.
AOUT2 R/L – Audio 2 Outputs (Fig. 4–11)
Output of the analog audio 2 signal. Connections to
these pins are intended to be AC coupled.
SPEAKER R/L – Loudspeaker Outputs (Fig. 4–13)
Output of the loudspeaker signal. A 1 nF capacitor to
GND must be connected to these pins. Connections to
these pins are intended to be AC-coupled.
VideoPins
VIN 1–11
These are the analog video inputs. A CVBS, S-VHS,
YCrCb or RGB/FB signal is converted using the luma,
chroma and component AD converters. The input signals must be AC-coupled by 100nF. In case of an analog fast blank signal carryingalphablending information
the input signal must be DC-coupled.
VOUT 1-3 − Analog Video Output (Fig. 4–16)
The analog video inputs that are selected by the video
source select matrix are output at these pins.
− Analog Video Input (Fig.4–15)
RIN, GIN, BIN − Analog RGB Input (Fig. 4–17)
These pins are used to insert an external analog RGB
signal, e.g. from a SCART connector which can be
switchedto the analogRGB outputswith the fastblank
signal. Separate brightness and contrast settings for
the external analog signals are provided.
FBIN − Fast Blank Input (Fig. 4–18)
This pin is used to switch the RGB outputs to the external analog RGB inputs. The active level (low or high)
can be selected by software.
ROUT, GOUT, BOUT − Analog RGB Output (Fig. 4–
19)
These pins are the analog Red/Green/Blue outputs of
the back-end. The outputs are current sinks.
SVMOUT − Scan Velocity Modulation Output (Fig. 4–
19)
This output delivers the analog SVM signal. The D/A
converter is a current sink like the RGB D/A converters. At zero signal the output current is 50% of the
maximum output current.
VRD − DAC Reference Decoupling (Fig. 4–20)
Via this pin the RGB-DAC reference voltage is decoupled by an external capacitor. The DAC output currents depend on this voltage, therefore a pulldown
transistor can be used to shut off all beam currents. A
decoupling capacitor of 4.7 µF in parallel to 100 nF
(low inductance) is required.
XREF − DAC Current Reference (Fig. 4–20)
External reference resistor for DAC output currents,
typical 10 kΩ to adjust the output current of the D/A
converters. (see recommended operating conditions).
This resistor has to be connected to ground as closely
as possible to the pin.
CRTPins
VPROT
The vertical protection circuitry prevents the picture
tube from burn-in in the event of a malfunction of the
vertical deflection stage. If the peak-to-peak value of
the sawtooth signal from the vertical deflection stage is
too small, the RGB output signals are blanked.
SAFETY − Safety Input (Fig. 4–22)
This input has two thresholds. A signal between the
lower and upper threshold means normal function. A
signal below the lower threshold or above the upper
threshold is detected as malfunction and the RGB signals will be blanked.
HOUT − Horizontal Drive Output (Fig. 4–21)
This open source output supplies the drive pulse for
the horizontal output stage. An external pulldown
resistor has to be used. The polarity and gating with
the flyback pulse are selectable by software.
HFLB − Horizontal Flyback Input (Fig. 4–22)
Via this pin the horizontal flyback pulse is supplied to
the VCT 49xxI.
VERT+, VERT−−Vertical Sawtooth Output (Fig. 4–23)
These pins supply the symmetrical drive signal for the
vertical output stage. The drive signal is generated
with 15-bit precision. The analog voltage is generated
by a 4 bit current-DAC with an external resistor of
6.8 kΩ and uses digital noise shaping.
EW − East-West Parabola Output (Fig. 4–24)
This pin supplies the parabola signal for the East-West
correction. The drive signal is generated with 15 bit
precision. The analog voltage is generated by a 4 bit
current-DAC with an external resistor of 6.8 kΩ and
uses digital noise shaping.
PWMV − PWM Vertical Output (Fig. 4–35)
This pin provides an adjustable vertical parabola with 7
bit resolution and appr. 79.4 kHz PWM frequency.
This pin supplies the blank pulse for dynamic focus
during vertival blanking period or a free programmable
horizontal pulse for horizontal dynamic focus generation.
− Vertical Protection Input (Fig. 4–22)
Page 59
GeneralDescription
CIRCUIT DESCRIPTIONS
SENSE − Measurement ADC Input (Fig. 4–27)
This is the input of the analog to digital converter for
the picture and tube measurement. Three measurement ranges are selectable with RSW1 and RSW2.
GNDM − Meas urement ADC Reference Input
This is the reference ground for the measurement A/D
converter. Connect this pin to GND.
RSW1 − Range Switch1 for Measuring ADC (Fig. 4–
25)
These pin is an open drain pulldown output. During
cutoff and white drive measurement the switch is off.
Duringtherestoftimeitison.TheRSW1pincanbe
used as second measurement ADC input for picture
beam current measurement.
RSW2 − Range Switch2 for Measuring ADC (Fig. 4–
26)
These pin is an open drain pulldown output. During
cutoff measurement the switch is off. During white
drive measurement the switch is on. Also during the
rest of time it is on. It is used to set the range for white
drive current measurement.
ControllerPins
XTAL1
4–28)
These pins connect a 20.25 MHz crystaltothe internal
oscillator. An external clock can be fed into XTAL1.
− Crystal Input and XTAL2 Crystal Output (Fig.
RESETQ − Reset Input/Output (Fig. 4–29)
A low level on this pin resets the VCT 49xxI. The internal CPU can pull down this pin to reset external
devices connected to this pin.
TEST − T est Input (Fig. 4–30)
This pin enables factorytest modes. For normal operation, it must be connected to ground.
SCL − I
This pin delivers the I
be pulled down by external slave ICs to slow down
data transfer.
SDA − I
This pin delivers the I
2
C Bus Clock (Fig. 4–31)
2
C bus clock line. The signal can
2
C Bus Dat a(Fig. 4–31)
2
C bus data line.
P10−P13, P20−P23 − I/O Port (Fig. 4–32)
These pins provide CPU controlled I/O ports.
P14−P17 − I/O Port (Fig. 4–33)
These pins provide CPU controlled I/O ports. Additionally they can be used as analog inputs for the controller ADC.
P24−P26, P30−P37 − I/O Port (Fig. 4–34)
These pins provide CPU controlled I/O ports.
ADB0−ADB19 − Address Bus Output (Fig. 4–35)
These 20 lines provide the CPU address bus output to
access external memory.
DB0−DB7 − Data Bus Input/Output (Fig. 4–36)
These 8 lines provide the bidirectional CPU data bus
to access external memory.
WRQ − Data Write Enable Output (Fig. 4–35)
This pin controls the direction of data exchange
between the CPU and the external data memory
device (SRAM).
RDQ − Data Read Enable Output (Fig. 4–35)
Thispinisusedtoenabletheoutputdriverofthe
external data memory device (SRAM) for read access.
PSENQ − Program Store Enable Output (Fig. 4–35)
Thispinisusedtoenabletheoutputdriverofthe
external program memory device (ROM/FLASH) for
read access.
PSWEQ − Program Store Write Enable Output (Fig. 4–
35)
This pin is used to write into the externalprogram flash
memory device.
XROMQ − External ROM Enable Input (Fig. 4–37)
This pin must be pulled low to access the external program memory.
tor.
EXTIFQ − Enable External Memory Interface Input
(Fig. 4–37)
This pin must be pulled low to enable the external
memory interface.
resistor.
STOPQ − Stop CPU Input (Fig. 4–37)
Applying a lowlevel during the inputphase freezes the
realtime relevant internal peripherals such as timers
and interrupt controller.
resistor.
ENEQ − Enable Emulation Input (Fig. 4–37)
Only if this pin is set tolow level, STOPQ and OCF are
operational.
ALE − Address Latch Enable Output (Fig. 4–35)
This signal indicates changes on the address bus.
OCF − Opcode Fetch Output (Fig. 4–35)
A high level driven by the CPU during output phase
indicates the beginning of a new instruction.
RSTQ − Internal CPU Reset Input/Output (Fig. 4–38)
This pin is used for emulation purpose only. A low level
on this pin resets the CPU. It also indicates an internal
reset of the CPU.
Changes to the previous revision are indicated by change bars. Please note section 2.1.1.2., which is of importance
for the use of the VCT-I F1 in combination with NICAM-audio modes.
1. VCT 49xyI Version History
1.1. Field Problems
Field test results are available for the VCT 49xyI versions C7 to D5. The versions F1 and F2 are intended to solve all
listed field problems.
Table 1–1: History of field problems
No.Field ProblemC7D2D4D5F1F2Comment
FP01 Streaky NoisexxxxProblem solved in F1
FP02 Modulator Imbalance
xxxxProblem solved in F1
FP03 FM Modulation
FP04 Color ClippingxxxxxProblem to be solved in F2
FP05 Closed Caption Performance
FP06 VSP-AGC performance
FP07 Sync/H-PLL performancexxxxxProblem to be solved in F2
xxxxProblem solved in F1
xxxxProblem to be solved in F1
xxxxxProblem to be solved in F2
1.2. Functional Problems
For a more detailed description and workarounds of the functional problems please refer to the list of the particular
VCT 49xyI version in the next sections. The problem numbers are consistent throughout the whole document. The
versions F1 and F2 are intended to solve the remaining problems.
Table 1–2: History of functional problems
No.Functional ProblemC6C7D2D4D5F1F2Comment
18Vertical Synchronisation
xxProblem solved in D2
Additional Info for VCT49xyI
VCT49xyI
6251-573-1AI, Edition Feb. 18, 2004
Version History
Dec. 16, 2004
26Picture Frame Blanked
34Reset after ReadxxProblem solved in D2
xxProblem solved in D2
Page 62
CIRCUIT DESCRIPTIONS
Table 1–2: History of functional problems, continued
No.Functional ProblemC6C7D2D4D5F1F2Comment
39Peaking FilterxxProblem solved in D2
40Bandwidth of Antialias Filter
xxProblem solved in D2
41SVM OverflowxxProblem solved in D2
42ADC Ini tia lis at ion
43a) Clock Noise
b) IF-Nonlinearity
xxProblem solved in D2
!!!!!!!! = Applicative methods
solve the problem to a
large extent
xxx
*)
xxx
*)
slight degradation in
comparison to C6/7, D4/5.
Problem to be solved in F2
45DRX Video-DAC Headroom
46HORPOS changes color multi-
Detection for EIA-J
54MSP Standard Toggle in HDEV-
Mode fails
xxxProblem solved in D4
xxxProblem solved in D4
!!!Problem appeared in D2,
Problem solved in F1
! = workaround available
xxProblem appeared in D2,
Problem solved in D5
55OSD Offset Compensation
56ESD Induced Reset
57White Blanking Line in OSD
xxxxxProblem solved in F1
!!!Problem appeared in D2,
Problem solved in F1
! = workaround available
!!!!!Problem solved in F1
! = workaround available
58EHT
!!!Problem appeared in D2,
Problem solved in F1
! = workaround available
60VCR detection “TVMODE”
61Vertical flywheel mode
(VFLYWHLMD)
xx!!!!!! = Workaround available
no redesign planned
!!!!!!!! = Workaround available
no redesign planned
62BLE
!!!!!Problem solved in F1
! = workaround available
Page 63
CIRCUIT DESCRIPTIONS
Table 1–2: History of functional problems, continued
No.Functional ProblemC6C7D2D4D5F1F2Comment
63ODC-Modes: FHPULLIN/
64Safety Pin
6513.5MHz Backend Mode
SHPULLIN
66ITU656 Interference
67Audio EIA-J: Plop from stereo to
68BSO
mono
69H-Out Jitter!!xxxProblem solved in F1
70SCE Luma Input
71YUV ECO Mode
72Scaler Bondoption
73FM rad io not working
74ITU656 Biterror
!!!!!!!! = Workaround available
no redesign planned
xxxxxProblem solved in F1
--xxx- = new feature in D2,
Problem solved in F1
--xxx- = new feature in D2,
Problem solved in F1
xxxxxxunder investigation
Problem to be solved in F2
xxxxxProblem solved in F1
! = workaround available
--xxx- = new feature in D2,
Problem solved in F1
xxxxxProblem solved in F1
xxxxxProblem solved in F1
!Problem appeared in F1,
Problem to be solved in F2
! = workaround available
xProblem appeared in F1,
Problem to be solved in F2
Page 64
CIRCUIT DESCRIPTIONS
7. VCT49xyI-C7
The VCT 49xyI-C7 is pin-compatible to VCT 49xyI-C6 and VCT 49xyI-C4.
Problem 45 has been solved. Problem 43 is partly solved: Improved internal clock suppression leads to reduced
noise floor and better video snr. Problems 53 and 54 have not been detected before D2.
VCT 49xyI-C7 includes functionality of DRX396xA-H8.
Table 7–1: Functional problems of VCT 49xyI-C7:
No.ProblemDescriptionCommentOK
18Vertical Synchr oni sa -
tion
26Picture Frame BlankedLeft side of picture frame is blanked
34Reset after ReadAll I2C register with "reset by read"
39Peaking FilterIn case of PKCF=2,3, the dynamic
40Bandwidth of Antialias
Filter
41SVM OverflowThe SVM output signal is not lim-
42ADC InitialisationWrong initialisation of RGB ADCs
43Clock NoiseInduced harmonics of the system
46HORPOS changes
color multiplex
47Preframe GeneratorThe preframe generator cannot
Vertical pull-in after channel
change takes too long
if HORPOSG<180.
are not functional (NMSTATUS,
LBDSTATUS, FBLACTIVE,
FBFALL, FBRISE, PFBL/G/R/B).
peaking adaption doesn’t work.
Thus the peaking signal is limited
only.
The bandwidth adjustment of the
antialias filter 1-6 is disturbed. This
causes wrong filter settings after
reset and/or after a modification of
TRIM_FILTER1-6
ited correctly over the full range of
SVLIM.
after power-on causes color mismatch.
clock generate visible interf erenc e
on weak IF input signals.
When picture is shifted to the right
via HORPOS the color multiplex is
inverted.
signal jumps above top level, AGC
hangup may occur and CVBS output level is reduced.
53MSP Automatic Stan-
dard Detection
Automatic standard detection fails,
if EIA-J is selected as preferred
4.5MHz-sound carrier.
54MSP Standard Toggle
in HDEV-Mode fails
T oggling between S tandard 3 and 8
while Mod_HDEV_A = 1 leads to
occasional sound impairments
firmware redesign D1
workaround:
KI_CHANGE_TH = 19 after stan-
dard change
firmware redesign D4
workaround:
avoid Mod_4_5MHz[1:0]=[1,0]. If
Mod_ASS and Mod_Dis_Std_Chg
= 1, EIA-J is detected anyhow
firmware redesign D4
workaround: not available
D2
D4
D4
Page 66
CIRCUIT DESCRIPTIONS
2. VCT49xyI-F1
The VCT 49xyI-F1 is targeted to solve field and functional problems of the earlier VCT-I versions. For that purpose
some new registers were implemented. In addition workarounds used for VCT-I versions prior to F1 may not be
compatible.
The VCT 49xyI-F1 is pin-compatible to VCT 49xyI-D5.
Functional problems 50, 56, 57 and 58, 62, 64, 65, 66, 68, 69, 70, 71 have been solved. Problem 55 has been
solved but requires software initialisation. Field problems FP01, FP02 and FP03 have been solved, FP06 and FP07
are still under inverstigation. New features F19 and F20 have been successfully implemented.
Table 2–1: New features of VCT 49xyI-F1:.
No.FeatureDescriptionOk
F19Vertical PeakingAdditional mode for vertical peaking in 4H-combfilter allows switching
F20Fastblank OutputThe fastblank signal of the TVT display generator is availbale as output
Table 2–2: Field problems of VCT 49xyI-F1:
No.ProblemDescriptionCommentOk
FP06 VSP-AGC performance Poor performance with some non
FP07 Sync/H-PLL perfor-
Table 2–3: Functional problems of VCT 49xyI-F1:
No.ProblemDescriptionCommentOk
73FM Radio not workingroot causes:
74ITU656 BiterrorBit errors on ITU656 output data
mance
between 2H and 1H peaking filter. See new register VPM in section
2.1.2.
signal for LCD-Scaler applications. It can be programmed to the pin
PWMV, P11 and P21.
hardware redesign in F2
standard signals
Poor performance with some VCR
tapes
a) fast carrier recovery is automatically always ON, but should be
OFF for FM-Radio mode
b) When switching to FM-Radio
mode the output frequency sometimes will not be set correctly
produce noisy and unstable picture.
hardware redesign in F2
firmware redesign F2
workaround: s. 2.1.1.4. W3 & W4
metal fix F1
no workaround available
F1
F1
F2
Page 67
CIRCUIT DESCRIPTIONS
2.1. Register Changes on VCT 49xyI-F1
2.1.1. DRX Part
The major improvement of the VCT 49xyI-F1 DRX-performance is based on the speed up of the Tuner-AGC, the
Video AGC and the Carrier Recovery. While the faster Tuner and Video AGC help to improve significantly the
Streaky Noise and Airplane Flutter issues, the extended Carrier Recovery removes all remaining field test matters.
Although the fast modes are activated by default, some new registers are introduced to enable the configuration of
the modified functions if necessary.
Table 2–4: New DRX Registers
NameSubAddrDirResetRangeFunction
Advanced Settings
MOD_ACCU_BS[9:0]h10h100E[10:1]RW0-512..511Modulator imbalance value
MOD_UPDATEh10h100E[0]W00,1Update modulator imbalan c e
MOD_TH[3:0]h10h100F[11:8]W50..15Imbalance control threshold
MOD_MODEh10h100F[7]W10,1Imbalance Control estimation mode
MOD_If[3:0]h10h100F[6:3]W60..15Imbalanc e control integral part (falling)
MOD_Ir[2:0]h10h100F[2:0]W10..7Imbalance control integral part (rising)
NOISE_BS[3:0]h10h1013[3:0]W150..15Maximum deviation for noise reduction
PHAC_BPh10h1015[9]W00,1Phase correction bypass
FAST_VAGC_ENh10h1023[8]W10,1Enable Fast VAGC
COMP_DC_MUX[2:0]h10h10B3[11:9]W70..7Multiplexer for DC estimation during compensation
COMP_FREQ_BS[8:0]h10h10B3[8:0]W930..511Increment for reference signal generation
Firmware
BP_KI_MIN_BS[5:0]h10h10A5[5:0]W210..63Minimum KI setting
2.1.1.1. Comments to the Tuner and Video-AGCs
The fast mode of the Video AGC is enabled by default and can be switched off by FAST_VAGC_EN = 0. Nevertheless, switching off this new AGC is not recommended.
In earlier versions the VAGC_KI and TAGC_KI values had to be continuously updated to prevent the adaptive KI
control from setting them too low. In the new version a minimum limit register is implemented: BP_KI_MIN_BS
allows to determine the minimum allowed KIs.
For example : BP_KI_MIN_BS = 0x15 means: TAGC_KI must not be lower than 2 and VAGC_KI must not be lower
than 5.
Write:set manual imbalance value (with MOD_IF=0,
MOD_IR=0, for take-over set MO D_UPDATE=1)
Read:compensated imbalance value
1: write Modulator imbalance value into hardware
Selects the edge sensitivity
0: trigger estimation on rising edges
1: trigger estimation on rising and falling edges
The control uses this value for decreasing i mbalance
The control uses this value for increasing imbalance
0: active phase correction
1: byp ass phase correction
0: Fast VAGC disabled
1: Fast VAGC enabled
The reference signal is attenuated with the following filter
H(z) = 0.5*(1+z^-(4+COMP_DC_MUX)) @fs=40.5MHz
TAGC_KI and VAGC_KI will not be set
below this values
BP_KI_MIN_BS is set to 0x15 by default. Should there be a need for further improving Streaky Noise, 0x16 or 0x17
can be user selected. With the new algorithm VAGC_KI = 6 or 7 are also stable settings and do not produce any
stripes.
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CIRCUIT DESCRIPTIONS
All controller software workarounds used at former versions which write the KIs will no longer be needed and should
be removed (see also next section).
2.1.1.2. Comments to the Carrier Recovery in Connection with NICAM Audio Performance
The speed up of the carrier recovery to optimize the performance at non standard RF signals (caused by FM modulation and modulator imbalance) is mainly based on a significant extension of the PLL-bandwith. However as a matter of principle any extension of the PLL bandwith increases the system noise sensitivity.
Since the NICAM audio system is basically highly sensitive to phase noise, the fast carrier recovery may reduce the
NICAM sensitivity, depending on the RF-signal condition. To avoid any reduction of the NICAM sound quality it is
recommended to switch off th e carrier recovery speed up in case of NICAM reception setting the register
to 1 (see also section 2.1.1.4., WP5).
2.1.1.3. Status of VCT 49xyI-F1 and how to deal with currently used workarounds
The following table gives recommendations how to deal with workarounds used at C7/Dx:
No.ProblemCountriesWorkaround
FP1 Streaky NoiseKoreaT1-Coefficients for M/N
for C7 / Dx
Speed up DRX video AGC:
- write VAGC_KI=5 every
20ms
FP2 Modulator Imbal-
ance
Korea,
China,
Thailand,
Brazil
- write TAGC_KI=2 every
20ms
Adaptively
(AFC_LOCK_QUAL):
- CR_AMP_TH 16 -> 64
FP3 FM ModulationIndia,
Flicker, Airplane
Flutter
RC: default AGC
setting too slow
Vietnam
Pakistan,
Korea
Asia,
France,
Czech
Adaptively (NLPFLD):
- CLMPST1 28 -> 45
- CLMPD1 11-> 3
- CR_P 3-> 4
Speed up DRX video AGC:
- write VAGC_KI=5 every
20ms
- write TAGC_KI=2 every
20ms
PHAC_BP
Side-Effect Status in F1Recommen-
dation for F1
Could not
solve problem completely
Reduced
FM
sound S/N
Could not
solve problem completely
SW code
overhead
adaptive
functionality not
usablex
significantly
improved
significantly
improved
significantly
improved
significantly
improved,
previously
forced va lues now
default
remove WA
remove WA
remove WA
remove WA
Page 69
CIRCUIT DESCRIPTIONS
No.ProblemCountriesWorkaround
Hsync DistortionMalaysiaSpeed up DRX video AGC:
Color Sensitivity,
bar edge distortion
RC: default
NOISE_BS=15
too high
India,
Malaysia
for C7 / Dx
- KI_CHANGE_TH=1
- VAGC_REDUC=1
Reduce NOISE_BS to 8
(partly adaptively when
chroma level is small)
Side-Effect Status in F1Recommen-
dation fo r F1
nonepreviously
forced values now
default
Measured
Video S/N
1-2dB
smaller
unchanged
(0xF still
default)
remove WA
keep WA
2.1.1.4. Recommended Workarounds for VCT 49xyI-F1
Although the field problems have been fixed successfully, there are recommendations for specific input-signals.
Please consider the following table.
No.IssueWorkaround for F1Side-EffectPlan for F2
W1Imbalance control can cause prob-
lems when changing from high to
low RF signal levels
W2MOD_ACCU_BS must be written
several times until value is accepted
W3FM radio not working; root cause:
fast carrier recovery is automatically
ON in FM radio mode, should be
OFF
W4When switching to FM-Radio mode
the output frequency sometimes will
not be set correctly
W5Reduction of NICAM sensitivity at
weak RF signal conditions
If TAGC_I = 0:
- set MOD_Ir = 0
- set MOD_If = 0
- write MOD_ACCU_BS = 0
(consider also W2)
Write MOD_ACCU_BS until readback
value matches written value (remember
that MOD_UPDATE has to be 1 for writing MOD_ACCU_BS)
Set PHAC_PB to 1 in FM radio mode
only, to 0 in TV modes
Repeat switching to FM-Radio mode
and subsequently read out AFC_DEV
until the value is 0
Set PHAC_PB to 1 in NICAM audio
mode
noneunder inves-
tigation
nonefirmware
redesign
nonefirmware
redesign
nonefirmware
redesign
noneunder inves-
tigation
Page 70
2.1.2. VSP Part
Table 2–5: New VSP Registers
CIRCUIT DESCRIPTIONS
NameSubDirSyncResetRangeFunction
CD
LPCDEL[2:0]h07[2:0]RWVS_CD0-8..7Window Shift For Fine Error Calculation
00: nothing present
01: AGC process present and colorstripe process not
present
10: AGC process present and colorstripe process type 2
present
11: AGC process present and colorstripe process type 3
present
0: normal
1: weak
00: sync amplitude and peak white
01: sync amplitude only
10: sync amplitude, peak white and peak dark
11: fixed to value AGCADJ1