查询CAT5132GZ-100TE13供应商
15 Volt Digitally Programmable Potentiometer (DPP™)
with 128 Taps and 2-wire Interface
CAT5132
FEATURES
■ Single linear Digitally Programmable Potentiometer
■ 128 Resistor taps
ΩΩ
■ End-to-end resistance of 10k
■ Potentiometer control and memory access via
Ω, 50k
ΩΩ
ΩΩ
Ω & 100k
ΩΩ
ΩΩ
Ω
ΩΩ
2-wire interface (I2C-like)
■ Nonvolatile memory storage for wiper settings
■ Automatic recall of saved wiper setting at power up
■ Special increment/decrement instruction mode for
automatic trimming adjustments
■ V
operation from 2.7 V to 5.5 V
CC
■ V+ (Analog Voltage Supply) operation from +8 V to
+15V
■ Standby current less than 15 µA
■ 100 year nonvolatile memory data retention
■ 10-pin MSOP package
■ Operating temperature of -40˚C to + 85˚C
APPLICATIONS
■ LCD screen adjustment
■ Volume control
■ Mechanical potentiometer replacement
■ Gain adjustment
■ Line impedance matching
■ VCOM setting adjustments
DESCRIPTION
The CAT5132 is a high voltage Digitally Programmable
Potentiometer (DPP) integrated with EEPROM memory
and control logic to operate in a similar manner as a
mechanical potentiometer. The DPP consists of a series
of resistive elements connected between two externally
accessible end points. The tap points between each
resistive element are connected to the wiper output with
CMOS switches. A separate 7-bit control register (WCR)
independently controls the wiper tap switches for the
DPP. Associated with the control register is a 7-bit
nonvolatile memory data register (DR) used for storing
wiper settings. Writing to the wiper control register or the
nonvolatile data register is via a 2-wire serial bus (I
like).
On power-up, WCR is set to mid scale (1000000) and
after the Power Supply becomes stable, the contents of
the data register (DR) are transferred to the wiper control
register (WCR) and the wiper is positioned to that
location.
The CAT5132 comes with 2 voltage supply inputs: VCC,
the digital supply voltage input and V+, an analog supply
voltage input. These inputs allow the V+ to be as much
as 10 volts higher than the VCC and allow the DPP
terminal values to be as much as 15 volts above ground.
The CAT5132 can be used as a potentiometer or as a
two-terminal variable resistor. It is intended for circuit
level adjustments. It is supplied standard in the -40°C to
+85°C industrial operating temperature range and offered
in the 10-pin MSOP package.
2
C-
BLOCK DIAGRAM
SDA
SCL
A0
A1
NONVOLATILE
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
V
CC
CONTROL LOGIC AND
ADDRESS DECODE
7-BIT
MEMORY
REGISTER
(DR)
7-BIT WIPER
CONTROL
REGISTER
(WCR)
V+
128 TAP POSITION
DECODE CONTROL
1
127
R
H
ELEMENTS
127 RESISTIVE
0
R
L
R
W
Doc. No. 25092, Rev. 00
CAT5132
PIN CONFIGURATION
10
SCL
V+
9
R
8
L
R
7
W
R
6
H
CC
A1
A0
1
2
3
4
5
SDA
GND
V
MSOP 10-Pin Package
PIN DESCRIPTION
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ORDERING INFORMATION
Prefix Device # Suffix
CAT
Company ID
5132
Product
Number
Notes:
1. The device used in the above example is a CAT5132R-10TE13 (MSOP, 10k ohms, Tape & Reel).
2. The Industrial Temperature range of -40˚C to +85˚C is standard on the above product.
R
-10
Resistance
-10: 10k ohms
-50: 50k ohms
-100: 100k ohms
Package
R: MSOP
Z: MSOP (Green with Sn Lead Finish)
GZ: MSOP (Green with NiPd Au Lead Finsh)
TE13
Tape & Reel
2500 units/Reel
Doc. No. 25092, Rev. 00
2
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5132
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias....................-55˚C to +125˚C
Storage Temperature........................ -65˚C to +150˚C
Voltage on any SDA, SCL, A0 & A1 pins with respect
to Ground
Voltage on RH, RL & RW Pins with respect
to Ground .................................... -2.0V to “V+” + 1.0V
with respect to Ground ................... -2.0V to 7.0V
V
CC
V+ with respect to Ground ................... -2.0V to 16.0V
Wiper Current (10 sec) ......................................
(1)(2)
.............................. -2.0V to VCC + 2.0V
+6mA
RECOMMENDED OPERATING CONDITIONS
VCC = +2.7V to +5.5V
V+ = 8.0V to +15V
Operating Temperature Range: -40˚C to +85˚C
COMMENT
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions outside of those listed
in the operational sections of this specification is not implied. Exposure to any
absolute maximum rating for extended periods may affect device performance
and reliability.
Lead Soldering temperature (10 sec) .............. +300˚C
POTENTIOMETER CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
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Notes:
1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
3. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.
4. LSB = (R
5. n = 1, 2, ..., 127
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
HM - RLM
)/127; where RHM and RLM are the highest and lowest measured values on the wiper terminal.
3
Doc No. 25092, Rev. 00
CAT5132
D.C. ELECTRICAL CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
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CAPACITANCE
TA = 25˚C, f = 1.0MHz, VCC = 5.0V
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A.C. CHARACTERISTICS
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Notes:
1. This parameter is tested initially and after a design or process change that affects the parameter.
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Doc. No. 25092, Rev. 00
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5132
POWER UP TIMING
(1)(2)
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t
WUP
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XDCP TIMING
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t
LRW
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WRITE CYCLE LIMITS
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t
RW
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not
respond to its slave address.
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RELIABILITY CHARACTERISTICS
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Notes:
1. This parameter is tested initially and after a design or process change that affects the parameter.
2. t
PUR
and t
are the delays required from the time VCC is stable until the specified operation can be initiated.
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TYPICAL PERFORMANCE CHARACTERISTICS
Resistance between RW and R
12.000
10.000
8.000
6.000
(Kohm)
WL
R
4.000
2.000
0.000
0 163248648096112128
Tap position
L
Vcc=2.7V; V+=8v
Vcc=5.5V; V+=1 5V
Icc2 (NV write) vs Temperature
400
350
300
250
200
Icc2 (uA)
150
100
50
0
-50 -30 -10 10 30 50 70 90 110 130
Temperature (
°
C)
Vcc = 2.7V
Vcc = 5.5V
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc No. 25092, Rev. 00
CAT5132
TYPICAL PERFORMANCE CHARACTERISTICS (CONT)
Absolute Linearity Error per Tap Position
Error (LSB)
LIN
A
1.000
0.800
0.600
0.400
0.200
0.000
-0.200
-0.400
-0.600
-0.800
-1.000
Tamb = 25 C
Rtotal = 10K
0 163248648096112128
Tap position
t
F
Vcc=2.7V; V+=8v
Vcc=5.5V; V+=15V
t
LOW
SCL
t
SU:STA
t
HD:STA
t
t
HIGH
HD:DAT
t
LOW
Relative Linearity Error
0.500
Tamb = 25 C
0.400
Rtotal = 10K
0.300
0.200
0.100
0.000
Error (LSB)
-0.100
LIN
R
-0.200
-0.300
-0.400
-0.500
0 1632486480 96112128
t
R
t
SU:DAT
Tap position
Vcc=2.7V; V+=8V
Vcc=5.5V; V+=15V
t
SU:STO
SDA IN
SDA OUT
SCL
SDA
BYTE n
t
AA
t
DH
Figure 1. Bus Timing
ACK8TH BIT
t
WR
STOP
CONDITION
Figure 2. Write Cycle Timing
START
CONDITION
t
BUF
ADDRESS
Doc. No. 25092, Rev. 00
6
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5132
SERIAL BUS PROTOCOL
The following defines the features of the 2-wire bus
protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock is high will be
interpreted as a START or STOP condition.
The device controlling the transfer is a master, typically
a processor or controller, and the device being controlled
is the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the CAT5132 will be considered
a slave device in all applications.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT5132 monitors the
SDA and SCL lines and will not respond until this
condition is met (see Fig. 3).
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition (see Fig. 3).
Acknowledge
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data (see Fig. 4).
The CAT5132 responds with an acknowledge after
receiving a START condition and its slave address. If
the device has been selected along with a write operation,
it responds with an acknowledge after receiving each
8-bit byte.
When the CAT5132 is in a READ mode it transmits 8 bits
of data, releases the SDA line, and monitors the line for
an acknowledge. Once it receives this acknowledge,
the CAT5132 will continue to transmit data. If no
acknowledge is sent by the Master, the device terminates
data transmission and waits for a STOP condition.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
the CAT5132 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issuing
the start condition followed by the slave address. If the
CAT5132 is still busy with the write operation, no ACK
will be returned. If the CAT5132 has completed the write
operation, an ACK will be returned and the host can then
proceed with the next instruction operation.
SDA
SCL
SCL FROM
MASTER
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
START CONDITION
Figure 3. Start/Stop Condition
START
Figure 4. Acknowledge Condition
STOP CONDITION
1
7
89
ACKNOWLEDGE
Doc No. 25092, Rev. 00
CAT5132
DEVICE DESCRIPTION
Access Control Register
The volatile register WCR and the non-volatile register
DR of CAT5132 are accessed only by addressing the
volatile Access Register AR first, using the 3 byte I
interface for all read and write operations (see Table 1).
The first byte is the slave address/instruction byte (see
details below). The second byte contains the address
(02h) of the AR register. The data in the third byte
controls which register WCR (80h) or DR (00h) is being
addressed (see Figure 5).
Slave Address Instruction Byte Description
The first byte sent to the CAT5132 from the master
processor is called the Slave/DPP Address Byte. The
most significant five bits of the slave address are a
device type identifier. These bits for the CAT5132 are
fixed at 01010 (refer to Table 2).
Table 1. Access Control Register
1st byte 2nd byte 3rd byte
START
ID4
ID3
ID2
ID1
ID0
A1
A0
TS 01010000A00000010A1000 0000A
TS 01010000A00000010A0000 0000APS
Wb
ACK
2
C
The next two bits, A1 and A0, are the internal slave
address and must match the physical device address
which is defined by the state of the A1 and A0 input pins
to successfully address the CAT5132. Only the device
with slave address matching the input byte will be
accessed by the master. This allows up to 4 devices to
reside on the same bus. The A1 and A0 inputs can be
actively driven by CMOS input signals or tied to VCC or
Ground.
The last bit is the READ/WRITE bit and determines the
function to be performed. If it is a “1” a read command is
initiated and if it is a “0” a write is initiated. For the AR
register only write is allowed.
After the Master sends a START condition and the slave
address byte, the CAT5132 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address.
h20-sserddaRAonitceles)h00(RD/)h08(RWC
ACK
ACK
STOP
SP
Table 2. Byte 1 Slave Address and Instruction Byte
reifitnedIepyTeciveDsserddAevalS/daeR etirW
4DI3DI2DI1DI0DI1A0A/R W
01010XXX
)BSM( )BSL(
BUS ACTIVITY:
MASTER
SDA LINE
SLAVE
ADDRESS
S
& INSTRUCTION
T
A
R
FIXED
T
S
VARIABLE
AR REGISTER
A
C
K
ADDRESS
WCR/DR
SELECTION
A
C
K
S
T
O
P
P
A
C
K
Figure 5. Access Register Addressing Using 3 Bytes
Doc. No. 25092, Rev. 00
8
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Wiper Control Register (WCR) Description
CAT5132
The CAT5132 contains a 7-bit Wiper Control Register
which is decoded to select one of the 128 switches along
its resistor array. The WCR is a volatile register and is
written with the contents of the nonvolatile Data Register
(DR) on power-up. The Wiper Control Register loses its
contents when the CAT5132 is powered-down. The
contents of the WCR may be read or changed directly by
the host using a READ/WRITE command after addressing
the WCR (see Table 1 to access WCR). Since the
CAT5132 will only make use of the 7 LSB bits (The first
data bit, or MSB, is ignored) on write instructions and will
always come back as a “0” on read commands.
A write operation (see Table 3) requires a Start condition, followed by a valid slave address byte, a valid address byte
00h, a data byte and a STOP condition. After each of the three bytes the CAT5132 responds with an acknowledge.
At this time the data is written only to volatile registers, then the device enters its standby state.
Table 3. WCR Write Operation
1st byte 2nd byte 3rd byte
START
ID4
ID3
ID2
ID1
ID0A1A0
TS 01010000A00000010A10000000APS
slave address byte WCR address - 00h data byte
START
TS 01010000A00000000 APS
Wb
ACK
ACK
Ah20-sserddaR
ACK
ACK
WCR(80h) selection
XXXXXXXAX
ACK
ACK
STOP
STOP
An increment operation (see Table 4) requires a Start condition, followed by a valid increment address byte (01011),
a valid address byte 00h. After each of the two bytes, the CAT5132 responds with an acknowledge. At this time if the
data is high then the wiper is incremented or if the data is low the wiper is decremented at each clock. Once the stop
is issued then the device enters its standby state with the WCR data as being the last inc/dec position. Also, the wiper
position does not roll over but is limited to min and max positions.
Table 4. WCR Increment/Decrement Operation
1st byte 2nd byte 3rd byte
START
ID4
ID3
ID2
ID1
ID0A1A0
TS 01010000A00000010A10000000
slave address byte WCR address - 00h increment (1) / decrement (0) bits
START
TS 01011000A00000000 SP
Wb
ACK
ACK
Ah20-sserddaR
ACK
ACK
WCR(80h) selection
111A1
0000
ACK
STOP
ASP
STOP
A read operation (see Table 5) requires a Start condition, followed by a valid slave address byte for write, a valid address
byte 00h, a second START and a second slave address byte for read. After each of the three bytes, the CAT5132
responds with an acknowledge and then the device transmits the data byte. The master terminates the read operation
by issuing a STOP condition following the last bit of Data byte.
Table 5. WCR Read Operation
1st byte 2nd byte 3rd byte
START
ID4
ID3
ID2
ID1
ID0A1A0
TS 01010000A00000010A10000000
slave address byte WCR address - 00h
START
TS 01010000A00000000
Wb
ACK
ACK
Ah20-sserddaR
ACK
WCR(80h) selection
ACK
STOP
ASP
slave address byte data byte
START
TS 01010001A0XXXXXXX
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
STOP
SP
Doc No. 25092, Rev. 00
CAT5132
Data Register (DR)
The Data Register (DR) is a nonvolatile register and its
contents are automatically written to the Wiper Control
Register (WCR) on power-up. It can be read at any time
without effecting the value of the WCR. The DR, like the
WCR, only stores the 7 LSB bits and will report the MSB
bit as a “0”. Writing to the DR is performed in the same
being performed. During the internal non-volatile write
cycle, the device ignores transitions at the SDA and SCL
pins, and the SDA output is at a high impedance state.
The WCR is also written during a write to DR. After a DR
WRITE is complete the DR and WCR will contain the
same wiper position.
fashion as the WCR except that a time delay of up to 5ms
is experienced while the nonvolatile store operation is
To write or read to the DR, first the access to DR is selected, see table 1 then the data is written or read using the
following sequences.
A write operation (see Table 6) requires a Start condition, followed by a valid slave address byte, a valid address byte
00h, a data byte and a STOP condition. After each of the three bytes the CAT5132 responds with an acknowledge.
At this time the data is written both to volatile and non-volatile registers, then the device enters its standby state.
Table 6. DR Write Operation
1st byte 2nd byte 3rd byte
START
ID4
ID3
ID2
ID1
ID0A1A0
TS 01010000A00000010A00000000APS
slave address byte DR address - 00h data byte
START
TS 01010000A00000000 APS
Wb
ACK
ACK
Ah20-sserddaR
ACK
ACK
DR(00h) selection
XXXXXXXAX
ACK
ACK
STOP
STOP
A read operation (see Table 7) requires a Start condition, followed by a valid slave address byte, a valid address byte
00h, a second Start and a second slave address byte for read. After each of the three bytes the CAT5132 responds
with an acknowledge and then the device transmits the data byte. The master terminates the read operation by issuing
a STOP condition following the last bit of Data byte.
Table 7. DR Read Operation
1st byte 2nd byte 3rd byte
START
ID4
ID3
ID2
ID1
ID0A1A0
TS 01010000A00000010A00000000
slave address byte DR address - 00h
START
TS 01010000A00000000
slave address byte data byte
START
TS 01010001A0XXXXXXX
Wb
ACK
ACK
Ah20-sserddaR
ACK
SP
STOP
DR(00h) selection
ACK
STOP
ASP
Doc. No. 25092, Rev. 00
10
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
POTENTIOMETER OPERATION
noitisoP
RlacipyT
W
Rot
L
rofecnatsiseR
k01 ΩΩΩΩΩ PPD
0007 Ω ro0Ω 07+ Ω
10941 Ω ro97 Ω 07+ Ω
36740,5 Ω ro779,4 Ω 07+ Ω
721070,01 Ω ro000,01 Ω 07+ Ω
noitisoP
RlacipyT
W
Rot
H
rofecnatsiseR
k01 ΩΩΩΩΩ PPD
00070,01 Ω ro000,01 Ω 07+ Ω
46740,5 Ω ro779,4 Ω 07+ Ω
621941 Ω ro97 Ω 07+ Ω
72107 Ω ro0Ω 07+ Ω
Power-On
The CAT5132 is a 128-position, digital controlled
potentiometer. At power-up the device turns on at the
mid-point wiper location (64) until the wiper register can
be loaded with the nonvolatile memory location previously
stored in the device. After the nonvolatile memory data
is loaded into the wiper register the wiper location will
change to the previously stored wiper position.
The end-to-end nominal resistance of the potentiometer
has 128 contact points linearly distributed across the
total resistor. Each of these contact points is addressed
by the 7 bit wiper register which is decoded to select one
of these 128 contact points.
Each contact point generates a linear resistive value
between the 0 position and the 127 position. These
values can be determined by dividing the end-to-end
value of the potentiometer by 127. In the case of the
10kΩ potentiometer~79Ω is the resistance between
each wiper position. However in addition to the ~79Ω for
each resistive segment of the potentiometer, a wiper
resistance offset must be considered. Table 8 shows the
effect of this value and how it would appear on the wiper
terminal.
CAT5132
This offset will appear in each of the CAT5132 end-toend resistance values in the same way as the 10kΩ
example. However resistance between each wiper
position for the 50kΩ version will be ~395Ω and for the
100kΩ version will be ~790Ω.
Table 8. Potentiometer Resistance and Wiper
Resistance Offset Effects
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc No. 25092, Rev. 00
CAT5132
PACKAGE OUTLINES
10-LEAD MSOP
Doc. No. 25092, Rev. 00
12
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
REVISION HISTORY
Date Rev. Reason
09/12/2005 00 Initial Issue
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Publication #: 25092
Revison: 00
Issue date: 09/12/05
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