CATALYST CAT1161-2 Service Manual

CAT1161/2 (16K)

Supervisory Circuits with I2C Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer

FEATURES

■ Watchdog monitors SDA signal (CAT1161)

■ 400kHz I

2

C bus compatible

■ 2.7V to 6.0V operation

■ Low power CMOS technology

■ 16-Byte page write buffer

■ Built-in inadvertent write protection

— VCC lock out
— Write protect pin, WP

DESCRIPTION

The CAT1161/2 is a complete memory and supervisory
solution for microcontroller-based systems. A serial
EEPROM memory (16K) with hardware memory write
protection, a system power supervisor with brown out
protection and a watchdog timer are integrated together
in low power CMOS technology. Memory interface is via
an I2C bus.

The 1.6-second watchdog circuit returns a system to a
known good state if a software or hardware glitch halts
or “hangs” the system. The CAT1161 watchdog monitors
the SDA line, making an additional PC board trace
unnecessary. The lower cost CAT1162 does not have a
watchdog timer.

■ Active high or low reset

— Precision power supply voltage monitor
— 5V, 3.3V and 3V systems
— Five threshold voltage options

■ 1,000,000 Program/Erase cycles

■ Manual Reset

■ 100 Year data retention

■ 8-pin DIP or 8-pin SOIC

■ Commercial and industrial temperature ranges

voltages support 5V, 3.3V and 3V systems. If power supply
voltages are out of tolerance reset signals become active,
preventing the system microcontroller, ASIC or peripherals
from operating. Reset signals become inactive typically 200
ms after the supply voltage exceeds the reset threshold
level. With both active high and low reset signals, interface
to microcontrollers and other ICs is simple. In addition, a
reset pin can be used as a debounced input for push-button
manual reset capability.

The CAT1161/2 memory features a 16-byte page. In addition,
hardware data protection is provided by a write protect pin
WP and by a VCC sense circuit that prevents writes to
memory whenever VCC falls below the reset threshold or
until VCC reaches the reset threshold during power up.

The power supply monitor and reset circuit protects
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold

PIN CONFIGURATION

DC

RESET

CAT1161/2

WP

GND

DC = Do not connect

Part Dash Minimum Maximum
Number Threshold Threshold

-45 4.50 4.75

-42 4.25 4.50

-30 3.00 3.15

-28 2.85 3.00

-25 2.55 2.70

© 2002 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

V

CC

RESET
SCL
SDA

Available packages include an 8-pin DIP and a surface
mount, 8-pin SO package.

BLOCK DIAGRAM

EXTERNAL LOAD

V

CC

GND

SDA

WP

Only for

CAT1161

D

WORD ADDRESS

BUFFERS

START/STOP

LOGIC

CONTROL

LOGIC

RESET Controller

WATCHDOG

OUT

ACK

Precision

Vcc Monitor

RESET RESET

XDEC

SENSE AMPS

SHIFT REGISTERS

COLUMN

DECODERS

16K

EEPROM

DATA IN STORAGE

HIGH VOLT A GE/

TIMING CONTROL

STATE COUNTERS
SLAVE

ADDRESS
COMPARATORS

SCL

Doc No. 3002, Rev. D

CAT1161/2

ABSOLUTE MAXIMUM RATINGS

Temperature Under Bias ................. –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

Voltage on any Pin with

Respect to Ground

VCC with Respect to Ground ............... –2.0V to +7.0V

Package Power Dissipation

Capability (TA = 25°C) ................................... 1.0W

Lead Soldering Temperature (10 secs)............ 300°C

Output Short Circuit Current
Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica­tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor­mance and reliability.

(1)

............ –2.0V to +VCC +2.0V

(2)

........................ 100 mA

PIN FUNCTIONS

Pin No. Pin Name Function

1 DC Do Not Connect
2 RESET Active Low Reset I/O

3 WP Write Protect
4 GND Ground
5 SDA Serial Data/Address

6 SCL Clock Input
7 RESET Active High Reset I/O
8VCCPower Supply

RELIABILITY CHARACTERISTICS

Symbol Parameter Reference Test Method Min Max Units

(3)

N
T
V
I

END
DR
ZAP

LTH

(3)

(3)

(3)(4)

Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte
Data Retention MIL-STD-883, Test Method 1008 100 Years
ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts
Latch-Up JEDEC Standard 17 100 mA

D.C. OPERATING CHARACTERISTICS

VCC = +2.7V to +6.0V, unless otherwise specified.

Symbol Parameter Test Conditions Min Typ Max Units

I

CC

I

SB

Power Supply Current f

= 100 KHz 3 mA

SCL

Standby Current VCC = 3.3V 40 µA

VCC = 5 50 µA

I

LI

I

LO

V

IL

V

IH

V

OL1

Input Leakage Current VIN = GND or V
Output Leakage Current VIN = GND or V

CC
CC

2 µA

10 µA
Input Low Voltage -1 VCC x 0.3 V
Input High Voltage V

X 0.7 V

CC

+ 0.5 V

CC

Output Low Voltage (SDA) IOL = 3 mA, VCC = 3.0V 0.4 V

Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

Doc. No. 3002, Rev. D

2

CAT1161/2

CAPACITANCE

TA = 25˚C, f = 1.0 MHz, VCC = 5V

Symbol Test Conditions Max Units

(1)

C

I/O

(1)

C

IN

A.C. CHARACTERISTICS

VCC=2.7V to 6.0V unless otherwise specified.
Output Load is 1 TTL Gate and 100pF.

SYMBOL PARAMETER Min Max Min Max Units

Input/Output Capacitance (SDA) V

= 0V 8 pF

I/O

Input Capacitance (SCL) VIN = 0V 6 pF

VCC = 2.7V - 6V VCC = 4.5V - 5.5V

F

SCL

(1)

T

I

t

AA

t

BUF

t

HD:STA

t

LOW

t

HIGH

t

SU:STA

t

HD:DAT

t

SU:DAT

(1)

t

R

(1)

t

F

t

SU:STO

(1)

Clock Frequency 100 400 kHz
Noise Suppresion Time 200 200 ns

Constant at SCL, SDA Inputs
SLC Low to SDA Data Out 3.5 1 µs

and ACK Out
Time the Bus Must be Free Before 4.7 1.2 µs

a New Transmission Can Start
Start Condition Hold Time 4 0.6 µs
Clock Low Period 4.7 1.2 µs
Clock High Period 4 0.6 µs

Start Condition Setup Time 4.7 0.6 µs
(for a Repeated Start Condition)

Data in Hold Time 0 0 ns
Data in Setup Time 50 50 ns
SDA and SCL Rise Time 1 0.3 µs
SDA and SCL Fall Time 300 300 ns
Stop Condition Setup Time 4 0.6 µs

t

DH

POWER-UP TIMING

Data Out Hold Time 100 100 ns

(1)(2)

Symbol Parameter Max Units

t

PUR

t

PUW

Power-up to Read Operation 1 ms
Power-up to Write Operation 1 ms

WRITE CYCLE LIMITS

Symbol Parameter Min Typ Max Units

t

WR

The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.

NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t

PUR

Write Cycle Time 10 ms

and t

are the delays required from the time V

PUW

is stable until the specific operation can be initiated.

CC

3

Doc No. 3002, Rev. D

CAT1161/2

RESET CIRCUIT CHARACTERISTICS

Symbol Parameter Min Typ Max Units

t

GLITCH

Glitch Reject Pulse Width 100 ns
V
V
V

RT
OLRS
OHRS

Reset Threshold Hystersis 15 mV

Reset Output Low Voltage (I

=1mA) 0.4 V

OLRS

Reset Output High Voltage VCC-0.75 V

Reset Threshold (V

=5V) 4.50 4.75

CC

(CAT1161/2-45)

Reset Threshold (VCC=5V) 4.25 4.50

(CAT1161/2-42)

V

TH

Reset Threshold (VCC=3.3V) 3.00 3.15

(CAT1161/2-30)

Reset Threshold (V

=3.3V) 2.85 3.00

CC

V

(CAT1161/2-28)

Reset Threshold (VCC=3V) 2.55 2.70

(CAT1161/2-25)
t

PURST

Power-Up Reset Timeout 130 270 ms
twp Watchdog Period 1.6 sec
t

RPD

V

RVALID

VTH to RESET Output Delay 5 µs

RESET Output Valid 1 V

Doc. No. 3002, Rev. D

4