BOSCH E-Ray User Manual

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Page 1

User’s Manual

E-Ray

FlexRay IP-Module

Revision 1.2.5 E-Ray

manual_cover.fm

User’s Manual

Revision 1.2.5

15.12.2006

Robert Bosch GmbH

Automotive Electronics

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User’s Manual

Revision 1.2.5 E-Ray

Copyright © 2002-2006 Robert Bosch GmbH. All rights reserved. This manual is owned by Robert Bosch GmbH. No part of this publication may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Robert Bosch GmbH, or as expressly provided by the license agreement.

Disclaimer

ROBERT BOSCH GMBH, MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.

ROBERT BOSCH GMBH, RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO THE PRODUCTS DESCRIBED HEREIN. ROBERT BOSCH GMBH DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN.

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1. About this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.1 Change Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.1.1 Current Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

1.1.2 Change History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

1.2 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.3 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.4 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.5 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.6 Terms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

2. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3. Generic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4. Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.2 Customer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4.3 Special Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.3.1 Lock Register (LCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

4.4 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

4.4.1 Error Interrupt Register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

4.4.2 Status Interrupt Register (SIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

4.4.3 Error Interrupt Line Select (EILS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

4.4.4 Status Interrupt Line Select (SILS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

4.4.5 Error Interrupt Enable Set / Reset (EIES, EIER) . . . . . . . . . . . . . . . . . . . .33

4.4.6 Status Interrupt Enable Set / Reset (SIES, SIER) . . . . . . . . . . . . . . . . . . .34

4.4.7 Interrupt Line Enable (ILE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

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4.4.8 Timer 0 Configuration (T0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

4.4.9 Timer 1 Configuration (T1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

4.4.10 Stop Watch Register 1 (STPW1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

4.4.11 Stop Watch Register 2 (STPW2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

4.5 CC Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

4.5.1 SUC Configuration Register 1 (SUCC1) . . . . . . . . . . . . . . . . . . . . . . . . . . .40

4.5.2 SUC Configuration Register 2 (SUCC2) . . . . . . . . . . . . . . . . . . . . . . . . . . .45

4.5.3 SUC Configuration Register 3 (SUCC3) . . . . . . . . . . . . . . . . . . . . . . . . . . .45

4.5.4 NEM Configuration Register (NEMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

4.5.5 PRT Configuration Register 1 (PRTC1) . . . . . . . . . . . . . . . . . . . . . . . . . . .47

4.5.6 PRT Configuration Register 2 (PRTC2) . . . . . . . . . . . . . . . . . . . . . . . . . . .48

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4.5.7 MHD Configuration Register (MHDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

4.5.8 GTU Configuration Register 1 (GTUC1) . . . . . . . . . . . . . . . . . . . . . . . . . . .50

4.5.9 GTU Configuration Register 2 (GTUC2) . . . . . . . . . . . . . . . . . . . . . . . . . . .50

4.5.10 GTU Configuration Register 3 (GTUC3) . . . . . . . . . . . . . . . . . . . . . . . . . .51

4.5.11 GTU Configuration Register 4 (GTUC4) . . . . . . . . . . . . . . . . . . . . . . . . . .52

4.5.12 GTU Configuration Register 5 (GTUC5) . . . . . . . . . . . . . . . . . . . . . . . . . .53

4.5.13 GTU Configuration Register 6 (GTUC6) . . . . . . . . . . . . . . . . . . . . . . . . . .53

4.5.14 GTU Configuration Register 7 (GTUC7) . . . . . . . . . . . . . . . . . . . . . . . . . .54

4.5.15 GTU Configuration Register 8 (GTUC8) . . . . . . . . . . . . . . . . . . . . . . . . . .54

4.5.16 GTU Configuration Register 9 (GTUC9) . . . . . . . . . . . . . . . . . . . . . . . . . .55

4.5.17 GTU Configuration Register 10 (GTUC10) . . . . . . . . . . . . . . . . . . . . . . . .55

4.5.18 GTU Configuration Register 11 (GTUC11) . . . . . . . . . . . . . . . . . . . . . . . .56

4.6 CC Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

4.6.1 CC Status Vector (CCSV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

4.6.2 CC Error Vector (CCEV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

4.6.3 Slot Counter Value (SCV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

4.6.4 Macrotick and Cycle Counter Value (MTCCV) . . . . . . . . . . . . . . . . . . . . . .61

4.6.5 Rate Correction Value (RCV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

4.6.6 Offset Correction Value (OCV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

4.6.7 Sync Frame Status (SFS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

4.6.8 Symbol Window and NIT Status (SWNIT) . . . . . . . . . . . . . . . . . . . . . . . . .64

4.6.9 Aggregated Channel Status (ACS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

4.6.10 Even Sync ID [1…15] (ESIDn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

4.6.11 Odd Sync ID [1…15] (OSIDn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

4.6.12 Network Management Vector [1…3] (NMVn) . . . . . . . . . . . . . . . . . . . . . .70

4.7 Message Buffer Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

4.7.1 Message RAM Configuration (MRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

4.7.2 FIFO Rejection Filter (FRF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

4.7.3 FIFO Rejection Filter Mask (FRFM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

4.7.4 FIFO Critical Level (FCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

4.8 Message Buffer Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

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4.8.1 Message Handler Status (MHDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

4.8.2 Last Dynamic Transmit Slot (LDTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

4.8.3 FIFO Status Register (FSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

4.8.4 Message Handler Constraints Flags (MHDF) . . . . . . . . . . . . . . . . . . . . . . .78

4.8.5 Transmission Request 1/2/3/4 (TXRQ1/2/3/4) . . . . . . . . . . . . . . . . . . . . . .80

4.8.6 New Data 1/2/3/4 (NDAT1/2/3/4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

4.8.7 Message Buffer Status Changed 1/2/3/4 (MBSC1/2/3/4) . . . . . . . . . . . . . .82

4.9 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

4.9.1 Core Release Register (CREL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

4.9.2 Endian Register (ENDN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

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4.10 Input Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

4.10.1 Write Data Section [1…64] (WRDSn) . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

4.10.2 Write Header Section 1 (WRHS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

4.10.3 Write Header Section 2 (WRHS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

4.10.4 Write Header Section 3 (WRHS3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

4.10.5 Input Buffer Command Mask (IBCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

4.10.6 Input Buffer Command Request (IBCR) . . . . . . . . . . . . . . . . . . . . . . . . . .88

4.11 Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

4.11.1 Read Data Section [1…64] (RDDSn) . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

4.11.2 Read Header Section 1 (RDHS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

4.11.3 Read Header Section 2 (RDHS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

4.11.4 Read Header Section 3 (RDHS3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

4.11.5 Message Buffer Status (MBS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

4.11.6 Output Buffer Command Mask (OBCM) . . . . . . . . . . . . . . . . . . . . . . . . . .96

4.11.7 Output Buffer Command Request (OBCR) . . . . . . . . . . . . . . . . . . . . . . .97

5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

5.1 Communication Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

5.1.1 Static Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

5.1.2 Dynamic Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

5.1.3 Symbol Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

5.1.4 Network Idle Time (NIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

5.1.5 Configuration of NIT Start and Offset Correction Start . . . . . . . . . . . . . . .100

5.2 Communication Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

5.2.1 Time-triggered Distributed (TT-D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

5.3 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

5.3.1 Global Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

5.3.2 Local Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

5.3.3 Synchronization Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

5.3.3.1 Offset (phase) Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.3.3.2 Rate (frequency) Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

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5.3.3.3 Sync Frame Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.3.4 External Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

5.4 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

5.4.1 Clock Correction Failed Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

5.4.2 Passive to Active Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

5.4.3 HALT Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

5.4.4 FREEZE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

5.5 Communication Controller States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

5.5.1 Communication Controller State Diagram . . . . . . . . . . . . . . . . . . . . . . . .106

5.5.2 DEFAULT_CONFIG State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

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5.5.3 CONFIG State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

5.5.4 MONITOR_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

5.5.5 READY State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

5.5.6 WAKEUP State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

5.5.6.1 Host activities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

5.5.6.2 Wakeup pattern (WUP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

5.5.7 STARTUP State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

5.5.7.1 Coldstart Inhibit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

5.5.7.2 Startup Timeouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

5.5.7.3 Path of leading Coldstart Node (initiating coldstart) . . . . . . . . . . . . . . . . . 117

5.5.7.4 Path of following Coldstart Node (responding to leading Coldstart Node) 118

5.5.7.5 Path of Non-coldstart Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

5.5.8 NORMAL_ACTIVE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

5.5.9 NORMAL_PASSIVE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

5.5.10 HALT State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

5.6 Network Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

5.7 Filtering and Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

5.7.1 Slot Counter Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

5.7.2 Cycle Counter Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

5.7.3 Channel ID Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

5.7.4 FIFO Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

5.8 Transmit Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

5.8.1 Static Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

5.8.2 Dynamic Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

5.8.3 Transmit Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

5.8.4 Frame Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

5.8.5 Null Frame Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

5.9 Receive Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

5.9.1 Dedicated Receive Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

5.9.2 Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

5.9.3 Null Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

5.10 FIFO Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

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5.10.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

5.10.2 Configuration of the FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

5.10.3 Access to the FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

5.11 Message Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

5.11.1 Reconfiguration of Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . .131

5.11.2 Host access to Message RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

5.11.2.1 Data Transfer from Input Buffer to Message RAM . . . . . . . . . . . . . . . . . 134

5.11.2.2 Data Transfer from Message RAM to Output Buffer . . . . . . . . . . . . . . . 136

5.11.3 FlexRay Protocol Controller access to Message RAM . . . . . . . . . . . . . .139

5.12 Message RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140

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5.12.1 Header Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

5.12.2 Data Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

5.12.3 Parity Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

5.13 Module Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

6. Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

6.1 Register Bit Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

6.2 Assignment of FlexRay Configuration Parameters . . . . . . . . . . . . . . . . . . . . .162

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

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Revision 1.2.5 E-Ray

1. About this Document

1.1 Change Control

1.1.1 Current Status

Revision 1.2.5

1.1.2 Change History

Issue Date By Change

Revision 1.0 29.10.04 C. Horst First complete revision Revision 1.0.1 16.11.04 C. Horst Message Buffer Status bits PLE, MLST, ES

replaced by bits ESA, ESB, MLST

Revision 1.0.2 28.01.05 C. Horst IBCR, IBCM, OBCR, OBCM: addresses changed

MHDC2: register removed MHDC1: renamed to MHDC Message buffer 0 dedicated to hold key slot ID SFS: description updated ESIDn, OSIDn: description updated EIR: bit SCE removed EILS: bit SCEL removed EIES, EIER: bit SCEE removed

Revision 1.1 29.04.05 C. Horst State DEFAULT_CONFIG added to POC working CCSV: assignment of states to POCS[5:0] changed:

POCS[5:0] = 00 0000 = DEFAULT_CONFIG POCS[5:0] = 00 1111 = CONFIG CCSV: bit DCREQ removed SIR: bit MBSI added SILS: bit MBSIL added SIES, SIER: bit MBSIE added Register BGSC removed EIR: bits SMEB, SMEA removed EILS: bits SMEBL, SMEAL removed EIES, EIER: bits SMEBE, SMEAE removed Registers TXRQ3, TXRQ4, NDAT3, NDAT4, MBSC3, MBSC4 added

manual_about.fm

Bus guardian related pins eray_arm, eray_bgt, eray_mt, eray_bge1, and eray_bge2 have no function

PRTC1: Configuration parameter CASM[6:0] added WRHS1: Bit NME changed to PPIT RDHS1: Bit NME changed to PPIT Pin eray_scanmode for scan mode control added

Revision 1.1 04.08.05 C. Horst EIR: Flags CCL, EFA, IIBA, IOBA, TABA,

TABB added SIR: Flag SDS added EILS: Control bits CCLL, EFAL, IIBAL, IOBAL, TABAL, TABBL added SILS: Control bit SDSL added

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EIES: Control bits CCLE, EFAE, IIBAE, IOBAE, TABAE, TABBE added EIER: Control bits CCLE, EFAE, IIBAE, IOBAE, TABAE, TABBE added SIES: Control bit SDSE added SIER: Control bit SDSE added SUCC2: LT[20:0] range modified PRTC1: TSST[3:0] range modified, SPP[1:0] added, configuration of BRP[1:0] for 1.25 MBit/s removed PRTC2: RXL[5:0] range modified MHDC: SLT[12:0] range modified GTUC1: UT[19:0] range modified GTUC2: MPC[13:0] range modified GTUC3: Configuration parameterMTIO[5:0] replaced by MIOA[6:0] and MIOB[6:0] GTUC4: NIT[13:0] and OCS[13:0] range modified GTUC5: DEC[7:0] range modified GTUC7: SSL[9:0] range modified GTUC8: NMS[12:0] range modified GTUC9: APO[5:0] and DSI[1:0] range modified GTUC10: MOC[13:0] range modified GTUC11: Configuration parameter ECC[1:0] replaced by EOCC[1:0] and ERCC[1:0] OCV: OCV[18:0] range modified SCV: SCCA[10:0], SCCB[10:0] range modified ACS: Flags can only be reset MRC: Configuration bits SEC[1:0] added Register LDTS added Bus guardian related pins eray_arm, eray_bgt, eray_mt, eray_bge1, and eray_bge2 removed from physical layer interface Chapter 6. Restrictions removed. Description of timing requirements for data transfers between Message RAM and IBF / OBF moved to "Addendum to E-Ray FlexRay IP-Module Specification Revision 1.1"

Revision 1.2 09.12.05 C. Horst Section 3.2 renamed from "Interrupt Flag Interface" to

"Internal Signal and Flag Interface"

manual_about.fm

With this revision it is possible to use message buffer 1 for sync frame transmission in addition to message buffer 0 if sync frames should have different payloads on channel A and B EIR: Handling of bits PERR and RFO same as for other bits, bit MHF added SIR: Bit RFF renamed to RFCL, handling of bits RFNE, RFCL same as for other bits EILS: Bit MHFL added SILS: Bit RFFL renamed to RFCLL EIES, EIER: Bit MHFE added SIES, SIER: Bit RFFE renamed to RFCLE

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Revision 1.2.5 E-Ray

Register STPW renamed to STPW1 STPW2: Register added CCSV: Bits PSL[5:0] added SWNIT: Bits MTSA, MTSB added MRC: Bit SPLM added FCL: Register added FSR: Register added MHDF: Register added MBSC1/2/3/4: Naming of bits changed from MBS to MBC to distinguish between message buffer status flag (MBC) and message buffer status register (MBS) CREL: Register added ENDN: Register added Message buffers in Message RAM: Header 2 and 3updated from received dataframes only MBS: Bits FTA, FTB, CCS[5:0], RCIS, SFIS, SYNS, NFIS, PPIS, RESS added

Revision 1.2.1 17.03.06 C. Horst All changes to previous release are described in

detail in [5].

Revision 1.2.2 19.05.06 C. Horst All changes to previous release are described in

detail in [6].

Revision 1.2.3 15.08.06 C. Horst All changes to previous release are described in

detail in [7]. Revision 1.2.4 Not published. Revision 1.2.5 15.12.06 C. Horst All changes to previous release are described in

detail in [8], [9].

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1.2 Conventions

The following conventions are used within this document: Times bold Names of bits and signals

CAPITALS POC states and CHI commands

1.3 Deﬁnitions

FlexRay Frame: Header Segment + Payload Segment Message Buffer: Header Section + Data Section Message RAM: Header Partition + Data Partition Data Frame: FlexRay frame that is not a null frame

1.4 Scope

This document describes the E-Ray FlexRay IP-module and its features from the application programmer’s point of view. All information necessary to integrate the E-Ray module into an user-defined ASIC is located in the Module Integration Guide. Information about a specific Customer CPU Interface can be found in the respective Customer CPU Interface Specification document.

1.5 References

This document refers to the following E-Ray release: Revision 1.0.1

This document refers to the following documents:

Ref Author(s) Title

[1] FlexRay Group FlexRay Communication System Protocol Specification v2.1 (05/05/12) [2] FlexRay Group FlexRay Communication System Protocol Specification v2.1 Revision A

Errata Sheet Version 1 (06/03/29) [3] FlexRay Group FlexRay Data Link Layer Conformance Test Specification v2.1 (06/03/27) [4] AE/EIP Addendum to E-Ray FlexRay IP-Module Specification Revision 1.2.2 [5] AE/EIP Changes E-Ray FlexRay IP-Module Specification v1.2 to v1.2.1 [6] AE/EIP Changes E-Ray FlexRay IP-Module Specification v1.2.1 to v1.2.2

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[7] AE/EIP Changes E-Ray FlexRay IP-Module Specification v1.2.2 to v1.2.3 [8] AE/EIP Changes E-Ray FlexRay IP-Module Specification v1.2.3 to v1.2.4 [9] AE/EIP Changes E-Ray FlexRay IP-Module Specification v1.2.4 to v1.2.5

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1.6 Terms and Abbreviations

This document uses the following terms and abbreviations:

Term Meaning

AP Action Point BD Bus Driver BSS Byte Start Sequence CAS Collision Avoidance Symbol CC Communication Controller CHI Controller Host Interface CIF Customer Interface Block CRC Cyclic Redundancy Check FES Frame End Sequence FSS Frame Start Sequence

Revision 1.2.5 E-Ray

FIFO First In First Out (message buffer structure) FSM Finite State Machine FSP Frame and Symbol Processing Block FTM Fault Tolerant Midpoint GIF Generic Interface Block GTU Global Time Unit Block IBF Input Buffer INT Interrupt Control Block MHD Message Handler Block MT Macrotick MTS Media Access Test Symbol NCT Network Communication Time NEM Network Management Block NIT Network Idle Time

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NM Network Management OBF Output Buffer POC Protocol Operation Control PRT Protocol Controller Block SDL Specification and Description Language SUC System Universal Control Block TBF Transient Buffer TDMA Time Division Multiple Access (media access method)

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TSS Transmission Start Sequence TT-D Time Triggered Distributed Synchronization µT Microtick WUP Wakeup Pattern WUS Wakeup Symbol

Revision 1.2.5 E-Ray

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2. Overview

The E-Ray module is a FlexRay IP-module that can be integrated as stand-alone device or as part of an ASIC. It is described in VHDL on RTL level, prepared for synthesis. The E-Ray IP-module performs communication according to the FlexRay protocolspecification v2.1. With maximum specified sample clock the bitrate is 10 MBit/s. Additional bus driver (BD) hardware is required for connection to the physical layer.

For communication on a FlexRay network, individual message buffers with up to 254 data bytes are configurable. The message storage consists of a single-ported Message RAM that holds up to 128 message buffers. All functions concerning the handling of messages are implemented in the Message Handler. Those functions are the acceptance filtering, the transfer of messages between the two FlexRay Channel Protocol Controllers and the Message RAM, maintaining the transmissionschedule as well as providing message status information.

The register set of the E-Ray IP-module can be accessed directlyby an external Host via the module’s Host interface. These registers are used to control/configure/monitor the FlexRay Channel Protocol Controllers, Message Handler, Global Time Unit, System Universal Control, Frame and Symbol Processing, Network Management, Interrupt Control, and to access the Message RAM via Input / Output Buffer.

The E-Ray IP-module can be connected to a wide range of customer-specific Host CPUs via its 8/16/32-bit Generic CPU Interface.

The E-Ray IP-module supports the following features:

• Conformance with FlexRay protocol specification v2.1

• Data rates of up to 10 Mbit/s on each channel

• Up to 128 message buffers configurable

• 8 Kbyte of Message RAM for storage of e.g. 128 message buffers with max. 48 byte data section

or up to 30 message buffers with 254 byte data section

• Configuration of message buffers with different payload lengths possible

• One configurable receive FIFO

• Each message buffer can be configured as receive buffer, as transmit buffer

or as part of the receive FIFO

• Host access to message buffers via Input and Output Buffer

Input Buffer: Holds message to be transferred to the Message RAM

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Output Buffer: Holds message read from the Message RAM

• Filtering for slot counter, cycle counter, and channel

• Maskable module interrupts

• Network Management supported

• 8/16/32-bit Generic CPU Interface, connectable to a wide range of customer-specific Host CPUs

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2.1 Block Diagram

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Revision 1.2.5 E-Ray

Rx_A

Physical

Layer

Host CPU

Figure 1: E-Ray block diagram

Tx_A

Control

Rx_B

Tx_B

Data

Addr

Control

Interrupt

PRT B

IBF

OBF

Generic CPU IF

Customer CPU IF

PRT A

TBF B

Message Handler

Message RAM

TBF A

GTU

SUC

FSP

NEM

INT

Customer CPU Interface (CIF)

Connects a customer specific Host CPU to the E-Ray IP-module via the Generic CPU Interface.

Generic CPU Interface (GIF)

The E-Ray IP-module is provided with an 8/16/32-bit Generic CPU Interface prepared for the connection to a wide range of customer-specific Host CPUs. Configuration registers, status registers, and interrupt registers are attached to the respective blocks and can be accesssed via the Generic CPU Interface.

Input Buffer (IBF)

For write access to the message buffers configured in the Message RAM, the Host can write the header and data section for a specific message buffer to the Input Buffer. The Message Handler then transfers the data from the Input Buffer to the selected message buffer in the Message RAM.

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Output Buffer (OBF)

For read access to a message buffer configured in the Message RAM the Message Handler transfers the selected message buffer to the Output Buffer. After the transfer has completed, the Host can read the header and data section of the transferred message buffer from the Output Buffer.

Message Handler (MHD)

The E-Ray Message Handler controls data transfers between the following components:

• Input / Output Buffer and Message RAM

• Transient Buffer RAMs of the two FlexRay Protocol Controllers and Message RAM

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Message RAM (MRAM)

The Message RAM consists of a single-ported RAM that stores up to 128 FlexRay message buffers together with the related configuration data (header and data partition).

Transient Buffer RAM (TBF A/B)

Stores the data section of two complete messages.

FlexRay Channel Protocol Controller (PRT A/B)

The FlexRay Channel Protocol Controllers consist of shift register and FlexRay protocol FSM. They are connected to the Transient Buffer RAMs for intermediatemessage storage and to thephysical layer via bus driver BD.

They perform the following functionality:

• Control and check of bit timing

• Reception / transmission of FlexRay frames and symbols

• Check of header CRC

• Generation / check of frame CRC

• Interfacing to bus driver The FlexRay Channel Protocol Controllers have interfaces to:

• Physical Layer (bus driver)

• Transient Buffer RAM

• Message Handler

• Global Time Unit

• System Universal Control

• Frame and Symbol Processing

• Network Management

• Interrupt Control

Global Time Unit (GTU)

The Global Time Unit performs the following functions:

• Generation of microtick

• Generation of macrotick

• Fault tolerant clock synchronization by FTM algorithm

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- rate correction

- offset correction

• Cycle counter

• Timing control of static segment

• Timing control of dynamic segment (minislotting)

• Support of external clock correction

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System Universal Control (SUC)

The System Universal Control controls the following functions:

• Configuration

• Wakeup

• Startup

• Normal Operation

• Passive Operation

• Monitor Mode

Frame and Symbol Processing (FSP)

The Frame and Symbol Processing controls the following functions:

• Checks the correct timing of frames and symbols

• Tests the syntactical and semantical correctness of received frames

• Sets the slot status flags

Network Management (NEM)

Revision 1.2.5 E-Ray

Handles the network management vector.

Interrupt Control (INT)

The Interrupt Controller performs the following functions:

• Provides error and status interrupt flags

• Enable / disable interrupt sources

• Assignment of interrupt sources to one of the two module interrupt lines

• Enable / disable module interrupt lines

• Manages the two interrupt timers

• Stop watch time capturing

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3. Generic Interface

The Generic Interface encapsulates the synthesizable code of the E-Ray design (E-Ray core).All customer specific components like Customer CPU Interfaces and RAM blocks are connected to the Generic Interface.

The Generic CPU Interface connects the E-Ray module to a customer specific Host CPU via the Customer CPU Interface. It supports 8/16/32-bit access modes.

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4. Programmer’s Model

4.1 Register Map

The E-Ray module allocates an address space of 2 Kbytes (0x0000 to 0x07FF). The registers are organized as 32-bit registers. 8/16-bit accesses are also supported. Host access to the Message RAM is done via the Input and Output Buffers. They buffer data to be transferred to and from the Message RAM under control of the Message Handler, avoiding conflicts between Host accesses and message reception / transmission. Addresses 0x0000 to 0x000F are reserved for customer specific purposes. All functions related to these addresses are located in the Customer CPU Interface.

The assignment of the message buffers is done according to the scheme shown in Table 1 below. The number N of available message buffers depends on the payload length of the configured message buffers. The maximum number of message buffers is 128. The maximum payload length supported is 254 bytes.

The message buffers are separated into three consecutive groups:

• Static Buffers - Transmit / receive buffers assigned to static segment

• Static + Dynamic Buffers - Transmit / receive buffers assigned to static or dynamic segment

• FIFO - Receive FIFO The message buffer separation configuration can be changed only in DEFAULT_CONFIG or CON-

FIG state only by programming register MRC (see 4.7.1 Message RAM Configuration (MRC)). The first group starts with message buffer0 andconsists of static message buffers only. Message buff-

er 0 is dedicated to hold the startup / sync frame or the single slot frame, if the node transmits one, as configured by SUCC1.TXST, SUCC1.TXSY, and SUCC1.TSM. In addition, message buffer 1 may be used for sync frame transmission in case that sync frames or single-slot frames should have different payloads on the two channels. In this case bit MRC.SPLM has to be programmed to ’1’ and message buffers 0 and 1 have to be configured with the key slot ID and can be (re)configured in DEFAULT_CONFIG or CONFIG state only.

The second group consists of message buffers assigned to the static or to the dynamic segment. Message buffers belonging to this group may be reconfigured during run time from dynamic to static or vice versa depending on the state of MRC.SEC[1:0].

The message buffers belonging to the third group are concatenated to a single receive FIFO.

Message Buffer 0 ⇓ Static Buffers

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Message Buffer 1

⇓ Static + Dynamic ⇐ FDB

…

Message Buffer N-1 Message Buffer N ⇐ LCB

Table 1: Assignment of message buffers

Buffers

⇓ FIFO ⇐ FFB

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Address Symbol Name

Customer Registers

0x0000 0x0004 0x0008

see Customer CPU Interface Speciﬁcation CIF

0x000C

Special Registers

0x0010-

0x0018

reserved (3)

0x001C LCK Lock Register 24

Interrupt Registers

0x0020 EIR Error Interrupt Register 25 0x0024 SIR Status Interrupt Register 28 0x0028 EILS Error Interrupt Line Select 31 0x002C SILS Status Interrupt Line Select 32 0x0030 EIES Error Interrupt Enable Set 33 0x0034 EIER Error Interrupt Enable Reset 33 0x0038 SIES Status Interrupt Enable Set 34 0x003C SIER Status Interrupt Enable Reset 34 0x0040 ILE Interrupt Line Enable 35 0x0044 T0C Timer 0 Conﬁguration 36 0x0048 T1C Timer 1 Conﬁguration 37 0x004C STPW1 Stop Watch Register 1 38 0x0050 STPW2 Stop Watch Register 2 39

0x0054 -

0x007C

reserved (11)

CC Control Registers

0x0080 SUCC1 SUC Conﬁguration Register 1 40

0x0088 SUCC3 SUC Conﬁguration Register 3 45 0x008C NEMC NEM Conﬁguration Register 46 0x0090 PRTC1 PRT Conﬁguration Register 1 47 0x0094 PRTC2 PRT Conﬁguration Register 2 48 0x0098 MHDC MHD Conﬁguration Register 49

manual_programmers_model.fm

0x009C reserved (1)

Page

Reset

0000 0000

0000 0000 0000 0000 0000 0000 0303 FFFF 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002 0000 0000 0000 0000 0000

0000 0000

0C40 1080 0100 0504 0000 0011 0000 0000 084C 0633 0F2D 0A0E 0000 0000 0000 0000

Acc Block

r/w GIF

r/w r/w r/w r/w r/w r/w r/w

INT r/w r/w r/w r/w r/w r/w

r/w

SUC0x0084 SUCC2 SUC Conﬁguration Register 2 45

r/w r/w r/w NEM r/w

PRT

r/w r/w MHD r

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Address Symbol Name

0x00A0 GTUC1 GTU Conﬁguration Register 1 50 0x00A4 GTUC2 GTU Conﬁguration Register 2 50 0x00A8 GTUC3 GTU Conﬁguration Register 3 51 0x00AC GTUC4 GTU Conﬁguration Register 4 52 0x00B0 GTUC5 GTU Conﬁguration Register 5 53 0x00B4 GTUC6 GTU Conﬁguration Register 6 53 0x00B8 GTUC7 GTU Conﬁguration Register 7 54 0x00BC GTUC8 GTU Conﬁguration Register 8 54 0x00C0 GTUC9 GTU Conﬁguration Register 9 55 0x00C4 GTUC10 GTU Conﬁguration Register 10 55 0x00C8 GTUC11 GTU Conﬁguration Register 11 56

0x00CC -

0x00FC

reserved (13)

CC Status Registers

0x0100 CCSV CC Status Vector 57 0x0104 CCEV CC Error Vector 60

0x0108 -

0x010C

reserved (2)

0x0110 SCV Slot Counter Value 61 0x0114 MTCCV Macrotick and Cycle Counter Value 61 0x0118 RCV Rate Correction Value 62 0x011C OCV Offset Correction Value 62 0x0120 SFS Sync Frame Status 63 0x0124 SWNIT Symbol Window and NIT Status 64 0x0128 ACS Aggregated Channel Status 66 0x012C reserved (1)

0x0130 -

0x0168

ESIDn Even Sync ID [1…15] 68

0x016C reserved (1)

0x0170 -

0x01A8

OSIDn Odd Sync ID [1…15] 69

0x01AC reserved (1)

0x01B0 -

0x01B8

0x01BC -

0x02FC

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NMVn Network Management Vector [1…3] 70

reserved (81)

Message Buffer Control Registers

0x0300 MRC Message RAM Conﬁguration 71 0x0304 FRF FIFO Rejection Filter 73 0x0308 FRFM FIFO Rejection Filter Mask 74 0x030C FCL FIFO Critical Level 74

Page

Reset

0000 0280 0002 000A 0202 0000 0008 0007 0E00 0000 0002 0000 0002 0004 0000 0002 0000 0101 0002 0005 0000 0000

0000 0000

0010 4000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

0000 0000

0180 0000 0180 0000 0000 0000

0000 0080

Acc Block

r/w r/w r/w r/w r/w

GTU

r/w r/w r/w r/w r/w r/w

SUC

r r r

r r r r r

GTU

r/w

r r r r r r NEM

r/w r/w

MHD

r/w r/w

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Address Symbol Name

Message Buffer Status Registers

0x0310 MHDS Message Handler Status 75 0x0314 LDTS Last Dynamic Transmit Slot 76 0x0318 FSR FIFO Status Register 77 0x031C MHDF Message Handler Constraints Flags 78 0x0320 TXRQ1 Transmission Request 1 80 0x0324 TXRQ2 Transmission Request 2 80 0x0328 TXRQ3 Transmission Request 3 80 0x032C TXRQ4 Transmission Request 4 80 0x0330 NDAT1 New Data 1 81 0x0334 NDAT2 New Data 2 81 0x0338 NDAT3 New Data 3 81 0x033C NDAT4 New Data 4 81 0x0340 MBSC1 Message Buffer Status Changed 1 82 0x0344 MBSC2 Message Buffer Status Changed 2 82 0x0348 MBSC3 Message Buffer Status Changed 3 82 0x034C MBSC4 Message Buffer Status Changed 4 82

0x0350 -

0x03EC

reserved (40)

Identiﬁcation Registers

0x03F0 CREL Core Release Register 83 0x03F4 ENDN Endian Register 83

0x03F8 -

0x03FC

reserved (2)

Input Buffer

0x0400 -

0x04FC

WRDSn Write Data Section [1…64] 84

0x0500 WRHS1 Write Header Section 1 85 0x0504 WRHS2 Write Header Section 2 86 0x0508 WRHS3 Write Header Section 3 86 0x050C reserved (1) 0x0510 IBCM Input Buffer Command Mask 87 0x0514 IBCR Input Buffer Command Request 88

0x0518 -

0x05FC

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0x0600 -

0x06FC

RDDSn Read Data Section [1…64] 89

reserved (58)

Output Buffer

0x0700 RDHS1 Read Header Section 1 90 0x0704 RDHS2 Read Header Section 2 91 0x0708 RDHS3 Read Header Section 3 92 0x070C MBS Message Buffer Status 93 0x0710 OBCM Output Buffer Command Mask 96 0x0714 OBCR Output Buffer Command Request 97

0x0718 -

0x07FC

reserved (58)

Page

Reset

0000 0080 0000 0000 0000 0000

0000 0000 0000 0000

0000 0000

[release info]

8765 4321

0000 0000

0000 0000 0000 0000

0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

0000 0000

0000 0000 0000 0000

0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

0000 0000

Acc Block

r/w

r r

r/w

r r r r

MHD

r r r r r r r r

GIF

r r

r/w r/w

IBF

r/w r/w r/w

r r

OBF

r r/w r/w

Table 2: E-Ray register map

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4.2 Customer Registers

The address space from 0x0000to 0x000F is reserved for customer-specificregisters. These registers, if implemented, are located in the Customer CPU Interface block. A description can be found in the specific Customer CPU Interface specification document.

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4.3 Special Registers

4.3.1 Lock Register (LCK)

The Lock Register is write-only. Reading the register will return 0x0000 0000.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LCK R0000000000000000

0x001C W

Reset 0 0 0 0000000000000

Bit 1514131211109876543210

R0000000000000000

W CLK7 CLK6 CLK5 CLK4 CLK3 CLK2 CLK1 CLK0

Reset 0 000000000000000

CLK[7:0] Conﬁguration Lock Key

To leave CONFIG state by writing SUCC1.CMD[3:0] (commands READY, MONITOR_MODE, ATM, LOOP_BACK), the write operation has to be directly preceded by two write accesses to the Configuration Lock Key (unlock sequence). If the write sequence below is interrupted by other write accesses between the second write to the Configuration Lock Key and the write access to the SUCC1 register, the CC remains in CONFIG state and the sequence has to be repeated.

First write: LCK.CLK[7:0] = "1100 1110" (0xCE) Second write: LCK.CLK[7:0] = "0011 0001" (0x31) Third write: SUCC1.CMD[3:0]

Note: In case that the Host uses 8/16-bit accesses to write CLK[7:0], the programmer has to ensure

that no "dummy accesses" e.g. to the remaining register bytes / words are inserted by the compiler.

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4.4 Interrupt Registers

4.4.1 Error Interrupt Register (EIR)

The flags are set when the CC detects one of the listed error conditions. The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’has no effect on the flag. A hard reset will also clear the register.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

EIR R00000

0x0020 W

Reset 0 000000000000000

Bit 1514131211109876543210

R0000

Reset 0 000000000000000

TABB LTVB EDB

MHF IOBA IIBA EFA RFO PERR CCL CCF SFO SFBM CNA PEMC

PEMC POC Error Mode Changed

This flag is set whenever the error mode signalled by CCEV.ERRM[1:0] has changed. 1 = Error mode has changed 0 = Error mode has not changed

00000

TABA LTVA EDA

CNA Command Not Accepted

The ﬂag signals that the write access to the CHI command vector SUCC1.CMD[3:0] was not successful because the requested command was not valid in the actual POC state, or because the CHI command was locked (CCL = ’1’).

1 = CHI command not accepted 0 = CHI command accepted

SFBM Sync Frames Below Minimum

This ﬂag signals that the number of sync frames received during the last communication cycle was below the limit required by the FlexRay protocol. May be set during startup and therefore should be cleared by the Host after the CC entered NORMAL_ACTIVE state.

1 = Less than the required minimum of sync frames received 0 = Sync node: 1 or more sync frames received, non-sync node: 2 or more sync frames received

SFO Sync Frame Overﬂow

Set when either the number of sync frames received during the last communication cycle or the total number of sync frames received during the last double cycle exceeds the maximum number of sync frames as defined by GTUC2.SNM[3:0].

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1 = More sync frames received than conﬁgured by GTUC2.SNM[3:0] 0 = Number of received sync frames ≤ GTUC2.SNM[3:0]

CCF Clock Correction Failure

This flag is set at the end of the cycle whenever one of the following errors occurred:

• Missing offset and / or rate correction

• Clock correction limit reached The clock correction status is monitored in registers CCEV and SFS. A failure may occur during

startup, therefore bit CCF should be cleared by the Host after the CC entered NORMAL_ACTIVE state.

1 = Clock correction failed 0 = No clock correction error

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CCL CHI Command Locked

The ﬂag signals that the write access to the CHI command vector SUCC1.CMD[3:0] was not successful because the execution of the previous CHI command has not yet completed. In this case bit CNA is also set to ’1’.

1 = CHI command not accepted 0 = CHI command accepted

PERR Parity Error

The ﬂag signals a parity error to the Host. It is set whenever one of the ﬂags MHDS.PIBF, MHDS.POBF, MHDS.PMR, MHDS.PTBF1, MHDS.PTBF2 changes from ’0’ to ’1’.

1 = Parity error detected 0 = No parity error detected

RFO Receive FIFO Overrun

The ﬂag is set by the CC when a receive FIFO overrun is detected. When a receive FIFO overrun occurs, the oldest message is overwritten with the actual received message. The actual state of the FIFO is monitored in register FSR.

1 = A receive FIFO overrun has been detected 0 = No receive FIFO overrun detected

EFA Empty FIFO Access

This ﬂag is set by the CC when the Host requests the transfer of a message from the receive FIFO via Output Buffer while the receive FIFO is empty.

1 = Host access to empty FIFO occurred 0 = No Host access to empty FIFO occurred

IIBA Illegal Input Buffer Access

This ﬂag is set by the CC when the Host wants to modify a message buffer via Input Buffer while the CC is not in CONFIG or DEFAULT_CONFIG state and one of the following conditions applies:

1) The Host writes to the Input Buffer Command Request register to modify the

• Header section of message buffer 0, 1 if conﬁgured for transmission in key slot

• Header section of static message buffers with buffer number < MRC.FDB[7:0] while MRC.SEC[1:0] = "01"

• Header section of any static or dynamic message buffer while MRC.SEC[1:0] = "1x"

• Header and / or data section of any message buffer belonging to the receive FIFO

2) The Host writes to any register of the Input Buffer while IBCR.IBSYH is set to ’1’.

1 = Illegal Host access to Input Buffer occurred 0 = No illegal Host access to Input Buffer occurred

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IOBA Illegal Output buffer Access

This ﬂag is set by the CC when the Host requests the transfer of a message buffer from the Message RAM to the Output Buffer while OBCR.OBSYS is set to ’1’.

1 = Illegal Host access to Output Buffer occurred 0 = No illegal Host access to Output Buffer occurred

MHF Message Handler Constraints Flag

The ﬂag signals a Message Handler constraints violation condition. It is set whenever one of the ﬂags MHDF.SNUA, MHDF.SNUB, MHDF.FNFA, MHDF.FNFB, MHDF.TBFA, MHDF.TBFB, MHDF.WAHP changes from ’0’ to ’1’.

1 = Message Handler failure detected 0 = No Message Handler failure detected

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Channel-specific error flags: EDA Error Detected on Channel A

This bit is set whenever one of the ﬂags ACS.SEDA, ACS.CEDA, ACS.CIA, ACS.SBVA changes from ’0’ to ’1’.

1 = Error detected on channel A 0 = No error detected on channel A

LTVA Latest Transmit Violation Channel A

The ﬂag signals a latest transmit violation on channel A to the Host. 1 = Latest transmit violation detected on channel A 0 = No latest transmit violation detected on channel A

TABA Transmission Across Boundary Channel A

The ﬂag signals to the Host that a transmission across a slot boundary occurred for channel A. 1 = Transmission across slot boundary detected on channel A 0 = No transmission across slot boundary detected on channel A

EDB Error Detected on Channel B

This bit is set whenever one of the ﬂags ACS.SEDB, ACS.CEDB, ACS.CIB, ACS.SBVB changes from ’0’ to ’1’.

1 = Error detected on channel B 0 = No error detected on channel B

LTVB Latest Transmit Violation Channel B

The ﬂag signals a latest transmit violation on channel B to the Host. 1 = Latest transmit violation detected on channel B 0 = No latest transmit violation detected on channel B

TABB Transmission Across Boundary Channel B

The ﬂag signals to the Host that a transmission across a slot boundary occurred for channel B. 1 = Transmission across slot boundary detected on channel B 0 = No transmission across slot boundary detected on channel B

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4.4.2 Status Interrupt Register (SIR)

The flags are set when the CC detects one of the listed events. The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect on the flag. A hard reset will also clear the register.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SIR R000000

0x0024 W

Reset 0 000000000000000

Bit 1514131211109876543210

SDS MBSI SUCS SWE TOBC TIBC TI1 TI0 NMVC RFCL RFNE RXI TXI CYCS CAS WST

Reset 0 000000000000000

MTSB WUPB

000000

MTSA WUPA

WST Wakeup Status

This flag is set when the wakeup status vector CCSV.WSV[2:0] is changed by a protocol event. 1 = Wakeup status changed 0 = Wakeup status unchanged

CAS Collision Avoidance Symbol

This ﬂag is set by the CC during STARTUP state when a CAS or a potential CAS was received. 1 = Bit pattern matching the CAS symbol received 0 = No bit pattern matching the CAS symbol received

CYCS Cycle Start Interrupt

This ﬂag is set by the CC when a communication cycle starts. 1 = Communication cycle started 0 = No communication cycle started

TXI Transmit Interrupt

This ﬂag is set by the CC at the end of frame transmission if bit MBI in the respective message buffer is set to ’1’ (see Table 17).

1 = At least one frame was transmitted from a transmit buffer with MBI = ’1’ 0 = No frame transmitted from a transmit buffer with MBI = ’1’

RXI Receive Interrupt

This ﬂag is set by the CC whenever the set condition of a message buffers ND ﬂag is fulﬁlled (see 4.8.6 New Data 1/2/3/4 (NDAT1/2/3/4)), and if bit MBI of that message buffer is set to ’1’ (see Table 17).

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1 = At least one ND ﬂag of a receive buffer with MBI = ’1’ has been set to ’1’ 0 = No ND ﬂag of a receive buffer with MBI = ’1’ has been set to ’1’

RFNE Receive FIFO Not Empty

This ﬂag is set by the CC when a received valid frame was stored into the empty receive FIFO. The actual state of the receive FIFO is monitored in register FSR.

1 = Receive FIFO is not empty 0 = Receive FIFO is empty

RFCL Receive FIFO Critical Level

This ﬂag is set when the receive FIFO ﬁll level FSR.RFFL[7:0] is equal or greater than the critical level as conﬁgured by FCL.CL[7:0].

1 = Receive FIFO critical level reached 0 = Receive FIFO below critical level

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NMVC Network Management Vector Changed

This interrupt flag signals a change in the Network Management Vector visible to the Host. 1 = Network management vector changed 0 = No change in the network management vector

TI0 Timer Interrupt 0

This flag is set whenever timer 0 matches the conditions configured in register T0C. A Timer Interrupt 0 is also signalled on pin eray_tint0.

1 = Timer Interrupt 0 occurred 0 = No Timer Interrupt 0

TI1 Timer Interrupt 1

This flag is set whenever timer 1 matches the conditions configured in register T1C. A Timer Interrupt 1 is also signalled on pin eray_tint1.

1 = Timer Interrupt 1 occurred 0 = No Timer Interrupt 1

TIBC Transfer Input Buffer Completed

This flag is set whenever a transfer from Input Buffer to the Message RAM has completed and IBCR.IBSYS has been reset by the Message Handler.

1 = Transfer between Input Buffer and Message RAM completed 0 = No transfer completed

TOBC Transfer Output Buffer Completed

This flag is set whenever a transfer from the Message RAM to the Output Buffer has completed and OBCR.OBSYS has been reset by the Message Handler.

1 = Transfer between Message RAM and Output Buffer completed 0 = No transfer completed

SWE Stop Watch Event

This flag is set after a stop watch activation when the actual cycle counter and macrotick value are stored in the Stop Watch register (see section 4.4.10 Stop Watch Register 1 (STPW1)).

1 = Stop Watch Event occurred 0 = No Stop Watch Event

SUCS Startup Completed Successfully

This flag is set whenever a startup completed successfully and the CC entered NORMAL_ACTIVE state.

1 = Startup completed successfully 0 = No startup completed successfully

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MBSI Message Buffer Status Interrupt

This ﬂag is set by the CC when the message buffer status MBS has changed if bit MBI of that message buffer is set (see Table 17).

1 = Message buffer status of at least one message buffer with MBI = ’1’ has changed 0 = No message buffer status change of message buffer with MBI = ’1’

SDS Start of Dynamic Segment

This ﬂag is set by the CC when the dynamic segment starts. 1 = Dynamic segment started 0 = Dynamic segment not yet started

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Channel-specific status flags: WUPA Wakeup Pattern Channel A

This ﬂag is set by the CC when a wakeup pattern was received on channel A. Only set when the CC is in WAKEUP, READY, or STARTUP state, or when in Monitor mode.

1 = Wakeup pattern received on channel A 0 = No wakeup pattern received on channel A

MTSA MTS Received on Channel A (vSS!ValidMTSA)

Media Access Test symbol received on channel A during the preceding symbol window. Updated by the CC for each channel at the end of the symbol window.

1 = MTS symbol received on channel A 0 = No MTS symbol received on channel A

WUPB Wakeup Pattern Channel B

This ﬂag is set by the CC when a wakeup pattern was received on channel B. Only set when the CC is in WAKEUP, READY, or STARTUP state, or when in Monitor mode.

1 = Wakeup pattern received on channel B 0 = No wakeup pattern received on channel B

MTSB MTS Received on Channel B (vSS!ValidMTSB)

Media Access Test symbol received on channel B during the preceding symbol window. Updated by the CC for each channel at the end of the symbol window.

1 = MTS symbol received on channel B 0 = No MTS symbol received on channel B

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4.4.3 Error Interrupt Line Select (EILS)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

EILS R00000

0x0028 W

Reset 0 0 0 0000000000000

Bit 1514131211109876543210

R0000

Reset 0 000000000000000

TABBL LTVBL EDBL

MHFL IOBAL IIBAL EFAL RFOL PERRL CCLL CCFL SFOL

00000

TABAL

SFBML

LTVAL EDAL

PEMCL

CNAL

The Error Interrupt Line Select register assigns an interruptgenerated by a specific errorinterrupt flag from register EIR to one of the two module interrupt lines:

1 = Interrupt assigned to interrupt line eray_int1 0 = Interrupt assigned to interrupt line eray_int0

PEMCL POC Error Mode Changed Interrupt Line CNAL Command Not Accepted Interrupt Line SFBML Sync Frames Below Minimum Interrupt Line SFOL Sync Frame Overﬂow Interrupt Line CCFL Clock Correction Failure Interrupt Line CCLL CHI Command Locked Interrupt Line PERRL Parity Error Interrupt Line RFOL Receive FIFO Overrun Interrupt Line EFAL Empty FIFO Access Interrupt Line IIBAL Illegal Input Buffer Access Interrupt Line IOBAL Illegal Output Buffer Access Interrupt Line MHFL Message Handler Constraints Flag Interrupt Line EDAL Error Detected on Channel A Interrupt Line LTVAL Latest Transmit Violation Channel A Interrupt Line TABAL Transmission Across Boundary Channel A Interrupt Line EDBL Error Detected on Channel B Interrupt Line

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LTVBL Latest Transmit Violation Channel B Interrupt Line TABBL Transmission Across Boundary Channel B Interrupt Line

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4.4.4 Status Interrupt Line Select (SILS)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SILS R000000

0x002C W

Reset 0 0 0 0001100000011

Bit 1514131211109876543210

SDSL MBSIL SUCSL SWEL

Reset 1 111111111111111

TOBCL

MTSBL WUPBL

TIBCL TI1L TI0L

000000

NMVCL

RFCLL RFNEL RXIL TXIL

CYCSL

MTSAL WUPAL

CASL WSTL

The Status Interrupt Line Select register assign an interrupt generated by a specific status interrupt flag from register SIR to one of the two module interrupt lines:

1 = Interrupt assigned to interrupt line eray_int1 0 = Interrupt assigned to interrupt line eray_int0

WSTL Wakeup Status Interrupt Line CASL Collision Avoidance Symbol Interrupt Line CYCSL Cycle Start Interrupt Line TXIL Transmit Interrupt Line RXIL Receive Interrupt Line RFNEL Receive FIFO Not Empty Interrupt Line RFCLL Receive FIFO Critical Level Interrupt Line NMVCL Network Management Vector Changed Interrupt Line TI0L Timer Interrupt 0 Line TI1L Timer Interrupt 1 Line TIBCL Transfer Input Buffer Completed Interrupt Line TOBCL Transfer Output Buffer Completed Interrupt Line SWEL Stop Watch Event Interrupt Line SUCSL Startup Completed Successfully Interrupt Line MBSIL Message Buffer Status Interrupt Line SDSL Start of Dynamic Segment Interrupt Line

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WUPAL Wakeup Pattern Channel A Interrupt Line MTSAL Media Access Test Symbol Channel A Interrupt Line WUPBL Wakeup Pattern Channel B Interrupt Line MTSBL Media Access Test Symbol Channel B Interrupt Line

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4.4.5 Error Interrupt Enable Set / Reset (EIES, EIER)

The settings in the Error Interrupt Enable register determine which status changes in the Error Interrupt Register will result in an interrupt.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

EIES,R R0 0 0 0 0

S:0x0030 R:0x0034

Reset 0 0 0 0 000000000000

Bit 1514131211109876543210

R0000

Reset 0 000000000000000

TABBE LTVBE EDBE

MHFE IOBAE IIBAE EFAE RFOE PERRE CCLE CCFE SFOE

00000

TABAE

SFBME

LTVAE EDAE

PEMCE

CNAE

The enable bits are set by writing to address 0x0030 and reset by writing to address 0x0034. Writing a ’1’ sets / resets the specific enable bit, writing a ’0’ has no effect. Reading from both addresses will result in the same value.

1 = Interrupt enabled 0 = Interrupt disabled

PEMCE POC Error Mode Changed Interrupt Enable CNAE Command Not Accepted Interrupt Enable SFBME Sync Frames Below Minimum Interrupt Enable SFOE Sync Frame Overﬂow Interrupt Enable CCFE Clock Correction Failure Interrupt Enable CCLE CHI Command Locked Interrupt Enable PERRE Parity Error Interrupt Enable RFOE Receive FIFO Overrun Interrupt Enable EFAE Empty FIFO Access Interrupt Enable IIBAE Illegal Input Buffer Access Interrupt Enable IOBAE Illegal Output Buffer Access Interrupt Enable MHFE Message Handler Constraints Flag Interrupt Enable EDAE Error Detected on Channel A Interrupt Enable

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LTVAE Latest Transmit Violation Channel A Interrupt Enable TABAE Transmission Across Boundary Channel A Interrupt Enable EDBE Error Detected on Channel B Interrupt Enable LTVBE Latest Transmit Violation Channel B Interrupt Enable TABBE Transmission Across Boundary Channel B Interrupt Enable

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4.4.6 Status Interrupt Enable Set / Reset (SIES, SIER)

The settings in the Status Interrupt Enable register determine which status changes in the Status Interrupt Register will result in an interrupt.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SIES,R R0 0 0 0 0 0

S:0x0038

R:0x003C

Reset 0 0 0 0 000000000000

Bit 1514131211109876543210

SDSE MBSIE SUCSE SWEE

Reset 0 000000000000000

TOBCE

MTSBE WUPBE

TIBCE TI1E TI0E

000000

NMVCE

RFCLE RFNEE RXIE TXIE

CYCSE

MTSAE WUPAE

CASE WSTE

The enable bits are set by writing to address 0x0038 and reset by writing to address 0x003C. Writing a ’1’ sets / resets the specific enable bit, writing a ’0’ has no effect. Reading from both addresses will result in the same value.

1 = Interrupt enabled 0 = Interrupt disabled

WSTE Wakeup Status Interrupt Enable CASE Collision Avoidance Symbol Interrupt Enable CYCSE Cycle Start Interrupt Enable TXIE Transmit Interrupt Enable RXIE Receive Interrupt Enable RFNEE Receive FIFO Not Empty Interrupt Enable RFCLE Receive FIFO Critical Level Interrupt Enable NMVCE Network Management Vector Changed Interrupt Enable TI0E Timer Interrupt 0 Enable TI1E Timer Interrupt 1 Enable TIBCE Transfer Input Buffer Completed Interrupt Enable TOBCE Transfer Output Buffer Completed Interrupt Enable SWEE Stop Watch Event Interrupt Enable

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SUCSE Startup Completed Successfully Interrupt Enable MBSIE Message Buffer Status Interrupt Enable SDSE Start of Dynamic Segment Interrupt Enable WUPAE Wakeup Pattern Channel A Interrupt Enable MTSAE MTS Received on Channel A Interrupt Enable WUPBE Wakeup Pattern Channel B Interrupt Enable MTSBE MTS Received on Channel B Interrupt Enable

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4.4.7 Interrupt Line Enable (ILE)

Each of the two interrupt lines to the Host (eray_int0, eray_int1) can be enabled / disabled separately by programming bit EINT0 and EINT1.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ILE R0000000000000000

0x0040 W

Reset 0 000000000000000

Bit 1514131211109876543210

R00000000000000

Reset 0 000000000000000

EINT1 EINT0

EINT0 Enable Interrupt Line 0

1 = Interrupt line eray_int0 enabled 0 = Interrupt line eray_int0 disabled

EINT1 Enable Interrupt Line 1

1 = Interrupt line eray_int1 enabled 0 = Interrupt line eray_int1 disabled

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4.4.8 Timer 0 Conﬁguration (T0C)

Absolute timer. Specifies in terms of cycle count and macrotick the point in time when the timer 0 interrupt occurs. When the timer 0 interrupt is asserted, output signal eray_tint0 is set to ’1’ for the duration of one macrotick and SIR.TI0 is set to ’1’.

Timer 0 can be activated as long as the POC is either in NORMAL_ACTIVE state or in NORMAL_PASSIVE state. Timer 0 is deactivated when leaving NORMAL_ACTIVE state or NORMAL_PASSIVE state except for transitions between the two states.

Before reconfiguration of the timer, the timer has to be halted first by writing bit T0RC to ’0’.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

T0C R0 0

0x0044 W

Reset 0 000000000000000

Bit 1514131211109876543210

Reset 0 000000000000000

T0MO13T0MO12T0MO11T0MO10T0MO9T0MO8T0MO7T0MO6T0MO5T0MO4T0MO3T0MO2T0MO1T0MO

T0CC6 T0CC5 T0CC4 T0CC3 T0CC2 T0CC1 T0CC0

000000

T0MS T0RC

T0RC Timer 0 Run Control

1 = Timer 0 running 0 = Timer 0 halted

T0MS Timer 0 Mode Select

1 = Continuous mode 0 = Single-shot mode

T0CC[6:0] Timer 0 Cycle Code

The 7-bit timer 0 cycle code determines the cycle set used for generation of the timer 0 interrupt. For details about the configuration of the cycle code see Section 5.7.2 Cycle Counter Filtering.

T0MO[13:0] Timer 0 Macrotick Offset

Configures the macrotick offset from the beginning of the cycle where the interrupt is to occur. The Timer 0 Interrupt occurs at this offset for each cycle of the cycle set.

Note: The configuration of timer 0 is compared against the macrotick counter value, there is no sep-

arate counter for timer 0.In case the CC leaves NORMAL_ACTIVEor NORMAL_PASSIVE state, or if timer 0 is halted by Host command, output signal eray_tint0 is reset to ’0’ immediately.

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4.4.9 Timer 1 Conﬁguration (T1C)

Relative timer. After the specified number of macroticks has expired, the timer 1 interrupt is asserted, output signal eray_tint1 is set to ’1’ for the duration of one macrotick and SIR.TI1 is set to ’1’.

Timer 1 can be activated as long as the POC is either in NORMAL_ACTIVE state or in NORMAL_PASSIVE state. Timer 1 is deactivated when leaving NORMAL_ACTIVE state or NORMAL_PASSIVE state except for transitions between the two states.

Before reconfiguration of the timer, the timer has to be halted first by writing bit T1RC to ’0’.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

T1C R0 0

0x0048 W

Reset 0 000000000000010

Bit 1514131211109876543210

R00000000000000

Reset 0 000000000000000

T1MC13T1MC12T1MC11T1MC

T1MC9 T1MC8 T1MC7 T1MC6 T1MC5 T1MC4 T1MC3 T1MC2 T1MC1 T1MC0

T1MS T1RC

T1RC Timer 1 Run Control

1 = Timer 1 running 0 = Timer 1 halted

T1MS Timer 1 Mode Select

1 = Continuous mode 0 = Single-shot mode

T1MC[13:0] Timer 1 Macrotick Count

When the configured macrotick count is reached the timer 1 interrupt is generated. Valid values are: 2 to 16383 MT in continuous mode

1 to 16383 MT in single-shot mode

Note: In case the CC leaves NORMAL_ACTIVE or NORMAL_PASSIVEstate, orif timer1 ishalt-

ed by Host command, output signal eray_tint1 is reset to ’0’ immediately.

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4.4.10 Stop Watch Register 1 (STPW1)

The stop watch is activated by a rising or falling edge on pin eray_stpwt, by an interrupt 0,1 event (rising edge on pin eray_int0 or eray_int1) or by theHost by writing bit SSWT to ’1’. With the macrotick counter increment following next to the stop watchactivation the actual cycle counter andmacrotick values are captured in register STPW1 while the slot counter values for channel A and B are captured in register STPW2.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

STPW1 R0 0 0x004C W

Reset 0 000000000000000

Bit 1514131211109876543210

R 0 0 SCCV5 SCCV4 SCCV3 SCCV2 SCCV1 SCCV0 0

Reset 0 000000000000000

SMTV13SMTV12SMTV11SMTV

SMTV9 SMTV8 SMTV7 SMTV6 SMTV5 SMTV4 SMTV3 SMTV2 SMTV1 SMTV0

EINT1 EINT0 EETP SSWT EDGE SWMS ESWT

ESWT Enable Stop Watch Trigger

If enabled an edge on input eray_stpwt or an interrupt 0,1 event (rising edge on pin eray_int0 or eray_int1) activates the stop watch. In single-shot mode this bit is reset to ’0’ after the actual cycle counter and macrotick value are stored in the Stop Watch register.

1 = Stop watch trigger enabled 0 = Stop watch trigger disabled

SWMS Stop Watch Mode Select

1 = Continuous mode 0 = Single-shot mode

EDGE Stop Watch Trigger Edge Select

1 = Rising edge 0 = Falling edge

SSWT Software Stop Watch Trigger

When the Host writes this bit to ’1’ the stop watch is activated. After the actual cycle counter and macrotick value are stored in the Stop Watch register this bit is reset to ’0’. The bit is only writeable while ESWT = ’0’.

1 = Stop watch activated by software trigger 0 = Software trigger reset

EETP Enable External Trigger Pin

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Enables stop watch trigger event via pin eray_stpwt if ESWT = ’1’. 1 = Edge on pin eray_stpwt triggers stop watch 0 = Stop watch trigger via pin eray_stpwt disabled

EINT0 Enable Interrupt 0 Trigger

Enables stop watch trigger by interrupt 0 event if ESWT = ’1’. 1 = Interrupt 0 event triggers stop watch 0 = Stop watch trigger by interrupt 0 disabled

EINT1 Enable Interrupt 1 Trigger

Enables stop watch trigger by interrupt 1event if ESWT = ’1’. 1 = Interrupt 1 event triggers stop watch 0 = Stop watch trigger by interrupt 1 disabled

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SCCV[5:0] Stop Watch Captured Cycle Counter Value

State of the cycle counter when the stop watch event occurred. Valid values are 0 to 63.

SMTV[13:0] Stop Watch Captured Macrotick Value

State of the macrotick counter when the stop watch event occurred. Valid values are 0 to 16000.

Note: Bits ESWT and SSWT cannot be set to ’1’ simultaneously. In this case the write access is ig-

nored, and both bits keep their previous values. Either the external stop watch trigger or the software stop watch trigger may be used.

4.4.11 Stop Watch Register 2 (STPW2)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

STPW2 R00000

0x0050 W

Reset 0 000000000000000

Bit 1514131211109876543210

R00000

Reset 0 000000000000000

SSCVB10SSCVB9SSCVB8SSCVB7SSCVB6SSCVB5SSCVB4SSCVB3SSCVB2SSCVB1SSCVB

SSCVA10SSCVA9SSCVA8SSCVA7SSCVA6SSCVA5SSCVA4SSCVA3SSCVA2SSCVA1SSCVA

SSCVA[10:0] Stop Watch Captured Slot Counter Value Channel A

State of the slot counter for channel A when the stop watch event occurred. Valid values are 0 to

2047.

SSCVB[10:0] Stop Watch Captured Slot Counter Value Channel B

State of the slot counter for channel B when the stop watch event occurred. Valid values are 0 to

2047.

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4.5 CC Control Registers

This section describes the registers provided by the CC to allow the Host to control the operation of the CC. The FlexRay protocol specification requires the Host to write application configuration data in CONFIG state only. Please consider that the configuration registers are not locked for writing in DEFAULT_CONFIG state.

The configuration data is resetwhen DEFAULT_CONFIGstate is entered from hardreset. Tochange POC state from DEFAULT_CONFIG to CONFIG state the Host has to apply CHI command CONFIG. If the Host wants the CC to leave CONFIG state, the Host has to proceed as described in Section

4.3.1 Lock Register (LCK). All bits marked with an asterisk * can be updated in DEFAULT_CONFIG or CONFIG state only!

4.5.1 SUC Conﬁguration Register 1 (SUCC1)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SUCC1 R0000

0x0080 W

Reset 0 000110001000000

CCHB* CCHA* MTSB* MTSA*

HCSE* TSM*

WUCS*

PTA4* PTA3* PTA2* PTA1* PTA0*

Bit 1514131211109876543210

CSA4* CSA3* CSA2* CSA1* CSA0*

Reset 0 001000010000000

TXSY* TXST*

PBSY 0 0 0

CMD3 CMD2 CMD1 CMD0

CMD[3:0] CHI Command Vector

The Host may write any CHI command at any time, but certain commands are enabled only in certain POC states. If a command is not enabled, it will not be executed, the CHI command vector CMD[3:0] will be reset to "0000" = command_not_accepted, and flag EIR.CNA will be set to ’1’. In case the previous CHI command has not yet completed, EIR.CCL is set to ’1’ together with EIR.CNA; the CHI command needs to be repeated. Except for HALT state, a POC state change command applied while the CC is already in the requested POC state will be ignored.

0000 = command_not_accepted 0001 = CONFIG 0010 = READY 0011 = WAKEUP 0100 = RUN

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0101 = ALL_SLOTS 0110 = HALT 0111 = FREEZE 1000 = SEND_MTS 1001 = ALLOW_COLDSTART 1010 = RESET_STATUS_INDICATORS 1011 = MONITOR_MODE 1100 = CLEAR_RAMS 1101 = reserved 1110 = reserved 1111 = reserved

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Reading CMD[3:0] shows whether the last CHI command was accepted. The actual POC state is monitored by CCSV.POCS[5:0]. The reserved CHI commands belong to the hardware test functions.

command_not_accepted CMD[3:0] is reset to "0000" due to one of the following conditions:

• Illegal command applied by the Host

• Host applied command to leave CONFIG state without preceding conﬁg lock key

• Host applied new command while execution of the previous Host command has not completed

• Host writes command_not_accepted

When CMD[3:0] is reset to "0000", EIR.CNA is set, and - if enabled - an interrupt is generated. Commands which are not accepted are not executed.

CONFIG

Go to POC state CONFIG when called in POC states DEFAULT_CONFIG, READY, or in MONITOR_MODE. When called in HALT state the CC transits to POC state DEFAULT_CONFIG. When called in any other state, CMD[3:0] will be reset to "0000" = command_not_accepted.

READY

Go to POC state READY when called in POC states CONFIG, NORMAL_ACTIVE, NORMAL_PASSIVE, STARTUP, or WAKEUP. When called in any other state, CMD[3:0] will be reset to "0000" = command_not_accepted.

WAKEUP

Go to POC state WAKEUP when called in POC state READY. When called in any other state,

CMD[3:0] will be reset to "0000" = command_not_accepted. RUN

Go to POC state STARTUP when called in POC state READY. When called in any other state,

CMD[3:0] will be reset to "0000" = command_not_accepted. ALL_SLOTS

Leave SINGLE slot mode after successful startup / integration at the next end of cycle when called in POC states NORMAL_ACTIVE or NORMAL_PASSIVE. When called in any other state, CMD[3:0] will be reset to "0000" = command_not_accepted.

HALT

Set halt request CCSV.HRQ and go to POC state HALT at the next end of cycle when called in POC states NORMAL_ACTIVE or NORMAL_PASSIVE. When called in any other state,

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CMD[3:0] will be reset to "0000" = command_not_accepted. FREEZE

Set the freeze status indicator CCSV.FSI and go to POC state HALT immediately. Can be called from any state.

SEND_MTS

Send single MTS symbol during the next following symbol window on the channel conﬁgured by MTSA, MTSB, when called in POC state NORMAL_ACTIVE after CC entered ALL slot mode (CCSV.SLM[1:0] = "11"). When called in any other state, or when called while a previ- ously requested MTS has not yet been transmitted, CMD[3:0] will be reset to "0000" = command_not_accepted.

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ALLOW_COLDSTART

The command resets CCSV.CSI to enable the node to become leading coldstarter. When called in states DEFAULT_CONFIG, CONFIG, HALT, or MONITOR_MODE, CMD[3:0] will be reset to "0000" = command_not_accepted. To become leading coldstarter it is also required that both TXST and TXSY are set.

RESET_STATUS_INDICATORS

Resets status ﬂags CCSV.CSNI, CCSV.CSAI, and CCSV.WSV[2:0] to their default values. May be called in POC states READY and STARTUP. When called in any other state, CMD[3:0] will be reset to "0000" = command_not_accepted.

MONITOR_MODE

Enter MONITOR_MODE when called in POC state CONFIG. In this mode the CC is able to receive FlexRay frames and wakeup pattern. It is also able to detect coding errors. The temporal integrity of received frames is not checked. This mode can be used for debugging purposes, e.g. in case that the startup of a FlexRay network fails. When called in any other state, CMD[3:0] will be reset to "0000" = command_not_accepted. For details see 5.5.4 MONITOR_MODE

CLEAR_RAMS

Sets MHDS.CRAM when called in DEFAULT_CONFIG or CONFIG state. When called in any other state, CMD[3:0] will be reset to "0000" = command_not_accepted. MHDS.CRAM is also set when the CC leaves hard reset. By setting MHDS.CRAM all internal RAM blocks are initialized to zero. During the initialization of the RAMs, PBSY will show POC busy. Access to the configuration and status registers is possible during execution of CHI command CLEAR_RAMS.

The initialization of the E-Ray internal RAM blocks requires 2048 eray_bclk cycles. There should be no Host access to IBF or OBF during initialization of the internal RAM blocks after hard reset or after assertion of CHI command CLEAR_RAMS. Before asserting CHI command CLEAR_RAMS the Host should make sure that no transfer between Message RAM and IBF / OBF or the Transient Buffer RAMs is ongoing. This command also resets the Message Buffer Status registers MHDS, LDTS, FSR, MHDF, TXRQ1/2/3/4, NDAT1/2/3/4, and MBSC1/2/3/4.

Note: All accepted commands with exception of CLEAR_RAMS and SEND_MTS will cause a

change of register CCSV after at most 8 cycles of the slower of the two clocks eray_bclk and eray_sclk, counted from the falling edge of the CHI input signal eray_select, assumed that POC was not busy when the command was applied and that no POC state change was forced by bus activity in that time frame. Reading register CCSV will show data that is delayed by synchronization from eray_sclk to eray_bclk domain and bythe Host-specific CPUinterface.

PBSY POC Busy

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Signals that the POC is busy and cannot accept a command from the Host. CMD[3:0] is locked against write accesses. Set to ’1’ after hard reset during initialization of internal RAM blocks.

1 = POC is busy, CMD[3:0] locked 0 = POC not busy, CMD[3:0] writeable

TXST Transmit Startup Frame in Key Slot (pKeySlotUsedForStartup)

Deﬁnes whether the key slot is used to transmit startup frames. The bit can be modiﬁed in DEFAULT_CONFIG or CONFIG state only.

1 = Key slot used to transmit startup frame, node is leading or following coldstarter 0 = No startup frame transmission in key slot, node is non-coldstarter

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TXSY Transmit Sync Frame in Key Slot (pKeySlotUsedForSync)

Deﬁnes whether the key slot is used to transmit sync frames. The bit can be modiﬁed in DEFAULT_CONFIG or CONFIG state only.

1 = Key slot used to transmit sync frame, node is sync node 0 = No sync frame transmission in key slot, node is neither sync nor coldstart node

Note: The protocol requires that both bits TXST and TXSY are set for coldstart nodes. CSA[4:0] Cold Start Attempts (gColdStartAttempts)

Conﬁgures the maximum number of attempts that a cold starting node is permitted to try to start up the network without receiving any valid response from another node. It can be modiﬁed in DEFAULT_CONFIG or CONFIG state only. Must be identical in all nodes of a cluster. Valid values are 2 to 31.

PTA[4:0] Passive to Active (pAllowPassiveToActive)

Deﬁnes the number of consecutive even / odd cycle pairs that must have valid clock correction terms before the CC is allowed to transit from NORMAL_PASSIVE to NORMAL_ACTIVE state. If set to "00000" the CC is not allowed to transit from NORMAL_PASSIVE to NORMAL_ACTIVE state. It can be modiﬁed in DEFAULT_CONFIG or CONFIG state only. Valid values are 0 to 31 even / odd cycle pairs.

WUCS Wakeup Channel Select (pWakeupChannel)

With this bit the Host selects the channel on which the CC sends the Wakeup pattern. The CC ignores any attempt to change the status of this bit when not in DEFAULT_CONFIG or CONFIG state.

1 = Send wakeup pattern on channel B 0 = Send wakeup pattern on channel A

TSM Transmission Slot Mode (pSingleSlotEnabled)

Selects the initial transmission slot mode. In SINGLE slot mode the CC may only transmit in the preconﬁgured key slot. The key slot ID is conﬁgured in the header section of message buffer 0 respectively message buffers 0 and 1 depending on bit MRC.SPLM. In case TSM = ’1’, message buffer 0 respectively message buffers 0,1 can be (re)configured in DEFAULT_CONFIG or CONFIG state only. In ALL slot mode the CC may transmit in all slots. TSM is a conﬁguration bit which can only be set / reset by the Host. The bit can be written in DEFAULT_CONFIG or CONFIG state only. The CC changes to ALL slot mode when the Host successfully applied the ALL_SLOTS command by writing CMD[3:0] = "0101" in POC states NORMAL_ACTIVE or NORMAL_PASSIVE. The actual slot mode is monitored by CCSV.SLM[1:0].

1 = SINGLE Slot Mode (default after hard reset) 0 = ALL Slot Mode

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HCSE Halt due to Clock Sync Error (pAllowHaltDueToClock)

Controls the transition to HALT state due to a clock synchronization error. The bit can be modiﬁed in DEFAULT_CONFIG or CONFIG state only.

1 = CC will enter HALT state 0 = CC will enter / remain in NORMAL_PASSIVE

MTSA Select Channel A for MTS Transmission

The bit selects channel A for MTS symbol transmission. The ﬂag is reset by default and may be modiﬁed only in DEFAULT_CONFIG or CONFIG state.

1 = Channel A selected for MTS transmission 0 = Channel A disabled for MTS transmission

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MTSB Select Channel B for MTS Transmission

The bit selects channel B for MTS symbol transmission. The ﬂag is reset by default and may be modiﬁed only in DEFAULT_CONFIG or CONFIG state.

1 = Channel B selected for MTS transmission 0 = Channel B disabled for MTS transmission

Note: MTSA,Bmay also be changed outside DEFAULT_CONFIG or CONFIG state when the write

to SUCC1 register is directly preceded bythe unlocksequence asdescribed in4.3.1 LockRegister (LCK). This may be combined with CHI command SEND_MTS. If both bits MTSA and MTSB are set to ’1’ an MTS symbol will be transmitted on both channels when requested by writing CMD[3:0] = "1000".

CCHA Connected to Channel A (pChannels)

Conﬁgures whether the node is connected to channel A. 1 = Node connected to channel A (default after hard reset) 0 = Not connected to channel A

CCHB Connected to Channel B (pChannels)

Conﬁgures whether the node is connected to channel B. 1 = Node connected to channel B (default after hard reset) 0 = Not connected to channel B

Table 3 below references the CHI commands from the FlexRay Protocol Specification v2.1 (section

2.2.1.1, Table 2-2) to the E-Ray CHI command vector CMD[3:0].

CHI command Where processed (POC States) CHI Command Vector

CMD[3:0]

ALL_SLOTS POC:normal active, POC:normal passive ALL_SLOTS ALLOW_COLDSTART All except POC:default conﬁg,

POC:conﬁg, POC:halt CONFIG POC:default conﬁg, POC:ready CONFIG CONFIG_COMPLETE POC:conﬁg Unlock sequence & READY DEFAULT_CONFIG POC:halt CONFIG FREEZE All FREEZE HALT POC:normal active, POC:normal passive HALT

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READY All except POC:default conﬁg,

POC:conﬁg, POC:ready, POC:halt RUN POC:ready RUN WAKEUP POC:ready WAKEUP

ALLOW_COLDSTART

READY

Table 3: Reference to CHI Host command summary from FlexRay protocol speciﬁcation

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4.5.2 SUC Conﬁguration Register 2 (SUCC2)

The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SUCC2 R0000

0x0084 W

Reset 0 000000100000000

Bit 1514131211109876543210

LT15* LT14* LT13* LT12* LT11* LT10* LT9* LT8* LT7* LT6* LT5* LT4* LT3* LT2* LT1* LT0*

Reset 0 000010100000100

LTN3* LTN2* LTN1* LTN0*

000

LT20* LT19* LT18* LT17* LT16*

LT[20:0] Listen Timeout (pdListenTimeout)

Conﬁgures wakeup / startup listen timeout in µT. The range for pdListenTimeout is 1284 to 1283846 µT.

LTN[3:0] Listen Timeout Noise (gListenNoise - 1)

Conﬁgures the upper limit for startup and wakeup listen timeout in the presence of noise expressed as a multiple of pdListenTimeout. The range for gListenNoise is 2 to 16. LTN[3:0] must be conﬁgured identical in all nodes of a cluster.

Note: The wakeup / startup noise timeout is calculated as follows:

pdListenTimeout • gListenNoise = LT[20:0] • (LTN[3:0] + 1)

4.5.3 SUC Conﬁguration Register 3 (SUCC3)

The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SUCC3 R0000000000000000

0x0088 W

Reset 0 000000000000000

Bit 1514131211109876543210

R00000000

Reset 0 000000000010001

WCF3* WCF2* WCF1* WCF0* WCP3* WCP2* WCP1* WCP0*

WCP[3:0] Maximum Without Clock Correction Passive (gMaxWithoutClockCorrectionPassive)

Deﬁnes the number of consecutive even / odd cycle pairs with missing clock correction terms that will cause a transition from NORMAL_ACTIVE to NORMAL_PASSIVE state. Must be

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identical in all nodes of a cluster. Valid values are 1 to 15 cycle pairs.

WCF[3:0] Maximum Without Clock Correction Fatal (gMaxWithoutClockCorrectionFatal)

Deﬁnes the number of consecutive even / odd cycle pairs with missing clock correction terms that will cause a transition from NORMAL_ACTIVE or NORMAL_PASSIVE to HALT state. Must be identical in all nodes of a cluster. Valid values are 1 to 15 cycle pairs.

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4.5.4 NEM Conﬁguration Register (NEMC)

The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

NEMC R0000000000000000

0x008C W

Reset 0 000000000000000

Bit 1514131211109876543210

R000000000000

Reset 0 000000000000000

NML3* NML2* NML1* NML0*

NML[3:0] Network Management Vector Length (gNetworkManagementVectorLength)

These bits conﬁgure the length of the NM vector. The conﬁgured length must be identical in all nodes of a cluster. Valid values are 0 to 12 bytes.

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4.5.5 PRT Conﬁguration Register 1 (PRTC1)

The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PRTC1 R

0x0090 W

Reset 0 000100001001100

Bit 1514131211109876543210

Reset 0 000011000110011

RWP5* RWP4* RWP3* RWP2* RWP1* RWP0*

BRP1* BRP0* SPP1* SPP0*

CASM6

RXW8* RXW7* RXW6* RXW5* RXW4* RXW3* RXW2* RXW1* RXW0*

CASM5*CASM4*CASM3*CASM2*CASM1*CASM0* TSST3* TSST2* TSST1* TSST0*

TSST[3:0] Transmission Start Sequence Transmitter (gdTSSTransmitter)

Conﬁgures the duration of the Transmission Start Sequence (TSS) in terms of bit times (1 bit time = 4 µT = 100ns @ 10Mbps). Must be identical in all nodes of a cluster. Valid values are 3 to 15 bit times.

CASM[6:0] Collision Avoidance Symbol Max (gdCASRxLowMax)

Conﬁgures the upper limit of the acceptance window for a collision avoidance symbol (CAS).

CASM6 is ﬁxed to ’1’. Valid values are 67 to 99 bit times.

SPP[1:0] Strobe Point Position

Deﬁnes the sample count value for strobing. The strobed bit value is set to the voted value when the sample count is incremented to the value conﬁgured by SPP[1:0].

00, 11= Sample 5 (default) 01 = Sample 4 10 = Sample 6

Note: The current revision 2.1 of the FlexRay protocol requires that SPP[1:0] = "00". The alternate

strobe point positions could be used to compensate for asymmetries in the physical layer.

BRP[1:0] Baud Rate Prescaler (gdSampleClockPeriod, pSamplesPerMicrotick)

The Baud Rate Prescaler configures the baud rate on the FlexRay bus. The baud rates listed below are valid with a sample clock eray_sclk = 80 MHz. One bit time always consists of 8 samples independent of the conﬁgured baud rate.

00 = 10 MBit/s (default)

gdSampleClockPeriod = 12.5 ns = 1 • eray_sclk pSamplesPerMicrotick = 2 (1 µT = 25 ns)

01 = 5 MBit/s

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gdSampleClockPeriod = 25 ns = 2 • eray_sclk pSamplesPerMicrotick = 1 (1 µT = 25 ns)

10, 11 = 2.5 MBit/s

gdSampleClockPeriod = 50 ns = 4 • eray_sclk pSamplesPerMicrotick = 1 (1 µT = 50 ns)

RXW[8:0] Wakeup Symbol Receive Window Length (gdWakeupSymbolRxWindow)

Conﬁgures the number of bit times used by the node to test the duration of the received wakeup pattern. Must be identical in all nodes of a cluster. Valid values are 76 to 301 bit times.

RWP[5:0] Repetitions of Tx Wakeup Pattern (pWakeupPattern)

Conﬁgures the number of repetitions (sequences) of the Tx wakeup symbol. Valid values are 2 to 63.

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4.5.6 PRT Conﬁguration Register 2 (PRTC2)

The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PRTC2 R0 0

0x0094 W

Reset 0 000111100101101

Bit 1514131211109876543210

R0 0

Reset 0 000101000001110

TXL5* TXL4* TXL3* TXL2* TXL1* TXL0* TXI7* TXI6* TXI5* TXI4* TXI3* TXI2* TXI1* TXI0*

RXL5* RXL4* RXL3* RXL2* RXL1* RXL0*

RXI5* RXI4* RXI3* RXI2* RXI1* RXI0*

RXI[5:0] Wakeup Symbol Receive Idle (gdWakeupSymbolRxIdle)

Conﬁgures the number of bit times used by the node to test the duration of the idle phase of the received wakeup symbol. Must be identical in all nodes of a cluster. Valid values are 14 to 59 bit times.

RXL[5:0] Wakeup Symbol Receive Low (gdWakeupSymbolRxLow)

Conﬁgures the number of bit times used by the node to test the duration of the low phase of the received wakeup symbol. Must be identical in all nodes of a cluster. Valid values are 10 to 55 bit times.

TXI[7:0] Wakeup Symbol Transmit Idle (gdWakeupSymbolTxIdle)

Conﬁgures the number of bit times used by the node to transmit the idle phase of the wakeup symbol. Must be identical in all nodes of a cluster. Valid values are 45 to 180 bit times.

TXL[5:0] Wakeup Symbol Transmit Low (gdWakeupSymbolTxLow)

Conﬁgures the number of bit times used by the node to transmit the low phase of the wakeup symbol. Must be identical in all nodes of a cluster. Valid values are 15 to 60 bit times.

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4.5.7 MHD Conﬁguration Register (MHDC)

The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MHDC R0 0 0

0x0098 W

Reset 0 000000000000000

Bit 1514131211109876543210

R000000000

Reset 0 000000000000000

SLT12* SLT11* SLT10* SLT9* SLT8* SLT7* SLT6* SLT5* SLT4* SLT3* SLT2* SLT1* SLT0*

SFDL6* SFDL5* SFDL4* SFDL3* SFDL2* SFDL1* SFDL0*

SFDL[6:0] Static Frame Data Length (gPayloadLengthStatic)

Conﬁgures the cluster-wide payload length for all frames sent in the static segment in double bytes. The payload length must be identical in all nodes of a cluster. Valid values are 0 to 127.

SLT[12:0] Start of Latest Transmit (pLatestTx)

Configures the maximum minislot value allowed before inhibiting frame transmission in the dynamic segment of the cycle. There is no transmission in dynamic segment if SLT[12:0] is set to zero. Valid values are 0 to 7981 minislots.

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4.5.8 GTU Conﬁguration Register 1 (GTUC1)

The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GTUC1 R000000000000 0x00A0 W

Reset 0 000000000000000

Bit 1514131211109876543210

UT15* UT14* UT13* UT12* UT11* UT10* UT9* UT8* UT7* UT6* UT5* UT4* UT3* UT2* UT1* UT0*

Reset 0 000001010000000

UT19* UT18* UT17* UT16*

UT[19:0] Microtick per Cycle (pMicroPerCycle)

Conﬁgures the duration of the communication cycle in microticks. Valid values are 640 to 640000 µT.

4.5.9 GTU Conﬁguration Register 2 (GTUC2)

The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GTUC2 R000000000000 0x00A4 W

Reset 0000000000000010

Bit 1514131211109876543210

R0 0

Reset 0 000000000001010

MPC13* MPC12* MPC11* MPC10*

MPC9* MPC8* MPC7* MPC6* MPC5* MPC4* MPC3* MPC2* MPC1* MPC0*

SNM3* SNM2* SNM1* SNM0*

MPC[13:0] Macrotick Per Cycle (gMacroPerCycle)

Configures the duration of one communication cycle in macroticks. The cycle length must be identical in all nodes of a cluster. Valid values are 10 to 16000 MT.

SNM[3:0] Sync Node Max (gSyncNodeMax)

Maximum number of frames within a cluster with sync frame indicator bit SYN set to ’1’. Must be identical in all nodes of a cluster. Valid values are 2 to 15.

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4.5.10 GTU Conﬁguration Register 3 (GTUC3)

The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GTUC3 R0 0x00A8 W

Reset 0000001000000010

Bit 1514131211109876543210

UIOB7* UIOB6* UIOB5* UIOB4* UIOB3* UIOB2* UIOB1* UIOB0* UIOA7* UIOA6* UIOA5* UIOA4* UIOA3* UIOA2* UIOA1* UIOA0*

Reset 0 000000000000000

MIOB5* MIOB4* MIOB3* MIOB2* MIOB1* MIOB0*

MIOB6*

MIOA5* MIOA4* MIOA3* MIOA2* MIOA1* MIOA0*

MIOA6*

UIOA[7:0] Microtick Initial Offset Channel A (pMicroInitialOffset[A])

Configures the number of microticks between the actual time reference point on channel A and the subsequent macrotick boundary of the secondary time reference point. The parameter depends on pDelayCompensation[A] and therefore has to be set for each channel independently. Valid values are 0 to 240 µT.

UIOB[7:0] Microtick Initial Offset Channel B (pMicroInitialOffset[B])

Configures the number of microticks between the actual time reference point on channel B and the subsequent macrotick boundary of the secondary time reference point. The parameter depends on pDelayCompensation[B] and therefore has to be set for each channel independently. Valid values are 0 to 240 µT.

MIOA[6:0] Macrotick Initial Offset Channel A (pMacroInitialOffset[A])

Configures the number of macroticks between the static slot boundary and the subsequent macrotick boundary of the secondary time reference point based on the nominal macrotick duration. Must be identical in all nodes of a cluster. Valid values are 2 to 72 MT.

MIOB[6:0] Macrotick Initial Offset Channel B (pMacroInitialOffset[B])

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4.5.11 GTU Conﬁguration Register 4 (GTUC4)

The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only. For details about configuration of NIT[13:0] and OCS[13:0] see Section 5.1.5 Configuration of NIT Start and Offset Correction Start.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GTUC4 R0 0 0x00AC W

Reset 0 000000000001000

Bit 1514131211109876543210

R0 0

Reset 0 000000000000111

OCS13* OCS12* OCS11* OCS10*

NIT13* NIT12* NIT11* NIT10* NIT9* NIT8* NIT7* NIT6* NIT5* NIT4* NIT3* NIT2* NIT1* NIT0*

OCS9* OCS8* OCS7* OCS6* OCS5* OCS4* OCS3* OCS2* OCS1* OCS0*

NIT[13:0] Network Idle Time Start (gMacroPerCycle - gdNIT - 1)

Conﬁgures the starting point of the Network Idle Time NIT at the end of the communication cycle expressed in terms of macroticks from the beginning of the cycle. The start of NIT is recognized if Macrotick = gMacroPerCycle - gdNIT -1 and the increment pulse of Macrotick is set. Must be identical in all nodes of a cluster. Valid values are 7 to 15997 MT.

OCS[13:0] Offset Correction Start (gOffsetCorrectionStart - 1)

Determines the start of the offset correction within the NIT phase, calculated from start of cycle. Must be identical in all nodes of a cluster. For cluster consisting of E-Ray implementations only, it is sufﬁcient to program OCS = NIT + 1. Valid values are 8 to 15998 MT.

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4.5.12 GTU Conﬁguration Register 5 (GTUC5)

The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GTUC5 R 0x00B0 W

Reset 0 000111000000000

Bit 1514131211109876543210

Reset 0 000000000000000

DEC7* DEC6* DEC5* DEC4* DEC3* DEC2* DEC1* DEC0*

DCB7* DCB6* DCB5* DCB4* DCB3* DCB2* DCB1* DCB0* DCA7* DCA6* DCA5* DCA4* DCA3* DCA2* DCA1* DCA0*

000

CDD4* CDD3* CDD2* CDD1* CDD0*

DCA[7:0] Delay Compensation Channel A (pDelayCompensation[A])

Used to compensate for reception delays on the indicated channel. This covers assumed propagation delay up to cPropagationDelayMax for microticks in the range of 0.0125 to 0.05µs. In practice, the minimum of the propagation delays of all sync nodes should be applied.

Valid values are 0 to 200 µT.

DCB[7:0] Delay Compensation Channel B (pDelayCompensation[B])

Valid values are 0 to 200 µT.

CDD[4:0] Cluster Drift Damping (pClusterDriftDamping)

Conﬁgures the cluster drift damping value used in clock synchronization to minimize accumulation of rounding errors. Valid values are 0 to 20 µT.

DEC[7:0] Decoding Correction (pDecodingCorrection)

Conﬁgures the decoding correction value used to determine the primary time reference point. Valid values are 14 to 143 µT.

4.5.13 GTU Conﬁguration Register 6 (GTUC6)

The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GTUC6 R00000 0x00B4 W

Reset 0 000000000000010

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Bit 1514131211109876543210

R00000

Reset 0 000000000000000

MOD

MOD9* MOD8*

10*

ASR10*

ASR9* ASR8* ASR7* ASR6* ASR5* ASR4* ASR3* ASR2* ASR1* ASR0*

MOD7* MOD6* MOD5* MOD4* MOD3* MOD2* MOD1* MOD0*

ASR[10:0] Accepted Startup Range (pdAcceptedStartupRange)

Number of microticks constituting the expanded range of measured deviation for startup frames during integration. Valid values are 0 to 1875 µT.

MOD[10:0] Maximum Oscillator Drift (pdMaxDrift)

Maximum drift offset between two nodes that operate with unsynchronized clocks over one communication cycle in µT. Valid values are 2 to 1923 µT.

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4.5.14 GTU Conﬁguration Register 7 (GTUC7)

The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GTUC7 R000000 0x00B8 W

Reset 0 000000000000010

Bit 1514131211109876543210

R000000

Reset 0 000000000000100

NSS9* NSS8* NSS7* NSS6* NSS5* NSS4* NSS3* NSS2* NSS1* NSS0*

SSL9* SSL8* SSL7* SSL6* SSL5* SSL4* SSL3* SSL2* SSL1* SSL0*

SSL[9:0] Static Slot Length (gdStaticSlot)

Conﬁgures the duration of a static slot in macroticks. The static slot length must be identical in all nodes of a cluster. Valid values are 4 to 659 MT.

NSS[9:0] Number of Static Slots (gNumberOfStaticSlots)

Configures the number of static slots in a cycle. At least 2 coldstart nodes must be configured to startup a FlexRay network. The number of static slots must be identical in all nodes of a cluster. Valid values are 2 to 1023.

4.5.15 GTU Conﬁguration Register 8 (GTUC8)

The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GTUC8 R0 0 0 0x00BC W

Reset 0 000000000000000

Bit 1514131211109876543210

R0000000000

Reset 0 000000000000010

NMS

12*

NMS

11*

NMS

NMS9* NMS8* NMS7* NMS6* NMS5* NMS4* NMS3* NMS2* NMS1* NMS0*

10*

MSL5* MSL4* MSL3* MSL2* MSL1* MSL0*

MSL[5:0] Minislot Length (gdMinislot)

Conﬁgures the duration of a minislot in macroticks. The minislot length must be identical in all nodes of a cluster. Valid values are 2 to 63 MT.

NMS[12:0] Number of Minislots (gNumberOfMinislots)

Configures the number of minislots within the dynamic segment of a cycle. The number of min-

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islots must be identical in all nodes of a cluster. Valid values are 0 to 7986.

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4.5.16 GTU Conﬁguration Register 9 (GTUC9)

The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GTUC9

0x00C0 W

R00000000000000

Reset 0 000000000000000

Bit 1514131211109876543210

R0 0 0

Reset 0 000000100000001

MAPO4*MAPO3*MAPO2*MAPO1*MAPO

APO5* APO4* APO3* APO2* APO1* APO0*

DSI1* DSI0*

APO[5:0] Action Point Offset (gdActionPointOffset)

Configures the action point offset in macroticks within static slots and symbol window. Must be identical in all nodes of a cluster. Valid values are 1 to 63 MT.

MAPO[4:0] Minislot Action Point Offset (gdMinislotActionPointOffset)

Configures the action point offset in macroticks within the minislots of the dynamic segment. Must be identical in all nodes of a cluster. Valid values are 1 to 31 MT.

DSI[1:0] Dynamic Slot Idle Phase (gdDynamicSlotIdlePhase)

The duration of the dynamic slot idle phase has to be greater or equal than the idle detection time. Must be identical in all nodes of a cluster. Valid values are 0 to 2 Minislot.

4.5.17 GTU Conﬁguration Register 10 (GTUC10)

The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GTUC10 R00000

0x00C4 W

Reset 0 000000000000010

Bit 1514131211109876543210

R0 0

Reset 0 000000000000101

MOC

13*

MOC

12*

MOC

11*

MRC

MRC9* MRC8* MRC7* MRC6* MRC5* MRC4* MRC3* MRC2* MRC1* MRC0*

10*

MOC

MOC9* MOC8* MOC7* MOC6* MOC5* MOC4* MOC3* MOC2* MOC1* MOC0*

10*

MOC[13:0] Maximum Offset Correction (pOffsetCorrectionOut)

Holds the maximum permitted offset correction value to be applied by the internal clock synchronization algorithm (absolute value). The CC checks only the internal offset correction value

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against the maximum offset correction value. Valid values are 5 to 15266 µT.

MRC[10:0] Maximum Rate Correction (pRateCorrectionOut)

Holds the maximum permitted rate correction value to be applied by the internal clock synchronization algorithm. The CC checks only the internal rate correction value against the maximum rate correction value (absolute value). Valid values are 2 to 1923 µT.

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4.5.18 GTU Conﬁguration Register 11 (GTUC11)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GTUC11

0x00C8 W

R00000

Reset 0 000000000000000

Bit 1514131211109876543210

R000000

Reset 0 000000000000000

ERC2* ERC1* ERC0*

ERCC1 ERCC0

00000

000000

EOC2* EOC1* EOC0*

EOCC1 EOCC0

EOCC[1:0] External Offset Correction Control (vExternOffsetControl)

By writing to EOCC[1:0] the external offset correction is enabled as speciﬁed below. Should be modiﬁed only outside NIT.

00, 01 = No external offset correction 10 = External offset correction value subtracted from calculated offset correction value 11 = External offset correction value added to calculated offset correction value

ERCC[1:0] External Rate Correction Control (vExternRateControl)

By writing to ERCC[1:0] the external rate correction is enabled as speciﬁed below. Should be modiﬁed only outside NIT.

00, 01 = No external rate correction 10 = External rate correction value subtracted from calculated rate correction value 11 = External rate correction value added to calculated rate correction value

EOC[2:0] External Offset Correction (pExternOffsetCorrection)

Holds the external offset correction value in microticks to be applied by the internal clock synchronization algorithm. The value is subtracted / added from / to the calculated offset correction value. The value is applied during NIT. May be modiﬁed in DEFAULT_CONFIG or CONFIG state only. Valid values are 0 to 7 µT.

ERC[2:0] External Rate Correction (pExternRateCorrection)

Holds the external rate correction value in microticks to be applied by the internal clock synchronization algorithm. The value is subtracted / added from / to the calculated rate correction value. The value is applied during NIT. May be modiﬁed in DEFAULT_CONFIG or CONFIG state only. Valid values are 0 to 7 µT.

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4.6 CC Status Registers

During 8/16-bit accesses to status variables coded with more than 8/16-bit, the variable might be updated by the CC between twoaccesses (non-atomic read accesses). The status vectormay change faster than the Host can poll the status vector, depending on eray_bclk frequency.

4.6.1 CC Status Vector (CCSV)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CCSV R 0 0 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0 RCA4 RCA3 RCA2 RCA1 RCA0 WSV2 WSV1 WSV0

0x0100 W

Reset 0 000000000010000

Bit 1514131211109876543210

R 0 CSI CSAI CSNI 0 0 SLM1 SLM0 HRQ FSI POCS5 POCS4 POCS3 POCS2 POCS1 POCS0

Reset 0 100000000000000

POCS[5:0] Protocol Operation Control Status

Indicates the actual state of operation of the CC Protocol Operation Control 00 0000 = DEFAULT_CONFIG state 00 0001 = READY state 00 0010 = NORMAL_ACTIVE state 00 0011 = NORMAL_PASSIVE state 00 0100 = HALT state 00 0101 = MONITOR_MODE state 00 0110…00 1110 = reserved 00 1111 = CONFIG state

Indicates the actual state of operation of the POC in the wakeup path 01 0000 = WAKEUP_STANDBY state 01 0001 = WAKEUP_LISTEN state 01 0010 = WAKEUP_SEND state 01 0011 = WAKEUP_DETECT state 01 0100…01 1111 = reserved

Indicates the actual state of operation of the POC in the startup path 10 0000 = STARTUP_PREPARE state 10 0001 = COLDSTART_LISTEN state

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10 0010 = COLDSTART_COLLISION_RESOLUTION state 10 0011 = COLDSTART_CONSISTENCY_CHECK state 10 0100 = COLDSTART_GAP state 10 0101 = COLDSTART_JOIN State 10 0110 = INTEGRATION_COLDSTART_CHECK state 10 0111 = INTEGRATION_LISTEN state 10 1000 = INTEGRATION_CONSISTENCY_CHECK state 10 1001 = INITIALIZE_SCHEDULE state 10 1010 = ABORT_STARTUP state 10 1011 = STARTUP_SUCCESS state 10 1100…11 1111 = reserved

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FSI Freeze Status Indicator (vPOC!Freeze)

Indicates that the POC has entered the HALT state due to CHI command FREEZE or due to an error condition requiring an immediate POC halt. Reset by transition from HALT to DEFAULT_CONFIG state.

HRQ Halt Request (vPOC!CHIHaltRequest)

Indicates that a request from the Host has been received to halt the POC at the end of the communication cycle. Reset by transition from HALT to DEFAULT_CONFIG state or when entering READY state.

SLM[1:0] Slot Mode (vPOC!SlotMode)

Indicates the actual slot mode of the POC in states READY, STARTUP, NORMAL_ACTIVE, and NORMAL_PASSIVE. Default is SINGLE. Changes to ALL, depending on SUCC1.TSM. In NORMAL_ACTIVE or NORMAL_PASSIVE state the CHI command ALL_SLOTS will change the slot mode from SINGLE over ALL_PENDING to ALL. Set to SINGLE in all other states.

00 = SINGLE 01 = reserved 10 = ALL_PENDING 11 = ALL

CSNI Coldstart Noise Indicator (vPOC!ColdstartNoise)

Indicates that the cold start procedure occurred under noisy conditions. Reset by CHI command RESET_STATUS_INDICATORS or by transition from HALT to DEFAULT_CONFIG state or from READY to STARTUP state.

CSAI Coldstart Abort Indicator

Coldstart aborted. Reset by CHI command RESET_STATUS_INDICATORS or by transition from HALT to DEFAULT_CONFIG state or from READY to STARTUP state.

CSI Cold Start Inhibit (vColdStartInhibit)

Indicates that the node is disabled from cold starting. The ﬂag is set whenever the POC enters READY state due to CHI command READY. The ﬂag has to be reset under control of the Host by CHI command ALLOW_COLDSTART (SUCC1.CMD[3:0] = "1001").

1 = Cold starting of node disabled 0 = Cold starting of node enabled

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WSV[2:0] Wakeup Status (vPOC!WakeupStatus)

Indicates the status of the current wakeup attempt. Reset by CHI command RESET_STATUS_INDICATORS or by transition from HALT to DEFAULT_CONFIG state or from READY to STARTUP state.

000 = UNDEFINED. Wakeup not yet executed by the CC. 001 = RECEIVED_HEADER. Set when the CC ﬁnishes wakeup due to the reception of a

frame header without coding violation on either channel in WAKEUP_LISTEN state.

010 = RECEIVED_WUP. Set when the CC ﬁnishes wakeup due to the reception of a valid

wakeup pattern on the conﬁgured wakeup channel in WAKEUP_LISTEN state.

011 = COLLISION_HEADER. Set when the CC stops wakeup due to a detected collision

during wakeup pattern transmission by receiving a valid header on either channel.

100 = COLLISION_WUP. Set when the CC stops wakeup due to a detected collision during

wakeup pattern transmission by receiving a valid wakeup pattern on the conﬁgured wakeup channel.

101 = COLLISION_UNKNOWN. Set when the CC stops wakeup by leaving

WAKEUP_DETECT state after expiration of the wakeup timer without receiving a valid wakeup pattern or a valid frame header.

110 = TRANSMITTED. Set when the CC has successfully completed the transmission of the

wakeup pattern.

111 = reserved

RCA[4:0] Remaining Coldstart Attempts (vRemainingColdstartAttempts)

Indicates the number of remaining coldstart attempts. The RUN command resets this counter to the maximum number of coldstart attempts as configured by SUCC1.CSA[4:0].

PSL[5:0] POC Status Log

Status of POCS[5:0] immediately before entering HALT state. Set when entering HALT state. Set to HALT when FREEZE command is applied during HALT state. Reset to "00 0000" when leaving HALT state.

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4.6.2 CC Error Vector (CCEV)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CCEV R0000000000000000

0x0104 W

Reset 0 000000000000000

Bit 1514131211109876543210

R 0 0 0 PTAC4 PTAC3 PTAC2 PTAC1 PTAC0

Reset 0 000000000000000

ERRM1 ERRM0

0 0 CCFC3 CCFC2 CCFC1 CCFC0

Reset by transition from HALT to DEFAULT_CONFIG state or when entering READY state. CCFC[3:0] Clock Correction Failed Counter (vClockCorrectionFailed)

The Clock Correction Failed Counter is incremented by one at the end of any odd communication cycle where either the missing offset correction error or missing rate correction error are active. The Clock Correction Failed Counter is reset to ’0’ at the end of an odd communication cycle if neither the offset correction failed nor the rate correction failed errors are active. The Clock Correction Failed Counter stops at 15.

ERRM[1:0] Error Mode (vPOC!ErrorMode)

Indicates the actual error mode of the POC. 00 = ACTIVE (green) 01 = PASSIVE (yellow) 10 = COMM_HALT (red) 11 = reserved

PTAC[4:0] Passive to Active Count (vAllowPassiveToActive)

Indicates the number of consecutive even / odd cycle pairs that have passed with valid rate and offset correction terms, while the node is waiting to transit from NORMAL_PASSIVE state to NORMAL_ACTIVE state. The transition takes place when PTAC[4:0] equals SUCC1.PTA[4:0] -1.

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4.6.3 Slot Counter Value (SCV)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SCV R00000

0x0110 W

Reset 0 000000000000000

Bit 1514131211109876543210

R00000

Reset 0 000000000000000

SCCB10

SCCB9 SCCB8 SCCB7 SCCB6 SCCB5 SCCB4 SCCB3 SCCB2 SCCB1 SCCB0

SCCA10

SCCA9 SCCA8 SCCA7 SCCA6 SCCA5 SCCA4 SCCA3 SCCA2 SCCA1 SCCA0

SCCA[10:0] Slot Counter Channel A (vSlotCounter[A])

Current slot counter value on channel A. The value is incremented by the CC and reset at the start of a communication cycle. Valid values are 0 to 2047.

SCCB[10:0] Slot Counter Channel B (vSlotCounter[B])

Current slot counter value on channel B. The value is incremented by the CC and reset at the start of a communication cycle. Valid values are 0 to 2047.

4.6.4 Macrotick and Cycle Counter Value (MTCCV)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MTCCV R0000000000CCV5 CCV4 CCV3 CCV2 CCV1 CCV0

0x0114 W

Reset 0 000000000000000

Bit 1514131211109876543210

R0 0

Reset 0 000000000000000

MTV13 MTV12 MTV11 MTV10

MTV9 MTV8 MTV7 MTV6 MTV5 MTV4 MTV3 MTV2 MTV1 MTV0

MTV[13:0] Macrotick Value (vMacrotick)

Current macrotick value. The value is incremented by the CC and reset at the start of a communication cycle. Valid values are 0 to 16000.

CCV[5:0] Cycle Counter Value (vCycleCounter)

Current cycle counter value. The value is incremented by the CC at the start of a communication cycle. Valid values are 0 to 63.

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4.6.5 Rate Correction Value (RCV)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RCV R0000000000000000

0x0118 W

Reset 0 000000000000000

Bit 1514131211109876543210

R 0 0 0 0 RCV11 RCV10 RCV9 RCV8 RCV7 RCV6 RCV5 RCV4 RCV3 RCV2 RCV1 RCV0

Reset 0 0 0 0 0 0 0 0 0 0 000000

RCV[11:0] Rate Correction Value (vRateCorrection)

Rate correction value (two’s complement). Calculated internal rate correction value before limitation. If the RCV value exceeds the limits defined by GTUC10.MRC[10:0], flag SFS.RCLR is set to ’1’.

4.6.6 Offset Correction Value (OCV)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OCV R0000000000000OCV18 OCV17 OCV16

0x011C W

Reset 0 000000000000000

Bit 1514131211109876543210

R OCV15 OCV14 OCV13 OCV12 OCV11 OCV10 OCV9 OCV8 OCV7 OCV6 OCV5 OCV4 OCV3 OCV2 OCV1 OCV0

Reset 0 0 0 0 0 0 0 0 0 0 000000

OCV[18:0] Offset Correction Value (vOffsetCorrection)

Offset correction value (two’s complement). Calculated internal offset correction value before limitation. If the OCV value exceeds the limits defined by GTUC10.MOC[13:0], flag SFS.OCLR is set to ’1’.

Note: The external rate / offset correction value is added to the limited rate / offset correction value.

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4.6.7 Sync Frame Status (SFS)

The maximum number of valid sync frames in a communication cycle is 15.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SFS R000000000000RCLR MRCS OCLR MOCS

0x0120 W

Reset 0 000000000000000

Bit 1514131211109876543210

R VSBO3 VSBO2 VSBO1 VSBO0 VSBE3 VSBE2 VSBE1 VSBE0 VSAO3 VSAO2 VSAO1 VSAO0 VSAE3 VSAE2 VSAE1 VSAE0

Reset 0 000000000000000

VSAE[3:0] Valid Sync Frames Channel A, even communication cycle

Holds the number of valid sync frames received on channel A in the even communication cycle. If transmission of sync frames is enabled by SUCC1.TXSY the value is incremented by one. The value is updated during the NIT of each even communication cycle.

VSAO[3:0] Valid Sync Frames Channel A, odd communication cycle

Holds the number of valid sync frames received on channel A in the odd communication cycle. If transmission of sync frames is enabled by SUCC1.TXSY the value is incremented by one. The value is updated during the NIT of each odd communication cycle.

VSBE[3:0] Valid Sync Frames Channel B, even communication cycle

Holds the number of valid sync frames received on channel B in the even communication cycle. If transmission of sync frames is enabled by SUCC1.TXSY the value is incremented by one. The value is updated during the NIT of each even communication cycle.

VSBO[3:0] Valid Sync Frames Channel B, odd communication cycle

Holds the number of valid sync frames received on channel B in the odd communication cycle. If transmission of sync frames is enabled by SUCC1.TXSY the value is incremented by one. The value is updated during the NIT of each odd communication cycle.

Note: The bit fields above are only valid if the respective channel is assigned to the CC by

SUCC1.CCHA or SUCC1.CCHB.

MOCS Missing Offset Correction Signal

The Missing Offset Correction flag signals to the Host, that no offset correction calculation can be performed because no sync frames were received. The flag is updated by the CC at start of offset correction phase.

1 = Missing offset correction signal

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0 = Offset correction signal valid

OCLR Offset Correction Limit Reached

The Offset Correction Limit Reached flag signals to the Host, that the offset correction value has exceeded its limit as defined by GTUC10.MOC[13:0]. The flag is updated by the CC at start of offset correction phase.

1 = Offset correction limit reached 0 = Offset correction below limit

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MRCS Missing Rate Correction Signal

The Missing Rate Correction flag signals to the Host, that no rate correction calculation can be performed because no pairs of even / odd sync frames were received. The flag is updated by the CC at start of offset correction phase.

1 = Missing rate correction signal 0 = Rate correction signal valid

RCLR Rate Correction Limit Reached

The Rate Correction Limit Reached flag signals to the Host, that the rate correction value has exceeded its limit as defined by GTUC10.MRC[10:0]. The flag is updated by the CC at start of offset correction phase.

1 = Rate correction limit reached 0 = Rate correction below limit

4.6.8 Symbol Window and NIT Status (SWNIT)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SWNIT R0000000000000000

0x0124 W

Reset 0 000000000000000

Bit 1514131211109876543210

R 0 0 0 0 SBNB SENB SBNA SENA MTSB MTSA TCSB SBSB SESB TCSA SBSA SESA

Reset 0 000000000000000

Symbol window related status information. Updated by the CC at the end of the symbol window for each channel. During startup the status data is not updated.

SESA Syntax Error in Symbol Window Channel A (vSS!SyntaxErrorA)

1 = Syntax error during symbol window detected on channel A 0 = No syntax error detected

SBSA Slot Boundary Violation in Symbol Window Channel A (vSS!BViolationA)

1 = Slot boundary violation during symbol window detected on channel A 0 = No slot boundary violation detected

TCSA Transmission Conﬂict in Symbol Window Channel A (vSS!TxConﬂictA)

1 = Transmission conflict in symbol window detected on channel A 0 = No transmission conflict detected

SESB Syntax Error in Symbol Window Channel B (vSS!SyntaxErrorB)

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1 = Syntax error during symbol window detected on channel B 0 = No syntax error detected

SBSB Slot Boundary Violation in Symbol Window Channel B (vSS!BViolationB)

1 = Slot boundary violation during symbol window detected on channel B 0 = No slot boundary violation detected

TCSB Transmission Conﬂict in Symbol Window Channel B (vSS!TxConﬂictB)

1 = Transmission conflict in symbol window detected on channel B 0 = No transmission conflict detected

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MTSA MTS Received on Channel A (vSS!ValidMTSA)

Media Access Test symbol received on channel A during the preceding symbol window. Updated by the CC for each channel at the end of the symbol window. When this bit is set to ’1’, also interrupt flag SIR.MTSA is set to ’1’.

1 = MTS symbol received on channel A 0 = No MTS symbol received on channel A

MTSB MTS Received on Channel B (vSS!ValidMTSB)

Media Access Test symbol received on channel B during the preceding symbol window. Updated by the CC for each channel at the end of the symbol window. When this bit is set to ’1’, also interrupt flag SIR.MTSB is set to ’1’.

1 = MTS symbol received on channel B 0 = No MTS symbol received on channel B

NIT related status information. Updated by the CC at the end of the NIT for each channel: SENA Syntax Error during NIT Channel A (vSS!SyntaxErrorA)

1 = Syntax error during NIT detected on channel A 0 = No syntax error detected

SBNA Slot Boundary Violation during NIT Channel A (vSS!BViolationA)

1 = Slot boundary violation during NIT detected on channel A 0 = No slot boundary violation detected

SENB Syntax Error during NIT Channel B (vSS!SyntaxErrorB)

1 = Syntax error during NIT detected on channel B 0 = No syntax error detected

SBNB Slot Boundary Violation during NIT Channel B (vSS!BViolationB)

1 = Slot boundary violation during NIT detected on channel B 0 = No slot boundary violation detected

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4.6.9 Aggregated Channel Status (ACS)

The aggregated channel status provides the Host with an accrued status of channel activity for all communication slots regardless of whetherthey are assigned for transmission orsubscribed for reception. The aggregated channel status also includes status data from the symbol windowand the network idle time. The status data is updated (set) after each slot and aggregated until it is reset by the Host. During startup the status data is not updated. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect on the flag. A hard reset will also clear the register.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ACS R0000000000000000

0x0128 W

Reset 0 000000000000000

Bit 1514131211109876543210

R0 0 0

Reset 0 000000000000000

SBVB CIB CEDB SEDB VFRB

000

SBVA CIA CEDA SEDA VFRA

VFRA Valid Frame Received on Channel A (vSS!ValidFrameA)

One or more valid frames were received on channel A in any static or dynamic slot during the observation period.

1 = Valid frame(s) received on channel A 0 = No valid frame received

SEDA Syntax Error Detected on Channel A (vSS!SyntaxErrorA)

One or more syntax errors in static or dynamic slots, symbol window, and NIT were observed on channel A.

1 = Syntax error(s) observed on channel A 0 = No syntax error observed

CEDA Content Error Detected on Channel A (vSS!ContentErrorA)

One or more frames with a content error were received on channel A in any static or dynamic slot during the observation period.

1 = Frame(s) with content error received on channel A 0 = No frame with content error received

CIA Communication Indicator Channel A

One or more valid frames were received on channel A in slots that also contained any additional communication during the observation period, i.e. one or more slots received a valid frame AND had any combination of either syntax error OR content error OR slot boundary violation.

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1 = Valid frame(s) received on channel A in slots containing any additional communication 0 = No valid frame(s) received in slots containing any additional communication

SBVA Slot Boundary Violation on Channel A (vSS!BViolationA)

One or more slot boundary violations were observed on channel A at any time during the observation period (static or dynamic slots, symbol window, and NIT).

1 = Slot boundary violation(s) observed on channel A 0 = No slot boundary violation observed

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VFRB Valid Frame Received on Channel B (vSS!ValidFrameB)

One or more valid frames were received on channel B in any static or dynamic slot during the observation period. Reset under control of the Host.

1 = Valid frame(s) received on channel B 0 = No valid frame received

SEDB Syntax Error Detected on Channel B (vSS!SyntaxErrorB)

One or more syntax errors in static or dynamic slots, symbol window, and NIT were observed on channel B.

1 = Syntax error(s) observed on channel B 0 = No syntax error observed

CEDB Content Error Detected on Channel B (vSS!ContentErrorB)

One or more frames with a content error were received on channel B in any static or dynamic slot during the observation period.

1 = Frame(s) with content error received on channel B 0 = No frame with content error received

CIB Communication Indicator Channel B

One or more valid frames were received on channel B in slots that also contained any additional communication during the observation period, i.e. one or more slots received a valid frame AND had any combination of either syntax error OR content error OR slot boundary violation.

1 = Valid frame(s) received on channel B in slots containing any additional communication 0 = No valid frame(s) received in slots containing any additional communication

SBVB Slot Boundary Violation on Channel B (vSS!BViolationB)

One or more slot boundary violations were observed on channel B at any time during the observation period (static or dynamic slots, symbol window, and NIT).

1 = Slot boundary violation(s) observed on channel B 0 = No slot boundary violation observed

Note: The set condition of flags CIA and CIB is also fulfilled if there is only one single frame in the

slot and the slot boundary at the end of the slot is reached during the frames channel idle recognition phase.

When one of the flags SEDB, CEDB, CIB, SBVB changes from ‘0‘ to ‘1‘, interrupt flag EIR.EDB is set to ’1’.When one of the flags SEDA, CEDA, CIA, SBVA changes from ‘0‘ to ‘1‘, interrupt flag EIR.EDA is set to ’1’.

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4.6.10 Even Sync ID [1…15] (ESIDn)

Registers ESID1 to ESID15 hold the frame IDs of the sync frames received in even communication cycles, sorted in ascending order, with register ESID1 holding the lowest received sync frame ID. If the node itself transmits a sync frame in an even communication cycle, register ESID1 holds the respective sync frame ID as configured in message buffer 0 and flags RXEA, RXEB are set. The value is updated during the NIT of each even communication cycle.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ESIDn R0000000000000000

0x0130 -

0x0168

Reset 0 000000000000000

Bit 1514131211109876543210

R RXEB RXEA 0 0 0 0 EID9 EID8 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0

Reset 0 000000000000000

EID[9:0] Even Sync ID (vsSyncIDListA,B even)

Sync frame ID even communication cycle.

RXEA Received / Conﬁgured Even Sync ID on Channel A

Signals that a sync frame corresponding to the stored even sync ID was received on channel A or that the node is conﬁgured to be a sync node with key slot = EID[9:0] (ESID1 only).

1 = Sync frame received on channel A / node conﬁgured to transmit sync frames 0 = No sync frame received on channel A / node not conﬁgured to transmit sync frames

RXEB Received / Conﬁgured Even Sync ID on Channel B

Signals that a sync frame corresponding to the stored even sync ID was received on channel B or that the node is conﬁgured to be a sync node with key slot = EID[9:0] (ESID1 only).

1 = Sync frame received on channel B / node conﬁgured to transmit sync frames 0 = No sync frame received on channel B / node not conﬁgured to transmit sync frames

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4.6.11 Odd Sync ID [1…15] (OSIDn)

Registers OSID1 to OSID15 hold the frame IDs of the sync frames received in odd communication cycles, sorted in ascending order, with register OSID1 holding the lowest received sync frame ID. If the node itself transmits a sync frame in an odd communication cycle, register OSID1 holds the respective sync frame ID as configured in message buffer 0 and flags RXOA,RXOB are set. The value is updated during the NIT of each odd communication cycle.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OSIDn R0000000000000000

0x0170 -

0x01A8

Reset 0 000000000000000

Bit 1514131211109876543210

R RXOB RXOA 0 0 0 0 OID9 OID8 OID7 OID6 OID5 OID4 OID3 OID2 OID1 OID0

Reset 0 000000000000000

OID[9:0] Odd Sync ID (vsSyncIDListA,B odd)

Sync frame ID odd communication cycle.

RXOA Received / Conﬁgured Odd Sync ID on Channel A

Signals that a sync frame corresponding to the stored odd sync ID was received on channel A or that the node is conﬁgured to be a sync node with key slot = OID[9:0] (OSID1 only).

1 = Sync frame received on channel A / node conﬁgured to transmit sync frames 0 = No sync frame received on channel A / node not conﬁgured to transmit sync frames

RXOB Received / Conﬁgured Odd Sync ID on Channel B

Signals that a sync frame corresponding to the stored odd sync ID was received on channel B or that the node is conﬁgured to be a sync node with key slot = OID[9:0] (OSID1 only).

1 = Sync frame received on channel B / node conﬁgured to transmit sync frames 0 = No sync frame received on channel B / node not conﬁgured to transmit sync frames

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4.6.12 Network Management Vector [1…3] (NMVn)

The three network management registers hold the accrued NM vector (configurable 0 to 12 bytes). The accrued NM vector is generated by the CC by bit-wise ORing each NM vector received (valid static frames with PPI = ’1’) on each channel (see 5.6 Network Management).

The CC updates the NM vector at the end of each communication cycle as long as the CC is either in NORMAL_ACTIVE or NORMAL_PASSIVE state.

NMVn-bytes exceeding the configured NM vector length are not valid.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

NMVn R NM31 NM30 NM29 NM28 NM27 NM26 NM25 NM24 NM23 NM22 NM21 NM20 NM19 NM18 NM17 NM16

0x01B0-

0x01B8

Reset 0 000000000000000

Bit 1514131211109876543210

R NM15 NM14 NM13 NM12 NM11 NM10 NM9 NM8 NM7 NM6 NM5 NM4 NM3 NM2 NM1 NM0

Reset 0 000000000000000

Table 4 below shows the assignment of the receivedpayload’s data bytes to the network management vector.

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Word

NMV1 Data3 Data2 Data1 Data0 NMV2 Data7 Data6 Data5 Data4 NMV3 Data11 Data10 Data9 Data8

Table 4: Assignment of data bytes to network management vector

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4.7 Message Buffer Control Registers

4.7.1 Message RAM Conﬁguration (MRC)

The Message RAM Configuration registerdefines the number of messagebuffers assigned to the static segment, dynamic segment, and FIFO. The register can be written during DEFAULT_CONFIG or CONFIG state only.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MRC R00000

0x0300 W

Reset 0 000000110000000

Bit 1514131211109876543210

FFB7* FFB6* FFB5* FFB4* FFB3* FFB2* FFB1* FFB0* FDB7* FDB6* FDB5* FDB4* FDB3* FDB2* FDB1* FDB0*

Reset 0 000000000000000

FDB[7:0] First Dynamic Buffer

0 = No group of message buffers exclusively for the static segment conﬁgured

1…127 = Message buffers 0 to FDB - 1 reserved for static segment

≥128 = No dynamic message buffers conﬁgured

SPLM* SEC1* SEC0* LCB7* LCB6* LCB5* LCB4* LCB3* LCB2* LCB1* LCB0*

FFB[7:0] First Buffer of FIFO

0 = All message buffers assigned to the FIFO

1…127 = Message buffers from FFB to LCB assigned to the FIFO

≥128 = No message buffer assigned to the FIFO

LCB[7:0] Last Conﬁgured Buffer

0…127 = Number of message buffers is LCB + 1

≥128 = No message buffer conﬁgured

SEC[1:0] Secure Buffers

Not evaluated when the CC is in DEFAULT_CONFIG or CONFIG state. 00 = Reconﬁguration of message buffers enabled with numbers < FFB enabled

Exception: In nodes conﬁgured for sync frame transmission or for single slot mode opera-

tion message buffer 0 (and if SPLM = ’1’, also message buffer 1) is always locked

01 = Reconﬁguration of message buffers with numbers < FDB and with numbers ≥ FFB locked

and transmission of message buffers for static segment with numbers ≥ FDB disabled

10 = Reconﬁguration of all message buffers locked

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11 = Reconﬁguration of all message buffers locked

and transmission of message buffers for static segment with numbers ≥ FDB disabled

SPLM Sync Frame Payload Multiplex

This bit is only evaluated if the node is conﬁgured as sync node (SUCC1.TXSY = ’1’) or for single slot mode operation (SUCC1.TSM = ’1’). When this bit is set to ’1’ message buffers 0 and 1 are dedicated for sync frame transmission with different payload data on channel A and B. When this bit is set to ’0’, sync frames are transmitted from message buffer0 with the same payload data on both channels. Note that the channel ﬁlter conﬁguration for message buffer 0 resp. message buffer 1 has to be chosen accordingly.

1 = Both message buffers 0 and 1 are locked against reconﬁguration 0 = Only message buffer 0 locked against reconﬁguration

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Note: In case the node is configured as sync node (SUCC1.TXSY = ’1’) or for single slot mode op-

eration (SUCC1.TSM = ’1’), message buffer 0 resp. 1 is reserved for sync frames or single slot frames and have to be configured with the node-specific key slot ID. In case the node is neither configured as sync nodenor for single slot operationmessage buffer 0 resp. 1is treated like all other message buffers.

Message Buffer 0 ⇓ Static Buffers Message Buffer 1

⇓ Static + Dynamic ⇐ FDB

…

Message Buffer N-1 Message Buffer N ⇐ LCB LCB ≥ FDB, LCB ≥ FFB

Buffers

FIFO conﬁgured: FFB > FDB

⇓ FIFO ⇐ FFB No FIFO conﬁgured: FFB ≥ 128

The programmer has to ensure that the configuration defined by FDB[7:0], FFB[7:0], and LCB[7:0] is valid. The CC does not check for erroneous configurations!

Note: Themaximum number of header sections is 128. This means a maximum of 128 message buff-

ers can be configured. The maximum length of a data section is 254 bytes. The length of the data section may be configured differently for each message buffer. For details see Section

5.12 Message RAM.

In case two or more messagebuffers are assigned to slot 1 by use of cycle filtering, all of them must be located either in the "Static Buffers" or at the beginning of the "Static + Dynamic Buffers" section.

The payload length configured and the length of the data section need to be configured identical for all message buffers belonging to the FIFO via WRHS2.PLC[6:0] and WRHS3.DP[10:0]. When the CC is not in DEFAULT_CONFIGor CONFIG state reconfiguration of message buffers belonging to the FIFO is locked.

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4.7.2 FIFO Rejection Filter (FRF)

The FIFO Rejection Filter defines a user specified sequence of bits to which channel, frame ID, and cycle count of the incoming frames are compared. Together with the FIFO Rejection Filter Mask this register determines whether a message is rejectedby theFIFO. The FRF register can be written during DEFAULT_CONFIG or CONFIG state only.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FRF R0000000

0x0304 W

Reset 0 000000110000000

Bit 1514131211109876543210

R0 0 0

Reset 0 000000000000000

FID10* FID9* FID8* FID7* FID6* FID5* FID4* FID3* FID2* FID1* FID0* CH1* CH0*

RNF* RSS* CYF6* CYF5* CYF4* CYF3* CYF2* CYF1* CYF0*

CH[1:0] Channel Filter

11 = no reception 10 = receive only on channel A 01 = receive only on channel B 00 = receive on both channels

Note: If reception on both channels is configured, also in static segment always both frames (from

channel A and B) are stored in the FIFO, even if they are identical.

FID[10:0] Frame ID Filter

Determines the frame ID to be rejected by the FIFO. With the additional conﬁguration of register FRFM, the corresponding frame ID ﬁlter bits are ignored, which results in further rejected frame IDs. When FRFM.MFID[10:0] is zero, a frame ID ﬁlter value of zero means that no frame ID is rejected.

0…2047 = Frame ID ﬁlter values

CYF[6:0] Cycle Counter Filter

The 7-bit cycle counter filter determines the cycle set to which frame ID and channel rejection filter are applied. In cycles not belonging to the cycle set specified by CYF[6:0], all frames are rejected. For details about the configuration of the cycle counter filter see Section 5.7.2 Cycle Counter Filtering.

RSS Reject in Static Segment

If this bit is set, the FIFO is used only for the dynamic segment.

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1 = Reject messages in static segment 0 = FIFO also used for static segment

RNF Reject Null Frames

If this bit is set, received null frames are not stored in the FIFO. 1 = Reject all null frames 0 = Null frames are stored in the FIFO

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4.7.3 FIFO Rejection Filter Mask (FRFM)

The FIFO Rejection Filter Mask specifies which of the corresponding frame ID filter bits are relevant for rejection filtering. If a bit is set, it indicates that the corresponding bit in the FRF register will not be considered for rejection filtering. The FRFM register can be written during DEFAULT_CONFIG or CONFIG state only.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FRFM R0000000000000000 0x0308 W

Reset 0 000000000000000

Bit 1514131211109876543210

R0 0 0

Reset 0 000000000000000

MFID

MFID9*MFID8*MFID7*MFID6*MFID5*MFID4*MFID3*MFID2*MFID1*MFID

10*

MFID[10:0] Mask Frame ID Filter

1 = Ignore corresponding frame ID ﬁlter bit. 0 = Corresponding frame ID ﬁlter bit is used for rejection ﬁltering

4.7.4 FIFO Critical Level (FCL)

The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FCL R0000000000000000

0x030C W

Reset 0 000000000000000

Bit 1514131211109876543210

R00000000

Reset 0 000000010000000

CL7* CL6* CL5* CL4* CL3* CL2* CL1* CL0*

CL[7:0] Critical Level

When the receive FIFO ﬁll level FSR.RFFL[7:0] is equal or greater than the critical level conﬁgured by CL[7:0], the receive FIFO critical level ﬂag FSR.RFCL is set. If CL[7:0] is programmed to values > 128, bit FSR.RFCL is never set. When FSR.RFCL changes from ’0’ to ’1’ bit SIR.RFCL is set to ’1’, and if enabled, an interrupt is generated.

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4.8 Message Buffer Status Registers

4.8.1 Message Handler Status (MHDS)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MHDS R 0 MBU6 MBU5 MBU4 MBU3 MBU2 MBU1 MBU0 0 MBT6 MBT5 MBT4 MBT3 MBT2 MBT1 MBT0 0x0310 W

Reset 0 000000000000000

Bit 1514131211109876543210

R 0 FMB6 FMB5 FMB4 FMB3 FMB2 FMB1 FMB0 CRAM

Reset 0 000000010000000

A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect on the flag. The register will also be cleared by hard reset or by CHI command CLEAR_RAMS.

PIBF Parity Error Input Buffer RAM 1,2

1 = Parity error occurred when reading Input Buffer RAM 1,2 0 = No parity error

MFMB FMBD PTBF2 PTBF1 PMR POBF PIBF

POBF Parity Error Output Buffer RAM 1,2

1 = Parity error occurred when reading Output Buffer RAM 1,2 0 = No parity error

PMR Parity Error Message RAM

1 = Parity error occurred when reading the Message RAM 0 = No parity error

PTBF1 Parity Error Transient Buffer RAM A

1 = Parity error occurred when reading Transient Buffer RAM A 0 = No parity error

PTBF2 Parity Error Transient Buffer RAM B

1 = Parity error occurred when reading Transient Buffer RAM B 0 = No parity error

Note: When one of the flags PIBF, POBF, PMR, PTBF1, PTBF2 changes from ’0’ to ’1’

EIR.PERR is set to ’1’.

FMBD Faulty Message Buffer Detected

1 = Message buffer referenced by FMB[6:0] holds faulty data due to a parity error

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0 = No faulty message buffer

MFMB Multiple Faulty Message Buffers detected

1 = Another faulty message buffer was detected while flag FMBD is set 0 = No additional faulty message buffer

CRAM Clear all internal RAM’s

Signals that execution of the CHI command CLEAR_RAMS is ongoing (all bits of all internal RAM blocks are written to ’0’). The bit is set by hard reset or by CHI command CLEAR_RAMS.

1 = Execution of the CHI command CLEAR_RAMS ongoing 0 = No execution of the CHI command CLEAR_RAMS

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FMB[6:0] Faulty Message Buffer

Parity error occurred when reading from the message buffer or when transferring data from Input Buffer or Transient Buffer 1,2 to the message buffer referenced by FMB[6:0]. Value only valid when one of the flags PIBF, PMR, PTBF1, PTBF2, and ﬂag FMBD is set. Updated only after the Host has reset flag FMBD.

MBT[6:0] Message Buffer Transmitted

Number of last successfully transmitted message buffer. If the message buffer is configured for single-shot mode, the respective TXR flag in the TXRQ1/2/3/4 registers was reset.

MBU[6:0] Message Buffer Updated

Number of message buffer that was updated last by the CC. For this message buffer the respective ND and / or MBC flag in the NDAT1/2/3/4 registers and the MBSC1/2/3/4 registers are also set.

Note: MBT[6:0] and MBU[6:0] are reset when the CC leaves CONFIG state or enters STARTUP

state.

4.8.2 Last Dynamic Transmit Slot (LDTS)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LDTS R00000

0x0314 W

Reset 0 000000000000000

Bit 1514131211109876543210

R00000

Reset 0 000000000000000

LDTB10

LDTB9 LDTB8 LDTB7 LDTB6 LDTB5 LDTB4 LDTB3 LDTB2 LDTB1 LDTB0

LDTA10

LDTA9 LDTA8 LDTA7 LDTA6 LDTA5 LDTA4 LDTA3 LDTA2 LDTA1 LDTA0

The register is reset when the CC leaves CONFIG state or enters STARTUP state. LDTA[10:0] Last Dynamic Transmission Channel A

Value of vSlotCounter[A] at the time of the last frame transmission on channel A in the dynamic segment of this node. It is updated at the end of the dynamic segment and is reset to zero if no frame was transmitted during the dynamic segment.

LDTB[10:0] Last Dynamic Transmission Channel B

Value of vSlotCounter[B] at the time of the last frame transmission on channel B in the dynamic segment of this node. It is updated at the end of the dynamic segment and is reset to zero if no frame was transmitted during the dynamic segment.

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4.8.3 FIFO Status Register (FSR)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FSR R00000

0x0318 W

Reset 0 000000000000000

Bit 1514131211109876543210

R RFFL7 RFFL6 RFFL5 RFFL4 RFFL3 RFFL2 RFFL1 RFFL0 0 0000RFORFCL RFNE

Reset 0 000000000000000

0000000000

The register is reset when the CC leaves CONFIG state or enters STARTUP state. RFNE Receive FIFO Not Empty

This ﬂag is set by the CC when a received valid frame (data or null frame depending on rejection mask) was stored in the FIFO. In addition, interrupt ﬂag SIR.RFNE is set. The bit is reset after the Host has read all message from the FIFO.

1 = Receive FIFO is not empty 0 = Receive FIFO is empty

RFCL Receive FIFO Critical Level

This ﬂag is set when the receive FIFO ﬁll level RFFL[7:0] is equal or greater than the critical level as conﬁgured by FCL.CL[7:0]. The ﬂag is cleared by the CC as soon as RFFL[7:0] drops below FCL.CL[7:0]. When RFCL changes from ’0’ to ’1’ bit SIR.RFCL is set to ’1’, and if enabled, an interrupt is generated.

1 = Receive FIFO critical level reached 0 = Receive FIFO below critical level

RFO Receive FIFO Overrun

The ﬂag is set by the CC when a receive FIFO overrun is detected. When a receive FIFO overrun occurs, the oldest message is overwritten with the actual received message. In addition, interrupt ﬂag EIR.RFO is set.The ﬂag is cleared by the next FIFO read access issued by the Host.

1 = A receive FIFO overrun has been detected 0 = No receive FIFO overrun detected

RFFL[7:0] Receive FIFO Fill Level

Number of FIFO buffers filled with new data not yet read by the Host. Maximum value is 128.

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4.8.4 Message Handler Constraints Flags (MHDF)

Some constraints exist for the Message Handler regarding eray_bclk frequency, Message RAM configuration, and FlexRay bus traffic (see Addendum to E-Ray FlexRay IP-Module Specification). To simplify software development, constraints violations are reported by setting flags in the MHDF.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MHDF R0000000000000000

0x031C W

Reset 0 000000000000000

Bit 1514131211109876543210

R0000000

Reset 0 000000000000000

WAHP

TBFB TBFA FNFB FNFA SNUB SNUA

A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect on the flag. A hard reset will also clear the register. The register is reset when the CC leaves CONFIG state or enters STARTUP state.

SNUA Status Not Updated Channel A

This ﬂag is set by the CC when the Message Handler, due to overload condition, was not able to update a message buffer’s status MBS with respect to channel A.

1 = MBS for channel A not updated 0 = No overload condition occurred when updating MBS for channel A

SNUB Status Not Updated Channel B

This ﬂag is set by the CC when the Message Handler, due to overload condition, was not able to update a message buffer’s status MBS with respect to channel B.

1 = MBS for channel B not updated 0 = No overload condition occurred when updating MBS for channel B

FNFA Find Sequence Not Finished Channel A

This ﬂag is set by the CC when the Message Handler, due to overload condition, was not able to ﬁnish a ﬁnd sequence (scan of Message RAM for matching message buffer) with respect to channel A.

1 = Find sequence not ﬁnished for channel A 0 = No ﬁnd sequence not ﬁnished for channel A

FNFB Find Sequence Not Finished Channel B

This ﬂag is set by the CC when the Message Handler, due to overload condition, was not able to

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ﬁnish a ﬁnd sequence (scan of Message RAM for matching message buffer) with respect to channel B.

1 = Find sequence not ﬁnished for channel B 0 = No ﬁnd sequence not ﬁnished for channel B

TBFA Transient Buffer Access Failure A

This ﬂag is set by the CC when a read or write access to TBF A requested by PRT A could not complete within the available time.

1 = TBF A access failure 0 = No TBF A access failure

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TBFB Transient Buffer Access Failure B

This ﬂag is set by the CC when a read or write access to TBF B requested by PRT B could not complete within the available time.

1 = TBF B access failure 0 = No TBF B access failure

WAHP Write Attempt to Header Partition

Outside DEFAULT_CONFIG and CONFIG state this ﬂag is set by the CC when the message handler tries to write message data into the header partition of the Message RAM due to faulty conﬁguration of a message buffer. The write attempt is not executed, to protect the header partition from unintended write accesses.

1 = Write attempt to header partition 0 = No write attempt to header partition

Note: When one of the flags SNUA, SNUB, FNFA, FNFB, TBFA, TBFB, WAHP changes from

’0’ to ’1’, interrupt flag EIR.MHF is set to ’1’.

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4.8.5 Transmission Request 1/2/3/4 (TXRQ1/2/3/4)

The four registers reflect the state of the TXR flags of all configured message buffers. The flags are evaluated for transmit buffers only. If the number of configured message buffers is less than 128, the remaining TXR flags have no meaning.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TXRQ4

0x032C W

Reset 0 000000000000000

Bit 1514131211109876543210

Reset 0 000000000000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TXRQ3

0x0328 W

Reset 0 000000000000000

TXR127 TXR126 TXR125 TXR124 TXR123 TXR122 TXR121 TXR120 TXR119 TXR118 TXR117 TXR116 TXR115 TXR114 TXR113 TXR112

TXR111 TXR110 TXR109 TXR108 TXR107 TXR106 TXR105 TXR104 TXR103 TXR102 TXR101 TXR100 TXR99 TXR98 TXR97 TXR96

R TXR95 TXR94 TXR93 TXR92 TXR91 TXR90 TXR89 TXR88 TXR87 TXR86 TXR85 TXR84 TXR83 TXR82 TXR81 TXR80

Bit 1514131211109876543210

R TXR79 TXR78 TXR77 TXR76 TXR75 TXR74 TXR73 TXR72 TXR71 TXR70 TXR69 TXR68 TXR67 TXR66 TXR65 TXR64

Reset 0 000000000000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TXRQ2

0x0324 W

TXRQ1

0x0320 W

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R TXR63 TXR62 TXR61 TXR60 TXR59 TXR58 TXR57 TXR56 TXR55 TXR54 TXR53 TXR52 TXR51 TXR50 TXR49 TXR48

Reset 0 000000000000000

Bit 1514131211109876543210

R TXR47 TXR46 TXR45 TXR44 TXR43 TXR42 TXR41 TXR40 TXR39 TXR38 TXR37 TXR36 TXR35 TXR34 TXR33 TXR32

Reset 0 000000000000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R TXR31 TXR30 TXR29 TXR28 TXR27 TXR26 TXR25 TXR24 TXR23 TXR22 TXR21 TXR20 TXR19 TXR18 TXR17 TXR16

Reset 0 000000000000000

Bit 1514131211109876543210

R TXR15 TXR14 TXR13 TXR12 TXR11 TXR10 TXR9 TXR8 TXR7 TXR6 TXR5 TXR4 TXR3 TXR2 TXR1 TXR0

Reset 0 000000000000000

TXR[127:0] Transmission Request

If the flag is set, the respective message buffer is ready for transmission respectively transmission of this message buffer is in progress. In single-shot mode the flags are reset after transmission has completed.

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4.8.6 New Data 1/2/3/4 (NDAT1/2/3/4)

The four registers reflect thestate of the ND flags ofall configured message buffers. NDflags belonging to transmit buffers haveno meaning. If the numberof configured message buffers isless than 128, the remaining ND flags have no meaning. The registers are reset when the CC leaves CONFIG state or enters STARTUP state.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

NDAT4

0x033C W

NDAT3

0x0338 W

R ND127 ND126 ND125 ND124 ND123 ND122 ND121 ND120 ND119 ND118 ND117 ND116 ND115 ND114 ND113 ND112

Reset 0 000000000000000

Bit 1514131211109876543210

R ND111 ND110 ND109 ND108 ND107 ND106 ND105 ND104 ND103 ND102 ND101 ND100 ND99 ND98 ND97 ND96

Reset 0 000000000000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R ND95 ND94 ND93 ND92 ND91 ND90 ND89 ND88 ND87 ND86 ND85 ND84 ND83 ND82 ND81 ND80

Reset 0 000000000000000

Bit 1514131211109876543210

R ND79 ND78 ND77 ND76 ND75 ND74 ND73 ND72 ND71 ND70 ND69 ND68 ND67 ND66 ND65 ND64

Reset 0 000000000000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

NDAT2

0x0334 W

NDAT1

0x0330 W

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R ND63 ND62 ND61 ND60 ND59 ND58 ND57 ND56 ND55 ND54 ND53 ND52 ND51 ND50 ND49 ND48

Reset 0 000000000000000

Bit 1514131211109876543210

R ND47 ND46 ND45 ND44 ND43 ND42 ND41 ND40 ND39 ND38 ND37 ND36 ND35 ND34 ND33 ND32

Reset 0 000000000000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R ND31 ND30 ND29 ND28 ND27 ND26 ND25 ND24 ND23 ND22 ND21 ND20 ND19 ND18 ND17 ND16

Reset 0 000000000000000

Bit 1514131211109876543210

R ND15 ND14 ND13 ND12 ND11 ND10 ND9 ND8 ND7 ND6 ND5 ND4 ND3 ND2 ND1 ND0

Reset 0 000000000000000

ND[127:0] New Data

The flags are set when a valid received data frame matches the message buffer’s filter configuration, independent of the payload length received or the payload length configured for that message buffer. The flags are not set after reception of null frames except for message buffers belonging to the receive FIFO. An ND flag is reset when the header section of the corresponding message buffer is reconfigured or when the data section has been transferred to the Output Buffer.

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4.8.7 Message Buffer Status Changed 1/2/3/4 (MBSC1/2/3/4)

The four registers reflect the state of the MBC flags of all configured message buffers. If the number of configured message buffers is less than 128, the remaining MBC flags have no meaning. The registers are reset when the CC leaves CONFIG state or enters STARTUP state.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MBSC4

0x034C W

Reset 0 000000000000000

Bit 1514131211109876543210

Reset 0 000000000000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MBSC3

0x0348 W

Reset 0 000000000000000

MBC127 MBC126 MBC125 MBC124 MBC123 MBC122 MBC121 MBC120 MBC119 MBC118 MBC117 MBC116 MBC115 MBC114 MBC113 MBC112

MBC111 MBC110 MBC109 MBC108 MBC107 MBC106 MBC105 MBC104 MBC103 MBC102 MBC101 MBC100 MBC99 MBC98 MBC97 MBC96

MBC95 MBC94 MBC93 MBC92 MBC91 MBC90 MBC89 MBC88 MBC87 MBC86 MBC85 MBC84 MBC83 MBC82 MBC81 MBC80

Bit 1514131211109876543210

MBC79 MBC78 MBC77 MBC76 MBC75 MBC74 MBC73 MBC72 MBC71 MBC70 MBC69 MBC68 MBC67 MBC66 MBC65 MBC64

Reset 0 000000000000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MBSC2

0x0344 W

Reset 0 000000000000000

Bit 1514131211109876543210

Reset 0 000000000000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MBSC1

0x0340 W

Reset 0 000000000000000

Bit 1514131211109876543210

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Reset 0 000000000000000

MBC63 MBC62 MBC61 MBC60 MBC59 MBC58 MBC57 MBC56 MBC55 MBC54 MBC53 MBC52 MBC51 MBC50 MBC49 MBC48

MBC47 MBC46 MBC45 MBC44 MBC43 MBC42 MBC41 MBC40 MBC39 MBC38 MBC37 MBC36 MBC35 MBC34 MBC33 MBC32

MBC31 MBC30 MBC29 MBC28 MBC27 MBC26 MBC25 MBC24 MBC23 MBC22 MBC21 MBC20 MBC19 MBC18 MBC17 MBC16

MBC15 MBC14 MBC13 MBC12 MBC11 MBC10 MBC9 MBC8 MBC7 MBC6 MBC5 MBC4 MBC3 MBC2 MBC1 MBC0

MBC[127:0] Message Buffer Status Changed

An MBC flag is set whenever the Message Handler changes one of the status flags VFRA,

VFRB, SEOA, SEOB, CEOA, CEOB, SVOA, SVOB, TCIA, TCIB, ESA, ESB, MLST, FTA, FTB in the header section (see 4.11.5 Message Buffer Status (MBS) and 5.12.1 Header

Partition, header 4) of the respective message buffer. An MBC flag is reset when the header section of the corresponding message buffer is reconfigured or when it has been transferred to the Output Buffer.

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4.9 Identiﬁcation Registers

4.9.1 Core Release Register (CREL)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CREL R REL3 REL2 REL1 REL0 STEP7

0x03F0 W

Reset release info

Bit 1514131211109876543210

R MON7 MON6 MON5 MON4 MON3 MON2 MON1 MON0 DAY7 DAY6 DAY5 DAY4 DAY3 DAY2 DAY1 DAY0

Reset release info

STEP6

STEP5 STEP4 STEP3 STEP2 STEP1 STEP0

DAY[7:0] Design Time Stamp, Day

Two digits, BCD-coded.

MON[7:0] Design Time Stamp, Month

Two digits, BCD-coded.

YEAR[3:0] Design Time Stamp, Year

One digit, BCD-coded.

YEAR3 YEAR2 YEAR1 YEAR0

STEP[7:0] Step of Core Release

Two digits, BCD-coded.

REL[3:0] Core Release

One digit, BCD-coded.

Table 5 below shows how releases are coded in register CREL.

Release Step Sub-Step Name

0 7 0 Beta2 0 7 1 Beta2ct 0 7 2 Revision 1.0RC1 1 0 0 Revision 1.0.0 1 0 1 Revision 1.0.1

Table 5: Coding for releases

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4.9.2 Endian Register (ENDN)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ENDN R ETV31 ETV30 ETV29 ETV28 ETV27

0x03F4 W

Reset 1 000011101100101

ETV26

ETV25 ETV24 ETV23 ETV22 ETV21 ETV20 ETV19 ETV18 ETV17 ETV16

Bit 1514131211109876543210

R ETV15 ETV14 ETV13 ETV12 ETV11 ETV10 ETV9 ETV8 ETV7 ETV6 ETV5 ETV4 ETV3 ETV2 ETV1 ETV0

Reset 0 100001100100001

ETV[31:0] Endianness Test Value

The endianness test value is 0x87654321.

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4.10 Input Buffer

Double buffer structure consisting of Input Buffer Host and Input Buffer Shadow. While the Host can write to Input Buffer Host, the transfer to the Message RAM is done from Input Buffer Shadow. The Input Buffer holds the header and data sections to be transferred to the selected message buffer in the Message RAM. It is used to configure the message buffers in the Message RAM and to update the data sections of transmit buffers.

When updating the header section of a message buffer in the Message RAM from the Input Buffer, the Message Buffer Status as described in Section 4.11.5 Message Buffer Status (MBS) is automatically reset to zero.

The header sections of message buffers belonging to the receive FIFO can only be (re)configured when the CC is in DEFAULT_CONFIG or CONFIG state. For those message buffers only the payload length configured and the data pointer need to be configured via WRHS2.PLC[6.0] and WRHS3.DP[10:0]. All information required for acceptance filtering is taken from the FIFO rejection filter and the FIFO rejection filter mask.

The data transfer between Input Buffer (IBF) and Message RAM is described in detail in Section

5.11.2.1 Data Transfer from Input Buffer to Message RAM.

4.10.1 Write Data Section [1…64] (WRDSn)

Holds the data words to be transferred to the data section of the addressed message buffer. The data words (DW DW

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WRDSn R 0x0400 -

0x04FC

Reset 0 000000000000000

Bit 1514131211109876543210

Reset 0 000000000000000

) are written to the Message RAM in transmission order from DW1(byte0, byte1) to

(PL = number of data words as defined by the payload length configured WRHS2.PLC[6:0]).

MD31 MD30 MD29 MD28 MD27 MD26 MD25 MD24 MD23 MD22 MD21 MD20 MD19 MD18 MD17 MD16

MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0

MD[31:0] Message Data

MD[7:0] = DWn, byte MD[15:8] = DWn, byte

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MD[23:16] = DW MD[31:24] = DW

n+1 n+1

n-1 n

, byte , byte

n+1 n+2

Note: DW127 is located on WRDS64.MD[15:0]. In this case WRDS64.MD[31:16] is unused (no

valid data). The Input Buffer RAMs are initialized to zero when leaving hard reset or by CHI command CLEAR_RAMS.

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4.10.2 Write Header Section 1 (WRHS1)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WRHS1 R0 0

0x0500 W

Reset 0 000000000000000

Bit 1514131211109876543210

R00000

Reset 0 000000000000000

MBI TXM PPIT CFG CHB CHA

FID10 FID9 FID8 FID7 FID6 FID5 FID4 FID3 FID2 FID1 FID0

CYC6 CYC5 CYC4 CYC3 CYC2 CYC1 CYC0

FID[10:0] Frame ID

Frame ID of the selected message buffer. The frame ID defines the slot number for transmission / reception of the respective message. Message buffers with frame ID = ’0’ are considered as

not valid.

CYC[6:0] Cycle Code

The 7-bit cycle code determines the cycle set used for cycle counter ﬁltering. For details about the configuration of the cycle code see Section 5.7.2 Cycle Counter Filtering.

CHA, CHB Channel Filter Control

The 2-bit channel ﬁltering ﬁeld associated with each buffer serves as a ﬁlter for receive buffers, and as a control ﬁeld for transmit buffers.

CHA CHB

1 1 both channels

(static segment only)

1 0 channel A channel A 0 1 channel B channel B 0 0 no transmission ignore frame

Transmit Buffer

transmit frame on

channel A or B (store ﬁrst semantically valid frame, static segment only)

Receive Buffer

store frame received from

Note: Ifa message buffer is configured for the dynamic segment and both bits of thechannel filtering

field are set to ’1’, no frames are transmitted resp. received frames are ignored (same function as CHA = CHB = ’0’)

CFG Message Buffer Direction Conﬁguration Bit

This bit is used to conﬁgure the corresponding buffer as transmit buffer or as receive buffer. For message buffers belonging to the receive FIFO the bit is not evaluated.

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1 = The corresponding buffer is conﬁgured as Transmit Buffer 0 = The corresponding buffer is conﬁgured as Receive Buffer

PPIT Payload Preamble Indicator Transmit

This bit is used to control the state of the Payload Preamble Indicator in transmit frames. If the bit is set in a static message buffer, the respective message buffer holds network management information. If the bit is set in a dynamic message buffer the ﬁrst two bytes of the payload segment may be used for message ID ﬁltering by the receiver. Message ID ﬁltering of received FlexRay frames is not supported by the E-Ray module, but can be done by the Host.

1 = Payload Preamble Indicator set 0 = Payload Preamble Indicator not set

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TXM Transmission Mode

This bit is used to select the transmission mode (see Section 5.8.3 Transmit Buffers). 1 = Single-shot mode 0 = Continuous mode

MBI Message Buffer Interrupt

This bit enables the receive / transmit interrupt for the corresponding message buffer. After a dedicated receive buffer has been updated by the Message Handler, ﬂag SIR.RXI and /or SIR.MBSI are set. After a transmission has completed ﬂag SIR.TXI is set.

1 = The corresponding message buffer interrupt is enabled 0 = The corresponding message buffer interrupt is disabled

4.10.3 Write Header Section 2 (WRHS2)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WRHS2 R000000000

0x0504 W

Reset 0 000000000000000

Bit 1514131211109876543210

R00000

Reset 0 000000000000000

CRC10 CRC9 CRC8 CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0

PLC6 PLC5 PLC4 PLC3 PLC2 PLC1 PLC0

CRC[10:0] Header CRC (vRF!Header!HeaderCRC)

Receive Buffer: Configuration not required Transmit Buffer: Header CRC calculated and conﬁgured by the Host For calculation of the header CRC the payload length of the frame send on the bus has to be con-

sidered. In static segment the payload length of all frames is conﬁgured by MHDC.SFDL[6:0].

PLC[6:0] Payload Length Conﬁgured

Length of data section (number of 2-byte words) as configured by the Host. During static segment the static frame payload length as conﬁgured by MHDC.SFDL[6:0] deﬁnes the payload length for all static frames. If the payload length conﬁgured by PLC[6:0] is shorter than this value padding bytes are inserted to ensure that frames have proper physical length. The padding pattern is logical zero.

4.10.4 Write Header Section 3 (WRHS3)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

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WRHS3 R0000000000000000

0x0508 W

Reset 0 000000000000000

Bit 1514131211109876543210

R00000

Reset 0 000000000000000

DP10 DP9 DP8 DP7 DP6 DP5 DP4 DP3 DP2 DP1 DP0

DP[10:0] Data Pointer

Pointer to the first 32-bit word of the data section of the addressed message buffer in the Message RAM.

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4.10.5 Input Buffer Command Mask (IBCM)

Configures how the message buffer in the Message RAM selected byregister IBCR is updated. When IBF Host and IBF Shadow are swapped, also mask bits LHSH, LDSH, and STXRH are swapped with bits LHSS, LDSS, and STXRS to keep them attached to the respective Input Buffer transfer.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

IBCM

R0000000000000

0x0510 W

Reset 0 000000000000000

Bit 1514131211109876543210

R0000000000000

Reset 0 000000000000000

STXRS

STXRH

LDSS LHSS

LDSH LHSH

LHSH Load Header Section Host

1 = Header section selected for transfer from Input Buffer to the Message RAM 0 = Header section is not updated

LDSH Load Data Section Host

1 = Data section selected for transfer from Input Buffer to the Message RAM 0 = Data section is not updated

STXRH Set Transmission Request Host

If this bit is set to ’1’, the TXR flag for the selected message buffer is set in the TXRQ1/2/3/4 registers to release the message buffer for transmission. In single-shot mode the flag is cleared by the CC after transmission has completed. TXR is evaluated for transmit buffers only.

1 = Set TXR ﬂag, transmit buffer released for transmission 0 = Reset TXR ﬂag

LHSS Load Header Section Shadow

1 = Header section selected for transfer from Input Buffer to the Message RAM

(transfer ongoing or ﬁnished)

0 = Header section is not updated

LDSS Load Data Section Shadow

1 = Data section selected for transfer from Input Buffer to the Message RAM

(transfer ongoing or ﬁnished)

0 = Data section is not updated

STXRS Set Transmission Request Shadow

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1 = Set TXR ﬂag, transmit buffer released for transmission (operation ongoing or ﬁnished) 0 = Reset TXR ﬂag

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4.10.6 Input Buffer Command Request (IBCR)

When the Host writes the number of the target message buffer in the Message RAM to IBRH[6:0], IBF Host and IBF Shadow are swapped. In addition the message buffer numbers stored under IBRH[6:0] and IBRS[6:0] are also swapped (see also Section 5.11.2.1 Data Transfer from Input Buffer to Message RAM).

With this write operation the IBSYSis set to ’1’. The Message Handler then starts to transfer the contents of IBF Shadow to the message buffer in the Message RAM selected by IBRS[6:0].

While the Message Handler transfers the data from IBF Shadow to the target message buffer in the Message RAM, the Host may write the next message into the IBF Host. After the transfer between IBF Shadow and the Message RAM has completed, IBSYS is set back to ’0’ and the next transfer to the Message RAM may be started by the Host bywriting the respective target message buffer number to IBRH[6:0].

If a write access to IBRH[6:0] occurs while IBSYS is ’1’, IBSYH is set to ’1’. After completion of the ongoing data transfer from IBF Shadow to the Message RAM, IBF Host and IBF Shadow are swapped, IBSYH is reset to ’0’. IBSYS remains set to ’1’, and the next transfer to the Message RAM is started. In addition the message buffer numbers stored under IBRH[6:0] and IBRS[6:0] are also swapped.

Any write access to an Input Buffer register whileboth IBSYSand IBSYH are setwill cause the error flag EIR.IIBA to be set. In this case the Input Buffer will not be changed.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

IBCR

R IBSYS 00000000IBRS6 IBRS5 IBRS4 IBRS3 IBRS2 IBRS1 IBRS0

0x0514 W

Reset 0 000000000000000

Bit 1514131211109876543210

R IBSYH 00000000

Reset 0 000000000000000

IBRH6 IBRH5 IBRH4 IBRH3 IBRH2 IBRH1 IBRH0

IBRH[6:0] Input Buffer Request Host

Selects the target message buffer in the Message RAM for data transfer from Input Buffer. Valid values are 0x00 to 0x7F (0…127).

IBSYH Input Buffer Busy Host

Set to ’1’ by writing IBRH[6:0] while IBSYS is still ’1’. After the ongoing transfer between IBF Shadow and the Message RAM has completed, the IBSYH is set back to ’0’.

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1 = Request while transfer between IBF Shadow and Message RAM in progress 0 = No request pending

IBRS[6:0] Input Buffer Request Shadow

Number of the target message buffer actually updated / lately updated. Valid values are 0x00 to 0x7F (0…127).

IBSYS Input Buffer Busy Shadow

Set to ’1’ after writing IBRH[6:0]. When the transfer between IBF Shadow and the Message RAM has completed, IBSYS is set back to ’0’.

1 = Transfer between IBF Shadow and Message RAM in progress 0 = Transfer between IBF Shadow and Message RAM completed

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4.11 Output Buffer

Double buffer structure consisting of Output Buffer Host and Output Buffer Shadow. Used to read out message buffers from the Message RAM. While the Host can read from Output Buffer Host, the Message Handler transfers the selected message buffer from Message RAM to Output Buffer Shadow. The data transfer between Message RAM and Output Buffer (OBF) is described in Section

5.11.2.2 Data Transfer from Message RAM to Output Buffer.

4.11.1 Read Data Section [1…64] (RDDSn)

Holds the data words read from the data section of the addressed message buffer. The data words

) are read from the Message RAM in reception order from DW1(byte0, byte1) to DWPL(PL =

(DW

number of data words as defined by the payload length configured RDHS2.PLC[6:0]).

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RDDSn R MD31 MD30 MD29 MD28 MD27 MD26 MD25 MD24 MD23 MD22 MD21 MD20 MD19 MD18 MD17 MD16

0x0600 -

0x06FC

Reset 0 000000000000000

Bit 1514131211109876543210

R MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0

Reset 0 000000000000000

MD[31:0] Message Data

MD[7:0] = DW MD[15:8] = DWn, byte MD[23:16] = DW MD[31:24] = DW

, byte

n+1 n+1

n-1 n

, byte , byte

n+1 n+2

Note: DW127 is located on RDDS64.MD[15:0]. Inthis case RDDS64.MD[31:16] is unused (noval-

id data). The Output Buffer RAMs are initialized to zero when leaving hard reset or by CHI command CLEAR_RAMS.

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4.11.2 Read Header Section 1 (RDHS1)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RDHS1 R 0 0 MBI TXM PPIT CFG CHB CHA 0 CYC6 CYC5 CYC4 CYC3 CYC2 CYC1 CYC0

0x0700 W

Reset 0 000000000000000

Bit 1514131211109876543210

R00000FID10 FID9 FID8 FID7 FID6 FID5 FID4 FID3 FID2 FID1 FID0

Reset 0 000000000000000

Values as configured by the Host via WRHS1:

FID[10:0] Frame ID CYC[6:0] Cycle Code CHA, CHB Channel Filter Control CFG Message Buffer Direction Conﬁguration Bit PPIT Payload Preamble Indicator Transmit TXM Transmission Mode MBI Message Buffer Interrupt

In case that the message buffer read from the Message RAM belongs to the receive FIFO, FID[10:0] holds the received frame ID, while CYC[6:0], CHA, CHB, CFG, PPIT, TXM, and MBI are reset to ’0’.

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4.11.3 Read Header Section 2 (RDHS2)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RDHS2 R 0 PLR6 PLR5 PLR4 PLR3 PLR2 PLR1 PLR0 0 PLC6 PLC5 PLC4 PLC3 PLC2 PLC1 PLC0

0x0704 W

Reset 0 000000000000000

Bit 1514131211109876543210

R00000CRC10 CRC9 CRC8 CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0

Reset 0 000000000000000

CRC[10:0] Header CRC (vRF!Header!HeaderCRC)

Receive Buffer: Header CRC updated from received data frames Transmit Buffer: Header CRC calculated and conﬁgured by the Host

PLC[6:0] Payload Length Conﬁgured

Length of data section (number of 2-byte words) as configured by the Host.

PLR[6:0] Payload Length Received (vRF!Header!Length)

Payload length value updated from received data frames (exception: if message buffer belongs to the receive FIFO PLR[6:0] is also updated from received null frames)

When a message is stored into a message buffer the following behaviour with respect to payload length received and payload length configured is implemented:

PLR[6:0] > PLC[6:0]: The payload data stored in the message buffer is truncated to the payload

length configured if PLC[6:0] even or else truncated to PLC[6:0] + 1.

PLR[6:0] ≤ PLC[6:0]: The received payload data is stored into the message buffers data section.

The remaining data bytes of the data section as configured by PLC[6:0] are filled with undefined data

PLR[6:0] = zero: The message buffer’s data section is filled with undefined data PLC[6:0] = zero: Message buffer has no data section configured. No data is stored into the

message buffer’s data section.

Note: The Message RAM is organized in 4-byte words. When received data is stored into a message

buffer’s data section, the number of 2-byte data words written into the message buffer is PLC[6:0] rounded to the next even value. PLC[6:0] should be configured identical for all message buffers belonging to the receive FIFO. Header 2 is updated from data frames only.

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4.11.4 Read Header Section 3 (RDHS3)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RDHS3 R 0 0 RES PPI NFI SYN SFI RCI 0 0 RCC5 RCC4 RCC3 RCC2 RCC1 RCC0

0x0708 W

Reset 0 000000000000000

Bit 1514131211109876543210

R00000DP10 DP9 DP8 DP7 DP6 DP5 DP4 DP3 DP2 DP1 DP0

Reset 0 000000000000000

DP[10:0] Data Pointer

Pointer to the first 32-bit word of the data section of the addressed message buffer in the Message RAM.

RCC[5:0] Receive Cycle Count (vRF!Header!CycleCount)

Cycle counter value updated from received data frame.

RCI Received on Channel Indicator (vSS!Channel)

Indicates the channel from which the received data frame was taken to update the respective receive buffer.

1 = Frame received on channel A 0 = Frame received on channel B

SFI Startup Frame Indicator (vRF!Header!SuFIndicator)

A startup frame is marked by the startup frame indicator. 1 = The received frame is a startup frame 0 = The received frame is not a startup frame

SYN Sync Frame Indicator (vRF!Header!SyFIndicator)

A sync frame is marked by the sync frame indicator. 1 = The received frame is a sync frame 0 = The received frame is not a sync frame

NFI Null Frame Indicator (vRF!Header!NFIndicator)

Is set to ’1’ after storage of the first received data frame. 1 = At least one data frame has been stored into the respective message buffer 0 = Up to now no data frame has been stored into the respective message buffer

PPI Payload Preamble Indicator (vRF!Header!PPIndicator)

The payload preamble indicator defines whether a network management vector or message ID is

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contained within the payload segment of the received frame. 1 = Static segment: Network management vector in the ﬁrst part of the payload

Dynamic segment:Message ID in the ﬁrst part of the payload

0 = The payload segment of the received frame does not contain a network management vector

nor a message ID

RES Reserved Bit (vRF!Header!Reserved)

Reflects the state of the received reserved bit. The reserved bit is transmitted as ’0’.

Note: Header 3 is updated from data frames only.

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4.11.5 Message Buffer Status (MBS)

The message buffer status is updated by the CC with respect to the assigned channel(s) latest at the end of the slot following the slot assigned to the message buffer. The flags are updated only when the CC is in NORMAL_ACTIVEor NORMAL_PASSIVE state. If only one channel (A orB) is assigned to a message buffer, the channel-specific status flags of the other channel are written to zero. If both channels are assigned to a message buffer, the channel-specific status flags of both channels are updated. The message buffer status is updated only when the slot counter reached the configured frame ID and when the cycle counter filter matched. When the Host updates a message buffer via Input Buffer, all MBS flags are reset to zeroindependent of whichIBCM bitsare set ornot. Fordetails about receive / transmit filtering see Sections 5.7 Filtering and Masking, 5.8 Transmit Process, and

5.9 Receive Process. Whenever the Message Handler changes oneof the flagsVFRA, VFRB, SEOA, SEOB, CEOA, CEOB, SVOA,SVOB, TCIA, TCIB, ESA,ESB, MLST, FTA, FTB the respective message buffer’s MBC flag in registers MBSC1/2/3/4 is set.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MBS

R 0 0 RESS PPIS NFIS SYNS SFIS RCIS 0 0 CCS5 CCS4 CCS3 CCS2 CCS1 CCS0

0x070C W

Reset 0 000000000000000

Bit 1514131211109876543210

R FTB FTA 0 MLST ESB ESA TCIB TCIA SVOB SVOA CEOB CEOA SEOB SEOA VFRB VFRA

Reset 0 000000000000000

VFRA Valid Frame Received on Channel A (vSS!ValidFrameA)

A valid frame indication is set if a valid frame was received on channel A. 1 = Valid frame received on channel A 0 = No valid frame received on channel A

VFRB Valid Frame Received on Channel B (vSS!ValidFrameB)

A valid frame indication is set if a valid frame was received on channel B. 1 = Valid frame received on channel B 0 = No valid frame received on channel B

SEOA Syntax Error Observed on Channel A (vSS!SyntaxErrorA)

A syntax error was observed in the assigned slot on channel A. 1 = Syntax error observed on channel A 0 = No syntax error observed on channel A

SEOB Syntax Error Observed on Channel B (vSS!SyntaxErrorB)

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A syntax error was observed in the assigned slot on channel B. 1 = Syntax error observed on channel B 0 = No syntax error observed on channel B

CEOA Content Error Observed on Channel A (vSS!ContentErrorA)

A content error was observed in the assigned slot on channel A. 1 = Content error observed on channel A 0 = No content error observed on channel A

CEOB Content Error Observed on Channel B (vSS!ContentErrorB)

A content error was observed in the assigned slot on channel B. 1 = Content error observed on channel B 0 = No content error observed on channel B

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SVOA Slot Boundary Violation Observed on Channel A (vSS!BViolationA)

A slot boundary violation (channel active at the start or at the end of the assigned slot) was observed on channel A.

1 = Slot boundary violation observed on channel A 0 = No slot boundary violation observed on channel A

SVOB Slot Boundary Violation Observed on Channel B (vSS!BViolationB)

A slot boundary violation (channel active at the start or at the end of the assigned slot) was observed on channel B.

1 = Slot boundary violation observed on channel B 0 = No slot boundary violation observed on channel B

TCIA Transmission Conﬂict Indication Channel A (vSS!TxConﬂictA)

A transmission conflict indication is set if a transmission conflict has occurred on channel A. 1 = Transmission conﬂict occurred on channel A 0 = No transmission conﬂict occurred on channel A

TCIB Transmission Conﬂict Indication Channel B (vSS!TxConﬂictB)

A transmission conflict indication is set if a transmission conflict has occurred on channel B. 1 = Transmission conﬂict occurred on channel B 0 = No transmission conﬂict occurred on channel B

ESA Empty Slot Channel A

In an empty slot there is no activity detected on the bus. The condition is checked in static and dynamic slots.

1 = No bus activity detected in the assigned slot on channel A 0 = Bus activity detected in the assigned slot on channel A

ESB Empty Slot Channel B

In an empty slot there is no activity detected on the bus. The condition is checked in static and dynamic slots.

1 = No bus activity detected in the assigned slot on channel B 0 = Bus activity detected in the assigned slot on channel B

MLST Message Lost

The flag is set in case the Host did not read the message before the message buffer was updated from a received data frame. Not affected by reception of null frames except for message buffers belonging to the receive FIFO. The flag is reset by a Host write to the message buffer via IBF or when a new message is stored into the message buffer after the message buffers ND flag was reset by reading out the message buffer via OBF.

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1 = Unprocessed message was overwritten 0 = No message lost

FTA Frame Transmitted on Channel A

Indicates that this node has transmitted a data frame in the configured slot on channel A. 1 = Data frame transmitted on channel A 0 = No data frame transmitted on channel A

FTB Frame Transmitted on Channel B

Indicates that this node has transmitted a data frame in the configured slot on channel B. 1 = Data frame transmitted on channel B 0 = No data frame transmitted on channel B

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Note: The FlexRay protocol specification requires that FTA, and FTBcan only be reset by the Host.

Therefore the Cycle Count Status CCS[5:0] for these bits is only valid for the cycle where the bits are set to ’1’.

CCS[5:0] Cycle Count Status

Actual cycle count when status was updated.

For receive buffers (CFG = ’0’) the following status bits are updated from both valid data and null frames. If no valid frame was received,the previous value is maintained. For transmit buffersthe flags have no meaning and should be ignored.

RCIS Received on Channel Indicator Status (vSS!Channel)

Indicates the channel on which the frame was received. 1 = Frame received on channel A 0 = Frame received on channel B

SFIS Startup Frame Indicator Status (vRF!Header!SuFIndicator)

A startup frame is marked by the startup frame indicator. 1 = The received frame is a startup frame 0 = No startup frame received

SYNS Sync Frame Indicator Status (vRF!Header!SyFIndicator)

A sync frame is marked by the sync frame indicator. 1 = The received frame is a sync frame 0 = No sync frame received

NFIS Null Frame Indicator Status (vRF!Header!NFIndicator)

If set to ’0’ the payload segment of the received frame contains no usable data. 1 = Received frame is not a null frame 0 = Received frame is a null frame

PPIS Payload Preamble Indicator Status (vRF!Header!PPIndicator)

The payload preamble indicator defines whether a network management vector or message ID is contained within the payload segment of the received frame.

1 = Static segment: Network management vector at the beginning of the payload

Dynamic segment: Message ID at the beginning of the payload

0 = The payload segment of the received frame does not contain a network management vector

or a message ID

RESS Reserved Bit Status (vRF!Header!Reserved)

Reflects the state of the received reserved bit. The reserved bit is transmitted as ’0’.

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4.11.6 Output Buffer Command Mask (OBCM)

Configures how the Output Buffer is updated from the message buffer in the Message RAM selected by register OBCR. When OBF Hostand OBFShadow are swapped, also mask bits RDSHand RHSH are swapped with bits RDSS and RHSS to keep them attached to the respective Output Buffer transfer.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OBCM

R00000000000000RDSH RHSH

0x0710 W

Reset 0 000000000000000

Bit 1514131211109876543210

R00000000000000

Reset 0 000000000000000

RDSS RHSS

RHSS Read Header Section Shadow

1 = Header section selected for transfer from Message RAM to Output Buffer 0 = Header section is not read

RDSS Read Data Section Shadow

1 = Data section selected for transfer from Message RAM to Output Buffer 0 = Data section is not read

RHSH Read Header Section Host

1 = Header section selected for transfer from Message RAM to Output Buffer 0 = Header section is not read

RDSH Read Data Section Host

1 = Data section selected for transfer from Message RAM to Output Buffer 0 = Data section is not read

Note: After the transfer of the header section from the Message RAM to OBF Shadow has complet-

ed, the message buffer status changed flag MBC of the selected message buffer in the MBSC1/2/3/4 registers is cleared. After the transfer of the data section from the Message RAM to OBF Shadow has completed, the new data flag ND of the selected message buffer in the NDAT1/2/3/4 registers is cleared.

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4.11.7 Output Buffer Command Request (OBCR)

The message buffer selected by OBRS[6:0] istransferred from the Message RAM to the OutputBuffer as soon as the Host has set REQ to ’1’. Bit REQ can only be set to ’1’ while OBSYS is ’0’ (see also Section 5.11.2.2 Data Transfer from Message RAM to Output Buffer).

After setting REQ to ’1’, OBSYS is automatically set to ’1’, and the transfer of the message buffer selected by OBRS[6:0] from the Message RAM to OBF Shadow is started. When the transfer between the Message RAM and OBF Shadow has completed, this is signalled by setting OBSYS back to ’0’. By setting the VIEW bit to ’1’ while OBSYS is ’0’, OBF Host and OBF Shadow are swapped. Now the Host can read the transferred message buffer from OBF Host. In parallel the Message Handler may transfer the next message from the Message RAM to OBF Shadow if VIEW and REQ are set at the same time.

Any write access to an OutputBuffer registerwhile OBSYS is set will cause theerror flagEIR.IOBA to be set. In this case the Output Buffer will not be changed.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OBCR

R000000000OBRH6

0x0714 W

Reset 0 000000000000000

OBRH5 OBRH4 OBRH3 OBRH2 OBRH1 OBRH0

Bit 1514131211109876543210

OBSYS

Reset 0 000000000000000

00000

REQ VIEW

OBRS6 OBRS5 OBRS4 OBRS3 OBRS2 OBRS1 OBRS0

OBRS[6:0] Output Buffer Request Shadow

Number of source message buffer to be transferred from the Message RAM to OBF Shadow. Valid values are 0x00 to 0x7F (0…127). If the number of the ﬁrst message buffer of the receive FIFO is written to this register the Message Handler transfers the message buffer addressed by the GET Index (GIDX, see Section 5.10 FIFO Function) to OBF Shadow.

VIEW View Shadow Buffer

Toggles between OBF Shadow and OBF Host. Only writeable while OBSYS = ’0’. 1 = Swap OBF Shadow and OBF Host 0 = No action

REQ Request Message RAM Transfer

Requests transfer of message buffer addressed by OBRS[6:0] from Message RAM to OBF Shadow. Only writeable while OBSYS = ’0’.

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1 = Transfer to OBF Shadow requested 0 = No request

OBSYS Output Buffer Busy Shadow

Set to ’1’ after setting bit REQ. When the transfer between the Message RAM and OBF Shadow has completed, OBSYS is set back to ’0’.

1 = Transfer between Message RAM and OBF Shadow in progress 0 = No transfer in progress

OBRH[6:0] Output Buffer Request Host

Number of message buffer currently accessible by the Host via RDHS[1…3], MBS, and RDDS[1…64]. By writing VIEW to ’1’ OBF Shadow and OBF Host are swapped and the transferred message buffer is accessible by the Host. Valid values are 0x00 to 0x7F (0…127).

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5. Functional Description

This chapter describes the E-Ray implementation togetherwith the related FlexRay protocol features. More information about the FlexRay protocol itself can be found in the FlexRay protocol specification v2.1.

Communication on FlexRay networks is based on frames and symbols. The wakeup symbol (WUS) and the collision avoidance symbol (CAS) are transmitted outside the communication cycle to setup the time schedule. Frames and media access test symbols (MTS) are transmitted inside the communication cycle.

5.1 Communication Cycle

A FlexRay communication cycle consists of the following elements:

• Static Segment

• Dynamic Segment (optional)

• Symbol Window (optional)

• Network Idle Time (NIT) Static segment, dynamic segment, and symbol window form the Network Communication Time

(NCT). For each communication channel the slot counter starts at 1 and counts up until the end of the dynamic segment is reached. Both channels share the same arbitration grid which means that they use the same synchronized macrotick.

time base derived trigger

static segment dynamic segment

communication cycle x-1

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Figure 2: Structure of communication cycle

symbol window

communication cycle x

time base derived trigger

NIT

communication cycle x+1

5.1.1 Static Segment

The Static Segment is characterized by the following features:

• Time slots of fixed length (optionally protected by bus guardian)

• Start of frame transmission at action point of the respective static slot

• Payload length same for all frames on both channels Parameters: Number of Static Slots GTUC7.NSS[9:0], Static Slot Length GTUC7.SSL[9:0],

Payload Length Static MHDC.SFDL[6:0], Action Point Offset GTUC9.APO[5:0]

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5.1.2 Dynamic Segment

The Dynamic Segment is characterized by the following features:

• All controllers have bus access (no bus guardian protection possible)

• Variable payload length and duration of slots, different for both channels

• Start of transmission at minislot action point Parameters: Number of Minislots GTUC8.NMS[12:0], Minislot Length GTUC8.MSL[5:0],

Minislot Action Point Offset GTUC9.MAPO[4:0], Start of Latest Transmit (last minislot) MHDC.SLT[12:0]

5.1.3 Symbol Window

During the symbol window only one media access test symbol (MTS) may be transmitted per channel. MTS symbols are send in NORMAL_ACTIVE state to test the bus guardian.

The symbol window is characterized by the following features:

• Send single symbol

• Transmission of the MTS symbol starts at the symbol windows action point Parameters: Symbol Window Action Point Offset GTUC9.APO[4:0] (same as for static slots),

Network Idle Time Start GTUC4.NIT[13:0]

5.1.4 Network Idle Time (NIT)

During network idle time the CC has to perform the following tasks:

• Calculate clock correction terms (offset and rate)

• Distribute offset correction over multiple macroticks after offset correction start

• Perform cluster cycle related tasks Parameters: Network Idle Time Start GTUC4.NIT[13:0],

Offset Correction Start GTUC4.OCS[13:0]

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5.1.5 Conﬁguration of NIT Start and Offset Correction Start

Revision 1.2.5 E-Ray

GTUC2.MPC = m GTUC4.NIT = k GTUC4.OCS = NIT + 1

Figure 3: Conﬁguration of NIT start and offset correction start

k+1 m-1 0 k n n+1

NITSymbol WindowStatic / Dynamic Segment

The number of macroticks per cycle gMacroPerCycle is assumed to be m. It is configured by programming GTUC2.MPC = m.

The static / dynamic segment starts with macrotick 0 and ends with macrotick n: n = static segment length + dynamic segment offset + dynamic segment length - 1MT n = gNumberOfStaticSlots • gdStaticSlot + dynamic segment offset

+ gNumberOfMinislots • gdMinislot - 1 MT

The static segment length is configured by GTUC7.SSL and GTUC7.NSS. The dynamic segment length is configured by GTUC8.MSL and GTUC8.NMS.

The dynamic segment offset is: If gdActionPointOffset ≤ gdMinislotActionPointOffset:

dynamic segment offset = 0 MT

Else if gdActionPointOffset > gdMinislotActionPointOffset:

dynamic segment offset = gdActionPointOffset - gdMinislotActionPointOffset

The NIT starts with macrotick k+1 and ends with the last macrotick of cycle m-1. It has to be configured by setting GTUC4.NIT = k.

For the E-Ray the offset correction start is required to be GTUC4.OCS ≥ GTUC4.NIT + 1 = k+1. The length of symbol window results from the number of macroticks between the end of the static /

dynamic segment and the beginning of the NIT. It can be calculated by k - n.

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Contents

1. About this Document

1.1 Change Control

1.1.1 Current Status

1.1.2 Change History

1.2 Conventions

1.4 Scope

1.5 References

1.6 Terms and Abbreviations

2. Overview

2.1 Block Diagram

3. Generic Interface

4. Programmer’s Model

4.1 Register Map

4.2 Customer Registers

4.3 Special Registers

4.3.1 Lock Register (LCK)

4.4 Interrupt Registers

4.4.1 Error Interrupt Register (EIR)

4.4.2 Status Interrupt Register (SIR)

4.4.3 Error Interrupt Line Select (EILS)

4.4.4 Status Interrupt Line Select (SILS)

4.4.5 Error Interrupt Enable Set / Reset (EIES, EIER)

4.4.6 Status Interrupt Enable Set / Reset (SIES, SIER)

4.4.7 Interrupt Line Enable (ILE)

4.4.10 Stop Watch Register 1 (STPW1)

4.4.11 Stop Watch Register 2 (STPW2)

4.5 CC Control Registers

4.6 CC Status Registers

4.6.1 CC Status Vector (CCSV)

4.6.2 CC Error Vector (CCEV)

4.6.3 Slot Counter Value (SCV)

4.6.4 Macrotick and Cycle Counter Value (MTCCV)

4.6.5 Rate Correction Value (RCV)

4.6.6 Offset Correction Value (OCV)

4.6.7 Sync Frame Status (SFS)

4.6.8 Symbol Window and NIT Status (SWNIT)

4.6.9 Aggregated Channel Status (ACS)

4.7 Message Buffer Control Registers

4.7.2 FIFO Rejection Filter (FRF)

4.7.3 FIFO Rejection Filter Mask (FRFM)

4.7.4 FIFO Critical Level (FCL)

4.8 Message Buffer Status Registers

4.8.1 Message Handler Status (MHDS)

4.8.2 Last Dynamic Transmit Slot (LDTS)

4.8.3 FIFO Status Register (FSR)

4.8.4 Message Handler Constraints Flags (MHDF)

4.8.5 Transmission Request 1/2/3/4 (TXRQ1/2/3/4)

4.8.6 New Data 1/2/3/4 (NDAT1/2/3/4)

4.8.7 Message Buffer Status Changed 1/2/3/4 (MBSC1/2/3/4)

4.9.1 Core Release Register (CREL)

4.9.2 Endian Register (ENDN)

4.10 Input Buffer

4.10.2 Write Header Section 1 (WRHS1)

4.10.3 Write Header Section 2 (WRHS2)

4.10.4 Write Header Section 3 (WRHS3)

4.10.5 Input Buffer Command Mask (IBCM)

4.10.6 Input Buffer Command Request (IBCR)

4.11 Output Buffer

4.11.2 Read Header Section 1 (RDHS1)

4.11.3 Read Header Section 2 (RDHS2)

4.11.4 Read Header Section 3 (RDHS3)

4.11.5 Message Buffer Status (MBS)

4.11.6 Output Buffer Command Mask (OBCM)

4.11.7 Output Buffer Command Request (OBCR)

5. Functional Description

5.1 Communication Cycle

5.1.1 Static Segment

5.1.2 Dynamic Segment

5.1.3 Symbol Window

5.1.4 Network Idle Time (NIT)