ROBERT BOSCH GMBH, MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
ROBERT BOSCH GMBH, RESERVES THE RIGHT TO MAKE CHANGES WITHOUT
FURTHER NOTICE TO THE PRODUCTS DESCRIBED HEREIN. ROBERT BOSCH GMBH
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF
ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN.
Bus guardian related pins eray_arm, eray_bgt,
eray_mt, eray_bge1, and eray_bge2 have no function
PRTC1: Configuration parameter CASM[6:0] added
WRHS1: Bit NME changed to PPIT
RDHS1: Bit NME changed to PPIT
Pin eray_scanmode for scan mode control added
TABB added
SIR: Flag SDS added
EILS: Control bits CCLL, EFAL, IIBAL, IOBAL,
TABAL, TABBL added
SILS: Control bit SDSL added
-8/165-
15.12.2006
Page 9
User’s Manual
Revision 1.2.5 E-Ray
EIES: Control bits CCLE, EFAE, IIBAE, IOBAE,
TABAE, TABBE added
EIER: Control bits CCLE, EFAE, IIBAE, IOBAE,
TABAE, TABBE added
SIES: Control bit SDSE added
SIER: Control bit SDSE added
SUCC2: LT[20:0] range modified
PRTC1: TSST[3:0] range modified, SPP[1:0] added,
configuration of BRP[1:0] for 1.25 MBit/s removed
PRTC2: RXL[5:0] range modified
MHDC: SLT[12:0] range modified
GTUC1: UT[19:0] range modified
GTUC2: MPC[13:0] range modified
GTUC3: Configuration parameterMTIO[5:0] replaced
by MIOA[6:0] and MIOB[6:0]
GTUC4: NIT[13:0] and OCS[13:0] range modified
GTUC5: DEC[7:0] range modified
GTUC7: SSL[9:0] range modified
GTUC8: NMS[12:0] range modified
GTUC9: APO[5:0] and DSI[1:0] range modified
GTUC10: MOC[13:0] range modified
GTUC11: Configuration parameter ECC[1:0] replaced
by EOCC[1:0] and ERCC[1:0]
OCV: OCV[18:0] range modified
SCV: SCCA[10:0], SCCB[10:0] range modified
ACS: Flags can only be reset
MRC: Configuration bits SEC[1:0] added
Register LDTS added
Bus guardian related pins eray_arm, eray_bgt,
eray_mt, eray_bge1, and eray_bge2 removed from
physical layer interface
Chapter 6. Restrictions removed. Description of timing
requirements for data transfers between Message RAM
and IBF / OBF moved to "Addendum to E-Ray
FlexRay IP-Module Specification Revision 1.1"
Revision 1.209.12.05C. HorstSection 3.2 renamed from "Interrupt Flag Interface" to
"Internal Signal and Flag Interface"
manual_about.fm
With this revision it is possible to use message buffer 1
for sync frame transmission in addition to message
buffer 0 if sync frames should have different payloads
on channel A and B
EIR: Handling of bits PERR and RFO same as for
other bits, bit MHF added
SIR: Bit RFF renamed to RFCL, handling of bits
RFNE, RFCL same as for other bits
EILS: Bit MHFL added
SILS: Bit RFFL renamed to RFCLL
EIES, EIER: Bit MHFE added
SIES, SIER: Bit RFFE renamed to RFCLE
-9/165-
15.12.2006
Page 10
User’s Manual
Revision 1.2.5 E-Ray
Register STPW renamed to STPW1
STPW2: Register added
CCSV: Bits PSL[5:0] added
SWNIT: Bits MTSA, MTSB added
MRC: Bit SPLM added
FCL: Register added
FSR: Register added
MHDF: Register added
MBSC1/2/3/4: Naming of bits changed from MBS to
MBC to distinguish between message buffer status flag
(MBC) and message buffer status register (MBS)
CREL: Register added
ENDN: Register added
Message buffers in Message RAM:
Header 2 and 3updated from received dataframes only
MBS: Bits FTA, FTB, CCS[5:0], RCIS, SFIS, SYNS,
NFIS, PPIS, RESS added
Revision 1.2.117.03.06C. HorstAll changes to previous release are described in
detail in [5].
Revision 1.2.219.05.06C. HorstAll changes to previous release are described in
detail in [6].
Revision 1.2.315.08.06C. HorstAll changes to previous release are described in
detail in [7].
Revision 1.2.4Not published.
Revision 1.2.515.12.06C. HorstAll changes to previous release are described in
detail in [8], [9].
manual_about.fm
-10/165-
15.12.2006
Page 11
User’s Manual
Revision 1.2.5 E-Ray
1.2 Conventions
The following conventions are used within this document:
Times boldNames of bits and signals
CAPITALSPOC states and CHI commands
1.3 Definitions
FlexRay Frame:Header Segment + Payload Segment
Message Buffer:Header Section + Data Section
Message RAM:Header Partition + Data Partition
Data Frame:FlexRay frame that is not a null frame
1.4 Scope
This document describes the E-Ray FlexRay IP-module and its features from the application programmer’s point of view. All information necessary to integrate the E-Ray module into an user-defined
ASIC is located in the Module Integration Guide. Information about a specific Customer CPU Interface can be found in the respective Customer CPU Interface Specification document.
1.5 References
This document refers to the following E-Ray release:
Revision 1.0.1
This document refers to the following documents:
RefAuthor(s)Title
[1]FlexRay GroupFlexRay Communication System Protocol Specification v2.1 (05/05/12)
[2]FlexRay GroupFlexRay Communication System Protocol Specification v2.1 Revision A
Errata Sheet Version 1 (06/03/29)
[3]FlexRay GroupFlexRay Data Link Layer Conformance Test Specification v2.1 (06/03/27)
[4]AE/EIPAddendum to E-Ray FlexRay IP-Module Specification Revision 1.2.2
[5]AE/EIPChanges E-Ray FlexRay IP-Module Specification v1.2 to v1.2.1
[6]AE/EIPChanges E-Ray FlexRay IP-Module Specification v1.2.1 to v1.2.2
manual_about.fm
[7]AE/EIPChanges E-Ray FlexRay IP-Module Specification v1.2.2 to v1.2.3
[8]AE/EIPChanges E-Ray FlexRay IP-Module Specification v1.2.3 to v1.2.4
[9]AE/EIPChanges E-Ray FlexRay IP-Module Specification v1.2.4 to v1.2.5
-11/165-
15.12.2006
Page 12
User’s Manual
1.6 Terms and Abbreviations
This document uses the following terms and abbreviations:
TermMeaning
APAction Point
BDBus Driver
BSSByte Start Sequence
CASCollision Avoidance Symbol
CCCommunication Controller
CHIController Host Interface
CIFCustomer Interface Block
CRCCyclic Redundancy Check
FESFrame End Sequence
FSSFrame Start Sequence
Revision 1.2.5 E-Ray
FIFOFirst In First Out (message buffer structure)
FSMFinite State Machine
FSPFrame and Symbol Processing Block
FTMFault Tolerant Midpoint
GIFGeneric Interface Block
GTUGlobal Time Unit Block
IBFInput Buffer
INTInterrupt Control Block
MHDMessage Handler Block
MTMacrotick
MTSMedia Access Test Symbol
NCTNetwork Communication Time
NEMNetwork Management Block
NITNetwork Idle Time
manual_about.fm
NMNetwork Management
OBFOutput Buffer
POCProtocol Operation Control
PRTProtocol Controller Block
SDLSpecification and Description Language
SUCSystem Universal Control Block
TBFTransient Buffer
TDMATime Division Multiple Access (media access method)
The E-Ray module is a FlexRay IP-module that can be integrated as stand-alone device or as part of
an ASIC. It is described in VHDL on RTL level, prepared for synthesis. The E-Ray IP-module performs communication according to the FlexRay protocolspecification v2.1. With maximum specified
sample clock the bitrate is 10 MBit/s. Additional bus driver (BD) hardware is required for connection
to the physical layer.
For communication on a FlexRay network, individual message buffers with up to 254 data bytes are
configurable. The message storage consists of a single-ported Message RAM that holds up to 128
message buffers. All functions concerning the handling of messages are implemented in the Message
Handler. Those functions are the acceptance filtering, the transfer of messages between the two
FlexRay Channel Protocol Controllers and the Message RAM, maintaining the transmissionschedule
as well as providing message status information.
The register set of the E-Ray IP-module can be accessed directlyby an external Host via the module’s
Host interface. These registers are used to control/configure/monitor the FlexRay Channel Protocol
Controllers, Message Handler, Global Time Unit, System Universal Control, Frame and Symbol
Processing, Network Management, Interrupt Control, and to access the Message RAM via Input /
Output Buffer.
The E-Ray IP-module can be connected to a wide range of customer-specific Host CPUs via its
8/16/32-bit Generic CPU Interface.
The E-Ray IP-module supports the following features:
• Conformance with FlexRay protocol specification v2.1
• Data rates of up to 10 Mbit/s on each channel
• Up to 128 message buffers configurable
• 8 Kbyte of Message RAM for storage of e.g. 128 message buffers with max. 48 byte data section
or up to 30 message buffers with 254 byte data section
• Configuration of message buffers with different payload lengths possible
• One configurable receive FIFO
• Each message buffer can be configured as receive buffer, as transmit buffer
or as part of the receive FIFO
• Host access to message buffers via Input and Output Buffer
Input Buffer:Holds message to be transferred to the Message RAM
manual_overview.fm
Output Buffer:Holds message read from the Message RAM
• Filtering for slot counter, cycle counter, and channel
• Maskable module interrupts
• Network Management supported
• 8/16/32-bit Generic CPU Interface, connectable to a wide range of customer-specific Host CPUs
-14/165-
15.12.2006
Page 15
2.1 Block Diagram
User’s Manual
Revision 1.2.5 E-Ray
Rx_A
Physical
Layer
Host
CPU
Figure 1: E-Ray block diagram
Tx_A
Control
Rx_B
Tx_B
Data
Addr
Control
Interrupt
PRT B
IBF
OBF
Generic CPU IF
Customer CPU IF
PRT A
TBF B
Message Handler
Message RAM
TBF A
GTU
SUC
FSP
NEM
INT
Customer CPU Interface (CIF)
Connects a customer specific Host CPU to the E-Ray IP-module via the Generic CPU Interface.
Generic CPU Interface (GIF)
The E-Ray IP-module is provided with an 8/16/32-bit Generic CPU Interface prepared for the connection to a wide range of customer-specific Host CPUs. Configuration registers, status registers, and
interrupt registers are attached to the respective blocks and can be accesssed via the Generic CPU Interface.
Input Buffer (IBF)
For write access to the message buffers configured in the Message RAM, the Host can write the header and data section for a specific message buffer to the Input Buffer. The Message Handler then transfers the data from the Input Buffer to the selected message buffer in the Message RAM.
manual_overview.fm
Output Buffer (OBF)
For read access to a message buffer configured in the Message RAM the Message Handler transfers
the selected message buffer to the Output Buffer. After the transfer has completed, the Host can read
the header and data section of the transferred message buffer from the Output Buffer.
Message Handler (MHD)
The E-Ray Message Handler controls data transfers between the following components:
• Input / Output Buffer and Message RAM
• Transient Buffer RAMs of the two FlexRay Protocol Controllers and Message RAM
-15/165-
15.12.2006
Page 16
User’s Manual
Revision 1.2.5 E-Ray
Message RAM (MRAM)
The Message RAM consists of a single-ported RAM that stores up to 128 FlexRay message buffers
together with the related configuration data (header and data partition).
Transient Buffer RAM (TBF A/B)
Stores the data section of two complete messages.
FlexRay Channel Protocol Controller (PRT A/B)
The FlexRay Channel Protocol Controllers consist of shift register and FlexRay protocol FSM. They
are connected to the Transient Buffer RAMs for intermediatemessage storage and to thephysical layer via bus driver BD.
They perform the following functionality:
• Control and check of bit timing
• Reception / transmission of FlexRay frames and symbols
• Check of header CRC
• Generation / check of frame CRC
• Interfacing to bus driver
The FlexRay Channel Protocol Controllers have interfaces to:
• Physical Layer (bus driver)
• Transient Buffer RAM
• Message Handler
• Global Time Unit
• System Universal Control
• Frame and Symbol Processing
• Network Management
• Interrupt Control
Global Time Unit (GTU)
The Global Time Unit performs the following functions:
• Generation of microtick
• Generation of macrotick
• Fault tolerant clock synchronization by FTM algorithm
manual_overview.fm
- rate correction
- offset correction
• Cycle counter
• Timing control of static segment
• Timing control of dynamic segment (minislotting)
• Support of external clock correction
-16/165-
15.12.2006
Page 17
User’s Manual
System Universal Control (SUC)
The System Universal Control controls the following functions:
• Configuration
• Wakeup
• Startup
• Normal Operation
• Passive Operation
• Monitor Mode
Frame and Symbol Processing (FSP)
The Frame and Symbol Processing controls the following functions:
• Checks the correct timing of frames and symbols
• Tests the syntactical and semantical correctness of received frames
• Sets the slot status flags
Network Management (NEM)
Revision 1.2.5 E-Ray
Handles the network management vector.
Interrupt Control (INT)
The Interrupt Controller performs the following functions:
• Provides error and status interrupt flags
• Enable / disable interrupt sources
• Assignment of interrupt sources to one of the two module interrupt lines
• Enable / disable module interrupt lines
• Manages the two interrupt timers
• Stop watch time capturing
manual_overview.fm
-17/165-
15.12.2006
Page 18
User’s Manual
Revision 1.2.5 E-Ray
3. Generic Interface
The Generic Interface encapsulates the synthesizable code of the E-Ray design (E-Ray core).All customer specific components like Customer CPU Interfaces and RAM blocks are connected to the Generic Interface.
The Generic CPU Interface connects the E-Ray module to a customer specific Host CPU via the Customer CPU Interface. It supports 8/16/32-bit access modes.
manual_generic_if.fm
-18/165-
15.12.2006
Page 19
User’s Manual
Revision 1.2.5 E-Ray
4. Programmer’s Model
4.1 Register Map
The E-Ray module allocates an address space of 2 Kbytes (0x0000 to 0x07FF). The registers are organized as 32-bit registers. 8/16-bit accesses are also supported. Host access to the Message RAM is
done via the Input and Output Buffers. They buffer data to be transferred to and from the Message
RAM under control of the Message Handler, avoiding conflicts between Host accesses and message
reception / transmission. Addresses 0x0000 to 0x000F are reserved for customer specific purposes.
All functions related to these addresses are located in the Customer CPU Interface.
The assignment of the message buffers is done according to the scheme shown in Table 1 below. The
number N of available message buffers depends on the payload length of the configured message
buffers. The maximum number of message buffers is 128. The maximum payload length supported is
254 bytes.
The message buffers are separated into three consecutive groups:
• Static + Dynamic Buffers - Transmit / receive buffers assigned to static or dynamic segment
• FIFO- Receive FIFO
The message buffer separation configuration can be changed only in DEFAULT_CONFIG or CON-
FIG state only by programming register MRC (see 4.7.1 Message RAM Configuration (MRC)).
The first group starts with message buffer0 andconsists of static message buffers only. Message buff-
er 0 is dedicated to hold the startup / sync frame or the single slot frame, if the node transmits one, as
configured by SUCC1.TXST, SUCC1.TXSY, and SUCC1.TSM. In addition, message buffer 1 may
be used for sync frame transmission in case that sync frames or single-slot frames should have different payloads on the two channels. In this case bit MRC.SPLM has to be programmed to ’1’ and message buffers 0 and 1 have to be configured with the key slot ID and can be (re)configured in
DEFAULT_CONFIG or CONFIG state only.
The second group consists of message buffers assigned to the static or to the dynamic segment. Message buffers belonging to this group may be reconfigured during run time from dynamic to static or
vice versa depending on the state of MRC.SEC[1:0].
The message buffers belonging to the third group are concatenated to a single receive FIFO.
The address space from 0x0000to 0x000F is reserved for customer-specificregisters. These registers,
if implemented, are located in the Customer CPU Interface block. A description can be found in the
specific Customer CPU Interface specification document.
manual_programmers_model.fm
-23/165-
15.12.2006
Page 24
User’s Manual
Revision 1.2.5 E-Ray
4.3 Special Registers
4.3.1 Lock Register (LCK)
The Lock Register is write-only. Reading the register will return 0x0000 0000.
Bit31302928272625242322212019181716
LCKR0000000000000000
0x001C W
Reset0000000000000000
Bit 1514131211109876543210
R0000000000000000
WCLK7 CLK6 CLK5 CLK4 CLK3 CLK2 CLK1 CLK0
Reset0000000000000000
CLK[7:0]Configuration Lock Key
ToleaveCONFIGstatebywritingSUCC1.CMD[3:0](commandsREADY,
MONITOR_MODE, ATM, LOOP_BACK), the write operation has to be directly preceded by
two write accesses to the Configuration Lock Key (unlock sequence). If the write sequence
below is interrupted by other write accesses between the second write to the Configuration Lock
Key and the write access to the SUCC1 register, the CC remains in CONFIG state and the
sequence has to be repeated.
First write:LCK.CLK[7:0]= "1100 1110" (0xCE)
Second write: LCK.CLK[7:0]= "0011 0001" (0x31)
Third write:SUCC1.CMD[3:0]
Note: In case that the Host uses 8/16-bit accesses to write CLK[7:0], the programmer has to ensure
that no "dummy accesses" e.g. to the remaining register bytes / words are inserted by the compiler.
manual_programmers_model.fm
-24/165-
15.12.2006
Page 25
User’s Manual
Revision 1.2.5 E-Ray
4.4 Interrupt Registers
4.4.1 Error Interrupt Register (EIR)
The flags are set when the CC detects one of the listed error conditions. The flags remain set until the
Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’has
no effect on the flag. A hard reset will also clear the register.
Bit31302928272625242322212019181716
EIRR00000
0x0020 W
Reset0000000000000000
Bit 1514131211109876543210
R0000
W
Reset0000000000000000
TABB LTVB EDB
MHF IOBA IIBAEFARFOPERR CCLCCFSFO SFBM CNA PEMC
PEMCPOC Error Mode Changed
This flag is set whenever the error mode signalled by CCEV.ERRM[1:0] has changed.
1 = Error mode has changed
0 = Error mode has not changed
00000
TABA LTVA EDA
CNACommand Not Accepted
The flag signals that the write access to the CHI command vector SUCC1.CMD[3:0] was not
successful because the requested command was not valid in the actual POC state, or because the
CHI command was locked (CCL = ’1’).
1 = CHI command not accepted
0 = CHI command accepted
SFBMSync Frames Below Minimum
This flag signals that the number of sync frames received during the last communication cycle
was below the limit required by the FlexRay protocol. May be set during startup and therefore
should be cleared by the Host after the CC entered NORMAL_ACTIVE state.
1 = Less than the required minimum of sync frames received
0 = Sync node: 1 or more sync frames received, non-sync node: 2 or more sync frames received
SFOSync Frame Overflow
Set when either the number of sync frames received during the last communication cycle or the
total number of sync frames received during the last double cycle exceeds the maximum number
of sync frames as defined by GTUC2.SNM[3:0].
manual_programmers_model.fm
1 = More sync frames received than configured by GTUC2.SNM[3:0]
0 = Number of received sync frames ≤ GTUC2.SNM[3:0]
CCFClock Correction Failure
This flag is set at the end of the cycle whenever one of the following errors occurred:
• Missing offset and / or rate correction
• Clock correction limit reached
The clock correction status is monitored in registers CCEV and SFS. A failure may occur during
startup,thereforebitCCFshould be clearedbytheHostafter theCCentered
NORMAL_ACTIVE state.
The flag signals that the write access to the CHI command vector SUCC1.CMD[3:0] was not
successful because the execution of the previous CHI command has not yet completed. In this
case bit CNA is also set to ’1’.
1 = CHI command not accepted
0 = CHI command accepted
PERRParity Error
The flag signals a parity error to the Host. It is set whenever one of the flags MHDS.PIBF,
MHDS.POBF, MHDS.PMR, MHDS.PTBF1, MHDS.PTBF2 changes from ’0’ to ’1’.
The flag is set by the CC when a receive FIFO overrun is detected. When a receive FIFO overrun
occurs, the oldest message is overwritten with the actual received message. The actual state of
the FIFO is monitored in register FSR.
1 = A receive FIFO overrun has been detected
0 = No receive FIFO overrun detected
EFAEmpty FIFO Access
This flag is set by the CC when the Host requests the transfer of a message from the receive
FIFO via Output Buffer while the receive FIFO is empty.
1 = Host access to empty FIFO occurred
0 = No Host access to empty FIFO occurred
IIBAIllegal Input Buffer Access
This flag is set by the CC when the Host wants to modify a message buffer via Input Buffer
while the CC is not in CONFIG or DEFAULT_CONFIG state and one of the following conditions applies:
1) The Host writes to the Input Buffer Command Request register to modify the
• Header section of message buffer 0, 1 if configured for transmission in key slot
• Header section of static message buffers with buffer number < MRC.FDB[7:0]
while MRC.SEC[1:0] = "01"
• Header section of any static or dynamic message buffer while MRC.SEC[1:0] = "1x"
• Header and / or data section of any message buffer belonging to the receive FIFO
2) The Host writes to any register of the Input Buffer while IBCR.IBSYH is set to ’1’.
1 = Illegal Host access to Input Buffer occurred
0 = No illegal Host access to Input Buffer occurred
manual_programmers_model.fm
IOBAIllegal Output buffer Access
This flag is set by the CC when the Host requests the transfer of a message buffer from the Message RAM to the Output Buffer while OBCR.OBSYS is set to ’1’.
1 = Illegal Host access to Output Buffer occurred
0 = No illegal Host access to Output Buffer occurred
MHFMessage Handler Constraints Flag
The flag signals a Message Handler constraints violation condition. It is set whenever one of the
flagsMHDF.SNUA,MHDF.SNUB,MHDF.FNFA,MHDF.FNFB,MHDF.TBFA,MHDF.TBFB, MHDF.WAHP changes from ’0’ to ’1’.
Channel-specific error flags:
EDAError Detected on Channel A
This bit is set whenever one of the flags ACS.SEDA, ACS.CEDA, ACS.CIA, ACS.SBVA
changes from ’0’ to ’1’.
1 = Error detected on channel A
0 = No error detected on channel A
LTVALatest Transmit Violation Channel A
The flag signals a latest transmit violation on channel A to the Host.
1 = Latest transmit violation detected on channel A
0 = No latest transmit violation detected on channel A
TABATransmission Across Boundary Channel A
The flag signals to the Host that a transmission across a slot boundary occurred for channel A.
1 = Transmission across slot boundary detected on channel A
0 = No transmission across slot boundary detected on channel A
EDBError Detected on Channel B
This bit is set whenever one of the flags ACS.SEDB, ACS.CEDB, ACS.CIB, ACS.SBVB
changes from ’0’ to ’1’.
1 = Error detected on channel B
0 = No error detected on channel B
LTVBLatest Transmit Violation Channel B
The flag signals a latest transmit violation on channel B to the Host.
1 = Latest transmit violation detected on channel B
0 = No latest transmit violation detected on channel B
TABBTransmission Across Boundary Channel B
The flag signals to the Host that a transmission across a slot boundary occurred for channel B.
1 = Transmission across slot boundary detected on channel B
0 = No transmission across slot boundary detected on channel B
manual_programmers_model.fm
-27/165-
15.12.2006
Page 28
User’s Manual
Revision 1.2.5 E-Ray
4.4.2 Status Interrupt Register (SIR)
The flags are set when the CC detects one of the listed events. The flags remain set until the Host
clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no
effect on the flag. A hard reset will also clear the register.
Bit31302928272625242322212019181716
SIRR000000
0x0024 W
Reset0000000000000000
Bit 1514131211109876543210
R
SDSMBSI SUCS SWE TOBC TIBCTI1TI0NMVC RFCL RFNERXITXICYCS CASWST
W
Reset0000000000000000
MTSB WUPB
000000
MTSA WUPA
WSTWakeup Status
This flag is set when the wakeup status vector CCSV.WSV[2:0] is changed by a protocol event.
1 = Wakeup status changed
0 = Wakeup status unchanged
CASCollision Avoidance Symbol
This flag is set by the CC during STARTUP state when a CAS or a potential CAS was received.
1 = Bit pattern matching the CAS symbol received
0 = No bit pattern matching the CAS symbol received
CYCSCycle Start Interrupt
This flag is set by the CC when a communication cycle starts.
1 = Communication cycle started
0 = No communication cycle started
TXITransmit Interrupt
This flag is set by the CC at the end of frame transmission if bit MBI in the respective message
buffer is set to ’1’ (see Table 17).
1 = At least one frame was transmitted from a transmit buffer with MBI = ’1’
0 = No frame transmitted from a transmit buffer with MBI = ’1’
RXIReceive Interrupt
This flag is set by the CC whenever the set condition of a message buffers ND flag is fulfilled
(see 4.8.6 New Data 1/2/3/4 (NDAT1/2/3/4)), and if bit MBI of that message buffer is set to ’1’
(see Table 17).
manual_programmers_model.fm
1 = At least one ND flag of a receive buffer with MBI = ’1’ has been set to ’1’
0 = No ND flag of a receive buffer with MBI = ’1’ has been set to ’1’
RFNEReceive FIFO Not Empty
This flag is set by the CC when a received valid frame was stored into the empty receive FIFO.
The actual state of the receive FIFO is monitored in register FSR.
1 = Receive FIFO is not empty
0 = Receive FIFO is empty
RFCLReceive FIFO Critical Level
This flag is set when the receive FIFO fill level FSR.RFFL[7:0] is equal or greater than the critical level as configured by FCL.CL[7:0].
This interrupt flag signals a change in the Network Management Vector visible to the Host.
1 = Network management vector changed
0 = No change in the network management vector
TI0Timer Interrupt 0
This flag is set whenever timer 0 matches the conditions configured in register T0C. A Timer
Interrupt 0 is also signalled on pin eray_tint0.
This flag is set whenever a transfer from Input Buffer to the Message RAM has completed and
IBCR.IBSYS has been reset by the Message Handler.
1 = Transfer between Input Buffer and Message RAM completed
0 = No transfer completed
TOBCTransfer Output Buffer Completed
This flag is set whenever a transfer from the Message RAM to the Output Buffer has completed
and OBCR.OBSYS has been reset by the Message Handler.
1 = Transfer between Message RAM and Output Buffer completed
0 = No transfer completed
SWEStop Watch Event
This flag is set after a stop watch activation when the actual cycle counter and macrotick value
are stored in the Stop Watch register (see section 4.4.10 Stop Watch Register 1 (STPW1)).
This flag is set by the CC when the message buffer status MBS has changed if bit MBI of that
message buffer is set (see Table 17).
1 = Message buffer status of at least one message buffer with MBI = ’1’ has changed
0 = No message buffer status change of message buffer with MBI = ’1’
SDSStart of Dynamic Segment
This flag is set by the CC when the dynamic segment starts.
1 = Dynamic segment started
0 = Dynamic segment not yet started
-29/165-
15.12.2006
Page 30
User’s Manual
Revision 1.2.5 E-Ray
Channel-specific status flags:
WUPAWakeup Pattern Channel A
This flag is set by the CC when a wakeup pattern was received on channel A. Only set when the
CC is in WAKEUP, READY, or STARTUP state, or when in Monitor mode.
1 = Wakeup pattern received on channel A
0 = No wakeup pattern received on channel A
MTSAMTS Received on Channel A (vSS!ValidMTSA)
Media Access Test symbol received on channel A during the preceding symbol window.
Updated by the CC for each channel at the end of the symbol window.
1 = MTS symbol received on channel A
0 = No MTS symbol received on channel A
WUPBWakeup Pattern Channel B
This flag is set by the CC when a wakeup pattern was received on channel B. Only set when the
CC is in WAKEUP, READY, or STARTUP state, or when in Monitor mode.
1 = Wakeup pattern received on channel B
0 = No wakeup pattern received on channel B
MTSBMTS Received on Channel B (vSS!ValidMTSB)
Media Access Test symbol received on channel B during the preceding symbol window.
Updated by the CC for each channel at the end of the symbol window.
1 = MTS symbol received on channel B
0 = No MTS symbol received on channel B
manual_programmers_model.fm
-30/165-
15.12.2006
Page 31
User’s Manual
Revision 1.2.5 E-Ray
4.4.3 Error Interrupt Line Select (EILS)
Bit31302928272625242322212019181716
EILS R00000
0x0028 W
Reset0000000000000000
Bit 1514131211109876543210
R0000
W
Reset0000000000000000
TABBL LTVBL EDBL
MHFL IOBAL IIBAL EFAL RFOL PERRL CCLL CCFL SFOL
00000
TABAL
SFBML
LTVAL EDAL
PEMCL
CNAL
The Error Interrupt Line Select register assigns an interruptgenerated by a specific errorinterrupt flag
from register EIR to one of the two module interrupt lines:
1 = Interrupt assigned to interrupt line eray_int1
0 = Interrupt assigned to interrupt line eray_int0
PEMCLPOC Error Mode Changed Interrupt Line
CNALCommand Not Accepted Interrupt Line
SFBMLSync Frames Below Minimum Interrupt Line
SFOLSync Frame Overflow Interrupt Line
CCFLClock Correction Failure Interrupt Line
CCLLCHI Command Locked Interrupt Line
PERRLParity Error Interrupt Line
RFOLReceive FIFO Overrun Interrupt Line
EFALEmpty FIFO Access Interrupt Line
IIBALIllegal Input Buffer Access Interrupt Line
IOBALIllegal Output Buffer Access Interrupt Line
MHFLMessage Handler Constraints Flag Interrupt Line
EDALError Detected on Channel A Interrupt Line
LTVALLatest Transmit Violation Channel A Interrupt Line
TABALTransmission Across Boundary Channel A Interrupt Line
EDBLError Detected on Channel B Interrupt Line
manual_programmers_model.fm
LTVBLLatest Transmit Violation Channel B Interrupt Line
TABBLTransmission Across Boundary Channel B Interrupt Line
-31/165-
15.12.2006
Page 32
User’s Manual
Revision 1.2.5 E-Ray
4.4.4 Status Interrupt Line Select (SILS)
Bit31302928272625242322212019181716
SILSR000000
0x002C W
Reset0000001100000011
Bit 1514131211109876543210
R
SDSL MBSIL SUCSL SWEL
W
Reset1111111111111111
TOBCL
MTSBL WUPBL
TIBCL TI1LTI0L
000000
NMVCL
RFCLL RFNEL RXIL TXIL
CYCSL
MTSAL WUPAL
CASL WSTL
The Status Interrupt Line Select register assign an interrupt generated by a specific status interrupt
flag from register SIR to one of the two module interrupt lines:
1 = Interrupt assigned to interrupt line eray_int1
0 = Interrupt assigned to interrupt line eray_int0
WSTLWakeup Status Interrupt Line
CASLCollision Avoidance Symbol Interrupt Line
CYCSLCycle Start Interrupt Line
TXILTransmit Interrupt Line
RXILReceive Interrupt Line
RFNELReceive FIFO Not Empty Interrupt Line
RFCLLReceive FIFO Critical Level Interrupt Line
NMVCLNetwork Management Vector Changed Interrupt Line
TI0LTimer Interrupt 0 Line
TI1LTimer Interrupt 1 Line
TIBCLTransfer Input Buffer Completed Interrupt Line
TOBCLTransfer Output Buffer Completed Interrupt Line
SWELStop Watch Event Interrupt Line
SUCSLStartup Completed Successfully Interrupt Line
MBSILMessage Buffer Status Interrupt Line
SDSLStart of Dynamic Segment Interrupt Line
manual_programmers_model.fm
WUPALWakeup Pattern Channel A Interrupt Line
MTSALMedia Access Test Symbol Channel A Interrupt Line
WUPBLWakeup Pattern Channel B Interrupt Line
MTSBLMedia Access Test Symbol Channel B Interrupt Line
-32/165-
15.12.2006
Page 33
User’s Manual
Revision 1.2.5 E-Ray
4.4.5 Error Interrupt Enable Set / Reset (EIES, EIER)
The settings in the Error Interrupt Enable register determine which status changes in the Error Interrupt Register will result in an interrupt.
Bit31302928272625242322212019181716
EIES,R R00000
S:0x0030
R:0x0034
W
Reset0000000000000000
Bit 1514131211109876543210
R0000
W
Reset0000000000000000
TABBE LTVBE EDBE
MHFE IOBAE IIBAE EFAE RFOE PERRE CCLE CCFE SFOE
00000
TABAE
SFBME
LTVAE EDAE
PEMCE
CNAE
The enable bits are set by writing to address 0x0030 and reset by writing to address 0x0034. Writing
a ’1’ sets / resets the specific enable bit, writing a ’0’ has no effect. Reading from both addresses will
result in the same value.
LTVAELatest Transmit Violation Channel A Interrupt Enable
TABAETransmission Across Boundary Channel A Interrupt Enable
EDBEError Detected on Channel B Interrupt Enable
LTVBELatest Transmit Violation Channel B Interrupt Enable
TABBETransmission Across Boundary Channel B Interrupt Enable
-33/165-
15.12.2006
Page 34
User’s Manual
Revision 1.2.5 E-Ray
4.4.6 Status Interrupt Enable Set / Reset (SIES, SIER)
The settings in the Status Interrupt Enable register determine which status changes in the Status Interrupt Register will result in an interrupt.
Bit31302928272625242322212019181716
SIES,R R0 000 00
S:0x0038
R:0x003C
W
Reset0000000000000000
Bit 1514131211109876543210
R
SDSE MBSIE SUCSE SWEE
W
Reset0000000000000000
TOBCE
MTSBE WUPBE
TIBCE TI1ETI0E
000000
NMVCE
RFCLE RFNEE RXIE TXIE
CYCSE
MTSAE WUPAE
CASE WSTE
The enable bits are set by writing to address 0x0038 and reset by writing to address 0x003C. Writing
a ’1’ sets / resets the specific enable bit, writing a ’0’ has no effect. Reading from both addresses will
result in the same value.
SUCSEStartup Completed Successfully Interrupt Enable
MBSIEMessage Buffer Status Interrupt Enable
SDSEStart of Dynamic Segment Interrupt Enable
WUPAEWakeup Pattern Channel A Interrupt Enable
MTSAEMTS Received on Channel A Interrupt Enable
WUPBEWakeup Pattern Channel B Interrupt Enable
MTSBEMTS Received on Channel B Interrupt Enable
-34/165-
15.12.2006
Page 35
User’s Manual
Revision 1.2.5 E-Ray
4.4.7 Interrupt Line Enable (ILE)
Each of the two interrupt lines to the Host (eray_int0, eray_int1) can be enabled / disabled separately
by programming bit EINT0 and EINT1.
Bit31302928272625242322212019181716
ILER0000000000000000
0x0040 W
Reset0000000000000000
Bit 1514131211109876543210
R00000000000000
W
Reset0000000000000000
EINT1 EINT0
EINT0Enable Interrupt Line 0
1 = Interrupt line eray_int0 enabled
0 = Interrupt line eray_int0 disabled
EINT1Enable Interrupt Line 1
1 = Interrupt line eray_int1 enabled
0 = Interrupt line eray_int1 disabled
manual_programmers_model.fm
-35/165-
15.12.2006
Page 36
User’s Manual
Revision 1.2.5 E-Ray
4.4.8 Timer 0 Configuration (T0C)
Absolute timer. Specifies in terms of cycle count and macrotick the point in time when the timer 0
interrupt occurs. When the timer 0 interrupt is asserted, output signal eray_tint0 is set to ’1’ for the
duration of one macrotick and SIR.TI0 is set to ’1’.
Timer 0 can be activated as long as the POC is either in NORMAL_ACTIVE state or in
NORMAL_PASSIVE state. Timer 0 is deactivated when leaving NORMAL_ACTIVE state or
NORMAL_PASSIVE state except for transitions between the two states.
Before reconfiguration of the timer, the timer has to be halted first by writing bit T0RC to ’0’.
The 7-bit timer 0 cycle code determines the cycle set used for generation of the timer 0 interrupt.
For details about the configuration of the cycle code see Section 5.7.2 Cycle Counter Filtering.
T0MO[13:0]Timer 0 Macrotick Offset
Configures the macrotick offset from the beginning of the cycle where the interrupt is to occur.
The Timer 0 Interrupt occurs at this offset for each cycle of the cycle set.
Note: The configuration of timer 0 is compared against the macrotick counter value, there is no sep-
arate counter for timer 0.In case the CC leaves NORMAL_ACTIVEor NORMAL_PASSIVE
state, or if timer 0 is halted by Host command, output signal eray_tint0 is reset to ’0’ immediately.
manual_programmers_model.fm
-36/165-
15.12.2006
Page 37
User’s Manual
Revision 1.2.5 E-Ray
4.4.9 Timer 1 Configuration (T1C)
Relative timer. After the specified number of macroticks has expired, the timer 1 interrupt is asserted,
output signal eray_tint1 is set to ’1’ for the duration of one macrotick and SIR.TI1 is set to ’1’.
Timer 1 can be activated as long as the POC is either in NORMAL_ACTIVE state or in
NORMAL_PASSIVE state. Timer 1 is deactivated when leaving NORMAL_ACTIVE state or
NORMAL_PASSIVE state except for transitions between the two states.
Before reconfiguration of the timer, the timer has to be halted first by writing bit T1RC to ’0’.
When the configured macrotick count is reached the timer 1 interrupt is generated.
Valid values are: 2 to 16383 MT in continuous mode
1 to 16383 MT in single-shot mode
Note: In case the CC leaves NORMAL_ACTIVE or NORMAL_PASSIVEstate, orif timer1 ishalt-
ed by Host command, output signal eray_tint1 is reset to ’0’ immediately.
manual_programmers_model.fm
-37/165-
15.12.2006
Page 38
User’s Manual
Revision 1.2.5 E-Ray
4.4.10 Stop Watch Register 1 (STPW1)
The stop watch is activated by a rising or falling edge on pin eray_stpwt, by an interrupt 0,1 event
(rising edge on pin eray_int0 or eray_int1) or by theHost by writing bit SSWT to ’1’. With the macrotick counter increment following next to the stop watchactivation the actual cycle counter andmacrotick values are captured in register STPW1 while the slot counter values for channel A and B are
captured in register STPW2.
If enabled an edge on input eray_stpwt or an interrupt 0,1 event (rising edge on pin eray_int0
or eray_int1) activates the stop watch. In single-shot mode this bit is reset to ’0’ after the actual
cycle counter and macrotick value are stored in the Stop Watch register.
When the Host writes this bit to ’1’ the stop watch is activated. After the actual cycle counter
and macrotick value are stored in the Stop Watch register this bit is reset to ’0’. The bit is only
writeable while ESWT = ’0’.
SSCVA[10:0]Stop Watch Captured Slot Counter Value Channel A
State of the slot counter for channel A when the stop watch event occurred. Valid values are 0 to
2047.
SSCVB[10:0] Stop Watch Captured Slot Counter Value Channel B
State of the slot counter for channel B when the stop watch event occurred. Valid values are 0 to
2047.
manual_programmers_model.fm
-39/165-
15.12.2006
Page 40
User’s Manual
Revision 1.2.5 E-Ray
4.5 CC Control Registers
This section describes the registers provided by the CC to allow the Host to control the operation of
the CC. The FlexRay protocol specification requires the Host to write application configuration data
in CONFIG state only. Please consider that the configuration registers are not locked for writing in
DEFAULT_CONFIG state.
The configuration data is resetwhen DEFAULT_CONFIGstate is entered from hardreset. Tochange
POC state from DEFAULT_CONFIG to CONFIG state the Host has to apply CHI command CONFIG. If the Host wants the CC to leave CONFIG state, the Host has to proceed as described in Section
4.3.1 Lock Register (LCK).
All bits marked with an asterisk * can be updated in DEFAULT_CONFIG or CONFIG state only!
4.5.1 SUC Configuration Register 1 (SUCC1)
Bit31302928272625242322212019181716
SUCC1 R0000
0x0080 W
Reset0000110001000000
CCHB* CCHA* MTSB* MTSA*
HCSE* TSM*
WUCS*
PTA4* PTA3* PTA2* PTA1* PTA0*
Bit 1514131211109876543210
R
CSA4* CSA3* CSA2* CSA1* CSA0*
W
Reset0001000010000000
0
TXSY* TXST*
PBSY000
CMD3 CMD2 CMD1 CMD0
CMD[3:0]CHI Command Vector
The Host may write any CHI command at any time, but certain commands are enabled only in
certain POC states. If a command is not enabled, it will not be executed, the CHI command vector CMD[3:0] will be reset to "0000" = command_not_accepted, and flag EIR.CNA will be set
to ’1’. In case the previous CHI command has not yet completed, EIR.CCL is set to ’1’ together
with EIR.CNA; the CHI command needs to be repeated. Except for HALT state, a POC state
change command applied while the CC is already in the requested POC state will be ignored.
Reading CMD[3:0] shows whether the last CHI command was accepted. The actual POC state
is monitored by CCSV.POCS[5:0]. The reserved CHI commands belong to the hardware test
functions.
command_not_accepted
CMD[3:0] is reset to "0000" due to one of the following conditions:
• Illegal command applied by the Host
• Host applied command to leave CONFIG state without preceding config lock key
• Host applied new command while execution of the previous Host command has not completed
• Host writes command_not_accepted
When CMD[3:0] is reset to "0000", EIR.CNA is set, and - if enabled - an interrupt is generated.
Commands which are not accepted are not executed.
CONFIG
Go to POC state CONFIG when called in POC states DEFAULT_CONFIG, READY, or in
MONITOR_MODE.WhencalledinHALTstatetheCCtransitstoPOCstate
DEFAULT_CONFIG. When called in any other state, CMD[3:0] will be reset to "0000" =
command_not_accepted.
READY
Go to POC state READY when called in POC states CONFIG, NORMAL_ACTIVE,
NORMAL_PASSIVE, STARTUP, or WAKEUP. When called in any other state, CMD[3:0] will
be reset to "0000" = command_not_accepted.
WAKEUP
Go to POC state WAKEUP when called in POC state READY. When called in any other state,
CMD[3:0] will be reset to "0000" = command_not_accepted.
RUN
Go to POC state STARTUP when called in POC state READY. When called in any other state,
CMD[3:0] will be reset to "0000" = command_not_accepted.
ALL_SLOTS
Leave SINGLE slot mode after successful startup / integration at the next end of cycle when
called in POC states NORMAL_ACTIVE or NORMAL_PASSIVE. When called in any other
state, CMD[3:0] will be reset to "0000" = command_not_accepted.
HALT
Set halt request CCSV.HRQ and go to POC state HALT at the next end of cycle when called in
POC states NORMAL_ACTIVE or NORMAL_PASSIVE. When called in any other state,
manual_programmers_model.fm
CMD[3:0] will be reset to "0000" = command_not_accepted.
FREEZE
Set the freeze status indicator CCSV.FSI and go to POC state HALT immediately. Can be called
from any state.
SEND_MTS
Send single MTS symbol during the next following symbol window on the channel configured
by MTSA, MTSB, when called in POC state NORMAL_ACTIVE after CC entered ALL slot
mode (CCSV.SLM[1:0] = "11"). When called in any other state, or when called while a previ-
ously requested MTS has not yet been transmitted, CMD[3:0] will be reset to "0000" =
command_not_accepted.
-41/165-
15.12.2006
Page 42
User’s Manual
Revision 1.2.5 E-Ray
ALLOW_COLDSTART
The command resets CCSV.CSI to enable the node to become leading coldstarter. When called
in states DEFAULT_CONFIG, CONFIG, HALT, or MONITOR_MODE, CMD[3:0] will be
reset to "0000" = command_not_accepted. To become leading coldstarter it is also required that
both TXST and TXSY are set.
RESET_STATUS_INDICATORS
Resets status flags CCSV.CSNI, CCSV.CSAI, and CCSV.WSV[2:0] to their default values.
May be called in POC states READY and STARTUP. When called in any other state, CMD[3:0]
will be reset to "0000" = command_not_accepted.
MONITOR_MODE
Enter MONITOR_MODE when called in POC state CONFIG. In this mode the CC is able to
receive FlexRay frames and wakeup pattern. It is also able to detect coding errors. The temporal
integrity of received frames is not checked. This mode can be used for debugging purposes, e.g.
in case that the startup of a FlexRay network fails. When called in any other state, CMD[3:0]
will be reset to "0000" = command_not_accepted. For details see 5.5.4 MONITOR_MODE
CLEAR_RAMS
Sets MHDS.CRAM when called in DEFAULT_CONFIG or CONFIG state. When called in any
other state, CMD[3:0] will be reset to "0000" = command_not_accepted. MHDS.CRAM is also
set when the CC leaves hard reset. By setting MHDS.CRAM all internal RAM blocks are initialized to zero. During the initialization of the RAMs, PBSY will show POC busy. Access to
the configuration and status registers is possible during execution of CHI command
CLEAR_RAMS.
The initialization of the E-Ray internal RAM blocks requires 2048 eray_bclk cycles. There
should be no Host access to IBF or OBF during initialization of the internal RAM blocks after
hard reset or after assertion of CHI command CLEAR_RAMS. Before asserting CHI command
CLEAR_RAMS the Host should make sure that no transfer between Message RAM and IBF /
OBF or the Transient Buffer RAMs is ongoing. This command also resets the Message Buffer
Status registers MHDS, LDTS, FSR, MHDF, TXRQ1/2/3/4, NDAT1/2/3/4, and MBSC1/2/3/4.
Note: All accepted commands with exception of CLEAR_RAMS and SEND_MTS will cause a
change of register CCSV after at most 8 cycles of the slower of the two clocks eray_bclk and
eray_sclk, counted from the falling edge of the CHI input signal eray_select, assumed that
POC was not busy when the command was applied and that no POC state change was forced
by bus activity in that time frame. Reading register CCSV will show data that is delayed by
synchronization from eray_sclk to eray_bclk domain and bythe Host-specific CPUinterface.
PBSYPOC Busy
manual_programmers_model.fm
Signals that the POC is busy and cannot accept a command from the Host. CMD[3:0] is locked
against write accesses. Set to ’1’ after hard reset during initialization of internal RAM blocks.
1 = POC is busy, CMD[3:0] locked
0 = POC not busy, CMD[3:0] writeable
TXSTTransmit Startup Frame in Key Slot (pKeySlotUsedForStartup)
Defines whether the key slot is used to transmit startup frames. The bit can be modified in
DEFAULT_CONFIG or CONFIG state only.
1 = Key slot used to transmit startup frame, node is leading or following coldstarter
0 = No startup frame transmission in key slot, node is non-coldstarter
-42/165-
15.12.2006
Page 43
User’s Manual
Revision 1.2.5 E-Ray
TXSYTransmit Sync Frame in Key Slot (pKeySlotUsedForSync)
Defines whether the key slot is used to transmit sync frames. The bit can be modified in
DEFAULT_CONFIG or CONFIG state only.
1 = Key slot used to transmit sync frame, node is sync node
0 = No sync frame transmission in key slot, node is neither sync nor coldstart node
Note: The protocol requires that both bits TXST and TXSY are set for coldstart nodes.
CSA[4:0]Cold Start Attempts (gColdStartAttempts)
Configures the maximum number of attempts that a cold starting node is permitted to try to start
up the network without receiving any valid response from another node. It can be modified in
DEFAULT_CONFIG or CONFIG state only. Must be identical in all nodes of a cluster. Valid
values are 2 to 31.
PTA[4:0]Passive to Active (pAllowPassiveToActive)
Defines the number of consecutive even / odd cycle pairs that must have valid clock correction
terms before the CC is allowed to transit from NORMAL_PASSIVE to NORMAL_ACTIVE
state. If set to "00000" the CC is not allowed to transit from NORMAL_PASSIVE to
NORMAL_ACTIVE state. It can be modified in DEFAULT_CONFIG or CONFIG state only.
Valid values are 0 to 31 even / odd cycle pairs.
WUCSWakeup Channel Select (pWakeupChannel)
With this bit the Host selects the channel on which the CC sends the Wakeup pattern. The CC
ignores any attempt to change the status of this bit when not in DEFAULT_CONFIG or CONFIG state.
1 = Send wakeup pattern on channel B
0 = Send wakeup pattern on channel A
TSMTransmission Slot Mode (pSingleSlotEnabled)
Selects the initial transmission slot mode. In SINGLE slot mode the CC may only transmit in the
preconfigured key slot. The key slot ID is configured in the header section of message buffer 0
respectively message buffers 0 and 1 depending on bit MRC.SPLM. In case TSM = ’1’, message buffer 0 respectively message buffers 0,1 can be (re)configured in DEFAULT_CONFIG or
CONFIG state only. In ALL slot mode the CC may transmit in all slots. TSM is a configuration
bit which can only be set / reset by the Host. The bit can be written in DEFAULT_CONFIG or
CONFIG state only. The CC changes to ALL slot mode when the Host successfully applied the
ALL_SLOTS command by writing CMD[3:0] = "0101" in POC states NORMAL_ACTIVE or
NORMAL_PASSIVE. The actual slot mode is monitored by CCSV.SLM[1:0].
1 = SINGLE Slot Mode (default after hard reset)
0 = ALL Slot Mode
manual_programmers_model.fm
HCSEHalt due to Clock Sync Error (pAllowHaltDueToClock)
Controls the transition to HALT state due to a clock synchronization error. The bit can be modified in DEFAULT_CONFIG or CONFIG state only.
1 = CC will enter HALT state
0 = CC will enter / remain in NORMAL_PASSIVE
MTSASelect Channel A for MTS Transmission
The bit selects channel A for MTS symbol transmission. The flag is reset by default and may be
modified only in DEFAULT_CONFIG or CONFIG state.
1 = Channel A selected for MTS transmission
0 = Channel A disabled for MTS transmission
-43/165-
15.12.2006
Page 44
User’s Manual
Revision 1.2.5 E-Ray
MTSBSelect Channel B for MTS Transmission
The bit selects channel B for MTS symbol transmission. The flag is reset by default and may be
modified only in DEFAULT_CONFIG or CONFIG state.
1 = Channel B selected for MTS transmission
0 = Channel B disabled for MTS transmission
Note: MTSA,Bmay also be changed outside DEFAULT_CONFIG or CONFIG state when the write
to SUCC1 register is directly preceded bythe unlocksequence asdescribed in4.3.1 LockRegister (LCK). This may be combined with CHI command SEND_MTS. If both bits MTSA and
MTSB are set to ’1’ an MTS symbol will be transmitted on both channels when requested by
writing CMD[3:0] = "1000".
CCHAConnected to Channel A (pChannels)
Configures whether the node is connected to channel A.
1 = Node connected to channel A (default after hard reset)
0 = Not connected to channel A
CCHBConnected to Channel B (pChannels)
Configures whether the node is connected to channel B.
1 = Node connected to channel B (default after hard reset)
0 = Not connected to channel B
Table 3 below references the CHI commands from the FlexRay Protocol Specification v2.1 (section
2.2.1.1, Table 2-2) to the E-Ray CHI command vector CMD[3:0].
CHI commandWhere processed (POC States)CHI Command Vector
Configures wakeup / startup listen timeout in µT. The range for pdListenTimeout is 1284 to
1283846 µT.
LTN[3:0]Listen Timeout Noise (gListenNoise - 1)
Configures the upper limit for startup and wakeup listen timeout in the presence of noise
expressed as a multiple of pdListenTimeout. The range for gListenNoise is 2 to 16. LTN[3:0]
must be configured identical in all nodes of a cluster.
Note: The wakeup / startup noise timeout is calculated as follows:
The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.
Bit31302928272625242322212019181716
SUCC3 R0000000000000000
0x0088 W
Reset0000000000000000
Bit 1514131211109876543210
R00000000
W
Reset0000000000010001
WCF3* WCF2* WCF1* WCF0* WCP3* WCP2* WCP1* WCP0*
WCP[3:0]Maximum Without Clock Correction Passive (gMaxWithoutClockCorrectionPassive)
Defines the number of consecutive even / odd cycle pairs with missing clock correction terms
that will cause a transition from NORMAL_ACTIVE to NORMAL_PASSIVE state. Must be
manual_programmers_model.fm
identical in all nodes of a cluster. Valid values are 1 to 15 cycle pairs.
WCF[3:0]Maximum Without Clock Correction Fatal (gMaxWithoutClockCorrectionFatal)
Defines the number of consecutive even / odd cycle pairs with missing clock correction terms
that will cause a transition from NORMAL_ACTIVE or NORMAL_PASSIVE to HALT state.
Must be identical in all nodes of a cluster. Valid values are 1 to 15 cycle pairs.
-45/165-
15.12.2006
Page 46
User’s Manual
Revision 1.2.5 E-Ray
4.5.4 NEM Configuration Register (NEMC)
The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.
Configures the duration of the Transmission Start Sequence (TSS) in terms of bit times (1 bit
time = 4 µT = 100ns @ 10Mbps). Must be identical in all nodes of a cluster. Valid values are 3 to
15 bit times.
CASM[6:0] Collision Avoidance Symbol Max (gdCASRxLowMax)
Configures the upper limit of the acceptance window for a collision avoidance symbol (CAS).
CASM6 is fixed to ’1’. Valid values are 67 to 99 bit times.
SPP[1:0]Strobe Point Position
Defines the sample count value for strobing. The strobed bit value is set to the voted value when
the sample count is incremented to the value configured by SPP[1:0].
The Baud Rate Prescaler configures the baud rate on the FlexRay bus. The baud rates listed
below are valid with a sample clock eray_sclk = 80 MHz. One bit time always consists of 8
samples independent of the configured baud rate.
RXW[8:0]Wakeup Symbol Receive Window Length (gdWakeupSymbolRxWindow)
Configures the number of bit times used by the node to test the duration of the received wakeup
pattern. Must be identical in all nodes of a cluster. Valid values are 76 to 301 bit times.
RWP[5:0]Repetitions of Tx Wakeup Pattern (pWakeupPattern)
Configures the number of repetitions (sequences) of the Tx wakeup symbol. Valid values are 2
to 63.
-47/165-
15.12.2006
Page 48
User’s Manual
Revision 1.2.5 E-Ray
4.5.6 PRT Configuration Register 2 (PRTC2)
The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.
RXI[5:0]Wakeup Symbol Receive Idle (gdWakeupSymbolRxIdle)
Configures the number of bit times used by the node to test the duration of the idle phase of the
received wakeup symbol. Must be identical in all nodes of a cluster. Valid values are 14 to 59 bit
times.
RXL[5:0]Wakeup Symbol Receive Low (gdWakeupSymbolRxLow)
Configures the number of bit times used by the node to test the duration of the low phase of the
received wakeup symbol. Must be identical in all nodes of a cluster. Valid values are 10 to 55 bit
times.
TXI[7:0]Wakeup Symbol Transmit Idle (gdWakeupSymbolTxIdle)
Configures the number of bit times used by the node to transmit the idle phase of the wakeup
symbol. Must be identical in all nodes of a cluster. Valid values are 45 to 180 bit times.
TXL[5:0]Wakeup Symbol Transmit Low (gdWakeupSymbolTxLow)
Configures the number of bit times used by the node to transmit the low phase of the
wakeup symbol. Must be identical in all nodes of a cluster. Valid values are 15 to 60 bit times.
manual_programmers_model.fm
-48/165-
15.12.2006
Page 49
User’s Manual
Revision 1.2.5 E-Ray
4.5.7 MHD Configuration Register (MHDC)
The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.
SFDL[6:0] Static Frame Data Length (gPayloadLengthStatic)
Configures the cluster-wide payload length for all frames sent in the static segment in double
bytes. The payload length must be identical in all nodes of a cluster. Valid values are 0 to 127.
SLT[12:0]Start of Latest Transmit (pLatestTx)
Configures the maximum minislot value allowed before inhibiting frame transmission in the
dynamic segment of the cycle. There is no transmission in dynamic segment if SLT[12:0] is set
to zero. Valid values are 0 to 7981 minislots.
manual_programmers_model.fm
-49/165-
15.12.2006
Page 50
User’s Manual
Revision 1.2.5 E-Ray
4.5.8 GTU Configuration Register 1 (GTUC1)
The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.
Configures the duration of one communication cycle in macroticks. The cycle length must be
identical in all nodes of a cluster. Valid values are 10 to 16000 MT.
SNM[3:0]Sync Node Max (gSyncNodeMax)
Maximum number of frames within a cluster with sync frame indicator bit SYN set to ’1’. Must
be identical in all nodes of a cluster. Valid values are 2 to 15.
manual_programmers_model.fm
-50/165-
15.12.2006
Page 51
User’s Manual
Revision 1.2.5 E-Ray
4.5.10 GTU Configuration Register 3 (GTUC3)
The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.
UIOA[7:0] Microtick Initial Offset Channel A (pMicroInitialOffset[A])
Configures the number of microticks between the actual time reference point on channel A and
the subsequent macrotick boundary of the secondary time reference point. The parameter
depends on pDelayCompensation[A] and therefore has to be set for each channel independently.
Valid values are 0 to 240 µT.
UIOB[7:0] Microtick Initial Offset Channel B (pMicroInitialOffset[B])
Configures the number of microticks between the actual time reference point on channel B and
the subsequent macrotick boundary of the secondary time reference point. The parameter
depends on pDelayCompensation[B] and therefore has to be set for each channel independently.
Valid values are 0 to 240 µT.
MIOA[6:0] Macrotick Initial Offset Channel A (pMacroInitialOffset[A])
Configures the number of macroticks between the static slot boundary and the subsequent macrotick boundary of the secondary time reference point based on the nominal macrotick duration.
Must be identical in all nodes of a cluster. Valid values are 2 to 72 MT.
MIOB[6:0] Macrotick Initial Offset Channel B (pMacroInitialOffset[B])
Configures the number of macroticks between the static slot boundary and the subsequent macrotick boundary of the secondary time reference point based on the nominal macrotick duration.
Must be identical in all nodes of a cluster. Valid values are 2 to 72 MT.
manual_programmers_model.fm
-51/165-
15.12.2006
Page 52
User’s Manual
Revision 1.2.5 E-Ray
4.5.11 GTU Configuration Register 4 (GTUC4)
The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only. For details about configuration of NIT[13:0] and OCS[13:0] see Section 5.1.5 Configuration of NIT Start
and Offset Correction Start.
NIT[13:0]Network Idle Time Start (gMacroPerCycle - gdNIT - 1)
Configures the starting point of the Network Idle Time NIT at the end of the communication
cycle expressed in terms of macroticks from the beginning of the cycle. The start of NIT is recognized if Macrotick = gMacroPerCycle - gdNIT -1 and the increment pulse of Macrotick is set.
Must be identical in all nodes of a cluster. Valid values are 7 to 15997 MT.
Determines the start of the offset correction within the NIT phase, calculated from start of cycle.
Must be identical in all nodes of a cluster. For cluster consisting of E-Ray implementations only,
it is sufficient to program OCS = NIT + 1. Valid values are 8 to 15998 MT.
manual_programmers_model.fm
-52/165-
15.12.2006
Page 53
User’s Manual
Revision 1.2.5 E-Ray
4.5.12 GTU Configuration Register 5 (GTUC5)
The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.
DCA[7:0]Delay Compensation Channel A (pDelayCompensation[A])
Used to compensate for reception delays on the indicated channel. This covers assumed propagation delay up to cPropagationDelayMax for microticks in the range of 0.0125 to 0.05µs. In
practice, the minimum of the propagation delays of all sync nodes should be applied.
Valid values are 0 to 200 µT.
DCB[7:0]Delay Compensation Channel B (pDelayCompensation[B])
Used to compensate for reception delays on the indicated channel. This covers assumed propagation delay up to cPropagationDelayMax for microticks in the range of 0.0125 to 0.05µs. In
practice, the minimum of the propagation delays of all sync nodes should be applied.
Configures the duration of a static slot in macroticks. The static slot length must be identical in
all nodes of a cluster. Valid values are 4 to 659 MT.
NSS[9:0]Number of Static Slots (gNumberOfStaticSlots)
Configures the number of static slots in a cycle. At least 2 coldstart nodes must be configured to
startup a FlexRay network. The number of static slots must be identical in all nodes of a cluster.
Valid values are 2 to 1023.
4.5.15 GTU Configuration Register 8 (GTUC8)
The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.
Configures the duration of a minislot in macroticks. The minislot length must be identical in all
nodes of a cluster. Valid values are 2 to 63 MT.
NMS[12:0] Number of Minislots (gNumberOfMinislots)
Configures the number of minislots within the dynamic segment of a cycle. The number of min-
manual_programmers_model.fm
islots must be identical in all nodes of a cluster. Valid values are 0 to 7986.
-54/165-
15.12.2006
Page 55
User’s Manual
Revision 1.2.5 E-Ray
4.5.16 GTU Configuration Register 9 (GTUC9)
The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.
Bit31302928272625242322212019181716
GTUC9
0x00C0 W
R00000000000000
Reset0000000000000000
Bit 1514131211109876543210
R0 00
W
Reset0000000100000001
MAPO4*MAPO3*MAPO2*MAPO1*MAPO
0*
00
APO5* APO4* APO3* APO2* APO1* APO0*
DSI1* DSI0*
APO[5:0]Action Point Offset (gdActionPointOffset)
Configures the action point offset in macroticks within static slots and symbol window. Must be
identical in all nodes of a cluster. Valid values are 1 to 63 MT.
MAPO[4:0] Minislot Action Point Offset (gdMinislotActionPointOffset)
Configures the action point offset in macroticks within the minislots of the dynamic segment.
Must be identical in all nodes of a cluster. Valid values are 1 to 31 MT.
The duration of the dynamic slot idle phase has to be greater or equal than the idle detection
time. Must be identical in all nodes of a cluster. Valid values are 0 to 2 Minislot.
4.5.17 GTU Configuration Register 10 (GTUC10)
The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.
MOC[13:0] Maximum Offset Correction (pOffsetCorrectionOut)
Holds the maximum permitted offset correction value to be applied by the internal clock synchronization algorithm (absolute value). The CC checks only the internal offset correction value
manual_programmers_model.fm
against the maximum offset correction value. Valid values are 5 to 15266 µT.
MRC[10:0] Maximum Rate Correction (pRateCorrectionOut)
Holds the maximum permitted rate correction value to be applied by the internal clock synchronization algorithm. The CC checks only the internal rate correction value against the maximum
rate correction value (absolute value). Valid values are 2 to 1923 µT.
-55/165-
15.12.2006
Page 56
User’s Manual
Revision 1.2.5 E-Ray
4.5.18 GTU Configuration Register 11 (GTUC11)
Bit31302928272625242322212019181716
GTUC11
0x00C8 W
R00000
Reset0000000000000000
Bit 1514131211109876543210
R000000
W
Reset0000000000000000
ERC2* ERC1* ERC0*
ERCC1 ERCC0
00000
000000
EOC2* EOC1* EOC0*
EOCC1 EOCC0
EOCC[1:0] External Offset Correction Control (vExternOffsetControl)
By writing to EOCC[1:0] the external offset correction is enabled as specified below. Should be
modified only outside NIT.
00, 01 = No external offset correction
10 =External offset correction value subtracted from calculated offset correction value
11 =External offset correction value added to calculated offset correction value
ERCC[1:0] External Rate Correction Control (vExternRateControl)
By writing to ERCC[1:0] the external rate correction is enabled as specified below. Should be
modified only outside NIT.
00, 01 = No external rate correction
10 =External rate correction value subtracted from calculated rate correction value
11 =External rate correction value added to calculated rate correction value
Holds the external offset correction value in microticks to be applied by the internal clock synchronization algorithm. The value is subtracted / added from / to the calculated offset correction
value. The value is applied during NIT. May be modified in DEFAULT_CONFIG or CONFIG
state only. Valid values are 0 to 7 µT.
Holds the external rate correction value in microticks to be applied by the internal clock synchronization algorithm. The value is subtracted / added from / to the calculated rate correction
value. The value is applied during NIT. May be modified in DEFAULT_CONFIG or CONFIG
state only. Valid values are 0 to 7 µT.
manual_programmers_model.fm
-56/165-
15.12.2006
Page 57
User’s Manual
Revision 1.2.5 E-Ray
4.6 CC Status Registers
During 8/16-bit accesses to status variables coded with more than 8/16-bit, the variable might be updated by the CC between twoaccesses (non-atomic read accesses). The status vectormay change faster than the Host can poll the status vector, depending on eray_bclk frequency.
Indicates the actual state of operation of the CC Protocol Operation Control
00 0000 = DEFAULT_CONFIG state
00 0001 = READY state
00 0010 = NORMAL_ACTIVE state
00 0011 = NORMAL_PASSIVE state
00 0100 = HALT state
00 0101 = MONITOR_MODE state
00 0110…00 1110 = reserved
00 1111 = CONFIG state
Indicates the actual state of operation of the POC in the wakeup path
01 0000 = WAKEUP_STANDBY state
01 0001 = WAKEUP_LISTEN state
01 0010 = WAKEUP_SEND state
01 0011 = WAKEUP_DETECT state
01 0100…01 1111 = reserved
Indicates the actual state of operation of the POC in the startup path
10 0000 = STARTUP_PREPARE state
10 0001 = COLDSTART_LISTEN state
manual_programmers_model.fm
10 0010 = COLDSTART_COLLISION_RESOLUTION state
10 0011 = COLDSTART_CONSISTENCY_CHECK state
10 0100 = COLDSTART_GAP state
10 0101 = COLDSTART_JOIN State
10 0110 = INTEGRATION_COLDSTART_CHECK state
10 0111 = INTEGRATION_LISTEN state
10 1000 = INTEGRATION_CONSISTENCY_CHECK state
10 1001 = INITIALIZE_SCHEDULE state
10 1010 = ABORT_STARTUP state
10 1011 = STARTUP_SUCCESS state
10 1100…11 1111 = reserved
-57/165-
15.12.2006
Page 58
User’s Manual
Revision 1.2.5 E-Ray
FSIFreeze Status Indicator (vPOC!Freeze)
Indicates that the POC has entered the HALT state due to CHI command FREEZE or due to an
error condition requiring an immediate POC halt. Reset by transition from HALT to
DEFAULT_CONFIG state.
HRQHalt Request (vPOC!CHIHaltRequest)
Indicates that a request from the Host has been received to halt the POC at the end of the communication cycle. Reset by transition from HALT to DEFAULT_CONFIG state or when entering READY state.
SLM[1:0]Slot Mode (vPOC!SlotMode)
Indicates the actual slot mode of the POC in states READY, STARTUP, NORMAL_ACTIVE,
and NORMAL_PASSIVE. Default is SINGLE. Changes to ALL, depending on SUCC1.TSM.
In NORMAL_ACTIVE or NORMAL_PASSIVE state the CHI command ALL_SLOTS will
change the slot mode from SINGLE over ALL_PENDING to ALL. Set to SINGLE in all other
states.
00 = SINGLE
01 = reserved
10 = ALL_PENDING
11 = ALL
Indicates that the cold start procedure occurred under noisy conditions. Reset by CHI command
RESET_STATUS_INDICATORS or by transition from HALT to DEFAULT_CONFIG state or
from READY to STARTUP state.
CSAIColdstart Abort Indicator
Coldstart aborted. Reset by CHI command RESET_STATUS_INDICATORS or by transition
from HALT to DEFAULT_CONFIG state or from READY to STARTUP state.
CSICold Start Inhibit (vColdStartInhibit)
Indicates that the node is disabled from cold starting. The flag is set whenever the POC enters
READY state due to CHI command READY. The flag has to be reset under control of the Host
by CHI command ALLOW_COLDSTART (SUCC1.CMD[3:0] = "1001").
1 = Cold starting of node disabled
0 = Cold starting of node enabled
manual_programmers_model.fm
-58/165-
15.12.2006
Page 59
User’s Manual
Revision 1.2.5 E-Ray
WSV[2:0]Wakeup Status (vPOC!WakeupStatus)
Indicatesthestatusofthecurrentwakeupattempt.ResetbyCHIcommand
RESET_STATUS_INDICATORS or by transition from HALT to DEFAULT_CONFIG state or
from READY to STARTUP state.
000 =UNDEFINED. Wakeup not yet executed by the CC.
001 =RECEIVED_HEADER. Set when the CC finishes wakeup due to the reception of a
frame header without coding violation on either channel in WAKEUP_LISTEN state.
010 =RECEIVED_WUP. Set when the CC finishes wakeup due to the reception of a valid
wakeup pattern on the configured wakeup channel in WAKEUP_LISTEN state.
011 =COLLISION_HEADER. Set when the CC stops wakeup due to a detected collision
during wakeup pattern transmission by receiving a valid header on either channel.
100 =COLLISION_WUP. Set when the CC stops wakeup due to a detected collision during
wakeup pattern transmission by receiving a valid wakeup pattern on the configured
wakeup channel.
Indicates the number of remaining coldstart attempts. The RUN command resets this counter to
the maximum number of coldstart attempts as configured by SUCC1.CSA[4:0].
PSL[5:0]POC Status Log
Status of POCS[5:0] immediately before entering HALT state. Set when entering HALT state.
Set to HALT when FREEZE command is applied during HALT state. Reset to "00 0000" when
leaving HALT state.
manual_programmers_model.fm
-59/165-
15.12.2006
Page 60
User’s Manual
Revision 1.2.5 E-Ray
4.6.2 CC Error Vector (CCEV)
Bit31302928272625242322212019181716
CCEV R0000000000000000
0x0104 W
Reset0000000000000000
Bit 1514131211109876543210
R000PTAC4 PTAC3 PTAC2 PTAC1 PTAC0
W
Reset0000000000000000
ERRM1 ERRM0
00CCFC3 CCFC2 CCFC1 CCFC0
Reset by transition from HALT to DEFAULT_CONFIG state or when entering READY state.
CCFC[3:0] Clock Correction Failed Counter (vClockCorrectionFailed)
The Clock Correction Failed Counter is incremented by one at the end of any odd communication cycle where either the missing offset correction error or missing rate correction error are
active. The Clock Correction Failed Counter is reset to ’0’ at the end of an odd communication
cycle if neither the offset correction failed nor the rate correction failed errors are active. The
Clock Correction Failed Counter stops at 15.
ERRM[1:0]Error Mode (vPOC!ErrorMode)
Indicates the actual error mode of the POC.
00 = ACTIVE (green)
01 = PASSIVE (yellow)
10 = COMM_HALT (red)
11 = reserved
PTAC[4:0] Passive to Active Count (vAllowPassiveToActive)
Indicates the number of consecutive even / odd cycle pairs that have passed with valid rate and
offset correction terms, while the node is waiting to transit from NORMAL_PASSIVE state to
NORMAL_ACTIVEstate.ThetransitiontakesplacewhenPTAC[4:0]equals
SUCC1.PTA[4:0] -1.
SCCA[10:0]Slot Counter Channel A (vSlotCounter[A])
Current slot counter value on channel A. The value is incremented by the CC and reset at the
start of a communication cycle. Valid values are 0 to 2047.
SCCB[10:0]Slot Counter Channel B (vSlotCounter[B])
Current slot counter value on channel B. The value is incremented by the CC and reset at the
start of a communication cycle. Valid values are 0 to 2047.
4.6.4 Macrotick and Cycle Counter Value (MTCCV)
Bit31302928272625242322212019181716
MTCCV R0000000000CCV5 CCV4 CCV3 CCV2 CCV1 CCV0
0x0114 W
Reset0000000000000000
Bit 1514131211109876543210
R0 0
W
Reset0000000000000000
MTV13 MTV12 MTV11 MTV10
MTV9 MTV8 MTV7 MTV6 MTV5 MTV4 MTV3 MTV2 MTV1 MTV0
MTV[13:0] Macrotick Value (vMacrotick)
Current macrotick value. The value is incremented by the CC and reset at the start of a communication cycle. Valid values are 0 to 16000.
CCV[5:0]Cycle Counter Value (vCycleCounter)
Current cycle counter value. The value is incremented by the CC at the start of a communication
cycle. Valid values are 0 to 63.
Rate correction value (two’s complement). Calculated internal rate correction value before limitation. If the RCV value exceeds the limits defined by GTUC10.MRC[10:0], flag SFS.RCLR
is set to ’1’.
OCV[18:0] Offset Correction Value (vOffsetCorrection)
Offset correction value (two’s complement). Calculated internal offset correction value before
limitation. If the OCV value exceeds the limits defined by GTUC10.MOC[13:0], flag
SFS.OCLR is set to ’1’.
Note: The external rate / offset correction value is added to the limited rate / offset correction value.
manual_programmers_model.fm
-62/165-
15.12.2006
Page 63
User’s Manual
Revision 1.2.5 E-Ray
4.6.7 Sync Frame Status (SFS)
The maximum number of valid sync frames in a communication cycle is 15.
VSAE[3:0] Valid Sync Frames Channel A, even communication cycle
Holds the number of valid sync frames received on channel A in the even communication cycle.
If transmission of sync frames is enabled by SUCC1.TXSY the value is incremented by one.
The value is updated during the NIT of each even communication cycle.
VSAO[3:0] Valid Sync Frames Channel A, odd communication cycle
Holds the number of valid sync frames received on channel A in the odd communication cycle.
If transmission of sync frames is enabled by SUCC1.TXSY the value is incremented by one.
The value is updated during the NIT of each odd communication cycle.
VSBE[3:0] Valid Sync Frames Channel B, even communication cycle
Holds the number of valid sync frames received on channel B in the even communication cycle.
If transmission of sync frames is enabled by SUCC1.TXSY the value is incremented by one.
The value is updated during the NIT of each even communication cycle.
VSBO[3:0] Valid Sync Frames Channel B, odd communication cycle
Holds the number of valid sync frames received on channel B in the odd communication cycle.
If transmission of sync frames is enabled by SUCC1.TXSY the value is incremented by one.
The value is updated during the NIT of each odd communication cycle.
Note: The bit fields above are only valid if the respective channel is assigned to the CC by
SUCC1.CCHA or SUCC1.CCHB.
MOCSMissing Offset Correction Signal
The Missing Offset Correction flag signals to the Host, that no offset correction calculation can
be performed because no sync frames were received. The flag is updated by the CC at start of
offset correction phase.
1 = Missing offset correction signal
manual_programmers_model.fm
0 = Offset correction signal valid
OCLROffset Correction Limit Reached
The Offset Correction Limit Reached flag signals to the Host, that the offset correction value
has exceeded its limit as defined by GTUC10.MOC[13:0]. The flag is updated by the CC at
start of offset correction phase.
The Missing Rate Correction flag signals to the Host, that no rate correction calculation can be
performed because no pairs of even / odd sync frames were received. The flag is updated by the
CC at start of offset correction phase.
1 = Missing rate correction signal
0 = Rate correction signal valid
RCLRRate Correction Limit Reached
The Rate Correction Limit Reached flag signals to the Host, that the rate correction value has
exceeded its limit as defined by GTUC10.MRC[10:0]. The flag is updated by the CC at start of
offset correction phase.
Symbol window related status information. Updated by the CC at the end of the symbol window for
each channel. During startup the status data is not updated.
SESASyntax Error in Symbol Window Channel A (vSS!SyntaxErrorA)
1 = Syntax error during symbol window detected on channel A
0 = No syntax error detected
SBSASlot Boundary Violation in Symbol Window Channel A (vSS!BViolationA)
1 = Slot boundary violation during symbol window detected on channel A
0 = No slot boundary violation detected
TCSATransmission Conflict in Symbol Window Channel A (vSS!TxConflictA)
1 = Transmission conflict in symbol window detected on channel A
0 = No transmission conflict detected
SESBSyntax Error in Symbol Window Channel B (vSS!SyntaxErrorB)
manual_programmers_model.fm
1 = Syntax error during symbol window detected on channel B
0 = No syntax error detected
SBSBSlot Boundary Violation in Symbol Window Channel B (vSS!BViolationB)
1 = Slot boundary violation during symbol window detected on channel B
0 = No slot boundary violation detected
TCSBTransmission Conflict in Symbol Window Channel B (vSS!TxConflictB)
1 = Transmission conflict in symbol window detected on channel B
0 = No transmission conflict detected
-64/165-
15.12.2006
Page 65
User’s Manual
Revision 1.2.5 E-Ray
MTSAMTS Received on Channel A (vSS!ValidMTSA)
Media Access Test symbol received on channel A during the preceding symbol window.
Updated by the CC for each channel at the end of the symbol window. When this bit is set to ’1’,
also interrupt flag SIR.MTSA is set to ’1’.
1 = MTS symbol received on channel A
0 = No MTS symbol received on channel A
MTSBMTS Received on Channel B (vSS!ValidMTSB)
Media Access Test symbol received on channel B during the preceding symbol window.
Updated by the CC for each channel at the end of the symbol window. When this bit is set to ’1’,
also interrupt flag SIR.MTSB is set to ’1’.
1 = MTS symbol received on channel B
0 = No MTS symbol received on channel B
NIT related status information. Updated by the CC at the end of the NIT for each channel:
SENASyntax Error during NIT Channel A (vSS!SyntaxErrorA)
1 = Syntax error during NIT detected on channel A
0 = No syntax error detected
SBNASlot Boundary Violation during NIT Channel A (vSS!BViolationA)
1 = Slot boundary violation during NIT detected on channel A
0 = No slot boundary violation detected
SENBSyntax Error during NIT Channel B (vSS!SyntaxErrorB)
1 = Syntax error during NIT detected on channel B
0 = No syntax error detected
SBNBSlot Boundary Violation during NIT Channel B (vSS!BViolationB)
1 = Slot boundary violation during NIT detected on channel B
0 = No slot boundary violation detected
manual_programmers_model.fm
-65/165-
15.12.2006
Page 66
User’s Manual
Revision 1.2.5 E-Ray
4.6.9 Aggregated Channel Status (ACS)
The aggregated channel status provides the Host with an accrued status of channel activity for all
communication slots regardless of whetherthey are assigned for transmission orsubscribed for reception. The aggregated channel status also includes status data from the symbol windowand the network
idle time. The status data is updated (set) after each slot and aggregated until it is reset by the Host.
During startup the status data is not updated. A flag is cleared by writing a ’1’ to the corresponding
bit position. Writing a ’0’ has no effect on the flag. A hard reset will also clear the register.
Bit31302928272625242322212019181716
ACSR0000000000000000
0x0128 W
Reset0000000000000000
Bit 1514131211109876543210
R0 00
W
Reset0000000000000000
SBVBCIBCEDB SEDB VFRB
000
SBVACIA CEDA SEDA VFRA
VFRAValid Frame Received on Channel A (vSS!ValidFrameA)
One or more valid frames were received on channel A in any static or dynamic slot during the
observation period.
1 = Valid frame(s) received on channel A
0 = No valid frame received
SEDASyntax Error Detected on Channel A (vSS!SyntaxErrorA)
One or more syntax errors in static or dynamic slots, symbol window, and NIT were observed
on channel A.
1 = Syntax error(s) observed on channel A
0 = No syntax error observed
CEDAContent Error Detected on Channel A (vSS!ContentErrorA)
One or more frames with a content error were received on channel A in any static or dynamic
slot during the observation period.
1 = Frame(s) with content error received on channel A
0 = No frame with content error received
CIACommunication Indicator Channel A
One or more valid frames were received on channel A in slots that also contained any additional
communication during the observation period, i.e. one or more slots received a valid frame
AND had any combination of either syntax error OR content error OR slot boundary violation.
manual_programmers_model.fm
1 = Valid frame(s) received on channel A in slots containing any additional communication
0 = No valid frame(s) received in slots containing any additional communication
SBVASlot Boundary Violation on Channel A (vSS!BViolationA)
One or more slot boundary violations were observed on channel A at any time during the observation period (static or dynamic slots, symbol window, and NIT).
1 = Slot boundary violation(s) observed on channel A
0 = No slot boundary violation observed
-66/165-
15.12.2006
Page 67
User’s Manual
Revision 1.2.5 E-Ray
VFRBValid Frame Received on Channel B (vSS!ValidFrameB)
One or more valid frames were received on channel B in any static or dynamic slot during the
observation period. Reset under control of the Host.
1 = Valid frame(s) received on channel B
0 = No valid frame received
SEDBSyntax Error Detected on Channel B (vSS!SyntaxErrorB)
One or more syntax errors in static or dynamic slots, symbol window, and NIT were observed
on channel B.
1 = Syntax error(s) observed on channel B
0 = No syntax error observed
CEDBContent Error Detected on Channel B (vSS!ContentErrorB)
One or more frames with a content error were received on channel B in any static or dynamic
slot during the observation period.
1 = Frame(s) with content error received on channel B
0 = No frame with content error received
CIBCommunication Indicator Channel B
One or more valid frames were received on channel B in slots that also contained any additional
communication during the observation period, i.e. one or more slots received a valid frame
AND had any combination of either syntax error OR content error OR slot boundary violation.
1 = Valid frame(s) received on channel B in slots containing any additional communication
0 = No valid frame(s) received in slots containing any additional communication
SBVBSlot Boundary Violation on Channel B (vSS!BViolationB)
One or more slot boundary violations were observed on channel B at any time during the observation period (static or dynamic slots, symbol window, and NIT).
1 = Slot boundary violation(s) observed on channel B
0 = No slot boundary violation observed
Note: The set condition of flags CIA and CIB is also fulfilled if there is only one single frame in the
slot and the slot boundary at the end of the slot is reached during the frames channel idle recognition phase.
When one of the flags SEDB, CEDB, CIB, SBVB changes from ‘0‘ to ‘1‘, interrupt flag
EIR.EDB is set to ’1’.When one of the flags SEDA, CEDA, CIA, SBVA changes from ‘0‘
to ‘1‘, interrupt flag EIR.EDA is set to ’1’.
manual_programmers_model.fm
-67/165-
15.12.2006
Page 68
User’s Manual
Revision 1.2.5 E-Ray
4.6.10 Even Sync ID [1…15] (ESIDn)
Registers ESID1 to ESID15 hold the frame IDs of the sync frames received in even communication
cycles, sorted in ascending order, with register ESID1 holding the lowest received sync frame ID. If
the node itself transmits a sync frame in an even communication cycle, register ESID1 holds the respective sync frame ID as configured in message buffer 0 and flags RXEA, RXEB are set. The value
is updated during the NIT of each even communication cycle.
Bit31302928272625242322212019181716
ESIDn R0000000000000000
0x0130 -
W
0x0168
Reset0000000000000000
Bit 1514131211109876543210
R RXEB RXEA0000EID9EID8EID7EID6EID5EID4EID3EID2EID1EID0
W
Reset0000000000000000
EID[9:0]Even Sync ID (vsSyncIDListA,B even)
Sync frame ID even communication cycle.
RXEAReceived / Configured Even Sync ID on Channel A
Signals that a sync frame corresponding to the stored even sync ID was received on channel A or
that the node is configured to be a sync node with key slot = EID[9:0] (ESID1 only).
1 = Sync frame received on channel A / node configured to transmit sync frames
0 = No sync frame received on channel A / node not configured to transmit sync frames
RXEBReceived / Configured Even Sync ID on Channel B
Signals that a sync frame corresponding to the stored even sync ID was received on channel B or
that the node is configured to be a sync node with key slot = EID[9:0] (ESID1 only).
1 = Sync frame received on channel B / node configured to transmit sync frames
0 = No sync frame received on channel B / node not configured to transmit sync frames
manual_programmers_model.fm
-68/165-
15.12.2006
Page 69
User’s Manual
Revision 1.2.5 E-Ray
4.6.11 Odd Sync ID [1…15] (OSIDn)
Registers OSID1 to OSID15 hold the frame IDs of the sync frames received in odd communication
cycles, sorted in ascending order, with register OSID1 holding the lowest received sync frame ID. If
the node itself transmits a sync frame in an odd communication cycle, register OSID1 holds the respective sync frame ID as configured in message buffer 0 and flags RXOA,RXOB are set. The value
is updated during the NIT of each odd communication cycle.
Signals that a sync frame corresponding to the stored odd sync ID was received on channel A or
that the node is configured to be a sync node with key slot = OID[9:0] (OSID1 only).
1 = Sync frame received on channel A / node configured to transmit sync frames
0 = No sync frame received on channel A / node not configured to transmit sync frames
RXOBReceived / Configured Odd Sync ID on Channel B
Signals that a sync frame corresponding to the stored odd sync ID was received on channel B or
that the node is configured to be a sync node with key slot = OID[9:0] (OSID1 only).
1 = Sync frame received on channel B / node configured to transmit sync frames
0 = No sync frame received on channel B / node not configured to transmit sync frames
manual_programmers_model.fm
-69/165-
15.12.2006
Page 70
User’s Manual
Revision 1.2.5 E-Ray
4.6.12 Network Management Vector [1…3] (NMVn)
The three network management registers hold the accrued NM vector (configurable 0 to 12 bytes).
The accrued NM vector is generated by the CC by bit-wise ORing each NM vector received (valid
static frames with PPI = ’1’) on each channel (see 5.6 Network Management).
The CC updates the NM vector at the end of each communication cycle as long as the CC is either in
NORMAL_ACTIVE or NORMAL_PASSIVE state.
NMVn-bytes exceeding the configured NM vector length are not valid.
Table 4: Assignment of data bytes to network management vector
manual_programmers_model.fm
-70/165-
15.12.2006
Page 71
User’s Manual
Revision 1.2.5 E-Ray
4.7 Message Buffer Control Registers
4.7.1 Message RAM Configuration (MRC)
The Message RAM Configuration registerdefines the number of messagebuffers assigned to the static segment, dynamic segment, and FIFO. The register can be written during DEFAULT_CONFIG or
CONFIG state only.
1…127 = Message buffers from FFB to LCB assigned to the FIFO
≥128 = No message buffer assigned to the FIFO
LCB[7:0]Last Configured Buffer
0…127 = Number of message buffers is LCB + 1
≥128 = No message buffer configured
SEC[1:0]Secure Buffers
Not evaluated when the CC is in DEFAULT_CONFIG or CONFIG state.
00 = Reconfiguration of message buffers enabled with numbers < FFB enabled
Exception: In nodes configured for sync frame transmission or for single slot mode opera-
tion message buffer 0 (and if SPLM = ’1’, also message buffer 1) is always
locked
01 = Reconfiguration of message buffers with numbers < FDB and with numbers ≥ FFB locked
and transmission of message buffers for static segment with numbers ≥ FDB disabled
10 = Reconfiguration of all message buffers locked
manual_programmers_model.fm
11 = Reconfiguration of all message buffers locked
and transmission of message buffers for static segment with numbers ≥ FDB disabled
SPLMSync Frame Payload Multiplex
This bit is only evaluated if the node is configured as sync node (SUCC1.TXSY = ’1’) or for
single slot mode operation (SUCC1.TSM = ’1’). When this bit is set to ’1’ message buffers 0
and 1 are dedicated for sync frame transmission with different payload data on channel A and B.
When this bit is set to ’0’, sync frames are transmitted from message buffer0 with the same payload data on both channels. Note that the channel filter configuration for message buffer 0 resp.
message buffer 1 has to be chosen accordingly.
1 = Both message buffers 0 and 1 are locked against reconfiguration
0 = Only message buffer 0 locked against reconfiguration
-71/165-
15.12.2006
Page 72
User’s Manual
Revision 1.2.5 E-Ray
Note: In case the node is configured as sync node (SUCC1.TXSY = ’1’) or for single slot mode op-
eration (SUCC1.TSM = ’1’), message buffer 0 resp. 1 is reserved for sync frames or single
slot frames and have to be configured with the node-specific key slot ID. In case the node is
neither configured as sync nodenor for single slot operationmessage buffer 0 resp. 1is treated
like all other message buffers.
The programmer has to ensure that the configuration defined by FDB[7:0], FFB[7:0], and LCB[7:0]
is valid. The CC does not check for erroneous configurations!
Note: Themaximum number of header sections is 128. This means a maximum of 128 message buff-
ers can be configured. The maximum length of a data section is 254 bytes. The length of the
data section may be configured differently for each message buffer. For details see Section
5.12 Message RAM.
In case two or more messagebuffers are assigned to slot 1 by use of cycle filtering, all of them
must be located either in the "Static Buffers" or at the beginning of the "Static + Dynamic
Buffers" section.
The payload length configured and the length of the data section need to be configured identical for all message buffers belonging to the FIFO via WRHS2.PLC[6:0] and
WRHS3.DP[10:0]. When the CC is not in DEFAULT_CONFIGor CONFIG state reconfiguration of message buffers belonging to the FIFO is locked.
manual_programmers_model.fm
-72/165-
15.12.2006
Page 73
User’s Manual
Revision 1.2.5 E-Ray
4.7.2 FIFO Rejection Filter (FRF)
The FIFO Rejection Filter defines a user specified sequence of bits to which channel, frame ID, and
cycle count of the incoming frames are compared. Together with the FIFO Rejection Filter Mask this
register determines whether a message is rejectedby theFIFO. The FRF register can be written during
DEFAULT_CONFIG or CONFIG state only.
11 = no reception
10 = receive only on channel A
01 = receive only on channel B
00 = receive on both channels
Note: If reception on both channels is configured, also in static segment always both frames (from
channel A and B) are stored in the FIFO, even if they are identical.
FID[10:0]Frame ID Filter
Determines the frame ID to be rejected by the FIFO. With the additional configuration of register FRFM, the corresponding frame ID filter bits are ignored, which results in further rejected
frame IDs. When FRFM.MFID[10:0] is zero, a frame ID filter value of zero means that no
frame ID is rejected.
0…2047 = Frame ID filter values
CYF[6:0]Cycle Counter Filter
The 7-bit cycle counter filter determines the cycle set to which frame ID and channel rejection
filter are applied. In cycles not belonging to the cycle set specified by CYF[6:0], all frames are
rejected. For details about the configuration of the cycle counter filter see Section 5.7.2 Cycle
Counter Filtering.
RSSReject in Static Segment
If this bit is set, the FIFO is used only for the dynamic segment.
manual_programmers_model.fm
1 = Reject messages in static segment
0 = FIFO also used for static segment
RNFReject Null Frames
If this bit is set, received null frames are not stored in the FIFO.
1 = Reject all null frames
0 = Null frames are stored in the FIFO
-73/165-
15.12.2006
Page 74
User’s Manual
Revision 1.2.5 E-Ray
4.7.3 FIFO Rejection Filter Mask (FRFM)
The FIFO Rejection Filter Mask specifies which of the corresponding frame ID filter bits are relevant
for rejection filtering. If a bit is set, it indicates that the corresponding bit in the FRF register will not
be considered for rejection filtering. The FRFM register can be written during DEFAULT_CONFIG
or CONFIG state only.
1 = Ignore corresponding frame ID filter bit.
0 = Corresponding frame ID filter bit is used for rejection filtering
4.7.4 FIFO Critical Level (FCL)
The CC accepts modifications of the register in DEFAULT_CONFIG or CONFIG state only.
Bit31302928272625242322212019181716
FCLR0000000000000000
0x030C W
Reset0000000000000000
Bit 1514131211109876543210
R00000000
W
Reset0000000010000000
CL7* CL6* CL5* CL4* CL3* CL2* CL1* CL0*
CL[7:0]Critical Level
When the receive FIFO fill level FSR.RFFL[7:0] is equal or greater than the critical level configured by CL[7:0], the receive FIFO critical level flag FSR.RFCL is set. If CL[7:0] is programmed to values > 128, bit FSR.RFCL is never set. When FSR.RFCL changes from ’0’ to
’1’ bit SIR.RFCL is set to ’1’, and if enabled, an interrupt is generated.
A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect on the
flag. The register will also be cleared by hard reset or by CHI command CLEAR_RAMS.
PIBFParity Error Input Buffer RAM 1,2
1 = Parity error occurred when reading Input Buffer RAM 1,2
0 = No parity error
MFMB FMBD PTBF2 PTBF1 PMR POBF PIBF
POBFParity Error Output Buffer RAM 1,2
1 = Parity error occurred when reading Output Buffer RAM 1,2
0 = No parity error
PMRParity Error Message RAM
1 = Parity error occurred when reading the Message RAM
0 = No parity error
PTBF1Parity Error Transient Buffer RAM A
1 = Parity error occurred when reading Transient Buffer RAM A
0 = No parity error
PTBF2Parity Error Transient Buffer RAM B
1 = Parity error occurred when reading Transient Buffer RAM B
0 = No parity error
Note: When one of the flags PIBF, POBF, PMR, PTBF1, PTBF2 changes from ’0’ to ’1’
EIR.PERR is set to ’1’.
FMBDFaulty Message Buffer Detected
1 = Message buffer referenced by FMB[6:0] holds faulty data due to a parity error
manual_programmers_model.fm
0 = No faulty message buffer
MFMBMultiple Faulty Message Buffers detected
1 = Another faulty message buffer was detected while flag FMBD is set
0 = No additional faulty message buffer
CRAMClear all internal RAM’s
Signals that execution of the CHI command CLEAR_RAMS is ongoing (all bits of all internal
RAM blocks are written to ’0’). The bit is set by hard reset or by CHI command
CLEAR_RAMS.
1 = Execution of the CHI command CLEAR_RAMS ongoing
0 = No execution of the CHI command CLEAR_RAMS
-75/165-
15.12.2006
Page 76
User’s Manual
Revision 1.2.5 E-Ray
FMB[6:0]Faulty Message Buffer
Parity error occurred when reading from the message buffer or when transferring data from
Input Buffer or Transient Buffer 1,2 to the message buffer referenced by FMB[6:0]. Value only
valid when one of the flags PIBF, PMR, PTBF1, PTBF2, and flag FMBD is set. Updated only
after the Host has reset flag FMBD.
MBT[6:0]Message Buffer Transmitted
Number of last successfully transmitted message buffer. If the message buffer is configured for
single-shot mode, the respective TXR flag in the TXRQ1/2/3/4 registers was reset.
MBU[6:0]Message Buffer Updated
Number of message buffer that was updated last by the CC. For this message buffer the
respective ND and / or MBC flag in the NDAT1/2/3/4 registers and the MBSC1/2/3/4 registers
are also set.
Note: MBT[6:0] and MBU[6:0] are reset when the CC leaves CONFIG state or enters STARTUP
The register is reset when the CC leaves CONFIG state or enters STARTUP state.
LDTA[10:0]Last Dynamic Transmission Channel A
Value of vSlotCounter[A] at the time of the last frame transmission on channel A in the dynamic
segment of this node. It is updated at the end of the dynamic segment and is reset to zero if no
frame was transmitted during the dynamic segment.
LDTB[10:0]Last Dynamic Transmission Channel B
Value of vSlotCounter[B] at the time of the last frame transmission on channel B in the dynamic
segment of this node. It is updated at the end of the dynamic segment and is reset to zero if no
frame was transmitted during the dynamic segment.
manual_programmers_model.fm
-76/165-
15.12.2006
Page 77
User’s Manual
Revision 1.2.5 E-Ray
4.8.3 FIFO Status Register (FSR)
Bit31302928272625242322212019181716
FSRR00000
0x0318 W
Reset0000000000000000
Bit 1514131211109876543210
R RFFL7 RFFL6 RFFL5 RFFL4 RFFL3 RFFL2 RFFL1 RFFL000000RFORFCL RFNE
W
Reset0000000000000000
0
0000000000
The register is reset when the CC leaves CONFIG state or enters STARTUP state.
RFNEReceive FIFO Not Empty
This flag is set by the CC when a received valid frame (data or null frame depending on rejection
mask) was stored in the FIFO. In addition, interrupt flag SIR.RFNE is set. The bit is reset after
the Host has read all message from the FIFO.
1 = Receive FIFO is not empty
0 = Receive FIFO is empty
RFCLReceive FIFO Critical Level
This flag is set when the receive FIFO fill level RFFL[7:0] is equal or greater than the critical
level as configured by FCL.CL[7:0]. The flag is cleared by the CC as soon as RFFL[7:0] drops
below FCL.CL[7:0]. When RFCL changes from ’0’ to ’1’ bit SIR.RFCL is set to ’1’, and if
enabled, an interrupt is generated.
The flag is set by the CC when a receive FIFO overrun is detected. When a receive FIFO overrun
occurs, the oldest message is overwritten with the actual received message. In addition, interrupt
flag EIR.RFO is set.The flag is cleared by the next FIFO read access issued by the Host.
1 = A receive FIFO overrun has been detected
0 = No receive FIFO overrun detected
RFFL[7:0]Receive FIFO Fill Level
Number of FIFO buffers filled with new data not yet read by the Host. Maximum value is 128.
manual_programmers_model.fm
-77/165-
15.12.2006
Page 78
User’s Manual
Revision 1.2.5 E-Ray
4.8.4 Message Handler Constraints Flags (MHDF)
Some constraints exist for the Message Handler regarding eray_bclk frequency, Message RAM configuration, and FlexRay bus traffic (see Addendum to E-Ray FlexRay IP-Module Specification). To
simplify software development, constraints violations are reported by setting flags in the MHDF.
Bit31302928272625242322212019181716
MHDF R0000000000000000
0x031C W
Reset0000000000000000
Bit 1514131211109876543210
R0000000
W
Reset0000000000000000
WAHP
00
TBFB TBFA FNFB FNFA SNUB SNUA
A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect on the
flag. A hard reset will also clear the register. The register is reset when the CC leaves CONFIG state
or enters STARTUP state.
SNUAStatus Not Updated Channel A
This flag is set by the CC when the Message Handler, due to overload condition, was not able to
update a message buffer’s status MBS with respect to channel A.
1 = MBS for channel A not updated
0 = No overload condition occurred when updating MBS for channel A
SNUBStatus Not Updated Channel B
This flag is set by the CC when the Message Handler, due to overload condition, was not able to
update a message buffer’s status MBS with respect to channel B.
1 = MBS for channel B not updated
0 = No overload condition occurred when updating MBS for channel B
FNFAFind Sequence Not Finished Channel A
This flag is set by the CC when the Message Handler, due to overload condition, was not able to
finish a find sequence (scan of Message RAM for matching message buffer) with respect to
channel A.
1 = Find sequence not finished for channel A
0 = No find sequence not finished for channel A
FNFBFind Sequence Not Finished Channel B
This flag is set by the CC when the Message Handler, due to overload condition, was not able to
manual_programmers_model.fm
finish a find sequence (scan of Message RAM for matching message buffer) with respect to
channel B.
1 = Find sequence not finished for channel B
0 = No find sequence not finished for channel B
TBFATransient Buffer Access Failure A
This flag is set by the CC when a read or write access to TBF A requested by PRT A could not
complete within the available time.
1 = TBF A access failure
0 = No TBF A access failure
-78/165-
15.12.2006
Page 79
User’s Manual
Revision 1.2.5 E-Ray
TBFBTransient Buffer Access Failure B
This flag is set by the CC when a read or write access to TBF B requested by PRT B could not
complete within the available time.
1 = TBF B access failure
0 = No TBF B access failure
WAHPWrite Attempt to Header Partition
Outside DEFAULT_CONFIG and CONFIG state this flag is set by the CC when the message
handler tries to write message data into the header partition of the Message RAM due to faulty
configuration of a message buffer. The write attempt is not executed, to protect the header partition from unintended write accesses.
1 = Write attempt to header partition
0 = No write attempt to header partition
Note: When one of the flags SNUA, SNUB, FNFA, FNFB, TBFA, TBFB, WAHP changes from
’0’ to ’1’, interrupt flag EIR.MHF is set to ’1’.
manual_programmers_model.fm
-79/165-
15.12.2006
Page 80
User’s Manual
Revision 1.2.5 E-Ray
4.8.5 Transmission Request 1/2/3/4 (TXRQ1/2/3/4)
The four registers reflect the state of the TXR flags of all configured message buffers. The flags are
evaluated for transmit buffers only. If the number of configured message buffers is less than 128, the
remaining TXR flags have no meaning.
If the flag is set, the respective message buffer is ready for transmission respectively transmission of this message buffer is in progress. In single-shot mode the flags are reset after transmission has completed.
-80/165-
15.12.2006
Page 81
User’s Manual
Revision 1.2.5 E-Ray
4.8.6 New Data 1/2/3/4 (NDAT1/2/3/4)
The four registers reflect thestate of the ND flags ofall configured message buffers. NDflags belonging to transmit buffers haveno meaning. If the numberof configured message buffers isless than 128,
the remaining ND flags have no meaning. The registers are reset when the CC leaves CONFIG state
or enters STARTUP state.
R ND15 ND14 ND13 ND12 ND11 ND10 ND9ND8ND7ND6ND5ND4ND3ND2ND1ND0
W
Reset0000000000000000
ND[127:0]New Data
The flags are set when a valid received data frame matches the message buffer’s filter configuration, independent of the payload length received or the payload length configured for that message buffer. The flags are not set after reception of null frames except for message buffers
belonging to the receive FIFO. An ND flag is reset when the header section of the corresponding
message buffer is reconfigured or when the data section has been transferred to the Output
Buffer.
-81/165-
15.12.2006
Page 82
User’s Manual
Revision 1.2.5 E-Ray
4.8.7 Message Buffer Status Changed 1/2/3/4 (MBSC1/2/3/4)
The four registers reflect the state of the MBC flags of all configured message buffers. If the number
of configured message buffers is less than 128, the remaining MBC flags have no meaning. The registers are reset when the CC leaves CONFIG state or enters STARTUP state.
An MBC flag is set whenever the Message Handler changes one of the status flags VFRA,
VFRB, SEOA, SEOB, CEOA, CEOB, SVOA, SVOB, TCIA, TCIB, ESA, ESB, MLST,
FTA, FTB in the header section (see 4.11.5 Message Buffer Status (MBS) and 5.12.1 Header
Partition, header 4) of the respective message buffer. An MBC flag is reset when the header section of the corresponding message buffer is reconfigured or when it has been transferred to the
Output Buffer.
Double buffer structure consisting of Input Buffer Host and Input Buffer Shadow. While the Host can
write to Input Buffer Host, the transfer to the Message RAM is done from Input Buffer Shadow. The
Input Buffer holds the header and data sections to be transferred to the selected message buffer in the
Message RAM. It is used to configure the message buffers in the Message RAM and to update the
data sections of transmit buffers.
When updating the header section of a message buffer in the Message RAM from the Input Buffer,
the Message Buffer Status as described in Section 4.11.5 Message Buffer Status (MBS) is automatically reset to zero.
The header sections of message buffers belonging to the receive FIFO can only be (re)configured
when the CC is in DEFAULT_CONFIG or CONFIG state. For those message buffers only the payload length configured and the data pointer need to be configured via WRHS2.PLC[6.0] and
WRHS3.DP[10:0]. All information required for acceptance filtering is taken from the FIFO rejection
filter and the FIFO rejection filter mask.
The data transfer between Input Buffer (IBF) and Message RAM is described in detail in Section
5.11.2.1 Data Transfer from Input Buffer to Message RAM.
4.10.1 Write Data Section [1…64] (WRDSn)
Holds the data words to be transferred to the data section of the addressed message buffer. The data
words (DW
DW
PL
Bit31302928272625242322212019181716
WRDSn R
0x0400 -
0x04FC
Reset0000000000000000
Bit 1514131211109876543210
Reset0000000000000000
) are written to the Message RAM in transmission order from DW1(byte0, byte1) to
n
(PL = number of data words as defined by the payload length configured WRHS2.PLC[6:0]).
Note: DW127 is located on WRDS64.MD[15:0]. In this case WRDS64.MD[31:16] is unused (no
valid data). The Input Buffer RAMs are initialized to zero when leaving hard reset or by CHI
command CLEAR_RAMS.
-84/165-
15.12.2006
Page 85
User’s Manual
Revision 1.2.5 E-Ray
4.10.2 Write Header Section 1 (WRHS1)
Bit31302928272625242322212019181716
WRHS1 R00
0x0500 W
Reset0000000000000000
Bit 1514131211109876543210
R00000
W
Reset0000000000000000
MBITXMPPITCFGCHBCHA
FID10 FID9FID8FID7FID6FID5FID4FID3FID2FID1FID0
0
CYC6 CYC5 CYC4 CYC3 CYC2 CYC1 CYC0
FID[10:0]Frame ID
Frame ID of the selected message buffer. The frame ID defines the slot number for transmission
/ reception of the respective message. Message buffers with frame ID = ’0’ are considered as
not valid.
CYC[6:0]Cycle Code
The 7-bit cycle code determines the cycle set used for cycle counter filtering. For details about
the configuration of the cycle code see Section 5.7.2 Cycle Counter Filtering.
CHA, CHBChannel Filter Control
The 2-bit channel filtering field associated with each buffer serves as a filter for receive buffers,
and as a control field for transmit buffers.
CHACHB
11both channels
(static segment only)
10channel Achannel A
01channel Bchannel B
00no transmissionignore frame
Transmit Buffer
transmit frame on
channel A or B
(store first semantically valid frame,
static segment only)
Receive Buffer
store frame received from
Note: Ifa message buffer is configured for the dynamic segment and both bits of thechannel filtering
field are set to ’1’, no frames are transmitted resp. received frames are ignored (same function
as CHA = CHB = ’0’)
CFGMessage Buffer Direction Configuration Bit
This bit is used to configure the corresponding buffer as transmit buffer or as receive buffer. For
message buffers belonging to the receive FIFO the bit is not evaluated.
manual_programmers_model.fm
1 = The corresponding buffer is configured as Transmit Buffer
0 = The corresponding buffer is configured as Receive Buffer
PPITPayload Preamble Indicator Transmit
This bit is used to control the state of the Payload Preamble Indicator in transmit frames. If the
bit is set in a static message buffer, the respective message buffer holds network management
information. If the bit is set in a dynamic message buffer the first two bytes of the payload segment may be used for message ID filtering by the receiver. Message ID filtering of received
FlexRay frames is not supported by the E-Ray module, but can be done by the Host.
1 = Payload Preamble Indicator set
0 = Payload Preamble Indicator not set
-85/165-
15.12.2006
Page 86
User’s Manual
Revision 1.2.5 E-Ray
TXMTransmission Mode
This bit is used to select the transmission mode (see Section 5.8.3 Transmit Buffers).
1 = Single-shot mode
0 = Continuous mode
MBIMessage Buffer Interrupt
This bit enables the receive / transmit interrupt for the corresponding message buffer. After a
dedicated receive buffer has been updated by the Message Handler, flag SIR.RXI and /or
SIR.MBSI are set. After a transmission has completed flag SIR.TXI is set.
1 = The corresponding message buffer interrupt is enabled
0 = The corresponding message buffer interrupt is disabled
Receive Buffer: Configuration not required
Transmit Buffer: Header CRC calculated and configured by the Host
For calculation of the header CRC the payload length of the frame send on the bus has to be con-
sidered. In static segment the payload length of all frames is configured by MHDC.SFDL[6:0].
PLC[6:0]Payload Length Configured
Length of data section (number of 2-byte words) as configured by the Host. During static segment the static frame payload length as configured by MHDC.SFDL[6:0] defines the payload
length for all static frames. If the payload length configured by PLC[6:0] is shorter than this
value padding bytes are inserted to ensure that frames have proper physical length. The padding
pattern is logical zero.
4.10.4 Write Header Section 3 (WRHS3)
Bit31302928272625242322212019181716
manual_programmers_model.fm
WRHS3 R0000000000000000
0x0508 W
Reset0000000000000000
Bit 1514131211109876543210
R00000
W
Reset0000000000000000
DP10DP9DP8DP7DP6DP5DP4DP3DP2DP1DP0
DP[10:0]Data Pointer
Pointer to the first 32-bit word of the data section of the addressed message buffer in the Message RAM.
-86/165-
15.12.2006
Page 87
User’s Manual
Revision 1.2.5 E-Ray
4.10.5 Input Buffer Command Mask (IBCM)
Configures how the message buffer in the Message RAM selected byregister IBCR is updated. When
IBF Host and IBF Shadow are swapped, also mask bits LHSH, LDSH, and STXRH are swapped
with bits LHSS, LDSS, and STXRS to keep them attached to the respective Input Buffer transfer.
Bit31302928272625242322212019181716
IBCM
R0000000000000
0x0510 W
Reset0000000000000000
Bit 1514131211109876543210
R0000000000000
W
Reset0000000000000000
STXRS
STXRH
LDSS LHSS
LDSH LHSH
LHSHLoad Header Section Host
1 = Header section selected for transfer from Input Buffer to the Message RAM
0 = Header section is not updated
LDSHLoad Data Section Host
1 = Data section selected for transfer from Input Buffer to the Message RAM
0 = Data section is not updated
STXRHSet Transmission Request Host
If this bit is set to ’1’, the TXR flag for the selected message buffer is set in the TXRQ1/2/3/4
registers to release the message buffer for transmission. In single-shot mode the flag is cleared
by the CC after transmission has completed. TXR is evaluated for transmit buffers only.
1 = Set TXR flag, transmit buffer released for transmission
0 = Reset TXR flag
LHSSLoad Header Section Shadow
1 = Header section selected for transfer from Input Buffer to the Message RAM
(transfer ongoing or finished)
0 = Header section is not updated
LDSSLoad Data Section Shadow
1 = Data section selected for transfer from Input Buffer to the Message RAM
(transfer ongoing or finished)
0 = Data section is not updated
STXRSSet Transmission Request Shadow
manual_programmers_model.fm
1 = Set TXR flag, transmit buffer released for transmission (operation ongoing or finished)
0 = Reset TXR flag
-87/165-
15.12.2006
Page 88
User’s Manual
Revision 1.2.5 E-Ray
4.10.6 Input Buffer Command Request (IBCR)
When the Host writes the number of the target message buffer in the Message RAM to IBRH[6:0],
IBF Host and IBF Shadow are swapped. In addition the message buffer numbers stored under
IBRH[6:0] and IBRS[6:0] are also swapped (see also Section 5.11.2.1 Data Transfer from Input
Buffer to Message RAM).
With this write operation the IBSYSis set to ’1’. The Message Handler then starts to transfer the contents of IBF Shadow to the message buffer in the Message RAM selected by IBRS[6:0].
While the Message Handler transfers the data from IBF Shadow to the target message buffer in the
Message RAM, the Host may write the next message into the IBF Host. After the transfer between
IBF Shadow and the Message RAM has completed, IBSYS is set back to ’0’ and the next transfer to
the Message RAM may be started by the Host bywriting the respective target message buffer number
to IBRH[6:0].
If a write access to IBRH[6:0] occurs while IBSYS is ’1’, IBSYH is set to ’1’. After completion of
the ongoing data transfer from IBF Shadow to the Message RAM, IBF Host and IBF Shadow are
swapped, IBSYH is reset to ’0’. IBSYS remains set to ’1’, and the next transfer to the Message RAM
is started. In addition the message buffer numbers stored under IBRH[6:0] and IBRS[6:0] are also
swapped.
Any write access to an Input Buffer register whileboth IBSYSand IBSYH are setwill cause the error
flag EIR.IIBA to be set. In this case the Input Buffer will not be changed.
Bit31302928272625242322212019181716
IBCR
R IBSYS00000000IBRS6 IBRS5 IBRS4 IBRS3 IBRS2 IBRS1 IBRS0
0x0514 W
Reset0000000000000000
Bit 1514131211109876543210
R IBSYH00000000
W
Reset0000000000000000
IBRH6 IBRH5 IBRH4 IBRH3 IBRH2 IBRH1 IBRH0
IBRH[6:0] Input Buffer Request Host
Selects the target message buffer in the Message RAM for data transfer from Input Buffer.
Valid values are 0x00 to 0x7F (0…127).
IBSYHInput Buffer Busy Host
Set to ’1’ by writing IBRH[6:0] while IBSYS is still ’1’. After the ongoing transfer between
IBF Shadow and the Message RAM has completed, the IBSYH is set back to ’0’.
manual_programmers_model.fm
1 = Request while transfer between IBF Shadow and Message RAM in progress
0 = No request pending
IBRS[6:0]Input Buffer Request Shadow
Number of the target message buffer actually updated / lately updated.
Valid values are 0x00 to 0x7F (0…127).
IBSYSInput Buffer Busy Shadow
Set to ’1’ after writing IBRH[6:0]. When the transfer between IBF Shadow and the Message
RAM has completed, IBSYS is set back to ’0’.
1 = Transfer between IBF Shadow and Message RAM in progress
0 = Transfer between IBF Shadow and Message RAM completed
-88/165-
15.12.2006
Page 89
User’s Manual
Revision 1.2.5 E-Ray
4.11 Output Buffer
Double buffer structure consisting of Output Buffer Host and Output Buffer Shadow. Used to read
out message buffers from the Message RAM. While the Host can read from Output Buffer Host, the
Message Handler transfers the selected message buffer from Message RAM to Output Buffer Shadow. The data transfer between Message RAM and Output Buffer (OBF) is described in Section
5.11.2.2 Data Transfer from Message RAM to Output Buffer.
4.11.1 Read Data Section [1…64] (RDDSn)
Holds the data words read from the data section of the addressed message buffer. The data words
) are read from the Message RAM in reception order from DW1(byte0, byte1) to DWPL(PL =
(DW
n
number of data words as defined by the payload length configured RDHS2.PLC[6:0]).
FID[10:0]Frame ID
CYC[6:0]Cycle Code
CHA, CHBChannel Filter Control
CFGMessage Buffer Direction Configuration Bit
PPITPayload Preamble Indicator Transmit
TXMTransmission Mode
MBIMessage Buffer Interrupt
In case that the message buffer read from the Message RAM belongs to the receive FIFO, FID[10:0]
holds the received frame ID, while CYC[6:0], CHA, CHB, CFG, PPIT, TXM, and MBI are reset to
’0’.
Receive Buffer: Header CRC updated from received data frames
Transmit Buffer: Header CRC calculated and configured by the Host
PLC[6:0]Payload Length Configured
Length of data section (number of 2-byte words) as configured by the Host.
PLR[6:0]Payload Length Received (vRF!Header!Length)
Payload length value updated from received data frames (exception: if message buffer belongs
to the receive FIFO PLR[6:0] is also updated from received null frames)
When a message is stored into a message buffer the following behaviour with respect to payload
length received and payload length configured is implemented:
PLR[6:0] > PLC[6:0]: The payload data stored in the message buffer is truncated to the payload
length configured if PLC[6:0] even or else truncated to PLC[6:0] + 1.
PLR[6:0] ≤ PLC[6:0]: The received payload data is stored into the message buffers data section.
The remaining data bytes of the data section as configured by PLC[6:0]
are filled with undefined data
PLR[6:0] = zero:The message buffer’s data section is filled with undefined data
PLC[6:0] = zero:Message buffer has no data section configured. No data is stored into the
message buffer’s data section.
Note: The Message RAM is organized in 4-byte words. When received data is stored into a message
buffer’s data section, the number of 2-byte data words written into the message buffer is
PLC[6:0] rounded to the next even value. PLC[6:0] should be configured identical for all
message buffers belonging to the receive FIFO. Header 2 is updated from data frames only.
A startup frame is marked by the startup frame indicator.
1 = The received frame is a startup frame
0 = The received frame is not a startup frame
SYNSync Frame Indicator (vRF!Header!SyFIndicator)
A sync frame is marked by the sync frame indicator.
1 = The received frame is a sync frame
0 = The received frame is not a sync frame
NFINull Frame Indicator (vRF!Header!NFIndicator)
Is set to ’1’ after storage of the first received data frame.
1 = At least one data frame has been stored into the respective message buffer
0 = Up to now no data frame has been stored into the respective message buffer
The payload preamble indicator defines whether a network management vector or message ID is
manual_programmers_model.fm
contained within the payload segment of the received frame.
1 = Static segment:Network management vector in the first part of the payload
Dynamic segment:Message ID in the first part of the payload
0 = The payload segment of the received frame does not contain a network management vector
nor a message ID
RESReserved Bit (vRF!Header!Reserved)
Reflects the state of the received reserved bit. The reserved bit is transmitted as ’0’.
Note: Header 3 is updated from data frames only.
-92/165-
15.12.2006
Page 93
User’s Manual
Revision 1.2.5 E-Ray
4.11.5 Message Buffer Status (MBS)
The message buffer status is updated by the CC with respect to the assigned channel(s) latest at the
end of the slot following the slot assigned to the message buffer. The flags are updated only when the
CC is in NORMAL_ACTIVEor NORMAL_PASSIVE state. If only one channel (A orB) is assigned
to a message buffer, the channel-specific status flags of the other channel are written to zero. If both
channels are assigned to a message buffer, the channel-specific status flags of both channels are
updated. The message buffer status is updated only when the slot counter reached the configured
frame ID and when the cycle counter filter matched. When the Host updates a message buffer via
Input Buffer, all MBS flags are reset to zeroindependent of whichIBCM bitsare set ornot. Fordetails
about receive / transmit filtering see Sections 5.7 Filtering and Masking, 5.8 Transmit Process, and
5.9 Receive Process. Whenever the Message Handler changes oneof the flagsVFRA, VFRB, SEOA,
SEOB, CEOA, CEOB, SVOA,SVOB, TCIA, TCIB, ESA,ESB, MLST, FTA, FTB the respective
message buffer’s MBC flag in registers MBSC1/2/3/4 is set.
VFRAValid Frame Received on Channel A (vSS!ValidFrameA)
A valid frame indication is set if a valid frame was received on channel A.
1 = Valid frame received on channel A
0 = No valid frame received on channel A
VFRBValid Frame Received on Channel B (vSS!ValidFrameB)
A valid frame indication is set if a valid frame was received on channel B.
1 = Valid frame received on channel B
0 = No valid frame received on channel B
SEOASyntax Error Observed on Channel A (vSS!SyntaxErrorA)
A syntax error was observed in the assigned slot on channel A.
1 = Syntax error observed on channel A
0 = No syntax error observed on channel A
SEOBSyntax Error Observed on Channel B (vSS!SyntaxErrorB)
manual_programmers_model.fm
A syntax error was observed in the assigned slot on channel B.
1 = Syntax error observed on channel B
0 = No syntax error observed on channel B
CEOAContent Error Observed on Channel A (vSS!ContentErrorA)
A content error was observed in the assigned slot on channel A.
1 = Content error observed on channel A
0 = No content error observed on channel A
CEOBContent Error Observed on Channel B (vSS!ContentErrorB)
A content error was observed in the assigned slot on channel B.
1 = Content error observed on channel B
0 = No content error observed on channel B
-93/165-
15.12.2006
Page 94
User’s Manual
Revision 1.2.5 E-Ray
SVOASlot Boundary Violation Observed on Channel A (vSS!BViolationA)
A slot boundary violation (channel active at the start or at the end of the assigned slot) was
observed on channel A.
1 = Slot boundary violation observed on channel A
0 = No slot boundary violation observed on channel A
SVOBSlot Boundary Violation Observed on Channel B (vSS!BViolationB)
A slot boundary violation (channel active at the start or at the end of the assigned slot) was
observed on channel B.
1 = Slot boundary violation observed on channel B
0 = No slot boundary violation observed on channel B
TCIATransmission Conflict Indication Channel A (vSS!TxConflictA)
A transmission conflict indication is set if a transmission conflict has occurred on channel A.
1 = Transmission conflict occurred on channel A
0 = No transmission conflict occurred on channel A
TCIBTransmission Conflict Indication Channel B (vSS!TxConflictB)
A transmission conflict indication is set if a transmission conflict has occurred on channel B.
1 = Transmission conflict occurred on channel B
0 = No transmission conflict occurred on channel B
ESAEmpty Slot Channel A
In an empty slot there is no activity detected on the bus. The condition is checked in static and
dynamic slots.
1 = No bus activity detected in the assigned slot on channel A
0 = Bus activity detected in the assigned slot on channel A
ESBEmpty Slot Channel B
In an empty slot there is no activity detected on the bus. The condition is checked in static and
dynamic slots.
1 = No bus activity detected in the assigned slot on channel B
0 = Bus activity detected in the assigned slot on channel B
MLSTMessage Lost
The flag is set in case the Host did not read the message before the message buffer was updated
from a received data frame. Not affected by reception of null frames except for message buffers
belonging to the receive FIFO. The flag is reset by a Host write to the message buffer via IBF or
when a new message is stored into the message buffer after the message buffers ND flag was
reset by reading out the message buffer via OBF.
manual_programmers_model.fm
1 = Unprocessed message was overwritten
0 = No message lost
FTAFrame Transmitted on Channel A
Indicates that this node has transmitted a data frame in the configured slot on channel A.
1 = Data frame transmitted on channel A
0 = No data frame transmitted on channel A
FTBFrame Transmitted on Channel B
Indicates that this node has transmitted a data frame in the configured slot on channel B.
1 = Data frame transmitted on channel B
0 = No data frame transmitted on channel B
-94/165-
15.12.2006
Page 95
User’s Manual
Revision 1.2.5 E-Ray
Note: The FlexRay protocol specification requires that FTA, and FTBcan only be reset by the Host.
Therefore the Cycle Count Status CCS[5:0] for these bits is only valid for the cycle where the
bits are set to ’1’.
CCS[5:0]Cycle Count Status
Actual cycle count when status was updated.
For receive buffers (CFG = ’0’) the following status bits are updated from both valid data and null
frames. If no valid frame was received,the previous value is maintained. For transmit buffersthe flags
have no meaning and should be ignored.
RCISReceived on Channel Indicator Status (vSS!Channel)
Indicates the channel on which the frame was received.
1 = Frame received on channel A
0 = Frame received on channel B
SFISStartup Frame Indicator Status (vRF!Header!SuFIndicator)
A startup frame is marked by the startup frame indicator.
1 = The received frame is a startup frame
0 = No startup frame received
SYNSSync Frame Indicator Status (vRF!Header!SyFIndicator)
A sync frame is marked by the sync frame indicator.
1 = The received frame is a sync frame
0 = No sync frame received
NFISNull Frame Indicator Status (vRF!Header!NFIndicator)
If set to ’0’ the payload segment of the received frame contains no usable data.
1 = Received frame is not a null frame
0 = Received frame is a null frame
PPISPayload Preamble Indicator Status (vRF!Header!PPIndicator)
The payload preamble indicator defines whether a network management vector or message ID is
contained within the payload segment of the received frame.
1 = Static segment: Network management vector at the beginning of the payload
Dynamic segment: Message ID at the beginning of the payload
0 = The payload segment of the received frame does not contain a network management vector
or a message ID
RESSReserved Bit Status (vRF!Header!Reserved)
Reflects the state of the received reserved bit. The reserved bit is transmitted as ’0’.
manual_programmers_model.fm
-95/165-
15.12.2006
Page 96
User’s Manual
Revision 1.2.5 E-Ray
4.11.6 Output Buffer Command Mask (OBCM)
Configures how the Output Buffer is updated from the message buffer in the Message RAM selected
by register OBCR. When OBF Hostand OBFShadow are swapped, also mask bits RDSHand RHSH
are swapped with bits RDSS and RHSS to keep them attached to the respective Output Buffer transfer.
Bit31302928272625242322212019181716
OBCM
R00000000000000RDSH RHSH
0x0710 W
Reset0000000000000000
Bit 1514131211109876543210
R00000000000000
W
Reset0000000000000000
RDSS RHSS
RHSSRead Header Section Shadow
1 = Header section selected for transfer from Message RAM to Output Buffer
0 = Header section is not read
RDSSRead Data Section Shadow
1 = Data section selected for transfer from Message RAM to Output Buffer
0 = Data section is not read
RHSHRead Header Section Host
1 = Header section selected for transfer from Message RAM to Output Buffer
0 = Header section is not read
RDSHRead Data Section Host
1 = Data section selected for transfer from Message RAM to Output Buffer
0 = Data section is not read
Note: After the transfer of the header section from the Message RAM to OBF Shadow has complet-
ed, the message buffer status changed flag MBC of the selected message buffer in the
MBSC1/2/3/4 registers is cleared. After the transfer of the data section from the Message
RAM to OBF Shadow has completed, the new data flag ND of the selected message buffer in
the NDAT1/2/3/4 registers is cleared.
manual_programmers_model.fm
-96/165-
15.12.2006
Page 97
User’s Manual
Revision 1.2.5 E-Ray
4.11.7 Output Buffer Command Request (OBCR)
The message buffer selected by OBRS[6:0] istransferred from the Message RAM to the OutputBuffer as soon as the Host has set REQ to ’1’. Bit REQ can only be set to ’1’ while OBSYS is ’0’ (see
also Section 5.11.2.2 Data Transfer from Message RAM to Output Buffer).
After setting REQ to ’1’, OBSYS is automatically set to ’1’, and the transfer of the message buffer
selected by OBRS[6:0] from the Message RAM to OBF Shadow is started. When the transfer between the Message RAM and OBF Shadow has completed, this is signalled by setting OBSYS back
to ’0’. By setting the VIEW bit to ’1’ while OBSYS is ’0’, OBF Host and OBF Shadow are swapped.
Now the Host can read the transferred message buffer from OBF Host. In parallel the Message Handler may transfer the next message from the Message RAM to OBF Shadow if VIEW and REQ are
set at the same time.
Any write access to an OutputBuffer registerwhile OBSYS is set will cause theerror flagEIR.IOBA
to be set. In this case the Output Buffer will not be changed.
Bit31302928272625242322212019181716
OBCR
R000000000OBRH6
0x0714 W
Reset0000000000000000
OBRH5 OBRH4 OBRH3 OBRH2 OBRH1 OBRH0
Bit 1514131211109876543210
OBSYS
R
W
Reset0000000000000000
00000
REQ VIEW
0
OBRS6 OBRS5 OBRS4 OBRS3 OBRS2 OBRS1 OBRS0
OBRS[6:0] Output Buffer Request Shadow
Number of source message buffer to be transferred from the Message RAM to OBF Shadow.
Valid values are 0x00 to 0x7F (0…127). If the number of the first message buffer of the receive
FIFO is written to this register the Message Handler transfers the message buffer addressed by
the GET Index (GIDX, see Section 5.10 FIFO Function) to OBF Shadow.
VIEWView Shadow Buffer
Toggles between OBF Shadow and OBF Host. Only writeable while OBSYS = ’0’.
1 = Swap OBF Shadow and OBF Host
0 = No action
REQRequest Message RAM Transfer
Requests transfer of message buffer addressed by OBRS[6:0] from Message RAM to OBF
Shadow. Only writeable while OBSYS = ’0’.
manual_programmers_model.fm
1 = Transfer to OBF Shadow requested
0 = No request
OBSYSOutput Buffer Busy Shadow
Set to ’1’ after setting bit REQ. When the transfer between the Message RAM and OBF
Shadow has completed, OBSYS is set back to ’0’.
1 = Transfer between Message RAM and OBF Shadow in progress
0 = No transfer in progress
OBRH[6:0] Output Buffer Request Host
Number of message buffer currently accessible by the Host via RDHS[1…3], MBS, and
RDDS[1…64]. By writing VIEW to ’1’ OBF Shadow and OBF Host are swapped and the transferred message buffer is accessible by the Host. Valid values are 0x00 to 0x7F (0…127).
-97/165-
15.12.2006
Page 98
User’s Manual
Revision 1.2.5 E-Ray
5. Functional Description
This chapter describes the E-Ray implementation togetherwith the related FlexRay protocol features.
More information about the FlexRay protocol itself can be found in the FlexRay protocol specification v2.1.
Communication on FlexRay networks is based on frames and symbols. The wakeup symbol (WUS)
and the collision avoidance symbol (CAS) are transmitted outside the communication cycle to setup
the time schedule. Frames and media access test symbols (MTS) are transmitted inside the communication cycle.
5.1 Communication Cycle
A FlexRay communication cycle consists of the following elements:
• Static Segment
• Dynamic Segment (optional)
• Symbol Window (optional)
• Network Idle Time (NIT)
Static segment, dynamic segment, and symbol window form the Network Communication Time
(NCT). For each communication channel the slot counter starts at 1 and counts up until the end of the
dynamic segment is reached. Both channels share the same arbitration grid which means that they use
the same synchronized macrotick.
time base
derived trigger
static segmentdynamic segment
communication
cycle x-1
manual_functional_description.fm
Figure 2: Structure of communication cycle
symbol
window
communication cycle x
time base
derived trigger
t
NIT
communication
cycle x+1
5.1.1 Static Segment
The Static Segment is characterized by the following features:
• Time slots of fixed length (optionally protected by bus guardian)
• Start of frame transmission at action point of the respective static slot
• Payload length same for all frames on both channels
Parameters: Number of Static Slots GTUC7.NSS[9:0], Static Slot Length GTUC7.SSL[9:0],
Payload Length Static MHDC.SFDL[6:0], Action Point Offset GTUC9.APO[5:0]
-98/165-
15.12.2006
Page 99
User’s Manual
Revision 1.2.5 E-Ray
5.1.2 Dynamic Segment
The Dynamic Segment is characterized by the following features:
• All controllers have bus access (no bus guardian protection possible)
• Variable payload length and duration of slots, different for both channels
• Start of transmission at minislot action point
Parameters: Number of Minislots GTUC8.NMS[12:0], Minislot Length GTUC8.MSL[5:0],
Minislot Action Point Offset GTUC9.MAPO[4:0],
Start of Latest Transmit (last minislot) MHDC.SLT[12:0]
5.1.3 Symbol Window
During the symbol window only one media access test symbol (MTS) may be transmitted per channel. MTS symbols are send in NORMAL_ACTIVE state to test the bus guardian.
The symbol window is characterized by the following features:
• Send single symbol
• Transmission of the MTS symbol starts at the symbol windows action point
Parameters: Symbol Window Action Point Offset GTUC9.APO[4:0] (same as for static slots),
Network Idle Time Start GTUC4.NIT[13:0]
5.1.4 Network Idle Time (NIT)
During network idle time the CC has to perform the following tasks:
• Calculate clock correction terms (offset and rate)
• Distribute offset correction over multiple macroticks after offset correction start
• Perform cluster cycle related tasks
Parameters: Network Idle Time Start GTUC4.NIT[13:0],
Offset Correction Start GTUC4.OCS[13:0]
manual_functional_description.fm
-99/165-
15.12.2006
Page 100
User’s Manual
5.1.5 Configuration of NIT Start and Offset Correction Start
Revision 1.2.5 E-Ray
GTUC2.MPC = m
GTUC4.NIT = k
GTUC4.OCS = NIT + 1
Figure 3: Configuration of NIT start and offset correction start
k+1m-1 0 k nn+1
NITSymbol WindowStatic / Dynamic Segment
The number of macroticks per cycle gMacroPerCycle is assumed to be m. It is configured by programming GTUC2.MPC = m.
The static / dynamic segment starts with macrotick 0 and ends with macrotick n:
n = static segment length + dynamic segment offset + dynamic segment length - 1MT
n = gNumberOfStaticSlots • gdStaticSlot + dynamic segment offset
+ gNumberOfMinislots • gdMinislot - 1 MT
The static segment length is configured by GTUC7.SSL and GTUC7.NSS.
The dynamic segment length is configured by GTUC8.MSL and GTUC8.NMS.
The dynamic segment offset is:
If gdActionPointOffset ≤ gdMinislotActionPointOffset:
dynamic segment offset = 0 MT
Else if gdActionPointOffset > gdMinislotActionPointOffset:
The NIT starts with macrotick k+1 and ends with the last macrotick of cycle m-1. It has to be configured by setting GTUC4.NIT = k.
For the E-Ray the offset correction start is required to be GTUC4.OCS ≥ GTUC4.NIT + 1 = k+1.
The length of symbol window results from the number of macroticks between the end of the static /
dynamic segment and the beginning of the NIT. It can be calculated by k - n.
manual_functional_description.fm
-100/165
15.12.2006
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.