Page 1
12
80286
MHz
Turbo
Zero-Wait
Main
Board
‘0
The
information
MBVLSI-168
in this
manual
is
subject
(V
.2)
to
change
without
notice.
Page 2
TABLE
CONTENTS
OF
WHAT
WE
POSSESSIVE
THAT
OTHERS
WITHOUT
!
1
VI.
VII.
VIII.
GENERAL
MAIN
MEMORY
HOW
BY
SOFTWARE
SYSTEM
CHANNEL
l/O
HARDWARE
ATTACHMENT
FUNCTION
ATTACHMENT
BLOCKDIAGRAM
SPECIFICATION
BOARD
TO
JUMPER
COMBINATION
CHANGE
MEMORY
SLOTS
COMPATIBILITY
OF
.........................
I:
JP13/JP14/JP15/JP18
ll:
...............
SELECT
.............
SYSTEM
THE
MAP
..................
................
.........
........
SPEED
........
4_7
8—9
12—15
.......................
3
10
11
16
22
23
*-
5
chips
Zero
wait
wait
One
20
mA,
8
mA, 150pF
Four
layer
Most
powerful
—Using
—Using
set
200pF
44256/41256
4164/41256/1M
CMOS
full
state
state
read
write
slot
DRAM
process
operations
operations
drive
drive
implementation
memory
(system
combination
memory
512K/640K/1024K/2048K/4096K
—-Using
4096K
RAM
Modular,
UP
low
power
bus)
capability
low
for
chip,
bit
memory
TO
512K/1024K/2048K/
consumption
capability
noise
operation.
available:
to
up
512K/1024K
chip,
up
to
ATTACHMENT
BOARD
LAYOUT
lll:
AND
JUMPER
POSITION
.
.24
**************************************
-)(-
*
NOTE:
*
80286:
*
*
4‘+35-X-*-)(-—)(-*******************************
In
this
means
80286
use
manual,
Personal
CPU
Computers
that
*
*
*
*
-)(-
Page 3
GENERAL
.
compatible
Fully
MHz
8/12
RAM
access
to
mega
4
Up
16
address
2
sockets
8
I/O
expansion
Socket
CMOS
battery
24-bit
16-Ievel
7-channel
3—programmable
1/0
Speed:
Most
powerful
—Using
—Using
SPECIFICATION
with
speed
mega
byte
hardware
O-wait
time
byte
expandable
mode
BIOS.
for
slots
for
clock
80287
math
and
support
addressing
and
interrupts
DMA
(Direct
timers
8MHz
memory
44256/41256
4164/41256/1M
80286
and
and
memory
memory
processor
calendar
16-bit data
memory
combination
memory
512K/640K/1024K/2048K/4096K
—Using
4096K
RAM
Modular,
UP
system
software
1-wait
board
on
circuit
chip,
bit
TO
selectable
switchable
in
the
path
access)
protect,
with
capabilities
virtual
rechargable
available:
512K/1024K
to
up
memory
chip,
up
512K/1024K/2048K/
to
3
II.
MAIN
CONNECTORS
Jumper
BOARD
No.
JUMPER
AND
PSi/PS2
KB1
JPl
JP2
JP3
JP4
JP5
JP6
JP7/JP8/JP9
JP10
JPll
JP12
*JP13/JP14/JP15/JP18
JP16
JP17
*:
Jumper
speed
this
It
unless
More
MENT
JP13/JP14/JP15/JP18
which
would
information,
board.
is
not
technical
change,
necessary
user
l”
JUMPERS:
Function
—
Power
—
Keyboard
—
Hardware
—
Keylock/Power
4
Speaker
—
Turbo
—
Turbo
—
Memory
—
Memory
—
Zero
—
EPROM
—
Display
—
Keyboard
—
Power
—
External
according
for
user
like
to
change
SELECTION
supply
connector
reset
connector
hardware
LED
indicator
speed
size
select
wait/One
size
select
adapter
controller
select
good
battery
is
default-set
the “BIOS”
to
the
the
“BIOS".
refer
to
adjust
please
connector
switch
LED
switch
Jumper
wait
select
select
select
connector
for
jumper
"ATTACH-
to
3‘
‘
software
used in
setting,
Page 4
JP1:
Hardware
It's
reset
a
reset
button
switch
JP10:
Zero
Short
Open
wait/One
JP10:
JP10:
Zero
One
wait
wait
select
wait
JP4:
JP5:
JP6:
Turbo
It's
a
Trubo
LED
Memory
Short
using
JP7/JP8/JP9:
JP7/JP8/JP9
open/short/short
short/open/open
short/open/short
short/short/open
short/short/short
hardware
Turbo
LED
lights
speed
1
Pin
100ns
Memory
switch
button
indicator
for
on
select
&
Pin
speed
size
Amount
memory
4096K
2048K
1024K
640K
512K
Turbo
2
of
Jumper
memory
select
(4MB)
(2MB)
(1MB)
mode
chips
(Base
JP6:
(DEFAULT)
memory/Expansion
640K
(640K
(640K
(640K
(512K
memory)
/3456K)
/1408K)
/384K))
/0
/0
JP11:
EPROM
Short
Open
JP12:
Display
Short
Open
JP16:
Power
Short
by
Short
by
)
)
)
9
JP17:
External
The
batteries
gable
E|_
1
2
3
4
size
JP11:
JP11:
adapter
JP12:
JP12:
good
Pin
Mother
Pin
Power
battery
connector
instead of
battery.
select
Using
Using
Using
Using
select
1
&
Pin
Board
2
&
Pin
supplier
Pin
256K
128K
select
Color
Monographics
2
(default)
3
itself
EPROM
EPROM
display
of JP16: Power
of
JP16:
Power
connector
is
for
connecting
blue
the
assignments
ASSIGNMENT
6Vdc
Not
used
GND
GND
adapter
display
good
good
for
barrel
as
followings:
adapter
size
shaped
provided
provided
”AA”
rechar-
6
Page 5
JP13/JP14/JP15/JP18:
Jumper
change
the
Unless
not
More
“ATTACHMENT l”.
JP13/JP14/JP15/JP18
speed
“BIOS"
necesory
used
would
you
technical
Keyboard
via
software,
in
like
for
you
information,
this
board.
to
to
adjust
controller
is
and
which
change
the
please
default-set
according
the
”BIOS”,
Jumper
setting.
refer
Ill
MEMORY
COMBINATION
to
Ill-1:
Using
to
is
it
1
to
Memory
512K
size
44256/41256
Jumper setting
JP7/JP8/JP9
short/short/short
memory
Bank
socket
44256x4
(U47-U50)
41256
(U29
chip
0
position
2
x
84
U38)
combination:
Bank
socket
pcs
pcs
1
position
0
1024K
(1MB)
Ill-2:
Memory
512K
640K
1024K
(1MB)
2048K
(2MB)
4096K
(4MB)
Using
size
short/open/short
44256
(U47-U50)
44256
(U29
4164/41256/1Mbbyte
JP7/JP8/JP9
short/short/short
short/short/open
short/open/short
short/open/open
open/short/short
Bank
41256
(U21-U38)
41256x18
(U21-U38) (U3-U20)
41256
lU21<U38l (U3-U20)
1M
(U21-U38)
1M
(U21-U38)
4
x
4
x
&
U38)
memory
0
18
x
18
x
x
byte
x
byte
pcs
pcs
pcs
18
18
pcs
pcs
pcs
pcs
44256
x
(U41 -U44)
41256
x
81
(U11
combination:
chip
1
Bank
4164
x
41256
x
1M
byte
(U3-U20)
4
2
U20)
18
18
x
pcs
pcs
pcs
18
pcs
pcs
Page 6
lll-3
Memory
Using
size
RAM
JP7/JP8/JP9
MODULAR
Chip
BankO
combination:
Bank
IV
1
HOW
FTW
so
TO
AR
CHANGE
E
THE
SYSTEM
SPEED
BY
512K
1024K
(1MB)
2048K
(MB)
4096K
(4MB)
u-§§*§§§*****************ata-asas-X-a-ai-ai-i-atseam-sunni-§§*********************
*
*
.
*
IvII-II§*******‘I'**********‘ll-i-i-************§§****i*§****§***********§
NOTE
:
User
for
Each
Sh°rt/Sh°"/5h°"
short/open/short
short/open/open
open/short/short
oombmate
cannot
total
amount
item
Ill-1/lll-2/lll-3
'
memory.
255KX259“
256Kx2
(U1&
1MBx2
(”18“”)
1MB
(U1
h
o
eac
works
(u1&u2)
U2)
2
x
&
U2)
m-
tern
fl
independently.
sets
sets
sets
1/m
—‘—‘
256K
(U39
——
——
1MB
(39
3
.
.
2/m
x&
x
x
&
2
U40)
2
sets
U40)
sets
+—
This
mother
12MHz,
Controller.
IV—l
Hardware
I)
,
‘
1
Hardware
SWitCh
|V-'2
*
*
*
*
<
‘
J
)
|V_2_‘|
IV
2 2
Software
When
BIOS"
and
change.
When
”AWARD
(A
Normal
lV-2—3
When
”PHONIX
(A
User
h”
LT)
LT)
board
has
can change
controller:
controller:
button”
controller:
the
equipment
Press
the
the
BlOS"
key
mode.
the
BIOS”
and
(+)or
equipment
and hit
equipment
and hit
_
key
two
system
speed
refer
for
Turbo/Normal
of
mother
hold
down
(—)key
Press
the
and
(1‘)
of
Press
and
the
(\
i.e.
L)
key
8MHz
or
press
Used
&
(ALT)
board
(CTR
for
board
clock
via
hardware
to
JP4,
board
(CTR
for
Turbo/Normal
of
mother
hold
(—)
or
mother
mOde
down
hold down (CTRL>&
>
key
for
Turbo/Normal
and
software
”Turbo
llAMl
key
speed
used
L)
Turbo/
used
&
mode.
Due
to
may
press
and hit
mode.
different
and
hold
<+>
the
version of
down
(—>
or
PHONlX
(CTRL)
for
key
&
BIOS,
(ALT)
user
key
Turbo/Normal
Page 7
V.
SYSTEM
MEMORY
MA)
VI.
I/O CHANNEL
SLOTS
ADDRESS RANGE START-END
000000-03FFFF
040000-07FFFF
080000—09FFFFF
OAFFFF-OBFFFF
OCOOOO-ODFFFF
OEOOOO-OEFFFF
OFOOOO—OFFFFF
100000-11FFFF
120000-15FFFF 1152K-1408K
160000-FDFFFF 1408K-16146K
FEOOOO-FEFFFF
FFOOOO-FFFFFF
COOK-256K
256K—512K Bank1
512K-640K Bank2
640K-768K Video
768K-869K
960K
896K-
960K-1024K
1024K-1152K
16146K-16210K
16210K»16274K
NAME
Bank 0
ROM
l/O
ROM
ROM
Bank
Bank
RAM
ROM
ROM
System
System
System
Display
(128K)
Expansion
System
BIOS (64K)
2
System
3
System
Expansion
System
BIOS
FUNCTION
memory
memory
memory
card
buffer
ROM
(64K)
usage
memory
memory
RAM
(64K)
usage
(64K)
(256K)
(256K)
(128K)
(128K)
(128K)
(128K)
(14870K)
)
l/O
The
*
*
channel
l/O address
24-bit
Refresh
memory
of
supports:
space
addresses
system
100
hex
memory
hex
to
(16MB)
from
3FF
channel
microproces-
sors
*
Selection of
data
accesses
(eigher
8
bit
or
16
bit)
interrupt
*
DMA
channels
l/O
wait-state
Open-bus
share
to
I/O
ADDRESS
HEX
RANGE DEVICES USAGE
000-01F
020-03F
040-051: Timer
060-06F 8042
070-O7F
080-09F
OAO-OBF
OCO-ODF DMA
OFO
OF’i
0F8-0FF
structure
the
system's
MAP
DMA
Interrupt
Real
DMA
Interrupt
Clear Math
Reset Math
Math
generation
(allowing
resources,
controller
(Keyboard)
time
page
controller
Coprocessor System
1
controller
NMl
clock,
register
controller
2
Coprocessor
Coprocessor
1
mask
2
multiple
including
busy
microprocessors
memory)
System
System
System
System
System
System
System
System
System
System
1FO-1
F8
200-207
278-27F
2F8-2FF
F
30031
360v36F Reserved
Fixed
disk
Game
No l/O
Parallel
printer
Serial
port
prototype
2
card
port
2
”0
|/O
l/O
I/O
|/O
I
11
12
Page 8
7
the
I/O
31
32
33
B4
85
36
B7
88
89
B10
811
812
B13
814
B15
816
B17
B18
819
820
B21
822
823
824
825
826
828
B29
830
831
is
slots
as
REARPANEL
l
I
|
l
I
|
l
I
I
I
I
I
I
I
I I
I
I
I
I
I
I
I
I
I
I I
I
I
I
I
I
I
follows:
|
A1
l
A2
|
A3
|
A4
I
A5
|
A6
l
A7
I
A8
I
A9
I
A10
I
A11
I
A12
I
A13
I
A14
A15
I
A16
I
A17
I
A18
I
A19
I
A20
I
A21
I
A22
I
A23
I
A24
A25
I
A26
I
A27
I
A28
I
A29
I
A30
I
A31
—|/0
SD7
306
805
304
803
502
501
800
—l/O
AEN
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
8A6
5A5
SA4
SA3
SA2
SA1
SAO
CH
CH
CK
RDY
ADDRESS
l/O
RANGE
HEX
378—37F
380-38F
3A0-3AF
3BO—3BF
3C0-3CF
3DO-3DF
3F0-3F7
3F8-3FF
MAP
Parallel
SDLC,
Bisynchronus
Monochrome
Reserved
Color/graphic
Floppy
Serial
printer
port
bisynchronus
1
display
monitor
diskette
1
port
DEVICES
1
2
and
adapter
controller
printer adapter
USAGE
”0
IIO
”0
IIO
I/O
I/0
IIO
I/o
W
()
.
Numbering
RESET
fl
I
I
I
‘
‘
I
I
))
,
”
'
;
O
—REFRESH
of
GND
DRV
+5Vdc
IRQZ
—5Vdc
DRQZ
—12Vdc
ows
+12Vdc
GND
—SMEMW
—SMEMR
—|OW
—IOR
—DCK3
DRQ3
—-DACK1
DRQ1
CLK
IRQ7
IR06
IROS
lRQ4
lR03
—DACK2
T/C 827
BALE
+5Vdc
030
GND
13
l/O CHANNEL
J1
—J8
I
14
Page 9
REARPANEL
VII.
HARDWARE
COMPATIBILITY
—MEM
I/O
IRQ16
IRQ11
|RO12
IRQ15
IRQ14
—DACKO
—DACK5
—DACK6
-—DACK7
—MASTER
C316
C816
DRQO
DROS
DRQS
DRO7
+5Vdc
GND
I
D1
D2
D3
D4
DS
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
I
|
l
I
|
l
I
I
I
I
l
I
I
l
I
I
I
l
I
I
I
I
I
I
I
I
I
I
I
I
I
I
l
I
I
HOCHANNELJ2—J7
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
SBHE
LA23
LA22
LA21
LA20
LA19
LA18
LA17
—MEMR
—MEMW
SD08
SD09
SD10
SD11
SD12
SD13
SD14
SD15
)
O
SYSTEM
The
trolled
channels
Channel
GATE
TIMERS
system
an
by
0
through
0
0
CLKINO
CLK
OUT
0
Channel
GATE
1
1
CLK|N1
cond
1
period
CLK OUT
Note: Channel
has
Intel
1
three
is
programmable
8254-2
defined
2,
System
Tied
timer/counter
follows:
as
Timer
on
1.190MHzOSC
8259A
Refresh
Tied
1.190MH2
Request
programmed
signal.
IRQ
Request
on
OSC
Refresh
timer/counters
Generator
Cycle
to
generate
chip.
a
These
15
microse-
con-
are
15
«3
a
Channel
GATE
2
CLK|N2
CLK
OUT
2
Tone
Generation for
Controlled
by
Speaker
bit0of
port
hex
61
PPl
bit
1.190MHzOSC
2
Used
to
drive
16
the
speaker
Page 10
SYSTEM
INTERRUPTS
DIRECT
MEMORY
ACCESS
Sixteen
80286
levels
NMI
The following
decreasing
Priority:
LEVEL
Microprocessor
Interrupt
CTLR
IRQ
IRO
IRO
controllers
1
0
1
2
of
and
shows
NMI
CTLR
IRQ8
IRQQ
|
R010
lRQ1
IRQ12
1
R013
IRO14
lRO15
system
two
2
1
intrrupts
8259A
the
Interrupt
interrupt-level
Parity or
Timer
Keyboard
Interrupt
Realtime
Software redirected
Reserved
Reserved
Reserved
Coprocessor
Fixed
Reserved
l/O channel
output
from
clock
disk
provided
are
Controller
assignments
FUNCTION
0
(Output
buffer
CTLR
interrupt
controller
check
2
to
by
INT
the
chips.
in
full)
OAh
(IRO2)
;)
O
O
Eight
Intel
chip)
DMA
8237-5
used.
are
CTLR1
—
Ch
0
1
—
Ch
2
—
Ch
Ch 3
—
Channels
‘I.
Transfers
16-
bit
system
of these
Each
throughout
Channel 4
To
cascade
channel
use
adapters
channels
in
data
address
odd-byte
128KB
space.
channels
DMA
DMA
Spare
SDLC
Diskette
Spare
0
through
8-
bit
of
memory
channels
16—megabyte
the
through
channels
4.
Transfers
16-bit
and
DMA
7.
5,
6,
blocks
These
boundaries.
are
controller
channels
Ch
Ch
Ch
Ch
3
are
8-
data,
are
will
7
are
0
through
of
system
channels
throughout
channels
supported
chips
are
4
5
6
7
(four
assigned
Cascade
—
—
Spare
—
Spare
—
Spare
contained
l/O
bit
supported
transfer
system
contained
3
to
16-bit
memory
5
through
the
will
the
by
channels
as
CTLR2
for
DMA
in
adapters
these
by
in
data
address
data
not
space.
DMA
in
the
micrOprocessor,
between 16-bit
are
16-megabyte
transfer
system.
in
follows:
L
CTR
controller
8-
and
channels.
64KB
conroller
supported
7 will
transfer
system
data
Two
each
1
bit
or
blicks
by
on
2.
lRO
IRQ 4
lRQ
IRQ
IRQ
for
addresses
3
Serial
Serial
5
6
7
Parallel
Diskette
Parallel
port
port
port
controller
port
17
2
1
2
1
The
the
page
register
18
are
as
follows:
Page 11
Address
*
For
SOURCE
Address
Note:
*
For
SOURCE
Address
Note:
PAGE
DMA
DMA
DMA
DMA
DMA
DMA
DMA
Refresh
generation
DMA
To
generate
(BHE)
DMA
The
logic
decrease
channels
through
REGISTER
channel
channel
channel
channel
channel
channel
channel
0
1
2
3
5
6
7
l/O
0087
0083
0081
0082
0088
0089
008A
j
0
,
g
ADDRESS
HEX
008F
is
DMA
channels
0
REGISTERS
A16
signal
A0.
5
”byte
channels
DMA
invert
channels
DMA
for
3
through
PAGE
A213
the
addressing
address
7
through
PAGE
the
—
line
REGISTERS
A23—A17
BHE
DMA
0.
7). 16
A0
and
channel
through
0
throught
addressing
addresses
3
and
boundaries
page
signals
do
128KB
as
high
are
not
for
follows:
8237A-5
—
A15
enable”
8237A-
—
A16
forced
increase
(64KB
channels
A0
5
A1
to
or
for
,
,)
a
5
.3
0
‘
»
’
1
0
The
TIME
real
REAL
information
colock
system
circuitry
configuration.
ADDRESS
00
01
02
03
04
05
06
07
08
09
0A
OB
CO
OD
0E
OF
10
1
1
12
13
14
15
17
18
CLOCK
-
clock
time
backed
are
uses
Seconds
Second
Minutes
Minute
Hours
Hour
Day
Date
Month
Year
Status
Status
Status
Status
Diagnostic
Shutdown
Diskette drive
Reserved
Fixed
Reserved
Equipment
Low
High
Low
High
AND
NONVOLATILE
MC146818
by
up
14
bytes
DESCRIPTION
alarm
alarm
alarm
of
week
of
month
register
register
register
register
status
disk
type
byte
base
memory
base
memory
expansion
expansion
and
DC
6V
while
A
B
C
D
byte
type
byte
memory
memory
its 64
bytes
battery.
the
restisallocated
byte-driver
—
driverCand
byte
byte
RAM
the
A
RAM
of
internal
B
and
D
to
19
,
20
Page 12
ADDRESS
DESCRIPTION
ATTACHMENT
JP15/JP18
I
FUNCTION OF JUMPER
JP13/JP14/
;:
30
31
32
33
.34
—
—22|l2
_
3F
R
2:53;:
Low
Hugh
Data
Information
Reserved
ed
expansion
.
expansnon
century
CMOS
checksum
memory
.
memory
byte
(set
flags
byte
byte
during
power
on)
4)
'
,,
)
.
()
0
In
this
mother
JP18
is
As
_
different
you
sure
compatible
Once
it
providelto
different
choose
that
the
is
necessary
JP15/JP18
the
to
"controller
“keyboard
a)
Short
b)
Short
0)
Short
d)
Short
While
can
JP13:
JP14:
JP15:
JP18:
the
change
board,
enable
BIOS
Jumper
[Ehe
t
with this
“BIOS"
setting
kspetc):if|cd”B|OS”
e
ey
to
for
software
controller”
menas
means keyboard
means keyboard
means keyboard
Jumpers
the
system
Jumper
and
.
oar
“Bl
and
“Keyboard
short
pin”
supported.
keyboard
setting
change
to
user
”keyboard
JP13/JP‘l4/JP15/JP18_
of
contro
OS”.
of these
one
that
change,
this
speed
controller
of
|flor
trsiggother
er
controller”
Jumper
and
specific
controller
controller
controller
JP13/JP14/JP15/JP18
speed
software.
by
JP13/JP14/JP15/
via
speed
controller”
software.
board,
contro
selected,
are
makes
Before
er)
JP13/JP14/
which
is
is
is
is
is
“BIOS”
set
set
set
set
set
correctly,
according
“PIN
on
”PIN
on
“PIN
on
"PlN
on
b.e
lS
and
30”
23”
27”
32”
you
1
2
iii
22
Page 13
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