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A78LD-M3S
Schematic
45 pgs1.34 Mb0
Schematic
43 pgs1.33 Mb0

Biostar A78LD-M3S Schematic

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CONTENTS
COVER BLOCK DIAGRAM
POWER DELIVERY
CLOCK DISTRIBUTION REVISION HISTROY
SKT 941 K8 AM3 CPU CPU DECOUPLING
DDR CLK BYPASS
DDR3 DIMM A1 DDR3 DIMM B1
ADO FUNCTION RS780-HT LINK
RS780-PCIE
RS780-SYSTEM RS780-PWOER&SBD_MEM
CLOCK GEN SB710-PCIE/PCI/CPU/LPC
SB710-ACPI/GPIO/USB/AUD
SB710-SATA/IDE/HWM/SPI SB710-POWER&DECOUPLING
SB710-STRAPS CRT
PCI-E 16X SLOT
PCI SLOT NONE
USB CONN CODEC VT1708B/ALC662
AUDIO CONNECTOR
SUPER I/O ITE8728 FAN CONTROL
PS2 CONN COM&LPT CONNECTOR
ATX PWR / FRONT PANEL / LED
OVER VOLTAGE IC FRONT USB
PWRGD / MISC DC-DC VCC_CORE DC-DC CONVER
MEMORY POWER
NB/SB CORE POWER Realtek RTL8105T
BOM
A78LD-M3S ( RS780&SB710 )
REV 7.1
DDR3 X 2 Dual channel , PCI-Ex16 X 1 , PCI X 1 , Realtek 10/100 PCI-E Lan , AMD AM3
DATE :2011/04/21
『
BIOSTAR'S PROPRIETARY INFORMATION
『
Any unauthorized use, reproduction, duplication, or disclosure of this document will be subject to the applicable civil and/or criminal penalties.
』
』
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
COVER
COVER
COVER
A78LD-M3S
A78LD-M3S
A78LD-M3S
1
7.1
7.1
7.1
1 45Thursday, April 21, 2011
1 45Thursday, April 21, 2011
1 45Thursday, April 21, 2011
5
4
3
2
1
AMD
DDRIII 800-1333
AM3/AM2+
AM3
LINK
SOCKET
OUT
AMD NB
16x16
IN
D D
Clock Generator
RTM880N-793
DVI/TMDS CON
HyperTransport
TMDS
128bit
DDRIII 800-1333
UNBUFFERED DDRIII DIMM1
UNBUFFERED DDRIII DIMM2
DDRIII FIRST LOGICAL DIMM
RS740G
VGA CON
PCIE SLOT1
16X
16X
HyperTransport LINK0 CPU I/F
INTEGRATED GRAPHICS
LVTM
1 16X PCIE VIDEO I/F
1 1X PCIE I/F
C C
SB710
4X PCIE
SPI I/F
HD AUDIO I/F
SATA II I/F
ATA 66/1 00/133 I/F
SPI ROM
AZILIA CODEC
SATA#0
IDE1
HW MONITOR
SATA#1
SATA#2
SATA#3
SATA#4 SATA#5
GIGABIT Realtek RTL8111C
4 1X PCIE INTERFACE
PCIE GPP0 X1
ATI SB
USB-5
USB-6
USB-4
USB-7
USB-3
USB-8
USB-2
USB-9
B B
USB-1
USB-10 USB-11
BOOTSTRAPS ROM (SB)
PCI BUS
USB-0
USB 2.0
I2C I/F
USB2.0 (12)
SATA II (6)
AC97 2.3/ AZALIA
ATA 66/100/133
ACPI
LPC I/F
INT RTC
HW MONITOR
PCI SLOT #1
DESKTOP M2 POWER
A A
RS760G CORE & PCIE POWER
DDR MEMORY POWER
5
PCI SLOT #2
PCI SLOT #3
4
ITE LPC SIO 8716/8718
FLOPPY
KBD MOUSE
HW MONITOR
3
Title
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Title
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Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
A78LD-M3S
A78LD-M3S
A78LD-M3S
1
7.1
7.1
7.1
2 45Thursday, April 21, 2011
2 45Thursday, April 21, 2011
2 45Thursday, April 21, 2011
D
DCCBBAA
5
ATX P/S WITH 1A STBY CURRENT
5VSB +/-5%
5V +/-5%
3.3V +/-5%
12V +/-5%
-12V +/-5%
CPU PW 12V +/-5%
VCC 1.1V SW REGULATOR
+3.3VSB REGULATOR ACPI CONTROLLER
4
+5VDUA L_MEM (S0,S 5)
VCC 1.2V SW REGULATOR
+3.3V SB (S0, S1, S3, S4, S5)
+3.3V DUAL (S 0, S1, S3, S4, S5)
+5VDUA L (S0, S1, S3, S 4, S5 )
2.5V SHUNT REGULATOR
VRM SW REGULATOR
1.8V VDD SW REGULATOR
VCC 1.1V SW REGULATOR
3
0.9V VTT_DDR REGULATOR
+1.1V RX78 0/RS7 80; +1 .2V RS740 (S0, S1)
+1.1V RX78 0/RS7 80; +1 .2V RS740 (S0, S1)
1.8V LINEAR REGULATOR
+1.2V (S0, S 1)
1.2V STB LDO REGULATOR
+1.8V (S0, S 1)
+1.2V SB (S5)
2
CPU_V DDA_RUN
(S0, S 1)
VDD_CP UCORE_RUN (S0, S1)/VDD_CP UNB_RUN (S0, S1)
CPU_VTT_SUS (S0,S1,S3)
CPU_VDDIO_SUS(S0,S1,S3)
DDRII DIMMs
VTT_DDR 2A
VDD MEM 12A
1.5V LINEAR REGULATOR
+1.5V (S0, S 1)
AM3
VDDA 2.5V 0.2A VDDCORE
0.8-1.55V 110 A DDRIII MEM I/F
VTT 2A, VDD 10A
VLDT 1.2V 0.5A
RS780
VDDHT/RX 1.1V 1.2A
VDDHTTX 1.2V 0.5A
VDDPCIE 1.1V 2A
NB CORE VDDC
1.1V 7A
VDDA18PCIE 1.8V 0.9A
PLLs 1.8V 0.1A
VDD18/VDD18_MEM
1.8V 0.01A
VDD_MEM 1.8V/1.5V 0.5A
AVDD 3.3V 0.135A
SB700
X4 PCI-E 0.8A
ATA I/O 0.5A
ATA PLL 0.01A
PCI-E PVDD 80mA
SB CORE 0.6A
CLOCK
1.2V S5 PW 0.22A
3.3V S5 PW 0.01A
USB CORE I/O 0.2A
3.3V I/O 0.45A
1
+3.3V DUAL (S 0, S1, S3)
PCI Slot (per slot) X16 PCIE
5V
3.3V
5.0A
7.6A 5VDual
12V
3.3Vaux
-12V
0.375A
0.1A
X1 PCIE per
3.3V
12V
3.3Vaux
3.0A
0.5A
0.1A
3.3V
12V
3.0A
5.5A
X16 PCIE
3.3V
12V
5.5A
USB X6 FR
VDD 3.0A
5VDual
2.0A0.5A
USB X6 RL
VDD
2.0A
2XPS/2
5VDual
1.0A
GBE
3.3V 0.5A (S0, S1)
3.3V 0.1A (S3)
AZALIA CODEC CON
3.3V CORE 0.3A
5V ANALOG 0.1A
12V 0.1A
Title
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Size Doc ument Number Rev
Custo m
Custo m
Custo m
Date: Shee t
Date: Shee t
Date: Shee t
POWER DELIVERY
POWER DELIVERY
POWER DELIVERY
A78LD-M3S
A78LD-M3S
A78LD-M3S
3 4 5Thursday, A pril 21, 20 11
3 4 5Thursday, A pril 21, 20 11
3 4 5Thursday, A pril 21, 20 11
of
of
of
7.1
7.1
7.1
5
544332211
DCCBBAA
D
DIM M1
3 PAIR MEM CLK
3 PAIR MEM CLK
AM3/AM 2g2 CPU
AM3 S OCKET
1 PAIR CPU CL K
DIM M2
200MHZ HT ref clock
100MHZ DIFF (RX780/RS 780)
HT RE FCLK
66MHz SE(RS 740)
14.318M HZ OSC
3 PAIR MEM CLK
3 PAIR MEM CLK
HT RE FCLK
66MHz SE(RS 740)
1 PAIR CPU CL K
200MHZ
100MHz DIFF (RX780/RS 780)
EXTERNAL
CLK GE N.
(RS740/RX780)
NB-OSCI N
14.318M HZ
PCIE GPP CL K
100MHZ
PCIE GPP CL K
100MHZ
NB GF X PCI E CLK
100MHZ
NB GP P PCI E CLK
100MHZ
PCIE GFX CLK
100MHZ
PCIE GPP CL K
100MHZ
PCIE GPP CL K
100MHZ
PCIE GPP CL K
100MHZ
USB CL K
48MHZ
(RX780)
25MHZ OSC INP UT
AMD NB RS780
PCIE GFX SLOT 1 - 1 6 LANES
PCIE GPP SLOT 1 - 1 LANE
PCIE GPP SLOT 2 - 4 LANES
PCIE GBE
NB PCI E Ref cl ock
100MHZ
NB Disp clock
100MHZ DIFF (RS780)
GPP Ref clo ck
100MHZ
GFX Ref clo ck 100MHZ
GPP Ref clo ck
100MHZ
GPP Ref clo ck 100MHZ
GPP Ref clo ck
100MHZ
25MHz
SATA
CPU_HT _CLK
NB_HT_C LK
25M_48 M_66M _OSC
AMD SB SB700
NB_DIS P_CLK
GPP_C LK3
PCIE_R CLK/ NB_LNK _CLK
SLT_G FX_CLK
GPP_C LK0
GPP_C LK1
GPP_C LK2
USB_CL K
SB_BIT CLK
48MHZ
PCI CL K0
33MHZ
PCI CL K1
33MHZ
PCI CL K2
33MHZ
LPC_CL K0
33MHZ
LPC CL K1
33MHZ
PCI CL K3
33MHZ
PCI CL K4
33MHZ
25MHz
PCI SLOT 0
PCI SLOT 1
PCI SLOT 2
TPM
LPC BIOS
DEBUG POST
SUPER IO IT8728
HD AUDIO CON
TPM (BCM5755/5761 )
External clock mode
Internal clock mode
SIO CL K
48MHZ
32.768KHz
Title
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Custo m
Custo m
Custo m
Date: Shee t
Date: Shee t
Date: Shee t of
CLOCK DISTRIBUTION
CLOCK DISTRIBUTION
CLOCK DISTRIBUTION
A78LD-M3S
A78LD-M3S
A78LD-M3S
4 45Thursday, A pril 21, 20 11
4 45Thursday, A pril 21, 20 11
4 45Thursday, A pril 21, 20 11
of
of
7.1
7.1
7.1
5
4
3
1
1.Change NB to RS780
2.Change SUPER IO to IT8728
3.Change Codec to VT1708B
4.Change Lan Chip to RTL8105T
5.Remove Floppy Connector
D D
6.Remove SPDIF Out Connector
7.Modify BAT Socket
C C
B B
A A
Title
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Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
REVISION HISTORY
REVISION HISTORY
REVISION HISTORY
A78LD-M3S
A78LD-M3S
A78LD-M3S
5 45Thursday, April 21, 2011
5 45Thursday, April 21, 2011
5 45Thursday, April 21, 2011
7.1
7.1
7.1
544332211
D
DCCBBAA
5
HyperTransport
CPU1A
CPU1A
HTCPU_U PCLK116
HTCPU_U PCLK1_16
HTCPU_U PCLK016
HTCPU_U PCLK0_16
HTCPU_U PCNTL116
HTCPU_U PCNTL1_16
HTCPU_U PCNTL16
HTCPU_U PCNTL_16
HTCPU_U P[15..0]16
HTCPU_U P_[15..0]16
HTCPU_U PCLK1 HTCPU_U PCLK1_ HTCPU_U PCLK0 HTCPU_U PCLK0_
HTCPU_U PCNTL1 HTCPU_U PCNTL1_ HTCPU_U PCNTL HTCPU_U PCNTL_
HTCPU_U P15 HTCPU_U P_15 HTCPU_U P14 HTCPU_U P_14 HTCPU_U P13 HTCPU_U P_13 HTCPU_U P12 HTCPU_U P_12 HTCPU_U P11 HTCPU_U P_11 HTCPU_U P10 HTCPU_U P_10 HTCPU_U P9 HTCPU_U P_9 HTCPU_U P8 HTCPU_U P_8
HTCPU_U P7 HTCPU_U P_7 HTCPU_U P6 HTCPU_U P_6 HTCPU_U P5 HTCPU_U P_5
HTCPU_U P_4 HTCPU_U P3 HTCPU_U P_3 HTCPU_U P2 HTCPU_U P_2 HTCPU_U P1 HTCPU_U P_1 HTCPU_U P0 HTCPU_U P_0
HTCPU_U P[15..0]
HTCPU_U P_[15..0]
N6
L0_CLKIN_H 1
P6
L0_CLKIN_L 1
N3
L0_CLKIN_H 0
N2
L0_CLKIN_L 0
V4
L0_CTLIN_ H1
V5
L0_CTLIN_ L1
U1
L0_CTLIN_ H0
V1
L0_CTLIN_ L0
U6
L0_CADIN_ H15
V6
L0_CADIN_ L15
T4
L0_CADIN_ H14
T5
L0_CADIN_ L14
R6
L0_CADIN_ H13
T6
L0_CADIN_ L13
P4
L0_CADIN_ H12
P5
L0_CADIN_ L12
M4
L0_CADIN_ H11
M5
L0_CADIN_ L11
L6
L0_CADIN_ H10
M6
L0_CADIN_ L10
K4
L0_CADIN_ H9
K5
L0_CADIN_ L9
J6
L0_CADIN_ H8
K6
L0_CADIN_ L8
U3
L0_CADIN_ H7
U2
L0_CADIN_ L7
R1
L0_CADIN_ H6
T1
L0_CADIN_ L6
R3
L0_CADIN_ H5
R2
L0_CADIN_ L5
N1
L0_CADIN_ H4
P1
L0_CADIN_ L4
L1
L0_CADIN_ H3
M1
L0_CADIN_ L3
L3
L0_CADIN_ H2
L2
L0_CADIN_ L2
J1
L0_CADIN_ H1
K1
L0_CADIN_ L1
J3
L0_CADIN_ H0
J2
L0_CADIN_ L0
SOCKET AM3 941 SMD
SOCKET AM3 941 SMD
L0_CLKOU T_H1
L0_CLKOU T_L1
L0_CLKOU T_H0
L0_CLKOU T_L0
L0_CTLOU T_H1
L0_CTLOU T_L1
L0_CTLOU T_H0
L0_CTLOU T_L0
L0_CADOU T_H15
L0_CADOU T_L15
L0_CADOU T_H14
L0_CADOU T_L14
L0_CADOU T_H13
L0_CADOU T_L13
L0_CADOU T_H12
L0_CADOU T_L12
L0_CADOU T_H11
L0_CADOU T_L11
L0_CADOU T_H10
L0_CADOU T_L10
L0_CADOU T_H9
L0_CADOU T_L9
L0_CADOU T_H8
L0_CADOU T_L8
L0_CADOU T_H7
L0_CADOU T_L7
L0_CADOU T_H6
L0_CADOU T_L6
L0_CADOU T_H5
L0_CADOU T_L5
HT LINK
HT LINK
L0_CADOU T_H4
L0_CADOU T_L4
L0_CADOU T_H3
L0_CADOU T_L3
L0_CADOU T_H2
L0_CADOU T_L2
L0_CADOU T_H1
L0_CADOU T_L1
L0_CADOU T_H0
L0_CADOU T_L0
HTCPU_D WNCLK1
AD5
HTCPU_D WNCLK1 _
AD4
HTCPU_D WNCLK0
AD1
HTCPU_D WNCLK0 _
AC1
HTCPU_D WNCN TL1
Y6
HTCPU_D WNCN TL1_
W6
HTCPU_D WNCN TL
W2
HTCPU_D WNCN TL_
W3
HTCPU_D WN15
Y5
HTCPU_D WN_15
Y4
HTCPU_D WN14
AB6
HTCPU_D WN_14
AA6
HTCPU_D WN13
AB5
HTCPU_D WN_13
AB4
HTCPU_D WN12
AD6
HTCPU_D WN_12
AC6
HTCPU_D WN11
AF6
HTCPU_D WN_11
AE6
HTCPU_D WN10
AF5
HTCPU_D WN_10
AF4
HTCPU_D WN9
AH6
HTCPU_D WN_9
AG6
HTCPU_D WN8
AH5
HTCPU_D WN_8
AH4
HTCPU_D WN7
Y1
HTCPU_D WN_7
W1
HTCPU_D WN6
AA2
HTCPU_D WN_6
AA3
HTCPU_D WN5
AB1
HTCPU_D WN_5
AA1
HTCPU_D WN4HTCPU_U P4
AC2
HTCPU_D WN_4
AC3
HTCPU_D WN3
AE2
HTCPU_D WN_3
AE3
HTCPU_D WN2
AF1
HTCPU_D WN_2
AE1
HTCPU_D WN1
AG2
HTCPU_D WN_1
AG3
HTCPU_D WN0
AH1
HTCPU_D WN_0
AG1
HTCPU_D WN[15..0]
HTCPU_D WN_[15..0]
HTCPU_D WNCLK1 16 HTCPU_D WNCLK1 _ 16 HTCPU_D WNCLK0 16 HTCPU_D WNCLK0 _ 16
HTCPU_D WNCN TL1 16 HTCPU_D WNCN TL1_ 16 HTCPU_D WNCN TL 16 HTCPU_D WNCN TL_ 16
HTCPU_D WN[15..0] 16
HTCPU_D WN_[15..0] 16
Title
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Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet of
K8 CPU HT
K8 CPU HT
K8 CPU HT
A78LD-M3S
A78LD-M3S
A78LD-M3S
6 45Thursday, April 21, 2011
6 45Thursday, April 21, 2011
6 45Thursday, April 21, 2011
of
of
7.1
7.1
7.1
544332211
D
DCCBBAA
5
Vout=Vref (1.25V) X ( 1+R2/R1 )
CQ2
CQ2
+5V
CCT 1
CR3
CR3
R1
49.9 1% 0402
R2
CPU_ CLK20
CPU_ CLK_20
+1.5V _SUS
SIO _SIC33 SIO _SID33
CPU_ TDI15
CPU_ TCK15 CPU_ TMS15
+1.5V _SUS
CPU_ CLK20
HTCP U_PWRG D2 1
+1.5V _SUS
49.9 1% 0402
CR6
CR6
49.9 1% 0402
49.9 1% 0402
CPU_ CLK_20
LDT _RST#15 ,18,21
2.5V DDA
+V_C PU
CPU_ CLK
CPU_ CLK_ HTCP U_PWRG D HTCP U_STOP_ LDT _RST#
CPU_ TDI CPU_ TRST# CPU_ TCK CPU_ TMS
CPU_ DBREQ#
CPU_ CORE_F B CPU_ CORE_F B-
CPU_ M_VREFF
I O A
CPU_ PRESENT #22
CPU_ TRST#15
CPU_ DBREQ#15
CPU_ CORE_F B41 CPU_ CORE_F B_41
CCT 1
+
+
1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
CC3 3 900P 50 V X7R 0 402CC3 3 900P 50 V X7R 0 402
CC4 3 900P 50 V X7R 0 402CC4 3 900P 50 V X7R 0 402
CR8 10K 0402CR8 10K 0402
CR1 9 39.2 1% 0402CR1 9 39.2 1% 0402 CR2 2 39.2 1% 0402CR2 2 39.2 1% 0402
CR2 3 510 0402C R23 5 10 0402 CR2 5 510 0402C R25 5 10 0402
CRN5
CRN5 330 8P4R 04 02
330 8P4R 04 02
CPUC LKPCP UCLKP CPUC LKNCPUC LKN
HTCP UPWRGDHTCPUPW RGD
LDT RSTLDTR ST
2V5 VDDA2V5 VDDA
1P5 SUS1P5 SUS
VCP UVCP U
CC1
CC1
1 2
1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
AZ1 117H-ADJ SOT-223
AZ1 117H-ADJ SOT-223
CPU_ CORE_F B
CPU_ CORE_F B_
+1.5V _SUS
+1.5V _SUS
CR1 7
CR1 7
16.9 1% 0402
16.9 1% 0402
CR2 1
CR2 1
16.9 1% 0402
16.9 1% 0402
+1.5V _SUS
1 2
LDT _RST#15 ,18,21 LDT _STOP#18,2 1
HTCP U_PWRG D21
1 2
CPU_ M_VREFF
12
CC2 9
CC2 9 1UF 10 V Y5V 04 02
1UF 10 V Y5V 04 02
CRN3
CRN3 330 8P4R 04 02
330 8P4R 04 02
3 4
5 6
7 8
CLOSE TO CPU
CC5
CC5
0.1UF 1 6V Y5V 0 402 /NI
0.1UF 1 6V Y5V 0 402 /NI
SIO _SID
78
SIO _SIC
56
ALE RT
34 12
RN64
RN64 1K 8 P4R 040 2
1K 8 P4R 040 2
12
CC3 0
CC3 0 100 0P 50V X 7R 040 2
100 0P 50V X 7R 040 2
LDT _RST# HTCP U_STOP_ HTCP U_PWRG D
2.5V DDA
=2.5V
12
CC2
CC2 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
CR1 3 169 1% 0402CR1 3 169 1% 0402
TES T18
78
TES T15
56
TES T14
34
TES T26
12
SA0 ALE RT
TES T19 TES T18
TES T15 TES T14 TES T12
C10 D10
AL3
AL6 AK6 AK4 AL4
AL10 AJ10 AH10
AL9
E12
F12 AH11 AJ11
A10
B10
F10
AJ7
AH9
AJ5
AH7
AJ6
C18
C20
G24
G25
H25
L25 L26
A8 B8
C9 D8 C7
A5
G2 G1
F3
E9
F6
D6
E7 F8
C5
E5
F2
CPU_THERMTRIP
CPU1 D
CPU1 D
VDDA_1 VDDA_2
CLKIN_H CLKIN_L
PWROK LDTSTOP_L RESET_L
CPU_PRESENT_L
SIC SID SA0 ALERT_L
TDI TRST_L TCK TMS
DBREQ_L
VDD_FB_H VDD_FB_L
M_VDDIO_PWRGD
VDDR_SENSE
M_VREF M_ZN M_ZP
TEST25_H TEST25_L TEST19 TEST18 TEST13 TEST9
TEST17 TEST16 TEST15 TEST14 TEST12
TEST7 TEST6 TEST3 TEST2
RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8
MISC.
MISC.
INT. MISC.
INT. MISC.
B
E
2N39 04 SOT2 32N3904 SOT23
CORE_TYPE
VID5
VID4 SVC/VID3 SVD/VID2
PVIEN/VID1
VID0
THERMDC THERMDA
THERMTRIP_L
PROCHOT_L
TDO
DBRDY
VDDIO_FB_H
VDDIO_FB_L VDDNB_FB_H VDDNB_FB_L
PSI_L
HTREF1 HTREF0
TEST29_H
TEST29_L
TEST24 TEST23 TEST22 TEST21 TEST20
TEST28_H
TEST28_L
TEST27 TEST26 TEST10
TEST8
RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16
Near CPU
SOC KET AM3 9 41 SMD
SOC KET AM3 9 41 SMD
CPU_ THERMTRI P# 2 2
+1.5V _SUS
1 2
3 4
5 6
G5
D2 D1 C1 E3 E2 E1
AG9 AG8 AK7 AL7
CPU_ TDO
AK10
CPU_ DBRDY
B6
AK11 AL11 G4 G3
F1
V8 V7
FBC LKOUT
C11
FBC LKOUT*
D11
TES T24
AK8 AH8
TES T22
AJ9
TES T21
AL8
TES T20
AJ8
J10 H9
TES T27
AK9
TES T26
AK5 G7 D4
L30 L31 AD25 AE24 AE25 AJ18 AJ20 AK3
+1.5V _SUS
CRN1
CRN1 1K 8 P4R 040 2
1K 8 P4R 040 2
1 2
3 4
5 6
RN1
RN1 330 8P4R 04 02
330 8P4R 04 02
7 8
PVI PWM-->FLOATING
CPU_ THERMDCC CPU_ THERMDAA CPU_ THERMTRI P CPU_ PROCHOT #
CR1 5 0 04 02 /NICR1 5 0 04 02 /NI CR9 0 04 02 /NICR9 0 04 02 /NI
CR1 8 44.2 1% 0402CR1 8 44.2 1% 0402 CR2 0 44.2 1% 0402CR2 0 44.2 1% 0402
CR2 4 80.6 1% 0402CR2 4 80.6 1% 0402
8/5/8/20 LAYOUT: ROUTE 80 OHM DIFF IMPEDENCE LAYOUT: PLACE WITHIN 1 INCH OF CPU
7 8
1 2
3 4
TES T27 TES T21 TES T19
TES T22 TES T12 TES T24 TES T20
5 6
7 8
CRN6
CRN6 1K 8 P4R 040 2
1K 8 P4R 040 2
K8_ VID5 41 K8_ VID4 41 K8_ VID3 41 K8_ VID2 41 K8_ VID1 41 K8_ VID0 41
K8_ VID5 41 K8_ VID4 41 K8_ VID3 41 K8_ VID2 41 K8_ VID1 41 K8_ VID0 41
CPU_ THERMDC 33 CPU_ THERMDA 33
CPU_ PROCHOT # 2 1
+1.2V _HT
CRN2
CRN2
78 56 34 12
330 8P4R 04 02
330 8P4R 04 02
CRN4
CRN4
78 56 34 12
1K 8 P4R 040 2
1K 8 P4R 040 2
PVI PWM-->VID1-->HI
CPU_ TDO 15
CPU_ DBRDY 15
+1.5V _SUS
Title
Title
Title
Size Doc ument Number Rev
Size Doc ument Number Rev
Size Doc ument Number Rev
Custo m
Custo m
Custo m
Date: Shee t
Date: Shee t
Date: Shee t of
K8 CPU MISC
K8 CPU MISC
K8 CPU MISC
A78LD-M3S
A78LD-M3S
A78LD-M3S
7 45Thursday, A pril 21, 20 11
7 45Thursday, A pril 21, 20 11
7 45Thursday, A pril 21, 20 11
of
of
7.1
7.1
7.1
544332211
D
DCCBBAA
5
CPU1 B
CPU1 B
AG21
MA_CLK_H7
AG20
MA_CLK_L7
AE20
MA_CLK_H6
AE19
MA_CLK_L6
U27
MA_CLK_H5
U26
MA_CLK_L5
MEM_MA0 _CLK_ H01 3
MEM_MA0 _CLK_ L013
MEM_MA0 _CLK_ H11 3
MEM_MA0 _CLK_ L113
MEM_MA0 _CS_L 113 MEM_MA0 _CS_L 013
MEM_MA0 _ODT113 MEM_MA0 _ODT013
MEM_MA_ RESET _L13
MEM_MA_ CAS_L1 3
MEM_MA_ WE_L13
MEM_MA_ RAS_L1 3
MEM_MA_ BANK213 MEM_MA_ BANK113 MEM_MA_ BANK013
MEM_MA_ CKE11 3 MEM_MA_ CKE01 3
MEM_MA_ ADD[15 ..0]13
MEM_MA_ DQS_H[8 ..0]13
MEM_MA_ DQS_L [8..0]1 3
MEM_MA_ DM[8..0]1 3
MEM_MA_ ADD[15 ..0] MEM_MA_ ADD15 MEM_MA_ ADD14 MEM_MA_ ADD13 MEM_MA_ ADD12 MEM_MA_ ADD11 MEM_MA_ ADD10 MEM_MA_ ADD9 MEM_MA_ ADD8 MEM_MA_ ADD7 MEM_MA_ ADD6 MEM_MA_ ADD5 MEM_MA_ ADD4 MEM_MA_ ADD3 MEM_MA_ ADD2 MEM_MA_ ADD1 MEM_MA_ ADD0
MEM_MA_ DQS_H[8 ..0] MEM_MA_ DQS_H7 MEM_MA_ DQS_L 7 MEM_MA_ DQS_H6 MEM_MA_ DQS_L 6 MEM_MA_ DQS_H5 MEM_MA_ DQS_L 5 MEM_MA_ DQS_H4 MEM_MA_ DQS_L 4 MEM_MA_ DQS_H3 MEM_MA_ DQS_L 3 MEM_MA_ DQS_H2 MEM_MA_ DQS_L 2 MEM_MA_ DQS_H1 MEM_MA_ DQS_L 1 MEM_MA_ DQS_H0 MEM_MA_ DQS_L 0
MEM_MA_ DQS_L [8..0] MEM_MA_ DM7 MEM_MA_ DM6 MEM_MA_ DM5 MEM_MA_ DM4 MEM_MA_ DM3 MEM_MA_ DM2 MEM_MA_ DM1 MEM_MA_ DM0
MEM_MA_ DM[8..0]
V27 W27 W26 W25
U24
V24
G19
H19
G20 G21
AC25
AA24
AE28
AC28
AD27
AA25
AE27
AC27
E20
AB25 AB27 AA26
N25
Y27
AA27
L27 M25
M27
N24
AC26
N26
P25
Y25
N27
R24
P27
R25 R26 R27
T25
U25
T27 W24
AD15
AE15 AG18 AG19 AG24 AG25 AG27 AG28
D29 C29 C25 D25
E19 F19 F15
G15
AF15
AF19
AJ25
AH29
B29 E24 E18 H15
MA_CLK_H4 MA_CLK_L4 MA_CLK_H3 MA_CLK_L3 MA_CLK_H2 MA_CLK_L2 MA_CLK_H1 MA_CLK_L1 MA_CLK_H0 MA_CLK_L0
MA0_CS_L1 MA0_CS_L0
MA0_ODT1 MA0_ODT0
MA1_CS_L1 MA1_CS_L0
MA1_ODT1 MA1_ODT0
MA_RESET_L
MA_CAS_L MA_WE_L MA_RAS_L
MA_BANK2 MA_BANK1 MA_BANK0
MA_CKE1 MA_CKE0
MA_ADD15 MA_ADD14 MA_ADD13 MA_ADD12 MA_ADD11 MA_ADD10 MA_ADD9 MA_ADD8 MA_ADD7 MA_ADD6 MA_ADD5 MA_ADD4 MA_ADD3 MA_ADD2 MA_ADD1 MA_ADD0
MA_DQS_H7 MA_DQS_L7 MA_DQS_H6 MA_DQS_L6 MA_DQS_H5 MA_DQS_L5 MA_DQS_H4 MA_DQS_L4 MA_DQS_H3 MA_DQS_L3 MA_DQS_H2 MA_DQS_L2 MA_DQS_H1 MA_DQS_L1 MA_DQS_H0 MA_DQS_L0
MA_DM7 MA_DM6 MA_DM5 MA_DM4 MA_DM3 MA_DM2 MA_DM1 MA_DM0
SOC KET AM3 9 41 SMD
SOC KET AM3 9 41 SMD
MEM CHA
MEM CHA
MA_DATA63 MA_DATA62 MA_DATA61 MA_DATA60 MA_DATA59 MA_DATA58 MA_DATA57 MA_DATA56 MA_DATA55 MA_DATA54 MA_DATA53 MA_DATA52 MA_DATA51 MA_DATA50 MA_DATA49 MA_DATA48 MA_DATA47 MA_DATA46 MA_DATA45 MA_DATA44 MA_DATA43 MA_DATA42 MA_DATA41 MA_DATA40 MA_DATA39 MA_DATA38 MA_DATA37 MA_DATA36 MA_DATA35 MA_DATA34 MA_DATA33 MA_DATA32 MA_DATA31 MA_DATA30 MA_DATA29 MA_DATA28 MA_DATA27 MA_DATA26 MA_DATA25 MA_DATA24 MA_DATA23 MA_DATA22 MA_DATA21 MA_DATA20 MA_DATA19 MA_DATA18 MA_DATA17 MA_DATA16 MA_DATA15 MA_DATA14 MA_DATA13 MA_DATA12 MA_DATA11 MA_DATA10
MA_DATA9 MA_DATA8 MA_DATA7 MA_DATA6 MA_DATA5 MA_DATA4 MA_DATA3 MA_DATA2 MA_DATA1 MA_DATA0
MA_DQS_H8
MA_DQS_L8
MA_DM8
MA_CHECK7 MA_CHECK6 MA_CHECK5 MA_CHECK4 MA_CHECK3 MA_CHECK2 MA_CHECK1 MA_CHECK0
MA_EVENT_L
MEM_MA_ DATA[0 ..63]
MEM_MA_ DATA6 3
AE14
MEM_MA_ DATA6 2
AG14
MEM_MA_ DATA6 1
AG16
MEM_MA_ DATA6 0
AD17
MEM_MA_ DATA5 9
AD13
MEM_MA_ DATA5 8
AE13
MEM_MA_ DATA5 7
AG15
MEM_MA_ DATA5 6
AE16
MEM_MA_ DATA5 5
AG17
MEM_MA_ DATA5 4
AE18
MEM_MA_ DATA5 3
AD21
MEM_MA_ DATA5 2
AG22
MEM_MA_ DATA5 1
AE17
MEM_MA_ DATA5 0
AF17
MEM_MA_ DATA4 9
AF21
MEM_MA_ DATA4 8
AE21
MEM_MA_ DATA4 7
AF23
MEM_MA_ DATA4 6
AE23
MEM_MA_ DATA4 5
AJ26
MEM_MA_ DATA4 4
AG26
MEM_MA_ DATA4 3
AE22
MEM_MA_ DATA4 2
AG23
MEM_MA_ DATA4 1
AH25
MEM_MA_ DATA4 0
AF25
MEM_MA_ DATA3 9
AJ28
MEM_MA_ DATA3 8
AJ29
MEM_MA_ DATA3 7
AF29
MEM_MA_ DATA3 6
AE26
MEM_MA_ DATA3 5
AJ27
MEM_MA_ DATA3 4
AH27
MEM_MA_ DATA3 3
AG29
MEM_MA_ DATA3 2
AF27
MEM_MA_ DATA3 1
E29
MEM_MA_ DATA3 0
E28
MEM_MA_ DATA2 9
D27
MEM_MA_ DATA2 8
C27
MEM_MA_ DATA2 7
G26
MEM_MA_ DATA2 6
F27
MEM_MA_ DATA2 5
C28
MEM_MA_ DATA2 4
E27
MEM_MA_ DATA2 3
F25
MEM_MA_ DATA2 2
E25
MEM_MA_ DATA2 1
E23
MEM_MA_ DATA2 0
D23
MEM_MA_ DATA1 9
E26
MEM_MA_ DATA1 8
C26
MEM_MA_ DATA1 7
G23
MEM_MA_ DATA1 6
F23
MEM_MA_ DATA1 5
E22
MEM_MA_ DATA1 4
E21
MEM_MA_ DATA1 3
F17
MEM_MA_ DATA1 2
G17
MEM_MA_ DATA1 1
G22
MEM_MA_ DATA1 0
F21
MEM_MA_ DATA9
G18
MEM_MA_ DATA8
E17
MEM_MA_ DATA7
G16
MEM_MA_ DATA6
E15
MEM_MA_ DATA5
G13
MEM_MA_ DATA4
H13
MEM_MA_ DATA3
H17
MEM_MA_ DATA2
E16
MEM_MA_ DATA1
E14
MEM_MA_ DATA0
G14
MEM_MA_ DQS_H8
J28
MEM_MA_ DQS_L 8
J27
MEM_MA_ DM8
J25
MEM_MA_ CHECK[7 ..0]
MEM_MA_ CHECK7
K25
MEM_MA_ CHECK6
J26
MEM_MA_ CHECK5
G28
MEM_MA_ CHECK4
G27
MEM_MA_ CHECK3
L24
MEM_MA_ CHECK2
K27
MEM_MA_ CHECK1
H29
MEM_MA_ CHECK0
H27
W30
CR4 1 1K 0402CR4 1 1K 0402
MEM_MA_ DATA[0 ..63] 13
MEM_MA_ CHECK[7 ..0] 13
MEM_MA_ EVENT_ L 13
+1.5V _SUS
Title
Title
Title
Size Doc ument Number Rev
Size Doc ument Number Rev
Size Doc ument Number Rev
Custo m
Custo m
Custo m
Date: Shee t of
Date: Shee t
Date: Shee t
K8 CPU MEMORY-1
K8 CPU MEMORY-1
K8 CPU MEMORY-1
A78LD-M3S
A78LD-M3S
A78LD-M3S
of
of
8 45Thursday, A pril 21, 20 11
8 45Thursday, A pril 21, 20 11
8 45Thursday, A pril 21, 20 11
7.1
7.1
7.1
544332211
D
DCCBBAA
5
CPU1 C
CPU1 C
AJ19
MB_CLK_H7
AK19
MB_CLK_L7
AL19
MB_CLK_H6
AL18
MB_CLK_L6
U31
MB_CLK_H5
U30
MB_CLK_L5
MEM_MB0 _CLK_ H014
MEM_MB0 _CLK_ L014
MEM_MB0 _CLK_ H114
MEM_MB0 _CLK_ L114
MEM_MB0 _CS_L 114 MEM_MB0 _CS_L 014
MEM_MB0 _ODT11 4 MEM_MB0 _ODT01 4
MEM_MB_ RESET _L1 4
MEM_MB_ CAS_L14
MEM_MB_ WE_L14
MEM_MB_ RAS_L14
MEM_MB_ BANK214 MEM_MB_ BANK114 MEM_MB_ BANK014
MEM_MB_ CKE114 MEM_MB_ CKE014
MEM_MB_ ADD[15 ..0]14
MEM_MB_ DQS_H[8 ..0]14
MEM_MB_ DQS_L [8..0]14
MEM_MB_ DM[8..0]14
MEM_MB_ ADD[15 ..0] MEM_MB_ ADD15 MEM_MB_ ADD14 MEM_MB_ ADD13 MEM_MB_ ADD12 MEM_MB_ ADD11 MEM_MB_ ADD10 MEM_MB_ ADD9 MEM_MB_ ADD8 MEM_MB_ ADD7 MEM_MB_ ADD6 MEM_MB_ ADD5 MEM_MB_ ADD4 MEM_MB_ ADD3 MEM_MB_ ADD2 MEM_MB_ ADD1 MEM_MB_ ADD0
MEM_MB_ DQS_H[8 ..0] MEM_MB_ DQS_H7 MEM_MB_ DQS_L 7 MEM_MB_ DQS_H6 MEM_MB_ DQS_L 6 MEM_MB_ DQS_H5 MEM_MB_ DQS_L 5 MEM_MB_ DQS_H4 MEM_MB_ DQS_L 4 MEM_MB_ DQS_H3 MEM_MB_ DQS_L 3 MEM_MB_ DQS_H2 MEM_MB_ DQS_L 2 MEM_MB_ DQS_H1 MEM_MB_ DQS_L 1 MEM_MB_ DQS_H0 MEM_MB_ DQS_L 0
MEM_MB_ DQS_L [8..0] MEM_MB_ DM7 MEM_MB_ DM6 MEM_MB_ DM5 MEM_MB_ DM4 MEM_MB_ DM3 MEM_MB_ DM2 MEM_MB_ DM1 MEM_MB_ DM0
MEM_MB_ DM[8..0]
W29
MB_CLK_H4
W28
MB_CLK_L4
Y31
MB_CLK_H3
Y30
MB_CLK_L3
V31
MB_CLK_H2
W31
MB_CLK_L2
A18
MB_CLK_H1
A19
MB_CLK_L1
C19
MB_CLK_H0
D19
MB_CLK_L0
AE30
MB0_CS_L1
AC31
MB0_CS_L0
AF31
MB0_ODT1
AD29
MB0_ODT0
AE29
MB1_CS_L1
AB31
MB1_CS_L0
AG31
MB1_ODT1
AD31
MB1_ODT0
B19
MB_RESET_L
AC29
MB_CAS_L
AC30
MB_WE_L
AB29
MB_RAS_L
N31
MB_BANK2
AA31
MB_BANK1
AA28
MB_BANK0
M31
MB_CKE1
M29
MB_CKE0
N28
MB_ADD15
N29
MB_ADD14
AE31
MB_ADD13
N30
MB_ADD12
P29
MB_ADD11
AA29
MB_ADD10
P31
MB_ADD9
R29
MB_ADD8
R28
MB_ADD7
R31
MB_ADD6
R30
MB_ADD5
T31
MB_ADD4
T29
MB_ADD3
U29
MB_ADD2
U28
MB_ADD1
AA30
MB_ADD0
AK13
MB_DQS_H7
AJ13
MB_DQS_L7
AK17
MB_DQS_H6
AJ17
MB_DQS_L6
AK23
MB_DQS_H5
AL23
MB_DQS_L5
AL28
MB_DQS_H4
AL29
MB_DQS_L4
D31
MB_DQS_H3
C31
MB_DQS_L3
C24
MB_DQS_H2
C23
MB_DQS_L2
D17
MB_DQS_H1
C17
MB_DQS_L1
C14
MB_DQS_H0
C13
MB_DQS_L0
AJ14
MB_DM7
AH17
MB_DM6
AJ23
MB_DM5
AK29
MB_DM4
C30
MB_DM3
A23
MB_DM2
B17
MB_DM1
B13
MB_DM0
SOC KET AM3 9 41 SMD
SOC KET AM3 9 41 SMD
MEM CHB
MEM CHB
MB_DATA63 MB_DATA62 MB_DATA61 MB_DATA60 MB_DATA59 MB_DATA58 MB_DATA57 MB_DATA56 MB_DATA55 MB_DATA54 MB_DATA53 MB_DATA52 MB_DATA51 MB_DATA50 MB_DATA49 MB_DATA48 MB_DATA47 MB_DATA46 MB_DATA45 MB_DATA44 MB_DATA43 MB_DATA42 MB_DATA41 MB_DATA40 MB_DATA39 MB_DATA38 MB_DATA37 MB_DATA36 MB_DATA35 MB_DATA34 MB_DATA33 MB_DATA32 MB_DATA31 MB_DATA30 MB_DATA29 MB_DATA28 MB_DATA27 MB_DATA26 MB_DATA25 MB_DATA24 MB_DATA23 MB_DATA22 MB_DATA21 MB_DATA20 MB_DATA19 MB_DATA18 MB_DATA17 MB_DATA16 MB_DATA15 MB_DATA14 MB_DATA13 MB_DATA12 MB_DATA11 MB_DATA10
MB_DATA9 MB_DATA8 MB_DATA7 MB_DATA6 MB_DATA5 MB_DATA4 MB_DATA3 MB_DATA2 MB_DATA1 MB_DATA0
MB_DQS_H8 MB_DQS_L8
MB_CHECK7 MB_CHECK6 MB_CHECK5 MB_CHECK4 MB_CHECK3 MB_CHECK2 MB_CHECK1 MB_CHECK0
MB_EVENT_L
MB_DM8
AH13 AL13 AL15 AJ15 AF13 AG13 AL14 AK15 AL16 AL17 AK21 AL21 AH15 AJ16 AH19 AL20 AJ22 AL22 AL24 AK25 AJ21 AH21 AH23 AJ24 AL27 AK27 AH31 AG30 AL25 AL26 AJ30 AJ31 E31 E30 B27 A27 F29 F31 A29 A28 A25 A24 C22 D21 A26 B25 B23 A22 B21 A20 C16 D15 C21 A21 A17 A16 B15 A14 E13 F13 C15 A15 A13 D13
J31 J30
J29
K29 K31 G30 G29 L29 L28 H31 G31
V29
MEM_MB_ DATA[0 ..63] MEM_MB_ DATA6 3 MEM_MB_ DATA6 2 MEM_MB_ DATA6 1 MEM_MB_ DATA6 0 MEM_MB_ DATA5 9 MEM_MB_ DATA5 8 MEM_MB_ DATA5 7 MEM_MB_ DATA5 6 MEM_MB_ DATA5 5 MEM_MB_ DATA5 4 MEM_MB_ DATA5 3 MEM_MB_ DATA5 2 MEM_MB_ DATA5 1 MEM_MB_ DATA5 0 MEM_MB_ DATA4 9 MEM_MB_ DATA4 8 MEM_MB_ DATA4 7 MEM_MB_ DATA4 6 MEM_MB_ DATA4 5 MEM_MB_ DATA4 4 MEM_MB_ DATA4 3 MEM_MB_ DATA4 2 MEM_MB_ DATA4 1 MEM_MB_ DATA4 0 MEM_MB_ DATA3 9 MEM_MB_ DATA3 8 MEM_MB_ DATA3 7 MEM_MB_ DATA3 6 MEM_MB_ DATA3 5 MEM_MB_ DATA3 4 MEM_MB_ DATA3 3 MEM_MB_ DATA3 2 MEM_MB_ DATA3 1 MEM_MB_ DATA3 0 MEM_MB_ DATA2 9 MEM_MB_ DATA2 8 MEM_MB_ DATA2 7 MEM_MB_ DATA2 6 MEM_MB_ DATA2 5 MEM_MB_ DATA2 4 MEM_MB_ DATA2 3 MEM_MB_ DATA2 2 MEM_MB_ DATA2 1 MEM_MB_ DATA2 0 MEM_MB_ DATA1 9 MEM_MB_ DATA1 8 MEM_MB_ DATA1 7 MEM_MB_ DATA1 6 MEM_MB_ DATA1 5 MEM_MB_ DATA1 4 MEM_MB_ DATA1 3 MEM_MB_ DATA1 2 MEM_MB_ DATA1 1 MEM_MB_ DATA1 0 MEM_MB_ DATA9 MEM_MB_ DATA8 MEM_MB_ DATA7 MEM_MB_ DATA6 MEM_MB_ DATA5 MEM_MB_ DATA4 MEM_MB_ DATA3 MEM_MB_ DATA2 MEM_MB_ DATA1 MEM_MB_ DATA0
MEM_MB_ DQS_H8 MEM_MB_ DQS_L 8
MEM_MB_ DM8
MEM_MB_ CHECK[7 ..0] MEM_MB_ CHECK7 MEM_MB_ CHECK6 MEM_MB_ CHECK5 MEM_MB_ CHECK4 MEM_MB_ CHECK3 MEM_MB_ CHECK2 MEM_MB_ CHECK1 MEM_MB_ CHECK0
CR4 2 1 K 0402CR42 1K 0 402
MEM_MB_ DATA[0 ..63] 14
MEM_MB_ CHECK[7 ..0] 14
MEM_MB_ EVENT_ L 14
+1.5V _SUS
Title
Title
Title
Size Doc ument Number Rev
Size Doc ument Number Rev
Size Doc ument Number Rev
Custo m
Custo m
Custo m
Date: Shee t
Date: Shee t
Date: Shee t
K8 CPU MEMORY-2
K8 CPU MEMORY-2
K8 CPU MEMORY-2
A78LD-M3S
A78LD-M3S
A78LD-M3S
9 45Thursday, A pril 21, 20 11
9 45Thursday, A pril 21, 20 11
9 45Thursday, A pril 21, 20 11
of
of
of
7.1
7.1
7.1
5
544332211
DCCBBAA
D
+V_C PU
CPU1 E
CPU1 E
B3
VDD_1
C2
VDD_2
C4
VDD_3
D3
VDD_4
D5
VDD_5
E4
VDD_6
E6
VDD_7
F5
VDD_8
F7
VDD_9
G6
VDD_10
G8
VDD_11
H7
VDD_12
H11
VDD_13
H23
VDD_14
J8
VDD_15
J12
VDD_16
J14
VDD_17
J16
VDD_18
J18
VDD_19
J20
VDD_20
J22
VDD_21
J24
VDD_22
K7
VDD_23
K9
VDD_24
K11
VDD_25
K13
VDD_26
K15
VDD_27
K17
VDD_28
K19
VDD_29
K21
VDD_30
K23
VDD_31
L4
VDD_32
L5
VDD_33
L8
VDD_34
L10
VDD_35
L12
VDD_36
L14
VDD_37
L16
VDD_38
L18
VDD_39
L20
VDD_40
L22
VDD_41
M2
VDD_42
M3
VDD_43
M7
VDD_44
M9
VDD_45
M11
VDD_46
M13
VDD_47
M15
VDD_48
M17
VDD_49
M19
VDD_50
M21
VDD_51
M23
VDD_52
N8
VDD_53
N10
VDD_54
N12
VDD_55
N14
VDD_56
N16
VDD_57
N18
VDD_58
N20
VDD_59
N22
VDD_60
P7
VDD_61
P9
VDD_62
P11
VDD_63
P13
VDD_64
P15
VDD_65
P17
VDD_66
P19
VDD_67
P21
VDD_68
P23
VDD_69
R4
VDD_70
R5
VDD_71
R8
VDD_72
R10
VDD_73
R12
VDD_74
R14
VDD_75
R16
VDD_76
R18
VDD_77
R20
VDD_78
R22
VDD_79
T2
VDD_80
T3
VDD_81
T7
VDD_82
T9
VDD_83
T11
VDD_84
T13
VDD_85
SOC KET AM3 9 41 SMD
SOC KET AM3 9 41 SMD
POWER/GND1
POWER/GND1
VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8
VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85
A3 A7 A9 A11 B4 B9 B11 B14 B16 B18 B20 B22 B24 B26 B28 B30 C3 D14 D16 D18 D20 D22 D24 D26 D28 D30 E11 F4 F14 F16 F18 F20 F22 F24 F26 F28 F30 G9 G11 H8 H10 H12 H14 H16 H18 H24 H26 H28 H30 J4 J5 J7 J9 J11 J13 J15 J17 J19 J21 J23 K2 K3 K8 K10 K12 K14 K16 K18 K20 K22 K24 K26 K28 K30 L7 L9 L11 L13 L15 L17 L19 L21 L23 M8 M10
+V_C PU
CPU1 F
CPU1 F
T15
VDD_86
T17
VDD_87
T19
VDD_88
T21
VDD_89
T23
VDD_90
U8
VDD_91
U10
VDD_92
U12
VDD_93
U14
VDD_94
U16
VDD_95
U18
VDD_96
U20
VDD_97
U22
VDD_98
V9
VDD_99
V11
VDD_100
V13
VDD_101
V15
VDD_102
V17
VDD_103
V19
VDD_104
V21
VDD_105
V23
VDD_106
W4
VDD_107
W5
VDD_108
W8
VDD_109
W10
VDD_110
W12
VDD_111
W14
VDD_112
W16
VDD_113
W18
VDD_114
W20
VDD_115
W22
VDD_116
Y2
VDD_117
Y3
VDD_118
Y7
VDD_119
Y9
VDD_120
Y11
VDD_121
Y13
VDD_122
Y15
VDD_123
Y17
VDD_124
Y19
VDD_125
Y21
VDD_126
Y23
VDD_127
AA8
VDD_128
AA10
VDD_129
AA12
VDD_130
AA14
VDD_131
AA16
VDD_132
AA18
VDD_133
AA20
VDD_134
AA22
VDD_135
AB7
VDD_136
AB9
VDD_137
AB11
VDD_138
AB13
VDD_139
AB15
VDD_140
AB17
VDD_141
AB19
VDD_142
AB21
VDD_143
AB23
VDD_144
AC4
VDD_145
AC5
VDD_146
AC8
VDD_147
AC10
VDD_148
AC12
VDD_149
AC14
VDD_150
AC16
VDD_151
AC18
VDD_152
AC20
VDD_153
AC22
VDD_154
AD2
VDD_155
AD3
VDD_156
AD7
VDD_157
AD9
VDD_158
AD11
VDD_159
AD23
VDD_160
AE10
VDD_161
AE12
VDD_162
AF7
VDD_163
AF9
VDD_164
AF11
VDD_165
AG4
VDD_166
AG5
VDD_167
AG7
VDD_168
AH2
VDD_169
AH3
VDD_170
SOC KET AM3 9 41 SMD
SOC KET AM3 9 41 SMD
POWER/GND2
POWER/GND2
VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98
VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170
M12 M14 M16 M18 M20 M22 N4 N5 N7 N9 N11 N13 N15 N17 N19 N21 N23 P2 P3 P8 P10 P12 P14 P16 P18 P20 P22 R7 R9 R11 R13 R15 R17 R19 R21 R23 T8 T10 T12 T14 T16 T18 T20 T22 U4 U5 U7 U9 U11 U13 U15 U17 U19 U21 U23 V2 V3 V10 V12 V14 V16 V18 V20 V22 W7 W9 W11 W13 W15 W17 W19 W21 W23 Y8 Y10 Y12 Y14 Y16 Y18 Y20 Y22 AA4 AA5 AA7 AA9
+V_C PU
CPU1 G
CPU1 G
A4
VDDNB_1
A6
VDDNB_2
B5
VDDNB_3
B7
VDDNB_4
C6
VDDNB_5
C8
VDDNB_6
D7
VDDNB_7
D9
VDDNB_8
E8
VDDNB_9
E10
VDDNB_10
F9
VDDNB_11
F11
VDDNB_12
G10
VDDNB_13
G12
VDDNB_14
B2
NP/RSVD
H20
NP/VSS1
AE7
NP/VSS2
SOC KET AM3 9 41 SMD
SOC KET AM3 9 41 SMD
+1.2V _HT
CC7
CC7 1UF 16 V 0805 Y5V /NI
1UF 16 V 0805 Y5V /NI
1 2
+1.2V _HT
12
CC1 2
CC1 2 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
POWER/GND3
POWER/GND3
CC9
CC9 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
1 2
12
CC1 3
CC1 3 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214
AA11 AA13 AA15 AA17 AA19 AA21 AA23 AB2 AB3 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC7 AC9 AC11 AC13 AC15 AC17 AC19 AC21 AC23 AD8 AD10 AD12 AD14 AD16 AD20 AD22 AD24 AE4 AE5 AE11 AF2 AF3 AF8 AF10 AF12 AF14 AF16
12
12
+1.2V _HT
+1.5V _SUS
CC1 0
CC1 0 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
C2
C2 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
+1.2V _HT
+1.2V _HT
CC8
CC8 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
1 2
VLDT_B_1 VLDT_B_2 VLDT_B_3 VLDT_B_4
VDDR_5 VDDR_6 VDDR_7 VDDR_8 VDDR_9
VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242
+1.2V _HT
H1 H2 H5 H6
AG12 AH12 AJ12 AK12 AL12
AF18 AF20 AF22 AF24 AF26 AF28 AG10 AG11 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH30 AK2 AK14 AK16 AK18 AK20 AK22 AK24 AK26 AK28 AK30 AL5
10 45Thursday, Ap ril 21, 2011
10 45Thursday, Ap ril 21, 2011
10 45Thursday, Ap ril 21, 2011
+1.2V _HT
of
of
of
CPU1 H
CPU1 H
AJ1
VLDT_A_1
AJ2
VLDT_A_2
AJ3
VLDT_A_3
AJ4
VLDT_A_4
A12
VDDR_1
B12
VDDR_2
C12
VDDR_3
D12
VDDR_4
M24
VDDIO_1
M26
VDDIO_2
M28
VDDIO_3
M30
VDDIO_4
P24
VDDIO_5
P26
VDDIO_6
P28
VDDIO_7
P30
VDDIO_8
T24
VDDIO_9
T26
VDDIO_10
T28
VDDIO_11
T30
VDDIO_12
V25
VDDIO_13
V26
VDDIO_14
V28
VDDIO_15
V30
VDDIO_16
Y24
VDDIO_17
Y26
VDDIO_18
Y28
VDDIO_19
Y29
VDDIO_20
AB24
VDDIO_21
AB26
VDDIO_22
AB28
VDDIO_23
AB30
VDDIO_24
AC24
VDDIO_25
AD26
VDDIO_26
AD28
VDDIO_27
AD30
VDDIO_28
AF30
VDDIO_29
SOC KET AM3 9 41 SMD
SOC KET AM3 9 41 SMD
Title
Title
Title
Size Doc ument Number Re v
Size Doc ument Number Re v
Size Doc ument Number Re v
Custo m
Custo m
Custo m
Date: Shee t
Date: Shee t
Date: Shee t
POWER/GND4
POWER/GND4
K8 CPU POWER
K8 CPU POWER
K8 CPU POWER
A78LD-M3S
A78LD-M3S
A78LD-M3S
7.1
7.1
7.1
544332211
DCCBBAA
+1.5V _SUS
5
D
12
CC3 5
CC3 5 1UF 10 V Y5V 04 02
1UF 10 V Y5V 04 02
+1.5V _SUS
+1.5V _SUS
+1.5V _SUS
PLACE BOTTOM SIDE
12
CC1 5
CC1 5 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
DECOUPLING BETWEEN PROCESSOR AND DIMMS
12
CC2 1
CC2 1 1UF 10 V Y5V 04 02
1UF 10 V Y5V 04 02
12
C14 3
C14 3 1UF 16 V 0805 Y5V /NI
1UF 16 V 0805 Y5V /NI
12
CC3 6
CC3 6 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
12
CC1 6
CC1 6 1UF 10 V Y5V 04 02
1UF 10 V Y5V 04 02
12
CC5 1
CC5 1 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
12
CC2 5
CC2 5 1UF 16 V 0805 Y5V /NI
1UF 16 V 0805 Y5V /NI
Bottom side
+V_C PU
12
CC3 7
CC3 7 1UF 10 V Y5V 04 02
1UF 10 V Y5V 04 02
12
CC1 9
CC1 9 1UF 10 V Y5V 04 02
1UF 10 V Y5V 04 02
12
CC5 3
CC5 3 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
12
CC4 7
CC4 7 1UF 16 V 0805 Y5V /NI
1UF 16 V 0805 Y5V /NI
12
CC3 8
CC3 8 1UF 16 V 0805 Y5V /NI
1UF 16 V 0805 Y5V /NI
+V_C PU
12
CC2 4
CC2 4 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
+V_C PU
12
CC5 5
CC5 5 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
12
CC3 9
CC3 9 1UF 16 V 0805 Y5V /NI
1UF 16 V 0805 Y5V /NI
12
CC2 6
CC2 6 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
12
CC5 6
CC5 6 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
12
CC4 0
CC4 0 1UF 16 V 0805 Y5V /NI
1UF 16 V 0805 Y5V /NI
12
CC4 8
CC4 8 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
12
CC5 7
CC5 7 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
12
CC4 1
CC4 1 1UF 16 V 0805 Y5V /NI
1UF 16 V 0805 Y5V /NI
12
CC4 9
CC4 9 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
12
CC5 8
CC5 8 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
12
CC4 2
CC4 2 1UF 16 V 0805 Y5V /NI
1UF 16 V 0805 Y5V /NI
12
CC5 0
CC5 0 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
12
CC5 9
CC5 9 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
12
CC4 3
CC4 3 1UF 16 V 0805 Y5V /NI
1UF 16 V 0805 Y5V /NI
12
CC5 4
CC5 4 1UF 16 V 0805 Y5V
1UF 16 V 0805 Y5V
12
CC4 4
CC4 4 1UF 16 V 0805 Y5V /NI
1UF 16 V 0805 Y5V /NI
12
CC4 5
CC4 5 1UF 16 V 0805 Y5V /NI
1UF 16 V 0805 Y5V /NI
12
CC4 6
CC4 6 1UF 16 V 0805 Y5V /NI
1UF 16 V 0805 Y5V /NI
Title
Title
Title
Size Doc ument Number Re v
Size Doc ument Number Re v
Size Doc ument Number Re v
Custo m
Custo m
Custo m
Date: Shee t of
Date: Shee t
Date: Shee t
CPU DECPOULING CAP
CPU DECPOULING CAP
CPU DECPOULING CAP
A78LD-M3S
A78LD-M3S
A78LD-M3S
of
of
11 45Thursday, Ap ril 21, 2011
11 45Thursday, Ap ril 21, 2011
11 45Thursday, Ap ril 21, 2011
7.1
7.1
7.1
5
4
3
2
1
DDR3_A1
DDR3_A1A
DDR3_A1A
6
DQS0-
7
DQS0
15
DQS1-
16
DQS1
24
DQS2-
25
DQS2
33
DQS3-
34
DQS3
84
DQS4-
85
DQS4
93
DQS5-
94
DQS5
102
DQS6-
103
DQS6
111
DQS7-
112
DQS7
42
DQS8-
43
DQS8
125
DM0/DQS9
126
DQS9-
134
DM1/DQS1 0
135
DQS10-
143
DM2/DQS1 1
144
DQS11-
152
DM3/DQS1 2
153
DQS12-
203
DM4/DQS1 3
204
DQS13-
212
DM5/DQS1 4
213
DQS14-
221
DM6/DQS1 5
222
DQS15-
230
DM7/DQS1 6
231
DQS16-
161
DM8/DQS1 7
162
DQS17-
39
CB0
40
CB1
45
CB2
46
CB3
158
CB4
159
CB5
164
CB6
165
CB7
79
RSVD
238
SDA
118
SCL
188
A0
181
A1
61
A2
180
A3
59
A4
58
A5
178
A6
56
A7
177
A8
175
A9
70
A10
55
A11
174
A12
196
A13
172
A14
171
A15
DDR3-240 PIN-R
DDR3-240 PIN-R
DC4
DC4
0.1UF 16V Y5V 0402 /NI
0.1UF 16V Y5V 0402 /NI
4
BLACK
BLACK
NC/PAR_IN
NC/ERR_OUT
DC5
DC5 1UF 10V Y5V 0402
1UF 10V Y5V 0402
DQ63 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 DQ55 DQ54 DQ53 DQ52 DQ51 DQ50 DQ49 DQ48 DQ47 DQ46 DQ45 DQ44 DQ43 DQ42 DQ41 DQ40 DQ39 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
NC/TEST4
234 233 228 227 115 114 109 108 225 224 219 218 106 105 100 99 216 215 210 209 97 96 91 90 207 206 201 200 88 87 82 81 156 155 150 149 37 36 31 30 147 146 141 140 28 27 22 21 138 137 132 131 19 18 13 12 129 128 123 122 10 9 4 3
68 53 167
MEM_MA_DATA[0..63] MEM_MA_DATA63 MEM_MA_DATA62 MEM_MA_DATA61MEM_MA_DQS_L1 MEM_MA_DATA60 MEM_MA_DATA59 MEM_MA_DATA58 MEM_MA_DATA57 MEM_MA_DATA56 MEM_MA_DATA55 MEM_MA_DATA54 MEM_MA_DATA53 MEM_MA_DATA52 MEM_MA_DATA51 MEM_MA_DATA50 MEM_MA_DATA49 MEM_MA_DATA48 MEM_MA_DATA47 MEM_MA_DATA46 MEM_MA_DATA45 MEM_MA_DATA44 MEM_MA_DATA43 MEM_MA_DATA42 MEM_MA_DATA41 MEM_MA_DATA40 MEM_MA_DATA39 MEM_MA_DATA38 MEM_MA_DATA37 MEM_MA_DATA36
MEM_MA_DATA34 MEM_MA_DATA33 MEM_MA_DATA32 MEM_MA_DATA31 MEM_MA_DATA30 MEM_MA_DATA29 MEM_MA_DATA28 MEM_MA_DATA27 MEM_MA_DATA26 MEM_MA_DATA25 MEM_MA_DATA24 MEM_MA_DATA23 MEM_MA_DATA22 MEM_MA_DATA21 MEM_MA_DATA20 MEM_MA_DATA19 MEM_MA_DATA18 MEM_MA_DATA17 MEM_MA_DATA16 MEM_MA_DATA15 MEM_MA_DATA14 MEM_MA_DATA13 MEM_MA_DATA12 MEM_MA_DATA11 MEM_MA_DATA10 MEM_MA_DATA9 MEM_MA_DATA8 MEM_MA_DATA7 MEM_MA_DATA6 MEM_MA_DATA5 MEM_MA_DATA4 MEM_MA_DATA3 MEM_MA_DATA2 MEM_MA_DATA1 MEM_MA_DATA0
+1.5V_SUS
DR4
DR4
16.9 1% 0402
16.9 1% 0402
DIMM_CA_VREF
DR8
DR8
16.9 1% 0402
16.9 1% 0402
MEM_MA_DATA[0..63] 8
DC6
DC6 1UF 10V Y5V 0402
1UF 10V Y5V 0402
3
DIMM_CA_VREF14 DIMM_DQ_VREF14
MEM_MA_CKE08 MEM_MA_CKE18
MEM_MA_BANK08 MEM_MA_BANK18 MEM_MA_BANK28
MEM_MA_RESET_L8
MEM_MA_WE_L8 MEM_MA_RAS_L8 MEM_MA_CAS_L8
MEM_MA0_CS_L08 MEM_MA0_CS_L18
MEM_MA0_ODT08 MEM_MA0_ODT18
MEM_MA0_CLK_L18 MEM_MA0_CLK_H18 MEM_MA0_CLK_L08 MEM_MA0_CLK_H08
MEM_MA_EVENT_L8
DC7
DC7
0.1UF 16V Y5V 0402 /NI
0.1UF 16V Y5V 0402 /NI
SDATA14,20,22 SCLK14,20,22
MEM_MA_DQS_L[8..0] MEM_MA_DQS_H[8..0]
MEM_MA_DQS_L0 MEM_MA_DQS_H0
MEM_MA_DQS_H1 MEM_MA_DQS_L2 MEM_MA_DQS_H2 MEM_MA_DQS_L3 MEM_MA_DQS_H3 MEM_MA_DQS_L4 MEM_MA_DQS_H4 MEM_MA_DQS_L5 MEM_MA_DQS_H5 MEM_MA_DQS_L6 MEM_MA_DQS_H6 MEM_MA_DQS_L7 MEM_MA_DQS_H7 MEM_MA_DQS_L8 MEM_MA_DQS_H8
MEM_MA_DM[8..0] MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3 MEM_MA_DATA35
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7
MEM_MA_DM8
MEM_MA_CHECK[7..0] MEM_MA_CHECK0 MEM_MA_CHECK1 MEM_MA_CHECK2 MEM_MA_CHECK3 MEM_MA_CHECK4 MEM_MA_CHECK5 MEM_MA_CHECK6 MEM_MA_CHECK7
MEM_MA_ADD[15..0] MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15
DC3
DC3DR6 1UF 10V Y5V 0402
1UF 10V Y5V 0402
MEM_MA_DQS_L[8..0]8 MEM_MA_DQS_H[8..0]8
D D
MEM_MA_DM[8..0]8
C C
MEM_MA_CHECK[7..0]8
MEM_MA_ADD[15..0]8
B B
MEM_VTT
DC2
DC2 1UF 16V 0805 Y5V
A A
1UF 16V 0805 Y5V
1 2
+1.5V_SUS
DR2
DR2
16.9 1% 0402
16.9 1% 0402
DIMM_DQ_VREF
DR6
16.9 1% 0402
16.9 1% 0402
5
+1.5V_SUS
+3.3V
DIMM_CA_VREF
DIMM_DQ_VREF
DDR3_A1B
DDR3_A1B
51
VDDQ1 (P)
54
VDDQ2 (P)
57
VDDQ3 (P)
60
VDDQ4 (P)
62
VDDQ5 (P)
65
VDDQ6 (P)
66
VDDQ7 (P)
69
VDDQ8 (P)
72
VDDQ9 (P)
75
VDDQ10 (P)
78
VDDQ11 (P)
170
VDD1 (P)
173
VDD2 (P)
176
VDD3 (P)
179
VDD4 (P)
182
VDD5 (P)
183
VDD6 (P)
186
VDD7(P)
189
VDD8(P)
191
VDD9(P)
194
VDD10(P)
197
VDD11(P)
236
VDDSPD(P)
67
VREFCA
1
VREFDQ
117
SA0
237
SA1
50
CKE0
169
CKE1
71
BA0
190
BA1
52
A16/BA2
168
RESET
73
WE-
192
RAS-
74
CAS-
193
S-0
76
S-1
195
ODT0
77
ODT1
64
CK-1
63
CK1
185
CK-0
184
CK0
48
FREE1
49
FREE2
187
FREE3
198
FREE4
DDR3-240 PIN-R
DDR3-240 PIN-R
DC8
DC8 1UF 10V Y5V 0402
1UF 10V Y5V 0402
2
2
VSS1(P)
5
VSS2(P)
8
VSS3(P)
11
VSS4(P)
14
VSS5(P)
17
VSS6(P)
20
VSS7(P)
23
VSS8(P)
26
VSS9(P)
29
VSS10(P)
32
VSS11(P)
35
VSS12(P)
38
VSS13(P)
41
VSS60(P)
44
VSS14(P)
47
VSS15(P)
80
VSS16(P)
83
VSS17(P)
86
VSS18(P)
92
VSS19(P)
95
VSS20(P)
98
VSS21(P)
101
VSS22(P)
104
VSS23(P)
107
VSS24(P)
110
VSS25(P)
113
VSS26(P)
116
VSS27(P)
119
SA2
121
VSS29(P)
124
VSS30(P)
127
VSS31(P)
130
VSS32(P)
133
VSS33(P)
136
VSS34(P)
139
VSS35(P)
142
VSS36(P)
145
VSS37(P)
148
VSS38(P)
151
VSS39(P)
154
VSS40(P)
157
VSS41(P)
160
VSS42(P)
163
VSS43(P)
166
VSS44(P)
199
VSS45(P)
202
VSS46(P)
205
VSS47(P)
208
VSS48(P)
211
VSS49(P)
214
VSS50(P)
217
VSS51(P)
220
VSS52(P)
223
VSS53(P)
226
VSS54(P)
229
VSS55(P)
232
VSS56(P)
235
VSS57(P)
239
VSS58(P)
89
VSS59(P)
120
VTT
240
VTT
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
MEM_VTT
DC1
DC1
0.1UF 16V Y5V 0402 /NI
0.1UF 16V Y5V 0402 /NI
1 2
DDR DIMM-1
DDR DIMM-1
DDR DIMM-1
A78LD-M3S
A78LD-M3S
A78LD-M3S
1
7.1
7.1
7.1
13 45Thursday, April 21, 2011
13 45Thursday, April 21, 2011
13 45Thursday, April 21, 2011
5
4
3
2
1
MEM_MB_DQS_L[8..0]9
MEM_MB_DQS_H[8..0]9
D D
MEM_MB_DM[8..0]9
C C
MEM_MB_CHECK[7..0]9
SDATA13,20,22 SCLK13,20,22
MEM_MB_ADD[15..0]9
B B
MEM_MB_DQS_L[8..0] MEM_MB_DQS_H[8..0] MEM_MB_DQS_L0 MEM_MB_DQS_H0 MEM_MB_DQS_L1 MEM_MB_DQS_H1 MEM_MB_DQS_L2 MEM_MB_DQS_H2 MEM_MB_DQS_L3 MEM_MB_DQS_H3 MEM_MB_DQS_L4 MEM_MB_DQS_H4
MEM_MB_DQS_H5 MEM_MB_DQS_L6 MEM_MB_DQS_H6 MEM_MB_DQS_L7 MEM_MB_DQS_H7 MEM_MB_DQS_L8 MEM_MB_DQS_H8
MEM_MB_DM[8..0] MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
MEM_MB_DM8
MEM_MB_CHECK[7..0] MEM_MB_CHECK0 MEM_MB_CHECK1 MEM_MB_CHECK2 MEM_MB_CHECK3 MEM_MB_CHECK4 MEM_MB_CHECK5 MEM_MB_CHECK6 MEM_MB_CHECK7
MEM_MB_ADD[15..0] MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15
DDR3_B1
DDR3_B1A
DDR3_B1A
6
DQS0-
7
DQS0
15
DQS1-
16
DQS1
24
DQS2-
25
DQS2
33
DQS3-
34
DQS3
84
DQS4-
85
DQS4
93
DQS5-
94
DQS5
102
DQS6-
103
DQS6
111
DQS7-
112
DQS7
42
DQS8-
43
DQS8
125
DM0/DQS9
126
DQS9-
134
DM1/DQS1 0
135
DQS10-
143
DM2/DQS1 1
144
DQS11-
152
DM3/DQS1 2
153
DQS12-
203
DM4/DQS1 3
204
DQS13-
212
DM5/DQS1 4
213
DQS14-
221
DM6/DQS1 5
222
DQS15-
230
DM7/DQS1 6
231
DQS16-
161
DM8/DQS1 7
162
DQS17-
39
CB0
40
CB1
45
CB2
46
CB3
158
CB4
159
CB5
164
CB6
165
CB7
79
RSVD
238
SDA
118
SCL
188
A0
181
A1
61
A2
180
A3
59
A4
58
A5
178
A6
56
A7
177
A8
175
A9
70
A10
55
A11
174
A12
196
A13
172
A14
171
A15
DDR3-240 PIN-R
DDR3-240 PIN-R
BLACK
BLACK
NC/PAR_IN
NC/ERR_OUT
DQ63 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 DQ55 DQ54 DQ53 DQ52 DQ51 DQ50 DQ49 DQ48 DQ47 DQ46 DQ45 DQ44 DQ43 DQ42 DQ41 DQ40 DQ39 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
NC/TEST4
MEM_MB_DATA[0..63]
MEM_MB_DATA63
234
MEM_MB_DATA62
233
MEM_MB_DATA61
228
MEM_MB_DATA60
227
MEM_MB_DATA59
115
MEM_MB_DATA58
114
MEM_MB_DATA57
109
MEM_MB_DATA56
108
MEM_MB_DATA55
225
MEM_MB_DATA54
224
MEM_MB_DATA53MEM_MB_DQS_L5
219
MEM_MB_DATA52
218
MEM_MB_DATA51
106
MEM_MB_DATA50
105
MEM_MB_DATA49
100
MEM_MB_DATA48
99
MEM_MB_DATA47
216
MEM_MB_DATA46
215
MEM_MB_DATA45
210
MEM_MB_DATA44
209
MEM_MB_DATA43
97
MEM_MB_DATA42
96
MEM_MB_DATA41
91
MEM_MB_DATA40
90
MEM_MB_DATA39
207
MEM_MB_DATA38
206
MEM_MB_DATA37
201
MEM_MB_DATA36
200
MEM_MB_DATA35
88
MEM_MB_DATA34
87
MEM_MB_DATA33
82
MEM_MB_DATA32
81
MEM_MB_DATA31
156
MEM_MB_DATA30
155
MEM_MB_DATA29
150
MEM_MB_DATA28
149
MEM_MB_DATA27
37
MEM_MB_DATA26
36
MEM_MB_DATA25
31
MEM_MB_DATA24
30
MEM_MB_DATA23
147
MEM_MB_DATA22
146
MEM_MB_DATA21
141
MEM_MB_DATA20
140
MEM_MB_DATA19
28
MEM_MB_DATA18
27
MEM_MB_DATA17
22
MEM_MB_DATA16
21
MEM_MB_DATA15
138
MEM_MB_DATA14
137
MEM_MB_DATA13
132
MEM_MB_DATA12
131
MEM_MB_DATA11
19
MEM_MB_DATA10
18
MEM_MB_DATA9
13
MEM_MB_DATA8
12
MEM_MB_DATA7
129
MEM_MB_DATA6
128
MEM_MB_DATA5
123
MEM_MB_DATA4
122
MEM_MB_DATA3
10
MEM_MB_DATA2
9
MEM_MB_DATA1
4
MEM_MB_DATA0
3
68 53 167
MEM_MB_DATA[0..63] 9
DIMM_CA_VREF13 DIMM_DQ_VREF13
MEM_MB_CKE09 MEM_MB_CKE19
MEM_MB_BANK09 MEM_MB_BANK19 MEM_MB_BANK29
MEM_MB_RESET_L9
MEM_MB_WE_L9 MEM_MB_RAS_L9 MEM_MB_CAS_L9
MEM_MB0_CS_L09 MEM_MB0_CS_L19
MEM_MB0_ODT09 MEM_MB0_ODT19
MEM_MB0_CLK_L19 MEM_MB0_CLK_H19 MEM_MB0_CLK_L09 MEM_MB0_CLK_H09
MEM_MB_EVENT_L9
+1.5V_SUS
+3.3V
DIMM_CA_VREF
DIMM_DQ_VREF
+3.3V
DDR3_B1B
DDR3_B1B
51 54 57 60 62 65 66 69 72 75
78 170 173 176 179 182 183 186 189 191 194 197 236
67
1
117 237
50 169
71 190
52
168
73 192
74 193
76
195
77
64
63 185 184
48
49 187 198
DDR3-240 PIN-R
DDR3-240 PIN-R
VDDQ1 (P) VDDQ2 (P) VDDQ3 (P) VDDQ4 (P) VDDQ5 (P) VDDQ6 (P) VDDQ7 (P) VDDQ8 (P) VDDQ9 (P) VDDQ10 (P) VDDQ11 (P) VDD1 (P) VDD2 (P) VDD3 (P) VDD4 (P) VDD5 (P) VDD6 (P) VDD7(P) VDD8(P) VDD9(P) VDD10(P) VDD11(P) VDDSPD(P)
VREFCA VREFDQ
SA0 SA1
CKE0 CKE1
BA0 BA1 A16/BA2
RESET WE­RAS­CAS­S-0 S-1
ODT0 ODT1
CK-1 CK1 CK-0 CK0
FREE1 FREE2 FREE3 FREE4
VSS1(P) VSS2(P) VSS3(P) VSS4(P) VSS5(P) VSS6(P) VSS7(P) VSS8(P)
VSS9(P) VSS10(P) VSS11(P) VSS12(P) VSS13(P) VSS60(P) VSS14(P) VSS15(P) VSS16(P) VSS17(P) VSS18(P) VSS19(P) VSS20(P) VSS21(P) VSS22(P) VSS23(P) VSS24(P) VSS25(P) VSS26(P) VSS27(P)
SA2 VSS29(P) VSS30(P) VSS31(P) VSS32(P) VSS33(P) VSS34(P) VSS35(P) VSS36(P) VSS37(P) VSS38(P) VSS39(P) VSS40(P) VSS41(P) VSS42(P) VSS43(P) VSS44(P) VSS45(P) VSS46(P) VSS47(P) VSS48(P) VSS49(P) VSS50(P) VSS51(P) VSS52(P) VSS53(P) VSS54(P) VSS55(P) VSS56(P) VSS57(P) VSS58(P) VSS59(P)
VTT
VTT
2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 80 83 86 92 95 98 101 104 107 110 113 116 119 121 124 127 130 133 136 139 142 145 148 151 154 157 160 163 166 199 202 205 208 211 214 217 220 223 226 229 232 235 239 89
120 240
MEM_VTT
DC9
DC9 1UF 10V Y5V 0402
1UF 10V Y5V 0402
1 2
MEM_VTT
DC11
DC10
A A
5
4
DC10 1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
1 2
DC11 1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
1 2
3
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
DDR DIMM-2
DDR DIMM-2
DDR DIMM-2
A78LD-M3S
A78LD-M3S
A78LD-M3S
1
7.1
7.1
7.1
14 45Thursday, April 21, 2011
14 45Thursday, April 21, 2011
14 45Thursday, April 21, 2011
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