Biostar A78LD-M2S Schematic REV 6.2
5
A
4
3
2
1
DD
PAGE
CC
BB
CONTENTS
1
COVER
2
BLOCK DIAGRAM
POWER DELIVERY
3
CLOCK DISTRIBUTION
4
5
REVISION HISTROY
6-10
SKT 940 K8 M2 CPU
11
CPU DECOUPLING
12
DDR CLK BYPASS
DDR2 DIMM A1
13
DDR2 DIMM B1
14
15
NONE
NONE
16
DDR2 VTT TERM
17
18
DDR2 DECOUPLING
19
RS760G-HT LINK
20
RS760G-PCIE
21
RS760G-SYSTEM
22
RS760G-PWOER&SBD_MEM
CLOCK GEN
23
24
SB710-PCIE/PCI/CPU/LPC
25
SB710-ACPI/GPIO/USB/AUD
26
SB710-SATA/IDE/HWM/SPI
27
SB710-POWER&DECOUPLING
28
SB710-STRAPS
29
CRT & DVI
30
PCI-E SLOT
31
PCI SLOT
32
IDE ATA 133
33
USB CONN
34
CODEC ALC662
35
AUDIO CONNECTOR
36
SUPER I/O ITE8718F
37
HW MONITOR / FAN CONTROL
38
FDD / PS2 CONN / FLASH
39
COM&LPT CONNECTOR
40
ATX PWR / FRONT PANEL / LED
41
OVER VOLTAGE IC
42
FRONT USB
43
PWRGD / MISC DC-DC
44
VCC_CORE DC-DC CONVER
45
MEMORY POWER
46
NB/SB CORE POWER
47
Realtek RTL8102EL
48
BOM
A78LD-M2S ( RS780L&SB710 )
REV 6.2
DDR2 X 2 Dual channel , PCI-Ex16 X 1 ,
PCI X 2 , Realtek 10/100 PCI-E Lan , AMD
K8-940
DATE :2010/03/04
A
Title
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Title
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Custom
Custom
Date:Sheet of
Date:Sheet of
Date:Sheet of
5
4
3
2
COVER
COVER
COVER
A78LD-M2S
A78LD-M2S
A78LD-M2S
1
6.2
6.2
148Thursday, March 04, 2010
148Thursday, March 04, 2010
148Thursday, March 04, 2010
6.2
5
A
4
3
2
1
UNBUFFERED
DDRII DIMM3
UNBUFFERED
DDRII DIMM4
DDRII SECOND LOGICAL DIMM
SATA#3
SATA#4 SATA#5
AZILIA
CODEC
SATA#0
IDE1
HW
MONITOR
UNBUFFERED
DDRII
DIMM1
UNBUFFERED
DDRII DIMM2
DDRII FIRST LOGICAL DIMM
SATA#1
SATA#2
AMD
AM2/AM2+
DD
Clock Generator
RTM880N-793
DVI/TMDS CON
VGA CON
PCIE
16X
SLOT1
HyperTransport
TMDS
16X
CC
GIGABIT
Realtek RTL8111C
USB-4
USB-7
USB-3
USB-8
USB-5
USB-6
BB
PCI SLOT #1
USB-2
USB-9
4 1X PCIE
INTERFACE
USB-1
USB-10 USB-11
PCI BUS
PCI SLOT #2
PCIE GPP0
X1
USB-0
BOOTSTRAPS
ROM (SB)
PCI SLOT #3
USB 2.0
I2C I/F
M2 SOCKET
LINK
OUT
AMD NB
RS760G
HyperTransport LINK0 CPU I/F
INTEGRATED GRAPHICS
LVTM
1 16X PCIE VIDEO I/F
1 1X PCIE I/F
ATI SB
SB710
USB2.0 (12)
SATA II (6)
AC97 2.3/ AZALIA
ATA 66/100/133
ACPI
LPC I/F
INT RTC
HW MONITOR
IN
4X
PCIE
16x16
DDRII 533,667,800
128bit
DDRII 533,667,800
SPI I/F
HD AUDIO I/F
SATA II I/F
ATA 66/100/133 I/F
SPI ROM
DESKTOP M2 POWER
RS760G
CORE & PCIE POWER
DDR MEMORY POWER
ITE LPC SIO 8716/8718
FLOPPY
KBD
MOUSE
HW
MONITOR
A
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Title
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Date:Sheet of
Date:Sheet of
Date:Sheet of
5
4
3
2
Custom
Custom
Custom
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
A78LD-M2S
A78LD-M2S
A78LD-M2S
1
6.2
6.2
248Thursday, March 04, 2010
248Thursday, March 04, 2010
248Thursday, March 04, 2010
6.2
5
A
ATX P/S WITH 1A STBY CURRENT
5VSB
+/-5%
5V
+/-5%
3.3V
+/-5%
12V
+/-5%
-12V
+/-5%
CPU
PW
12V
+/-5%
DD
VCC 1.1V SW
REGULATOR
+3.3VSB REGULATOR
ACPI CONTROLLER
CC
BB
4
+5VDUAL_MEM (S0,S5)
VCC 1.2V SW
REGULATOR
+3.3VSB (S0, S1, S3, S4, S5)
+3.3VDUAL (S0, S1, S3, S4, S5)
+5VDUAL (S0, S1, S3, S4, S5)
2.5V SHUNT
REGULATOR
VRM SW
REGULATOR
1.8V VDD SW
REGULATOR
VCC 1.1V SW
REGULATOR
3
0.9V VTT_DDR
REGULATOR
+1.1V RX780/RS780; +1.2V RS740 (S0, S1)
+1.1V RX780/RS780; +1.2V RS740 (S0, S1)
1.8V LINEAR
REGULATOR
1.2V STB LDO
REGULATOR
+1.8V(S0, S1)
+1.2V(S0, S1)
+1.2VSB (S5)
2
VDD_CPUCORE_RUN (S0, S1)/VDD_CPUNB_RUN (S0, S1)
DDRII DIMMs
VTT_DDR 2A
VDD MEM 12A
1.5V LINEAR
REGULATOR
+1.5V(S0, S1)
CPU_VDDA_RUN
CPU_VTT_SUS (S0,S1,S3)
CPU_VDDIO_SUS(S0,S1,S3)
(S0, S1)
AM2
VDDA 2.5V 0.2A
VDDCORE
0.8-1.55V 110A
DDRII MEM I/F
VTT 2A, VDD 10A
VLDT 1.2V 0.5A
RS780
VDDHT/RX 1.1V 1.2A
VDDHTTX 1.2V 0.5A
VDDPCIE 1.1V 2A
NB CORE VDDC
1.1V 7A
VDDA18PCIE 1.8V 0.9A
PLLs 1.8V 0.1A
VDD18/VDD18_MEM
1.8V 0.01A
VDD_MEM 1.8V/1.5V 0.5A
AVDD 3.3V 0.135A
SB700
X4 PCI-E 0.8A
ATA I/O 0.5A
ATA PLL 0.01A
PCI-E PVDD 80mA
SB CORE 0.6A
CLOCK
1.2V S5 PW 0.22A
3.3V S5 PW 0.01A
USB CORE I/O 0.2A
3.3V I/O 0.45A
AZALIA CODEC CON
3.3V CORE 0.3A
5V ANALOG 0.1A
12V 0.1A
1
X1 PCIE per
3.3V
12V
3.3Vaux
3.0A
0.5A
0.1A
3.3V
12V
5.0A
7.6A5VDual
0.375A
0.1A
4
3.0A
5.5A
X16 PCIE
3.3V
12V
5.5A
USB X6 FR
VDD 3.0A
5VDual
2.0A0.5A
3
USB X6 RL
VDD
2.0A
2XPS/2
5VDual
1.0A
GBE
3.3V 0.5A (S0, S1)
3.3V 0.1A (S3)
2
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SizeDocument NumberRev
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Custom
Custom
Date:Sheet of
Date:Sheet of
Date:Sheet of
POWER DELIVERY
POWER DELIVERY
POWER DELIVERY
A78LD-M2S
A78LD-M2S
A78LD-M2S
348Thursday, March 04, 2010
348Thursday, March 04, 2010
348Thursday, March 04, 2010
1
A
6.2
6.2
6.2
+3.3VDUAL (S0, S1, S3)
5
PCI Slot (per slot) X16 PCIE
5V
3.3V
12V
3.3Vaux
-12V
5
A
4
3
2
1
DIMM3
DD
DIMM1
3 PAIR MEM CLK
3 PAIR MEM CLK
AM2/AM2g2 CPU
AM2 SOCKET
CC
BB
DIMM4
1 PAIR CPU CLK
DIMM2
3 PAIR MEM CLK
3 PAIR MEM CLK
1 PAIR CPU CLK
200MHZ
EXTERNAL
CLK GEN.
HT REFCLK
66MHz SE(RS740)
100MHz
DIFF(RX780/RS780)
14.318MHZ OSC
(RS740/RX780)
NB-OSCIN
14.318MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
NB GFX PCIE CLK
100MHZ
NB GPP PCIE CLK
100MHZ
PCIE GFX CLK
100MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
USB CLK
48MHZ
SIO CLK
48MHZ
AMD NB
RS740/RX780/RS780
(RX780)
PCIE GFX SLOT 1 - 16 LANES
PCIE GPP SLOT 1 - 1 LANE
PCIE GPP SLOT 2 - 4 LANES
PCIE GBE
25MHZ OSC INPUT
200MHZ
HT ref clock
100MHZ DIFF(RX780/RS780)
HT REFCLK
66MHz SE(RS740)
NB PCIE Ref clock
100MHZ
NB Disp clock
100MHZ DIFF(RS780)
GPP Ref clock
100MHZ
GFX Ref clock
100MHZ
GPP Ref clock
100MHZ
GPP Ref clock
100MHZ
GPP Ref clock
100MHZ
SATA
25MHz
CPU_HT_CLK
NB_HT_CLK
25M_48M_66M_OSC
AMD SB
SB700
NB_DISP_CLK
GPP_CLK3
PCIE_RCLK/
NB_LNK_CLK
SLT_GFX_CLK
GPP_CLK0
GPP_CLK1
GPP_CLK2
USB_CLK
SB_BITCLK
48MHZ
PCI CLK0
33MHZ
PCI CLK1
33MHZ
PCI CLK2
33MHZ
LPC_CLK0
LPC CLK1
PCI CLK3
PCI CLK4
25MHz
32.768KHz
33MHZ
33MHZ
33MHZ
33MHZ
PCI SLOT 0
PCI SLOT 1
PCI SLOT 2
TPM
LPC BIOS
DEBUG POST
SUPER IO
IT8716F
HD AUDIO CON
TPM (BCM5755/5761)
External clock mode
A
Internal clock mode
Title
Title
Title
CLOCK DISTRIBUTION
CLOCK DISTRIBUTION
CLOCK DISTRIBUTION
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Custom
Date:Sheet of
Date:Sheet of
Date:Sheet of
5
4
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A78LD-M2S
A78LD-M2S
A78LD-M2S
1
448Thursday, March 04, 2010
448Thursday, March 04, 2010
448Thursday, March 04, 2010
6.2
6.2
6.2
5
A
4
3
2
1
DD
CC
BB
A
Title
Title
Title
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
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Custom
Custom
Date:Sheet of
Date:Sheet of
Date:Sheet of
5
4
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REVISION HISTORY
REVISION HISTORY
REVISION HISTORY
A78LD-M2S
A78LD-M2S
A78LD-M2S
548Thursday, March 04, 2010
548Thursday, March 04, 2010
548Thursday, March 04, 2010
1
6.2
6.2
6.2
5
DCCBBAA
4
3
2
1
D
HT_CLKIN1_P19
HT_CLKIN1_N19
HT_CLKIN0_P19
HT_CLKIN0_N19
HT_CTLIN1_P19
HT_CTLIN1_N19
HT_CTLIN0_N19
HT_CADIN15_P19
HT_CADIN15_N19
HT_CADIN14_P19
HT_CADIN14_N19
HT_CADIN13_P19
HT_CADIN13_N19
HT_CADIN12_P19
HT_CADIN12_N19
HT_CADIN11_P19
HT_CADIN11_N19
HT_CADIN10_P19
HT_CADIN9_P19
HT_CADIN9_N19
HT_CADIN8_P19
HT_CADIN8_N19
HT_CADIN7_P19
HT_CADIN7_N19
HT_CADIN6_P19
HT_CADIN6_N19
HT_CADIN5_P19
HT_CADIN5_N19
HT_CADIN4_P19
HT_CADIN4_N19
HT_CADIN3_P19
HT_CADIN3_N19
HT_CADIN2_P19
HT_CADIN2_N19 HT_CADOUT2_N19
HT_CADIN1_P19
HT_CADIN1_N19
HT_CADIN0_P19
HT_CADIN0_N19
5
4
HyperTransport
CPU1A
CPU1A
HYPERTRANSPORT
L0_CLKIN_H(1)
P6
L0_CLKIN_L(1)
L0_CLKIN_H(0)
L0_CLKIN_L(0)
V4
L0_CTLIN_H(1)
V5
L0_CTLIN_L(1)
L0_CTLIN_H(0)
V1
L0_CTLIN_L(0)
L0_CADIN_H(15)
V6
L0_CADIN_L(15)
T4
L0_CADIN_H(14)
T5
L0_CADIN_L(14)
L0_CADIN_H(13)
T6
L0_CADIN_L(13)
P4
L0_CADIN_H(12)
P5
L0_CADIN_L(12)
L0_CADIN_H(11)
L0_CADIN_L(11)
L6
L0_CADIN_H(10)
L0_CADIN_L(10)
K4
L0_CADIN_H(9)
K5
L0_CADIN_L(9)
J6
L0_CADIN_H(8)
K6
L0_CADIN_L(8)
L0_CADIN_H(7)
L0_CADIN_L(7)
L0_CADIN_H(6)
T1
L0_CADIN_L(6)
L0_CADIN_H(5)
L0_CADIN_L(5)
L0_CADIN_H(4)
P1
L0_CADIN_L(4)
L1
L0_CADIN_H(3)
L0_CADIN_L(3)
L3
L0_CADIN_H(2)
L2
L0_CADIN_L(2)
J1
L0_CADIN_H(1)
K1
L0_CADIN_L(1)
J3
L0_CADIN_H(0)
J2
L0_CADIN_L(0)
SOCKET_M2 940 SMD
SOCKET_M2 940 SMD
HYPERTRANSPORT
L0_CLKOUT_H(1)
L0_CLKOUT_L(1)
L0_CLKOUT_H(0)
L0_CLKOUT_L(0)
L0_CTLOUT_H(1)
L0_CTLOUT_L(1)
L0_CTLOUT_H(0)
L0_CTLOUT_L(0)
L0_CADOUT_H(15)
L0_CADOUT_L(15)
L0_CADOUT_H(14)
L0_CADOUT_L(14)
L0_CADOUT_H(13)
L0_CADOUT_L(13)
L0_CADOUT_H(12)
L0_CADOUT_L(12)
L0_CADOUT_H(11)
L0_CADOUT_L(11)
L0_CADOUT_H(10)
L0_CADOUT_L(10)
L0_CADOUT_H(9)
L0_CADOUT_L(9)
L0_CADOUT_H(8)
L0_CADOUT_L(8)
L0_CADOUT_H(7)
L0_CADOUT_L(7)
L0_CADOUT_H(6)
L0_CADOUT_L(6)
L0_CADOUT_H(5)
L0_CADOUT_L(5)
L0_CADOUT_H(4)
L0_CADOUT_L(4)
L0_CADOUT_H(3)
L0_CADOUT_L(3)
L0_CADOUT_H(2)
L0_CADOUT_L(2)
L0_CADOUT_H(1)
L0_CADOUT_L(1)
L0_CADOUT_H(0)
L0_CADOUT_L(0)
N6
N3
N2
U1
U6
R6
M4
M5
M6
U3
U2
R1
R3
R2
N1
M1
AD5
AD4
AD1
AC1
Y6
W6
W2
W3
Y5
Y4
AB6
AA6
AB5
AB4
AD6
AC6
AF6
AE6
AF5
AF4
AH6
AG6
AH5
AH4
Y1
W1
AA2
AA3
AB1
AA1
AC2
AC3
AE2
AE3
AF1
AE1
AG2
AG3
AH1
AG1
3
HT_CLKOUT1_P19
HT_CLKOUT1_N19
HT_CLKOUT0_P19
HT_CLKOUT0_N19
HT_CTLOUT1_P19
HT_CTLOUT1_N19
HT_CTLOUT0_P19HT_CTLIN0_P19
HT_CTLOUT0_N19
HT_CADOUT15_P19
HT_CADOUT15_N19
HT_CADOUT14_P19
HT_CADOUT14_N19
HT_CADOUT13_P19
HT_CADOUT13_N19
HT_CADOUT12_P19
HT_CADOUT12_N19
HT_CADOUT11_P19
HT_CADOUT11_N19
HT_CADOUT10_P19
HT_CADOUT10_N19HT_CADIN10_N19
HT_CADOUT9_P19
HT_CADOUT9_N19
HT_CADOUT8_P19
HT_CADOUT8_N19
HT_CADOUT7_P19
HT_CADOUT7_N19
HT_CADOUT6_P19
HT_CADOUT6_N19
HT_CADOUT5_P19
HT_CADOUT5_N19
HT_CADOUT4_P19
HT_CADOUT4_N19
HT_CADOUT3_P19
HT_CADOUT3_N19
HT_CADOUT2_P19
HT_CADOUT1_P19
HT_CADOUT1_N19
HT_CADOUT0_P19
HT_CADOUT0_N19
Title
Title
Title
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
Custom
Custom
Custom
Date:Sheet of
Date:Sheet of
Date:Sheet of
2
K8 CPU HT
K8 CPU HT
K8 CPU HT
A78LD-M2S
A78LD-M2S
A78LD-M2S
1
6.2
6.2
648Thursday, March 04, 2010
648Thursday, March 04, 2010
648Thursday, March 04, 2010
6.2
5
A
4
3
2
1
+5V
Vout=Vref (1.25V) X ( 1+R2/R1 )=2.5V
CPU_ALL_PWROK
CPU_LDTSTOP#
CPU_HT_RESET#
CPU_PRESENT#
CPU_SIC
CPU_SID
CPU_CORE_FB
CPU_CORE_FB_
CPU_M_VREFF
Q86
Q86
2N3904 SOT23
2N3904 SOT23
CPU_HT_RESET#
C
CPU_VDDA
12
C2
C2
3300P 50V X7R 0402
3300P 50V X7R 0402
TEST19
TEST18
+1.8V
R561
R561
10K 1% 0402 /NI
10K 1% 0402 /NI
CPU1D
CPU1D
C10
VDDA1
D10
VDDA2
A8
CLKIN_H
B8
CLKIN_L
C9
PWROK
D8
LDTSTOP_L
C7
RESET_L
AL3
CPU_PRESENT_L
AL6
SIC
AK6
SID
AK4
CPU_SA0
AL10
TDI
AJ10
TRST_L
AH10
TCK
AL9
TMS
A5
DBREQ_L
G2
VDD_FB_H
G1
VDD_FB_L
E12
VTT_SENSE
F1
PSI_L
F12
M_VREF
AH11
M_ZN
AJ11
M_ZP
A10
TEST25_H
B10
TEST25_L
F10
TEST19
E9
TEST18
AJ7
TEST13
F6
TEST9
D6
TEST17
E7
TEST16
F8
TEST15
C5
TEST14
AH9
TEST12
E5
TEST7
AJ5
TEST6
AG9
THERMDC
AG8
THERMDA
AH7
TEST3
AJ6
TEST2
SOCKET_M2 940 SMD
SOCKET_M2 940 SMD
TEST22
TEST18
TEST21
TEST19
MISC
MISC
CORE_TYPE
THERMTRIP_L
PROCHOT_L
VDDIO_FB_H
VDDIO_FB_L
VDDNB_FB_H
VDDNB_FB_L
RN65
RN65
330 8P4R 0402
330 8P4R 0402
7 8
5 6
3 4
1 2
VID(5)
VID(4)
VID(3)
VID(2)
VID(1)
VID(0)
ALERT_
DBRDY
HTREF1
HTREF0
TEST29_H
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8
+1.8V_SUS
G5
D2
D1
C1
E3
E2
E1
AK7
AL7
CPU_TDO
AK10
TDO
ALERT
AL4
CPU_DBRDY
B6
AK11
AL11
G4
G3
R1144.2 1% 0402R1144.2 1% 0402
V8
R1344.2 1% 0402R1344.2 1% 0402
V7
FBCLKOUT
C11
FBCLKOUT_
D11
AK8
AH8
TEST22
AJ9
TEST21
AL8
AJ8
J10
H9
AK9
TEST26
AK5
G7
D4
5 6
7 8
CPU_THERMTRIP
TEST26
RN1
RN1
330 8P4R 0402
330 8P4R 0402
1 2
3 4
K8_VID1
CPU_P ROCHO T_L_1. 8
CPU_THERMTRIP
CPU_PROCHOT_L_1.8
Required for compatibility
with future processors
12
12
R1780.6 1% 0402R1780.6 1% 0402
+1.2V_HT
12
R541
R541
R542
R542
1K 1% 0402
1K 1% 0402
1K 1% 0402
ALERT
+1.8V_SUS
G
Q2
Q2
FDV301N SOT23
FDV301N SOT23
DS
R5320 0402 /NIR5320 0402 /NI
LAYOUT: PLACE WITHIN 1 INCH OF CPU
5/10
20/8/5/8/20
LAYOUT: PLACE WITHIN 1 INCH OF CPU
LAYOUT: ROUTE 80 OHM DIFF IMPEDENCE
1K 1% 0402
CPU_THERMTRIP#
R543
R543
1K 1% 0402
1K 1% 0402
K8_VID544
K8_VID444
K8_VID344
K8_VID244
K8_VID144
K8_VID044
+3.3V_DUAL
R382
R382
4.7K 0402 /NI
4.7K 0402 /NI
CPU_THERMTRIP#25
1 2
CPU_PROCHOT#24
CPU_TDO15
CPU_DBRDY15
ADO Extreme
A
DD
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
ROUTE AS DIF 20/5/5/5/20
LAYOUT: PLACE 169 OHM WITHIN
600mils OF CPU
AND TRACE TO AC CAPS LESS
THAN 1250mil
CC
16.9 1% 0402R616.9 1% 0402
BB
16.9 1% 0402
16.9 1% 0402
LDT_RST#21,24
SB_CPUPWRGD24
LDT_STOP#21,24
C533
C533
+1.8V_SUS
R6
1 2
12
R10
R10
LESS THAN 1000mil
5/10 M_ZN,M_ZP
CPU_HT_RESET#
CPU_ALL_PWROK
CPU_LDTSTOP#
+1.8V_SUS
12
Q1
Q1
AZ1117H-ADJ SOT-223
AZ1117H-ADJ SOT-223
R1
R1
OIA
100 1% 0402R1100 1% 0402
R4
R2
100 1% 0402R4100 1% 0402
CPU_CLKIN_P23
CPU_CLKIN_N23
ADO Extreme
Layout: keep trace to resistors less than 1" from CPU pins
CPU_M_VREFF
12
0.1UF 16V Y5V 0402
0.1UF 16V Y5V 0402
C6
C6
5 6
7 8
CPU_LDTSTOP#
CPU_HT_RESET#
CPU_DBREQ#
CPU_ALL_PWROK
RN4
RN4
330 8P4R 0402
330 8P4R 0402
1 2
3 4
12
C7
C7
1000P 50V X7R 0402
1000P 50V X7R 0402
CPU_PRESENT#25
CPU_TRST#15
CPU_DBREQ#15
+1.8V_SUS
12
CT1
CT1
10UF 10V 0805 Y5V
10UF 10V 0805 Y5V
+1.8V_SUS
CPU_TDI15
CPU_TCK15
CPU_TMS15
ACC FUNCTION
CPUCLK
CPUCLK#
IMC_CRST_L25
12
C3
C3
0.1UF 16V Y5V 0402
0.1UF 16V Y5V 0402
C4
C4
C53900P 50V X7R 0402 C53900P 50V X7R 0402
RN64
RN64
1K 8P4R 0402
1K 8P4R 0402
7 8
5 6
3 4
1 2
CPU_CORE_FB44
CPU_CORE_FB_44
CPU_THERMDC36,37
CPU_THERMDA36
R562
R562
10K 1% 0402 /NI
10K 1% 0402 /NI
12
C1
C1
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
3900P 50V X7R 0402
3900P 50V X7R 0402
12
R5
169 1% 0402R5169 1% 0402
12
1 2
CPU_SIC
CPU_SID
CPU_PRESENT#
CPU_TDI
CPU_TRST#
CPU_TCK
CPU_TMS
CPU_DBREQ#
R1239.2 1% 0402R1239.2 1% 0402
R1439.2 1% 0402R1439.2 1% 0402
R15510 0402R15510 0402
R16510 0402R16510 0402
+1.8V
+3.3V_DUAL
B
E
1 2
1 2
1 2
1 2
A
R560
R560
10K 0402
10K 0402
Title
Title
Title
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
Custom
Custom
Custom
Date:Sheet of
Date:Sheet of
Date:Sheet of
5
4
3
2
K8 CPU MISC
K8 CPU MISC
K8 CPU MISC
A78LD-M2S
A78LD-M2S
A78LD-M2S
1
6.2
6.2
748Thursday, March 04, 2010
748Thursday, March 04, 2010
748Thursday, March 04, 2010
6.2
5
A
MEM_MA0_CLK_H212,13
MEM_MA_ADD[15..0]
MEM_MA_DQS_H[8..0]
MEM_MA_DQS_L[8..0]
MEM_MA0_CLK_L212,13
MEM_MA0_CLK_H112,13
MEM_MA0_CLK_L112,13
MEM_MA0_CLK_H012,13
MEM_MA0_CLK_L012,13
MEM_MA0_CS_L113,17
MEM_MA0_CS_L013,17
MEM_MA0_ODT013,17
MEM_MA_CAS_L13,17
MEM_MA_WE_L13,17
MEM_MA_RAS_L13,17
MEM_MA_BANK213,17
MEM_MA_BANK113,17
MEM_MA_BANK013,17
MEM_MA_CKE013,17
DD
CC
MEM_MA_ADD[15..0]13,17
MEM_MA_DQS_H[8..0]13
MEM_MA_DQS_L[8..0]13
BB
MEM_MA_DM[8..0]13
MEM_MA_DM[8..0]
4
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
AG21
AG20
AC25
AC28
AD27
AC27
AC26
AD15
AG18
AG19
AG24
AG25
AG27
AG28
AH29
CPU1B
CPU1B
G19
H19
U27
U26
AA24
AE20
AE19
G20
G21
V27
W27
AA25
AB25
AB27
AA26
N25
Y27
AA27
L27
M25
M27
N24
N26
P25
Y25
N27
R24
P27
R25
R26
R27
T25
U25
T27
W24
AE15
D29
C29
C25
D25
E19
F19
F15
G15
AF15
AF19
AJ25
B29
E24
E18
H15
MEMORY INTERFACE A
MEMORY INTERFACE A
MA0_CLK_H(2)
MA0_CLK_L(2)
MA0_CLK_H(1)
MA0_CLK_L(1)
MA0_CLK_H(0)
MA0_CLK_L(0)
MA0_CS_L(1)
MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)
MA1_CLK_L(2)
MA1_CLK_H(1)
MA1_CLK_L(1)
MA1_CLK_H(0)
MA1_CLK_L(0)
MA1_CS_L(1)
MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_L
MA_WE_L
MA_RAS_L
MA_BANK(2)
MA_BANK(1)
MA_BANK(0)
MA_CKE(1)
MA_CKE(0)
MA_ADD(15)
MA_ADD(14)
MA_ADD(13)
MA_ADD(12)
MA_ADD(11)
MA_ADD(10)
MA_ADD(9)
MA_ADD(8)
MA_ADD(7)
MA_ADD(6)
MA_ADD(5)
MA_ADD(4)
MA_ADD(3)
MA_ADD(2)
MA_ADD(1)
MA_ADD(0)
MA_DQS_H(7)
MA_DQS_L(7)
MA_DQS_H(6)
MA_DQS_L(6)
MA_DQS_H(5)
MA_DQS_L(5)
MA_DQS_H(4)
MA_DQS_L(4)
MA_DQS_H(3)
MA_DQS_L(3)
MA_DQS_H(2)
MA_DQS_L(2)
MA_DQS_H(1)
MA_DQS_L(1)
MA_DQS_H(0)
MA_DQS_L(0)
MA_DM(7)
MA_DM(6)
MA_DM(5)
MA_DM(4)
MA_DM(3)
MA_DM(2)
MA_DM(1)
MA_DM(0)
SOCKET_M2 940 SMD
SOCKET_M2 940 SMD
MA_DATA(63)
MA_DATA(62)
MA_DATA(61)
MA_DATA(60)
MA_DATA(59)
MA_DATA(58)
MA_DATA(57)
MA_DATA(56)
MA_DATA(55)
MA_DATA(54)
MA_DATA(53)
MA_DATA(52)
MA_DATA(51)
MA_DATA(50)
MA_DATA(49)
MA_DATA(48)
MA_DATA(47)
MA_DATA(46)
MA_DATA(45)
MA_DATA(44)
MA_DATA(43)
MA_DATA(42)
MA_DATA(41)
MA_DATA(40)
MA_DATA(39)
MA_DATA(38)
MA_DATA(37)
MA_DATA(36)
MA_DATA(35)
MA_DATA(34)
MA_DATA(33)
MA_DATA(32)
MA_DATA(31)
MA_DATA(30)
MA_DATA(29)
MA_DATA(28)
MA_DATA(27)
MA_DATA(26)
MA_DATA(25)
MA_DATA(24)
MA_DATA(23)
MA_DATA(22)
MA_DATA(21)
MA_DATA(20)
MA_DATA(19)
MA_DATA(18)
MA_DATA(17)
MA_DATA(16)
MA_DATA(15)
MA_DATA(14)
MA_DATA(13)
MA_DATA(12)
MA_DATA(11)
MA_DATA(10)
MA_DATA(9)
MA_DATA(8)
MA_DATA(7)
MA_DATA(6)
MA_DATA(5)
MA_DATA(4)
MA_DATA(3)
MA_DATA(2)
MA_DATA(1)
MA_DATA(0)
MA_DQS_H(8)
MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)
MA_CHECK(6)
MA_CHECK(5)
MA_CHECK(4)
MA_CHECK(3)
MA_CHECK(2)
MA_CHECK(1)
MA_CHECK(0)
3
MEM_MA_DATA63
AE14
MEM_MA_DATA62
AG14
MEM_MA_DATA61
AG16
MEM_MA_DATA60
AD17
MEM_MA_DATA59
AD13
MEM_MA_DATA58
AE13
MEM_MA_DATA57
AG15
MEM_MA_DATA56
AE16
MEM_MA_DATA55
AG17
MEM_MA_DATA54
AE18
MEM_MA_DATA53
AD21
MEM_MA_DATA52
AG22
MEM_MA_DATA51
AE17
MEM_MA_DATA50
AF17
MEM_MA_DATA49
AF21
MEM_MA_DATA48
AE21
MEM_MA_DATA47
AF23
MEM_MA_DATA46
AE23
MEM_MA_DATA45
AJ26
MEM_MA_DATA44
AG26
MEM_MA_DATA43
AE22
MEM_MA_DATA42
AG23
MEM_MA_DATA41
AH25
MEM_MA_DATA40
AF25
MEM_MA_DATA39
AJ28
MEM_MA_DATA38
AJ29
MEM_MA_DATA37
AF29
MEM_MA_DATA36
AE26
MEM_MA_DATA35
AJ27
MEM_MA_DATA34
AH27
MEM_MA_DATA33
AG29
MEM_MA_DATA32
AF27
MEM_MA_DATA31
E29
MEM_MA_DATA30
E28
MEM_MA_DATA29
D27
MEM_MA_DATA28
C27
MEM_MA_DATA27
G26
MEM_MA_DATA26
F27
MEM_MA_DATA25
C28
MEM_MA_DATA24
E27
MEM_MA_DATA23
F25
MEM_MA_DATA22
E25
MEM_MA_DATA21
E23
MEM_MA_DATA20
D23
MEM_MA_DATA19
E26
MEM_MA_DATA18
C26
MEM_MA_DATA17
G23
MEM_MA_DATA16
F23
MEM_MA_DATA15
E22
MEM_MA_DATA14
E21
MEM_MA_DATA13
F17
MEM_MA_DATA12
G17
MEM_MA_DATA11
G22
MEM_MA_DATA10
F21
MEM_MA_DATA9
G18
MEM_MA_DATA8
E17
MEM_MA_DATA7
G16
MEM_MA_DATA6
E15
MEM_MA_DATA5
G13
MEM_MA_DATA4
H13
MEM_MA_DATA3
H17
MEM_MA_DATA2
E16
MEM_MA_DATA1
E14
MEM_MA_DATA0
G14
MEM_MA_DQS_H8
J28
MEM_MA_DQS_L8
J27
MEM_MA_DM8
J25
MEM_MA_CHECK7
K25
MEM_MA_CHECK6
J26
MEM_MA_CHECK5
G28
MEM_MA_CHECK4
G27
MEM_MA_CHECK3
L24
MEM_MA_CHECK2
K27
MEM_MA_CHECK1
H29
MEM_MA_CHECK0
H27
2
MEM_MA_DATA[0..63]
MEM_MA_DATA[0..63]13
MEM_MA_CHECK[7..0]
1
MEM_MA_CHECK[7..0]13
A
Title
Title
Title
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
Date:Sheet of
Date:Sheet of
Date:Sheet of
5
4
3
2
Custom
Custom
Custom
K8 CPU MEMORY-1
K8 CPU MEMORY-1
K8 CPU MEMORY-1
A78LD-M2S
A78LD-M2S
A78LD-M2S
1
6.2
6.2
848Thursday, March 04, 2010
848Thursday, March 04, 2010
848Thursday, March 04, 2010
6.2
5
A
MEM_MB0_CLK_H212,14
MEM_MB0_CLK_L212,14
MEM_MB0_CLK_H112,14
MEM_MB0_CLK_L112,14
MEM_MB0_CLK_H012,14
DD
CC
MEM_MB_ADD[15..0]14,17
MEM_MB_DQS_H[8..0]14
MEM_MB_DQS_L[8..0]14
BB
MEM_MB_DM[8..0]14 MEM_MB_CHECK[7..0]14
MEM_MB0_CLK_L012,14
MEM_MB0_CS_L114,17
MEM_MB0_CS_L014,17
MEM_MB0_ODT014,17
MEM_MB_CAS_L14,17
MEM_MB_WE_L14,17
MEM_MB_RAS_L14,17
MEM_MB_BANK214,17
MEM_MB_BANK114,17
MEM_MB_BANK014,17
MEM_MB_CKE014,17
MEM_MB_ADD[15..0]
MEM_MB_DQS_H[8..0]
MEM_MB_DQS_L[8..0]
MEM_MB_DM[8..0]
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
4
CPU1C
CPU1C
MEMORY INTERFACE B
MEMORY INTERFACE B
AJ19
AC31
AD29
AD31
AC29
AC30
AH17
AK19
AE30
AL19
AL18
W29
W28
AE29
AB31
AB29
AA31
AA28
M31
M29
AE31
AA29
AA30
AK13
AJ13
AK17
AJ17
AK23
AL23
AL28
AL29
AJ14
AJ23
AK29
A18
A19
U31
U30
C19
D19
N31
N28
N29
N30
P29
P31
R29
R28
R31
R30
T31
T29
U29
U28
D31
C31
C24
C23
D17
C17
C14
C13
C30
A23
B17
B13
MB0_CLK_H(2)
MB0_CLK_L(2)
MB0_CLK_H(1)
MB0_CLK_L(1)
MB0_CLK_H(0)
MB0_CLK_L(0)
MB0_CS_L(1)
MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)
MB1_CLK_L(2)
MB1_CLK_H(1)
MB1_CLK_L(1)
MB1_CLK_H(0)
MB1_CLK_L(0)
MB1_CS_L(1)
MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_L
MB_WE_L
MB_RAS_L
MB_BANK(2)
MB_BANK(1)
MB_BANK(0)
MB_CKE(1)
MB_CKE(0)
MB_ADD(15)
MB_ADD(14)
MB_ADD(13)
MB_ADD(12)
MB_ADD(11)
MB_ADD(10)
MB_ADD(9)
MB_ADD(8)
MB_ADD(7)
MB_ADD(6)
MB_ADD(5)
MB_ADD(4)
MB_ADD(3)
MB_ADD(2)
MB_ADD(1)
MB_ADD(0)
MB_DQS_H(7)
MB_DQS_L(7)
MB_DQS_H(6)
MB_DQS_L(6)
MB_DQS_H(5)
MB_DQS_L(5)
MB_DQS_H(4)
MB_DQS_L(4)
MB_DQS_H(3)
MB_DQS_L(3)
MB_DQS_H(2)
MB_DQS_L(2)
MB_DQS_H(1)
MB_DQS_L(1)
MB_DQS_H(0)
MB_DQS_L(0)
MB_DM(7)
MB_DM(6)
MB_DM(5)
MB_DM(4)
MB_DM(3)
MB_DM(2)
MB_DM(1)
MB_DM(0)
MB_DATA(63)
MB_DATA(62)
MB_DATA(61)
MB_DATA(60)
MB_DATA(59)
MB_DATA(58)
MB_DATA(57)
MB_DATA(56)
MB_DATA(55)
MB_DATA(54)
MB_DATA(53)
MB_DATA(52)
MB_DATA(51)
MB_DATA(50)
MB_DATA(49)
MB_DATA(48)
MB_DATA(47)
MB_DATA(46)
MB_DATA(45)
MB_DATA(44)
MB_DATA(43)
MB_DATA(42)
MB_DATA(41)
MB_DATA(40)
MB_DATA(39)
MB_DATA(38)
MB_DATA(37)
MB_DATA(36)
MB_DATA(35)
MB_DATA(34)
MB_DATA(33)
MB_DATA(32)
MB_DATA(31)
MB_DATA(30)
MB_DATA(29)
MB_DATA(28)
MB_DATA(27)
MB_DATA(26)
MB_DATA(25)
MB_DATA(24)
MB_DATA(23)
MB_DATA(22)
MB_DATA(21)
MB_DATA(20)
MB_DATA(19)
MB_DATA(18)
MB_DATA(17)
MB_DATA(16)
MB_DATA(15)
MB_DATA(14)
MB_DATA(13)
MB_DATA(12)
MB_DATA(11)
MB_DATA(10)
MB_DATA(9)
MB_DATA(8)
MB_DATA(7)
MB_DATA(6)
MB_DATA(5)
MB_DATA(4)
MB_DATA(3)
MB_DATA(2)
MB_DATA(1)
MB_DATA(0)
MB_DQS_H(8)
MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)
MB_CHECK(6)
MB_CHECK(5)
MB_CHECK(4)
MB_CHECK(3)
MB_CHECK(2)
MB_CHECK(1)
MB_CHECK(0)
AH13
AL13
AL15
AJ15
AF13
AG13
AL14
AK15
AL16
AL17
AK21
AL21
AH15
AJ16
AH19
AL20
AJ22
AL22
AL24
AK25
AJ21
AH21
AH23
AJ24
AL27
AK27
AH31
AG30
AL25
AL26
AJ30
AJ31
E31
E30
B27
A27
F29
F31
A29
A28
A25
A24
C22
D21
A26
B25
B23
A22
B21
A20
C16
D15
C21
A21
A17
A16
B15
A14
E13
F13
C15
A15
A13
D13
J31
J30
J29
K29
K31
G30
G29
L29
L28
H31
G31
3
MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0
MEM_MB_DQS_H8
MEM_MB_DQS_L8
MEM_MB_DM8
MEM_MB_CHECK7
MEM_MB_CHECK6
MEM_MB_CHECK5
MEM_MB_CHECK4
MEM_MB_CHECK3
MEM_MB_CHECK2
MEM_MB_CHECK1
MEM_MB_CHECK0
MEM_MB_DATA[0..63]
MEM_MB_CHECK[7..0]
2
MEM_MB_DATA[0..63]14
1
A
Title
Title
Title
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
Date:Sheet of
Date:Sheet of
Date:Sheet of
5
4
3
2
Custom
Custom
Custom
K8 CPU MEMORY-2
K8 CPU MEMORY-2
K8 CPU MEMORY-2
A78LD-M2S
A78LD-M2S
A78LD-M2S
1
6.2
6.2
948Thursday, March 04, 2010
948Thursday, March 04, 2010
948Thursday, March 04, 2010
6.2
5
A
4
3
10UF 10V 0805 Y5V
10UF 10V 0805 Y5V
+1.2V_HT
1 2
2
C9
C9
C10
C10
0.1UF 16V Y5V 0402
0.1UF 16V Y5V 0402
1
DD
+V_CPU +V_CPU +V_CPU +1.2V_HT
CC
BB
AA10
AA12
AA14
AA16
AA18
AB11
AC10
AE10
CPU1F
CPU1F
VDD1
VDD1
A4
VDD1
A6
VDD2
AA8
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
AB7
VDD9
AB9
VDD10
VDD11
AC4
VDD12
AC5
VDD13
AC8
VDD14
VDD15
AD2
VDD16
AD3
VDD17
AD7
VDD18
AD9
VDD19
VDD20
AF7
VDD21
AF9
VDD22
AG4
VDD23
AG5
VDD24
AG7
VDD25
AH2
VDD26
AH3
VDD27
B3
VDD28
B5
VDD29
B7
VDD30
C2
VDD31
C4
VDD32
C6
VDD33
C8
VDD34
D3
VDD35
D5
VDD36
D7
VDD37
D9
VDD38
E4
VDD39
E6
VDD40
E8
VDD41
E10
VDD42
F5
VDD43
F7
VDD44
F9
VDD45
F11
VDD46
G6
VDD47
G8
VDD48
G10
VDD49
G12
VDD50
H7
VDD51
H11
VDD52
H23
VDD53
J8
VDD54
J12
VDD55
J14
VDD56
J16
VDD57
J18
VDD58
J20
VDD59
J22
VDD60
J24
VDD61
K7
VDD62
K9
VDD63
K11
VDD64
K13
VDD65
K15
VDD66
K17
VDD67
K19
VDD68
K21
VDD69
K23
VDD70
L4
VDD71
L5
VDD72
L8
VDD73
L10
VDD74
L12
VDD75
Y17
VDD150
Y19
VDD151
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS240
VSS241
A3
A7
A9
A11
AA4
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AB2
AB3
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AD8
AD10
AD12
AD14
AD16
AD20
AD22
AD24
AE4
AE5
AE9
AE11
AF2
AF3
AF8
AF10
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK2
AK14
AK16
AK18
Y14
Y16
CPU1G
CPU1G
VDD2
VDD2
L14
VDD1
L16
VDD2
L18
VDD3
M2
VDD4
M3
VDD5
M7
VDD6
M9
VDD7
M11
VDD8
M13
VDD9
M15
VDD10
M17
VDD11
M19
VDD12
N8
VDD13
N10
VDD14
N12
VDD15
N14
VDD16
N16
VDD17
N18
VDD18
P7
VDD19
P9
VDD20
P11
VDD21
P13
VDD22
P15
VDD23
P17
VDD24
P19
VDD25
R4
VDD26
R5
VDD27
R8
VDD28
R10
VDD29
R12
VDD30
R14
VDD31
R16
VDD32
R18
VDD33
R20
VDD34
T2
VDD35
T3
VDD36
T7
VDD37
T9
VDD38
T11
VDD39
T13
VDD40
T15
VDD41
T17
VDD42
T19
VDD43
T21
VDD44
U8
VDD45
U10
VDD46
U12
VDD47
U14
VDD48
U16
VDD49
U18
VDD50
U20
VDD51
V9
VDD52
V11
VDD53
V13
VDD54
V15
VDD55
V17
VDD56
V19
VDD57
V21
VDD58
W4
VDD59
W5
VDD60
W8
VDD61
W10
VDD62
W12
VDD63
W14
VDD64
W16
VDD65
W18
VDD66
W20
VDD67
Y2
VDD68
Y3
VDD69
Y7
VDD70
Y9
VDD71
Y11
VDD72
Y13
VDD73
Y15
VDD74
Y21
VDD75
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
AK20
AK22
AK24
AK26
AK28
AK30
AL5
B4
B9
B11
B14
B16
B18
B20
B22
B24
B26
B28
B30
C3
D14
D16
D18
D20
D22
D24
D26
D28
D30
E11
F4
F14
F16
F18
F20
F22
F24
F26
F28
F30
G9
G11
H8
H10
H12
H14
H16
H18
H22
H24
H26
H28
H30
J4
J5
J7
J9
J11
J13
J15
J17
J19
J21
J23
K2
K3
K8
K10
K12
K14
K16
K18
K20
K22
Y18
AA20
AA22
AB13
AB15
AB17
AB19
AB21
AB23
AC12
AC14
AC16
AC18
AC20
AC22
AD11
AD23
AE12
AF11
CPU1H
CPU1H
VDD3
VDD3
N17
VSS1
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
L20
VDD19
L22
VDD20
M21
VDD21
M23
VDD22
N20
VDD23
N22
VDD24
P21
VDD25
P23
VDD26
R22
VDD27
T23
VDD28
U22
VDD29
V23
VDD30
W22
VDD31
Y23
VDD32
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
N19
N21
N23
P2
P3
P8
P10
P12
P14
P16
P18
P20
P22
R7
R9
R11
R13
R15
R17
R19
R21
R23
T8
T10
T12
T14
T16
T18
T20
T22
U4
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
W7
Y20
Y22
+1.8V_SUS
+0.9V_SUS
1UF 16V 0805 Y5VC8 1UF 16V 0805 Y5VC8
10UF 10V 0805 Y5VC12 10UF 10V 0805 Y5VC12
0.1UF 16V Y5V 0402C568 0.1UF 16V Y5V 0402C568
0.1UF 16V Y5V 0402C569 0.1UF 16V Y5V 0402C569
AB24
AB26
AB28
AB30
AC24
AD26
AD28
AD30
AF30
CPU1I
CPU1I
VDDIO
VDDIO
AJ4
VLDT_A1
AJ3
VLDT_A2
AJ2
VLDT_A3
AJ1
VLDT_A4
D12
VTT1
C12
VTT2
B12
VTT3
A12
VTT4
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO29
M24
VDDIO9
M26
VDDIO10
M28
VDDIO11
M30
VDDIO12
P24
VDDIO13
P26
VDDIO14
P28
VDDIO15
P30
VDDIO16
T24
VDDIO17
T26
VDDIO18
T28
VDDIO19
T30
VDDIO20
V25
VDDIO21
V26
VDDIO22
V28
VDDIO23
V30
VDDIO24
Y24
VDDIO25
Y26
VDDIO26
Y28
VDDIO27
Y29
VDDIO28
VLDT_B1
VLDT_B2
VLDT_B3
VLDT_B4
VTT5
VTT6
VTT7
VTT8
VTT9
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
H6
H5
H2
H1
AK12
AJ12
AH12
AG12
AL12
K24
K26
K28
K30
L7
L9
L11
L13
L15
L17
L19
L21
L23
M8
M10
M12
M14
M16
M18
M20
M22
N4
N5
N7
N9
N11
N13
N15
+1.2V_HT
C11
C11
1 2
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
+0.9V_SUS
A
Title
Title
Title
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
Date:Sheet of
Date:Sheet of
Date:Sheet of
5
4
3
2
Custom
Custom
Custom
K8 CPU POWER
K8 CPU POWER
K8 CPU POWER
A78LD-M2S
A78LD-M2S
A78LD-M2S
1
6.2
6.2
1048Thursday, March 04, 2010
1048Thursday, March 04, 2010
1048Thursday, March 04, 2010
6.2
5
A
DECOUPLING BETWEEN PROCESSOR AND DIMMS
PLACE AS CLOSE TO PROCESSOR AS
POSSIBLE
4
3
2
1
DD
+0.9V_SUS
12
C13
C13
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
+0.9V_SUS
12
C15
C15
CC
10UF 10V 0805 Y5V /NI
10UF 10V 0805 Y5V /NI
12
C14
C14
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
12
C16
C16
0.1UF 16V Y5V 0402
0.1UF 16V Y5V 0402
12
C549
C549
10UF 10V 0805 Y5V /NI
10UF 10V 0805 Y5V /NI
12
C17
C17
0.1UF 16V Y5V 0402 /NI
0.1UF 16V Y5V 0402 /NI
12
C550
C550
10UF 10V 0805 Y5V /NI
10UF 10V 0805 Y5V /NI
12
C18
C18
0.1UF 16V Y5V 0402 /NI
0.1UF 16V Y5V 0402 /NI
12
C19
C19
0.1UF 16V Y5V 0402 /NI
0.1UF 16V Y5V 0402 /NI
+V_CPU
12
C24
C24
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
BB
+V_CPU
12
C553
C553
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
+1.8V_SUS
12
C40
C40
1UF 16V 0805 Y5V /NI
1UF 16V 0805 Y5V /NI
PLACE BOTTOM SIDE DECOUPLING
12
C25
C25
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
12
C29
C29
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
12
C41
C41
0.1UF 16V Y5V 0402 /NI
0.1UF 16V Y5V 0402 /NI
12
C26
C26
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
12
C30
C30
10UF 10V 0805 Y5V
10UF 10V 0805 Y5V
12
C42
C42
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
5
12
12
+V_CPU
12
C27
C27
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
C554
C554
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
C46
C46
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
12
C312
C312
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
12
C555
C555
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
12
C47
C47
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
4
+1.8V_SUS
12
C21
C21
1UF 16V 0805 Y5V /NI
1UF 16V 0805 Y5V /NI
12
C556
C556
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
12
C22
C22
1UF 16V 0805 Y5V /NI
1UF 16V 0805 Y5V /NI
12
C557
C557
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
12
C23
C23
1UF 16V 0805 Y5V /NI
1UF 16V 0805 Y5V /NI
12
C35
C35
10UF 10V 0805 Y5V
10UF 10V 0805 Y5V
3
12
C20
C20
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
12
C36
C36
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
12
C38
C38
10UF 10V 0805 Y5V
10UF 10V 0805 Y5V
A
Title
Title
Title
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
Date:Sheet of
Date:Sheet of
Date:Sheet of
2
CPU DECPOULING CAP
CPU DECPOULING CAP
CPU DECPOULING CAP
Custom
Custom
Custom
A78LD-M2S
A78LD-M2S
A78LD-M2S
1
6.2
6.2
1148Thursday, March 04, 2010
1148Thursday, March 04, 2010
1148Thursday, March 04, 2010
6.2
5
A
4
3
2
1
MEM_MA0_CLK_H28,13
DD
CC
BB
MEM_MA0_CLK_L28,13
MEM_MA0_CLK_H18,13
MEM_MA0_CLK_L18,13
MEM_MA0_CLK_H08,13
MEM_MA0_CLK_L08,13
MEM_MB0_CLK_H29,14
MEM_MB0_CLK_L29,14
MEM_MB0_CLK_H19,14
MEM_MB0_CLK_L19,14
MEM_MB0_CLK_H09,14
MEM_MB0_CLK_L09,14
12
C48
C48
1.5P 50V NPO 0402
1.5P 50V NPO 0402
12
C50
C50
1.5P 50V NPO 0402
1.5P 50V NPO 0402
12
C52
C52
1.5P 50V NPO 0402
1.5P 50V NPO 0402
12
C54
C54
1.5P 50V NPO 0402
1.5P 50V NPO 0402
12
C56
C56
1.5P 50V NPO 0402
1.5P 50V NPO 0402
12
C58
C58
1.5P 50V NPO 0402
1.5P 50V NPO 0402
A
Title
Title
Title
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
Custom
Custom
Custom
Date:Sheet of
Date:Sheet of
Date:Sheet of
5
4
3
2
DDR CLK BYPASS
DDR CLK BYPASS
DDR CLK BYPASS
A78LD-M2S
A78LD-M2S
A78LD-M2S
1248Thursday, March 04, 2010
1248Thursday, March 04, 2010
1248Thursday, March 04, 2010
1
6.2
6.2
6.2
5
A
4
3
2
1
+1.8V_SUS
+3.3V
DIMMA1
DIMMA1
DIMMA1
172
178
184
187
189
197
64
69
170
175
181
191
194
72
78
VDDQ5
VDDQ651VDDQ756VDDQ862VDDQ9
VDDQ1075VDDQ11
3
238
VDDSPD
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
WE_L
VREF
TEST
ODT0
ODT1
ERR_OUT_L
PAR_IN
MEM_MA_DATA63
236
MEM_MA_DATA62
235
MEM_MA_DATA61
230
MEM_MA_DATA60
229
MEM_MA_DATA59
117
MEM_MA_DATA58
116
MEM_MA_DATA57
111
MEM_MA_DATA56
110
MEM_MA_DATA55
227
MEM_MA_DATA54
226
MEM_MA_DATA53
218
MEM_MA_DATA52
217
MEM_MA_DATA51
108
MEM_MA_DATA50
107
MEM_MA_DATA49
99
MEM_MA_DATA48
98
MEM_MA_DATA47
215
MEM_MA_DATA46
214
MEM_MA_DATA45
209
MEM_MA_DATA44
208
MEM_MA_DATA43
96
MEM_MA_DATA42
95
MEM_MA_DATA41
90
MEM_MA_DATA40
89
MEM_MA_DATA39
206
MEM_MA_DATA38
205
MEM_MA_DATA37
200
MEM_MA_DATA36
199
MEM_MA_DATA35
87
MEM_MA_DATA34
86
MEM_MA_DATA33
81
MEM_MA_DATA32
80
MEM_MA_DATA31
159
MEM_MA_DATA30
158
MEM_MA_DATA29
153
MEM_MA_DATA28
152
MEM_MA_DATA27
40
MEM_MA_DATA26
39
MEM_MA_DATA25
34
MEM_MA_DATA24
33
MEM_MA_DATA23
150
MEM_MA_DATA22
149
MEM_MA_DATA21
144
MEM_MA_DATA20
143
MEM_MA_DATA19
31
MEM_MA_DATA18
30
MEM_MA_DATA17
25
MEM_MA_DATA16
24
MEM_MA_DATA15
141
MEM_MA_DATA14
140
MEM_MA_DATA13
132
MEM_MA_DATA12
131
MEM_MA_DATA11
22
MEM_MA_DATA10
21
MEM_MA_DATA9
13
DQ9
MEM_MA_DATA8
12
DQ8
MEM_MA_DATA7
129
DQ7
MEM_MA_DATA6
128
DQ6
MEM_MA_DATA5
123
DQ5
MEM_MA_DATA4
122
DQ4
MEM_MA_DATA3
10
DQ3
MEM_MA_DATA2
9
DQ2
MEM_MA_DATA1
4
DQ1
MEM_MA_DATA0
3
DQ0
73
1
102
195
77
55
68
19
NC1
MEM_MA_WE_L8,17
MEM_MA0_ODT08,17
MEM_MA_DATA[0..63]
+1.8V_SUS
16.9 1% 0402
16.9 1% 0402
16.9 1% 0402
16.9 1% 0402
MEM_M_VREF
R19
R19
1 2
R20
R20
1 2
MEM_MA_DATA[0..63]8
12
C60
C60
0.1UF 16V Y5V 0402
0.1UF 16V Y5V 0402
MEM_M_VREF
12
C61
C61
0.1UF 16V Y5V 0402 /NI
0.1UF 16V Y5V 0402 /NI
PLACE NEAR DIMM SOCKETS
A
Title
Title
Title
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
Custom
Custom
Custom
Date:Sheet of
Date:Sheet of
Date:Sheet of
2
DDR DIMM-1
DDR DIMM-1
DDR DIMM-1
A78LD-M2S
A78LD-M2S
A78LD-M2S
1
6.2
6.2
1348Thursday, March 04, 2010
1348Thursday, March 04, 2010
1348Thursday, March 04, 2010
6.2
DD
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD753VDD859VDD9
VDD1067VDD11
VDDQ1
VDDQ2
VDDQ3
MEM_MA_DM[8..0]8
MEM_MA_DQS_H[8..0]8
MEM_MA_DQS_L[8..0]8
MEM_MA_DM[8..0]
MEM_MA_DQS_H[8..0]
MEM_MA_DQS_L[8..0]
CC
SCLK14,23,25
SDATA14,23,25
MEM_MA_BANK28,17
MEM_MA_BANK18,17
MEM_MA_ADD[15..0]8,17
MEM_MA_BANK08,17
BB
MEM_MA_CHECK[7..0]8
MEM_MA_CHECK[7..0]
MEM_MA0_CLK_H08,12
MEM_MA0_CLK_L08,12
MEM_MA0_CLK_H18,12
MEM_MA0_CLK_L18,12
MEM_MA0_CLK_H28,12
MEM_MA0_CLK_L28,12
MEM_MA_RAS_L8,17
MEM_MA_CAS_L8,17
MEM_MA0_CS_L08,17
MEM_MA0_CS_L18,17
MEM_MA_CKE08,17
5
MEM_MA_DM8
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
MEM_MA_DQS_H8
MEM_MA_DQS_L8
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_CHECK7
MEM_MA_CHECK6
MEM_MA_CHECK5
MEM_MA_CHECK4
MEM_MA_CHECK3
MEM_MA_CHECK2
MEM_MA_CHECK1
MEM_MA_CHECK0
MEM_MA_CKE0
4
164
165
232
233
223
224
211
212
202
203
155
156
146
147
134
135
125
126
46
45
114
113
105
104
93
92
84
83
37
36
28
27
16
15
7
6
101
240
239
120
119
54
190
71
173
174
196
176
57
70
177
179
58
180
60
61
182
63
183
188
168
167
162
161
49
48
43
42
185
186
137
138
220
221
18
52
171
192
74
193
76
DDR2-240 PIN-R
DDR2-240 PIN-R
DQS17_H
DQS17_L
DQS16_H
DQS16_L
DQS15_H
DQS15_L
DQS14_H
DQS14_L
DQS13_H
DQS13_L
DQS12_H
DQS12_L
DQS11_H
DQS11_L
DQS10_H
DQS10_L
DQS9_H
DQS9_L
DQS8_H
DQS8_L
DQS7_H
DQS7_L
DQS6_H
DQS6_L
DQS5_H
DQS5_L
DQS4_H
DQS4_L
DQS3_H
DQS3_L
DQS2_H
DQS2_L
DQS1_H
DQS1_L
DQS0_H
DQS0_L
SA2
SA1
SA0
SCL
SDA
BA2
BA1
BA0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
CK0_H
CK0_L
CK1_H
CK1_L
CK2_H
CK2_L
RESET_L
CKE0
CKE1
RAS_L
CAS_L
S0_L
S1_L
VDDQ4
5
A
4
3
2
1
+1.8V_SUS
+3.3V
DIMMB1
DIMMB1
DD
MEM_MB_DM[8..0]9
MEM_MB_DQS_H[8..0]9
MEM_MB_DQS_L[8..0]9
MEM_MB_DM[8..0]
MEM_MB_DQS_H[8..0]
MEM_MB_DQS_L[8..0]
CC
SDATA13,23,25
MEM_MB_BANK29,17
MEM_MB_BANK19,17
MEM_MB_BANK09,17
MEM_MB_ADD[15..0]9,17
MEM_MB_ADD[15..0]
BB
MEM_MB_CHECK[7..0]9
MEM_MB_CHECK[7..0]
MEM_MB0_CLK_H09,12
MEM_MB0_CLK_L09,12
MEM_MB0_CLK_H19,12
MEM_MB0_CLK_L19,12
MEM_MB0_CLK_H29,12
MEM_MB0_CLK_L29,12
MEM_MB_CKE09,17
MEM_MB_RAS_L9,17
MEM_MB_CAS_L9,17
MEM_MB0_CS_L09,17
MEM_MB0_CS_L19,17
5
MEM_MB_DM8
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
MEM_MB_DQS_H8
MEM_MB_DQS_L8
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
+3.3V
SCLK13,23,25
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7 MEM_MB_DATA9
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_CHECK7
MEM_MB_CHECK6
MEM_MB_CHECK5
MEM_MB_CHECK4
MEM_MB_CHECK3
MEM_MB_CHECK2
MEM_MB_CHECK1
MEM_MB_CHECK0
4
DIMMB1
164
165
232
233
223
224
211
212
202
203
155
156
146
147
134
135
125
126
46
45
114
113
105
104
93
92
84
83
37
36
28
27
16
15
7
6
101
240
239
120
119
54
190
71
173
174
196
176
57
70
177
179
58
180
60
61
182
63
183
188
168
167
162
161
49
48
43
42
185
186
137
138
220
221
18
52
171
192
74
193
76
DDR2-240 PIN-R
DDR2-240 PIN-R
DQS17_H
DQS17_L
DQS16_H
DQS16_L
DQS15_H
DQS15_L
DQS14_H
DQS14_L
DQS13_H
DQS13_L
DQS12_H
DQS12_L
DQS11_H
DQS11_L
DQS10_H
DQS10_L
DQS9_H
DQS9_L
DQS8_H
DQS8_L
DQS7_H
DQS7_L
DQS6_H
DQS6_L
DQS5_H
DQS5_L
DQS4_H
DQS4_L
DQS3_H
DQS3_L
DQS2_H
DQS2_L
DQS1_H
DQS1_L
DQS0_H
DQS0_L
SA2
SA1
SA0
SCL
SDA
BA2
BA1
BA0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
CK0_H
CK0_L
CK1_H
CK1_L
CK2_H
CK2_L
RESET_L
CKE0
CKE1
RAS_L
CAS_L
S0_L
S1_L
172
178
184
187
189
197
64
69
170
175
181
191
194
72
78
238
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD753VDD859VDD9
VDD1067VDD11
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ651VDDQ756VDDQ862VDDQ9
VDDQ1075VDDQ11
VDDSPD
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
WE_L
VREF
ODT0
ODT1
ERR_OUT_L
PAR_IN
TEST
MEM_MB_DATA63
236
MEM_MB_DATA62
235
MEM_MB_DATA61
230
MEM_MB_DATA60
229
MEM_MB_DATA59
117
MEM_MB_DATA58
116
MEM_MB_DATA57
111
MEM_MB_DATA56
110
MEM_MB_DATA55
227
MEM_MB_DATA54
226
MEM_MB_DATA53
218
MEM_MB_DATA52
217
MEM_MB_DATA51
108
MEM_MB_DATA50
107
MEM_MB_DATA49
99
MEM_MB_DATA48
98
MEM_MB_DATA47
215
MEM_MB_DATA46
214
MEM_MB_DATA45
209
MEM_MB_DATA44
208
MEM_MB_DATA43
96
MEM_MB_DATA42
95
MEM_MB_DATA41
90
MEM_MB_DATA40
89
MEM_MB_DATA39
206
MEM_MB_DATA38
205
MEM_MB_DATA37
200
MEM_MB_DATA36
199
MEM_MB_DATA35
87
MEM_MB_DATA34
86
MEM_MB_DATA33
81
MEM_MB_DATA32
80
MEM_MB_DATA31
159
MEM_MB_DATA30
158
MEM_MB_DATA29
153
MEM_MB_DATA28
152
MEM_MB_DATA27
40
MEM_MB_DATA26
39
MEM_MB_DATA25
34
MEM_MB_DATA24
33
MEM_MB_DATA23
150
MEM_MB_DATA22
149
MEM_MB_DATA21
144
MEM_MB_DATA20
143
MEM_MB_DATA19
31
MEM_MB_DATA18
30
MEM_MB_DATA17
25
MEM_MB_DATA16
24
MEM_MB_DATA15
141
MEM_MB_DATA14
140
MEM_MB_DATA13
132
MEM_MB_DATA12
131
MEM_MB_DATA11
22
MEM_MB_DATA10
21
13
DQ9
MEM_MB_DATA8
12
DQ8
MEM_MB_DATA7
129
DQ7
MEM_MB_DATA6
128
DQ6
MEM_MB_DATA5
123
DQ5
MEM_MB_DATA4
122
DQ4
MEM_MB_DATA3
10
DQ3
MEM_MB_DATA2
9
DQ2
MEM_MB_DATA1
4
DQ1
MEM_MB_DATA0
3
DQ0
73
1
102
195
77
55
68
19
NC1
MEM_MB_WE_L9,17
MEM_MB0_ODT09,17
MEM_MB_DATA[0..63]
12
C62
C62
0.1UF 16V Y5V 0402
0.1UF 16V Y5V 0402
PLACE NEAR DIMM SOCKETS
MEM_MB_DATA[0..63]9
MEM_M_VREF
A
Title
Title
Title
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
Custom
Custom
Custom
Date:Sheet of
Date:Sheet of
3
2
Date:Sheet of
DDR DIMM-2
DDR DIMM-2
DDR DIMM-2
A78LD-M2S
A78LD-M2S
A78LD-M2S
1
6.2
6.2
1448Thursday, March 04, 2010
1448Thursday, March 04, 2010
1448Thursday, March 04, 2010
6.2
5
A
4
3
2
1
DD
+1.8V+1.8V
R567
R567
10K 1% 0402 /NI
10K 1% 0402 /NI
+1.8V
R573
R573
10K 1% 0402 /NI
10K 1% 0402 /NI
+1.8V
R579
R579
10K 1% 0402 /NI
10K 1% 0402 /NI
+1.8V
+1.8V
+1.8V
+3.3V+3.3V
R564
R564
10K 0402
10K 0402
B
Q88
Q88
2N3904 SOT23
2N3904 SOT23
E
C
R570
R570
10K 0402
10K 0402
B
Q90
Q90
2N3904 SOT23
2N3904 SOT23
E
C
R576
R576
10K 0402
10K 0402
B
Q92
Q92
2N3904 SOT23
2N3904 SOT23
E
C
+3.3V
+3.3V
R568
R568
10K 1% 0402 /NI
10K 1% 0402 /NI
R574
R574
10K 1% 0402 /NI
10K 1% 0402 /NI
IMC_TCK25
R580
R580
10K 1% 0402 /NI
10K 1% 0402 /NI
IMC_DBREQ#25
IMC_DBRDY25
+1.8V
+3.3V
+3.3V
R577
R577
10K 1% 0402 /NI
10K 1% 0402 /NI
+3.3V
R582
R582
10K 1% 0402 /NI
10K 1% 0402 /NI
B
C
+1.8V
B
E
+1.8V
E
+1.8V
E
R565
R565
10K 1% 0402 /NI
10K 1% 0402 /NI
IMC_TDI25
R571
R571
10K 1% 0402 /NI
10K 1% 0402 /NI
CC
IMC_TRST#25
IMC_TDO25
IMC_TMS25
R563
R563
10K 0402
10K 0402
Q87
Q87
2N3904 SOT23
2N3904 SOT23
E
R569
R569
10K 0402
10K 0402
Q89
Q89
2N3904 SOT23
2N3904 SOT23
C
R575
R575
10K 0402
10K 0402
B
Q91
Q91
2N3904 SOT23
2N3904 SOT23
C
R581
R581
10K 0402
10K 0402
B
Q93
Q93
2N3904 SOT23
2N3904 SOT23
C
CPU_TDO7
CPU_TRST#7
+1.8V
+1.8V
+1.8V
R566
R566
10K 1% 0402 /NI
10K 1% 0402 /NI
R572
R572
10K 1% 0402 /NI
10K 1% 0402 /NI
CPU_TDI7
R578
R578
10K 1% 0402 /NI
10K 1% 0402 /NI
CPU_TMS7
R583
R583
10K 1% 0402 /NI
10K 1% 0402 /NI
CPU_DBREQ#7
CPU_DBRDY7
CPU_TCK7
BB
A
Title
Title
Title
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
Custom
Custom
Custom
Date:Sheet of
Date:Sheet of
5
4
3
2
Date:Sheet of
ADO Extreme
ADO Extreme
ADO Extreme
A78LD-M2S
A78LD-M2S
A78LD-M2S
1
6.2
6.2
1548Thursday, March 04, 2010
1548Thursday, March 04, 2010
1548Thursday, March 04, 2010
6.2
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