Biostar A78LC-M3S Schematic
5
A
4 3
2
1
D D
PAGE
1
2
3
4
5
6-9
10
11
12
13
14
C C
B B
15
16
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
CONTENTS
COVER
BLOCK DIAGRAM
POWER DELIVERY
CLOCK DISTRIBUTION
REVISION HISTROY
SKT 941 K8 M3 CPU
CPU DECOUPLING
DDR2 DIMM -1
DDR2 DIMM -2
OV/ACC FUNCTION
RS760G-HT LINK
RS760G-PCIE
RS760G-SYSTEM
RS760G-PWOER&SBD_MEM17
CLOCK GEN
SB710-PCIE/PCI/CPU/LPC
SB710-ACPI/GPIO/USB/AUD
SB710-SATA/IDE/HWM/SPI
SB710-POWER&DECOUPLING
SB710-STRAPS
CRT & DVI
PCI-E SLOT
PCI SLOT
IDE ATA 133
USB CONN
CODEC ALC662
AUDIO CONNECTOR
SUPER I/O ITE8721
HW MONITOR / FAN CONTROL
FDD / PS2 CONN / FLASH
COM&LPT CONNECTOR
ATX PWR / FRONT PANEL / LED
Realtek RTL8103EL
FRONT USB
PWRGD / MISC DC-DC
VCC_CORE DC-DC CONVER
MEMORY POWER
NB/SB CORE POWER
BOM
A78LC-M3S ( RS780L&SB710 )
REV 6.0
DATE :2010/05/18
BIOSTAR'S PROPRIETARY INFORMATION
Any unauthorized use, reproduction,
duplication, or disclosure of this
document will be subject to the
applicable civil and/or criminal
penalties.
A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
COVER
COVER
COVER
A78LC-M3S
A78LC-M3S
A78LC-M3S
6.0
6.0
1 42Wednesday, May 19, 2010
1 42Wednesday, May 19, 2010
1 42Wednesday, May 19, 2010
6.0
w
5
A
4 3
2
1
AMD
AM2/AM2+
D D
Clock Generator
RTM880N-793
DVI/TMDS CON
VGA CON
PCIE
16X
SLOT1
TMDS
16X
HyperTransport
LINK
M2 SOCKET
OUT
AMD NB
RS760G
HyperTransport LINK0 CPU I/F
INTEGRATED GRAPHICS
LVTM
1 16X PCIE VIDEO I/F
1 1X PCIE I/F
16x16
IN
DDRII 533,667,800
128bit
DDRII 533,667,800
UNBUFFERED
DDRII
DIMM1
UNBUFFERED
DDRII DIMM2
DDRII FIRST LOGICAL DIMM
UNBUFFERED
DDRII DIMM3
UNBUFFERED
DDRII DIMM4
DDRII SECOND LOGICAL DIMM
C C
ATI SB
SB710
4X
PCIE
SPI I/F
HD AUDIO I/F
SATA II I/F
ATA 66/100/133 I/F
SPI ROM
AZILIA
CODEC
SATA#0
IDE1
HW
MONITOR
SATA#1
SATA#2
SATA#3
SATA#4 SATA#5
GIGABIT
Realtek RTL8111C
USB-5
USB-6
USB-4
USB-7
USB-3
USB-8
B B
USB-2
USB-9
4 1X PCIE
INTERFACE
USB-1
USB-10 USB-11
PCI BUS
PCIE GPP0
X1
USB-0
BOOTSTRAPS
ROM (SB)
USB 2.0
I2C I/F
USB2.0 (12)
SATA II (6)
AC97 2.3/ AZALIA
ATA 66/100/133
ACPI
LPC I/F
INT RTC
HW MONITOR
PCI SLOT #1
DESKTOP M2 POWER
RS760G
CORE & PCIE POWER
DDR MEMORY POWER
PCI SLOT #2
PCI SLOT #3
ITE LPC SIO 8716/8718
FLOPPY
KBD
MOUSE
HW
MONITOR
A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
A78LC-M3S
A78LC-M3S
A78LC-M3S
6.0
6.0
2 42Wednesday, May 19, 2010
2 42Wednesday, May 19, 2010
2 42Wednesday, May 19, 2010
6.0
w
5
A
ATX P/S WITH 1A STBY CURRENT
5VSB
+/-5%
5V
+/-5%
3.3V
+/-5%
12V
+/-5%
-12V
+/-5%
CPU
PW
12V
+/-5%
D D
VCC 1.1V SW
REGULATOR
+3.3VSB REGULATOR
ACPI CONTROLLER
C C
4 3
2.5V SHUNT
REGULATOR
VRM SW
REGULATOR
+5VDUAL_MEM (S0,S5)
VCC 1.2V SW
REGULATOR
+3.3VSB (S0, S1, S3, S4, S5)
+3.3VDUAL (S0, S1, S3, S4, S5)
+5VDUAL (S0, S1, S3, S4, S5)
1.8V VDD SW
REGULATOR
VCC 1.1V SW
REGULATOR
1.8V LINEAR
REGULATOR
VDD_CPUCORE_RUN (S0, S1)/VDD_CPUNB_RUN (S0, S1)
0.9V VTT_DDR
REGULATOR
+1.1V RX780/RS780; +1.2V RS740 (S0, S1)
+1.1V RX780/RS780; +1.2V RS740 (S0, S1)
+1.8V(S0, S1)
1.5V LINEAR
+1.2V(S0, S1)
1.2V STB LDO
REGULATOR
+1.2VSB (S5)
REGULATOR
DDRII DIMMs
VTT_DDR 2A
VDD MEM 12A
+1.5V(S0, S1)
2
CPU_VDDA_RUN
CPU_VTT_SUS (S0,S1,S3)
CPU_VDDIO_SUS(S0,S1,S3)
(S0, S1)
AM2
VDDA 2.5V 0.2A
VDDCORE
0.8-1.55V 110A
DDRII MEM I/F
VTT 2A, VDD 10A
VLDT 1.2V 0.5A
RS780
VDDHT/RX 1.1V 1.2A
VDDHTTX 1.2V 0.5A
VDDPCIE 1.1V 2A
NB CORE VDDC
1.1V 7A
VDDA18PCIE 1.8V 0.9A
PLLs 1.8V 0.1A
VDD18/VDD18_MEM
1.8V 0.01A
VDD_MEM 1.8V/1.5V 0.5A
AVDD 3.3V 0.135A
SB700
X4 PCI-E 0.8A
ATA I/O 0.5A
ATA PLL 0.01A
PCI-E PVDD 80mA
SB CORE 0.6A
CLOCK
1.2V S5 PW 0.22A
3.3V S5 PW 0.01A
USB CORE I/O 0.2A
3.3V I/O 0.45A
1
AZALIA CODEC CON
3.3V CORE 0.3A
Custom
Custom
Custom
5V ANALOG 0.1A
12V 0.1A
POWER DELIVERY
POWER DELIVERY
POWER DELIVERY
A78LC-M3S
A78LC-M3S
A78LC-M3S
3 42Wednesday, May 19, 2010
3 42Wednesday, May 19, 2010
3 42Wednesday, May 19, 2010
B B
X1 PCIE per
3.3V
3.3V
12V
3.3Vaux
3.0A
0.5A
0.1A
12V
5.0A
7.6A 5VDual
3.0A
5.5A
X16 PCIE
3.3V
12V
5.5A
USB X6 FR
VDD 3.0A
5VDual
2.0A0.5A
USB X6 RL
VDD
2.0A
0.1A
2XPS/2
5VDual
1.0A
GBE
3.3V 0.5A (S0, S1)
3.3V 0.1A (S3)
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
+3.3VDUAL (S0, S1, S3)
PCI Slot (per slot) X16 PCIE
5V
3.3V
12V
3.3Vaux
0.375A
-12V
w
A
6.0
6.0
6.0
5
A
4 3
2
1
3 PAIR MEM CLK
DIMM4
DIMM2
3 PAIR MEM CLK
1 PAIR CPU CLK
200MHZ
EXTERNAL
CLK GEN.
(RS740/RX780)
HT REFCLK
66MHz SE(RS740)
100MHz
DIFF(RX780/RS780)
NB-OSCIN
14.318MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
NB GFX PCIE CLK
100MHZ
NB GPP PCIE CLK
100MHZ
PCIE GFX CLK
100MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
14.318MHZ OSC
(RX780)
USB CLK
48MHZ
AMD NB
RS740/RX780/RS780
PCIE GFX SLOT 1 - 16 LANES
PCIE GPP SLOT 1 - 1 LANE
PCIE GPP SLOT 2 - 4 LANES
PCIE GBE
25MHZ OSC INPUT
1 PAIR CPU CLK
200MHZ
HT ref clock
100MHZ DIFF(RX780/RS780)
HT REFCLK
66MHz SE(RS740)
NB PCIE Ref clock
100MHZ
NB Disp clock
100MHZ DIFF(RS780)
GPP Ref clock
100MHZ
GFX Ref clock
100MHZ
GPP Ref clock
100MHZ
GPP Ref clock
100MHZ
GPP Ref clock
100MHZ
25MHz
SATA
CPU_HT_CLK
NB_HT_CLK
25M_48M_66M_OSC
AMD SB
SB700
NB_DISP_CLK
GPP_CLK3
PCIE_RCLK/
NB_LNK_CLK
SLT_GFX_CLK
GPP_CLK0
GPP_CLK1
GPP_CLK2
USB_CLK
SB_BITCLK
48MHZ
PCI CLK0
33MHZ
PCI CLK1
33MHZ
PCI CLK2
33MHZ
LPC_CLK0
33MHZ
LPC CLK1
33MHZ
PCI CLK3
33MHZ
PCI CLK4
33MHZ
25MHz
PCI SLOT 0
PCI SLOT 1
PCI SLOT 2
TPM
LPC BIOS
DEBUG POST
SUPER IO
IT8716F
HD AUDIO CON
TPM (BCM5755/5761)
DIMM3
D D
DIMM1
3 PAIR MEM CLK
3 PAIR MEM CLK
AM2/AM2g2 CPU
AM2 SOCKET
C C
B B
External clock mode
SIO CLK
48MHZ
32.768KHz
A
Internal clock mode
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
CLOCK DISTRIBUTION
CLOCK DISTRIBUTION
CLOCK DISTRIBUTION
A78LC-M3S
A78LC-M3S
A78LC-M3S
4 42Wednesday, May 19, 2010
4 42Wednesday, May 19, 2010
4 42Wednesday, May 19, 2010
6.0
6.0
6.0
w
5
A
4 3
2
1
D D
C C
B B
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
REVISION HISTORY
REVISION HISTORY
REVISION HISTORY
A78LC-M3S
A78LC-M3S
A78LC-M3S
5 42Wednesday, May 19, 2010
5 42Wednesday, May 19, 2010
5 42Wednesday, May 19, 2010
w
A
6.0
6.0
6.0
5
DCC
A
4
3
2
1
D
HyperTransport 3.0
CPU1A
CPU1A
HTCPU_UPCLK114
HTCPU_UPCLK1_14
HTCPU_UPCLK014
HTCPU_UPCLK0_14
HTCPU_UPCNTL114
HTCPU_UPCNTL1_14
HTCPU_UPCNTL14
HTCPU_UPCNTL_14
B B
HTCPU_UP[15..0]14
HTCPU_UP_[15..0]14
HTCPU_UPCLK1
HTCPU_UPCLK1_
HTCPU_UPCLK0
HTCPU_UPCLK0_
HTCPU_UPCNTL1
HTCPU_UPCNTL1_
HTCPU_UPCNTL
HTCPU_UPCNTL_
HTCPU_UP15
HTCPU_UP_15
HTCPU_UP14
HTCPU_UP_14
HTCPU_UP13
HTCPU_UP_13
HTCPU_UP12
HTCPU_UP_12
HTCPU_UP11
HTCPU_UP_11
HTCPU_UP10
HTCPU_UP_10
HTCPU_UP9
HTCPU_UP_9
HTCPU_UP8
HTCPU_UP_8
HTCPU_UP7
HTCPU_UP_7
HTCPU_UP6
HTCPU_UP_6
HTCPU_UP5
HTCPU_UP_5
HTCPU_UP4
HTCPU_UP_4
HTCPU_UP3
HTCPU_UP_3
HTCPU_UP2
HTCPU_UP_2
HTCPU_UP1
HTCPU_UP_1
HTCPU_UP0
HTCPU_UP_0
HTCPU_UP[15..0]
HTCPU_UP_[15..0]
N6
L0_CLKIN_H1
P6
L0_CLKIN_L1
N3
L0_CLKIN_H0
N2
L0_CLKIN_L0
V4
L0_CTLIN_H1
V5
L0_CTLIN_L1
U1
L0_CTLIN_H0
V1
L0_CTLIN_L0
U6
L0_CADIN_H15
V6
L0_CADIN_L15
T4
L0_CADIN_H14
T5
L0_CADIN_L14
R6
L0_CADIN_H13
T6
L0_CADIN_L13
P4
L0_CADIN_H12
P5
L0_CADIN_L12
M4
L0_CADIN_H11
M5
L0_CADIN_L11
L6
L0_CADIN_H10
M6
L0_CADIN_L10
K4
L0_CADIN_H9
K5
L0_CADIN_L9
J6
L0_CADIN_H8
K6
L0_CADIN_L8
U3
L0_CADIN_H7
U2
L0_CADIN_L7
R1
L0_CADIN_H6
T1
L0_CADIN_L6
R3
L0_CADIN_H5
R2
L0_CADIN_L5
N1
L0_CADIN_H4
P1
L0_CADIN_L4
L1
L0_CADIN_H3
M1
L0_CADIN_L3
L3
L0_CADIN_H2
L2
L0_CADIN_L2
J1
L0_CADIN_H1
K1
L0_CADIN_L1
J3
L0_CADIN_H0
J2
L0_CADIN_L0
SOCKET AM3 941 SMD
SOCKET AM3 941 SMD
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
HT LINK
HT LINK
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
HTCPU_DWNCLK1
AD5
HTCPU_DWNCLK1_
AD4
HTCPU_DWNCLK0
AD1
HTCPU_DWNCLK0_
AC1
HTCPU_DWNCNTL1
Y6
HTCPU_DWNCNTL1_
W6
HTCPU_DWNCNTL
W2
HTCPU_DWNCNTL_
W3
HTCPU_DWN15
Y5
HTCPU_DWN_15
Y4
HTCPU_DWN14
AB6
HTCPU_DWN_14
AA6
HTCPU_DWN13
AB5
HTCPU_DWN_13
AB4
HTCPU_DWN12
AD6
HTCPU_DWN_12
AC6
HTCPU_DWN11
AF6
HTCPU_DWN_11
AE6
HTCPU_DWN10
AF5
HTCPU_DWN_10
AF4
HTCPU_DWN9
AH6
HTCPU_DWN_9
AG6
HTCPU_DWN8
AH5
HTCPU_DWN_8
AH4
HTCPU_DWN7
Y1
HTCPU_DWN_7
W1
HTCPU_DWN6
AA2
HTCPU_DWN_6
AA3
HTCPU_DWN5
AB1
HTCPU_DWN_5
AA1
HTCPU_DWN4
AC2
HTCPU_DWN_4
AC3
HTCPU_DWN3
AE2
HTCPU_DWN_3
AE3
HTCPU_DWN2
AF1
HTCPU_DWN_2
AE1
HTCPU_DWN1
AG2
HTCPU_DWN_1
AG3
HTCPU_DWN0
AH1
HTCPU_DWN_0
AG1
HTCPU_DWN[15..0]
HTCPU_DWN_[15..0]
HTCPU_DWNCLK1 14
HTCPU_DWNCLK1_ 14
HTCPU_DWNCLK0 14
HTCPU_DWNCLK0_ 14
HTCPU_DWNCNTL1 14
HTCPU_DWNCNTL1_ 14
HTCPU_DWNCNTL 14
HTCPU_DWNCNTL_ 14
HTCPU_DWN[15..0] 14
HTCPU_DWN_[15..0] 14
A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
K8 CPU HT
K8 CPU HT
K8 CPU HT
A78LC-M3S
A78LC-M3S
A78LC-M3S
1
6.0
6.0
6.0
6 42Wednesday, May 19, 2010
6 42Wednesday, May 19, 2010
6 42Wednesday, May 19, 2010
5
DCCBBAA
4
3
2
1
Vout=Vref (1.25V) X ( 1+R2/R1 )
CPU_CLKIN_P18
CPU_CLKIN_N18
CPU_PRESENT#20
CPU_TRST#13
CPU_DBREQ#13
CPU_CORE_FB39
CPU_CORE_FB_39
+1.5V_SUS
+1.5V_SUS
1 2
3 4
ACC FUNCTION
HTCPU_RST_1
PWM_PWROK 39
=2.5V
12
CC1
CC1
10UF 10V 0805 Y5V
10UF 10V 0805 Y5V
CPU_TDI13
CPU_TCK13
CPU_TMS13
CRN8
CRN8
1K 8P4R 0402
1K 8P4R 0402
5 6
7 8
4
CC5 3900P 50V X7R 0402CC5 3900P 50V X7R 0402
CC6 3900P 50V X7R 0402CC6 3900P 50V X7R 0402
CR7 10K 0402CR7 10K 0402
+1.5V_SUS
CR34 330 0402CR34 330 0402
+1.5V_SUS
CR15 39.2 1% 0402CR15 39.2 1% 0402
CR18 39.2 1% 0402CR18 39.2 1% 0402
CR19 510 0402CR19 510 0402
CR21 510 0402CR21 510 0402
ALERT
SID
SIC
CPU_VDDA
12
CC2
CC2
10UF 10V 0805 Y5V
10UF 10V 0805 Y5V
+1.5V_SUS
+1.5V_SUS
12
CC3
CC3
0.1UF 16V Y5V 0402
0.1UF 16V Y5V 0402
CR6 169 1% 0402CR6 169 1% 0402
CR29
CR29
330 0402 /NI
330 0402 /NI
SIC
CR32
CR32
330 0402 /NI
330 0402 /NI
SID
+5V
12
CC4
LDT_STOP#16,19
LDT_RST#16,19
CC4
1UF 10V 0603 Y5V 0402
1UF 10V 0603 Y5V 0402
CPU_CORE_FB
CPU_CORE_FB_
+1.5V_SUS
CR13
CR13
16.9 1% 0402
16.9 1% 0402
CR17
CR17
16.9 1% 0402
16.9 1% 0402
IMC_CRST_L20
+1.5V_SUS
1 2
+1.5V_SUS
HTCPU_PWRGD19
CLOSE TO CPU
CC7
CC7
0.1UF 16V Y5V 0402 /NI
0.1UF 16V Y5V 0402 /NI
1 2
CPU_M_VREFF
12
CC8
CC8
1UF 10V 0603 Y5V 0402
1UF 10V 0603 Y5V 0402
CRN3
CRN3
330 8P4R 0402
330 8P4R 0402
3 4
5 6
7 8
+3.3V_DUAL
CR27
CR27
10K 0402 /NI
10K 0402 /NI
HTCPU_STOP_
HTCPU_RST_1
HTCPU_PWRGD
HTCPU_PWRGD
D
+5V
I
O
A
CQ2
CQ2
AZ1117H-ADJ SOT-223
AZ1117H-ADJ SOT-223
12
CC9
CC9
1000P 50V X7R 0402
1000P 50V X7R 0402
+1.5V_SUS
CR26
CR26
10K 0402
10K 0402
B
CQ3
CQ3
2N3904 SOT23
2N3904 SOT23
E
C
CR31
CR31
330 0402
330 0402
G
S
R1
R2
CQ5
CQ5
D
FDV301N SOT23
FDV301N SOT23
CR2
CR2
49.9 1% 0402
49.9 1% 0402
CR3
CR3
49.9 1% 0402
49.9 1% 0402
+1.5V_SUS
CR28
CR28
10K 0402 /NI
10K 0402 /NI
5
HTCPU_PWRGD
HTCPU_STOP_
HTCPU_RST_1
SIC
SID
SA0
ALERT
CPU_M_VREFF
TEST19
TEST18
TEST15
TEST14
TEST12
CQ4
CQ4
G
S
CQ6
CQ6
G
S
2.5VDDA
CPU1D
CPU1D
C10
VDDA_1
D10
VDDA_2
A8
CLKIN_H
B8
CLKIN_L
C9
PWROK
D8
LDTSTOP_L
C7
RESET_L
AL3
CPU_PRESENT_L
AL6
SIC
AK6
SID
AK4
SA0
AL4
ALERT_L
AL10
TDI
AJ10
TRST_L
AH10
TCK
AL9
TMS
A5
DBREQ_L
G2
VDD_FB_H
G1
VDD_FB_L
F3
M_VDDIO_PWRGD
E12
VDDR_SENSE
F12
M_VREF
AH11
M_ZN
AJ11
M_ZP
A10
TEST25_H
B10
TEST25_L
F10
TEST19
E9
TEST18
AJ7
TEST13
F6
TEST9
D6
TEST17
E7
TEST16
F8
TEST15
C5
TEST14
AH9
TEST12
E5
TEST7
AJ5
TEST6
AH7
TEST3
AJ6
TEST2
C18
RSVD1
C20
RSVD2
F2
RSVD3
G24
RSVD4
G25
RSVD5
H25
RSVD6
L25
RSVD7
L26
RSVD8
SOCKET AM3 941 SMD
SOCKET AM3 941 SMD
D
FDV301N SOT23 /NI
FDV301N SOT23 /NI
D
FDV301N SOT23 /NI
FDV301N SOT23 /NI
MISC.
MISC.
INT. MISC.
INT. MISC.
SIO_SIC 31
CR30
CR30
4.7K 0402 /NI
4.7K 0402 /NI
CR33
CR33
4.7K 0402 /NI
4.7K 0402 /NI
+3.3V_DUAL
SIO_SID 31
+3.3V_DUAL
3
+1.5V_SUS
123456
78
CRN5
CRN5
330 8P4R 0402
330 8P4R 0402
G5
CORE_TYPE
D2
VID5
D1
VID4
C1
SVC/VID3
E3
SVD/VID2
E2
PVIEN/VID1
E1
VID0
AG9
THERMDC
AG8
THERMDA
THERMTRIP_L
VDDIO_FB_H
VDDNB_FB_H
VDDNB_FB_L
AK7
AL7
PROCHOT_L
AK10
TDO
B6
DBRDY
AK11
AL11
VDDIO_FB_L
G4
G3
F1
PSI_L
V8
HTREF1
V7
HTREF0
FBCLKOUT
C11
TEST29_H
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
FBCLKOUT*
D11
TEST24
AK8
AH8
TEST22
AJ9
TEST21
AL8
TEST20
AJ8
J10
H9
TEST27
AK9
TEST26
AK5
G7
D4
L30
L31
AD25
AE24
AE25
AJ18
AJ20
AK3
V0.51 modify 1, Pin AJ9 (TEST22) add 300 0402 pull down
2, Pin A5 (DBREQ_L) add 300 0402 pull to +1.8V_SUS
CORE_TYPECORE_TYPE
CPU_THERMTRIP
CPU_PROCHOT#
CPU_TDO
CPU_DBRDY
CR14 44.2 1% 0402CR14 44.2 1% 0402
CR16 44.2 1% 0402CR16 44.2 1% 0402
CR20 80.6 1% 0402CR20 80.6 1% 0402
TEST12
TEST24
TEST20
TEST19
TEST18
TEST15
TEST14
2
CPU_THERMTRIP
1/6 SWAP
K8_VID5
K8_VID4
K8_VID3
K8_VID2
K8_VID1
K8_VID0
78
56
34
12
CRN4
CRN4
1K 8P4R 0402 /NI
1K 8P4R 0402 /NI
78
56
34
12
CRN7
CRN7
330 8P4R 0402 /NI
330 8P4R 0402 /NI
CQ1
CQ1
G
S
K8_VID5 39
K8_VID4 39
K8_VID3 39
K8_VID2 39
K8_VID1 39
K8_VID0 39
CPU_THERMDC 31
CPU_THERMDA 31
CPU_PROCHOT# 19
CPU_TDO 13
CPU_DBRDY 13
CPUNB_VDDHT
+1.5V_SUS
D
FDV301N SOT23
FDV301N SOT23
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU_THERMTRIP# 20
+1.5V_SUS
CRN1
CRN1
1K 8P4R 0402
1K 8P4R 0402
1 2
3 4
5 6
7 8
TEST27
TEST21
TEST26
TEST22
CRN6
CRN6
330 8P4R 0402
330 8P4R 0402
+5V +5V
12
C8
C8
0.1UF 16V Y5V 0402
0.1UF 16V Y5V 0402
K8 CPU MISC
K8 CPU MISC
K8 CPU MISC
A78LC-M3S
A78LC-M3S
A78LC-M3S
1 2
3 4
78
56
34
12
12
C9
C9
0.1UF 16V Y5V 0402
0.1UF 16V Y5V 0402
EMIEMI
5 6
7 8
CRN2
CRN2
1K 8P4R 0402
1K 8P4R 0402
K8_VID2
K8_VID1
K8_VID0
K8_VID5
K8_VID4
K8_VID3
7 42Wednesday, May 19, 2010
7 42Wednesday, May 19, 2010
7 42Wednesday, May 19, 2010
1
6.0
6.0
6.0
5
DCCBBAA
CPU1B
CPU1B
AG21
MA_CLK_H7
AG20
MA_CLK_L7
AE20
MA_CLK_H6
D
MEM_MA0_CLK_H011
MEM_MA0_CLK_L011
MEM_MA0_CLK_H111
MEM_MA0_CLK_L111
MEM_MA0_CS_L111
MEM_MA0_CS_L011
MEM_MA0_ODT111
MEM_MA0_ODT011
MEM_MA_RESET_L11
MEM_MA_CAS_L11
MEM_MA_WE_L11
MEM_MA_RAS_L11
MEM_MA_BANK211
MEM_MA_BANK111
MEM_MA_BANK011
MEM_MA_CKE111
MEM_MA_CKE011
MEM_MA_ADD[15..0]11
MEM_MA_DQS_H[8..0]11
MEM_MA_DQS_L[8..0]11
MEM_MA_DM[8..0]11
MEM_MA_ADD[15..0]
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_DQS_H[8..0]
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DQS_L[8..0]
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
MEM_MA_DM[8..0]
AE19
MA_CLK_L6
U27
MA_CLK_H5
U26
MA_CLK_L5
V27
MA_CLK_H4
W27
MA_CLK_L4
W26
MA_CLK_H3
W25
MA_CLK_L3
U24
MA_CLK_H2
V24
MA_CLK_L2
G19
MA_CLK_H1
H19
MA_CLK_L1
G20
MA_CLK_H0
G21
MA_CLK_L0
AC25
MA0_CS_L1
AA24
MA0_CS_L0
AE28
MA0_ODT1
AC28
MA0_ODT0
AD27
MA1_CS_L1
AA25
MA1_CS_L0
AE27
MA1_ODT1
AC27
MA1_ODT0
E20
MA_RESET_L
AB25
MA_CAS_L
AB27
MA_WE_L
AA26
MA_RAS_L
N25
MA_BANK2
Y27
MA_BANK1
AA27
MA_BANK0
L27
MA_CKE1
M25
MA_CKE0
M27
MA_ADD15
N24
MA_ADD14
AC26
MA_ADD13
N26
MA_ADD12
P25
MA_ADD11
Y25
MA_ADD10
N27
MA_ADD9
R24
MA_ADD8
P27
MA_ADD7
R25
MA_ADD6
R26
MA_ADD5
R27
MA_ADD4
T25
MA_ADD3
U25
MA_ADD2
T27
MA_ADD1
W24
MA_ADD0
AD15
MA_DQS_H7
AE15
MA_DQS_L7
AG18
MA_DQS_H6
AG19
MA_DQS_L6
AG24
MA_DQS_H5
AG25
MA_DQS_L5
AG27
MA_DQS_H4
AG28
MA_DQS_L4
D29
MA_DQS_H3
C29
MA_DQS_L3
C25
MA_DQS_H2
D25
MA_DQS_L2
E19
MA_DQS_H1
F19
MA_DQS_L1
F15
MA_DQS_H0
G15
MA_DQS_L0
AF15
MA_DM7
AF19
MA_DM6
AJ25
MA_DM5
AH29
MA_DM4
B29
MA_DM3
E24
MA_DM2
E18
MA_DM1
H15
MA_DM0
SOCKET AM3 941 SMD
SOCKET AM3 941 SMD
5
4
MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MEM CHA
MEM CHA
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0
MA_DQS_H8
MA_DQS_L8
MA_DM8
MA_CHECK7
MA_CHECK6
MA_CHECK5
MA_CHECK4
MA_CHECK3
MA_CHECK2
MA_CHECK1
MA_CHECK0
MA_EVENT_L
4
3
MEM_MA_DATA[0..63]
MEM_MA_DATA63
AE14
MEM_MA_DATA62
AG14
MEM_MA_DATA61
AG16
MEM_MA_DATA60
AD17
MEM_MA_DATA59
AD13
MEM_MA_DATA58
AE13
MEM_MA_DATA57
AG15
MEM_MA_DATA56
AE16
MEM_MA_DATA55
AG17
MEM_MA_DATA54
AE18
MEM_MA_DATA53
AD21
MEM_MA_DATA52
AG22
MEM_MA_DATA51
AE17
MEM_MA_DATA50
AF17
MEM_MA_DATA49
AF21
MEM_MA_DATA48
AE21
MEM_MA_DATA47
AF23
MEM_MA_DATA46
AE23
MEM_MA_DATA45
AJ26
MEM_MA_DATA44
AG26
MEM_MA_DATA43
AE22
MEM_MA_DATA42
AG23
MEM_MA_DATA41
AH25
MEM_MA_DATA40
AF25
MEM_MA_DATA39
AJ28
MEM_MA_DATA38
AJ29
MEM_MA_DATA37
AF29
MEM_MA_DATA36
AE26
MEM_MA_DATA35
AJ27
MEM_MA_DATA34
AH27
MEM_MA_DATA33
AG29
MEM_MA_DATA32
AF27
MEM_MA_DATA31
E29
MEM_MA_DATA30
E28
MEM_MA_DATA29
D27
MEM_MA_DATA28
C27
MEM_MA_DATA27
G26
MEM_MA_DATA26
F27
MEM_MA_DATA25
C28
MEM_MA_DATA24
E27
MEM_MA_DATA23
F25
MEM_MA_DATA22
E25
MEM_MA_DATA21
E23
MEM_MA_DATA20
D23
MEM_MA_DATA19
E26
MEM_MA_DATA18
C26
MEM_MA_DATA17
G23
MEM_MA_DATA16
F23
MEM_MA_DATA15
E22
MEM_MA_DATA14
E21
MEM_MA_DATA13
F17
MEM_MA_DATA12
G17
MEM_MA_DATA11
G22
MEM_MA_DATA10
F21
MEM_MA_DATA9
G18
MEM_MA_DATA8
E17
MEM_MA_DATA7
G16
MEM_MA_DATA6
E15
MEM_MA_DATA5
G13
MEM_MA_DATA4
H13
MEM_MA_DATA3
H17
MEM_MA_DATA2
E16
MEM_MA_DATA1
E14
MEM_MA_DATA0
G14
MEM_MA_DQS_H8
J28
MEM_MA_DQS_L8
J27
MEM_MA_DM8
J25
MEM_MA_CHECK[7..0]
MEM_MA_CHECK7
K25
MEM_MA_CHECK6
J26
MEM_MA_CHECK5
G28
MEM_MA_CHECK4
G27
MEM_MA_CHECK3 MEM_MB_DQS_H1
L24
MEM_MA_CHECK2
K27
MEM_MA_CHECK1
H29
MEM_MA_CHECK0
H27
W30
MEM_MA_DATA[0..63] 11
MEM_MA_CHECK[7..0] 11
MEM_MA_EVENT_L 11
MEM_MA_EVENT_L
MEM_MB_EVENT_L
78
56
34
12
CRN9
CRN9
1K 8P4R 0402
1K 8P4R 0402
+1.5V_SUS
MEM_MB0_CLK_H012
MEM_MB0_CLK_L012
MEM_MB0_CLK_H112
MEM_MB0_CLK_L112
MEM_MB0_CS_L112
MEM_MB0_CS_L012
MEM_MB0_ODT112
MEM_MB0_ODT012
MEM_MB_RESET_L12
MEM_MB_CAS_L12
MEM_MB_WE_L12
MEM_MB_RAS_L12
MEM_MB_BANK212
MEM_MB_BANK112
MEM_MB_BANK012
MEM_MB_CKE112
MEM_MB_CKE012
MEM_MB_ADD[15..0]12
MEM_MB_DQS_H[8..0]12
MEM_MB_DQS_L[8..0]12
MEM_MB_DM[8..0]12
3
MEM_MB_ADD[15..0]
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_DQS_H[8..0]
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3MEM_MA_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DQS_L[8..0]
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
MEM_MB_DM[8..0]
CPU1C
CPU1C
AJ19
MB_CLK_H7
AK19
MB_CLK_L7
AL19
MB_CLK_H6
AL18
MB_CLK_L6
U31
MB_CLK_H5
U30
MB_CLK_L5
W29
MB_CLK_H4
W28
MB_CLK_L4
Y31
MB_CLK_H3
Y30
MB_CLK_L3
V31
MB_CLK_H2
W31
MB_CLK_L2
A18
MB_CLK_H1
A19
MB_CLK_L1
C19
MB_CLK_H0
D19
MB_CLK_L0
AE30
MB0_CS_L1
AC31
MB0_CS_L0
AF31
MB0_ODT1
AD29
MB0_ODT0
AE29
MB1_CS_L1
AB31
MB1_CS_L0
AG31
MB1_ODT1
AD31
MB1_ODT0
B19
MB_RESET_L
AC29
MB_CAS_L
AC30
MB_WE_L
AB29
MB_RAS_L
N31
MB_BANK2
AA31
MB_BANK1
AA28
MB_BANK0
M31
MB_CKE1
M29
MB_CKE0
N28
MB_ADD15
N29
MB_ADD14
AE31
MB_ADD13
N30
MB_ADD12
P29
MB_ADD11
AA29
MB_ADD10
P31
MB_ADD9
R29
MB_ADD8
R28
MB_ADD7
R31
MB_ADD6
R30
MB_ADD5
T31
MB_ADD4
T29
MB_ADD3
U29
MB_ADD2
U28
MB_ADD1
AA30
MB_ADD0
AK13
MB_DQS_H7
AJ13
MB_DQS_L7
AK17
MB_DQS_H6
AJ17
MB_DQS_L6
AK23
MB_DQS_H5
AL23
MB_DQS_L5
AL28
MB_DQS_H4
AL29
MB_DQS_L4
D31
MB_DQS_H3
C31
MB_DQS_L3
C24
MB_DQS_H2
C23
MB_DQS_L2
D17
MB_DQS_H1
C17
MB_DQS_L1
C14
MB_DQS_H0
C13
MB_DQS_L0
AJ14
MB_DM7
AH17
MB_DM6
AJ23
MB_DM5
AK29
MB_DM4
C30
MB_DM3
A23
MB_DM2
B17
MB_DM1
B13
MB_DM0
SOCKET AM3 941 SMD
SOCKET AM3 941 SMD
2
MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MEM CHB
MEM CHB
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0
MB_DQS_H8
MB_DQS_L8
MB_DM8
MB_CHECK7
MB_CHECK6
MB_CHECK5
MB_CHECK4
MB_CHECK3
MB_CHECK2
MB_CHECK1
MB_CHECK0
MB_EVENT_L
MEM_MB_DATA62
AL13
MEM_MB_DATA61
AL15
MEM_MB_DATA60
AJ15
MEM_MB_DATA59
AF13
MEM_MB_DATA58
AG13
MEM_MB_DATA57
AL14
MEM_MB_DATA56
AK15
MEM_MB_DATA55
AL16
MEM_MB_DATA54
AL17
MEM_MB_DATA53
AK21
MEM_MB_DATA52
AL21
MEM_MB_DATA51
AH15
MEM_MB_DATA50
AJ16
MEM_MB_DATA49
AH19
MEM_MB_DATA48
AL20
MEM_MB_DATA47
AJ22
MEM_MB_DATA46
AL22
MEM_MB_DATA45
AL24
MEM_MB_DATA44
AK25
MEM_MB_DATA43
AJ21
MEM_MB_DATA42
AH21
MEM_MB_DATA41
AH23
MEM_MB_DATA40
AJ24
MEM_MB_DATA39
AL27
MEM_MB_DATA38
AK27
MEM_MB_DATA37
AH31
MEM_MB_DATA36
AG30
MEM_MB_DATA35
AL25
MEM_MB_DATA34
AL26
MEM_MB_DATA33
AJ30
MEM_MB_DATA32
AJ31
MEM_MB_DATA31
E31
MEM_MB_DATA30
E30
MEM_MB_DATA29
B27
MEM_MB_DATA28
A27
MEM_MB_DATA27
F29
MEM_MB_DATA26
F31
MEM_MB_DATA25
A29
MEM_MB_DATA24
A28
MEM_MB_DATA23
A25
MEM_MB_DATA22
A24
MEM_MB_DATA21
C22
MEM_MB_DATA20
D21
MEM_MB_DATA19
A26
MEM_MB_DATA18
B25
MEM_MB_DATA17
B23
MEM_MB_DATA16
A22
MEM_MB_DATA15
B21
MEM_MB_DATA14
A20
MEM_MB_DATA13
C16
MEM_MB_DATA12
D15
MEM_MB_DATA11
C21
MEM_MB_DATA10
A21
MEM_MB_DATA9
A17
MEM_MB_DATA8
A16
MEM_MB_DATA7
B15
MEM_MB_DATA6
A14
MEM_MB_DATA5
E13
MEM_MB_DATA4
F13
MEM_MB_DATA3
C15
MEM_MB_DATA2
A15
MEM_MB_DATA1
A13
MEM_MB_DATA0
D13
MEM_MB_DQS_H8
J31
MEM_MB_DQS_L8
J30
MEM_MB_DM8
J29
MEM_MB_CHECK[7..0]
MEM_MB_CHECK7
K29
MEM_MB_CHECK6
K31
MEM_MB_CHECK5
G30
MEM_MB_CHECK4
G29
MEM_MB_CHECK3
L29
MEM_MB_CHECK2
L28
MEM_MB_CHECK1
H31
MEM_MB_CHECK0
G31
V29
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
K8 CPU MEMORY-1
K8 CPU MEMORY-1
K8 CPU MEMORY-1
MEM_MB_DATA[0..63]
MEM_MB_DATA63
AH13
2
1
MEM_MB_DATA[0..63] 12
MEM_MB_CHECK[7..0] 12
MEM_MB_EVENT_L 12
A78LC-M3S
A78LC-M3S
A78LC-M3S
1
6.0
6.0
8 42Wednesday, May 19, 2010
8 42Wednesday, May 19, 2010
8 42Wednesday, May 19, 2010
6.0
5
A
4 3
2
1
+V_CPU
D D
C C
B B
CPU1E
CPU1E
B3
VDD_1
C2
VDD_2
C4
VDD_3
D3
VDD_4
D5
VDD_5
E4
VDD_6
E6
VDD_7
F5
VDD_8
F7
VDD_9
G6
VDD_10
G8
VDD_11
H7
VDD_12
H11
VDD_13
H23
VDD_14
J8
VDD_15
J12
VDD_16
J14
VDD_17
J16
VDD_18
J18
VDD_19
J20
VDD_20
J22
VDD_21
J24
VDD_22
K7
VDD_23
K9
VDD_24
K11
VDD_25
K13
VDD_26
K15
VDD_27
K17
VDD_28
K19
VDD_29
K21
VDD_30
K23
VDD_31
L4
VDD_32
L5
VDD_33
L8
VDD_34
L10
VDD_35
L12
VDD_36
L14
VDD_37
L16
VDD_38
L18
VDD_39
L20
VDD_40
L22
VDD_41
M2
VDD_42
M3
VDD_43
M7
VDD_44
M9
VDD_45
M11
VDD_46
M13
VDD_47
M15
VDD_48
M17
VDD_49
M19
VDD_50
M21
VDD_51
M23
VDD_52
N8
VDD_53
N10
VDD_54
N12
VDD_55
N14
VDD_56
N16
VDD_57
N18
VDD_58
N20
VDD_59
N22
VDD_60
P7
VDD_61
P9
VDD_62
P11
VDD_63
P13
VDD_64
P15
VDD_65
P17
VDD_66
P19
VDD_67
P21
VDD_68
P23
VDD_69
R4
VDD_70
R5
VDD_71
R8
VDD_72
R10
VDD_73
R12
VDD_74
R14
VDD_75
R16
VDD_76
R18
VDD_77
R20
VDD_78
R22
VDD_79
T2
VDD_80
T3
VDD_81
T7
VDD_82
T9
VDD_83
T11
VDD_84
T13
VDD_85
SOCKET AM3 941 SMD
SOCKET AM3 941 SMD
A3
VSS_1
A7
VSS_2
A9
VSS_3
A11
VSS_4
B4
VSS_5
B9
VSS_6
B11
VSS_7
B14
VSS_8
B16
VSS_9
B18
VSS_10
B20
VSS_11
B22
VSS_12
B24
VSS_13
B26
VSS_14
B28
VSS_15
B30
VSS_16
C3
VSS_17
D14
VSS_18
D16
VSS_19
D18
VSS_20
D20
VSS_21
D22
VSS_22
D24
VSS_23
D26
VSS_24
D28
VSS_25
D30
VSS_26
E11
VSS_27
F4
VSS_28
F14
VSS_29
F16
VSS_30
F18
VSS_31
F20
VSS_32
F22
VSS_33
F24
VSS_34
F26
VSS_35
F28
VSS_36
F30
VSS_37
G9
VSS_38
G11
VSS_39
H8
VSS_40
H10
VSS_41
H12
VSS_42
H14
VSS_43
H16
VSS_44
H18
VSS_45
H24
VSS_46
H26
VSS_47
H28
VSS_48
H30
VSS_49
J4
VSS_50
POWER/GND1
POWER/GND1
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
J5
J7
J9
J11
J13
J15
J17
J19
J21
J23
K2
K3
K8
K10
K12
K14
K16
K18
K20
K22
K24
K26
K28
K30
L7
L9
L11
L13
L15
L17
L19
L21
L23
M8
M10
+V_CPU
CPU1F
CPU1F
T15
VDD_86
T17
VDD_87
T19
VDD_88
T21
VDD_89
T23
VDD_90
U8
VDD_91
U10
VDD_92
U12
VDD_93
U14
VDD_94
U16
VDD_95
U18
VDD_96
U20
VDD_97
U22
VDD_98
V9
VDD_99
V11
VDD_100
V13
VDD_101
V15
VDD_102
V17
VDD_103
V19
VDD_104
V21
VDD_105
V23
VDD_106
W4
VDD_107
W5
VDD_108
W8
VDD_109
W10
VDD_110
W12
VDD_111
W14
VDD_112
W16
VDD_113
W18
VDD_114
W20
VDD_115
W22
VDD_116
Y2
VDD_117
Y3
VDD_118
Y7
VDD_119
Y9
VDD_120
Y11
VDD_121
Y13
VDD_122
Y15
VDD_123
Y17
VDD_124
Y19
VDD_125
Y21
VDD_126
Y23
VDD_127
AA8
VDD_128
AA10
VDD_129
AA12
VDD_130
AA14
VDD_131
AA16
VDD_132
AA18
VDD_133
AA20
VDD_134
AA22
VDD_135
AB7
VDD_136
AB9
VDD_137
AB11
VDD_138
AB13
VDD_139
AB15
VDD_140
AB17
VDD_141
AB19
VDD_142
AB21
VDD_143
AB23
VDD_144
AC4
VDD_145
AC5
VDD_146
AC8
VDD_147
AC10
VDD_148
AC12
VDD_149
AC14
VDD_150
AC16
VDD_151
AC18
VDD_152
AC20
VDD_153
AC22
VDD_154
AD2
VDD_155
AD3
VDD_156
AD7
VDD_157
AD9
VDD_158
AD11
VDD_159
AD23
VDD_160
AE10
VDD_161
AE12
VDD_162
AF7
VDD_163
AF9
VDD_164
AF11
VDD_165
AG4
VDD_166
AG5
VDD_167
AG7
VDD_168
AH2
VDD_169
AH3
VDD_170
SOCKET AM3 941 SMD
SOCKET AM3 941 SMD
M12
VSS_86
M14
VSS_87
M16
VSS_88
M18
VSS_89
M20
VSS_90
M22
VSS_91
N4
VSS_92
N5
VSS_93
N7
VSS_94
N9
VSS_95
N11
VSS_96
N13
VSS_97
N15
VSS_98
N17
VSS_99
N19
VSS_100
N21
VSS_101
N23
VSS_102
P2
VSS_103
P3
VSS_104
P8
VSS_105
P10
VSS_106
P12
VSS_107
P14
VSS_108
P16
VSS_109
P18
VSS_110
P20
VSS_111
P22
VSS_112
R7
VSS_113
R9
VSS_114
R11
VSS_115
R13
VSS_116
R15
VSS_117
R17
VSS_118
R19
VSS_119
R21
VSS_120
R23
VSS_121
T8
VSS_122
T10
VSS_123
T12
VSS_124
T14
VSS_125
T16
VSS_126
T18
VSS_127
T20
VSS_128
T22
VSS_129
U4
VSS_130
U5
VSS_131
U7
VSS_132
U9
VSS_133
U11
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W7
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
Y14
Y16
Y18
Y20
Y22
AA4
AA5
AA7
AA9
POWER/GND2
POWER/GND2
+V_CPU
CPU1G
CPU1G
A4
VDDNB_1
A6
VDDNB_2
B5
VDDNB_3
B7
VDDNB_4
C6
VDDNB_5
C8
VDDNB_6
D7
VDDNB_7
D9
VDDNB_8
E8
VDDNB_9
E10
VDDNB_10
F9
VDDNB_11
F11
VDDNB_12
G10
VDDNB_13
G12
VDDNB_14
B2
NP/RSVD
H20
NP/VSS1
AE7
NP/VSS2
SOCKET AM3 941 SMD
SOCKET AM3 941 SMD
CPUNB_VDDHT
CC10
CC10
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
1 2
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
POWER/GND3
POWER/GND3
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
CC11
CC11
10UF 10V 0805 Y5V
10UF 10V 0805 Y5V
1 2
1 2
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AB2
AB3
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AD8
AD10
AD12
AD14
AD16
AD20
AD22
AD24
AE4
AE5
AE11
AF2
AF3
AF8
AF10
AF12
AF14
AF16
CC12
CC12
10UF 10V 0805 Y5V
10UF 10V 0805 Y5V
CPUNB_VDDHT
+1.5V_SUS
12
CC16
CC16
10UF 10V 0805 Y5V
10UF 10V 0805 Y5V
VLDT_B_1
VLDT_B_2
VLDT_B_3
VLDT_B_4
VDDR_5
VDDR_6
VDDR_7
VDDR_8
VDDR_9
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
+1.2V_HT_CPU
H1
H2
H5
H6
AG12
AH12
AJ12
AK12
AL12
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK2
AK14
AK16
AK18
AK20
AK22
AK24
AK26
AK28
AK30
AL5
CPUNB_VDDHT
CPU1H
CPU1H
AJ1
VLDT_A_1
AJ2
VLDT_A_2
AJ3
VLDT_A_3
AJ4
VLDT_A_4
A12
VDDR_1
B12
VDDR_2
C12
VDDR_3
D12
VDDR_4
M24
VDDIO_1
M26
VDDIO_2
M28
VDDIO_3
M30
VDDIO_4
P24
VDDIO_5
P26
VDDIO_6
P28
VDDIO_7
P30
VDDIO_8
T24
VDDIO_9
T26
VDDIO_10
T28
VDDIO_11
T30
VDDIO_12
V25
VDDIO_13
V26
VDDIO_14
V28
VDDIO_15
V30
VDDIO_16
Y24
VDDIO_17
Y26
VDDIO_18
Y28
VDDIO_19
Y29
VDDIO_20
AB24
VDDIO_21
AB26
VDDIO_22
AB28
VDDIO_23
AB30
VDDIO_24
AC24
VDDIO_25
AD26
VDDIO_26
AD28
VDDIO_27
AD30
VDDIO_28
AF30
VDDIO_29
SOCKET AM3 941 SMD
SOCKET AM3 941 SMD
12
CC14
CC14
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
POWER/GND4
POWER/GND4
+1.2V_HT_CPU
12
CC15
CC15
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
K8 CPU MEMORY-2
K8 CPU MEMORY-2
K8 CPU MEMORY-2
A78LC-M3S
A78LC-M3S
A78LC-M3S
9 42Wednesday, May 19, 2010
9 42Wednesday, May 19, 2010
9 42Wednesday, May 19, 2010
CPUNB_VDDHT
it
A
6.0
6.0
6.0
5
DCC
A
+1.5V_SUS
靠
DDR SOLT
12
C1
C1
0.1UF 16V Y5V 0402
0.1UF 16V Y5V 0402
12
C2
C2
10UF 10V 0805 Y5V
10UF 10V 0805 Y5V
4
12
C3
C3
0.1UF 16V Y5V 0402
0.1UF 16V Y5V 0402
12
C4
C4
0.1UF 16V Y5V 0402 /NI
0.1UF 16V Y5V 0402 /NI
12
C5
C5
0.1UF 16V Y5V 0402 /NI
0.1UF 16V Y5V 0402 /NI
3
12
C6
C6
0.1UF 16V Y5V 0402
0.1UF 16V Y5V 0402
2
1
D
+1.5V_SUS
12
BC1
BC1
10UF 10V 0805 Y5V /NI
10UF 10V 0805 Y5V /NI
+1.5V_SUS
12
CC32
CC32
0.1UF 16V Y5V 0402
0.1UF 16V Y5V 0402
+V_CPU
12
BC4
BC4
1UF 16V 0805 Y5V /NI
1UF 16V 0805 Y5V /NI
B B
+V_CPU
12
C139
C139
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
12
BC2
BC2
10UF 10V 0805 Y5V /NI
10UF 10V 0805 Y5V /NI
CC34
CC34
10UF 10V 0805 Y5V
10UF 10V 0805 Y5V
12
BC5
BC5
1UF 16V 0805 Y5V /NI
1UF 16V 0805 Y5V /NI
12
C140
C140
10UF 10V 0805 Y5V
10UF 10V 0805 Y5V
12
BC3
BC3
10UF 10V 0805 Y5V /NI
10UF 10V 0805 Y5V /NI
12
CC21
CC21
10UF 10V 0805 Y5V
10UF 10V 0805 Y5V
12
BC6
BC6
1UF 16V 0805 Y5V /NI
1UF 16V 0805 Y5V /NI
12
C30
C30
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
12
CC24
CC24
0.1UF 16V Y5V 0402
0.1UF 16V Y5V 0402
12
BC7
BC7
1UF 16V 0805 Y5V /NI
1UF 16V 0805 Y5V /NI
12
C555
C555
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
12
BC8
BC8
1UF 16V 0805 Y5V /NI
1UF 16V 0805 Y5V /NI
12
C556
C556
1UF 16V 0805 Y5V /NI
1UF 16V 0805 Y5V /NI
12
BC9
BC9
1UF 16V 0805 Y5V /NI
1UF 16V 0805 Y5V /NI
12
C35
C35
1UF 16V 0805 Y5V /NI
1UF 16V 0805 Y5V /NI
12
BC10
BC10
1UF 16V 0805 Y5V /NI
1UF 16V 0805 Y5V /NI
12
C36
C36
10UF 10V 0805 Y5V /NI
10UF 10V 0805 Y5V /NI
12
BC11
BC11
1UF 16V 0805 Y5V /NI
1UF 16V 0805 Y5V /NI
12
C38
C38
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
12
BC12
BC12
1UF 16V 0805 Y5V /NI
1UF 16V 0805 Y5V /NI
+V_CPU
12
C46
C46
10UF 10V 0805 Y5V
10UF 10V 0805 Y5V
5
12
C25
C25
10UF 10V 0805 Y5V
10UF 10V 0805 Y5V
12
C26
C26
10UF 10V 0805 Y5V
10UF 10V 0805 Y5V
4
12
C145
C145
10UF 10V 0805 Y5V
10UF 10V 0805 Y5V
12
C312
C312
1UF 16V 0805 Y5V
1UF 16V 0805 Y5V
A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
3
2
CPU DECPOULING CAP
CPU DECPOULING CAP
CPU DECPOULING CAP
A78LC-M3S
A78LC-M3S
A78LC-M3S
10 42Wednesday, May 19, 2010
10 42Wednesday, May 19, 2010
10 42Wednesday, May 19, 2010
1
6.0
6.0
6.0
5
DCC
A
4
3
2
1
MEM_MA_DQS_L[8..0]8
MEM_MA_DQS_H[8..0]8
D
MEM_MA_DM[8..0]8
B B
SDATA12,18,20
SCLK12,18,20
MEM_MA_ADD[15..0]8
MEM_MA_DQS_L[8..0]
MEM_MA_DQS_H[8..0]
MEM_MA_DQS_L0
MEM_MA_DQS_H0
MEM_MA_DQS_L1
MEM_MA_DQS_H1
MEM_MA_DQS_L2
MEM_MA_DQS_H2
MEM_MA_DQS_L3
MEM_MA_DQS_H3
MEM_MA_DQS_L4
MEM_MA_DQS_H4
MEM_MA_DQS_L5
MEM_MA_DQS_H5
MEM_MA_DQS_L6
MEM_MA_DQS_H6
MEM_MA_DQS_L7
MEM_MA_DQS_H7
MEM_MA_DQS_L8
MEM_MA_DQS_H8
MEM_MA_DM[8..0]
MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7
MEM_MA_DM8
MEM_MA_CHECK[7..0]
MEM_MA_CHECK0
MEM_MA_CHECK2
MEM_MA_CHECK3
MEM_MA_CHECK4
MEM_MA_CHECK5
MEM_MA_CHECK6
MEM_MA_CHECK7
MEM_MA_ADD[15..0]
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15
DDR3_A1A
DDR3_A1A
6
DQS0-
7
DQS0
15
DQS1-
16
DQS1
24
DQS2-
25
DQS2
33
DQS3-
34
DQS3
84
DQS4-
85
DQS4
93
DQS5-
94
DQS5
102
DQS6-
103
DQS6
111
DQS7-
112
DQS7
42
DQS8-
43
DQS8
125
DM0/DQS9
126
DQS9-
134
DM1/DQS10
135
DQS10-
143
DM2/DQS11
144
DQS11-
152
DM3/DQS12
153
DQS12-
203
DM4/DQS13
204
DQS13-
212
DM5/DQS14
213
DQS14-
221
DM6/DQS15
222
DQS15-
230
DM7/DQS16
231
DQS16-
161
DM8/DQS17
162
DQS17-
39
CB0
40
CB1
45
CB2
46
CB3
158
CB4
159
CB5
164
CB6
165
CB7
79
RSVD
238
SDA
118
SCL
188
A0
181
A1
61
A2
180
A3
59
A4
58
A5
178
A6
56
A7
177
A8
175
A9
70
A10
55
A11
174
A12
196
A13
172
A14
171
A15
DDR3-240 PIN-R
DDR3-240 PIN-R
BLACK
BLACK
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
NC/PAR_IN
NC/ERR_OUT
NC/TEST4
MEM_MA_DATA[0..63]
234
233
228
227
115
114
109
108
225
224
219
218
106
105
100
99
216
215
210
209
97
96
91
90
207
206
201
200
88
87
82
81
156
155
150
149
37
36
31
30
147
146
141
140
28
27
22
21
138
137
132
131
19
18
13
12
129
128
123
122
10
9
4
3
68
53
167
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA59
MEM_MA_DATA58
MEM_MA_DATA57
MEM_MA_DATA56
MEM_MA_DATA55
MEM_MA_DATA54
MEM_MA_DATA53
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA49
MEM_MA_DATA48
MEM_MA_DATA47
MEM_MA_DATA46
MEM_MA_DATA45
MEM_MA_DATA44
MEM_MA_DATA43
MEM_MA_DATA42
MEM_MA_DATA41
MEM_MA_DATA40
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA37
MEM_MA_DATA36
MEM_MA_DATA35
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA31
MEM_MA_DATA30
MEM_MA_DATA29
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA26
MEM_MA_DATA25
MEM_MA_DATA24
MEM_MA_DATA23
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA20MEM_MA_CHECK1
MEM_MA_DATA19
MEM_MA_DATA18
MEM_MA_DATA17
MEM_MA_DATA16
MEM_MA_DATA15
MEM_MA_DATA14
MEM_MA_DATA13
MEM_MA_DATA12
MEM_MA_DATA11
MEM_MA_DATA10
MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA7
MEM_MA_DATA6
MEM_MA_DATA5
MEM_MA_DATA4
MEM_MA_DATA3
MEM_MA_DATA2
MEM_MA_DATA1
MEM_MA_DATA0
MEM_MA_DATA[0..63]8
+1.5V_SUS
+3.3V
DIMM_CA_VREF12
DIMM_DQ_VREF12
MEM_MA_CKE08
MEM_MA_CKE18
MEM_MA_BANK08
MEM_MA_BANK18
MEM_MA_BANK28
MEM_MA_RESET_L8
MEM_MA_WE_L8MEM_MA_CHECK[7..0]8
MEM_MA_RAS_L8
MEM_MA_CAS_L8
MEM_MA0_CS_L08
MEM_MA0_CS_L18
MEM_MA0_ODT08
MEM_MA0_ODT18
MEM_MA0_CLK_L18
MEM_MA0_CLK_H18
MEM_MA0_CLK_L08
MEM_MA0_CLK_H08
MEM_MA_EVENT_L8
DIMM_CA_VREF
DIMM_DQ_VREF
DDR3_A1B
DDR3_A1B
51
VDDQ1 (P)
54
VDDQ2 (P)
57
VDDQ3 (P)
60
VDDQ4 (P)
62
VDDQ5 (P)
65
VDDQ6 (P)
66
VDDQ7 (P)
69
VDDQ8 (P)
72
VDDQ9 (P)
75
VDDQ10 (P)
78
VDDQ11 (P)
170
VDD1 (P)
173
VDD2 (P)
176
VDD3 (P)
179
VDD4 (P)
182
VDD5 (P)
183
VDD6 (P)
186
VDD7(P)
189
VDD8(P)
191
VDD9(P)
194
VDD10(P)
197
VDD11(P)
236
VDDSPD(P)
67
VREFCA
1
VREFDQ
117
SA0
237
SA1
50
CKE0
169
CKE1
71
BA0
190
BA1
52
A16/BA2
168
RESET
73
WE-
192
RAS-
74
CAS-
193
S-0
76
S-1
195
ODT0
77
ODT1
64
CK-1
63
CK1
185
CK-0
184
CK0
48
FREE1
49
FREE2
187
FREE3
198
FREE4
DDR3-240 PIN-R
DDR3-240 PIN-R
VSS1(P)
VSS2(P)
VSS3(P)
VSS4(P)
VSS5(P)
VSS6(P)
VSS7(P)
VSS8(P)
VSS9(P)
VSS10(P)
VSS11(P)
VSS12(P)
VSS13(P)
VSS60(P)
VSS14(P)
VSS15(P)
VSS16(P)
VSS17(P)
VSS18(P)
VSS19(P)
VSS20(P)
VSS21(P)
VSS22(P)
VSS23(P)
VSS24(P)
VSS25(P)
VSS26(P)
VSS27(P)
SA2
VSS29(P)
VSS30(P)
VSS31(P)
VSS32(P)
VSS33(P)
VSS34(P)
VSS35(P)
VSS36(P)
VSS37(P)
VSS38(P)
VSS39(P)
VSS40(P)
VSS41(P)
VSS42(P)
VSS43(P)
VSS44(P)
VSS45(P)
VSS46(P)
VSS47(P)
VSS48(P)
VSS49(P)
VSS50(P)
VSS51(P)
VSS52(P)
VSS53(P)
VSS54(P)
VSS55(P)
VSS56(P)
VSS57(P)
VSS58(P)
VSS59(P)
VTT
VTT
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
80
83
86
92
95
98
101
104
107
110
113
116
119
121
124
127
130
133
136
139
142
145
148
151
154
157
160
163
166
199
202
205
208
211
214
217
220
223
226
229
232
235
239
89
120
240
MEM_VTT
+1.5V_SUS
R610
R610
16.9 1% 0402
16.9 1% 0402
R611
16.9 1% 0402
16.9 1% 0402
+1.5V_SUS
R612
R612
16.9 1% 0402
16.9 1% 0402
R613
R613
16.9 1% 0402
16.9 1% 0402
MEM_VTT
C588
C588
0.1UF 16V Y5V 0402
0.1UF 16V Y5V 0402
DIMM_DQ_VREF
C580
C580R611
0.1UF 16V Y5V 0402
0.1UF 16V Y5V 0402
DIMM_CA_VREF
C585
C585
0.1UF 16V Y5V 0402
0.1UF 16V Y5V 0402
A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
DDR DIMM-1
DDR DIMM-1
DDR DIMM-1
A78LC-M3S
A78LC-M3S
A78LC-M3S
1
6.0
6.0
6.0
11 42Wednesday, May 19, 2010
11 42Wednesday, May 19, 2010
11 42Wednesday, May 19, 2010
5
DCC
A
4
3
2
1
MEM_MB_DQS_L[8..0]8
MEM_MB_DQS_H[8..0]8 MEM_MB_DATA[0..63]8
D
MEM_MB_DM[8..0]8
MEM_MB_CHECK[7..0]8
B B
SDATA11,18,20
SCLK11,18,20
MEM_MB_ADD[15..0]8
5
MEM_MB_DQS_L[8..0]
MEM_MB_DQS_H[8..0]
MEM_MB_DQS_L0
MEM_MB_DQS_H0
MEM_MB_DQS_L1
MEM_MB_DQS_H1
MEM_MB_DQS_L2
MEM_MB_DQS_H2
MEM_MB_DQS_L3
MEM_MB_DQS_H3
MEM_MB_DQS_L4
MEM_MB_DQS_H4
MEM_MB_DQS_L5
MEM_MB_DQS_H5
MEM_MB_DQS_L6
MEM_MB_DQS_H6
MEM_MB_DQS_L7
MEM_MB_DQS_L8
MEM_MB_DQS_H8
MEM_MB_DM[8..0]
MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
MEM_MB_DM8
MEM_MB_CHECK[7..0]
MEM_MB_CHECK0
MEM_MB_CHECK1
MEM_MB_CHECK2
MEM_MB_CHECK3
MEM_MB_CHECK4
MEM_MB_CHECK5
MEM_MB_CHECK6
MEM_MB_CHECK7
MEM_MB_ADD[15..0]
MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15
DDR3_B1A
DDR3_B1A
6
DQS0-
7
DQS0
15
DQS1-
16
DQS1
24
DQS2-
25
DQS2
33
DQS3-
34
DQS3
84
DQS4-
85
DQS4
93
DQS5-
94
DQS5
102
DQS6-
103
DQS6
111
DQS7-
112
DQS7
42
DQS8-
43
DQS8
125
DM0/DQS9
126
DQS9-
134
DM1/DQS10
135
DQS10-
143
DM2/DQS11
144
DQS11-
152
DM3/DQS12
153
DQS12-
203
DM4/DQS13
204
DQS13-
212
DM5/DQS14
213
DQS14-
221
DM6/DQS15
222
DQS15-
230
DM7/DQS16
231
DQS16-
161
DM8/DQS17
162
DQS17-
39
CB0
40
CB1
45
CB2
46
CB3
158
CB4
159
CB5
164
CB6
165
CB7
79
RSVD
238
SDA
118
SCL
188
A0
181
A1
61
A2
180
A3
59
A4
58
A5
178
A6
56
A7
177
A8
175
A9
70
A10
55
A11
174
A12
196
A13
172
A14
171
A15
DDR3-240 PIN-R
DDR3-240 PIN-R
BLACK
BLACK
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
NC/PAR_IN
NC/ERR_OUT
NC/TEST4
4
MEM_MB_DATA[0..63]
MEM_MB_DATA63
234
MEM_MB_DATA62
233
MEM_MB_DATA61
228
MEM_MB_DATA60
227
MEM_MB_DATA59
115
MEM_MB_DATA58
114
MEM_MB_DATA57
109
MEM_MB_DATA56
108
MEM_MB_DATA55
225
MEM_MB_DATA54
224
MEM_MB_DATA53
219
MEM_MB_DATA52
218
MEM_MB_DATA51
106
MEM_MB_DATA50
105
MEM_MB_DATA49
100
MEM_MB_DATA48MEM_MB_DQS_H7
99
MEM_MB_DATA47
216
MEM_MB_DATA46
215
MEM_MB_DATA45
210
MEM_MB_DATA44
209
MEM_MB_DATA43
97
MEM_MB_DATA42
96
MEM_MB_DATA41
91
MEM_MB_DATA40
90
MEM_MB_DATA39
207
MEM_MB_DATA38
206
MEM_MB_DATA37
201
MEM_MB_DATA36
200
MEM_MB_DATA35
88
MEM_MB_DATA34
87
MEM_MB_DATA33
82
MEM_MB_DATA32
81
MEM_MB_DATA31
156
MEM_MB_DATA30
155
MEM_MB_DATA29
150
MEM_MB_DATA28
149
MEM_MB_DATA27
37
MEM_MB_DATA26
36
MEM_MB_DATA25
31
MEM_MB_DATA24
30
MEM_MB_DATA23
147
MEM_MB_DATA22
146
MEM_MB_DATA21
141
MEM_MB_DATA20
140
MEM_MB_DATA19
28
MEM_MB_DATA18
27
MEM_MB_DATA17
22
MEM_MB_DATA16
21
MEM_MB_DATA15
138
MEM_MB_DATA14
137
MEM_MB_DATA13
132
MEM_MB_DATA12
131
MEM_MB_DATA11
19
MEM_MB_DATA10
18
MEM_MB_DATA9
13
MEM_MB_DATA8
12
MEM_MB_DATA7
129
MEM_MB_DATA6
128
MEM_MB_DATA5
123
MEM_MB_DATA4
122
MEM_MB_DATA3
10
MEM_MB_DATA2
9
MEM_MB_DATA1
4
MEM_MB_DATA0
3
68
53
167
MEM_VTT
1 2
DIMM_CA_VREF
C586
C586
0.1UF 16V Y5V 0402
0.1UF 16V Y5V 0402
DIMM_DQ_VREF
C582
C582
0.1UF 16V Y5V 0402
0.1UF 16V Y5V 0402
C590
C590
0.1UF 16V Y5V 0402
0.1UF 16V Y5V 0402
3
MEM_VTT
1 2
DIMM_CA_VREF11
DIMM_DQ_VREF11
MEM_MB_CKE08
MEM_MB_CKE18
MEM_MB_BANK08
MEM_MB_BANK18
MEM_MB_BANK28
MEM_MB_RESET_L8
MEM_MB_WE_L8
MEM_MB_RAS_L8
MEM_MB_CAS_L8
MEM_MB0_CS_L08
MEM_MB0_CS_L18
MEM_MB0_ODT08
MEM_MB0_ODT18
MEM_MB0_CLK_L18
MEM_MB0_CLK_H18
MEM_MB0_CLK_L08
MEM_MB0_CLK_H08
MEM_MB_EVENT_L8
C591
C591
0.1UF 16V Y5V 0402
0.1UF 16V Y5V 0402
+1.5V_SUS
+3.3V
DIMM_CA_VREF
DIMM_DQ_VREF
+3.3V
DDR3_B1B
DDR3_B1B
51
VDDQ1 (P)
54
VDDQ2 (P)
57
VDDQ3 (P)
60
VDDQ4 (P)
62
VDDQ5 (P)
65
VDDQ6 (P)
66
VDDQ7 (P)
69
VDDQ8 (P)
72
VDDQ9 (P)
75
VDDQ10 (P)
78
VDDQ11 (P)
170
VDD1 (P)
173
VDD2 (P)
176
VDD3 (P)
179
VDD4 (P)
182
VDD5 (P)
183
VDD6 (P)
186
VDD7(P)
189
VDD8(P)
191
VDD9(P)
194
VDD10(P)
197
VDD11(P)
236
VDDSPD(P)
67
VREFCA
1
VREFDQ
117
SA0
237
SA1
50
CKE0
169
CKE1
71
BA0
190
BA1
52
A16/BA2
168
RESET
73
WE-
192
RAS-
74
CAS-
193
S-0
76
S-1
195
ODT0
77
ODT1
64
CK-1
63
CK1
185
CK-0
184
CK0
48
FREE1
49
FREE2
187
FREE3
198
FREE4
DDR3-240 PIN-R
DDR3-240 PIN-R
2
2
VSS1(P)
5
VSS2(P)
8
VSS3(P)
11
VSS4(P)
14
VSS5(P)
17
VSS6(P)
20
VSS7(P)
23
VSS8(P)
26
VSS9(P)
29
VSS10(P)
32
VSS11(P)
35
VSS12(P)
38
VSS13(P)
41
VSS60(P)
44
VSS14(P)
47
VSS15(P)
80
VSS16(P)
83
VSS17(P)
86
VSS18(P)
92
VSS19(P)
95
VSS20(P)
98
VSS21(P)
101
VSS22(P)
104
VSS23(P)
107
VSS24(P)
110
VSS25(P)
113
VSS26(P)
116
VSS27(P)
119
SA2
121
VSS29(P)
124
VSS30(P)
127
VSS31(P)
130
VSS32(P)
133
VSS33(P)
136
VSS34(P)
139
VSS35(P)
142
VSS36(P)
145
VSS37(P)
148
VSS38(P)
151
VSS39(P)
154
VSS40(P)
157
VSS41(P)
160
VSS42(P)
163
VSS43(P)
166
VSS44(P)
199
VSS45(P)
202
VSS46(P)
205
VSS47(P)
208
VSS48(P)
211
VSS49(P)
214
VSS50(P)
217
VSS51(P)
220
VSS52(P)
223
VSS53(P)
226
VSS54(P)
229
VSS55(P)
232
VSS56(P)
235
VSS57(P)
239
VSS58(P)
89
VSS59(P)
120
VTT
240
VTT
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
MEM_VTT
DDR DIMM-2
DDR DIMM-2
DDR DIMM-2
A78LC-M3S
A78LC-M3S
A78LC-M3S
12 42Wednesday, May 19, 2010
12 42Wednesday, May 19, 2010
12 42Wednesday, May 19, 2010
1
6.0
6.0
6.0
A
5
DCCBBAA
4
3
2
1
TDO_POWER
B
Q106
Q106
2N3904 SOT23
C
E
E
E
C
E
C
2N3904 SOT23
E
TRST#_POWER
B
Q107
Q107
2N3904 SOT23
2N3904 SOT23
C
TDI_POWER
B
Q110
Q110
2N3904 SOT23
2N3904 SOT23
C
TMS_POWER
B
Q111
Q111
2N3904 SOT23
2N3904 SOT23
C
DBREQ#_POWER
B
Q112
Q112
2N3904 SOT23
2N3904 SOT23
E
DBRDY_POWER
B
Q113
Q113
2N3904 SOT23
2N3904 SOT23
C
TCK_POWER
B
Q114
Q114
2N3904 SOT23
2N3904 SOT23
E
CPU_TDO 7
CPU_TRST# 7
CPU_TDI 7
CPU_TMS 7
IMC_DBREQ# 20
IMC_DBRDY 20
IMC_TCK 20
4
D
IMC_TDI20
IMC_TRST#20
IMC_TDO20
IMC_TMS20
CPU_DBREQ#7
CPU_DBRDY7
CPU_TCK7
5
+1.5V_SUS
+1.5V_SUS
+1.5VDIMM_FB40
OV_CHIP41
OV_VCORE39
+3.3V
+3.3V
78
56
34
12
RN102
RN102
10K 8P4R 0402
10K 8P4R 0402
78
56
34
12
RN103
RN103
10K 8P4R 0402
10K 8P4R 0402
78
56
34
12
RN95
RN95
10K 8P4R 0402 /NI
10K 8P4R 0402 /NI
78
56
34
12
RN96
RN96
10K 8P4R 0402 /NI
10K 8P4R 0402 /NI
TDI_POWER
TMS_POWER
TRST#_POWER
TDO_POWER
TCK_POWER
DBREQ#_POWER
DBRDY_POWER
R624 4.64K 1% 0402R624 4.64K 1% 0402
R625 1.87K 1% 0402R625 1.87K 1% 0402
R626 931 1% 0402R626 931 1% 0402
R629 1.58K 1% 0402R629 1.58K 1% 0402
R630 806 1% 0402R630 806 1% 0402
R634 1.27K 1% 0402R634 1.27K 1% 0402
R636 649 1% 0402R636 649 1% 0402
IMC_TMS
IMC_TDI
IMC_TDO
IMC_TRST#
IMC_DBRDY
IMC_DBREQ#
IMC_TCK
3
VDIMM0 31
VDIMM1 31
VDIMM2 31
VCHIP0 31
VCHIP1 31
OVCPU0 31
OVCPU1 31
+1.5VDIMM_FB
Default
1.509V
1.547V
1.605V
1.644V
1.703V
1.742V
1.799V
1.838V
+1.2V / +1.296V
+1.250V / +1.346V
+1.299V / +1.403V
+1.349V / +1.452V
1+1.204V
+1.246V
0
+1.284V
1
+1.324V
0
1
0
1
0
1
0
1
0
OV_NB_1P1_FB0
1
0
1
0
VDIMM1
1
1
0
0
1
1
0
1
1
1
1
0
0
0
00
OV_NB_1P1_FB1
1
1
0
0
VDIMM0 VDIMM2
OV_SB_1P1_FB1OV_SB_1P1_FB0
1
1
0
0
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
OV/ACC FUNCTION
OV/ACC FUNCTION
OV/ACC FUNCTION
A78LC-M3S
A78LC-M3S
A78LC-M3S
13 42Wednesday, May 19, 2010
13 42Wednesday, May 19, 2010
13 42Wednesday, May 19, 2010
1
6.0
6.0
6.0
Loading...