Biostar A78DG-A2T Schematic
5
A
4
3
2
1
D D
C C
B B
PAGE
1
2
3
4
5
6-10
11
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48
CONTENTS
COVER
BLOCK DIAGRAM
POWER DELIVERY
CLOCK DISTRIBUTION
REVISION HISTROY
SKT 940 K8 M2 CPU
CPU DECOUPLING
DDR ADD/CTL/VTT TER
DDR2 DIMMA1/A2
DDR2 DIMMB1/B2
RS780D-HT LINK I/F
RS780D-PCIE I/F
RS780D-SYSTEM I/F
RS780D-SPMEM
RS780D-POWER
CLOCK GEN
SB750-PCIE/PCI/CPU/LPC
SB750-ACPI/GPIO/USB/AUD
SB750-SATA/IDE/HWM/SPI
SB750-POWER&DECOUPLING
SB750-STRAPS
PE X16 SLOT 1/2
VGA
DVI
PCIEX1 & MDV_SOLT
PCI SLOT 1/2
IDE ATA 133
USB CONN
FRONT USB
Super I/O ITE8718F
FAN & POWER CONN
K/B, MOUSE & FDD
H/W MONITOR/COM/PARALLE
FRONT PANEL/LED
CODEC ALC662/888
AUDIO CONNECTOR
ADO Extreme
Over Voltage IC
VCC_CORE DC-DC CONVER
PWRGD/ Misc DC-DC
MEM POWER
NB/SB CORE POWER
RTL8111C/RTL8102E
BOM
A78DG-A2T ( RS780D&SB750 )
REV 6.0
AMD AM2+
DDR2 X 4 (Dual channel)
PCI-EX16 X 1
PCI-EX1 X 2
PCI X 3
RELTEK 10/100/1000 PCI-E Lan
A
Title
Size Document Number Rev
Custom
Date: Sheet of
5
4
3
2
COVER
A78DG-A2T
1
1 48Friday, May 29, 2009
6.0
5
A
4
3
2
1
34
PCIE
SLOT
PCIE
SLOT
32
UNBUFFERED
DDRII DIMM3
UNBUFFERED
DDRII DIMM4
8X
(RS780D)
27
16X
27
10,12,13
AMD
AM2/AM2g2
Clock
D D
Generator
DVI CON
HDMI CON
VGA CON
19
HyperTransport
Link
26
26
25
OPTION
2CH TMDS
AM2 SOCKET
OUT
IN
6,7,8,9
16x16
RS780/RS780D
HyperTransport LINK0 CPU I/F
DX10 IGP
LVDS/TVOUT/TMDS
DISPLAY PORT X2
Side Port Memory
1 X16 GFX PCIE I/F (RS780)
2 X8 GFX PCIE I/F (RS780D)
1 X4 PCIE I/F WITH SB
6 X1 GPP PCIE I/F
14,15,16,17,18
C C
4X
PCIE
USB-7
USB-8
USB-6 USB-3USB-4
30
USB-9
31
USB-5
USB-11USB-10
31 30 30
B B
USB-2
PCI BUS
USB-0
3030313130
31
USB-12
31
SPI ROM SPI I/F
22
USB 2.0
USB 1.1
SB700(SB710,SB750)
USB2.0 (12)+ 1.1(2)
SATA II (6 PORTS)
AZALIA HD AUDIO
ATA 66/100/133
SPI I/F
LPC I/F(S5)
ACPI 1.1
INT RTC
HW MONITOR
PCI/PCI BDGE
20, 21, 22, 23,24
DDRII 400,533,667,800
128bit
DDRII 400,533,667,800
Side port
I2C I/F
16X
PCIE GPP[3:0]
X4
28
HD AUDIO I/F
SATA II I/F
ATA 66/100/133 I/F
HW MONITOR I/F
IR I/F
FRAME BUFFER
DDR3 512MBIT
BOOTSTRAPS
ROM(NB)
6 1X PCIE INTERFACE
PCIE GPP4
X1
28
UNBUFFERED
DDRII DIMM1
UNBUFFERED
DDRII DIMM2
DDRII FIRST LOGICAL DIMM DDRII SECOND LOGICAL DIMM
17
17
PCIE GPP5
GIGABIT
BCM5761/5755
HD AUDIO HDR
iSATA#0 to #5
IDE CON
HW
MONITOR
IR Transceiver
34
22
34
10,12,13
11,12,13 11,12,13
8X
16X or 8X
USB-1
HD AUDIO
REAR CON
(5761)
32
34
22
DESKTOP AM2/AM2g2
POWER
DDR2
MEMORY
POWER
5
37,38
PCI SLOT
#1
RS780D
CORE POWER
+1.1V, +1.2V
39
POWER
PCI SLOT
29
40
42
29
#2
ITE LPC SIO
8716F
KBD
MOUSE
COM
4
FLOPPY
3
LPC I/F
33
3536
TPM 1.2
LPC
BIOS
2
35
35
Title
Size Document Number Rev
Custom
Date: Sheet of
BLOCK DIAGRAM
A78DG-A2T
1
A
6.0
2 48Friday, May 29, 2009
5
A
4
3
2
1
ATX P/S WITH 1A STBY CURRENT
5V
5VSB
+/-5%
+/-5%
3.3V
+/-5%
12V
+/-5%
-12V
+/-5%
CPU
PW
12V
+/-5%
D D
+5VDUAL_MEM (S0,S5)
VCC 1.1V SW
REGULATOR
VCC 1.2V SW
REGULATOR
+3.3VSB (S0, S1, S3, S4, S5)
+3.3VSB REGULATOR
C C
ACPI CONTROLLER
+3.3VDUAL (S0, S1, S3, S4, S5)
+5VDUAL (S0, S1, S3, S4, S5)
2.5V SHUNT
REGULATOR
VRM SW
REGULATOR
1.8V VDD SW
REGULATOR
VCC 1.1V SW
REGULATOR
+1.1V (S0, S1)
1.8V LINEAR
REGULATOR
VDD_CPUCORE_RUN (S0, S1)/VDD_CPUNB_RUN (S0, S1)
0.9V VTT_DDR
REGULATOR
+1.1V RS780; +1.2V RS780D (S0, S1)
+1.8V(S0, S1)
1.5V LINEAR
+1.2V(S0, S1)
1.2V STB LDO
REGULATOR
+1.2VSB (S5)
REGULATOR
DDRII DIMMs
VTT_DDR 2A
VDD MEM 12A
+1.5V(S0, S1)
CPU_VDDA_RUN(S0, S1)
CPU_VTT_SUS (S0,S1,S3)
CPU_VDDIO_SUS(S0,S1,S3)
AM2
VDDA 2.5V 0.2A
VDDCORE
0.8-1.55V 110A
DDRII MEM I/F
VTT 2A, VDD 10A
VLDT 1.2V 0.5A
RS780
VDDHT/RX 1.1V 1.2A
VDDHTTX 1.2V 0.5A
VDDPCIE 1.1V 2A
NB CORE VDDC
1.1V 10A
VDDA18PCIE 1.8V 0.9A
PLLs 1.8V 0.1A
VDD18/VDD18_MEM
1.8V 0.01A
VDD_MEM 1.8V/1.5V 0.5A
AVDD 3.3V 0.135A
SB700(SB710,SB750)
X4 PCI-E 0.8A
ATA I/O 0.5A
ATA PLL 0.01A
PCI-E PVDD 80mA
SB CORE 0.6A
CLOCK
1.2V S5 PW 0.22A
3.3V S5 PW 0.01A
USB CORE I/O 0.2A
3.3V I/O 0.45A
AZALIA CODEC CON
B B
3
USB X6 FR
VDD
5VDual
2.0A
USB X6 RL 2XPS/2
VDD
5VDual
2.0A
5VDual
1.0A
GBE
3.3V 0.5A (S0, S1)
3.3V 0.1A (S3)
2
Title
Size Document Number Rev
Custom
Date: Sheet of
+3.3VDUAL (S0, S1, S3)
5
PCI Slot (per slot)
5V
3.3V
12V
3.3Vaux
-12V
0.375A
5.0A
7.6A
0.5A
0.1A
3.3V
3.3Vaux
4
0.5A
0.1A
X16 PCIEX1 PCIE per
3.3V
12V12V
3.0A3.0A
5.5A
X16 PCIE
3.3V
12V
3.0A
5.5A
3.3V CORE 0.3A
5V ANALOG 0.1A
12V 0.1A
POWER DELIVERY
A78DG-A2T
3 48Friday, May 29, 2009
1
A
6.0
5
A
DIMM4DIMM3
4
3
2
1
D D
DIMM1 DIMM2
3 PAIR MEM CLK
3 PAIR MEM CLK
AM2/AM2g2 CPU
AM2 SOCKET
C C
B B
3 PAIR MEM CLK
3 PAIR MEM CLK
AMD NB
RS780
PCIE GFX SLOT 1 - 16 LANES
PCIE GPP SLOT 1 - 1 LANE
PCIE GPP SLOT 2 - 4 LANES
PCIE GFX SLOT 1 - 8 LANES
PCIE GBE
25MHZ OSC INPUT
25MHz
SATA
1 PAIR CPU CLK
200MHZ
HT REFCLK
100MHz DIFF
EXTERNAL
CLK GEN.
NB-OSCIN
14.318MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
NB GFX PCIE CLK
100MHZ
PCIE GFX CLK
100MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
PCIE GFX CLK
100MHZ
PCIE GPP CLK
100MHZ
USB CLK
48MHZ
CPU_HT_CLK
NB_HT_CLK
25M_48M_66M_OSC
AMD SB
SB700
(SB710,SB750)
NB_DISP_CLK
GPP_CLK3
PCIE_RCLK/
NB_LNK_CLK
SLT_GFX_CLK
GPP_CLK0
GPP_CLK1
GPP_CLK2
USB_CLK
SB_BITCLK
48MHZ
PCI CLK0
33MHZ
PCI CLK1
33MHZ
PCI CLK2
33MHZ
LPC_CLK0
33MHZ
LPC CLK1
33MHZ
PCI CLK3
33MHZ
PCI CLK4
33MHZ
25MHz
PCI SLOT 0
PCI SLOT 1
TPM
LPC BIOS
TPM (BCM5755/5761)
SUPER IO
IT8716F
HD AUDIO CON
14.31818MHz
SIO CLK
48MHZ
32.768KHz
External clock mode
A
Title
Size Document Number Rev
Custom
Date: Sheet of
5
4
3
2
CLOCK DISTRIBUTION
A78DG-A2T
4 48Friday, May 29, 2009
1
6.0
5
A
4
3
2
1
HyperTransport
D D
HTCPU_UPCLK115
HTCPU_UPCLK1_15
HTCPU_UPCLK015
HTCPU_UPCLK0_15
HTCPU_UPCNTL115
HTCPU_UPCNTL1_15
HTCPU_UPCNTL15
C C
B B
HTCPU_UP[15..0]15
HTCPU_UP_[15..0]15
HTCPU_UPCLK1
HTCPU_UPCLK1_
HTCPU_UPCLK0
HTCPU_UPCLK0_
HTCPU_UPCNTL1
HTCPU_UPCNTL1_
HTCPU_UPCNTL
HTCPU_UPCNTL_
HTCPU_UP15
HTCPU_UP_15
HTCPU_UP14
HTCPU_UP_14
HTCPU_UP13
HTCPU_UP_13
HTCPU_UP12
HTCPU_UP_12
HTCPU_UP11
HTCPU_UP_11
HTCPU_UP10
HTCPU_UP_10
HTCPU_UP9
HTCPU_UP_9
HTCPU_UP8
HTCPU_UP_8
HTCPU_UP7
HTCPU_UP_7
HTCPU_UP6
HTCPU_UP_6
HTCPU_UP5
HTCPU_UP_5
HTCPU_UP4
HTCPU_UP_4
HTCPU_UP3
HTCPU_UP_3
HTCPU_UP2
HTCPU_UP_2
HTCPU_UP1
HTCPU_UP_1
HTCPU_UP0
HTCPU_UP_0
HTCPU_UP[15..0]
HTCPU_UP_[15..0]
CPU1A
N6
L0_CLKIN_H1
P6
L0_CLKIN_L1
N3
L0_CLKIN_H0
N2
L0_CLKIN_L0
V4
L0_CTLIN_H1
V5
L0_CTLIN_L1
U1
L0_CTLIN_H0
V1
L0_CTLIN_L0
U6
L0_CADIN_H15
V6
L0_CADIN_L15
T4
L0_CADIN_H14
T5
L0_CADIN_L14
R6
L0_CADIN_H13
T6
L0_CADIN_L13
P4
L0_CADIN_H12
P5
L0_CADIN_L12
M4
L0_CADIN_H11
M5
L0_CADIN_L11
L6
L0_CADIN_H10
M6
L0_CADIN_L10
K4
L0_CADIN_H9
K5
L0_CADIN_L9
J6
L0_CADIN_H8
K6
L0_CADIN_L8
U3
L0_CADIN_H7
U2
L0_CADIN_L7
R1
L0_CADIN_H6
T1
L0_CADIN_L6
R3
L0_CADIN_H5
R2
L0_CADIN_L5
N1
L0_CADIN_H4
P1
L0_CADIN_L4
L1
L0_CADIN_H3
M1
L0_CADIN_L3
L3
L0_CADIN_H2
L2
L0_CADIN_L2
J1
L0_CADIN_H1
K1
L0_CADIN_L1
J3
L0_CADIN_H0
J2
L0_CADIN_L0
SOCKET_M2 940 SMD
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
HT LINK
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
HTCPU_DWNCLK1
AD5
HTCPU_DWNCLK1_
AD4
HTCPU_DWNCLK0
AD1
HTCPU_DWNCLK0_
AC1
HTCPU_DWNCNTL1
Y6
HTCPU_DWNCNTL1_
W6
HTCPU_DWNCNTL
W2
HTCPU_DWNCNTL_
W3
HTCPU_DWN15
Y5
HTCPU_DWN_15
Y4
HTCPU_DWN14
AB6
HTCPU_DWN_14
AA6
HTCPU_DWN13
AB5
HTCPU_DWN_13
AB4
HTCPU_DWN12
AD6
HTCPU_DWN_12
AC6
HTCPU_DWN11
AF6
HTCPU_DWN_11
AE6
HTCPU_DWN10
AF5
HTCPU_DWN_10
AF4
HTCPU_DWN9
AH6
HTCPU_DWN_9
AG6
HTCPU_DWN8
AH5
HTCPU_DWN_8
AH4
HTCPU_DWN7
Y1
HTCPU_DWN_7
W1
HTCPU_DWN6
AA2
HTCPU_DWN_6
AA3
HTCPU_DWN5
AB1
HTCPU_DWN_5
AA1
HTCPU_DWN4
AC2
HTCPU_DWN_4
AC3
HTCPU_DWN3
AE2
HTCPU_DWN_3
AE3
HTCPU_DWN2
AF1
HTCPU_DWN_2
AE1
HTCPU_DWN1
AG2
HTCPU_DWN_1
AG3
HTCPU_DWN0
AH1
HTCPU_DWN_0
AG1
HTCPU_DWN[15..0]
HTCPU_DWN_[15..0]
HTCPU_DWNCLK115
HTCPU_DWNCLK1_15
HTCPU_DWNCLK015
HTCPU_DWNCLK0_15
HTCPU_DWNCNTL115
HTCPU_DWNCNTL1_15
HTCPU_DWNCNTL15
HTCPU_DWNCNTL_15HTCPU_UPCNTL_15
HTCPU_DWN[15..0] 15
HTCPU_DWN_[15..0] 15
A
Title
Size Document Number Rev
B
Date: Sheet of
5
4
3
2
K8 CPU HT
A78DG-A2T
1
6 48Friday, May 29, 2009
6.0
A
LAYOUT: PLACE 169 OHM WITHIN 600mils OF CPU
AND TRACE TO AC CAPS LESS THAN 1250mil
10UF 10V 0805 Y5V
D D
ROUTE AS DIF 5/5/5/20
LAYOUT: PLACE 169 OHM WITHIN 600mils OF CPU
AND TRACE TO AC CAPS LESS THAN 1250mil
CPU_CORE_FB
CPU_CORE_FB_
C1
1 2
CLOSE TO CPU
C7
0.1UF 16V Y5V 0402 /NI
1 2
Q1
AZ1117H-ADJ SOT-223
CPU_PRESENT#22
C C
+1.8V_SUS
綼
1 2
12
B B
LDT_RST#17,21
LDT_STOP#17,21
CPU PIN F12
R11
150 1% 0402
CPU_M_VREFF
12
R19
150 1% 0402
+1.8V_SUS
1 2
3 4
5 6
C8
1UF 10V Y5V
RN3
680 8P4R 0402
7 8
Vout=Vref (1.25V) X ( 1+R2/R1 )
=2.5V
+5V
R1
I
O
A
R2
CPU_CLK20
CPU_CLK_20
CPU_CLK
AOD Extreme
CPU_TDI42
CPU_TRST#42
CPU_TCK42
CPU_TMS42
CPU_DBREQ#42
02/18 >10mils
ROUTE AS DIF 5/5/5/20
5
R1
49.9 1% 0402
R2
49.9 1% 0402
CT1
3900P 50V X7R 0402
3900P 50V X7R 0402
HTCPU_RST_1
HTCPU_STOP_
HTCPU_PWRGD
4
綼
C5
C6
+1.8V_SUS
+1.8V_SUS
CPU_CORE_FB43
CPU_CORE_FB_43
+1.8V_SUS
+
3
CPU_VDDA
CT1
100UF 16V 5X11 2mm
12
C2
1UF 16V 0805 Y5V
C2
綼
CPU PIN C10&D11
R1&R2
12
R3
169 1% 0402
CPU
HTCPU_PWRGD
HTCPU_STOP_CPU_CLK*
HTCPU_RST_1
CPU_M_VREFF
1 2
12
R6 1K 0402
1 2
R7 300 0402
1 2
R8 300 0402
1 2
R10 1K 0402
CPU_TDI CPU_TDOCPU_TDO
CPU_TRST#
CPU_TCK
CPU_TMS
CPU_CORE_FB
CPU_CORE_FB-
綼
R13 39.2 1% 0402
1 2
R15 39.2 1% 0402
1 2
R16 510 0402
1 2
R18 510 0402
1 2
R20 300 0402
1 2
R21 300 0402
1 2
CPU1D
C10
VDDA_1
D10
VDDA_2
A8
B8
C9
D8
C7
AL3
AL6
AK6
AK4
AL4
AL10
AJ10
AH10
AL9
A5
G2
G1
E12
F12
AH11
AJ11
A10
B10
F10
E9
AJ7
F6
D6
E7
F8
C5
AH9
E5
AJ5
AH7
AJ6 D4
AD25
AE24
AE25
AJ18
AJ20
AK3
C18
C20
SOCKET_M2 940 SMD
MISC.
CLKIN_H
CLKIN_L
PWROK
LDTSTOP_L
RESET_L
CPU_PRESENT_L
SIC
SID
SA0
ALERT_L
TDI
TRST_L
TCK
TMS
DBREQ_L
VDD_FB_H
VDD_FB_L
VTT_SENSE
M_VREF
M_ZN
M_ZP
TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9
TEST17
TEST16
TEST15
TEST14
TEST12
TEST7
TEST6
TEST3
TEST2 TEST8
RSVD1
RSVD2
RSVD3
RSVD4
INT. MISC.
RSVD5
RSVD6
RSVD9
RSVD10
PLATFORM_TYPE
THERMTRIP_L
VDDNB_FB_H
VDDNB_FB_L
KEY/VSS1
KEY/VSS2
CORE_TYPE
VID5
VID4
SVC/VID3
SVD/VID2
PVIEN/VID1
VID0
THERMDC
THERMDA
PROCHOT_L
TDO
DBRDY
VDDIO_FB_H
VDDIO_FB_L
PSI_L
HTREF1
HTREF0
TEST29_H
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
CPU_THERMTRIP
+1.8V_SUS
H22
AE9
F2
G5
D2
D1
C1
E3
E2
E1
AG9
AG8
AK7
AL7
AK10
B6
AK11
AL11
G4
G3
F1
V8
V7
C11
D11
AK8
AH8
AJ9
AL8
AJ8
J10
H9
AK9
AK5
G7
L30
L31
V29
W30
F3
G24
G25
H25
L25
L26
R4
330 0402
CPU_DBRDYCPU_DBRDYCPU_DBREQ#
R12 44.2 1% 0402
R14 44.2 1% 0402
FBCLKOUT
FBCLKOUT*
R17 80.6 1% 0402
RN2
330 8P4R 0402
2
+1.8V_SUS
R5
330 0402
VID3
VID2
VID1
CPU_THERMTRIPCPU_THERMTRIP
12
12
78
56
34
12
R43
10K 0402
G
S
Q15
FDV301N SOT23
1 2
3 4
5 6
+1.2V_HT
12
+1.8V_SUS
D
RN1
330 8P4R 0402
7 8
1
CPU_THERMTRIP#22
CPU_CORE_TYPE 43
K8_VID543
K8_VID443
K8_VID343
K8_VID243
K8_VID143
K8_VID043
CPU_THERMDC34,37
CPU_THERMDA34
CPU_PROCHOT# 21
VDDNB_FB_H 43
VDDNB_FB_L 43
8/5/8/20
LAYOUT: ROUTE 80 OHM DIFF IMPEDENCE
LAYOUT: PLACE WITHIN 1 INCH OF CPU
CPU_TDO42
CPU_DBRDY 42
AOD Extreme
+1.8V
+3.3V_DUAL
R23
10K 0402 /NI
IMC_CRST_L22
E
R22
10K 0402
B
Q2
2N3904 SOT23
C
5
+1.8V
R299
10K 0402 /NI
HTCPU_RST_1
V0.51 modify 1, Pin AJ9 (TEST22) add 300 0402 pull down
2, Pin A5 (DBREQ_L) add 300 0402 pull to +1.8V_SUS
+1.8V_SUS
R44
10K 0402
Q16
G
LDT_PG21
HTCPU_PWRGD
S
D
FDV301N SOT23
4
PWM_PWROK43
3
2
Title
Size Document Number Rev
Custom
Date: Sheet of
CTRL/STRAPS
A78DG-A2T
7 48Friday, May 29, 2009
1
A
6.0
5
A
4
3
2
1
CPU1B
MEM_MA0_CLK_H212,13
MEM_MA0_CLK_L212,13
MEM_MA1_CLK_H212,13
MEM_MA1_CLK_L212,13
MEM_MA0_CLK_H012,13
MEM_MA0_CLK_L012,13
D D
C C
B B
MEM_MA1_CLK_H012,13
MEM_MA1_CLK_L012,13
MEM_MA0_CLK_H112,13
MEM_MA0_CLK_L112,13
MEM_MA1_CLK_H112,13
MEM_MA1_CLK_L112,13
MEM_MA0_CS_L112,13
MEM_MA0_CS_L012,13
MEM_MA0_ODT012,13
MEM_MA1_CS_L112,13
MEM_MA1_CS_L012,13
MEM_MA1_ODT012,13
MEM_MA_CAS_L12,13
MEM_MA_WE_L12,13
MEM_MA_RAS_L12,13
MEM_MA_BANK212,13
MEM_MA_BANK112,13
MEM_MA_BANK012,13
MEM_MA_CKE112,13
MEM_MA_CKE012,13
MEM_MA_ADD[15..0]12,13
MEM_MA_DQS_H[8..0]13
MEM_MA_DQS_L[8..0]13
MEM_MA_DM[8..0]13
MEM_MA_ADD[15..0]
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_DQS_H[8..0]
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DQS_L[8..0]
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
MEM_MA_DM[8..0]
AG21
MA_CLK_H7
AG20
MA_CLK_L7
AE20
MA_CLK_H6
AE19
MA_CLK_L6
U27
MA_CLK_H5
U26
MA_CLK_L5
V27
MA_CLK_H4
W27
MA_CLK_L4
W26
MA_CLK_H3
W25
MA_CLK_L3
U24
MA_CLK_H2
V24
MA_CLK_L2
G19
MA_CLK_H1
H19
MA_CLK_L1
G20
MA_CLK_H0
G21
MA_CLK_L0
AC25
MA0_CS_L1
AA24
MA0_CS_L0
AE28
MA0_ODT1
AC28
MA0_ODT0
AD27
MA1_CS_L1
AA25
MA1_CS_L0
AE27
MA1_ODT1
AC27
MA1_ODT0
E20
MA_RESET_L
AB25
MA_CAS_L
AB27
MA_WE_L
AA26
MA_RAS_L
N25
MA_BANK2
Y27
MA_BANK1
AA27
MA_BANK0
L27
MA_CKE1
M25
MA_CKE0
M27
MA_ADD15
N24
MA_ADD14
AC26
MA_ADD13
N26
MA_ADD12
P25
MA_ADD11
Y25
MA_ADD10
N27
MA_ADD9
R24
MA_ADD8
P27
MA_ADD7
R25
MA_ADD6
R26
MA_ADD5
R27
MA_ADD4
T25
MA_ADD3
U25
MA_ADD2
T27
MA_ADD1
W24
MA_ADD0
AD15
MA_DQS_H7
AE15
MA_DQS_L7
AG18
MA_DQS_H6
AG19
MA_DQS_L6
AG24
MA_DQS_H5
AG25
MA_DQS_L5
AG27
MA_DQS_H4
AG28
MA_DQS_L4
D29
MA_DQS_H3
C29
MA_DQS_L3
C25
MA_DQS_H2
D25
MA_DQS_L2
E19
MA_DQS_H1
F19
MA_DQS_L1
F15
MA_DQS_H0
G15
MA_DQS_L0
AF15
MA_DM7
AF19
MA_DM6
AJ25
MA_DM5
AH29
MA_DM4
B29
MA_DM3
E24
MA_DM2
E18
MA_DM1
H15
MA_DM0
SOCKET_M2 940 SMD
MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MEM CHA
MA_DATA12
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0
MA_DQS_H8
MA_DQS_L8
MA_DM8
MA_CHECK7
MA_CHECK6
MA_CHECK5
MA_CHECK4
MA_CHECK3
MA_CHECK2
MA_CHECK1
MA_CHECK0
MEM_MA_DATA[0..63]
MEM_MA_DATA63
AE14
MEM_MA_DATA62
AG14
MEM_MA_DATA61
AG16
MEM_MA_DATA60
AD17
MEM_MA_DATA59
AD13
MEM_MA_DATA58
AE13
MEM_MA_DATA57
AG15
MEM_MA_DATA56
AE16
MEM_MA_DATA55
AG17
MEM_MA_DATA54
AE18
MEM_MA_DATA53
AD21
MEM_MA_DATA52
AG22
MEM_MA_DATA51
AE17
MEM_MA_DATA50
AF17
MEM_MA_DATA49
AF21
MEM_MA_DATA48
AE21
MEM_MA_DATA47
AF23
MEM_MA_DATA46
AE23
MEM_MA_DATA45
AJ26
MEM_MA_DATA44
AG26
MEM_MA_DATA43
AE22
MEM_MA_DATA42
AG23
MEM_MA_DATA41
AH25
MEM_MA_DATA40
AF25
MEM_MA_DATA39
AJ28
MEM_MA_DATA38
AJ29
MEM_MA_DATA37
AF29
MEM_MA_DATA36
AE26
MEM_MA_DATA35
AJ27
MEM_MA_DATA34
AH27
MEM_MA_DATA33
AG29
MEM_MA_DATA32
AF27
MEM_MA_DATA31
E29
MEM_MA_DATA30
E28
MEM_MA_DATA29
D27
MEM_MA_DATA28
C27
MEM_MA_DATA27
G26
MEM_MA_DATA26
F27
MEM_MA_DATA25
C28
MEM_MA_DATA24
E27
MEM_MA_DATA23
F25
MEM_MA_DATA22
E25
MEM_MA_DATA21
E23
MEM_MA_DATA20
D23
MEM_MA_DATA19
E26
MEM_MA_DATA18
C26
MEM_MA_DATA17
G23
MEM_MA_DATA16
F23
MEM_MA_DATA15
E22
MEM_MA_DATA14
E21
MEM_MA_DATA13
F17
MEM_MA_DATA12
G17
MEM_MA_DATA11
G22
MEM_MA_DATA10
F21
MEM_MA_DATA9
G18
MEM_MA_DATA8
E17
MEM_MA_DATA7
G16
MEM_MA_DATA6
E15
MEM_MA_DATA5
G13
MEM_MA_DATA4
H13
MEM_MA_DATA3
H17
MEM_MA_DATA2
E16
MEM_MA_DATA1
E14
MEM_MA_DATA0
G14
MEM_MA_DQS_H8
J28
MEM_MA_DQS_L8
J27
MEM_MA_DM8
J25
MEM_MA_CHECK[7..0]
MEM_MA_CHECK7
K25
MEM_MA_CHECK6
J26
MEM_MA_CHECK5
G28
MEM_MA_CHECK4
G27
MEM_MA_CHECK3
L24
MEM_MA_CHECK2
K27
MEM_MA_CHECK1
H29
MEM_MA_CHECK0
H27
MEM_MA_DATA[0..63]13
MEM_MA_CHECK[7..0] 13
A
Title
Size Document Number Rev
Custom
Date: Sheet of
5
4
3
2
K8 CPU MEMORY-1
A78DG-A2T
8 48Friday, May 29, 2009
1
6.0
5
A
4
3
2
1
CPU1C
MEM_MB0_CLK_H212,14
MEM_MB0_CLK_L212,14
MEM_MB1_CLK_H212,14
MEM_MB1_CLK_L212,14
MEM_MB0_CLK_H012,14
MEM_MB0_CLK_L012,14
D D
C C
B B
MEM_MB1_CLK_H012,14
MEM_MB1_CLK_L012,14
MEM_MB0_CLK_H112,14
MEM_MB0_CLK_L112,14
MEM_MB1_CLK_H112,14
MEM_MB1_CLK_L112,14
MEM_MB0_CS_L112,14
MEM_MB0_CS_L012,14
MEM_MB0_ODT012,14
MEM_MB1_CS_L112,14
MEM_MB1_CS_L012,14
MEM_MB1_ODT012,14
MEM_MB_CAS_L12,14
MEM_MB_WE_L12,14
MEM_MB_RAS_L12,14
MEM_MB_BANK212,14
MEM_MB_BANK112,14
MEM_MB_BANK012,14
MEM_MB_CKE112,14
MEM_MB_CKE012,14
MEM_MB_ADD[15..0]12,14
MEM_MB_DQS_H[8..0]14
MEM_MB_DQS_L[8..0]14
MEM_MB_DM[8..0]14
MEM_MB_ADD[15..0]
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_DQS_H[8..0]
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DQS_L[8..0]
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
MEM_MB_DM[8..0]
AJ19
MB_CLK_H7
AK19
MB_CLK_L7
AL19
MB_CLK_H6
AL18
MB_CLK_L6
U31
MB_CLK_H5
U30
MB_CLK_L5
W29
MB_CLK_H4
W28
MB_CLK_L4
Y31
MB_CLK_H3
Y30
MB_CLK_L3
V31
MB_CLK_H2
W31
MB_CLK_L2
A18
MB_CLK_H1
A19
MB_CLK_L1
C19
MB_CLK_H0
D19
MB_CLK_L0
AE30
MB0_CS_L1
AC31
MB0_CS_L0
AF31
MB0_ODT1
AD29
MB0_ODT0
AE29
MB1_CS_L1
AB31
MB1_CS_L0
AG31
MB1_ODT1
AD31
MB1_ODT0
B19
MB_RESET_L
AC29
MB_CAS_L
AC30
MB_WE_L
AB29
MB_RAS_L
N31
MB_BANK2
AA31
MB_BANK1
AA28
MB_BANK0
M31
MB_CKE1
M29
MB_CKE0
N28
MB_ADD15
N29
MB_ADD14
AE31
MB_ADD13
N30
MB_ADD12
P29
MB_ADD11
AA29
MB_ADD10
P31
MB_ADD9
R29
MB_ADD8
R28
MB_ADD7
R31
MB_ADD6
R30
MB_ADD5
T31
MB_ADD4
T29
MB_ADD3
U29
MB_ADD2
U28
MB_ADD1
AA30
MB_ADD0
AK13
MB_DQS_H7
AJ13
MB_DQS_L7
AK17
MB_DQS_H6
AJ17
MB_DQS_L6
AK23
MB_DQS_H5
AL23
MB_DQS_L5
AL28
MB_DQS_H4
AL29
MB_DQS_L4
D31
MB_DQS_H3
C31
MB_DQS_L3
C24
MB_DQS_H2
C23
MB_DQS_L2
D17
MB_DQS_H1
C17
MB_DQS_L1
C14
MB_DQS_H0
C13
MB_DQS_L0
AJ14
MB_DM7
AH17
MB_DM6
AJ23
MB_DM5
AK29
MB_DM4
C30
MB_DM3
A23
MB_DM2
B17
MB_DM1
B13
MB_DM0
SOCKET_M2 940 SMD
MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MEM CHB
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0
MB_DQS_H8
MB_DQS_L8
MB_DM8
MB_CHECK7
MB_CHECK6
MB_CHECK5
MB_CHECK4
MB_CHECK3
MB_CHECK2
MB_CHECK1
MB_CHECK0
AH13
AL13
AL15
AJ15
AF13
AG13
AL14
AK15
AL16
AL17
AK21
AL21
AH15
AJ16
AH19
AL20
AJ22
AL22
AL24
AK25
AJ21
AH21
AH23
AJ24
AL27
AK27
AH31
AG30
AL25
AL26
AJ30
AJ31
E31
E30
B27
A27
F29
F31
A29
A28
A25
A24
C22
D21
A26
B25
B23
A22
B21
A20
C16
D15
C21
A21
A17
A16
B15
A14
E13
F13
C15
A15
A13
D13
J31
J30
J29
K29
K31
G30
G29
L29
L28
H31
G31
MEM_MB_DATA[0..63]
MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0
MEM_MB_DQS_H8
MEM_MB_DQS_L8
MEM_MB_DM8
MEM_MB_CHECK7
MEM_MB_CHECK6
MEM_MB_CHECK5
MEM_MB_CHECK4
MEM_MB_CHECK3
MEM_MB_CHECK2
MEM_MB_CHECK1
MEM_MB_CHECK0
MEM_MB_CHECK[7..0]
MEM_MB_DATA[0..63]14
MEM_MB_CHECK[7..0] 14
A
Title
Size Document Number Rev
Custom
Date: Sheet of
5
4
3
2
K8 CPU MEMORY-2
A78DG-A2T
9 48Friday, May 29, 2009
1
6.0
5
A
4
3
2
1
CPU1E
+V_CPU +V_CPU CPU_VDDNB
B3
VDD_1
C2
VDD_2
C4
VDD_3
D3
VDD_4
D5
VDD_5
D D
C C
B B
E4
VDD_6
E6
VDD_7
F5
VDD_8
F7
VDD_9
G6
VDD_10
G8
VDD_11
H7
VDD_12
H11
VDD_13
H23
VDD_14
J8
VDD_15
J12
VDD_16
J14
VDD_17
J16
VDD_18
J18
VDD_19
J20
VDD_20
J22
VDD_21
J24
VDD_22
K7
VDD_23
K9
VDD_24
K11
VDD_25
K13
VDD_26
K15
VDD_27
K17
VDD_28
K19
VDD_29
K21
VDD_30
K23
VDD_31
L4
VDD_32
L5
VDD_33
L8
VDD_34
L10
VDD_35
L12
VDD_36
L14
VDD_37
L16
VDD_38
L18
VDD_39
L20
VDD_40
L22
VDD_41
M2
VDD_42
M3
VDD_43
M7
VDD_44
M9
VDD_45
M11
VDD_46
M13
VDD_47
M15
VDD_48
M17
VDD_49
M19
VDD_50
M21
VDD_51
M23
VDD_52
N8
VDD_53
N10
VDD_54
N12
VDD_55
N14
VDD_56
N16
VDD_57
N18
VDD_58
N20
VDD_59
N22
VDD_60
P7
VDD_61
P9
VDD_62
P11
VDD_63
P13
VDD_64
P15
VDD_65
P17
VDD_66
P19
VDD_67
P21
VDD_68
P23
VDD_69
R4
VDD_70
R5
VDD_71
R8
VDD_72
R10
VDD_73
R12
VDD_74
R14
VDD_75
R16
VDD_76
R18
VDD_77
R20
VDD_78
R22
VDD_79
T2
VDD_80
T3
VDD_81
T7
VDD_82
T9
VDD_83
T11
VDD_84
T13
VDD_85
SOCKET_M2 940 SMD
POWER/GND1
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
A3
A7
A9
A11
B4
B9
B11
B14
B16
B18
B20
B22
B24
B26
B28
B30
C3
D14
D16
D18
D20
D22
D24
D26
D28
D30
E11
F4
F14
F16
F18
F20
F22
F24
F26
F28
F30
G9
G11
H8
H10
H12
H14
H16
H18
H24
H26
H28
H30
J4
J5
J7
J9
J11
J13
J15
J17
J19
J21
J23
K2
K3
K8
K10
K12
K14
K16
K18
K20
K22
K24
K26
K28
K30
L7
L9
L11
L13
L15
L17
L19
L21
L23
M8
M10
CPU1F
T15
VDD_86
T17
VDD_87
T19
VDD_88
T21
VDD_89
T23
VDD_90
U8
VDD_91
U10
VDD_92
U12
VDD_93
U14
VDD_94
U16
VDD_95
U18
VDD_96
U20
VDD_97
U22
VDD_98
V9
VDD_99
V11
VDD_100
V13
VDD_101
V15
VDD_102
V17
VDD_103
V19
VDD_104
V21
VDD_105
V23
VDD_106
W4
VDD_107
W5
VDD_108
W8
VDD_109
W10
VDD_110
W12
VDD_111
W14
VDD_112
W16
VDD_113
W18
VDD_114
W20
VDD_115
W22
VDD_116
Y2
VDD_117
Y3
VDD_118
Y7
VDD_119
Y9
VDD_120
Y11
VDD_121
Y13
VDD_122
Y15
VDD_123
Y17
VDD_124
Y19
VDD_125
Y21
VDD_126
Y23
VDD_127
AA8
VDD_128
AA10
VDD_129
AA12
VDD_130
AA14
VDD_131
AA16
VDD_132
AA18
VDD_133
AA20
VDD_134
AA22
VDD_135
AB7
VDD_136
AB9
VDD_137
AB11
VDD_138
AB13
VDD_139
AB15
VDD_140
AB17
VDD_141
AB19
VDD_142
AB21
VDD_143
AB23
VDD_144
AC4
VDD_145
AC5
VDD_146
AC8
VDD_147
AC10
VDD_148
AC12
VDD_149
AC14
VDD_150
AC16
VDD_151
AC18
VDD_152
AC20
VDD_153
AC22
VDD_154
AD2
VDD_155
AD3
VDD_156
AD7
VDD_157
AD9
VDD_158
AD11
VDD_159
AD23
VDD_160
AE10
VDD_161
AE12
VDD_162
AF7
VDD_163
AF9
VDD_164
AF11
VDD_165
AG4
VDD_166
AG5
VDD_167
AG7
VDD_168
AH2
VDD_169
AH3
VDD_170
SOCKET_M2 940 SMD
M12
VSS_86
M14
VSS_87
M16
VSS_88
M18
VSS_89
M20
VSS_90
M22
VSS_91
N4
VSS_92
N5
VSS_93
N7
VSS_94
N9
VSS_95
N11
VSS_96
N13
VSS_97
N15
VSS_98
N17
VSS_99
N19
VSS_100
N21
VSS_101
N23
VSS_102
P2
VSS_103
P3
VSS_104
P8
VSS_105
P10
VSS_106
P12
VSS_107
P14
VSS_108
P16
VSS_109
P18
VSS_110
P20
VSS_111
P22
VSS_112
R7
VSS_113
R9
VSS_114
R11
VSS_115
R13
VSS_116
R15
VSS_117
R17
VSS_118
R19
VSS_119
R21
VSS_120
R23
VSS_121
T8
VSS_122
T10
VSS_123
T12
VSS_124
T14
VSS_125
T16
VSS_126
T18
VSS_127
T20
VSS_128
T22
VSS_129
U4
VSS_130
U5
VSS_131
U7
VSS_132
U9
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
U11
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W7
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
Y14
Y16
Y18
Y20
Y22
AA4
AA5
AA7
AA9
POWER/GND2
CPU1G
A4
VDDNB_1
A6
VDDNB_2
B5
VDDNB_3
B7
VDDNB_4
C6
VDDNB_5
C8
VDDNB_6
D7
VDDNB_7
D9
VDDNB_8
E8
VDDNB_9
E10
VDDNB_10
F9
VDDNB_11
F11
VDDNB_12
G10
VDDNB_13
G12
VDDNB_14
H3
NC1
H4
NC2
H20
NC3
H21
NC4
AD18
NC6
AD19
NC7
AE7
NC8
AE8
NC9
SOCKET_M2 940 SMD
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
POWER/GND3
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
+1.2V_HT
C9
10UF 10V 0805 Y5V
1 2
AA11
AA13
AA15
AA17
AA19
AA21
AA23
+0.9V_SUS
AB2
AB3
AB8
AB10
AB12
AB14
+1.8V_SUS
AB16
AB18
AB20
AB22
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AD8
AD10
AD12
AD14
AD16
AD20
AD22
AD24
AE4
AE5
AE11
AF2
AF3
AF8
AF10
AF12
AF14
AF16
C10
1UF 16V 0805 Y5V
1 2
+1.2V_HT
+1.2V_HT_CPU
12
C11
1UF 16V 0805 Y5V
CPU1H
AJ1
VLDT_A_1
AJ2
VLDT_A_2
AJ3
VLDT_A_3
AJ4
VLDT_A_4
A12
VTT_1
B12
VTT_2
C12
VTT_3
D12
VTT_4
M24
VDDIO_1
M26
VDDIO_2
M28
VDDIO_3
M30
VDDIO_4
P24
VDDIO_5
P26
VDDIO_6
P28
VDDIO_7
P30
VDDIO_8
T24
VDDIO_9
T26
VDDIO_10
T28
VDDIO_11
T30
VDDIO_12
V25
VDDIO_13
V26
VDDIO_14
V28
VDDIO_15
V30
VDDIO_16
Y24
VDDIO_17
Y26
VDDIO_18
Y28
VDDIO_19
Y29
VDDIO_20
AB24
VDDIO_21
AB26
VDDIO_22
AB28
VDDIO_23
AB30
VDDIO_24
AC24
VDDIO_25
AD26
VDDIO_26
AD28
VDDIO_27
AD30
VDDIO_28
AF30
VDDIO_29
SOCKET_M2 940 SMD
12
C12
10UF 10V 0805 Y5V
+1.2V_HT_CPU
H1
VLDT_B_1
H2
VLDT_B_2
H5
VLDT_B_3
H6
VLDT_B_4
AG12
VTT_5
AH12
VTT_6
AJ12
VTT_7
AK12
VTT_8
AL12
VTT_9
AF18
VSS_215
AF20
VSS_216
AF22
VSS_217
AF24
VSS_218
AF26
VSS_219
AF28
VSS_220
AG10
VSS_221
AG11
VSS_222
AH14
VSS_223
AH16
VSS_224
AH18
VSS_225
AH20
VSS_226
AH22
VSS_227
AH24
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
AH26
AH28
AH30
AK2
AK14
AK16
AK18
AK20
AK22
AK24
AK26
AK28
AK30
AL5
POWER/GND4
+0.9V_SUS
A
Title
Size Document Number Rev
Custom
Date: Sheet of
5
4
3
2
POWER/GND
A78DG-A2T
1
10 48Friday, May 29, 2009
6.0
5
A
02/27 BC249=>NI
BC
筿甧簿 タ
02/27 BC250=>NI 02/27 BC251=>NI 02/27 BC252=>NI 02/27 BC253=>NI
4
рB
奔э
02/27 BC254=>NI
3
02/27 BC262=>NI
2
1
D D
+1.8V_SUS
PLACE BOTTOM SIDE
12
C13
1UF 16V 0805 Y5V /NI
+1.8V_SUS
DECOUPLING BETWEEN PROCESSOR AND DIMMS
12
C20
1UF 16V 0805 Y5V /NI
12
C14
10UF 10V 0805 Y5V
C25
0.1UF 16V Y5V 0402
12
C15
1UF 16V 0805 Y5V /NI
C22
0.1UF 16V Y5V 0402
12
C16
10UF 10V 0805 Y5V /NI
12
C17
1UF 16V 0805 Y5V /NI
12
C18
10UF 10V 0805 Y5V /NI
12
C19
1UF 16V 0805 Y5V /NI
C C
+0.9V_SUS
12
C26
1UF 10V Y5V
+V_CPU
PLACE BOTTOM SIDE DECOUPLING
12
B B
C35
10UF 10V 0805 Y5V
+V_CPU
5
12
C27
0.1UF 16V Y5V 0402
12
C38
10UF 10V 0805 Y5V
02/27 BC47=>NI 02/27 BC50=>NI
12
C28
1000P 50V X7R 0402
FOR EMI FOR EMI
12
C51
10UF 10V 0805 Y5V
4
+0.9V_SUS
12
C29
10UF 10V 0805 Y5V
+V_CPU
PLACE LEFT SIDE OF CPU SOCKETPLACE RIGHT SIDE OF CPU SOCKET
12
C30
1UF 10V Y5V
12
C256
10UF 10V 0805 Y5V
12
C31
0.1UF 16V Y5V 0402
CPU_VDDNB
3
12
C36
10UF 10V 0805 Y5V
12
C32
1000P 50V X7R 0402
12
C137
10UF 10V 0805 Y5V
Title
Size Document Number Rev
Custom
Date: Sheet of
2
DECOUPLING
A78DG-A2T
1
11 48Friday, May 29, 2009
6.0
A
5
A
4
3
2
1
MEM_MA0_CLK_H28,13
C53
D D
C C
MEM_MA0_CLK_L28,13
MEM_MA0_CLK_H18,13
MEM_MA0_CLK_L18,13
MEM_MA0_CLK_H08,13
MEM_MA0_CLK_L08,13
MEM_MB0_CLK_H29,14
MEM_MB0_CLK_L29,14
MEM_MB0_CLK_H19,14
MEM_MB0_CLK_L19,14
MEM_MB0_CLK_H09,14
MEM_MB0_CLK_L09,14
LAYOUT: FRONT SIDE PLACE ALTERNATING GND AND 1.8V
ALONG 0.9V VTT FILL
1.5P 50V NPO 0402
C55
1.5P 50V NPO 0402
C57
1.5P 50V NPO 0402
C59
1.5P 50V NPO 0402
C61
1.5P 50V NPO 0402
C63
1.5P 50V NPO 0402
MEM_MA1_CLK_H28,13
C54
MEM_MA1_CLK_L28,13
MEM_MA1_CLK_H18,13
MEM_MA1_CLK_L18,13
MEM_MA1_CLK_H08,13
MEM_MA1_CLK_L08,13
MEM_MB1_CLK_H29,14
MEM_MB1_CLK_L29,14
MEM_MB1_CLK_H19,14
MEM_MB1_CLK_L19,14
MEM_MB1_CLK_H09,14
MEM_MB1_CLK_L09,14
1.5P 50V NPO 0402
C56
1.5P 50V NPO 0402
C58
1.5P 50V NPO 0402
C60
1.5P 50V NPO 0402
C62
1.5P 50V NPO 0402
C64
1.5P 50V NPO 0402
B B
+0.9V_SUS +1.8V_SUS
C83 0.1UF 16V Y5V 0402
1 2
C89 0.1UF 16V Y5V 0402
1 2
C95 0.1UF 16V Y5V 0402
1 2
C101 0.1UF 16V Y5V 0402
1 2
C107 0.1UF 16V Y5V 0402
1 2
C113 0.1UF 16V Y5V 0402
1 2
C118 0.1UF 16V Y5V 0402
1 2
C121 0.1UF 16V Y5V 0402
1 2
C122 0.1UF 16V Y5V 0402
1 2
C123 0.1UF 16V Y5V 0402
1 2
C124 100P 50V NPO 0402
C468 1UF 10V Y5V
C469 10UF 10V 0805 Y5V
12
12
12
5
FOR EMI
+0.9V_SUS
C84 0.1UF 16V Y5V 0402
1 2
C90 0.1UF 16V Y5V 0402
1 2
C96 0.1UF 16V Y5V 0402
1 2
C102 0.1UF 16V Y5V 0402
1 2
C108 0.1UF 16V Y5V 0402
1 2
4
MEM_MA_ADD[15..0]8,13
MEM_MA_BANK18,13
MEM_MA_BANK28,13
MEM_MA_CAS_L8,13
MEM_MA_WE_L8,13
MEM_MA_RAS_L8,13
MEM_MA_CKE08,13
MEM_MA_CKE18,13
MEM_MA0_CS_L08,13
MEM_MA0_CS_L18,13
MEM_MA1_CS_L08,13
MEM_MA1_CS_L18,13 MEM_MB1_CS_L09,14
MEM_MA0_ODT08,13
MEM_MA1_ODT08,13
MEM_MA_ADD[15..0]
MEM_MA_ADD9
MEM_MA_ADD12
MEM_MA_BANK2
MEM_MA_ADD14
MEM_MA_ADD5
MEM_MB_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MB_RAS_L
MEM_MB1_CS_L0
MEM_MB0_CS_L0
MEM_MB_CAS_L
MEM_MA0_ODT0
MEM_MA1_ODT0
MEM_MA_CAS_L
MEM_MB_WE_L
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD9
MEM_MB_ADD7
MEM_MA_ADD15
MEM_MA_CKE0
MEM_MA_CKE1
MEM_MB_CKE0
MEM_MB0_ODT0
MEM_MB1_ODT0
MEM_MB_ADD13
MEM_MB1_CS_L1
MEM_MB_CKE1
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_BANK2
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15
3
22P 50V NPO 0402C65
22P 50V NPO 0402C67
22P 50V NPO 0402C69
22P 50V NPO 0402C71
22P 50V NPO 0402C73
22P 50V NPO 0402C75
22P 50V NPO 0402C77
22P 50V NPO 0402C79
22P 50V NPO 0402C81
22P 50V NPO 0402C85
22P 50V NPO 0402C87
22P 50V NPO 0402C91
22P 50V NPO 0402C93
22P 50V NPO 0402C97
22P 50V NPO 0402C99
22P 50V NPO 0402C103
22P 50V NPO 0402C105
22P 50V NPO 0402C109
22P 50V NPO 0402C111
22P 50V NPO 0402C114
22P 50V NPO 0402C116
22P 50V NPO 0402C119
MEM_MB_CKE09,14
MEM_MB_CKE19,14
MEM_MB0_CS_L09,14
MEM_MB0_CS_L19,14
MEM_MB1_CS_L19,14
MEM_MB0_ODT09,14
MEM_MB1_ODT09,14
+0.9V_SUS
RN4 47 8P4R 0402
78
56
34
12
RN6 47 8P4R 0402
78
56
34
12
RN8 47 8P4R 0402
78
56
34
12
RN1047 8P4R 0402
78
56
34
12
RN1247 8P4R 0402
78
56
34
12
RN1447 8P4R 0402
78
56
34
12
RN1647 8P4R 0402
78
56
34
12
RN1847 8P4R 0402
78
56
34
12
+1.8V_SUS
MEM_MB_ADD[15..0]9,14
MEM_MB_BANK09,14MEM_MA_BANK08,13
MEM_MB_BANK19,14
MEM_MB_BANK29,14
MEM_MB_CAS_L9,14
MEM_MB_WE_L9,14
MEM_MB_RAS_L9,14
MEM_MB_ADD[15..0]
MEM_MA_WE_L
MEM_MA0_CS_L0
MEM_MA1_CS_L0
MEM_MA_RAS_L
MEM_MA_ADD6
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD11
MEM_MB_ADD8
MEM_MB_ADD6
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD0
MEM_MA_ADD10
MEM_MA_BANK1
MEM_MA_BANK0
MEM_MA0_CS_L1
MEM_MA1_CS_L1
MEM_MB0_CS_L1
MEM_MA_ADD13
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD0
MEM_MB_ADD10
MEM_MB_BANK1
MEM_MB_BANK0
22P 50V NPO 0402C66
22P 50V NPO 0402C68
22P 50V NPO 0402C70
22P 50V NPO 0402C72
22P 50V NPO 0402C74
MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15
Title
Size Document Number Rev
Custom
Date: Sheet of
22P 50V NPO 0402C76
22P 50V NPO 0402C78
22P 50V NPO 0402C80
22P 50V NPO 0402C82
22P 50V NPO 0402C86
22P 50V NPO 0402C88
22P 50V NPO 0402C92
22P 50V NPO 0402C94
22P 50V NPO 0402C98
22P 50V NPO 0402C100
22P 50V NPO 0402C104
22P 50V NPO 0402C106
22P 50V NPO 0402C110
22P 50V NPO 0402C112
22P 50V NPO 0402C115
22P 50V NPO 0402C117
22P 50V NPO 0402C120
VTT TERMINATI
A78DG-A2T
2
+0.9V_SUS
RN5 47 8P4R 0402
78
56
34
12
RN7 47 8P4R 0402
78
56
34
12
RN9 47 8P4R 0402
78
56
34
12
RN1147 8P4R 0402
78
56
34
12
RN1347 8P4R 0402
78
56
34
12
RN1547 8P4R 0402
78
56
34
12
RN1747 8P4R 0402
78
56
34
12
+1.8V_SUS
12 48Friday, May 29, 2009
1
6.0
A
5
A
4
3
2
1
238
VDDSPD
236
DQ63
235
DQ62
230
DQ61
229
DQ60
117
DQ59
116
DQ58
111
DQ57
110
DQ56
227
DQ55
226
DQ54
218
DQ53
217
DQ52
108
DQ51
107
DQ50
99
DQ49
98
DQ48
215
DQ47
214
DQ46
209
DQ45
208
DQ44
96
DQ43
95
DQ42
90
DQ41
89
DQ40
206
DQ39
205
DQ38
200
DQ37
199
DQ36
87
DQ35
86
DQ34
81
DQ33
80
DQ32
159
DQ31
158
DQ30
153
DQ29
152
DQ28
40
DQ27
39
DQ26
34
DQ25
33
DQ24
150
DQ23
149
DQ22
144
DQ21
143
DQ20
31
DQ19
30
DQ18
25
DQ17
24
DQ16
141
DQ15
140
DQ14
132
DQ13
131
DQ12
22
DQ11
21
DQ10
13
DQ9
12
DQ8
129
DQ7
128
DQ6
123
DQ5
122
DQ4
10
DQ3
9
DQ2
4
DQ1
3
DQ0
73
WE_L
1
VREF
102
TEST
195
ODT0
77
ODT1
55
68
PAR_IN
19
NC1
DIMMA1
MEM_MA_DATA[0..63]
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA59
MEM_MA_DATA58
MEM_MA_DATA57
MEM_MA_DATA56
MEM_MA_DATA54
MEM_MA_DATA53
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA49
MEM_MA_DATA48
MEM_MA_DATA47
MEM_MA_DATA46
MEM_MA_DATA45
MEM_MA_DATA44
MEM_MA_DATA43
MEM_MA_DATA42
MEM_MA_DATA41
MEM_MA_DATA40
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA37
MEM_MA_DATA36
MEM_MA_DATA35
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA31
MEM_MA_DATA30
MEM_MA_DATA29
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA26
MEM_MA_DATA25
MEM_MA_DATA24
MEM_MA_DATA23
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA20
MEM_MA_DATA19
MEM_MA_DATA18
MEM_MA_DATA17
MEM_MA_DATA16
MEM_MA_DATA14
MEM_MA_DATA13
MEM_MA_DATA12
MEM_MA_DATA11 MEM_MA_DATA11
MEM_MA_DATA10
MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA7
MEM_MA_DATA6
MEM_MA_DATA5
MEM_MA_DATA4
MEM_MA_DATA3
MEM_MA_DATA2
MEM_MA_DATA1
MEM_MA_WE_L8,12
MEM_M_VREF
MEM_MA0_ODT08,12
12
C125
0.1UF 16V Y5V 0402
PLACE NEAR DIMM SOCKETS
+1.8V_SUS
R24
150 1% 0402
1 2
R25
150 1% 0402
1 2
MEM_M_VREF
12
C127
0.1UF 16V Y5V 0402
MEM_MA_DM[8..0]8
MEM_MA_DQS_H[8..0]8
MEM_MA_DQS_L[8..0]8
SCLK14,20,22,43
SDATA14,20,22,43
MEM_MA_BANK28,12
MEM_MA_BANK18,12
MEM_MA_BANK08,12
MEM_MA_CHECK[7..0]8MEM_MA_CHECK[7..0]8
MEM_MA1_CLK_H08,12
MEM_MA1_CLK_L08,12
MEM_MA1_CLK_H18,12
MEM_MA1_CLK_L18,12
MEM_MA1_CLK_H28,12
MEM_MA1_CLK_L28,12
MEM_MA_CKE18,12
MEM_MA_RAS_L8,12MEM_MA_RAS_L8,12
MEM_MA_CAS_L8,12
MEM_MA1_CS_L08,12
MEM_MA1_CS_L18,12
3
MEM_MA_DM[8..0]
MEM_MA_DM8
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
MEM_MA_DQS_H[8..0]
MEM_MA_DQS_H8
MEM_MA_DQS_L8
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DQS_L[8..0]
+3.3V
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13MEM_MA_DATA15
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5 MEM_MA_DATA7
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_CHECK[7..0]
MEM_MA_CHECK7
MEM_MA_CHECK6
MEM_MA_CHECK5
MEM_MA_CHECK4
MEM_MA_CHECK3
MEM_MA_CHECK2
MEM_MA_CHECK1
MEM_MA_CHECK0
MEM_MA_CKE1
+3.3V +3.3V
DIMMA1
172
178
184
187
189
1975359646769170
VDD1
VDD2
VDD3
VDD4
VDD5
D D
MEM_MA_DM[8..0]8
MEM_MA_DQS_H[8..0]8
C C
MEM_MA_DQS_L[8..0]8
SCLK14,20,22,43
SDATA14,20,22,43
MEM_MA_BANK28,12
MEM_MA_BANK18,12
MEM_MA_BANK08,12
MEM_MA_ADD[15..0]8,12 MEM_MA_ADD[15..0]8,12
B B
MEM_MA0_CLK_H08,12
MEM_MA0_CLK_L08,12
MEM_MA0_CLK_H18,12
MEM_MA0_CLK_L18,12
MEM_MA0_CLK_H28,12
MEM_MA0_CLK_L28,12
MEM_MA_CKE08,12
MEM_MA_CAS_L8,12
MEM_MA0_CS_L08,12
MEM_MA0_CS_L18,12
MEM_MA_DM[8..0]
MEM_MA_DM8
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
MEM_MA_DQS_H[8..0]
MEM_MA_DQS_H8
MEM_MA_DQS_L8
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DQS_L[8..0]
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_CHECK[7..0]
MEM_MA_CHECK7
MEM_MA_CHECK6
MEM_MA_CHECK5
MEM_MA_CHECK4
MEM_MA_CHECK3
MEM_MA_CHECK2
MEM_MA_CHECK1
MEM_MA_CHECK0
MEM_MA_CKE0
164
165
232
233
223
224
211
212
202
203
155
156
146
147
134
135
125
126
46
45
114
113
105
104
93
92
84
83
37
36
28
27
16
15
7
6
101
240
239
120
119
54
190
71
173
174
196
176
57
70
177
179
58
180
60
61
182
63
183
188
168
167
162
161
49
48
43
42
185
186
137
138
220
221
18
52
171
192
74
193
76
DDR2-240 pin-T
DQS17_H
DQS17_L
DQS16_H
DQS16_L
DQS15_H
DQS15_L
DQS14_H
DQS14_L
DQS13_H
DQS13_L
DQS12_H
DQS12_L
DQS11_H
DQS11_L
DQS10_H
DQS10_L
DQS9_H
DQS9_L
DQS8_H
DQS8_L
DQS7_H
DQS7_L
DQS6_H
DQS6_L
DQS5_H
DQS5_L
DQS4_H
DQS4_L
DQS3_H
DQS3_L
DQS2_H
DQS2_L
DQS1_H
DQS1_L
DQS0_H
DQS0_L
SA2
SA1
SA0
SCL
SDA
BA2
BA1
BA0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
CK0_H
CK0_L
CK1_H
CK1_L
CK2_H
CK2_L
RESET_L
CKE0
CKE1
RAS_L
CAS_L
S0_L
S1_L
VDD6
5
175
181
191
194515662727578
VDD7
VDD8
VDD9
VDD10
VDD11
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
ERR_OUT_L
4
DIMMA2
164
DQS17_H
165
DQS17_L
232
DQS16_H
233
DQS16_L
223
DQS15_H
224
DQS15_L
211
DQS14_H
212
DQS14_L
202
DQS13_H
203
DQS13_L
155
DQS12_H
156
DQS12_L
146
DQS11_H
147
DQS11_L
134
DQS10_H
135
DQS10_L
125
DQS9_H
126
DQS9_L
46
DQS8_H
45
DQS8_L
114
DQS7_H
113
DQS7_L
105
DQS6_H
104
DQS6_L
93
DQS5_H
92
DQS5_L
84
DQS4_H
83
DQS4_L
37
DQS3_H
36
DQS3_L
28
DQS2_H
27
DQS2_L
16
DQS1_H
15
DQS1_L
7
DQS0_H
6
DQS0_L
101
SA2
240
SA1
239
SA0
120
SCL
119
SDA
54
BA2
190
BA1
71
BA0
173
A15
174
A14
196
A13
176
A12
57
A11
70
A10
177
A9
179
A8
58
A7
180
A6
60
A5
61
A4
182
A3
63
A2
183
A1
188
A0
168
CB7
167
CB6
162
CB5
161
CB4
49
CB3
48
CB2
43
CB1
42
CB0
185
CK0_H
186
CK0_L
137
CK1_H
138
CK1_L
220
CK2_H
221
CK2_L
18
RESET_L
52
CKE0
171
CKE1
192
RAS_L
74
CAS_L
193
S0_L
76
S1_L
DDR2-240 pin-G
+1.8V_SUS+1.8V_SUS
172
178
184
187
189
VDD1
VDD2
1975359646769170
VDD3
VDD4
VDD5
VDD6
175
181
191
194515662727578
VDD7
VDD8
VDD9
VDD10
VDD11
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
ERR_OUT_L
Title
Size Document Number Rev
Custom
Date: Sheet of
2
238
VDDSPD
236
DQ63
235
DQ62
230
DQ61
229
DQ60
117
DQ59
116
DQ58
111
DQ57
110
DQ56
227
DQ55
226
DQ54
218
DQ53
217
DQ52
108
DQ51
107
DQ50
99
DQ49
98
DQ48
215
DQ47
214
DQ46
209
DQ45
208
DQ44
96
DQ43
95
DQ42
90
DQ41
89
DQ40
206
DQ39
205
DQ38
200
DQ37
199
DQ36
87
DQ35
86
DQ34
81
DQ33
80
DQ32
159
DQ31
158
DQ30
153
DQ29
152
DQ28
40
DQ27
39
DQ26
34
DQ25
33
DQ24
150
DQ23
149
DQ22
144
DQ21
143
DQ20
31
DQ19
30
DQ18
25
DQ17
24
DQ16
141
DQ15
140
DQ14
132
DQ13
131
DQ12
22
DQ11
21
DQ10
13
DQ9
12
DQ8
129
DQ7
128
DQ6
123
DQ5
122
DQ4
10
DQ3
9
DQ2
4
DQ1
3
DQ0
73
WE_L
1
VREF
102
TEST
195
ODT0
77
ODT1
55
68
PAR_IN
19
NC1
DIMMA2
MEM_MA_DATA[0..63]
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA59
MEM_MA_DATA58
MEM_MA_DATA57
MEM_MA_DATA56
MEM_MA_DATA55MEM_MA_DATA55
MEM_MA_DATA54
MEM_MA_DATA53
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA49
MEM_MA_DATA48
MEM_MA_DATA47
MEM_MA_DATA46
MEM_MA_DATA45
MEM_MA_DATA44
MEM_MA_DATA43
MEM_MA_DATA42
MEM_MA_DATA41
MEM_MA_DATA40
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA37
MEM_MA_DATA36
MEM_MA_DATA35
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA31
MEM_MA_DATA30
MEM_MA_DATA29
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA26
MEM_MA_DATA25
MEM_MA_DATA24
MEM_MA_DATA23
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA20
MEM_MA_DATA19
MEM_MA_DATA18
MEM_MA_DATA17
MEM_MA_DATA16
MEM_MA_DATA15
MEM_MA_DATA14
MEM_MA_DATA13
MEM_MA_DATA12
MEM_MA_DATA10
MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA6
MEM_MA_DATA5
MEM_MA_DATA4
MEM_MA_DATA3
MEM_MA_DATA2
MEM_MA_DATA1
MEM_MA_DATA0MEM_MA_DATA0
12
C126
0.1UF 16V Y5V 0402
PLACE NEAR DIMM SOCKETS
DDR DIMM1 & 2
A78DG-A2T
1
MEM_MA_DATA[0..63] 8MEM_MA_DATA[0..63] 8
MEM_MA_WE_L8,12
MEM_M_VREF
MEM_MA1_ODT08,12
6.0
13 48Friday, May 29, 2009
A
5
A
4
3
2
1
194515662727578
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
4
VDDQ9
+3.3V
VDDQ10
VDDQ11
238
VDDSPD
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
WE_L
VREF
TEST
ODT0
ODT1
ERR_OUT_L
PAR_IN
DIMMB1
MEM_MB_DATA[0..63]
MEM_MB_DATA63
236
MEM_MB_DATA62
235
MEM_MB_DATA61
230
MEM_MB_DATA60
229
MEM_MB_DATA59
117
MEM_MB_DATA58
116
MEM_MB_DATA57
111
MEM_MB_DATA56
110
MEM_MB_DATA55
227
MEM_MB_DATA54
226
MEM_MB_DATA53
218
MEM_MB_DATA52
217
MEM_MB_DATA51
108
MEM_MB_DATA50
107
MEM_MB_DATA49
99
MEM_MB_DATA48
98
MEM_MB_DATA47
215
MEM_MB_DATA46
214
MEM_MB_DATA45
209
MEM_MB_DATA44
208
MEM_MB_DATA43
96
MEM_MB_DATA42
95
MEM_MB_DATA41
90
MEM_MB_DATA40
89
MEM_MB_DATA39
206
MEM_MB_DATA38
205
MEM_MB_DATA37
200
MEM_MB_DATA36
199
MEM_MB_DATA35
87
MEM_MB_DATA34
86
MEM_MB_DATA33
81
MEM_MB_DATA32
80
MEM_MB_DATA31
159
MEM_MB_DATA30
158
MEM_MB_DATA29
153
MEM_MB_DATA28
152
MEM_MB_DATA27
40
MEM_MB_DATA26
39
MEM_MB_DATA25
34
MEM_MB_DATA24
33
MEM_MB_DATA23
150
MEM_MB_DATA22
149
MEM_MB_DATA21
144
MEM_MB_DATA20
143
MEM_MB_DATA19
31
MEM_MB_DATA18
30
MEM_MB_DATA17
25
MEM_MB_DATA16
24
MEM_MB_DATA15
141
MEM_MB_DATA14
140
MEM_MB_DATA13
132
MEM_MB_DATA12
131
MEM_MB_DATA11
22
MEM_MB_DATA10
21
MEM_MB_DATA9
13
DQ9
MEM_MB_DATA8
12
DQ8
MEM_MB_DATA7
129
DQ7
MEM_MB_DATA6
128
DQ6
MEM_MB_DATA5
123
DQ5
MEM_MB_DATA4
122
DQ4
MEM_MB_DATA3
10
DQ3
MEM_MB_DATA2
9
DQ2
MEM_MB_DATA1
4
DQ1
MEM_MB_DATA0
3
DQ0
73
1
102
195
77
55
68
19
NC1
MEM_MB_DATA[0..63]9
MEM_MB_WE_L9,12
MEM_M_VREF
MEM_MB0_ODT09,12
12
C128
0.1UF 16V Y5V 0402
PLACE NEAR DIMM SOCKETS
+1.8V_SUS
C135 0.1UF 16V Y5V 0402 /NI
1 2
194515662727578
VDDQ4
VDDQ5
VDDQ6
VDDQ7
+3.3V
238
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDSPD
ERR_OUT_L
Title
Size Document Number Rev
Date: Sheet of
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
WE_L
VREF
TEST
ODT0
ODT1
PAR_IN
Custom
236
235
230
229
117
116
111
110
227
226
218
217
108
107
99
98
215
214
209
208
96
95
90
89
206
205
200
199
87
86
81
80
159
158
153
152
40
39
34
33
150
149
144
143
31
30
25
24
141
140
132
131
22
21
13
DQ9
12
DQ8
129
DQ7
128
DQ6
123
DQ5
122
DQ4
10
DQ3
9
DQ2
4
DQ1
3
DQ0
73
1
102
195
77
55
68
19
NC1
DIMMB2
MEM_MB_DATA[0..63]
MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0
MEM_MB_DATA[0..63]9
MEM_MB_WE_L9,12
MEM_MB1_ODT09,12
12
C129
0.1UF 16V Y5V 0402
PLACE NEAR DIMM SOCKETS
DDR DIMMB2&3
A78DG-A2T
MEM_M_VREF
1
14 48Friday, May 29, 2009
6.0
+1.8V_SUS
DIMMB2
172
178
184
187
189
1975359646769170
MEM_MB_DM[8..0]9
MEM_MB_DQS_H[8..0]9
MEM_MB_DQS_L[8..0]9
SCLK13,20,22,43
SDATA13,20,22,43
MEM_MB_BANK29,12
MEM_MB_BANK19,12
MEM_MB_BANK09,12
MEM_MB_ADD[15..0]9,12
MEM_MB_CHECK[7..0]9
MEM_MB1_CLK_H09,12
MEM_MB1_CLK_L09,12
MEM_MB1_CLK_H19,12
MEM_MB1_CLK_L19,12
MEM_MB1_CLK_H29,12
MEM_MB1_CLK_L29,12
MEM_MB_CKE19,12
MEM_MB_RAS_L9,12
MEM_MB_CAS_L9,12
MEM_MB1_CS_L09,12
MEM_MB1_CS_L19,12
MEM_MB_DM[8..0]
MEM_MB_DM8
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
MEM_MB_DQS_H[8..0]
MEM_MB_DQS_H8
MEM_MB_DQS_L8
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DQS_L[8..0]
+3.3V
MEM_MB_ADD[15..0]
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_CHECK[7..0]
MEM_MB_CHECK7
MEM_MB_CHECK6
MEM_MB_CHECK5
MEM_MB_CHECK4
MEM_MB_CHECK3
MEM_MB_CHECK2
MEM_MB_CHECK1
MEM_MB_CHECK0
3
164
165
232
233
223
224
211
212
202
203
155
156
146
147
134
135
125
126
46
45
114
113
105
104
93
92
84
83
37
36
28
27
16
15
7
6
101
240
239
120
119
54
190
71
173
174
196
176
57
70
177
179
58
180
60
61
182
63
183
188
168
167
162
161
49
48
43
42
185
186
137
138
220
221
18
52
171
192
74
193
76
DDR2-240 pin-G
DQS17_H
DQS17_L
DQS16_H
DQS16_L
DQS15_H
DQS15_L
DQS14_H
DQS14_L
DQS13_H
DQS13_L
DQS12_H
DQS12_L
DQS11_H
DQS11_L
DQS10_H
DQS10_L
DQS9_H
DQS9_L
DQS8_H
DQS8_L
DQS7_H
DQS7_L
DQS6_H
DQS6_L
DQS5_H
DQS5_L
DQS4_H
DQS4_L
DQS3_H
DQS3_L
DQS2_H
DQS2_L
DQS1_H
DQS1_L
DQS0_H
DQS0_L
SA2
SA1
SA0
SCL
SDA
BA2
BA1
BA0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
CK0_H
CK0_L
CK1_H
CK1_L
CK2_H
CK2_L
RESET_L
CKE0
CKE1
RAS_L
CAS_L
S0_L
S1_L
VDD1
VDD2
VDD3
VDD4
VDD5
2
175
181
191
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDDQ1
VDDQ2
VDDQ3
+1.8V_SUS
DIMMB1
172
178
184
187
189
1975359646769170
VDD1
VDD2
VDD3
VDD4
D D
MEM_MB_DM[8..0]9
MEM_MB_DQS_H[8..0]9
C C
MEM_MB_DQS_L[8..0]9
SCLK13,20,22,43
SDATA13,20,22,43
MEM_MB_BANK29,12
MEM_MB_BANK19,12
MEM_MB_BANK09,12
MEM_MB_ADD[15..0]9,12
B B
MEM_MB_CHECK[7..0]9
MEM_MB0_CLK_H09,12
MEM_MB0_CLK_L09,12
MEM_MB0_CLK_H19,12
MEM_MB0_CLK_L19,12
MEM_MB0_CLK_H29,12
MEM_MB0_CLK_L29,12
MEM_MB_CKE09,12
MEM_MB_RAS_L9,12
MEM_MB_CAS_L9,12
MEM_MB0_CS_L09,12
MEM_MB0_CS_L19,12
MEM_MB_DM[8..0]
MEM_MB_DM8
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
MEM_MB_DQS_H[8..0]
MEM_MB_DQS_H8
MEM_MB_DQS_L8
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DQS_L[8..0]
+3.3V
MEM_MB_ADD[15..0]
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_CHECK[7..0]
MEM_MB_CHECK7
MEM_MB_CHECK6
MEM_MB_CHECK5
MEM_MB_CHECK4
MEM_MB_CHECK3
MEM_MB_CHECK2
MEM_MB_CHECK1
MEM_MB_CHECK0
164
165
232
233
223
224
211
212
202
203
155
156
146
147
134
135
125
126
46
45
114
113
105
104
93
92
84
83
37
36
28
27
16
15
7
6
101
240
239
120
119
54
190
71
173
174
196
176
57
70
177
179
58
180
60
61
182
63
183
188
168
167
162
161
49
48
43
42
185
186
137
138
220
221
18
52
171
192
74
193
76
DDR2-240 pin-T
DQS17_H
DQS17_L
DQS16_H
DQS16_L
DQS15_H
DQS15_L
DQS14_H
DQS14_L
DQS13_H
DQS13_L
DQS12_H
DQS12_L
DQS11_H
DQS11_L
DQS10_H
DQS10_L
DQS9_H
DQS9_L
DQS8_H
DQS8_L
DQS7_H
DQS7_L
DQS6_H
DQS6_L
DQS5_H
DQS5_L
DQS4_H
DQS4_L
DQS3_H
DQS3_L
DQS2_H
DQS2_L
DQS1_H
DQS1_L
DQS0_H
DQS0_L
SA2
SA1
SA0
SCL
SDA
BA2
BA1
BA0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
CK0_H
CK0_L
CK1_H
CK1_L
CK2_H
CK2_L
RESET_L
CKE0
CKE1
RAS_L
CAS_L
S0_L
S1_L
VDD5
175
181
191
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDDQ1
VDDQ2
VDDQ3
5
A
5
A
4
3
2
1
D D
C C
HTCPU_DWNCLK06
HTCPU_DWNCLK0_6
HTCPU_DWNCLK16
HTCPU_DWNCLK1_6
HTCPU_DWNCNTL6
HTCPU_DWNCNTL_6
HTCPU_DWNCNTL16
HTCPU_DWNCNTL1_6
B B
HTCPU_DWN0
HTCPU_DWN_0
HTCPU_DWN1
HTCPU_DWN_1
HTCPU_DWN2
HTCPU_DWN_2
HTCPU_DWN3
HTCPU_DWN_3
HTCPU_DWN4
HTCPU_DWN_4
HTCPU_DWN5
HTCPU_DWN_5
HTCPU_DWN6
HTCPU_DWN_6
HTCPU_DWN7
HTCPU_DWN_7
HTCPU_DWN8
HTCPU_DWN_8
HTCPU_DWN9
HTCPU_DWN_9
HTCPU_DWN10
HTCPU_DWN_10
HTCPU_DWN11
HTCPU_DWN_11
HTCPU_DWN12
HTCPU_DWN_12
HTCPU_DWN13
HTCPU_DWN_13
HTCPU_DWN14
HTCPU_DWN_14
HTCPU_DWN15
HTCPU_DWN_15
HTCPU_DWNCLK0
HTCPU_DWNCLK0_
HTCPU_DWNCLK1
HTCPU_DWNCLK1_
HTCPU_DWNCNTL
HTCPU_DWNCNTL_
HTCPU_DWNCNTL1
HTCPU_DWNCNTL1_
HT_RXCALP
HT_RXCALN
HTCPU_DWN[15..0]6
HTCPU_DWN_[15..0]6 HTCPU_UP_[15..0] 6
HTCPU_DWN[15..0]
HTCPU_DWN_[15..0] HTCPU_UP_[15..0]
Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25
AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18
T22
T23
AB23
AA22
M22
M23
R21
R20
C23
A24
U1A
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N
HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N
HT_RXCALP
HT_RXCALN
RS780D
PART 1 OF 6
HYPER TRANSPORT CPU
I/F
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
HT_TXCALP
HT_TXCALN
D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22
F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18
H24
H25
L21
L20
M24
M25
P19
R18
B24
B25
HTCPU_UP[15..0]
HT_TXCALP
HT_TXCALN
HTCPU_UP0
HTCPU_UP_0
HTCPU_UP1
HTCPU_UP_1
HTCPU_UP2
HTCPU_UP_2
HTCPU_UP3
HTCPU_UP_3
HTCPU_UP4
HTCPU_UP_4
HTCPU_UP5
HTCPU_UP_5
HTCPU_UP6
HTCPU_UP_6
HTCPU_UP7
HTCPU_UP_7
HTCPU_UP8
HTCPU_UP_8
HTCPU_UP9
HTCPU_UP_9
HTCPU_UP10
HTCPU_UP_10
HTCPU_UP11
HTCPU_UP_11
HTCPU_UP12
HTCPU_UP_12
HTCPU_UP13
HTCPU_UP_13
HTCPU_UP14
HTCPU_UP_14
HTCPU_UP15
HTCPU_UP_15
HTCPU_UPCLK0
HTCPU_UPCLK0_
HTCPU_UPCLK1
HTCPU_UPCLK1_
HTCPU_UPCNTL
HTCPU_UPCNTL_
HTCPU_UPCNTL1
HTCPU_UPCNTL1_
R27 301 1% 0402R26 301 1% 0402
HTCPU_UP[15..0] 6
HTCPU_UPCLK06
HTCPU_UPCLK0_6
HTCPU_UPCLK16
HTCPU_UPCLK1_6
HTCPU_UPCNTL6
HTCPU_UPCNTL_6
HTCPU_UPCNTL16
HTCPU_UPCNTL1_6
+V_CPU
C138
10UF 10V 0805 Y5V
C139
10UF 10V 0805 Y5V
C140
10UF 10V 0805 Y5V
C142
10UF 10V 0805 Y5V
HT LINK STITCHING CAPS
A
Title
Size Document Number Rev
Date: Sheet of
5
4
3
2
RS780-HT LINK
A78DG-A2T
15 48Friday, May 29, 2009
1
6.0B
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