BBK 9907-S Service manual

INDEX

1. PRAFACE

1.1 PRAFACE.....................................................................................................................1

1.2 FRANT PENEL& REAR PENEL.....................................................................................2

1.3 REMOTE CONTROL............................................................................. .......................3

2. BLOCK DIAGRAM

2.1 BLOCK DIAGRAM........................................................................................................4.

2.2 SCHEMATIC DIAGRAM.................................................................................................5

3. EXPLODED VIEW......................................................................6

4. PARTS SPECIFICATIONS

4.1 2A265.....................................................................................................................7-10

4.2 CS9800.................................................................................................................11-18

4.3 DRAM 2M*32(EM638165).......................................................................................19-22

4.4 CS4955.................................................................................................................23-25

4.5 CS4360.................................................................................................................26-30

4.6 CS92288...............................................................................................................31-45

4.7 DRAM 1M*16(VT3617161)......................................................................................46-49

4.8 SAA7114H.............................................................................................................50-57

4.9 CS533...................................................................................................................58-59

4.10 PCF8563.............................................................................................................60-62

4.11 TUNER................................................................................................................... .63

4.12 VFD DRIVER PT6312.................................................................... ......................64-65

4.13 SERVO............................................................................................. .......................66

4.14 HDD INFORMATION.............................................................................................67-68

INDEX

5. SCHEMATIC DIAGRAM

5.1 POWER SCHEMATIC..................................................................... .......................69-70

5.2 MAIN SCHEMATIC......................................................................... .......................71-79

5.3 AV INPUT /OUTPUT SCHEMATIC.................................................... ...................... 80-87

5.4 VFD DRIVER........................................................................................................ 88-89

6. PARTS LIST

6.1 MAIN BOARD........................................................................................................90-92

6.2 VFD DRIVER BOARD.......................................................................... .......................93

6.3 POWER BOARD....................................................................................................94-95

6.4 AV BOARD.................................................................................................................96

~110~240V

POWER

BOARD

BLOCK DIAGRAM

VIDEO OUT VIDIO IN PUT

AUDIO OUT AUDIO IN PUT

+12V

+5V

-12V

+3.3V

+2.5V

+1.8V

S-VIDEO OUT

CB.CR.YOUT

COAXIAL OUT

OPTICAL OUT

TUNER75

IN PUT

AV BOARD

DVD LOADER

DRIVE

40GB HDD

40GB HDD DRIVE

MAIN BOARD

MPEG VIDEO DECODER&

MPEG-2

AUDIO/ VIDEO CODER

PT16312

KEY SCANNING &

VFD DISPLAY

SCHEMATIC DIAGRAM

ATAPI

TO DVD LOADER DRIVE

HDD ATAPI I/O CHAN

CPLD

Host interface

3.3V

L.R CH

2.5V

VCC

AUDIO

TO-TUNER

5VSTB

1.8V

AUDIO

ADC

DECOD

S-VIDEO

P-CT L

CS5331

SAA7114

VIDEO

1M*16 4PCS

DRAM

16M

FLASH

CS92288

MPEG-2

A/V CODEC

To front panel

SS9800

MPEG

DECODER

CS4360

AUDIO

DACS

AUDIO R(3CH)

AUDIO L3CH

ENCODER

VIDEO

—— D/A

TO TUNER

CS4955

TO S-VIDEO

TO VFD BOARD

CN104

To front panel

2M*32

DRAM

COMPOSITE VIDEO

S-VIDEO

NO. ITEM NAME MATERIAL QUANTITY

Mirror bar pc

Left decorative bar ABS

Tray door ABS

Front panel ABS

Left four-key button ABS

Small light conductor PMMA

Big light conductor PMMA

LED stander PS

VFD driver board

Chasis SECC

Loader mechanism PS

DVD loader

Iron stand SECC

Power board

Top cover SECC

Rear panel SECC

AV board

Main board

Hard disc

Copper column

Rubber pad RUBBER

Open/close button ABS

Right four-key button ABS

Right decorative bar ABS

EXPLODED VIEW

Circuit Diagram: ICE2AXXX for OFF ¨C Line Switch Mode Power Supplies

ICE2AXXX for OFF – Line Switch Mode Power Supplies

Protection Functions

The block diagram displayed in Fig. 4 shows the interal functions of the protection unit. The

comparators C1, C2, C3 and C4 compare the soft-start and feedback-pin voltages. Logic gates

connected to the comparator outputs ensure the combination of the signals and enables the setting of

the “Error-Latch”.

ICE2AXXX for OFF – Line Switch Mode Power Supplies

Overload and Open-Loop Protection

• Feedback voltage (VFB) exceeds 4.8V and soft start

voltage (VSS) is above 5.3V (soft start is completed) (t1)

• After a 5µs delay the CoolMOS is switched off (t2)

• Voltage at Vcc – Pin (VCC) decreases to 8.5V (t2)

• Control logic is switched off (t3)

• Start-up resistor charges Vcc capacitor (t3)

• Operation starts again with soft start after Vcc voltage

has exceeded 13.5V (t4)

t1, t2

VFB

VSS

Fig. 6

Fig. 7

t1, t2

VFB

VSS

ICE2AXXX for OFF – Line Switch Mode Power Supplies

References

[1] Keith Billings,

Switch Mode Power Supply Handbook

[2] Ralph E. Tarter,

Solid-State Power Conversion Handbook

[3] R. D. Middlebrook and Slobodan Cuk,

Advances in Switched-Mode Power Conversion

[4] Herfurth Michael,

Ansteuerschaltungen für getaktete Stromversorgungen mit Erstellung eines linearisierten

Signalflußplans zur Dimensionierung der Regelung

[5] Herfurth Michael,

Topologie, Übertragungsverhalten und Dimensionierung häufig eingesetzter

Regelverstärker

[6] Infineon Technologies, Datasheet,

CoolSET-II

Off – Line SMPS Current Mode Controller with 650V/800V CoolMOSääää on Board,

[7] Robert W. Erickson,

Fundamentals of Power Electronics

Internet DVD (iDVD) Chip Solution

CS98000

Features

Powerful Dual 32-bit RISCs >160MIPS

Software based on popular RTOS, C/C++

MPEG video decoder supports DVD, VCD, VCD 3.0, SVCD standards

Video input with picture-in-picture & zoom

8-bit multi-region OSD w/vertical flicker filter

Universal subpictur e unit for DVD and SVCD

PAL<->NTSC Scaling ~ Transcoding

Supports SDRAM and FLASH memories

Powerful 32-bit Audio DSP >80 MIPS

Decodes: 5.1 channel AC-3, MPEG Stereo

Plays MP-3 CDs (a MP-3 CD =12 albums)

Karaoke echo mix and pitch shift

Optional 3-D Virtual, bass & treble control

8-channel dual-zone PCM output

IEC-60958/61937 Out: AC-3, DTS, MPEG

Multi-Mode Serial Audio I/O: I2S & AC-Link

AV Bus or ATAPI interface or DVD/CD/HD

GPIO support for all common sub-circuits

Description

Overall the CS98000 Crystal DVD Processor is targeted as a market s pecific c onsum er ent ert ainment proces sor empowering new product classes with the inclusion of a DVD player as a fundamental feature. This integrated circuit when used with al l the other Crystal mixed signal data converters, DSPs and high quality factory firmware enables the conception and rapid design of market leading internet age products like:

• DVD A/V Mini-System

• Home Media Controller

• Combination DVD Player

• Car/SUV Entertainment Unit

Future Fir m w are Enhancem ent s :

• Web I/O vi a AC-Li n k In put & Built-in Soft Modem

• DVD Audio Navigation

• MLP Decoder, DTS Dec oder, AAC Decoder

• MP-3 Encoder, Ripping Controller

ORDERING INFORMATION

CS98000-CQ 0° to 70° C 208-pin CS98010-CQ 0° to 70° C 128-pin

RISC-1

I-Cache D-Cache

MMU

Video Input

Filter

MPEG Decoder

VLC Parser

RAM MoCo

Video Processor

On-Screen Display Picture-in-Picture

Video/Graphics Display

MAC

Scaler

IDCT

Preliminary Product Information

RISC-2

I-Cache D-Cache

MMU

Clock Manager

Dataflow Engine

External I/Os

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

MAC

DMA / BitBlit SRAM Buffer

Remote Input

GPIOs

Memory Controller

SDRAM Control

FLASH Control

Subpicture Decode

Scaler

System Controls

STC

Interrupts

Registers

SDRAM

32- Bit DSP

I-Cache

X,Y Data

Memory

CPU / MAC

Audio I/O

PCM Out

PCM In

XMT958

A/V Bus ATAPI-IDE Local Bus

6. PIN DESCRIPTION

CS98000

Host/Loader (30)

Video In (12)

CODEC IF (5)

MISC. (41)

GPIO_[15-10, 8-7, 4-2, 0]

H_D_[15:0] H_CS_[3:0]

H_A_[4:0]

H_ALE

H_RD

H_WR

H_CKO

H_RDY

VIN_D[7:0] VIN_HSNC VIN_VSNC

VIN_CLK VIN_FLD

CDC_DI

CDC_DO

CDC_RST

CDC_CK CDC_SY

XTLCLOCK

RST_N

IR_IN

MFG_TST

GPIO_D[20-0]

GPIO_H[16-14]

GPIO_V10

CS98000

M_A_[11:0] M_BS_L M_D_[31:0] M_DQM_[3:0 ] M_RAS_L M_CAS_L M_WE_L M_AP M_CKE M_CKO NVR_OE_L NVR_WR_L

HSYNC VSYNC CLK27_O VDAT_[7:0]

AUD_BCK AUD_LRCK AUD_DO_[3:0] SPDIF_O

AIN_BCK AIN_LRCK AIN_DATA

Memory IF (57)

Video out (11)

DAC Out (7)

ADC In (3)

Table 5 lists the conventions used to identify the pin type and direction in the table that follows.

I Input IS Input, with schmitt trigger ID Input, with pull down resistor IU Input, with pull up resistor O Output O4 Output – 4mA drive

O8 Output – 8mA drive T4 Tri-State-able Output – 4mA drive B Bi-direction B4 Bi-direction – 4mA drive B4U Bi-direction – 4mA drive, with pull-up B8U Bi-direction – 8mA drive, with pull-up B4S Bi-direction – 4mA drive, with schmitt trigger B4SU Bi-direction – 4mA drive, with pull-up and schmitt trigger Pwr +2.5V or +3.3V power supply voltage Gnd Power supply ground Name_N Low active Name_L Low active

Table 5. Pin Type legend

CS98000

6.1 Pin Assignments

Table 6 lists the pin number, pin name and pin type for the 208 pin CS98000 package. The primary function and pin direction is shown for all signal

Pin Name Type Primary Function Dir Seco ndary Function Dir Note

1 V DD_P LL Pwr PLL Power 2.5V 2 M_A_11 O8 SDRAM Address[11] O ROM/NVRAM Address[11] O 3 M_A_10 O8 SDRAM Address[10] O ROM/NVR AM Ad dress[10] O 4 GPIO_D18 B4U GenioDVD[18] B System Clock PLL Bypass I 5 M_A_9 O8 SDRAM Address[9] O ROM/NVRAM Address[9] O 6 M_A _8 O8 SDRAM Address[8] O ROM/NVRAM Address8] O 7 M_A_7 O8 SDRAM Address[7] O ROM/NVRAM Address[7] O 8 GPIO_D16 B4SU GenioDVD[16] B

9 M_A_6 O8 SDRAM Address[6] O ROM/NVRAM Address[6] O 10 M_A_5 O8 SDRAM Address[5] O ROM/NVRAM Address[5] O 11 M_A_4 O8 SDRAM Addre ss[4] O ROM/NVRAM Address[4] O 12 GPIO_D17 B4U GenioDVD[17] B 13 M_A_3 O8 SDRAM Address[3] O ROM/NVRAM Address[3] O 14 M_A_2 O8 SDRAM Address[2] O ROM/NVRAM Address[2] O 15 M_A_1 O8 SDRAM Address[1] O ROM/NVRAM Address[1] O 16 M_A_0 O8 SDRAM Address[0] O ROM/NVRAM Address[0] O 17 GPIO_D19 B4U GenioDVD[19] B Memory Clock PLL Bypass I 18 VSS_IO G nd I/O Ground 19 M_CKO O8 SDRAM Clock O 20 VDD_IO Pwr I/O Power 3.3V 21 M_BS_L O8 SDRAM Bank Select O 22 M_CKE B8 SDRAM Clock Enable O GenioMis(7) B 23 M_ AP O8 SDRAM Auto Pre-charge O 24 M_RAS _L O8 SDRAM Row Strobe O 25 M_CAS _L O8 SDRAM Column Strobe O 26 GPIO_D20 B4U G enioDVD[20] B 27 M_WE_L O8 SDRA M Write Enable O 28 M_DQM_0 O8 SDRAM DQM[0] O 29 M_DQM_1 O8 SDRAM DQM[1] O 30 GPIO_D0 B4U GenioDVD[0] B 31 M_DQM_2 O8 SDRAM DQM[2] O 32 M_DQM_3 O8 SDRAM DQM[3] O 33 M_D_8 B8U SDRAM Data[8] B ROM/NVRAM Data[8] B 34 GPIO_D1 B4U GenioDVD[1] B 35 VSS_IO G nd I/O Ground

pins. For some signal pins, a secondary function and direction are also shown. For pins having more than one function, the primary function is chosen when the chip is reset.

Table 6. Pin assignments

CS98000

36 VSS_CORE Gnd Core Ground 37 M_D_7 B8U SDRAM Data[7] B ROM/NVRAM Data[7] B 38 VDD_IO Pwr I/O Power 3.3V 39 GPIO_D2 B4U GenioDVD[2] B 40 M_D_9 B8U SDRAM Data[9] B ROM/NVRAM Data[9] B 41 VDD_CORE Pwr Core Power 2.5V 42 M_D_6 B8U SDRAM Data[6] B ROM/NVRAM Data[6] B 43 GPIO_D3 B4U GenioDVD[3] B 44 M_D_10 B8U SDRAM Data[10] B ROM/NVRAM Data[10] B 45 M_D_5 B8U SDRAM Data[5] B ROM/NVRAM Data[5] B 46 M _D_11 B8U S DRAM Data[11] B ROM/NVRAM Data[11] B 47 GPIO_D4 B4U GenioDVD[4] B 48 M_D_4 B8U SDRAM Data[4] B ROM/NVRAM Data[4] B 49 M_D_12 B8U SDRAM Data[12] B ROM/NVRAM Data[12] B 50 GPIO_D5 B4U GenioDVD[5] B 51 M_D_3 B8U SDRAM Data[3] B ROM/NVRAM Data[3] B 52 UNUSED may leave unconnected 53 UNUSED may leave unconnected 54 M_D_13 B8U SDRAM Data[13] B ROM/NVRAM Data[13] B 55 M_D_2 B8U SDRAM Data[2] B ROM/NVRAM Data[2] B 56 M_D_14 B8U SDRAM Data[14] B ROM/NVRAM Data[14] B 57 GPIO_D6 B4U GenioDVD[6] B 58 VSS_IO G nd I/O Ground 59 M_D_1 B8U SDRAM Data[1] B ROM/NVRAM Data[1] B 60 M_D_15 B8U SDRAM Data[15] B ROM/NVRAM Data[15] B 61 GPIO_D7 B4U GenioDVD[7] I B 62 M_D_0 B8U SDRAM Data[0] B ROM/NVRAM Data[0] B 63 VSS_CORE Gnd Core Ground 64 M_D_24 B8U SDRAM Data[24] B ROM/NVRAM Address[20] O 65 GPIO_D11 B4U GenioDVD[11] B 66 VDD_CORE Pwr Core Power 2.5V 67 M_D_23 B8U SDRAM Data[23] B ROM/NVRAM Address[19] O 68 M_D_25 B8U SDRAM Data[23] B ROM/NVRAM Address[21] O 69 GPIO_D10 B4U GenioDVD[10] B 70 M_D_22 B8U SDRAM Data[22] B ROM/NVRAM Address[18] O 71 M_D_26 B8U SDRAM Data[26] B ROM/NVRAM Address[22] O 72 M_D_21 B8U SDRAM Data[21] B ROM/NVRAM Address[17] O 73 GPIO_D9 B4U GenioDVD[9] B 74 M_D_27 B8U SDRAM Data[27] B ROM/NVRAM Address[23] O 75 M_D_20 B8U SDRAM Data[20] B ROM/NVRAM Address[16] O 76 M_D_28 B8U SDRAM Data[28] B

Table 6. Pin assignments (Continued)

CS98000

77 GPIO_D8 B4U GenioDVD[8] B

78 M_D_19 B8U SDRAM Data[19] B ROM/NVRAM Address[15] O

79 M_D_29 B8U SDRAM Data[29] B

80 M_D_18 B8U SDRAM Data[18] B ROM/NVRAM Address[14] O

81 NV_WE_L B4U NV RA M Write Enable O GenioMis[8] B

82 VSS_CORE Gnd Core Ground

83 M_D_30 B8U SDRA M Data[30] B ROM/NVRAM Decode Low O

84 VDD_CORE Pwr Core Power 2.5V

85 H_ALE B4U Host Address Latch O GenioHst[13] B

86 M_D_17 B8U SDRAM Data[18] B ROM/NVRAM Address[13] O

87 M_D_31 B8U SDRAM Data[31] B ROM/NVRAM Decode High O

88 M_D_16 B8U SDRAM Data[16] B ROM/NVRAM Address[12] O

89 GPIO_H14 B4U GenioHst[14] B

90 NV_OE_L O4 ROM/NVRAM Output

Enable 91 VDD_IO Pwr I/O Power 3.3V 92 H_RD B4S Host Read Strobe O DVD Data Strobe I 1 93 H_WR B4 Host Write Strobe O DVD Data Enable I 1 94 GPIO_H15 B4U GenioHst[15] B 95 H_RDY B4 Host Ready I DVD Data Ready O 1 96 VSS_IO G nd I/O Ground 97 H_A_2 B4 Host Address[2] O GenioHst[10] B 1 98 GPIO_H16 B4U GenioHst[16] B 99 H_A_1 B4 Host Address[1] O GenioHst[9] B 1

100 H_A_0 B4 Host Address[0] O GenioHst[8] B 1 101 H_CS_1 B4 Host Chip Select [1] O DVD Error I 1 102 H_A_4 B4 Host Address[4] O GenioHst[12] B 1 103 VSS_CORE Gnd Core Ground 104 VSS_PLL Gnd PLL Ground 105 VDD_PLL Pwr PLL Power 2.5V 106 H_CS_0 B4 Ho st Chip Select[0] O DVD Start Sector I 1 107 H_A_3 B 4 Host Address[3] O G enioH st[11] B 1 108 VDD_CORE Pwr Core Power 2.5V 109 H_D_15 B4 Host Data[15] B CD Data I 1, 2 1 10 H_D_14 B4 Host Data[14] B CD Left Right Clock I 1, 2 111 H_CS_3 B4 Host Chip Select[3] O Gen ioHst[18] B 1 112 H_D_13 B4S Host Data[13] B CD Clock I 1, 2 113 H_D_12 B4 Host Data[12] B CD Error I 1, 2 1 14 H_D_11 B4 Host Data[11] B DVD Control Data In I 1, 2 115 H_CS_2 B4 Host Chip Select[2] O GenioHst[17] B 1 1 16 H_D_10 B4 Host Data[10] B DVD Control Data Out O 1, 2

Table 6. Pin assignments (Continued)

CS98000

117 H_D_9 B4 Host Data[9] B DVD Control Ready I 1, 2 1 1 8 H_D_8 B4 Host Data[8] B DVD Control Clock O 1, 2

119 VSS_IO Gnd I/O Ground 120 H_CKO B4 Host Clock O GenioHst[19] B 1 121 H_D_7 B4 Host Data[7] B DVD Data[7] I 1 122 H_D_6 B4 Host Data[6] B DVD Data[6] I 1 123 H_D_5 B4 Host Data[5] B DVD Data[5] I 1 124 AUD_BCK B4 Audio Out Bit Clock O GenioMis[3] B 125 H_D_4 B4 Host Data[4] B DVD Data[4] I 1 126 VSS_CORE Gnd Core Ground 127 H_D_3 B4 Host Data[3] B DVD Data[3] I 1 128 AUD_LRCK O4 A udio Out LR Clock O 129 VDD_CORE Pwr Core Power 2.5V 130 H_D_2 B4 Host Data[2] B DVD Data[2] I 1 131 VDD_IO Pwr I/O Pow er 3.3V 132 H_D_1 B4 Host Data[1] B DVD Data[1] I 1 133 AUD_DO_2 B4 Audio Out Data[2] O GenioMis[2] B 134 H_D_0 B4 Host Data[0] B DVD Data[0] I 1 135 AUD_DO_0 O4 Audio Out Data[0] O 136 AUD_DO_1 B4 Audio Out Data[1] O GenioMis[1] B 137 AIN_BC K IU Audio In Bit Clock I 138 VSS_CORE Gnd Core Ground 139 AIN_LRCK IU A udio In LR Clock I 140 AIN_DATA B4U Audio In Data I GenioMis[0] B 141 VDD_CORE Pwr Core Power 2.5V 142 CDC_DI IU S erial CODEC Data In I 143 VSS_IO Gnd I/O Ground 144 CDC_DO T4 Serial CODEC Data Out O 145 VIN_CLK IU Video Input Clock I 146 CDC_RST T4 Serial CODEC Reset O 147 CDC_CK IU Seri al CODEC Bit Clock I 148 CDC_SY B4U Serial CODEC Sync B 149 GPIO_V10 B4U GenioMis[26] B 150 GPIO_D15 B4U GenioDvd[15] 151 GPIO_D14 B4U GenioDvd[14] 152 GPIO_D13 B4SU GenioDvd[13] 153 VIN_VSNC B4U Video Input Vsync I GenioMis[25] B 154 CLK 27_O B4U Video Output Clock O GenioMis[6] B 155 GPIO_D12 B4U GenioDvd[12] 156 VDD_PLL Pwr PLL Power 2.5V 157 VSS_PLL Gnd PLL Ground

Table 6. Pin assignments (Continued)

CS98000

158 VSS_CORE Gnd Core Ground

159 HSYNC B4U Video Output Hsync O GenioMis[4] B

160 VIN_HSYNC B4U Video Input Hsync I GenioMis[24] B

161 VDD_CORE Pwr Core Power 2.5V

162 VSYNC B4U Video Output Vsync O GenioMis[ 5] B

163 VDAT_0 O4 Video Output Data[0] O

164 VIN_D0 B4U Video Input Data[ 0] I GenioMis[16] B

165 VDAT_1 O4 Video Output Data[1] O

166 VDAT_2 O4 Video Output Data[2] O

167 VDAT_3 O4 Video Output Data[3] O

168 VIN_D1 B4U Video Input Data[ 1] I GenioMis[17] B

169 VDAT_4 O4 Video Output Data[4] O

170 VDAT_5 O4 Video Output Data[5] O

171 UNUSED may leave unconnected

172 VDAT_6 O4 Video Output Data[6] O

173 VDAT_7 O4 Video Output Data[7] O

174 GPIO_0 B4U General Purpose IO[0] B Audio PLL Input Bypass I

175 VIN_D2 B4U Video Input Data[ 2] I GenioMis[18] B

176 VSS_CORE Gnd Core Ground

177 AUD_DO_3 B4U Audio Out Data[3] O General Purpos e IO[1] B

178 VDD_CORE Pwr Core Power 2.5V

179 VIN_D3 B4U Video Input Data[ 3] I GenioMis[19] B

180 VDD_IO Pwr I/O Pow er 3.3V

181 GPIO_2 B4U G eneral Purpose IO [2] B

182 VSS_IO Gnd I/O Ground

183 GPIO_3 B4U G eneral Purpose IO [3] B

184 VIN_D4 B4U Video Input Data[ 4] I GenioMis[20] B

185 GPIO_4 B4U G eneral Purpose IO [4] B

186 SCL B4U I

187 SDA B4U I

188 GPIO_7 B4U G eneral Purpose IO [7] B

189 VIN_D5 B4U Video Input Data[ 5] I GenioMis[21] B

190 GPIO_8 B4U G eneral Purpose IO [8] B

191 AUD_XCLK B4U Audio 256x/384x Clock B General Purpose IO[9] B

192 GPIO_10 B4U General Purpose IO[10] B

193 VIN_D6 B4U Video Input Data[ 6] I GenioMis[22] B

194 GPIO_11 B4U General Purpos e IO[11] B

195 GPIO_12 B4U General Purpose IO[12] B

196 GPIO_13 B4U General Purpose IO[13] B

197 GPIO_14 B4U General Purpose IO[14] B

198 VIN_D7 B4U Video Input Data[ 7] I GenioMis[23] B

C Clock B General Purpose IO[5] B

C Data B General Purpose IO[6] B

Table 6. Pin assignments (Continued)

CS98000

158 VSS_CORE Gnd Core Ground

159 HSYNC B4U Video Output Hsync O GenioMis[4] B

160 VIN_HSYNC B4U Video Input Hsync I GenioMis[24] B

161 VDD_CORE Pwr Core Power 2.5V

162 VSYNC B4U Video Output Vsync O GenioMis[ 5] B

163 VDAT_0 O4 Video Output Data[0] O

164 VIN_D0 B4U Video Input Data[ 0] I GenioMis[16] B

165 VDAT_1 O4 Video Output Data[1] O

166 VDAT_2 O4 Video Output Data[2] O

167 VDAT_3 O4 Video Output Data[3] O

168 VIN_D1 B4U Video Input Data[ 1] I GenioMis[17] B

169 VDAT_4 O4 Video Output Data[4] O

170 VDAT_5 O4 Video Output Data[5] O

171 UNUSED may leave unconnected

172 VDAT_6 O4 Video Output Data[6] O

173 VDAT_7 O4 Video Output Data[7] O

174 GPIO_0 B4U General Purpose IO[0] B Audio PLL Input Bypass I

175 VIN_D2 B4U Video Input Data[ 2] I GenioMis[18] B

176 VSS_CORE Gnd Core Ground

177 AUD_DO_3 B4U Audio Out Data[3] O General Purpos e IO[1] B

178 VDD_CORE Pwr Core Power 2.5V

179 VIN_D3 B4U Video Input Data[ 3] I GenioMis[19] B

180 VDD_IO Pwr I/O Pow er 3.3V

181 GPIO_2 B4U G eneral Purpose IO [2] B

182 VSS_IO Gnd I/O Ground

183 GPIO_3 B4U G eneral Purpose IO [3] B

184 VIN_D4 B4U Video Input Data[ 4] I GenioMis[20] B

185 GPIO_4 B4U G eneral Purpose IO [4] B

186 SCL B4U I

187 SDA B4U I

188 GPIO_7 B4U G eneral Purpose IO [7] B

189 VIN_D5 B4U Video Input Data[ 5] I GenioMis[21] B

190 GPIO_8 B4U G eneral Purpose IO [8] B

191 AUD_XCLK B4U Audio 256x/384x Clock B General Purpose IO[9] B

192 GPIO_10 B4U General Purpose IO[10] B

193 VIN_D6 B4U Video Input Data[ 6] I GenioMis[22] B

194 GPIO_11 B4U General Purpos e IO[11] B

195 GPIO_12 B4U General Purpose IO[12] B

196 GPIO_13 B4U General Purpose IO[13] B

197 GPIO_14 B4U General Purpose IO[14] B

198 VIN_D7 B4U Video Input Data[ 7] I GenioMis[23] B

C Clock B General Purpose IO[5] B

C Data B General Purpose IO[6] B

Table 6. Pin assignments (Continued)

CLK is driven by the system clock. All SDRAM input signals are

nal burst

CKE activates(HIGH) and deactivates(LOW) the CLK signal. If

up and hold time same as other

the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power

ter the device enters Power Down and Self Refresh modes, where CKE becomes asynchronous until exiting the same mode. The input buffers, including CLK, are disabled during Power Down and Self Refresh modes, providing low

A11 are sampled during the BankActivate command (row

A7 with A10 defining Auto Precharge) to select one location out of the 2M available in the respective bank. During a Precharge command, A10 is sampled to determine if

dress inputs also provide

CS# enables (sampled LOW) and disables (sampled HIGH) the

command decoder. All commands are masked when CS# is sampled HIGH.

lection on systems with multiple banks. It is

The RAS# signal defines the operation commands in

conjunction with the CAS# and WE# signals and is latched at the positive edges

RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH," the

ned on to the active state. When the WE# is asserted "LOW," the Precharge command is selected and the bank designated by BS is switched to the idle state after the

n commands in conjunction with the RAS# and WE# signals and is latched at the positive edges of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is started by asserting CAS# "LOW." Then, the Read or Write command

EM638165

Pin Descriptions

Symbol Type Description

CLK Input

CKE Input

BA0,BA1 Input

Table 1. Pin Details of EM638165

Clock:

sampled on the positive edge of CLK. CLK also increments the inter counter and controls the output registers.

Clock Enable:

CKE goes low synchronously with clock(setinputs), the internal clock is suspended from

Down and Self Refresh modes. CKE is synchronous except af

standby power.

Bank Select:

BA0,BA1 input select the bank for operation.

BA1 BA0 Select Bank

0 0 BANK #A 0 1 BANK #B 1 0 BANK #C 1 1 BANK #D

A0-A11 Input

CS# Input

RAS# Input

CAS# Input

Address Inputs:

address A0-A11) and Read/Write command (column address A0-

all banks are to be precharged (A10 = HIGH). The ad the op-code during a Mode Register Set command.

Chip Select:

CS# provides for external bank se considered part of the command code.

Row Address Strobe:

of CLK. When

BankActivate command is selected and the bank designated by BS is tur

precharge operation.

Column Address Strobe:

is selected by asserting WE# "LOW" or "HIGH."

A0-

The CAS# signal defines the operatio

CLK is driven by the system clock. All SDRAM input signals are

nal burst

CKE activates(HIGH) and deactivates(LOW) the CLK signal. If

up and hold time same as other

the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power

A11 are sampled during the BankActivate command (row

A7 with A10 defining Auto Precharge) to select one location out of the 2M available in the respective bank. During a Precharge command, A10 is sampled to determine if

dress inputs also provide

CS# enables (sampled LOW) and disables (sampled HIGH) the

command decoder. All commands are masked when CS# is sampled HIGH.

lection on systems with multiple banks. It is

The RAS# signal defines the operation commands in

conjunction with the CAS# and WE# signals and is latched at the positive edges

RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH," the

ned on to the active state. When the WE# is asserted "LOW," the Precharge command is selected and the bank designated by BS is switched to the idle state after the

EM638165

Pin Descriptions

Symbol Type Description

CLK Input

CKE Input

BA0,BA1 Input

Table 1. Pin Details of EM638165

Clock:

sampled on the positive edge of CLK. CLK also increments the inter counter and controls the output registers.

Clock Enable:

CKE goes low synchronously with clock(setinputs), the internal clock is suspended from

Down and Self Refresh modes. CKE is synchronous except af

standby power.

Bank Select:

BA0,BA1 input select the bank for operation.

BA1 BA0 Select Bank

0 0 BANK #A 0 1 BANK #B 1 0 BANK #C 1 1 BANK #D

A0-A11 Input

CS# Input

RAS# Input

CAS# Input

Address Inputs:

address A0-A11) and Read/Write command (column address A0-

all banks are to be precharged (A10 = HIGH). The ad the op-code during a Mode Register Set command.

Chip Select:

CS# provides for external bank se considered part of the command code.

Row Address Strobe:

of CLK. When

BankActivate command is selected and the bank designated by BS is tur

precharge operation.

Column Address Strobe:

is selected by asserting WE# "LOW" or "HIGH."

A0-

The CAS# signal defines the operatio

EM638165

Operation Mode

Fully synchronous operations are performed to latch the commands at the positive edges of CLK.

Table 2 shows the truth table for the operation commands.

Table 2. Truth Table (Note (1), (2) )

BankActivate BankPrecharge PrechargeAll Write Write and AutoPrecharge Read Read and Autoprecharge Mode Register Set No-Operation Burst Stop Device Deselect AutoRefresh SelfRefresh Entry SelfRefresh Exit

Clock Suspend Mode Entry Power Down Mode Entry

Clock Suspend Mode Exit Power Down Mode Exit

Data Write/Output Enable Data Mask/Output Disable

Command State CKE

(3)

Idle

H X X V Row address L L H H Any H X X V L X L L H L Any H X X X H

(3)

Active Active Active Active

H X X V L L H L L

(3)

H X X V H

(3)

H X X V L L H L H

(3)

H X X V H

Idle H X X OP code L L L L

Any H X X X X

(4)

Active

H X X X X Any H X X X X

Idle H H X X X Idle H L X X X Idle L H X X X

(SelfRefresh)

Active

(5)

Any

H L X X X

Active

L H X X X Any L H X X X

(PowerDown)

Active Active

H X L X X

H X H X X

n-1

CKE

DQM BA

0,1

0-9,11

X L L H L

Column address

(A0 ~ A7)

Column address

(A0 ~ A7)

X L H H H X L H H L X H X L L L H X L L L H X H

X X X H

X X X X

CS# RAS# CAS# WE#

L H L L

L H L H

X X X

L H H H

X X X X X X

L H H H

X X X X X X

L H H H

X X X X X X

Note:

1. V=Valid X=Don't Care L=Low level H=High level

2. CKEn signal is input level when commands are provided. CKE

signal is input level one clock cycle before the commands are provided.

n-1

3. These are states of bank designated by BS signal.

4. Device state is 1, 2, 4, 8, and full page burst operation.

5. Power Down Mode can not enter in the burst operation.

When this command is asserted in the burst cycle, device state is clock suspend mode.

EM638165

Commands

1 BankActivate (RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A11 = Row Address)

The BankActivate command activates the idle bank designated by the BA0,1 signals. By

latching the row address on A0 to A11 at the time of this command, the selected row access is initiated. The read or write operation in the same bank can occur after a time delay of t from the time of bank activation. A subsequent BankActivate command to a different row in the same bank can only be issued after the previous active row has been precharged (refer to the following figure). The minimum time interval between successive BankActivate commands to the same bank is defined by tRC(min.). The SDRAM has four internal banks on the same chip and shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back activation of the four banks. t different banks. After this command is used, the Write command and the Block Write command perform the no mask write operation.

(min.) specifies the minimum time required between activating

RRD

T0 T 1 T2 T3 Tn+3 Tn+4 Tn+5 T n+6

RCD

(min.)

CLK

ADDRESS

COMM A ND

Bank A

Row Addr.

Bank A

Activate

RAS# - CAS# delay (tRCD)

: "H" or "L"

BankActivate Command Cycle

2 BankPrecharge command

(RAS# = "L", CAS# = "H", WE# = "L", BAs = Bank, A10 = "L", A0-A9 and A11 = Don't care)

The BankPrecharge command precharges the bank disignated by BA signal. The precharged bank is switched from the active state to the idle state. This command can be asserted anytime after t

(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any

RAS

bank can be active is specified by t in any active bank within t state and is ready to be activated again.

3 PrechargeAll command

(RAS# = "L", CAS# = "H", WE# = "L", BAs = Don’t care, A10 = "H", A0 -A9 and A11 = Don't care)

The PrechargeAll command precharges all banks simultaneously and can be issued even if all banks are not in the active state. All banks are then switched to the idle state.

NOP

..............

NOP

Bank A

Col Addr.

R/W A with

AutoPrecharge

RAS# Cycle time (tRC)

..............

(Burst Length = n, CAS# Latency = 3)

(max.). Therefore, the precharge function must be performed

RAS

(max.). At the end of precharge, the precharged bank is still in the idle

RAS

Bank B

Row Addr.

Bank B

Activate

AutoPrecharge

Begin

RAS# - RAS# delay time (tRRD)

NOP

Bank A

Row Addr.

Bank A

Activate

4 Read command

(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "L", A0-A7 = Column Address)

The Read command is used to read a burst of data on consecutive clock cycles from an active row in an active bank. The bank must be active for at least t issued. During read bursts, the valid data-out element from the starting column address will be available following the CAS# latency after the issue of the Read command. Each subsequent dataout element will be valid by the next positive clock edge (refer to the following figure). The DQs go into high-impedance at the end of the burst unless other command is initiated. The burst length, burst sequence, and CAS# latency are determined by the mode register, which is already programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue).

222324252627282930

(min.) before the Read command is

RCD

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