Datasheet U2896B Datasheet (TEMIC)

查询U2896B-MFCG3供应商

Modulation PLL for GSM, DCS and PCS Systems

Description

The U2896B is a monolithic integrated circuit. It is realized using TEMIC’s advanced silicon bipolar UHF5S technology. The device integrates a mixer, an I/Q modulator, a phase-frequency detector (PFD) with two synchronous programmable dividers, and a charge pump. The U2896B is designed for cellular phones such as GSM900, DCS1800, and PCS1900, applying a transmitter architecture at which the VCO operates at the TX output frequency. No duplexer is needed since the

out-of-band noise is very low. The U2896B exhibits low power consumption. Broadband operation gives high flexibility for multi-band frequency mappings. The IC is available in a shrinked small-outline 36-pin package (SSO36).

Electrostatic sensitive device. Observe precautions for handling.

U2896B

Features

D

Supply voltage range 2.7 V to 5.5 V

D

Current consumption 50 mA

D

Power-down functions

D

High-speed PFD and charge pump (CP)

D

Small CP saturation voltages (0.5/0.6 V)

D

Programmable dividers and CP polarity

D

Low-current standby mode

Block Diagram

I NI Q NQ PU NMIXOMIXO

56

MDLO

NMDLO

MDO

NMDO

VS1 GND1

3 4

7 8

90°

Modulator

LO

Benefits

D

Novel TX architecture saves filter costs

D

Extended battery operating time without duplexer

D

Less board space (few external components)

D

VCO control without voltage doubler

D

Small SSO36 package

D

One device for all GSM bands

PUMIXMIXLO

23353621

V

32 33

Ref

34 25

Mixer

24

31 29

28 30

NMIXLO VS3

RF NRF

GND3

ND

NND

RD

NRD

22 21

15 16

N

1:2

MUX

R

1:2

Mode control

17

MC GND2

PFD

27

VS2

Figure 1. Block diagram

Charge

pump

26

CPCL CPCH

1413

10

11

12

14891

VSP

CPO

GNDP

Rev . A1, 18-Sep-98 1 (13)

Preliminary Information

U2896B

Á

Ordering Information

Extended Type Number Package Remarks

U2896B-MFCG3 SSO36 T aped and reeled

Pin Description

NI

MDLO

NMDLO

GND1

VSI

MDO

NMDO

SUB

VSP

CPO

GNDP

CPCL

CPCH

RD

NRD

MC

n.c.

I

1

2

3

4

5

1)

6

7

8

9

10

11

12

13

14

15

16

17

18 19

Figure 2. Pinning

14892

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

Q

NQ

PUMIX

MIXO

NMIXO

1)

VS3

GND3

RF

NRF

1)

VS2

GND2

MIXLO

NMIXLO

PU

ND

NND

n.c.

Pin Symbol Function

1 2 3 4 5 6 7 8

9 10 11 12 13

I

NI

MDLO

NMDLO

GND1

1)

VS1

MDO

NMDO

SUB VSP CPO

GNDP

CPCL

In-phase base band-input Complementary to I I/Q-modulator LO input Complementary to MDLO Ground Supply I/Q modulator I/Q modulator Complementary to MDO Substrate, connected to GND Supply charge pump Charge pump output Ground Charge pump current control

GSM1800

14

Á

15 16 17 18 19 20 21 22 23

Á

24 25 26 27 28 29 30 31 32 33 34 35 36

CPCH

ÁÁ

RD

NRD

MC n.c. n.c. n.c.

NND

ND

PU

ÁÁ

NMIXLO

MIXLO

GND2

1)

VS2

NRF

RF

GND3

1)

VS3

NMIXO

MIXO

PUMIX

NQ

Q

Charge pump current control

БББББББББ

GSM900 R-divider input Complementary to RD Mode control Not connected Not connected Not connected Complementary to ND N-divider input Power-up. whole chip, except

mixer

БББББББББ

Complementary to MIXLO Mixer LO input Ground Supply (MISC) Complementary to RF Mixer RF input Ground Supply mixer Complementary to MIXO Mixer output Power-up mixer Complementary to Q Quad-phase base-band input

1)

Between the Pins VS1, VS2 and VS3 the allowed maximum voltage is ≤ 200 mV

Preliminary Information

Rev . A1, 18-Sep-982 (13)

Absolute Maximum Ratings

ÁÁÁ

pp y

ÁÁÁ

pp y

ÁÁÁ

pp y

ÁÁÁ

Á

1)

Á

ÁÁÁ

Á

ÁÁÁ

Parameters Symbol Value Unit Supply voltage VS1, VS2, VS3 Supply voltage charge pump VSP Voltage at any input Current at any input / output pin

except CPC CPC output currents Ambient temperature Storage temperature

Operating Range

Parameters Symbol Value Unit Supply voltage Supply voltage Ambient temperature

Thermal Resistance

Parameters Symbol Value Unit Junction ambient SSO36

V

VS#

V

VSP

V

Vi#

| II# | | IO# |

| I

|

CPC

T

amb

T

stg

V

VS#

V

VSP

T

amb

R

thJA

–0.5 v V

–40 to +125

v

V

VSP

5.5 v V

Vi#

2

5

–20 to +85

2.7 to 5.5

–20 to +85

130

U2896B

+5.5

VS#

mA

°C °C

°C

K/W

V V V

V V

Electrical Characteristics

VS = 2.7 to 5.5 V, T

Parameters T est Conditions / Pin Symbol Min. T yp. Max. Unit

DC supply

Supply voltages VS# Supply voltage VSP Supply current I

Supply current I

ББББББ

N & R divider inputs ND, NND & RD, NRD

N:1 divider frequency R:1 divider frequency Input impedance Input sensitivity Input capacitance

= –20°C to +85°C, final test at 25°C

amb

V

VS1

= V

VS1

Active (VPU = VS)

VS2

= V

Standby (VPU = 0)

VS2

Active (VPU = VS) Standby (VPU = 0)

VS3

VSP

Active (V Standby (V

PUMIX

Active (V

= VS, CPO open)

PU

БББББББ

Standby (VPU = 0)

50-W source 50-W source Active & standby 50-W source Active & standby

VS3

= VS)

= 0)

V

VS#

V

VSP

I

VS1A

I

VS1Y

I

VS2A

I

VS2Y

I

VS3A

I

VS3Y

I

VSPA

ÁÁÁ

I

VSPY

f

ND

f

RD

ZRD, Z

ND

VRD, V

CRD, C

ND

2.7

V

– 0.3

VS#

ÁÁÁ

100 100

1

2)

5

17

13

1.4

Á

5.5

5.5 22 20 22 20 17 30

1.8

ÁÁ

20

600 600

200

0.5

V V

mA

m

A

mA

m

A

mA

m

A

mA

ÁÁ

m

A

MHz MHz

k

W

mV

rms

pF

1) Mean value, measured with FND = 151 MHz, FRD = 150 MHz, current vs. time, see page 6, figure 3

2) For optimized noise performance this voltage level may be higher

Rev . A1, 18-Sep-98 3 (13)

Preliminary Information

U2896B

Á

Electrical Characteristics (continued)

VS = 2.7 to 5.5 V, T

Parameters T est Conditions / Pin Symbol Min. T yp. Max. Unit

Phase-frequency detector (PFD)

PFD operation

ББББББ

Frequency comparison

4)

only

I/Q modulator baseband inputs I, NI & Q, NQ

DC voltage

ББББББ

MD_IQ AC voltage

5)

AC voltage

I/Q modulator LO input MDLO

MDLO Input impedance Input level I/Q modulator outputs MDO, NMDO DC current Internal pull-up resistor Voltage compliance MDO output level

ББББББ

(differential) Carrier suppression Sideband suppression IF spurious

Noise

6)

Frequency range

Mixer (900 MHz)

RF input level Output resistance LO-spurious at

RF/NRF port

ББББББ

MIXLO input level MIXO Output level 7) differen-

ББББББ

tial Carrier suppression

= –20°C to +85°C, final test at 25°C

amb

fND = 600 MHz, N = 2

ББББББ

fRD = 600 MHz, R = 2 fND = 600 MHz, N = 2

f

= 450 MHz, R = 2

RD

Referred to GND

ББББББ

Frequency range Referred to GND

Differential (preferres)

Frequency range Active & standby 50-W source

V

, V

MDO

V

, V

MDO

615 W to VS

ББББББ

1.5 pF external load

NMDO

6)

= VS

= VC

6)

fLO ± 3 f

mod

@ 400 kHz off carrier

900 MHz

@ P9 @ P9

ББББББ

= –10 dBm

MIXLO

= –15 dBm

RF

0.05 to 2 GHz Frequency range @ P9

ББББББ

@ P9

MIXLO

= –15 dBm

f

V

R

V

I,

AC

I

MDO MDO MDO

CS

MIXO

P9

CS9

PFD

f

FD

V

NI,

Q,

f

IO

AC

I,

Q, ACNQ

AC

DI,

f

MDLO

Z

MDLO

P

MDLO

, I

NMDO

, R

NMDO

, VC

P

MDO

SS

MDO

SP

MDO

N

MDO

f

MDO

P9

RF

, R

NMIXO

SP9

RF

MIXLO

f

MIXO

V

NQ

NI,

DQ

NMDOVS

БББББ

VC

БББББ

50

Á

ÁÁÁÁÁ

300

400

1.35

Á

0

VS1/2

ÁÁ

VS1/2

ÁÁ

+ 0.1

1

200

400

100

450

3

–14

–11

–5

0.8

615 – 0.7 40

Á

–32 –35

ÁÁÁÁÁ

–35

–40

–50

5.5 60

–45

–115

100

–23

450

–17

650

–40

ÁÁÁÁÁÁÁ

–22

50

ÁÁÁÁ

80

–12 450

ÁÁÁÁÁ

–20

MHz

ÁÁ

MHz

V

ÁÁ

MHz

mV

pp

mV

pp

MHz

k

W

dBm

mA

W

V

mV

rms

ÁÁ

dBc dBc dBc

dBc/Hz

MHz

dBm

W

dBm

ÁÁ

dBm MHz

mV

rms

dBc

4)

PFD can be used as a frequency comparator until 300 MHz for loop acquisition

5)

Single-ended operation (complementary baseband input is AC-grounded) leads to reduced linearity (degrading suppression of odd harmonics)

6)

With typical drive levels at MDLO- & I/Q-inputs

7)

–1 dB compression point C = 1.5 pF to GND

Preliminary Information

Rev . A1, 18-Sep-984 (13)

Electrical Characteristics (continued)

Á

pp

Á

VS = 2.7 to 5.5 V, T

Parameters Test Conditions / Pin Symbol Min. Typ. Max. Unit

Mixer (1900 MHz)

Output resistance RF input level LO-spurious at

RF/NRF ports

ББББББ

MIXLO input level MIXO Output level 8) differen-

ББББББ

tial Carrier suppression

Charge-pump output CPO (V

Pump-current pulse

Sensivity to V

ББББББ

V

voltage range

CPO

ББББББ

VSP

Mode control

Sink current Power-up input PU (power-up for all functions, except mixer) Settling time

ББББББ

High level Low level High-level current Low-level current

Power-up input PUMIX (power-up for mixer only)

Settling time

ББББББ

High level Low level High-level current Low-level current

= –20°C to +85°C, final test at 25°C

amb

0.5 to 2 GHz @ P19

@ P19RF = –15 dBm

ББББББ

MIXLO

= –10 dBm

0.05 to 2 GHz

@ P19

ББББББ

@ P19

VSP

R

CPCH

R

CPCL

D

I

CPO

|

I

CPO

| I

CPO

ББББББ

10%

ББББББ

(V

VSP

= –17 dBm

MIXLO

= –17 dBm

MIXLO

= 5 V; V

9)

= 4.7 kΩ

10)

= 2.4 kΩ

||

CPO

D

V

| degradation <

= 2.7 V to 5 V)

= 2.5 V)

VSP

VMC = VS

Output power within 10%

ББББББ

of steady state values Active Standby Active, V Standby , V

Output power within 10%

ББББББ

of steady state values

PUH

PUL

= 2.2 V

= 0.4 V

Active Standby Active, V

PUMIXH

= 2.2 V

Standby , V

PUMIXL

= 0.4 V

R

MIXO

ÁÁÁÁ

P19

ÁÁÁÁ

CS19

| I

ÁÁÁÁ

|

ÁÁÁÁ

V V

I I

, R

P19

RF

SP19

MIXLO

MIXO

CPO_H CPO_L

S

ICPO

V

CPO

I

MC

S

PU

V

PUH

V

PUL

I

PUH

I

PUL

t

setl

PUMIXH

PUMIXL

PUMIXH

PUMIXL

NMIXO

RF

| |

U2896B

650

–23

ÁÁÁÁÁÁÁÁ

–22

70

ÁÁÁÁÁ

–20

1.4 3

ÁÁÁÁÁÁÁÁ

0.5

ÁÁ

2 4

ÁÁ

60

ÁÁÁÁÁ

5

2.0 0

–1

ÁÁÁÁÁ

5

2.0 0

0.1

–1

–17 –40

–12

ÁÁÁÁÁ

2.6 5

0.1

V

–0.6

VSP

ÁÁ

10

ÁÁ

0.4

70 20

10

ÁÁ

0.4

70 20

W

dBm dBm

ÁÁ

dBm

mVrms

dBc

mA mA

–

ÁÁ

V

ÁÁ

m

A

m

s

ÁÁ

V V

m

A

m

A

m

s

ÁÁ

V V

m

A

m

A

8)

9)

10)

Rev . A1, 18-Sep-98 5 (13)

– 1 dB compression point C = 1.5 pF to GND R

: external resistor to GND for charge-pump current control (MODE 1, 5, only Pin 14 active)

CPCH

R

: external resistor to GND for charge-pump current control (MODE 2, 3, 4, only Pin 13 active)

CPCL

Preliminary Information

U2896B

Supply Current of the Charge Pump I

Due to the pulsed operation of the charge pump, the current into the charge-pump supply pin VSP is not constant. Depending on I (see figure 5) and the phase difference at the phase detector inputs, the current I over time varies. Basically, the total current is the sum of the quiescent current, the charge-/discharge current, and – after each phase comparison cycle – a current spike (see figure 3).

Internal current |I

R

CPC

19.2 k

W

9.6 k

W

4.8 k

W

2.4 k

W

CPC

| vs. R

CPC

|I

CPCO

0.5 mA 1 mA 2 mA 4 mA

|

(typical values)

VSP

vs. Time

VSP

I

VSP

I

CPO

Up

Down

2.5 I

CPCO

1.5 I

CPCO

I

CPCO

–I

CPCO

Figure 3. Supply current of the charge pump

t

14913

Mode Selection

The device can be programmed to different modes via an external resistor RMODE (including short, open) from Pin MC to VS2. The mode is distinguished from specific N-, R-divider ratios, and the polarity of the charge-pump selection.

Mode Selection N-Divider R-Divider CPO Current Polarity

Mode Resistance

fn < fR

1)

fn > fR between Pin MC and Pin VS2

1 0 (<50 W) 1:1 1:1 sink source t.b.d. x 2 2.7 kW (±5%) 1:1 1:1 source sink t.b.d. x 3 10 kW (±5%) 1:1 2:1 source sink t.b.d. x 4 47 kW (±5%) 2:1 2:1 source sink PCN/ PCS 5 ∞ (> MW) 2:1 2:1 sink source GSM

1)

Frequencies referred to PFD input

2)

LO frequencies below VCO frequency

3)

LO frequencies above VCO frequency

4

) Sink current into Pin CPO. Source: current out from Pin CPO.

4)

Application CPCH

1)

3)

CPCL

active

2)

active

x

Preliminary Information

Rev . A1, 18-Sep-986 (13)

Equivalent Circuits at the IC’s Pins

I,Q

MDLO

NI, NQ

V

Bias_MDLO

U2896B

2 x 615

W

VS1

MDO NMDO

2230 Ω2230 Ω

V

Ref_input

V

Ref_MDLO

V

Baseband inputs LO input Output

Figure 4. I/Q modulator

RF

1 kΩ

V

Bias_RF

890 Ω 890 Ω

1 kΩ

V

Bias_LO

1.6 kΩ 1.6 kΩ

650

W

NMIXO

NRF

RF input

V

Ref_RF

MIXLO

V

Ref_LO

LO output

Figure 5. Mixer

Ref_output

Output

650

GND

14893

VS3

W

MIXO

GND

14894

4

VSP

4

I

CPO

I

GNDP

14896

CPCL

CPCH

up

Ref

V

Ref

n

= Transistor with an emitter area–factor of “n”

n

Ref

n

down

Figure 6. Charge pump

Rev . A1, 18-Sep-98 7 (13)

Preliminary Information

U2896B

ND/RD

VS2

NND/NRD

VS2

MC

Figure 7. Dividers

2x

60 µA

2 kΩ 2 kΩ

V

Ref_div

Logic

GND

14897

N–divider

R–divider

MUX

PU, PUMIX

20 kΩ

Figure 8. Power-up

C (U) is a non-linear junction capacitance

Figure 10. ESD-protection diodes

GND

14899

≅

C (U)

0.5 pF @ 2 V

14900

GND

14898

Figure 9. Mode control

Rev . A1, 18-Sep-988 (13)

Preliminary Information

Application Hints

Interfacing

For some of the baseband ICs it may be necessary to reduce the I/Q voltage swing so that it can be handled by the U2896B. In those cases, the following circuitry can be used.

Mode Control

U2896B

R1

II

R1

Baseband IC

Figure 11. Interfacing the U2896B to I/Q baseband circuits

NI

Q

R1

NQ

R1

R2

C

NI

U2896B

Q

C

NQ

14901

Due to a possible current offset in the differential baseband inputs of the U2896B the best values for the carrier suppression of the I/Q modulator can be achieved with voltage driven I/NI-, and Q/NQ-inputs. A value of R

= R2/2*RS v 1.5 kW should be realized. RS is the

source

sum of R1 (above drawing) and the output resistance of the baseband IC.

VS2

R

Mode

R

Mode1RMode2

MC

a) any single mode b) any 2 modes

U2896B

VS2

R

Mode

R

Mode

MC

c) any mode & mode 5

Figure 12. Application examples for programming

d) mode 5 & mode 3 or mode 4

different modes

36 kΩor 10 kΩ

VS2

MC

U2896B

VS2

MC

14895

Rev . A1, 18-Sep-98 9 (13)

Preliminary Information

U2896B

Test Circuit

V4

1.35V

200MHz

–10dBm

3V, 5V

200.1MHz –15dBm

3V

1.5V

V7

R1

R2

R5

R6

R3

R4

R7

V5

450 mV

C1

C2

C5

C6

pp

C4

C3

10

11

12

13

14

15

16

1

2

3

4

5

6

7

8

9

U2896B

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

V2

450 mV

C14

C16

C7

C8

C10

C11

C13

C15

R11

pp

V3

R12

C9

C12

R13

R14

1.35V

3V

900MHz

–15dBm

3V

1100MHz

–15dBm

3V

200MHz

–15dBm

3V

R8

R9

R10

n.c.

17

n.c.

18 19

Figure 13. Test circuit

20

n.c.

14903

Preliminary Information

Rev . A1, 18-Sep-9810 (13)

Application Circuit for DCS1800 (1710 – 1785 MHz)

U2896B

Baseband

2nd LO

–10dBm

3V

R1

R2

3V, 5V

Tuning voltage

R4

C7

C8

C9

C10

R3

C6

R9

R8

R10

C13

VCO

880 to 915MHz

1710 to 1785MHz

–20dBm

Baseband

3V

C4

C2

C3

C1

1

2

3

4

5

6

7

8

9

36

35

34

33

32

31

30

29

28

C12

C14

C15

U2896B

10

C5

11

12

13

R5

14

R6

15

L2L1

C11

16

27

26

25

24

23

22

21

C17

C18

C19

C20

C16

L3

3V

1st LO

–15dBm

3V

C29

3V

Measurements

R7

17

n.c.

18 19

Figure 14. Application circuit

Modulation Spectrum & Phase Error

14904

20

n.c.

CPC: 1 kΩ to GND

Modulation-Loop Settling Time

As valid for all PLL loops the settling time depends on several factors. The following figure is an extraction from measurements performed in an arrangement like the application circuit. It shows that a loop settling time of a few ms can be achieved.

Vertical: VCO tuning voltage 1 V/Div Horizontal: Time 1 ms/Div

Rev . A1, 18-Sep-98 11 (13)

CPC ‘open’

Preliminary Information

U2896B

Package Information

Package SSO36

Dimensions in mm

0.2

0.5

36 19

118

9.6

9.1

8.45

1.3

0.15

0.05

technical drawings according to DIN specifications

5.6

5.2

4.5

4.3

0.12

6.6

6.3

13047

Preliminary Information

Rev . A1, 18-Sep-9812 (13)

U2896B

Ozone Depleting Substances Policy Statement

It is the policy of TEMIC Semiconductor GmbH to

1. Meet all present and future national and international statutory requirements.

2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment.

It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs).

The Montreal Protocol ( 1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances.

TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents.

1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively

2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA

3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.

TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.

We reserve the right to make changes to improve technical design and may do so without further notice.

Parameters can vary in different applications. All operating parameters must be validated for each customer

application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized

application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of,

directly or indirectly, any claim of personal damage, injury or death associated with such unintended or

unauthorized use.

TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany

T elephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423

Rev . A1, 18-Sep-98 13 (13)

Preliminary Information

Datasheet U2896B Datasheet (TEMIC)

Specifications and Main Features

Frequently Asked Questions

User Manual