ATMEL ATxmega64A3, ATxmega256A3, ATA5746-PXQW, ATA5745 Datasheet
Features
• High-performance, Low-power AVR 8/16-bit XMEGA Microcontroller
• Non-volatile Program and Data Memories
– 64K/128K/192K/256K Bytes of In-System Self-Programmable Flash
– 4K/8K/8K/8K Boot Code Section with Independent Lock Bits
– 2K/2K/4K/4K Bytes EEPROM
– 4K/8K/16K/16K Bytes Internal SRAM
• Peripheral Features
– Four-channel DMA Controller with support for external requests
– Seven 16-bit Timer/Counters
4 Timer/Counters with 4 Output Compare or Input Capture channels
3 Timer/Counters with 2 Output Compare or Input Capture channels
High Resolution Extensions on all Timer/Counters
Advanced Waveform Extension on 1 Timer/Counters
– Seven USARTs
IrDA Extension on 1 USART
– AES Crypto Engine
– DES Crypto Engine
– Two 2-wire Interfaces (I
– Four SPIs (Serial Peripheral Interfaces)
– 16-bit Real Time Counter with Separate Oscillator
– Two Eight-channel, 12-bit, 2 Msps ADCs
– One Two-channel, 12-bit, 1 Msps DAC
– Four Analog Comparators
– External Interrupts on all General Purpose I/O pins
– Programmable Watchdog Timer with Separate On-chip Oscillator
• Special Microcontroller Features
– Power -on Reset and Programmable Brown-out Detection
– Internal and External Clock Options with PLL
– Programmable Multi-level Interrupt Controller
– Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby
– Advanced Programming, Test and Debugging Interfaces
JTAG (IEEE 1149.1 Compliant) Interface f or test, debug and programming
PDI (Program and Debug Interface) for programming, test and debugging
• I/O and Pac kages
– 50 Programmable I/O Lines
– 64-lead TQFP
– 64-pad MLF
• Operating Voltage
– 1.8 – 3.6V
• Speed performance
– 0 – 12 MHz @ 1.8 – 2.7V
– 0 – 32 MHz @ 2.7 – 3.6V
2
C and SMBus compliant)
8/16-bit
XMEGA
Microcontroller
ATxmega256A3
ATxmega192A3
ATxmega128A3
ATxmega64A3
Advance
Information
Typical Applications
• Industrial control • Climate control • Hand-held battery applications
• Factory automation • ZigBee • Power tools
• Building control • Motor control • HVAC
• Board control • Networking • Metering
• White Goods • Optical • Medical Application
8068A–AVR–02/08
1. Block Diagram/Pinout
ATxmega A3
BAT
INDEX CORNER
AC3/ACD3/PA3
AC4/ADC4/PA4
AC5/ADC5/PA5
AC6/ADC6/PA6
AC7/ADC7/PA7
AREF/AC0/ADC0/ADC8/PB0
AC1/ADC1/ADC9/PB1
DAC0/AC2/ADC2/ADC10/PB2
DAC1/AC3/ADC3/ADC11/PB3
TMS/AC4/ADC4/ADC12/PB4
TDI/AC5/ADC5/ADC13/PB5
TCK/AC6/ADC6/ADC14/PB6
TDO/AC7/ADC7/ADC15/PB7
GND
VCC
SDA/OC0A/_OC0A/PC0
PA2/ADC2/AC2
PA1/ADC1/AC1
PA0/ADC0/AC0/AREF
AVCC
GND
PR1/XTAL1
PR0/XTAL2
PDI_CLK/RESET
PDI_DATA/TEST
PF7
PF6
VCC
646362616059585756555453525150
1
2
3
4
5
6
7
8
9
10
11
12
13
ADC A
DAC A
A
Por t
AC A0
AC A1
ADC B
DAC B
B
Por t
AC B0
AC B1
Por t R
OSC/CLK
Control
Powe r
Control
Reset
Control
Watchdog
EVENT ROUTING NETWORK
DATA BU S
VREF
BOD POR
TEMP
RTC
FLASH
CPU
DMA
Interrupt Controller
Event System ctrl
DATA BU S
RAM
E2PROM
14
15
16
T/C0:1
USART0:1
SPI
TWI
Port C Port D Port E Port F
T/C0:1
USART0:1
SPI
T/C0:1
USART0:1
TWI
SPI
171819202122232425262728293031
GND
PF5/VCC
OCD
T/C0:1
PF4
PF3/OC0D/TXD0
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
SPI
34
USART0:1
33
32
PF2OC0C/RXD0
PF1/OC0B/XCK0
PF0/OC0A
GND
VCC
PE7/SCK/TXD1/TOSC1
PE6/MISO/RXD1/TOSC2
PE5OC1B/MOSI/XCK1
PE4OC1A/_SS
PE3/OC0D/TXD0
PE2OC0C/RXD0
PE1/OC0B/XCK0/SCL
PE0/OC0A/SDA
GND
VCC
PD7/SCK/TXD1
8068A–AVR–02/08
VCC
GND
_SS/OC1A/OC0C/PC4
RXD0/OC0C/_OC0B/PC2
TXD0/OC0D/D/OC0B/PC3
TXD1/SCK/OC0D/PC7
RXD1/MISO/_OC0D/PC6
SCL/XCK0/OC0B/OC0A/PC1
XCK1/MOSI/OC1BB/OC0C/PC5
OC0A/PD0
XCK0/OCB0PD1
TXD0/OCD0/PD3
RXD0/OC0C/PD2
_SS/OC1A/PD4
RXD1/MISO/PD6
XCk1/MOSI/OC1B/PD5
2
ATxmega A3
2. Ordering Information
For packaging information, see ”Packaging information” on page 53.
64A
64M1
(1)(2)
Temp
-40° - 85°C
Ordering Code Flash (B) E2 (B) SRAM (B) Speed (MHz) Power Supply Package
ATxmega256A3-AU 256K + 8K 4K 16K 32 1.8 - 3.6V
ATxmega192A3-AU 192K + 8K 4K 16K 32 1.8 - 3.6V
ATxmega128A3-AU 128K + 8K 2K 8K 32 1.8 - 3.6V
ATxmega64A3-AU 64K + 4K 2K 4K 32 1.8 - 3.6V
ATxmega256A3-MU 256K + 8K 4K 16K 32 1.8 - 3.6V
ATxmega192A3-MU 192K + 8K 4K 16K 32 1.8 - 3.6V
ATxmega128A3-MU 128K + 8K 2K 8K 32 1.8 - 3.6V
ATxmega64A3-MU 64K + 4K 2K 4K 32 1.8 - 3.6V
Notes: 1. This device can also be supplied in wafer f orm. Please contact your local Atmel sales office for detailed ordering information.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
64A
64M1
8068A–AVR–02/08
Package Type
64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)
3
3. Disclaimer
4. Overview
ATxmega A3
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured o n th e same proce ss te ch nolo gy. Min a nd Ma x valu es
will be available after the device is characterized.
The XMEGA A3 is a family of low power, high performance and peripheral rich CMOS 8/16-bit
microcontrollers based on the AVR
instructions in a single clock cycle, the XMEGA A3 achieves throughputs approaching 1 MIPS
per MHz allowing the system designer to optimize power co nsumption versus pr ocessing speed.
5. Resources
A comprehensive set of development tools, application notes, and datasheets are available for
download on http://www.atmel.com.
5.1 Recommended reading
• XMEGA A Manual
• Application Notes
This document contains part specific information only. The XMEGA A Manual describes the
peripherals in-depth. The application notes contain example code and show applied use of the
peripherals.
®
enhanced RISC architecture. By executing powerful
8068A–AVR–02/08
4
6. AVR CPU
6.1 Features
6.2 Overview
ATxmega A3
• 8/16-bit high performance AVR RISC Architecture
– 139 instructions
– Hardware multiplier
• 32x8-bit registers directly connected to the ALU
• Stack in RAM
• Stack Pointer accessible in I/O memory space
• Direct addressing of up to 16M bytes of program and data memory.
• True 16/24-bit access to 16/24-bit I/O registers
• Support for 8-, 16- and 32-bit Aritmetic’s
• Configuration Change Protection of system critical features.
The XMEGA A3 uses an 8/16-bit AVR CPU. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform
calculations and control peripherals. Interrupt handling is described in a separate section. Figure
6-1 on page 5 shows the CPU block diagram.
Figure 6-1. CPU block diagram
DATA BUS
Program
Counter
Indirect Addressing
32 x 8 General
Purpose
Registers
FLASH
Program
Memory
SRAM
Data
ALU
Dir ec t Addr essing
Instruction
Register
PERIPHERAL
MODULE 1
PERIPHERAL
MODULE n
The AVR uses a Harvard architecture - with separate memories and buses for program and
data. Instructions in the program memory are executed with a single level pipeline. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This
concept enables instructions to be executed in every clock cycle. The pr ogram memory is InSystem Re-programmable Flash mem o ry.
Instruction
Decoder
DATA BUS
STATUS/
CONTROL
EEPROMI/O LINES
PMIC
8068A–AVR–02/08
5
6.3 Register File
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File - in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing - enabling efficient address calculations. One of these add ress pointers can
also be used as an address pointer for look up tables in Flash program memory.
6.4 ALU - Arithmetic Logic Unit
The high performance Arithmetic Logic Unit (ALU) supports arithmetic and logic operations
between registers or between a constant and a register. Single register operations can also be
executed in the ALU. Within a single clock cycle, arithmetic operations between genera l purpose
registers or between a register and an immediate are executed. Aft er an arithmetic or logic operation, the Status Register is updated to reflect information about the result of the operation.
The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Both 8-, 16 and 32-bit arithmet ic is supp orted. Th e ALU als o provide a powerfu l multiplier
supporting both signed/unsigned multiplication and fractional format.
ATxmega A3
6.5 Program Flow
Program flow is provided by conditional and unconditional jump and call instructions, able to
address the whole address space directly. Most AVR instructions use a 16-bit word format.
Some instructions also use a 32-bit format.
The Program Flash memory space is divided in two sections, the Boot section and the Application section. Both sections have dedicated Lock bits for write and read/write protection. The
Store Program Memory (SPM) instruction used to access the Application section must reside in
the Boot section.
A third section exists inside the Application section. This section, the Application Table section,
has separate Lock bits for write and read/write protection. The Application Table section can be
used for storing non-volatile data or application software.
The Program Counter (PC) addresses t he locat ion fr om wh ere t he instru ction s are f etched . Af ter
a reset, the PC is set to location ‘0’.
During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequent ly the Stack size is o nly limited
by the total SRAM size and the usage of the SRAM. The Stack Pointer (SP) is default reset to
the highest address of the internal SRAM. The SP is read/write accessible in the I/O space. The
data SRAM can easily be accessed through the five dif ferent addr essing modes support ed in the
AVR architecture.
8068A–AVR–02/08
6
7. Memories
7.1 Features
7.2 Overview
ATxmega A3
• Flash Program Memory
– One linear address space
– In-System Reprogrammable
– Self-Programming and Bootloader support
– Application Section fo r application code
– Application Table Section for application code or data storage
– Bootloader Section for application code or bootloader code
– Separate lock bits and protection for all sections
• Data Memory
– One linear address space
– Single cycle access from CPU
– SRAM
– EEPROM
Byte or page accessible
Optional memory mapping for direct Load/Store
– I/O Memory
Configuration and Status register for all peripherals and modules
16 bit accessible General Purpose Register for global variable or flags
– External Memory
– Bus arbitration
Safe and deterministic handling of CPU and DMA Controller priority
– Separate buses for SRAM, EEPROM, IO Memory and External Memory access
• Enables simulatiouns bus access for CPU and DMA Controller
The AVR architecture has two main memory spaces, the Program Memory and the Data Memory. In addition, the XMEGA A3 features an EEPROM Memory for non-volatile data storage. All
three memory spaces are linear and require no pagi ng. The memory conf igurations are shown in
”Ordering Information” on page 3.
Non-volatile memory spaces can be locked for further write and read/write operations. This prevents unrestricted access to the application software.
7.3 In-system Programmable Flash Program Memory
The XMEGA A3 contains On-chip In-System Re-programmable Flash memory for program storage, see Table 7-1 on page 8. Since all AVR instructions are 16- or 32-bits wide, each Flash
address location is 16 bits.
The XMEGA A3 has additional Boot section for bootloader applications. The Store Program
Memory (SPM) instruction used to write to the Flash will only operate from this section. Operation of the SPM is also associated with Boot Lock bits for software protection.
The XMEGA A3 has an Application Table section inside the Application section for storage of
Non-volatile data.
8068A–AVR–02/08
7
Figure 7-1. Flash Program Memory (Hexadecimal address)
Word Address
ATxmega A3
The Application Table- and Boot sections can also be used for general application software.
7.4 SRAM Data Memory
The XMEGA A3 has internal SRAM memory for data storage. The Memory Map for the devices
in the family resemble each other, see Table 7-2 on page 8.
7.5 EEPROM Data Memory
The XMEGA A3 has internal EEPROM memory for non-volatile data storage. It is addressable
either in a separate data space or it can be memory mapped the normal data space. The
EEPROM memory supports both byte and page access.
The Internal SRAM and EEPROM memory spaces start at the same address in all devices, see
Table 7-2 on page 8. The Reserved memory space is empty.
1EFFF / 16FFF / EFFF / 77FF
1F000 / 17000 / F000 / 7800
1FFFF / 17FFF / FFFF / 7FFF
20000 / 18000 / 10000 / 8000
20FFF / 18FFF / 10FFF / 87FF
0
Application Section
(256K/192K/128K/64K)
...
Application Table Section
(8K/8K/8K/4K)
Boot Section
(8K/8K/8K/4K)
Figure 7-2. Data Memory Map (Hexadecimal address)
Byte Address ATxmega192A3 Byte Address ATxmega128A3 Byte Address ATxmega64A3
1000
1FFF
2000
5FFF 3FFF 2FFF
6000
FFFFFF FFFFFF FFFFFF
8068A–AVR–02/08
0
FFF FFF FFF
I/O Registers
(4KB)
EEPROM
(4K)
Internal SRAM
(16K)
External Mempry
(0 - 16 MB)
0
1000
17FF 17FF
2000
4000
I/O Registers
(4KB)
EEPROM
(2K)
RESERVED RESERVED
Internal SRAM
(8K)
External Mempry
(0 - 16 MB)
1000
2000
3000
0
I/O Registers
EEPROM
Internal SRAM
External Mempry
(0 - 16 MB)
(4KB)
(2K)
(4K)
8
ATxmega A3
Byte Address ATxmega256A3
0
FFF
1000
1FFF
2000
5FFF
I/O Registers
(4KB)
EEPROM
(4K)
Internal SRAM
(16K)
6000
FFFFFF
External Mempry
(0 - 16 MB)
8068A–AVR–02/08
9
7.6 I/O Memory
ATxmega A3
All XMEGA A3 I/Os and peripherals are addressable through I/O memory locations in the data
memory space. All I/O locations may be accessed by the LD/L DS/LDD and ST/STS/STD
instructions, transferring data between the 32 general purpose registers and the I/O memory.
IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F directly.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and
CBI instructions. The value of single bits can be checked by using th e SBIS and SBIC instructions in these registers.
The I/O space definition of the XMEGA A3 is shown in ”Peripheral Module Address Map” on
page 51.
8068A–AVR–02/08
10
8. DMA - Direct Memory Access Controller
8.1 Features
• Allows High-speed data transfer
– From memory to peripheral
– From memory to memory
– From peripheral to memory
– From peripheral to peripheral
• 4 Channels
• From 1 byte and up to 16 M bytes transfers in a single transaction
• Multiple addressing modes for source and destination address
–Incremental
– Decremental
– Static
• 1, 2, 4, or 8 bytes Burst Tra nsfers
• Programmable priority between channels
8.2 Overview
The XMEGA A3 has a Direct Memory Access (DMA) controller to move data between memories
and peripherals in the data space. The DMA controller uses the same data bus as the CPU to
transfer data.
ATxmega A3
The XMEGA A3 has 4 DMA channels that may be configured independently. The DMA controller supports transfer of up to 64K data blocks and can be configured to access memory with
incrementing, decrementing or static addressing.
Since the DMA can access all the peripherals through the I/O memory, the DMA may be used
for automatic transfer of data to/from communication modules, as well as automatic da ta
retrieval from ADC conversions or data transfer to DAC conversions.
The DMA controller can read from memory mapped EEPROM, but it cannot write to the
EEPROM or access the Flash.
8068A–AVR–02/08
11
9. Event System
9.1 Features
9.2 Overview
• Inter peripheral communication and signalling
• CPU and DMA independent operation
• 8 Event Channels allows for up to 8 signals to be routed at the same time
• Events can be generated by
– Timer/Counters (TCxn)
– Real Time Counter (RTC)
– Analog to Digital Converters (ADCx)
– Analog Comparators (ACx)
– Ports (PORTx)
– System Clock (Clk
– Software (CPU)
SYS
)
• Events can be used by
– TImer/Counters (TCxn)
– Analog to Digital Converters (ADCx)
– Digital to Analog Converters (DACx)
– Ports (PORTx)
– DMA Controller (DMAC)
• Advanced Features
– Manual Event Generation from software (CPU)
– Quadrature Decoding
– Digital Filtering
• Operative in Active and Idle mode
ATxmega A3
The Event System is a set of features for inter pe ripheral comm unication. It enable s the possibility for a change of state in one peripheral to automatically trigger actions in other pe ripherals.
What change of state in a peripheral that will trigger actions in other peripherals is configurable
in software. It is a simple, but powerful system as it allows for autonomous cont rol of per iph erals
without any use of interrupt, CPU or DMA resources
The indication of a change of state in a peripheral is referred to as an event. The events are
passed between peripherals using a dedicated ro uting network called the Event Routing Net work. Figure 9-1 on page 13 shows a basic block diagram of the Event System with the Event
Routing Network and the peripherals that are connected. The event system is no t a single enti ty,
but a set of features for inter peripheral communication. This highly flexible system can be used
for simple rerouting of signals, pin functions or for sequencing of events.
The event system is functional in both Active- and Idle mode.
8068A–AVR–02/08
12
Figure 9-1. Event system block diagram.
ATxmega A3
CPU
ADCx
DACx
PORTxn
The the event routing network can directly connect together ADCs, DACs, Analog Comparators
(AC), I/O ports (PORT), the Real-time Counter (RTC), and Timer/Counters (T/C). Events can
also be generated from software (CPU).
DMA IRCOM
RTC
Event
Routing Network
ACxn
T/Cxn
8068A–AVR–02/08
13
10. System Clock and Clock options
10.1 Features
• Fast start-up time
• Safe run time clock switching
• 4 Internal Oscillators; 32 MHz, 2 MHz, 32 kHz, 32 kHz Ultra Low Power (ULP)
• 0.4 - 16 MHz Crystal Oscillator, 32 kHz Crystal Oscillator, external clock
• PLL with internal and external clock options and 1 to 31x multiplication
• Clock Prescalers with 1 to 2048x division
• Fast peripheral clock.
• Automatic Run-Time Calibration of internal oscillators
• Crystal Oscillator failure detection
10.2 Overview
XMEGA A3 has an advanced clock system, supporting a lar ge numbe r of clo ck sources. It in corporates both integrated oscillators, and external crystal oscillators and resonators. A high
frequency Phase Locked Loop (PLL) and clock pr escalers can be controlled from software to
generate a wide range of clock frequencies. The clock distribution also enables the possibility to
switch between clock sources from software during run-time. A calibration feature (DFLL) is
available, and can be used for automatic run-time calibration of the internal oscillators. A Crystal
Oscillator Failure Monitor can be enabled to issue a Non-Maskable Interrupt and switch to internal oscillator if the external oscillator fails. Figure 10-1 on page 15 shows the principal clock
system in XMEGA A3.
ATxmega A3
8068A–AVR–02/08
14
Figure 10-1. Clock system overview
ATxmega A3
32 KHz ULP
Intern al Oscillator
32 KHz Calibrated
Intern al Oscillator
32 KHz
Crystal Oscillator
0.4 - 16 MHz
Crystal Oscillator
2 MHz
Run-time C a libra te d
Intern al Oscillator
CLOCK
CONTROL
UNIT
with PLL
WDT/BOD
RTC
PERIPHERALS
ADC
DAC
...
...
SYSTEM
CPU
DMA
INTERRUPT
...
32 MHz
Run-time C a libra te d
Intern al Oscillator
External
Clock Input
Each clock source is briefly described in the following sub-sections.
MEMORY
RAM
FLASH
EEPROM
...
8068A–AVR–02/08
15
10.3 Clock Options
10.3.1 32 kHz Ultra Low Power Internal Oscillator
The 32 kHz Ultra Low Power (ULP) Internal Oscillator is a very low power consumptio n clock
source based on internal components only. As it is intended mainly for system functions, it
should not be used when an accurate clock is required.
10.3.2 32 kHz Calibrated Internal Oscillator
Compared to the internal ULP oscillator, the 32 kHz Calibrated Internal Oscillator is a high accuracy clock source based on internal components only.
10.3.3 32 kHz Crystal Oscillator
The 32 kHz Crystal Oscillator is a low power driver for an external watch crystal.
10.3.4 0.4 - 16 MHz Crystal Oscillator
The 0.4 - 16 MHz Crystal Oscillator is a driver intended both for driving resonators and crystals
from 400 kHz to 16 MHz.
10.3.5 2 MHz Run-ti me Ca librat ed Interna l Os ci lla tor
ATxmega A3
The 2 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator based on internal components only. The oscillator can use the 32 kHz Calibrated Internal Oscillator or the 32
kHz Crystal Oscillator to calibrate the frequency run-time to compensate for temperature and
voltage drift, optimizing the accuracy of the oscillator.
10.3.6 32 MHz Run-time Calibrated Internal Oscillator
The 32 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator based on internal components only. The oscillator can use the 32 kHz Calibrated Internal Oscillator or the 32
kHz Crystal Oscillator to calibrate the frequency run-time to compensate for temperature and
voltage drift, optimizing the accuracy of the oscillator.
10.3.7 External Clock input
The external clock input gives the possibility to connect to a clock from an external source.
10.3.8 PLL with Multiplication factor 2 - 31x
The PLL provides the possibility of multiplying a frequency with any real number from 2 to 31. In
combination with some prescalers, this gives a numerous number of clock frequency options to
use.
8068A–AVR–02/08
16
11. Power Management and Sleep Modes
11.1 Features
• 5 sleep modes
–IDLE
– Power-down
–Power-save
–Standby
– Extended standby
• Power Reduction register to disable clock to un u sed peripheral
11.2 Overview
The XMEGA A3 provides various sleep modes tailored to reduce power consumption to a minimum. All sleep modes are accessible from Active mode. In Active mode the CPU is executing
application code. The application code decides when and what sleep mode to enter.
Various sources can restore the microcontroller from sleep to Active mode. This is called a
wake-up.
ATxmega A3
In addition Power Reduction Registers (PRR) provides a method to stop the clock to individual
peripherals from software. When this is done the current state of the peripheral is frozen and
there is no power consuption from the peripheral.
11.3 Sleep Modes
11.3.1 Idle Mode
In Idle mode the CPU and Non-Volatile Memory are stopped, but all peripherals including the
Interrupt Controller, Event System and DMA Controller are kept running.
Interrupt request from all enabled interrupts will wake the device.
11.3.2 Power-down Mode
In Power-down mode all system clock sources, including the Real Time Counter clock source
are stopped. This allows operation of asynchronous modules only. The only interrupts that can
wake up the MCU are the Two Wire Interface address match interrupts, and asynchronous port
interrupts.
11.3.3 Power-save Mode
Power-save mode is identical to Power-down, with one exception:
If the Real Time Counter (RTC) is enabled, it will keep running during sleep and the device can
also wake up from either RTC Overflow or Compare Match interrupt.
11.3.4 Standby Mode
8068A–AVR–02/08
Standby mode is identical to Power-down with the exception that the system clock sources are
kept running, while the CPU, Peripheral and RTC clocks are stopped. This r edu ces t he wake-up
time when external crystals or resonators are used.
17
11.3.5 Extended Standby Mode
Extended Standby mode is identical to Power-save mode with the exception that the system
clock sources are kept running while the CPU and Peripheral clocks are stopped. This reduces
the wake-up time when external crystals or resonators are used.
ATxmega A3
8068A–AVR–02/08
18
12. System Control and Reset
12.1 Resetting the AVR
During reset, all I/O Registers are set to their initial values. Application execution starts from the
Reset Vector. The instruction placed at t he Reset Vector should be a JMP - Absolute Jump instruction to the reset handling r outine. If the applic ation neve r enab les an int errupt sour ce, th e
Interrupt Vectors are not used. The regular application code can then be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt
Vectors are in the Boot section or vice versa.
The I/O ports of the AVR are immediately tri-stated when a reset source goes active.
The reset functionality is asynchronous, hence no running clock is required to reset the device.
12.2 Reset Sources
The reset source can be determined by the application by readig a reset status register. The
XMEGA A3 has the following sources of reset:
•
Power-on Reset
• External Reset
• Watchdog Reset
• Brown-out Reset
• JTAG AVR Reset
• PDI reset
• Software reset
ATxmega A3
12.2.1 Power-on Reset
The MCU is reset when the supply voltage VCC is below the Power-on Reset threshold voltage.
12.2.2 External Reset
The MCU is reset when a low level is present on the RESET pin.
12.2.3 Watchdog Reset
The MCU is reset when the Watchdog Timer period exp ires and the Wat chdog Reset is enable d.
12.2.4 Brown-out Reset
The MCU is reset when the supply voltage VCC is below the Brown-out Reset threshold voltage
and the Brown-out Detector is enabled.
12.2.5 JTAG AVR Reset
The MCU is reset as long as there is a logic one in the Reset Register, one of the scan chains of
the JTAG system. Refer to IEEE 1149.1 (JTAG) Boundary-scan for details.
12.2.6 PDI reset
The MCU may be reset through the Program and Debug Interface (PDI).
12.2.7 Software res et
8068A–AVR–02/08
The MCU may be reset by the CPU writing to a special I/O register.
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