Features
• Core
• Pin-to-pin compatible with AT91SAM7S legacy products (48- and 64-pin versions) and
ATSAM3S (48-, 64- and 100-pin version)
• Memories
• System
• Low Power Modes
• Peripherals
• I/O
• Packages
®
– ARM
–Thumb
– 24-bit SysTick Counter
– Nested Vector Interrupt Controller
– From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,
– From 8 to 24 Kbytes embedded SRAM
– 16 Kbytes ROM with embedded bootloader routines (UART) and IAP routines
– Embedded voltage regulator for single supply operation
– Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe
– Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure
– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default
– Slow Clock Internal RC oscillator as permanent low-power mode device clock
– One PLL up to 130 MHz for device clock
– Up to 10 peripheral DMA (PDC) channels
– Sleep and Backup modes, down to 3 µA in Backup mode
– Ultra low power RTC
– Up to 2 USARTs with ISO7816, IrDA
– Two 2-wire UARTs
– 2 Two Wire Interface (I2C compatible), 1 SPI
– Up to 6 Three-Channel 16-bit Timer/Counter with capture, waveform, compare and
– 4-channel 16-bit PWM
– 32-bit Real-time Timer and RTC with calendar and alarm features
– Up to 16 channels, 384 KSPS 10-bit ADC
– One 500 KSPS 10-bit DAC
– Up to 79 I/O lines with external interrupt capability (edge or level sensitivity),
– Three 32-bit Parallel Input/Output Controllers
– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm / 100-ball LFBGA, 9 x 9 mm, pitch 0.8 mm
– 64-lead LQFP, 12 x 12 mm, pitch 0.5 mm / 64-pad QFN 9x9 mm, pitch 0.45 mm
– 48-lead LQFP, 9 x 9 mm, pitch 0.5 mm / 48-pad QFN 7x7 mm, pitch 0.45 mm
Cortex®-M3 revision 2.0 running at up to 48 MHz
®
-2 instruction
single plane
operation
Detection and optional low power 32.768 kHz for RTC or device clock
frequency for device startup. In-application trimming access for frequency
adjustment
®
, RS-485 and SPI mode
PWM mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for
Stepper Motor
debouncing, glitch filtering and on-die Series Resistor Termination
AT91SAM
ARM-based
Flash MCU
SAM3N Series
Summary
NOTE: This is a summary document.
The complete document is available
under NDA. For more information,
please contact your local Atmel sales
office.
11011AS–ATARM–04-Oct-10
1. SAM3N Description
Atmel's SAM3N series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 48 MHz
and features up to 256 Kbytes of Flash and up to 24 Kbytes of SRAM. The peripheral set
includes 2x USARTs, 2x UARTs, 2x TWIs, 3x SPI, as well as 1 PWM timer, 6x general purpose
16-bit timers, an RTC, a 10-bit ADC and a 10-bit DAC.
The SAM3N series is ready for capacitive touch thanks to the QTouch library, offering an easy
way to implement buttons, wheels and sliders.
The SAM3N device is an entry-level general purpose microcontroller. That makes the SAM3N
the ideal starting point to move from 8- /16-bit to 32-bit microcontrollers.
It operates from 1.62V to 3.6V and is available in 48-pin, 64-pin and 100-pin QFP, 48-pin and
64-pin QFN, and 100-pin BGA packages.
The SAM3N series is the ideal migration path from the SAM3S for applications that require a
reduced BOM cost. The SAM3N series is pin-to-pin compatible with the SAM3S series. Its
aggressive price point and high level of integration pushes its scope of use far into cost-sensitive, high-volume applications.
1.1 Configuration Summary
The SAM3N4/2/1 differ in memory size, package and features list. Table 1-1 summarizes the
configurations of the 9 devices.
Table 1-1. Configuration Summary
Device Flash SRAM Package
ATSAM3N4A 256 Kbytes 24 Kbytes
ATSAM3N4B 256 Kbytes 24 Kbytes
ATSAM3N4C 256 Kbytes 24 Kbytes
ATSAM3N2A 128 Kbytes 16 Kbytes
ATSAM3N2B 128 Kbytes 16 Kbytes
ATSAM3N2C 128 Kbytes 16 Kbytes
ATSAM3N1A 64 Kbytes 8 Kbytes
ATSAM3N1B 64 Kbytes 8 Kbytes
ATSAM3N1C 64 Kbytes 8 Kbytes
LQFP48
QFN48
LQFP64
QFN64
LQFP100
BGA100
LQFP48
QFN48
LQFP64
QFN64
LQFP100
BGA100
LQFP48
QFN48
LQFP64
QFN64
LQFP100
BGA100
Number
of PIOs ADC Timer
34 8 channels 6
47 10 channels 6
79 16 channels 6 10 2 1
34 8 channels 6
47 10 channels 6(
79 16 channels 6 10 2 1
34 8 channels 6
47 10 channels 6
79 16 channels 6 10 2 1
(1)
(2)
(1)
(2)
(1)
(2)
PDC
Channels USART DAC
81_
10 2 1
81 _
10 2 1
81 _
10 2 1
Notes: 1. Only two TC channels are accessible through the PIO.
2. Only three TC channels are accessible through the PIO.
2
SAM3N Summary
11011AS–ATARM–04-Oct-10
2. SAM3N Block Diagram
Figure 2-1. SAM3N 100-pin version Block Diagram
SAM3N Summary
PCK0-PCK2
XOUT
XIN32
XOUT32
ERASE
VDDIO
NRST
VDDCORE
URXD0
UTXD0
URXD1
UTXD1
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
PWM[0:3]
ADTRG
AD[0..15]
ADVREF
DAC0
DATRG
TST
XIN
System Controller
PMC
OSC
3-20 MHz
WDT
RC OSC
12/8/4 MHz
SUPC
OSC 32k
RC 32k
PLL
RTT
RTC
POR
RSTC
PIOA PIOB
PIOC
SM
10-bit ADC
10-bit DAC
TDI
TCK/SWCLK
TDO/TRACESWO
TMS/SWDIO
JTAG & Serial Wire
In-Circuit Emulator
Cortex-M3 Processor
Fmax 48 MHz
I/D
UART0
PDC
UART1
USART0
PDC
USART1
PWM
PDC
PDC
JTAGSEL
24-bit
SysTick Counter
N
V
I
C
FLASH
256 KBytes
128 KBytes
64 KBytes
S
3- layer AHB Bus Matrix Fmax 48 MHz
Peripheral
Bridge
VDDINVDDOUT
Voltage
Regulator
SRAM
24 KBytes
16 KBytes
8 KBytes
Timer Counter A
TC[0..2]
Timer Counter B
TC[3..5]
PDC
SPI
PDC
TWI0
TWI1
ROM
16 KBytes
TCLK[0:2]
TIOA[0:2]
TIOB[0:2]
TCLK[3:5]
TIOA[3:5]
TIOB[3:5]
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOS
SPCK
TWCK0
TWD0
TWCK1
TWD1
11011AS–ATARM–04-Oct-10
3
Figure 2-2. SAM3N 64-pin version Block Diagram
TC[3..5]
AD[0..9]
3- layer AHB Bus Matrix Fmax 48 MHz
TST
PCK0-PCK2
System Controller
XIN
NRST
PMC
XOUT
OSC 32k
XIN32
XOUT32
SUPC
RSTC
OSC
3-20 MHz
PIOA PIOB
POR
RTC
RTT
RC 32k
RC OSC
12/8/4 MHz
ERASE
TDI
TDO/TRACESWO
TMS/SWDIO
TCK/SWCLK
JTAGSEL
I/D
S
VDDINVDDOUT
TC[0..2]
TCLK[0:2]
TWCK0
TWD0
TWCK1
TWD1
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOS
SPCK
TIOA[0:2]
TIOB[0:2]
PDC
PDC
PDC
PDC
PDC
PWM
In-Circuit Emulator
PDC
JTAG & Serial Wire
PWM[0:3]
ADTRG
ADVREF
DAC0
DATRG
10-bit ADC
10-bit DAC
SM
VDDIO
PLL
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
USART0
UART1
UART0
USART1
Cortex-M3 Processor
Fmax 48 MHz
24-bit
SysTick Counter
ROM
16 KBytes
SRAM
24 KBytes
16 KBytes
8 KBytes
FLASH
256 KBytes
128 KBytes
64 KBytes
VDDCORE
WDT
Peripheral
Bridge
URXD0
UTXD0
URXD1
UTXD1
Timer Counter A
Timer Counter B
SPI
TWI0
TWI1
N
V
I
C
Voltage
Regulator
3-layer AHB Bus Matrix Fmax 48 MHz
4
SAM3N Summary
11011AS–ATARM–04-Oct-10
Figure 2-3. SAM3N 48-pin version Block Diagramz
SAM3N Summary
PCK0-PCK2
XOUT
XIN32
XOUT32
ERASE
VDDIO
NRST
VDDCORE
URXD0
UTXD0
URXD1
UTXD1
TST
XIN
System Controller
PMC
3-20 MHz
WDT
RC OSC
12/8/4 MHz
SUPC
OSC 32k
RC 32k
RTC
POR
RSTC
PIOA PIOB
OSC
SM
PLL
RTT
TDI
TCK/SWCLK
TDO/TRACESWO
TMS/SWDIO
JTAG & Serial Wire
In-Circuit Emulator
Cortex-M3 Processor
Fmax 48 MHz
I/D
UART0
PDC
UART1
JTAGSEL
24-bit
SysTick Counter
N
V
I
C
FLASH
256 KBytes
128 KBytes
64 KBytes
S
3-layer AHB Bus Matrix Fmax 48 MHz
3- layer AHB Bus Matrix Fmax 48 MHz
Peripheral
Bridge
N
VDDOUT
VDDI
Voltage
Regulator
SRAM
24 KBytes
16 KBytes
8 KBytes
Timer Counter A
TC[0..2]
ROM
16 KBytes
TCLK[0:2]
TIOA[0:2]
TIOB[0:2]
RXD0
TXD0
SCK0
RTS0
CTS0
PWM[0:3]
ADTRG
AD[0..7]
ADVREF
USART0
PWM
10-bit ADC
PDC
PDC
Timer Counter B
TC[3..5]
PDC
SPI
PDC
TWI0
TWI1
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOS
SPCK
TWCK0
TWD0
TWCK1
TWD1
11011AS–ATARM–04-Oct-10
5
3. Signal Description
Table 3-1 gives details on the signal name classified by peripheral.
Table 3-1. Signal Description List
Active
Signal Name Function Type
Power Supplies
VDDIO Peripherals I/O Lines Power Supply Power 1.62V to 3.6V
VDDIN
VDDOUT Voltage Regulator Output Power 1.8V Output
VDDPLL Oscillator and PLL Power Supply Power 1.65 V to 1.95V
VDDCORE
GND Ground Ground
XIN Main Oscillator Input Input
XOUT Main Oscillator Output Output
XIN32 Slow Clock Oscillator Input Input
XOUT32 Slow Clock Oscillator Output Output
PCK0 - PCK2 Programmable Clock Output Output
Voltage Regulator, ADC and DAC Power
Supply
Power the core, the embedded memories
and the peripherals
Clocks, Oscillators and PLLs
Power 1.8V to 3.6V
Power
Level
Voltage
Reference Comments
1.65V to 1.95V
Connected externally
to VDDOUT
Reset State:
- PIO Input
- Internal Pull-up
disabled
VDDIO
- Schmitt Trigger
enabled
Reset State:
- PIO Input
- Internal Pull-up
enabled
- Schmitt Trigger
enabled
(1)
(1)
(3)
ICE and JTAG
TCK/SWCLK Test Clock/Serial Wire Clock Input
TDI Test Data In Input
TDO/TRACESWO
TMS/SWDIO
JTAGSEL JTAG Selection Input High
6
SAM3N Summary
Test Data Out/Trace Asynchronous Data
Out
Test Mode Select /Serial Wire
Input/Output
Output
Input / I/O
VDDIO
Reset State:
- SWJ-DP Mode
- Internal pull-up
disabled
- Schmitt Trigger
enabled
Permanent Internal
pull-down
11011AS–ATARM–04-Oct-10
(1)
Table 3-1. Signal Description List (Continued)
SAM3N Summary
Active
Signal Name Function Type
Flash Memory
ERASE
NRST Microcontroller Reset I/O Low VDDIO
TST Test Mode Select Input VDDIO
URXDx UART Receive Data Input
UTXDx UART Transmit Data Output
PA0 - PA31 Parallel IO Controller A I/O
PB0 - PB14 Parallel IO Controller B I/O
PC0 - PC31 Parallel IO Controller C I/O
SCKx USARTx Serial Clock I/O
Flash and NVM Configuration Bits Erase
Command
Reset/Test
Universal Asynchronous Receiver Transceiver - UARTx
PIO Controller - PIOA - PIOB - PIOC
Universal Synchronous Asynchronous Receiver Transmitter USARTx
Input High VDDIO
Level
Voltage
Reference Comments
VDDIO
Reset State:
- Erase Input
- Internal pull-down
enabled
- Schmitt Trigger
enabled
Permanent Internal
pull-up
Permanent Internal
pull-down
Reset State:
- PIO or System
IOs
- Internal pull-up
enabled
- Schmitt Trigger
enabled
(1)
(2)
(1)
TXDx USARTx Transmit Data I/O
RXDx USARTx Receive Data Input
RTSx USARTx Request To Send Output
CTSx USARTx Clear To Send Input
Timer/Counter - TC
TCLKx TC Channel x External Clock Input Input
TIOAx TC Channel x I/O Line A I/O
TIOBx TC Channel x I/O Line B I/O
Pulse Width Modulation Controller- PWMC
PWMx PWM Waveform Output for channel x Output
11011AS–ATARM–04-Oct-10
7
Table 3-1. Signal Description List (Continued)
Active
Signal Name Function Type
Serial Peripheral Interface - SPI
MISO Master In Slave Out I/O
MOSI Master Out Slave In I/O
SPCK SPI Serial Clock I/O
SPI_NPCS0 SPI Peripheral Chip Select 0 I/O Low
SPI_NPCS1 SPI_NPCS3
TWDx TWIx Two-wire Serial Data I/O
TWCKx TWIx Two-wire Serial Clock I/O
ADVREF ADC and DAC Reference Analog
AD0 - AD15 Analog Inputs Analog
ADTRG ADC Trigger Input VDDIO
DAC0 DACC channel analog output Analog
DATRG DACC Trigger Input VDDIO
SPI Peripheral Chip Select Output Low
Two-Wire Interface- TWIx
Analog
10-bit Analog-to-Digital Converter - ADC
Digital-to-Analog Converter Controller- DACC
Level
Voltage
Reference Comments
Fast Flash Programming Interface
PGMEN0-PGMEN2 Programming Enabling Input
PGMM0-PGMM3 Programming Mode Input
PGMD0-PGMD15 Programming Data I/O
PGMRDY Programming Ready Output High
PGMNVALID Data Direction Output Low
PGMNOE Programming Read Input Low
PGMCK Programming Clock Input
PGMNCMD Programming Command Input Low
Notes: 1. Schmitt Triggers can be disabled through PIO registers.
2. Some PIO lines are shared with System IOs.
3. See Section 5.3 “Typical Powering Schematics” for restriction on voltage range of Analog Cells.
VDDIO
8
SAM3N Summary
11011AS–ATARM–04-Oct-10
4. Package and Pinout
125
26
50
5175
76
100
SAM3N4/2/1 series is pin-to-pin compatible with SAM3S products. Furthermore SAM3N4/2/1
devices have new functionalities referenced in italic inTable 4-1, Table 4-3 and Table 4-4.
4.1 SAM3N4/2/1C Package and Pinout
4.1.1 100-lead LQFP Package Outline
Figure 4-1. Orientation of the 100-lead LQFP Package
SAM3N Summary
4.1.2 100-ball LFBGA Package Outline
The 100-Ball LFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimensions are 9 x 9 x 1.1 mm.
Figure 4-2. Orientation of the 100-ball LFBGA Package
TOP VIEW
10
9
8
7
6
5
4
3
2
1
ABCDEFGHJK
BALL A1
9
11011AS–ATARM–04-Oct-10
4.1.3 100-Lead LQFP Pinout
Table 4-1. 100-lead LQFP SAM3N4/2/1C Pinout
1 ADVREF 26 GND 51 TDI/PB4 76 TDO/TRACESWO/PB5
2 GND 27 VDDIO 52 PA6/PGMNOE 77 JTAGSEL
3 PB0/AD4 28 PA16/PGMD4 53 PA5/PGMRDY 78 PC18
4 PC29/AD13 29 PC7 54 PC28 79 TMS/SWDIO/PB6
5 PB1/AD5 30 PA15/PGMD3 55 PA4/PGMNCMD 80 PC19
6 PC30/AD14 31 PA14/PGMD2 56 VDDCORE 81 PA31
7 PB2/AD6 32 PC6 57 PA27 82 PC20
8 PC31/AD15 33 PA13/PGMD1 58 PC8 83 TCK/SWCLK/PB7
9 PB3/AD7 34 PA24 59 PA28 84 PC21
10 VDDIN 35 PC5 60 NRST 85 VDDCORE
11 VDDOUT 36 VDDCORE 61 TST 86 PC22
12 PA17/PGMD5/AD0 37 PC4 62 PC9 87 ERASE/PB12
13 PC26 38 PA25 63 PA29 88 PB10
14 PA18/PGMD6/AD1 39 PA26 64 PA30 89 PB11
15 PA21/AD8 40 PC3 65 PC10 90 PC23
16 VDDCORE 41 PA12/PGMD0 66 PA3 91 VDDIO
17 PC27 42 PA11/PGMM3 67 PA2/PGMEN2 92 PC24
18 PA19/PGMD7/AD2 43 PC2 68 PC11 93 PB13/DAC0
19 PC15/AD11 44 PA10/PGMM2 69 VDDIO 94 PC25
20 PA22/AD9 45 GND 70 GND 95 GND
21 PC13/AD10 46 PA9/PGMM1 71 PC14 96 PB8/XOUT
22 PA23 47 PC1 72 PA1/PGMEN1 97 PB9/PGMCK/XIN
23 PC12/AD12 48
24 PA20/AD3 49
25 PC0 50 VDDIO 75 PC17 100 VDDPLL
PA8/XOUT32/
PGMM0
PA7/XIN32/
PGMNVALID
73 PC16 98 VDDIO
74 PA0/PGMEN0 99 PB14
10
SAM3N Summary
11011AS–ATARM–04-Oct-10
4.1.4 100-ball LFBGA Pinout
Table 4-2. 100-ball LFBGA SAM3N4/2/1C Pinout
SAM3N Summary
A1 PB1/AD5 C6 TCK/SWCLK/PB7 F1
A2 PC29 C7 PC16 F2 PC26 H7 PA11/PGMM3
A3 VDDIO C8 PA1/PGMEN1 F3 VDDOUT H8 PC1
A4 PB9/PGMCK/XIN C9 PC17 F4 GND H9 PA6/PGMNOE
A5 PB8/XOUT C10 PA0/PGMEN0 F5 VDDIO H10 TDI/PB4
A6 PB13/DAC0 D1 PB3/AD7 F6 PA27 J1 PC15/AD11
A7 DDP/PB11 D2 PB0/AD4 F7 PC8 J2 PC0
A8 DDM/PB10 D3 PC24 F8 PA28 J3 PA16/PGMD4
A9 TMS/SWDIO/PB6 D4 PC22 F9 TST J4 PC6
A10 JTAGSEL D5 GND F10 PC9 J5 PA24
B1 PC30 D6 GND G1 PA21/AD8 J6 PA25
B2 ADVREF D7 VDDCORE G2 PC27 J7 PA10/PGMM2
B3 GNDANA D8 PA2/PGMEN2 G3 PA15/PGMD3 J8 GND
B4 PB14/DAC1 D9 PC11 G4 VDDCORE J9 VDDCORE
B5 PC21 D10 PC14 G5 VDDCORE J10 VDDIO
B6 PC20 E1
PA17/PGMD5/
AD0
G 6 PA 2 6 K 1 PA 22 / AD 9
PA 1 8/ P G MD 6 /
AD1
H6 PC4
B7 PA31 E2 PC31 G7 PA12/PGMD0 K2 PC13/AD10
B8 PC19 E3 VDDIN G8 PC28 K3 PC12/AD12
B9 PC18 E4 GND G9 PA4/PGMNCMD K4 PA20/AD3
B10
TDO/TRACESWO/
PB5
C1 PB2/AD6 E6 NRST H1
C2 VDDPLL E7 PA29/AD13 H2 PA23 K7 PC2
C3 PC25 E8 PA30/AD14 H3 PC7 K8 PA9/PGMM1
C4 PC23 E9 PC10 H4 PA14/PGMD2 K9
C5 ERASE/PB12 E10 PA3 H5 PA13/PGMD1 K10
E5 GND G10 PA5/PGMRDY K5 PC5
PA 1 9/ P G MD 7 /
AD2
K6 PC3
PA8/XOUT32/
PGMM0
PA7/XIN32/
PGMNVALID
11011AS–ATARM–04-Oct-10
11
4.2 SAM3N4/2/1B Package and Pinout
Figure 4-3. Orientation of the 64-pad QFN Package
4964
1
48
16
17
TOP VIEW
Figure 4-4. Orientation of the 64-lead LQFP Package
48
49
64
1
33
32
33
32
17
16
12
SAM3N Summary
11011AS–ATARM–04-Oct-10
SAM3N Summary
4.2.1 64-Lead LQFP and QFN Pinout
64-pin version SAM3N devices are pin-to-pin compatible with SAM3S products. Furthermore,
SAM3N products have new functionalities shown in italic in Table 4-3.
Table 4-3. 64-pin SAM3N4/2/1B Pinout
1 ADVREF 17 GND 33 TDI/PB4 49 TDO/TRACESWO/PB5
2 GND 18 VDDIO 34 PA6/PGMNOE 50 JTAGSEL
3 PB0/AD4 19 PA16/PGMD4 35 PA5/PGMRDY 51 TMS/SWDIO/PB6
4 PB1AD5 20 PA15/PGMD3 36 PA4/PGMNCMD 52 PA31
5 PB2/AD6 21 PA14/PGMD2 37 PA27/PGMD15 53 TCK/SWCLK/PB7
6 PB3/AD7 22 PA13/PGMD1 38 PA28 54 VDDCORE
7 VDDIN 23 PA24/PGMD12 39 NRST 55 ERASE/PB12
8 VDDOUT 24 VDDCORE 40 TST 56 PB10
9 PA17/PGMD5/AD0 25 PA25/PGMD13 41 PA29 57 PB11
10 PA18/PGMD6/AD1 26 PA26/PGMD14 42 PA30 58 VDDIO
11 PA21/PGMD9/AD8 27 PA12/PGMD0 43 PA3 59 PB13/DAC0
12 VDDCORE 28 PA11/PGMM3 44 PA2/PGMEN2 60 GND
13 PA19/PGMD7/AD2 29 PA10/PGMM2 45 VDDIO 61 XOUT/PB8
14 PA22/PGMD10/AD9 30 PA9/PGMM1 46 GND 62 XIN/PGMCK/PB9
15 PA23/PGMD11 31
16 PA20/PGMD8/AD3 32
Note: The bottom pad of the QFN package must be connected to ground.
PA8/XOUT32/PGMM
0
PA7/XIN32/XOUT32/
PGMNVALID
47 PA1/PGMEN1 63 PB14
48 PA0/PGMEN0 64 VDDPLL
11011AS–ATARM–04-Oct-10
13
4.3 SAM3N4/2/1A Package and Pinout
25
37
36
24
13
12
1
48
Figure 4-5. Orientation of the 48-pad QFN Package
3748
1
12
13 24
TOP VIEW
Figure 4-6. Orientation of the 48-lead LQFP Package
36
25
14
SAM3N Summary
11011AS–ATARM–04-Oct-10
4.3.1 48-Lead LQFP and QFN Pinout
Table 4-4. 48-pin SAM3N4/2/1A Pinout
SAM3N Summary
1 ADVREF 13 VDDIO 25 TDI/PB4 37
2 GND 14 PA16/PGMD4 26 PA6/PGMNOE 38 JTAGSEL
3 PB0/AD4 15 PA15/PGMD3 27 PA5/PGMRDY 39 TMS/SWDIO/PB6
4 PB1/AD5 16 PA14/PGMD2 28 PA4/PGMNCMD 40 TCK/SWCLK/PB7
5 PB2/AD6 17 PA13/PGMD1 29 NRST 41 VDDCORE
6 PB3/AD7 18 VDDCORE 30 TST 42 ERASE/PB12
7 VDDIN 19 PA12/PGMD0 31 PA3 43 PB10
8 VDDOUT 20 PA11/PGMM3 32 PA2/PGMEN2 44 PB11
9 PA17/PGMD5/AD0 21 PA10/PGMM2 33 VDDIO 45 XOUT/PB8
10 PA18/PGMD6/AD1 22 PA9/PGMM1 34 GND 46 XIN/P/PB9/GMCK
11 PA19/PGMD7/AD2 23
12 PA20/AD3 24
Note: The bottom pad of the QFN package must be connected to ground.
PA8/XOUT32/PG
MM0
PA7/XIN32/PGMN
VALID
35 PA1/PGMEN1 47 VDDIO
36 PA0/PGMEN0 48 VDDPLL
TDO/TRACESWO/
PB5
11011AS–ATARM–04-Oct-10
15
5. Power Considerations
5.1 Power Supplies
The SAM3N product has several types of power supply pins:
• VDDCORE pins: Power the core, including the processor, the embedded memories and the
peripherals. Voltage ranges from 1.62V and 1.95V.
• VDDIO pins: Power the Peripherals I/O lines, Backup part, 32 kHz crystal oscillator and
oscillator pads. Voltage ranges from 1.62V and 3.6V
• VDDIN pin: Voltage Regulator, ADC and DAC Power Supply. Voltage ranges from 1.8V to
3.6V for the Voltage Regulator
• VDDPLL pin: Powers the PLL, the Fast RC and the 3 to 20 MHz oscillators. Voltage ranges
from 1.62V and 1.95V.
5.2 Voltage Regulator
The SAM3N embeds a voltage regulator that is managed by the Supply Controller.
This internal regulator is intended to supply the internal core of SAM3N. It features two different
operating modes:
• In Normal mode, the voltage regulator consumes less than 700 µA static current and draws
60 mA of output current. Internal adaptive biasing adjusts the regulator quiescent current
depending on the required load current. In Wait Mode quiescent current is only 7 µA.
• In Backup mode, the voltage regulator consumes less than 1 µA while its output (VDDOUT)
is driven internally to GND. The default output voltage is 1.80V and the start-up time to reach
Normal mode is less than100 µs.
For adequate input and output power supply decoupling/bypassing, refer to the Voltage Regulator section in the Electrical Characteristics section of the datasheet.
5.3 Typical Powering Schematics
The SAM3N supports a 1.62V-3.6V single supply mode. The internal regulator input connected
to the source and its output feeds VDDCORE. Figure 5-1 shows the power schematics.
As VDDIN powers the voltage regulator and the ADC/DAC, when the user does not want to use
the embedded voltage regulator, it can be disabled by software via the SUPC (note that it is different from Backup mode).
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SAM3N Summary
11011AS–ATARM–04-Oct-10
Figure 5-1. Single Supply
Main Supply
(1.8V-3.6V)
ADC, DAC
I/Os.
VDDIN
Voltage
Regulator
VDDOUT
VDDCORE
VDDIO
VDDPLL
Main Supply
(1.62V-3.6V)
Can be the
same supply
VDDCORE Supply
(1.62V-1.95V)
ADC, DAC Supply
(3V-3.6V)
ADC, DAC
VDDIN
Voltage
Regulator
VDDOUT
VDDCORE
VDDIO
VDDPLL
I/Os.
Figure 5-2. Core Externally Supplied
SAM3N Summary
11011AS–ATARM–04-Oct-10
Note: Restrictions
With Main Supply < 3V, ADC and DAC are not usable.
With Main Supply >= 3V, all peripherals are usable.
Figure 5-3 below provides an example of the powering scheme when using a backup battery.
Since the PIO state is preserved when in backup mode, any free PIO line can be used to switch
off the external regulator by driving the PIO line at low level (PIO is input, pull-up enabled after
backup reset). External wake-up of the system can be from a push button or any signal. See
Section 5.6 “Wake-up Sources” for further details.
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Figure 5-3. Core Externally Supplied (backup battery)
ADC, DAC
I/Os.
VDDIN
Voltage
Regulator
3.3V
LDO
Backup
Battery
+
-
ON/OFF
IN
OUT
VDDOUT
Main Supply
VDDCORE
ADC, DAC Supply
(3V-3.6V)
VDDIO
VDDPLL
PIOx (Output)
WAKEUPx
External wakeup signal
Note: The two diodes provide a “switchover circuit” (for illustration purpose)
between the backup battery and the main supply when the system is put in
backup mode.
5.4 Active Mode
5.5 Low Power Modes
5.5.1 Backup Mode
Active mode is the normal running mode with the core clock running from the fast RC oscillator,
the main crystal oscillator or the PLL. The power management controller can be used to adapt
the frequency and to disable the peripheral clocks.
The various low-power modes of the SAM3N are described below:
The purpose of backup mode is to achieve the lowest power consumption possible in a system
that is performing periodic wakeups to carry out tasks but not requiring fast startup time
(<0.1ms). Total current consumption is 3 µA typical.
The Supply Controller, zero-power power-on reset, RTT, RTC, Backup registers and 32 kHz
oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The
regulator and the core supply are off.
Backup mode is based on the Cortex-M3 deep sleep mode with the voltage regulator disabled.
The SAM3N can be awakened from this mode through WUP0-15 pins, the supply monitor (SM),
the RTT or RTC wake-up event.
Backup mode is entered by using WFE instructions with the SLEEPDEEP bit in the System Control Register of the Cortex-M3 set to 1. (See the Power management description in The ARM
Cortex M3 Processor section of the product datasheet).
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Exit from Backup mode happens if one of the following enable wake-up events occurs:
• WKUPEN0-15 pins (level transition, configurable debouncing)
SAM3N Summary
11011AS–ATARM–04-Oct-10
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