ATMEL AT93C46 User Manual
Features
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (V
• User-selectable Internal Organization
– 1K: 128 x 8 or 64 x 16
– 2K: 256 x 8 or 128 x 16
– 4K: 512 x 8 or 256 x 16
• Three-wire Serial Interface
• 2 MHz Clock Rate (5V)
• Self-timed Write Cycle (10 ms max)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Automotive Grade, Extended Temperature and Lead-Free/Halogen-Free
Devices Available
• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP, 8-lead TSSOP,
and 8-ball dBGA2 Packages
= 1.8V to 5.5V)
CC
Three-wire
Serial
EEPROMs
1K (128 x 8 or 64 x 16)
Description
The AT93C46/56/66 provides 1024/2048/4096 bits of serial electrically erasable programmable read-only memory (EEPROM), organized as 64/128/256 words of 16 bits
each (when the ORG pin is connected to VCC), and 128/256/512 words of 8 bits each
(when the ORG pin is tied to ground). The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are
essential. The AT93C46/56/66 is available in space-saving 8-lead PDIP, 8-lead
JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP, 8-lead TSSOP, and 8-lead dBGA2
packages.
The AT93C46/56/66 is enabled through the Chip Select pin (CS) and accessed via a
three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the
data is clocked out serially on the DO pin. The Write cycle is completely self-timed,
and no separate Erase cycle is required before Write. The Write cycle is only enabled
when the part is in the Erase/Write Enable state. When CS is brought high following
the initiation of a Write cycle, the DO pin outputs the Ready/Busy status of the part.
The AT93C46/56/66 is available in 2.7V to 5.5V and 1.8V to 5.5V versions.
Table 1. Pin Configurations
Pin Name Function
CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
GND Ground
VCC Power Supply
ORG Internal Organization
DC Don’t Connect
8-lead SOIC
1
CS
2
SK
3
DI
4
DO
8-lead PDIP
1
CS
2
SK
3
DI
4
DO
8-lead MAP 8-lead TSSOP
8
VCC
7
DC
6
ORG
5
GND
VCC
8
DC
7
ORG
6
GND
5
VCC
8
DC
7
ORG
6
GND
5
1
CS
2
SK
3
DI
4
DO
VCC
DC
ORG
GND
(1K JEDEC Only)
DC
VCC
CS
SK
1
CS
2
SK
3
DI
4
DO
8-lead dBGA2
1
8
2
7
3
6
4
5
8-lead SOIC
Rotated (R)
1
8
2
7
3
6
4
5
CS
SK
D1
D0
ORG
GND
DO
DI
8
VCC
7
DC
6
ORG
5
GND
2K (256 x 8 or 128 x 16)
4K (512 x 8 or 256 x 16)
AT93C46
AT93C56
AT93C66
Note: 1. This device is not recom-
mended for new designs.
Please refer to AT93C56A.
2. This device is not recommended for new designs.
Please refer to AT93C66A.
(1)
(2)
0172Z–SEEPR–9/05
1
Absolute Maximum Ratings*
Operating Temperature......................................−55°C to +125°C
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Note: When the ORG pin is connected to VCC, the “x 16” organization is selected. When it is
connected to ground, the “x 8” organization is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1
Meg ohm pullup, then the “x 16” organization is selected. The feature is not available on
the 1.8V devices.
For the AT93C46, if “x 16” organization is the mode of choice and Pin 6 (ORG) is left
unconnected, Atmel recommends using the AT93C46A device. For more details, see the
AT93C46A datasheet.
2
AT93C46/56/66
0172Z–SEEPR–9/05
AT93C46/56/66
Table 2. Pin Capacitance
(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol Test Conditions Max Units Conditions
C
OUT
C
IN
Output Capacitance (DO) 5 pF V
OUT
= 0V
Input Capacitance (CS, SK, DI) 5 pF VIN = 0V
Note: 1. This parameter is characterized and is not 100% tested.
Table 3. DC Characteristics
Applicable over recommended operating range from: T
T
= -40°C to +125°C, VCC = +1.8V to +5.5V (unless otherwise noted)
AE
Symbol Parameter Test Condition Min Typ Max Unit
V
CC1
V
CC2
V
CC3
I
CC
I
SB1
I
SB2
I
SB3
I
IL
I
OL
(1)
V
IL1
(1)
V
IH1
(1)
V
IL2
(1)
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Note: 1. VIL min and VIH max are reference only and are not tested.
Supply Voltage 1.8 5.5 V
Supply Voltage 2.7 5.5 V
Supply Voltage 4.5 5.5 V
Supply Current VCC = 5.0V
Standby Current VCC = 1.8V CS = 0V 0 0.1 µA
Standby Current VCC = 2.7V CS = 0V 6.0 10.0 µA
Standby Current VCC = 5.0V CS = 0V 17 30 µA
Input Leakage VIN = 0V to VCC 0.1 1.0 µA
Output Leakage VIN = 0V to VCC 0.1 1.0 µA
Input Low Voltage
2.7V ≤ VCC ≤ 5.5V
Input High Voltage 2.0 VCC + 1
Input Low Voltage
1.8V ≤ V
Input High Voltage VCC x 0.7 VCC + 1
Output Low Voltage
Output High Voltage IOH = −0.4 mA 2.4 V
2.7V ≤ V
≤ 5.5V
CC
Output Low Voltage
Output High Voltage IOH = −100 µA VCC – 0.2 V
1.8V ≤ V
≤ 2.7V
CC
= −40°C to +85°C, VCC = +1.8V to +5.5V,
AI
READ at 1.0 MHz 0.5 2.0 mA
WRITE at 1.0 MHz 0.5 2.0 mA
−0.6 0.8
≤ 2.7V
−0.6 V
CC
I
= 2.1 mA 0.4 V
OL
I
= 0.15 mA 0.2 V
OL
CC
x 0.3
V
V
0172Z–SEEPR–9/05
3
Table 4. AC Characteristics
Applicable over recommended operating range from T
= −40°C to + 85°C, VCC = As Specified,
AI
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
f
SK
t
SKH
t
SKL
t
CS
t
CSS
t
DIS
t
CSH
t
DIH
SK Clock
Frequency
SK High Time
4.5V ≤ V
2.7V ≤ V
1.8V ≤ VCC ≤ 5.5V
4.5V ≤ V
2.7V ≤ V
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
1.8V ≤ VCC ≤ 5.5V
SK Low Time
4.5V ≤ V
2.7V ≤ V
≤ 5.5V
CC
≤ 5.5V
CC
1.8V ≤ VCC ≤ 5.5V
Minimum CS
Low Time
4.5V ≤ V
2.7V ≤ V
1.8V ≤ VCC ≤ 5.5V
≤ 5.5V
CC
≤ 5.5V
CC
CS Setup Time Relative to SK
DI Setup Time Relative to SK
4.5V ≤ V
2.7V ≤ V
≤ 5.5V
CC
≤ 5.5V
CC
1.8V ≤ VCC ≤ 5.5V
4.5V ≤ V
2.7V ≤ V
≤ 5.5V
CC
≤ 5.5V
CC
1.8V ≤ VCC ≤ 5.5V
0
0
0
250
250
1000
250
250
1000
250
250
1000
50
50
200
100
100
400
CS Hold Time Relative to SK 0 ns
DI Hold Time Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
100
400
2
1
0.25
MHz
ns
ns
ns
ns
ns
ns
4.5V ≤ V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
4.5V ≤ V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ V
4.5V ≤ V
2.7V ≤ V
1.8V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ V
1.8V ≤ V
4.5V ≤ V
t
PD1
t
PD0
t
SV
t
DF
t
WP
Endurance
Output Delay to
“1”
Output Delay to
“0”
CS to Status
Valid
CS to DO in High
Impedance
AC Test
AC Test
AC Test
AC Test
CS = V
IL
Write Cycle Time
(1)
5.0V, 25°C 1M Write Cycles
Note: 1. This parameter is characterized and is not 100% tested.
≤ 5.5V
CC
250
250
1000
≤ 5.5V
CC
250
250
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
1000
250
250
1000
100
≤ 5.5V
CC
≤ 5.5V
CC
100
400
10 ms
≤ 5.5V 0.1 3 ms
CC
ns
ns
ns
ns
4
AT93C46/56/66
0172Z–SEEPR–9/05
Table 5. Instruction Set for the AT93C46
AT93C46/56/66
Op
Instruction SB
Code
READ 1 10 A6 – A
EWEN 1 00 11XXXXX 11XXXX
ERASE 1 11 A
WRITE 1 01 A6 – A
ERAL 1 00 10XXXXX 10XXXX
WRAL 1 00 01XXXXX 01XXXX D7 – D
Address Data
A5 – A
A5 – A
A5 – A
0
0
0
D7 – D
6
– A
0
0
0
Commentsx 8 x 16 x 8 x 16
Reads data stored in memory, at
specified address
Write enable must precede all
programming modes
Erases memory location An – A
D
0
15
– D
Writes memory location An – A
0
0
0
Erases all memory locations. Valid
only at V
D
0
15
– D
Writes all memory locations. Valid
0
only at VCC = 4.5V to 5.5V
= 4.5V to 5.5V
CC
EWDS 1 00 00XXXXX 00XXXX Disables all programming instructions
Note: The Xs in the address field represent DON’T CARE values and must be clocked.
Table 6. Instruction Set for the AT93C56
Op
Instruction SB
READ 1 10 A8 – A
Code
(1)
and AT93C66
Address Data
0
A7 – A
EWEN 1 00 11XXXXXXX 11XXXXXX
(2)
Commentsx 8 x 16 x 8 x 16
0
Reads data stored in memory, at
specified address
Write enable must precede all
programming modes
ERASE 1 11 A
WRITE 1 01 A8 – A
8
– A
0
0
ERAL 1 00 10XXXXXXX 10XXXXXX
A7 – A
A7 – A
0
0
D7 – D
D
0
15
– D
Erases memory location An – A
Writes memory location An– A
0
0
0
Erases all memory locations. Valid
only at V
= 4.5V to 5.5V
CC
Writes all memory locations. Valid
WRAL 1 00 01XXXXXXX 01XXXXXX D
7
– D
D
0
15
– D
only at VCC = 5.0V ±10% and Disable
0
Register cleared
EWDS 1 00 00XXXXXXX 00XXXXXX Disables all programming instructions
Notes: 1. This device is not recommended for new designs. Please refer to AT93C56A.
2. This device is not recommended for new designs. Please refer to AT93C66A.
0172Z–SEEPR–9/05
5
Functional Description
The AT93C46/56/66 is accessed via a simple and versatile three-wire serial communication interface. Device operation is controlled by seven instructions issued by the host
processor. A valid instruction starts with a rising edge of CS and consists of a start bit
(logic “1”) followed by the appropriate op code and the desired memory address
location.
READ (READ): The Read (READ) instruction contains the address code for the memory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output string.
ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes
into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write
Enable (EWEN) instruction must be executed first before any programming instructions
can be carried out. Please note that once in the EWEN state, programming remains
enabled until an EWDS instruction is executed or V
power is removed from the part.
CC
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
Erase instruction and address are decoded. The DO pin outputs the Ready/Busy status
of the part if CS is brought high after being kept low for a minimum of 250 ns (t
CS
). A
logic “1” at pin DO indicates that the selected memory location has been erased and the
part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be
written into the specified memory location. The self-timed programming cycle t
WP
starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
Read/Busy status of the part if CS is brought high after being kept low for a minimum of
250 ns (t
). A logic “0” at DO indicates that programming is still in progress. A logic “1”
CS
indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions. A
Ready/Busy status cannot be obtained if the CS is brought high after the end of the selftimed programming cycle tWP.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic “1” state and is primarily used for testing purposes. The DO pin
outputs the Ready/Busy status of the part if CS is brought high after being kept low for a
minimum of 250 ns (t
). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
CS
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy
status of the part if CS is brought high after being kept low for a minimum of 250 ns (t
The WRAL instruction is valid only at V
= 5.0V ± 10%.
CC
CS
).
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the Read instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
6
AT93C46/56/66
0172Z–SEEPR–9/05
Timing Diagrams
Figure 2. Synchronous Data Timing
AT93C46/56/66
µs
Note: 1. This is the minimum SK period.
Table 7. Organization Key for Timing Diagrams
AT93C46 (1K) AT93C56 (2K)
I/O
A
N
D
N
Notes: 1. This device is not recommended for new designs. Please refer to AT93C56A.
2. This device is not recommended for new designs. Please refer to AT93C66A.
is a don’t care value, but the extra clock is required.
3. A
8
4. A7 is a don’t care value, but the extra clock is required.
x 8 x 16 x 8 x 16 x 8 x 16
A
6
D
7
A
5
D
15
(3)
A
8
D
7
(1)
(4)
A
7
D
15
AT93C66 (4K)
A
8
D
7
(2)
A
7
D
15
0172Z–SEEPR–9/05
7
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