ATMEL AT91SAM9XE512 User Manual

Download

BDTIC www.bdtic.com/ATMEL

Features

• Incorporates the ARM7TDMI

– High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – EmbeddedICE

• Internal High-speed Flash

– 512 Kbytes (AT91SAM7XC512) Organized in Two Banks of 1024 Pages of 256 Bytes

(Dual Plane)

– 256 Kbytes (AT91SAM7XC256) Organized in 1024 Pages of 256 Bytes (Single

Plane)

– 128 Kbytes (AT91SAM7XC128) Organized in 512 Pages of 256 Bytes (Single Plane)

• Single Cycle Access at Up to 30 MHz in Worst Case Conditions

• Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed

• Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms

• 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit

• Fast Flash Programming Interface for High Volume Production

• Internal High-speed SRAM, Single-cycle Access at Maximum Speed

– 128 Kbytes (AT91SAM7XC512) – 64 Kbytes (AT91SAM7XC256) – 32 Kbytes (AT91SAM7XC128)

• Memory Controller (MC)

– Embedded Flash Controller, Abort Status and Misalignment Detection

• Reset Controller (RSTC)

– Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout

Detector

– Provides External Reset Signal Shaping and Reset Source Status

• Clock Generator (CKGR)

– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL

• Power Management Controller (PMC)

– Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and

Idle Mode

– Four Programmable External Clock Signals

• Advanced Interrupt Controller (AIC)

– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt

Protected

• Debug Unit (DBGU)

– 2-wire UART and Support for Debug Communication Channel interrupt,

Programmable ICE Access Prevention

– Mode for General Purpose 2-wire UART Serial Communication

• Periodic Interval Timer (PIT)

– 20-bit Programmable Counter plus 12-bit Interval Counter

• Windowed Watchdog (WDT)

– 12-bit Key-protected Programmable Counter – Provides Reset or Interrupt Signals to the System – Counter May Be Stopped While the Processor is in Debug State or in Idle Mode

™

In-circuit Emulation, Debug Communication Channel Support

ARM® Thumb® Processor

AT91 ARM Thumb-based Microcontrollers

AT91SAM7XC512 AT91SAM7XC256 AT91SAM7XC128

Preliminary

6209F–ATARM–17-Feb-09

• Real-time Timer (RTT)

– 32-bit Free-running Counter with Alarm – Runs Off the Internal RC Oscillator

• Two Parallel Input/Output Controllers (PIO)

– Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output

• Seventeen Peripheral DMA Controller (PDC) Channels

• One Advanced Encryption System (AES)

– 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications (AT91SAM7XC512) – 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications (AT91SAM7XC256/128) – Buffer Encryption/Decryption Capabilities with PDC

• One Triple Data Encryption System (TDES)

– Two-key or Three-key Algorithms, Compliant with FIPS PUB 46-3 Specifications – Optimized for Triple Data Encryption Capability

• One USB 2.0 Full Speed (12 Mbits per second) Device Port

– On-chip Transceiver, 1352-byte Configurable Integrated FIFOs

• One Ethernet MAC 10/100 base-T

– Media Independent Interface (MII) or Reduced Media Independent Interface (RMII) – Integrated 28-byte FIFOs and Dedicated DMA Channels for Transmit and Receive

• One Part 2.0A and Part 2.0B Compliant CAN Controller

– Eight Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter

• One Synchronous Serial Controller (SSC)

– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I²S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer

• Two Universal Synchronous/Asynchronous Receiver Transmitters (USART)

– Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation – Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support – Full Modem Line Support on USART1

• Two Master/Slave Serial Peripheral Interfaces (SPI)

– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects

• One Three-channel 16-bit Timer/Counter (TC)

– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability

• One Four-channel 16-bit Power Width Modulation Controller (PWMC)

• One Two-wire Interface (TWI)

– Master Mode Support Only, All Two-wire Atmel EEPROMs and I

C Compatible Devices Supported

• One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os

• SAM-BA

Boot Assistant – Default Boot program – Interface with SAM-BA Graphic User Interface

• IEEE 1149.1 JTAG Boundary Scan on All Digital Pins

• 5V-tolerant I/Os, Including Four High-current Drive I/O lines, Up to 16 mA Each

• Power Supplies

– Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components – 3.3V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply – 1.8V VDDCORE Core Power Supply with Brownout Detector

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

• Fully Static Operation: Up to 55 MHz at 1.65V and 85°C Worst Case Conditions

• Available in 100-lead LQFP Green and 100-ball TFBGA Green Packages

6209F–ATARM–17-Feb-09

1. Description

Atmel's AT91SAM7XC512/256/128 is a member of a series of highly integrated Flash microcontrollers based on the 32-bit ARM RISC processor. It features 512/256/128 Kbyte high-speed Flash and 128/64/32 Kbyte SRAM, a large set of peripherals, including an 802.3 Ethernet MAC, a CAN controller, an AES 128 Encryption accelerator and a Triple Data Encryption System. A complete set of system functions minimizes the number of external components.

The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel interface on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from accidental overwrite and preserve its confidentiality.

The AT91SAM7XC512/256/128 system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator.

By combining the ARM7TDMI processor with on-chip Flash and SRAM, and a wide range of peripheral functions, including USART, SPI, CAN Controller, Ethernet MAC, AES 128 accelerator, TDES, Timer Counter, RTT and Analog-to-Digital Converters on a monolithic chip, the AT91SAM7XC512/256/128 is a powerful device that provides a flexible, cost-effective solution to many embedded control applications requiring secure communication over, for example, Ethernet, CAN wired and Zigbee

1.1 Configuration Summary of the AT91SAM7XC512/256/128

The AT91SAM7XC512, AT91SAM7XC256 and AT91SAM7XC128 differ only in memory sizes.

Table 1-1 summarizes the configurations of the two devices.

™

wireless networks.

Table 1-1. Configuration Summary

Device Flash Flash Organization SRAM AES TDES

AT91SAM7XC512 512K bytes dual plane 128K bytes 1 AES 256/192/128 1

AT91SAM7XC256 256K bytes single plane 64K bytes 1 AES 128 1

AT91SAM7XC128 128K bytes single plane 32K bytes 1 AES 128 1

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

TDI TDO TMS TCK

NRST

FIQ

IRQ0-IRQ1

PCK0-PCK3

PMC

Peripheral Bridge

Peripheral DMA

Controller

AIC

PLL

RCOSC

SRAM

128/64/32

Kbytes

ARM7TDMI

Processor

ICE

JTAG

SCAN

JTAGSEL

PIOA

USART0

SSC

Timer Counter

RXD0

TXD0

SCK0

RTS0 CTS0

SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3

SPI0_MISO SPI0_MOSI

SPI0_SPCK

Flash

512/256/128

Kbytes

Reset

Controller

DRXD DTXD

TF TK TD RD RK RF TCLK0 TCLK1 TCLK2 TIOA0 TIOB0

TIOA1 TIOB1

TIOA2 TIOB2

Memory Controller

Abort

Status

Address Decoder

Misalignment

Detection

PIO

APB

POR

Embedded

Flash

Controller

AD0 AD1 AD2 AD3

ADTRG

PLLRC

17 Channels

PDC

USART1

RXD1

TXD1

SCK1

RTS1

CTS1 DCD1 DSR1 DTR1

RI1

PDC

SPI0

PDC

ADC

ADVREF

PDC

TC0

TC1

TC2

TWD TWCK

TWI

OSC

XIN

XOUT

VDDIN

PWMC

PWM0 PWM1 PWM2 PWM3

1.8 V

Voltage

Regulator

USB Device

FIFO

DDM DDP

Transceiver

GND VDDOUT

BOD

VDDCORE

VDDFLASH

AD4 AD5 AD6 AD7

VDDFLASH

Fast Flash

Programming

Interface

ERASE

PIO

PGMD0-PGMD15 PGMNCMD PGMEN0-PGMEN1

PGMRDY PGMNVALID PGMNOE PGMCK PGMM0-PGMM3

VDDIO

TST

DBGU

PDC

PIT

WDT

RTT

System Controller

VDDCORE

CAN

CANRX CANTX

PIO

Ethernet MAC 10/100

ETXCK-ERXCK-EREFCK ETXEN-ETXER ECRS-ECOL, ECRSDV ERXER-ERXDV ERX0-ERX3 ETX0-ETX3 EMDC EMDIO

DMA

FIFO

PIOB

SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3

SPI1_MISO SPI1_MOSI

SPI1_SPCK

PDC

SPI1

AES 128

PDC

EF100

SAM-BA

TDES

PDC

ROM

VDDFLASH

AT91SAM7XC512/256/128 Preliminary

2. AT91SAM7XC512/256/128 Block Diagram

Figure 2-1. AT91SAM7XC512/256/128 Block Diagram

6209F–ATARM–17-Feb-09

3. Signal Description

Table 3-1. Signal Description List

Active

Signal Name Function Type

Power

VDDIN

VDDOUT Voltage Regulator Output Power 1.85V

VDDFLASH Flash and USB Power Supply Power 3V to 3.6V

VDDIO I/O Lines Power Supply Power 3V to 3.6V

VDDCORE Core Power Supply Power 1.65V to 1.95V

VDDPLL PLL Power 1.65V to 1.95V

GND Ground Ground

XIN Main Oscillator Input Input

XOUT Main Oscillator Output Output

PLLRC PLL Filter Input

PCK0 - PCK3 Programmable Clock Output Output

TCK Test Clock Input No pull-up resistor

TDI Test Data In Input No pull-up resistor

TDO Test Data Out Output

TMS Test Mode Select Input No pull-up resistor

JTAGSEL JTAG Selection Input Pull-down resistor

ERASE

NRST Microcontroller Reset I/O Low

TST Test Mode Select Input High Pull-down resistor

DRXD Debug Receive Data Input

DTXD Debug Transmit Data Output

IRQ0 - IRQ1 External Interrupt Inputs Input

FIQ Fast Interrupt Input Input

PA0 - PA30 Parallel IO Controller A I/O Pulled-up input at reset.

PB0 - PB30 Parallel IO Controller B I/O Pulled-up input at reset.

Voltage Regulator and ADC Power Supply Input

Clocks, Oscillators and PLLs

ICE and JTAG

Flash Memory

Flash and NVM Configuration Bits Erase Command

Reset/Test

Debug Unit

AIC

PIO

Power 3V to 3.6V

Input High Pull-down resistor

Level Comments

(1)

Pull-Up resistor, Open Drain Output.

(1)

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

Table 3-1. Signal Description List (Continued)

Active

Signal Name Function Type

USB Device Port

DDM USB Device Port Data - Analog

DDP USB Device Port Data + Analog

USART

SCK0 - SCK1 Serial Clock I/O

TXD0 - TXD1 Transmit Data I/O

RXD0 - RXD1 Receive Data Input

RTS0 - RTS1 Request To Send Output

CTS0 - CTS1 Clear To Send Input

DCD1 Data Carrier Detect Input

DTR1 Data Terminal Ready Output

DSR1 Data Set Ready Input

RI1 Ring Indicator Input

Synchronous Serial Controller

TD Transmit Data Output

RD Receive Data Input

TK Transmit Clock I/O

RK Receive Clock I/O

TF Transmit Frame Sync I/O

RF Receive Frame Sync I/O

Timer/Counter

TCLK0 - TCLK2 External Clock Inputs Input

TIOA0 - TIOA2 I/O Line A I/O

TIOB0 - TIOB2 I/O Line B I/O

PWM Controller

PWM0 - PWM3 PWM Channels Output

Serial Peripheral Interface - SPIx

SPIx_MISO Master In Slave Out I/O

SPIx_MOSI Master Out Slave In I/O

SPIx_SPCK SPI Serial Clock I/O

SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low

SPIx_NPCS1-NPCS3 SPI Peripheral Chip Select 1 to 3 Output Low

Two-wire Interface

TWD Two-wire Serial Data I/O

TWCK Two-wire Serial Clock I/O

Level Comments

6209F–ATARM–17-Feb-09

Table 3-1. Signal Description List (Continued)

Active

Signal Name Function Type

Analog-to-Digital Converter

AD0-AD3 Analog Inputs Analog Digital pulled-up inputs at reset.

AD4-AD7 Analog Inputs Analog Analog Inputs

ADTRG ADC Trigger Input

ADVREF ADC Reference Analog

Fast Flash Programming Interface

PGMEN0-PGMEN1 Programming Enabling Input

PGMM0-PGMM3 Programming Mode Input

PGMD0-PGMD15 Programming Data I/O

PGMRDY Programming Ready Output High

PGMNVALID Data Direction Output Low

PGMNOE Programming Read Input Low

PGMCK Programming Clock Input

PGMNCMD Programming Command Input Low

CAN Controller

CANRX CAN Input Input

CANTX CAN Output Output

Ethernet MAC 10/100

EREFCK Reference Clock Input RMII only

ETXCK Transmit Clock Input MII only

ERXCK Receive Clock Input MII only

ETXEN Transmit Enable Output

ETX0 - ETX3 Transmit Data Output ETX0 - ETX1 only in RMII

ETXER Transmit Coding Error Output MII only

ERXDV Receive Data Valid Input MII only

ECRSDV Carrier Sense and Data Valid Input RMII only

ERX0 - ERX3 Receive Data Input ERX0 - ERX1 only in RMII

ERXER Receive Error Input

ECRS Carrier Sense Input MII only

ECOL Collision Detected Input MII only

EMDC Management Data Clock Output

EMDIO Management Data Input/Output I/O

EF100 Force 100 Mbits/sec. Output High RMII only

Level Comments

Note: 1. Refer to Section 6. ”I/O Lines Considerations”.

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

4. Package

125

5175

100

The AT91SAM7XC512/256/128 is available in 100-lead LQFP Green and 100-ball TFBGA RoHS-compliant packages.

4.1 100-lead LQFP Package Outline

Figure 4-1 shows the orientation of the 100-lead LQFP package. A detailed mechanical descrip-

tion is given in the Mechanical Characteristics section of the full datasheet.

Figure 4-1. 100-lead LQFP Package Outline (Top View)

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

4.2 100-lead LQFP Pinout

Table 4-1. Pinout in 100-lead LQFP Package

1 ADVREF 26 PA18/PGMD6 51 TDI 76 TDO 2 GND 27 PB9 52 GND 77 JTAGSEL 3 AD4 28 PB8 53 PB16 78 TMS 4 AD5 29 PB14 54 PB4 79 TCK 5 AD6 30 PB13 55 PA23/PGMD11 80 PA30 6 AD7 31 PB6 56 PA24/PGMD12 81 PA0/PGMEN0 7 VDDOUT 32 GND 57 NRST 82 PA1/PGMEN1 8 VDDIN 33 VDDIO 58 TST 83 GND

9 PB27/AD0 34 PB5 59 PA25/PGMD13 84 VDDIO 10 PB28/AD1 35 PB15 60 PA26/PGMD14 85 PA3 11 PB29/AD2 36 PB17 61 VDDIO 86 PA2 12 PB30/AD3 37 VDDCORE 62 VDDCORE 87 VDDCORE 13 PA8/PGMM0 38 PB7 63 PB18 88 PA4/PGMNCMD 14 PA9/PGMM1 39 PB12 64 PB19 89 PA5/PGMRDY 15 VDDCORE 40 PB0 65 PB20 90 PA6/PGMNOE 16 GND 41 PB1 66 PB21 91 PA7/PGMNVALID 17 VDDIO 42 PB2 67 PB22 92 ERASE 18 PA10/PGMM2 43 PB3 68 GND 93 DDM 19 PA11/PGMM3 44 PB10 69 PB23 94 DDP 20 PA12/PGMD0 45 PB11 70 PB24 95 VDDFLASH 21 PA13/PGMD1 46 PA19/PGMD7 71 PB25 96 GND 22 PA14/PGMD2 47 PA20/PGMD8 72 PB26 97 XIN/PGMCK 23 PA15/PGMD3 48 VDDIO 73 PA27/PGMD15 98 XOUT 24 PA16/PGMD4 49 PA21/PGMD9 74 PA28 99 PLLRC 25 PA17/PGMD5 50 PA22/PGMD10 75 PA29 100 VDDPLL

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

4.3 100-ball TFBGA Package Outline

ABCDEFGH JK

TOP VIEW

BALL A1

Figure 4-2 shows the orientation of the 100-ball TFBGA package. A detailed mechanical

description is given in the Mechanical Characteristics section of the full datasheet.

Figure 4-2. 100-ball TFBGA Package Orientation (Top View)

4.4 100-ball TFBGA Pinout

AT91SAM7XC512/256/128 Preliminary

Table 4-2. Pinout in 100-ball TFBGA Package

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

A1 PA22/PGMD10 C6 PB17 F1 PB21 H6 PA7/PGMNVALID

A2 PA21/PGMD9 C7 PB13 F2 PB23 H7 PA9/PGMM1

A3 PA20/PGMD8 C8 PA13/PGMD1 F3 PB25 H8 PA8/PGMM0

A4 PB1 C9 PA12/PGMD0 F4 PB26 H9 PB29/AD2

A5 PB7 C10 PA15/PGMD3 F5 TCK H10 PLLRC

A6 PB5 D1 PA23/PGMD11 F6 PA6/PGMNOE J1 PA29

A7 PB8 D2 PA24/PGMD12 F7 ERASE J2 PA30

A8 PB9 D3 NRST F8 VDDCORE J3 PA0/PGMEN0

A9 PA18/PGMD6 D4 TST F9 GND J4 PA1/PGMEN1

A10 VDDIO D5 PB19 F10 VDDIN J5 VDDFLASH

B1 TDI D6 PB6 G1 PB22 J6 GND

B2 PA19/PGMD7 D7 PA10/PGMM2 G2 PB24 J7 XIN/PGMCK

B3 PB11 D8 VDDIO G3 PA27/PGMD15 J8 XOUT

B4 PB2 D9 PB27/AD0 G4 TDO J9 GND

B5 PB12 D10 PA11/PGMM3 G5 PA2 J10 VDDPLL

B6 PB15 E1 PA25/PGMD13 G6 PA5/PGMRDY K1 VDDCORE

B7 PB14 E2 PA26/PGMD14 G7 VDDCORE K2 VDDCORE

B8 PA14/PGMD2 E3 PB18 G8 GND K3 DDP

B9 PA16/PGMD4 E4 PB20 G9 PB30/AD3 K4 DDM

B10 PA17/PGMD5 E5 TMS G10 VDDOUT K5 GND

C1 PB16 E6 GND H1 VDDCORE K6 AD7

C2 PB4 E7 VDDIO H2 PA28 K7 AD6

C3 PB10 E8 PB28/AD1 H3 JTAGSEL K8 AD5

C4 PB3 E9 VDDIO H4 PA3 K9 AD4

C5 PB0 E10 GND H5 PA4/PGMNCMD K10 ADVREF

6209F–ATARM–17-Feb-09

5. Power Considerations

5.1 Power Supplies

The AT91SAM7XC512/256/128 has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are:

• VDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V,

3.3V nominal. In order to decrease current consumption, if the voltage regulator and the ADC are not used, VDDIN, ADVREF,AD4, AD5, AD6 and AD7 should be connected to GND. In this case, VDDOUT should be left unconnected.

• VDDOUT pin. It is the output of the 1.8V voltage regulator.

• VDDIO pin. It powers the I/O lines; voltage ranges from 3.0V to 3.6V, 3.3V nominal.

• VDDFLASH pin. It powers the USB transceivers and a part of the Flash and is required for the Flash to operate correctly; voltage ranges from 3.0V to 3.6V, 3.3V nominal.

• VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V,

1.8V typical. It can be connected to the VDDOUT pin with decoupling capacitor. VDDCORE is required for the device, including its embedded Flash, to operate correctly.

• VDDPLL pin. It powers the oscillator and the PLL. It can be connected directly to the VDDOUT pin.

No separate ground pins are provided for the different power supplies. Only GND pins are provided and should be connected as shortly as possible to the system ground plane.

5.2 Power Consumption

The AT91SAM7XC512/256/128 has a static current of less than 60 µA on VDDCORE at 25°C, including the RC oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. Activating the brownout detector adds 28 µA static current.

The dynamic power consumption on VDDCORE is less than 90 mA at full speed when running out of the Flash. Under the same conditions, the power consumption on VDDFLASH does not exceed 10 mA.

5.3 Voltage Regulator

The AT91SAM7XC512/256/128 embeds a voltage regulator that is managed by the System Controller.

In Normal Mode, the voltage regulator consumes less than 100 µA static current and draws 100 mA of output current.

The voltage regulator also has a Low-power Mode. In this mode, it consumes less than 25 µA static current and draws 1 mA of output current.

Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel: one external 470 pF (or 1 nF) NPO capacitor should be connected between VDDOUT and GND as close to the chip as possible. One external 2.2 µF (or 3.3 µF) X7R capacitor should be connected between VDDOUT and GND.

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability

Power Source

ranges

from 4.5V (USB)

to 18V

3.3V

VDDIN

Voltage

Regulator

VDDOUT

VDDIO

DC/DC Converter

VDDCORE

VDDFLASH

VDDPLL

and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R.

5.4 Typical Powering Schematics

The AT91SAM7XC512/256/128 supports a 3.3V single supply mode. The internal regulator input connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. Figure 5-

1 shows the power schematics to be used for USB bus-powered systems.

Figure 5-1. 3.3V System Single Power Supply Schematic

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

6. I/O Lines Considerations

6.1 JTAG Port Pins

TMS, TDI and TCK are schmitt trigger inputs and are not 5-V tolerant. TMS, TDI and TCK do not integrate a pull-up resistor.

TDO is an output, driven at up to VDDIO, and has no pull-up resistor.

The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The JTAGSEL pin integrates a permanent pull-down resistor of about 15 kΩ.

To eliminate any risk of spuriously entering the JTAG boundary scan mode due to noise on JTAGSEL, it should be tied externally to GND if boundary scan is not used, or pulled down with an external low-value resistor (such as 1 kΩ) .

6.2 Test Pin

The TST pin is used for manufacturing test or fast programming mode of the AT91SAM7XC512/256/128 when asserted high. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND.

To eliminate any risk of entering the test mode due to noise on the TST pin, it should be tied to GND if the FFPI is not used, or pulled down with an external low-value resistor (such as 1 kΩ) .

To enter fast programming mode, the TST pin and the PA0 and PA1 pins should be tied high and PA2 tied to low.

Driving the TST pin at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results.

6.3 Reset Pin

The NRST pin is bidirectional with an open drain output buffer. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. There is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length. This allows connection of a simple push-button on the NRST pin as system user reset, and the use of the signal NRST to reset all the components of the system.

The NRST pin integrates a permanent pull-up resistor to VDDIO.

6.4 ERASE Pin

The ERASE pin is used to re-initialize the Flash content and some of its NVM bits. It integrates a permanent pull-down resistor of about 15 kΩ to GND.

To eliminate any risk of erasing the Flash due to noise on the ERASE pin, it shoul be tied externally to GND, which prevents erasing the Flash from the applicatiion, or pulled down with an external low-value resistor (such as 1 kΩ) .

This pin is debounced by the RC oscillator to improve the glitch tolerance. Minimum debouncing time is 200 ms.

6.5 PIO Controller Lines

All the I/O lines, PA0 to PA30 and PB0 to PB30, are 5V-tolerant and all integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO controllers.

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be driven with a voltage of up to 5.5V. However, driving an I/O line with a voltage over VDDIO while the programmable pull-up resistor is enabled will create a current path through the pull-up resistor from the I/O line to VDDIO. Care should be taken, in particular at reset, as all the I/O lines default to input with pull-up resistor enabled at reset.

6.6 I/O Lines Current Drawing

The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently.

The remaining I/O lines can draw only 8 mA.

However, the total current drawn by all the I/O lines cannot exceed 200 mA.

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

7. Processor and Architecture

7.1 ARM7TDMI Processor

• RISC processor based on ARMv4T Von Neumann architecture

– Runs at up to 55 MHz, providing 0.9 MIPS/MHz

• Two instruction sets

–ARM

–Thumb

• Three-stage pipeline architecture

– Instruction Fetch (F)

– Instruction

– Execute (E)

7.2 Debug and Test Features

• Integrated embedded in-circuit emulator

– Two watchpoint units

– Test access port accessible through a JTAG protocol

– Debug communication channel

• Debug Unit

–Two-pin UART

– Debug communication channel interrupt handling

– Chip ID Register

• IEEE1149.1 JTAG Boundary-scan on all digital pins

high-performance 32-bit instruction set

high code density 16-bit instruction set

Decode (D)

7.3 Memory Controller

• Programmable Bus Arbiter

• Address decoder provides selection signals for

• Abort Status Registers

• Misalignment Detector

• Remap Command

– Handles requests from the ARM7TDMI, the Ethernet MAC and the Peripheral DMA

Controller

– Three internal 1 Mbyte memory areas

– One 256 Mbyte embedded peripheral area

– Source, Type and all parameters of the access leading to an abort are saved

– Facilitates debug by detection of bad pointers

– Alignment checking of all data accesses

– Abort generation in case of misalignment

– Remaps the SRAM in place of the embedded non-volatile memory

– Allows handling of dynamic exception vectors

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

• Embedded Flash Controller

– Embedded Flash interface, up to three programmable wait states

– Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required

wait states

– Key-protected program, erase and lock/unlock sequencer

– Single command for erasing, programming and locking operations

– Interrupt generation in case of forbidden operation

7.4 Peripheral DMA Controller

• Handles data transfer between peripherals and memories

• Seventeen channels

– Two for each USART

– Two for the Debug Unit

– Two for the Serial Synchronous Controller

– Two for each Serial Peripheral Interface

– Two for the Advanced Encryption Standard 128-bit accelerator

– Two for the Triple Data Encryption Standard 128-bit accelerator

– One for the Analog-to-digital Converter

• Low bus arbitration overhead

– One Master Clock cycle needed for a transfer from memory to peripheral

– Two Master Clock cycles needed for a transfer from peripheral to memory

• Next Pointer management for reducing interrupt latency requirements

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

8. Memory

8.1 AT91SAM7XC512

• 512 Kbytes of dual-plane Flash Memory

• 128 Kbytes of Fast SRAM

8.2 AT91SAM7XC256

• 256 Kbytes of Flash Memory

• 64 Kbytes of Fast SRAM

– 2 contiguous banks of 1024 pages of 256 bytes

– Fast access time, 30 MHz single-cycle access in Worst Case conditions

– Page programming time: 6 ms, including page auto-erase

– Page programming without auto-erase: 3 ms

– Full chip erase time: 15 ms

– 10,000 write cycles, 10-year data retention capability

– 32 lock bits, protecting 32 sectors of 64 pages

– Protection Mode to secure contents of the Flash

– Single-cycle access at full speed

– 1024 pages of 256 bytes

– Fast access time, 30 MHz single-cycle access in Worst Case conditions

– Page programming time: 6 ms, including page auto-erase

– Page programming without auto-erase: 3 ms

– Full chip erase time: 15 ms

– 10,000 write cycles, 10-year data retention capability

– 16 lock bits, each protecting 16 sectors of 64 pages

– Protection Mode to secure contents of the Flash

– Single-cycle access at full speed

8.3 AT91SAM7XC128

• 128 Kbytes of Flash Memory

• 32 Kbytes of Fast SRAM

AT91SAM7XC512/256/128 Preliminary

– 512 pages of 256 bytes

– Fast access time, 30 MHz single-cycle access in Worst Case conditions

– Page programming time: 6 ms, including page auto-erase

– Page programming without auto-erase: 3 ms

– Full chip erase time: 15 ms

– 10,000 write cycles, 10-year data retention capability

– 8 lock bits, each protecting 8 sectors of 64 pages

– Protection Mode to secure contents of the Flash

– Single-cycle access at full speed

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

0x1000 0000

0x0000 0000

0x0FFF FFFF

0xF000 0000

0xEFFF FFFF

0xFFFF FFFF

256 MBytes

14 x 256 MBytes 3,584 MBytes

0x000F FFF

0x0010 0000

0x001F FFF

0x0020 0000

0x002F FFF

0x0030 0000

0x003F FFF

0x0040 0000

0x0000 0000

1 MBytes

252 MBytes

0xFFFA 0000

0xFFFA BFFF 0xFFFA C000

0xF000 0000

0xFFFB 8000

0xFFFC 0000

0xFFFC 3FFF

0xFFFC 4000

0xFFFC 7FFF

0xFFFD 4000

0xFFFD 7FFF

0xFFFD 3FFF

0xFFFD FFFF

0xFFFE 0000

0xFFFE 3FFF

0xFFFF EFFF 0xFFFE F000

0xFFFF FFFF

0xFFFE 4000

0xFFFE 8000

0xFFFE 7FFF

0xFFFB 4000

0xFFFB 7FFF

0xFFF9 FFFF

0xFFFA 3FFF

0xFFFA 7FFF

0xFFFC FFFF

0xFFFD 8000

0xFFFD BFFF

0xFFFC BFFF

0xFFFC C000

0xFFFB FFFF

0xFFFB C000

0xFFFB BFFF

0xFFFA FFFF

0xFFFB 0000

0xFFFB 3FFF

0xFFFD 0000

0xFFFD C000

0xFFFC 8000

16 Kbytes

0xFFFA 4000

16 Kbytes

0xFFFA 8000

16 Kbytes

0x0FFF FFFF

512 Bytes/128 registers

256 Bytes/64 registers

16 Bytes/4 registers

256 Bytes/64 registers

4 Bytes/1 register

512 Bytes/128 registers

0xFFFF F000

0xFFFF F200

0xFFFF F1FF

0xFFFF F3FF

0xFFFF FBFF

0xFFFF FCFF

0xFFFF FEFF

0xFFFF FFFF

0xFFFF F400

0xFFFF FC00

0xFFFF FD0F

0xFFFF FC2F

0xFFFF FC3F

0xFFFF FD4F

0xFFFF FC6F

0xFFFF F5FF

0xFFFF F600

0xFFFF F7FF

0xFFFF F800

0xFFFF FD00

0xFFFF FF00

0xFFFF FD20

0xFFFF FD30

0xFFFF FD40

0xFFFF FD60

0xFFFF FD70

Internal Memories

Undefined

(Abort)

(1) Can be ROM, Flash or SRAM depending on GPNVM2 and REMAP

Flash before Remap

SRAM after Remap

Internal Flash

Internal SRAM

Internal ROM

Reserved

Boot Memory (1)

Address Memory Space

Internal Memory Mapping

Note:

TC0, TC1, TC2

AES 128

TDES

USART0

USART1

PWMC

Reserved

ReservedReserved

CAN

EMAC

Reserved

TWI

SSC

SPI0

SPI1

UDP

ADC

AIC

DBGU

PIOA

Reserved

PMC

WDT

PIT

RTT

RSTC

VREG

PIOB

Peripheral Mapping

System Controller Mapping

Internal Peripherals

Reserved

SYSC

Figure 8-1. AT91SAM7XC512/256/128 Memory Mapping

6209F–ATARM–17-Feb-09

8.4 Memory Mapping

256M Bytes

ROM Before Remap

SRAM After Remap

Undefined Areas

(Abort)

0x000F FFFF

0x001F FFFF

0x002F FFFF

0x0FFF FFFF

1 M Bytes

252 M Bytes

Internal FLASH

Internal SRAM

0x0000 0000

0x0010 0000

0x0020 0000

0x0030 0000

Internal ROM

0x003F FFFF 0x0040 0000

1 M Bytes

8.4.1 Internal RAM

• The AT91SAM7XC512 embeds a high-speed 128-Kbyte SRAM bank.

• The AT91SAM7XC256 embeds a high-speed 64-Kbyte SRAM bank.

• The AT91SAM7XC128 embeds a high-speed 32-Kbyte SRAM bank.

After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0.

8.4.2 Internal ROM

The AT91SAM7XC512/256/128 embeds an Internal ROM. At any time, the ROM is mapped at address 0x30 0000. The ROM contains the FFPI and the SAM-BA program.

8.4.3 Internal Flash

• The AT91SAM7XC512 features two banks (dual plane) of 256 Kbytes of Flash.

• The AT91SAM7XC256 features one bank (single plane) of 256 Kbytes of Flash.

• The AT91SAM7XC128 features one bank (single plane) of 128 Kbytes of Flash.

At any time, the Flash is mapped to address 0x0010 0000. It is also accessible at address 0x0 after the reset, if GPNVM bit 2 is set and before the Remap Command.

A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the Flash.

This GPNVM bit can be cleared or set respectively through the commands “Clear General-purpose NVM Bit” and “Set General-purpose NVM Bit” of the EFC User Interface.

Setting the GPNVM Bit 2 selects the boot from the Flash. Asserting ERASE clears the GPNVM Bit 2 and thus selects the boot from the ROM by default.

Figure 8-2. Internal Memory Mapping with GPNVM Bit 2 = 0 (default)

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

Figure 8-3. Internal Memory Mapping with GPNVM Bit 2 = 1

256M Bytes

Flash Before Remap

SRAM After Remap

Undefined Areas

(Abort)

0x000F FFFF

0x001F FFFF

0x002F FFFF

0x0FFF FFFF

1 M Bytes

252 M Bytes

Internal FLASH

Internal SRAM

0x0000 0000

0x0010 0000

0x0020 0000

0x0030 0000

Internal ROM

0x003F FFFF 0x0040 0000

1 M Bytes

8.5 Embedded Flash

8.5.1 Flash Overview

The Flash contains a 256-byte write buffer, accessible through a 32-bit interface.

AT91SAM7XC512/256/128 Preliminary

• The Flash of the AT91SAM7XC512 is organized in two banks (dual plane) 0f 1254 pages of 256 bytes. The 524, 288 bytes are organized in 32-bit words.

• The Flash of the AT91SAM7XC256 is organized in 1024 pages of 256 bytes (single plane). It reads as 65,536 32-bit words.

• The Flash of the AT91SAM7XC128 is organized in 512 pages of 256 bytes (single plane). It reads as 32,768 32-bit words.

The Flash benefits from the integration of a power reset cell and from the brownout detector. This prevents code corruption during power supply changes, even in the worst conditions.

When Flash is not used (read or write access), it is automatically placed into standby mode.

8.5.2 Embedded Flash Controller

The Embedded Flash Controller (EFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped within the Memory Controller on the APB. The User Interface allows:

• programming of the access parameters of the Flash (number of wait states, timings, etc.)

• starting commands such as full erase, page erase, page program, NVM bit set, NVM bit clear, etc.

• getting the end status of the last command

6209F–ATARM–17-Feb-09

• getting error status

• programming interrupts on the end of the last commands or on errors

The Embedded Flash Controller also provides a dual 32-bit Prefetch Buffer that optimizes 16-bit access to the Flash. This is particularly efficient when the processor is running in Thumb mode.

Two EFCs are embedded in the AT91SAM7XC512 to control each bank of 256 KBytes. Dualplane organization allows concurrent read and program functionality. Read from one memory

plane may be performed even while program or erase functions are being executed in the other memory plane.

One EFC is embedded in the AT91SAM7XC256/128 to control the single plane of 256/128 KBytes.

8.5.3 Lock Regions

8.5.3.1 AT91SAM7XC512

Two Embedded Flash Controllers each manage 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7XC512 contains 32 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes.

If a locked-region’s erase or program command occurs, the command is aborted and the EFC trigs an interrupt.

The 32 NVM bits are software programmable through both of the EFC User Interfaces. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.

Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

8.5.3.2 AT91SAM7XC256

The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7XC256 contains 16 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes.

If a locked-region’s erase or program command occurs, the command is aborted and the EFC trigs an interrupt.

The 16 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.

Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

8.5.3.3 AT91SAM7XC128

The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7XC128 contains 8 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes.

If a locked-region’s erase or program command occurs, the command is aborted and the EFC trigs an interrupt.

The 8 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.

Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

8.5.4 Security Bit Feature

The AT91SAM7XC512/256/128 features a security bit, based on a specific NVM-Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash.

This security bit can only be enabled, through the Command “Set Security Bit” of the EFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full flash erase is performed. When the security bit is deactivated, all accesses to the flash are permitted.

It is important to note that the assertion of the ERASE pin should always be longer than 220 ms.

As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is safer to connect it directly to GND for the final application.

8.5.5 Non-volatile Brownout Detector Control

Two general purpose NVM (GPNVM) bits are used for controlling the brownout detector (BOD), so that even after a power loss, the brownout detector operations remain in their state.

These two GPNVM bits can be cleared or set respectively through the commands “Clear General-purpose NVM Bit” and “Set General-purpose NVM Bit” of the EFC User Interface.

• GPNVM Bit 0 is used as a brownout detector enable bit. Setting the GPNVM Bit 0 enables the BOD, clearing it disables the BOD. Asserting ERASE clears the GPNVM Bit 0 and thus disables the brownout detector by default.

• The GPNVM Bit 1 is used as a brownout reset enable signal for the reset controller. Setting the GPNVM Bit 1 enables the brownout reset when a brownout is detected, Clearing the GPNVM Bit 1 disables the brownout reset. Asserting ERASE disables the brownout reset by default.

8.5.6 Calibration Bits

Eight NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits.

8.6 Fast Flash Programming Interface

The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang-programming with market-standard industrial programmers.

The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands.

The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin and the PA0 and PA1 pins are all tied high.

8.7 SAM-BA Boot Assistant

The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program insitu the on-chip Flash memory.

The SAM-BA Boot Assistant supports serial communication via the DBGU or the USB Device Port.

• Communication via the DBGU supports a wide range of crystals from 3 to 20 MHz via software auto-detection.

6209F–ATARM–17-Feb-09

• Communication via the USB Device Port is limited to an 18.432 MHz crystal.

The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).

The SAM-BA Boot is in ROM and is mapped at address 0x0 when the GPNVM Bit 2 is set to 0.

When GPNVM bit 2 is set to 1, the device boots from the Flash.

When GPNVM bit 2 is set to 0, the device boots from ROM (SAM-BA).

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

9. System Controller

The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset.

The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF.

Figure 9-1 on page 26 shows the System Controller Block Diagram.

Figure 8-1 on page 19 shows the mapping of the User Interface of the System Controller periph-

erals. Note that the Memory Controller configuration user interface is also mapped within this address space.

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

Figure 9-1. System Controller Block Diagram

NRST

SLCK

Advanced

Interrupt

Controller

Real-Time

Timer

Periodic

Interval

Timer

Reset

Controller

PA0-PA30

periph_nreset

System Controller

Watchdog

Timer

wdt_fault WDRPROC

PIO

Controller

POR

BOD

RCOSC

gpnvm[0]

cal

Power

Management

Controller

OSC

PLL

XIN

XOUT

PLLRC

MAINCK

PLLCK

pit_irq

MCK

proc_nreset

wdt_irq

periph_irq{2-3]

periph_nreset

periph_clk[2..18]

PCK

MCK

pmc_irq

UDPCK

nirq

nfiq

rtt_irq

Embedded Peripherals

periph_clk[2-3]

pck[0-3]

out

enable

ARM7TDMI

SLCK

irq0-irq1

fiq

irq0-irq1

fiq

periph_irq[4..19]

periph_irq[2..19]

int

periph_nreset

periph_clk[4..19]

Embedded

Flash

flash_poe

jtag_nreset

flash_poe

gpnvm[0..2]

flash_wrdis

proc_nreset

periph_nreset

dbgu_txd

dbgu_rxd

pit_irq rtt_irq

dbgu_irq

pmc_irq

rstc_irq

wdt_irq

rstc_irq

efc_irq

SLCK

gpnvm[1]

Boundary Scan

TAP Controller

jtag_nreset

power_on_reset

debug

PCK

debug

idle

debug

Memory

Controller

MCK

proc_nreset

bod_rst_en

proc_nreset

periph_nreset

idle

Debug

Unit

dbgu_irq

MCK

dbgu_rxd

periph_nreset

force_ntrst

dbgu_txd

USB Device

Por t

UDPCK

periph_nreset

periph_clk[11]

periph_irq[11]

usb_suspend

Voltage

Regulator

standby

Voltage

Regulator

Mode

Controller

security_bit

cal

power_on_reset

force_ntrst

cal

PB0-PB30

efc_irq

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

9.1 Reset Controller

• Based on one power-on reset cell and one brownout detector

• Status of the last reset, either Power-up Reset, Software Reset, User Reset, Watchdog Reset, Brownout Reset

• Controls the internal resets and the NRST pin output

• Allows to shape a signal on the NRST line, guaranteeing that the length of the pulse meets any requirement.

9.1.1 Brownout Detector and Power-on Reset

The AT91SAM7XC512/256/128 embeds one brownout detection circuit and a power-on reset cell. The power-on reset is supplied with and monitors VDDCORE.

Both signals are provided to the Flash to prevent any code corruption during power-up or powerdown sequences or if brownouts occur on the power supplies.

The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its output remains low during power-up until VDDCORE goes over this voltage level. This signal goes to the reset controller and allows a full re-initialization of the device.

The brownout detector monitors the VDDCORE and VDDFLASH levels during operation by comparing them to a fixed trigger level. It secures system operations in the most difficult environments and prevents code corruption in case of brownout on the VDDCORE or VDDFLASH.

When the brownout detector is enabled and VDDCORE decreases to a value below the trigger level (Vbot18-, defined as Vbot18 - hyst/2), the brownout output is immediately activated.

When VDDCORE increases above the trigger level (Vbot18+, defined as Vbot18 + hyst/2), the reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer than about 1µs.

The VDDCORE threshold voltage has a hysteresis of about 50 mV, to ensure spike free brownout detection. The typical value of the brownout detector threshold is 1.68V with an accuracy of ± 2% and is factory calibrated.

When the brownout detector is enabled and VDDFLASH decreases to a value below the trigger level (Vbot33-, defined as Vbot33 - hyst/2), the brownout output is immediately activated.

When VDDFLASH increases above the trigger level (Vbot33+, defined as Vbot33 + hyst/2), the reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer than about 1µs.

The VDDFLASH threshold voltage has a hysteresis of about 50 mV, to ensure spike free brownout detection. The typical value of the brownout detector threshold is 2.80V with an accuracy of ± 3.5% and is factory calibrated.

The brownout detector is low-power, as it consumes less than 28 µA static current. However, it can be deactivated to save its static current. In this case, it consumes less than 1µA. The deactivation is configured through the GPNVM bit 0 of the Flash.

6209F–ATARM–17-Feb-09

9.2 Clock Generator

Embedded

Oscillator

Main

Oscillator

PLL and

Divider

Clock Generator

Power

Management

Controller

XIN

XOUT

PLLRC

Slow Clock SLCK

Main Clock MAINCK

PLL Clock PLLCK

Control

Status

The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics:

It provides SLCK, MAINCK and PLLCK.

Figure 9-2. Clock Generator Block Diagram

• RC Oscillator ranges between 22 KHz and 42 KHz

• Main Oscillator frequency ranges between 3 and 20 MHz

• Main Oscillator can be bypassed

• PLL output ranges between 80 and 200 MHz

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

9.3 Power Management Controller

MCK

periph_clk[2..18]

int

UDPCK

SLCK

MAINCK

PLLCK

Prescaler

/1,/2,/4,...,/64

PCK

Processor

Clock

Controller

Idle Mode

Master Clock Controller

Peripherals

Clock Controller

ON/OFF

USB Clock Controller

ON/OFF

SLCK

MAINCK

PLLCK

Prescaler

/1,/2,/4,...,/64

Programmable Clock Controller

PLLCK

Divider /1,/2,/4

pck[0..3]

The Power Management Controller uses the Clock Generator outputs to provide:

• the Processor Clock PCK

• the Master Clock MCK

• the USB Clock UDPCK

• all the peripheral clocks, independently controllable

• four programmable clock outputs

The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating frequency of the device.

The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing reduced power consumption while waiting for an interrupt.

Figure 9-3. Power Management Controller Block Diagram

AT91SAM7XC512/256/128 Preliminary

9.4 Advanced Interrupt Controller

• Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor

• Individually maskable and vectored interrupt sources

6209F–ATARM–17-Feb-09

– Source 0 is reserved for the Fast Interrupt Input (FIQ)

– Source 1 is reserved for system peripherals (RTT, PIT, EFC, PMC, DBGU, etc.)

– Other sources control the peripheral interrupts or external interrupts

– Programmable edge-triggered or level-sensitive internal sources

– Programmable positive/negative edge-triggered or high/low level-sensitive external

sources

• 8-level Priority Controller

– Drives the normal interrupt nIRQ of the processor

– Handles priority of the interrupt sources

9.5 Debug Unit

– Higher priority interrupts can be served during service of lower priority interrupt

• Vectoring

– Optimizes interrupt service routine branch and execution

– One 32-bit vector register per interrupt source

– Interrupt vector register reads the corresponding current interrupt vector

•Protect Mode

– Easy debugging by preventing automatic operations

•Fast Forcing

– Permits redirecting any interrupt source on the fast interrupt

• General Interrupt Mask

– Provides processor synchronization on events without triggering an interrupt

• Comprises:

– One two-pin UART

– One Interface for the Debug Communication Channel (DCC) support

– One set of Chip ID Registers

– One Interface providing ICE Access Prevention

•Two-pin UART

– USART-compatible User Interface

– Programmable Baud Rate Generator

– Parity, Framing and Overrun Error

– Automatic Echo, Local Loopback and Remote Loopback Channel Modes

• Debug Communication Channel Support

– Offers visibility of COMMRX and COMMTX signals from the ARM Processor

• Chip ID Registers

– Identification of the device revision, sizes of the embedded memories, set of

peripherals

– Chip ID is 0x271C 0A40 (VERSION 0) for AT91SAM7XC512

– Chip ID is 0x271B 0940 (VERSION 0) for AT91SAM7XC256

– Chip ID is 0x271A 0740 (VERSION 0) for AT91SAM7XC128

9.6 Periodic Interval Timer

• 20-bit programmable counter plus 12-bit interval counter

9.7 Watchdog Timer

• 12-bit key-protected Programmable Counter running on prescaled SLCK

• Provides reset or interrupt signals to the system

• Counter may be stopped while the processor is in debug state or in idle mode

9.8 Real-time Timer

• 32-bit free-running counter with alarm running on prescaled SLCK

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

• Programmable 16-bit prescaler for SLCK accuracy compensation

9.9 PIO Controllers

• Two PIO Controllers, each controlling 31 I/O lines

• Fully programmable through set/clear registers

• Multiplexing of two peripheral functions per I/O line

• For each I/O line (whether assigned to a peripheral or used as general-purpose I/O)

– Input change interrupt

– Half a clock period glitch filter

– Multi-drive option enables driving in open drain

– Programmable pull-up on each I/O line

– Pin data status register, supplies visibility of the level on the pin at any time

• Synchronous output, provides Set and Clear of several I/O lines in a single write

9.10 Voltage Regulator Controller

The purpose of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set).

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

10. Peripherals

10.1 User Interface

The User Peripherals are mapped in the 256 MBytes of address space between 0xF000 0000 and 0xFFFE FFFF. Each peripheral is allocated 16 Kbytes of address space.

A complete memory map is provided in Figure 8-1 on page 19.

10.2 Peripheral Identifiers

The AT91SAM7XC512/256/128 embeds a wide range of peripherals. Table 10-1 defines the Peripheral Identifiers of the AT91SAM7XC512/256/128. Unique peripheral identifiers are defined for both the Advanced Interrupt Controller and the Power Management Controller.

Table 10-1. Peripheral Identifiers

Peripheral ID Peripheral Mnemonic Peripheral Name

0 AIC Advanced Interrupt Controller FIQ

1 SYSC

2 PIOA Parallel I/O Controller A

3 PIOB Parallel I/O Controller B

4 SPI0 Serial Peripheral Interface 0

5 SPI1 Serial Peripheral Interface 1

6 US0 USART 0

7 US1 USART 1

8 SSC Synchronous Serial Controller

9 TWI Two-wire Interface

10 PWMC Pulse Width Modulation Controller

11 UDP USB device Port

12 TC0 Timer/Counter 0

13 TC1 Timer/Counter 1

14 TC2 Timer/Counter 2

15 CAN CAN Controller

16 EMAC Ethernet MAC

17 ADC

18 AES Advanced Encryption Standard 128-bit

19 TDES Triple Data Encryption Standard

20-29 Reserved

30 AIC Advanced Interrupt Controller IRQ0

31 AIC Advanced Interrupt Controller IRQ1

External Interrupt

(1)

System

Analog-to Digital Converter

Note: 1. Setting SYSC and ADC bits in the clock set/clear registers of the PMC has no effect. The Sys-

tem Controller and ADC are continuously clocked.

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

10.3 Peripheral Multiplexing on PIO Lines

The AT91SAM7XC512/256/128 features two PIO controllers, PIOA and PIOB, that multiplex the I/O lines of the peripheral set.

Each PIO Controller controls 31 lines. Each line can be assigned to one of two peripheral functions, A or B. Some of them can also be multiplexed with the analog inputs of the ADC Controller.

Table 10-2 on page 34 and Table 10-3 on page 35 defines how the I/O lines of the peripherals A,

B or the analog inputs are multiplexed on the PIO Controller A and PIO Controller B. The two columns “Function” and “Comments” have been inserted for the user’s own comments; they may be used to track how pins are defined in an application.

Note that some peripheral functions that are output only, may be duplicated in the table.

At reset, all I/O lines are automatically configured as input with the programmable pull-up enabled, so that the device is maintained in a static state as soon as a reset is detected.

6209F–ATARM–17-Feb-09

10.4 PIO Controller A Multiplexing

Table 10-2. Multiplexing on PIO Controller A

PIO Controller A Application Usage

I/O Line Peripheral A Peripheral B Comments Function Comments

PA0 RXD0 High-Drive

PA1 TXD0 High-Drive

PA2 SCK0 SPI1_NPCS1 High-Drive

PA3 RTS0 SPI1_NPCS2 High-Drive

PA4 CTS0 SPI1_NPCS3

PA 5 R XD 1

PA 6 T X D 1

PA7 SCK1 SPI0_NPCS1

PA8 RTS1 SPI0_NPCS2

PA9 CTS1 SPI0_NPCS3

PA 10 T W D

PA 11 T W C K

PA12 SPI_NPCS0

PA13 SPI0_NPCS1 PCK1

PA14 SPI0_NPCS2 IRQ1

PA15 SPI0_NPCS3 TCLK2

PA16 SPI0_MISO

PA17 SPI0_MOSI

PA18 SPI0_SPCK

PA19 CANRX

PA20 CANTX

PA21 TF SPI1_NPCS0

PA22 TK SPI1_SPCK

PA23 TD SPI1_MOSI

PA24 RD SPI1_MISO

PA25 RK SPI1_NPCS1

PA26 RF SPI1_NPCS2

PA27 DRXD PCK3

PA 28 D T X D

PA29 FIQ SPI1_NPCS3

PA 30

IRQ0 PCK2

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

10.5 PIO Controller B Multiplexing

Table 10-3. Multiplexing on PIO Controller B

PIO Controller B Application Usage

I/O Line Peripheral A Peripheral B Comments Function Comments

PB0 ETXCK/EREFCK PCK0

PB1 ETXEN

PB2 ETX0

PB3 ETX1

PB4 ECRS

PB5 ERX0

PB6 ERX1

PB7 ERXER

PB8 EMDC

PB9 EMDIO

PB10 ETX2 SPI1_NPCS1

PB11 ETX3 SPI1_NPCS2

PB12 ETXER TCLK0

PB13 ERX2 SPI0_NPCS1

PB14 ERX3 SPI0_NPCS2

PB15 ERXDV/ECRSDV

PB16 ECOL SPI1_NPCS3

PB17 ERXCK SPI0_NPCS3

PB18 EF100 ADTRG

PB19 PWM0 TCLK1

PB20 PWM1 PCK0

PB21 PWM2 PCK1

PB22 PWM3 PCK2

PB23 TIOA0 DCD1

PB24 TIOB0 DSR1

PB25 TIOA1 DTR1

PB26 TIOB1 RI1

PB27 TIOA2 PWM0 AD0

PB28 TIOB2 PWM1 AD1

PB29 PCK1 PWM2 AD2

PB30 PCK2 PWM3 AD3

6209F–ATARM–17-Feb-09

10.6 Ethernet MAC

• DMA Master on Receive and Transmit Channels

• Compatible with IEEE Standard 802.3

• 10 and 100 Mbit/s operation

• Full- and half-duplex operation

• Statistics Counter Registers

• MII/RMII interface to the physical layer

• Interrupt generation to signal receive and transmit completion

• 28-byte transmit FIFO and 28-byte receive FIFO

• Automatic pad and CRC generation on transmitted frames

• Automatic discard of frames received with errors

• Address checking logic supports up to four specific 48-bit addresses

• Support Promiscuous Mode where all valid received frames are copied to memory

• Hash matching of unicast and multicast destination addresses

• Physical layer management through MDIO interface

• Half-duplex flow control by forcing collisions on incoming frames

• Full-duplex flow control with recognition of incoming pause frames

• Support for 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged frames

• Multiple buffers per receive and transmit frame

• Jumbo frames up to 10240 bytes supported

10.7 Serial Peripheral Interface

• Supports communication with external serial devices

– Four chip selects with external decoder allow communication with up to 15

peripherals

– Serial memories, such as DataFlash

– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and

Sensors

– External co-processors

• Master or slave serial peripheral bus interface

– 8- to 16-bit programmable data length per chip select

– Programmable phase and polarity per chip select

– Programmable transfer delays per chip select, between consecutive transfers and

between clock and data

– Programmable delay between consecutive transfers

– Selectable mode fault detection

– Maximum frequency at up to Master Clock

and 3-wire EEPROMs

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

10.8 Two-wire Interface

• Master Mode only

• Compatibility with I

• One, two or three bytes internal address registers for easy Serial Memory access

• 7-bit or 10-bit slave addressing

• Sequential read/write operations

10.9 USART

• Programmable Baud Rate Generator

• 5- to 9-bit full-duplex synchronous or asynchronous serial communications

• RS485 with driver control signal

• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards

• IrDA modulation and demodulation

• Test Modes

AT91SAM7XC512/256/128 Preliminary

C compatible devices (refer to the TWI section of the datasheet)

– 1, 1.5 or 2 stop bits in Asynchronous Mode

– 1 or 2 stop bits in Synchronous Mode

– Parity generation and error detection

– Framing error detection, overrun error detection

– MSB or LSB first

– Optional break generation and detection

– By 8 or by 16 over-sampling receiver frequency

– Hardware handshaking RTS - CTS

– Modem Signals Management DTR-DSR-DCD-RI on USART1

– Receiver time-out and transmitter timeguard

– Multi-drop Mode with address generation and detection

– NACK handling, error counter with repetition and iteration limit

– Communication at up to 115.2 Kbps

– Remote Loopback, Local Loopback, Automatic Echo

10.10 Serial Synchronous Controller

• Provides serial synchronous communication links used in audio and telecom applications

• Contains an independent receiver and transmitter and a common clock divider

• Offers a configurable frame sync and data length

• Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal

• Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal

6209F–ATARM–17-Feb-09

10.11 Timer Counter

• Three 16-bit Timer Counter Channels

– Two output compare or one input capture per channel

• Wide range of functions including:

– Frequency measurement

– Event counting

– Interval measurement

– Pulse generation

– Delay timing

– Pulse Width Modulation

– Up/down capabilities

• Each channel is user-configurable and contains:

– Three external clock inputs

• Five internal clock inputs, as defined in Table 10-4

Table 10-4. Timer Counter Clocks Assignment

TC Clock input Clock

TIMER_CLOCK1 MCK/2

TIMER_CLOCK2 MCK/8

TIMER_CLOCK3 MCK/32

TIMER_CLOCK4 MCK/128

TIMER_CLOCK5 MCK/1024

– Two multi-purpose input/output signals

– Two global registers that act on all three TC channels

10.12 Pulse Width Modulation Controller

• Four channels, one 16-bit counter per channel

• Common clock generator, providing thirteen different clocks

– One Modulo n counter providing eleven clocks

– Two independent linear dividers working on modulo n counter outputs

• Independent channel programming

– Independent enable/disable commands

– Independent clock selection

– Independent period and duty cycle, with double buffering

– Programmable selection of the output waveform polarity

– Programmable center or left aligned output waveform

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

10.13 USB Device Port

10.14 CAN Controller

• Fully compliant with CAN 2.0A and 2.0B

• Bit rates up to 1Mbit/s

• Eight object oriented mailboxes each with the following properties:

AT91SAM7XC512/256/128 Preliminary

• USB V2.0 full-speed compliant,12 Mbits per second

• Embedded USB V2.0 full-speed transceiver

• Embedded 1352-byte dual-port RAM for endpoints

• Six endpoints

– Endpoint 0: 8 bytes

– Endpoint 1 and 2: 64 bytes ping-pong

– Endpoint 3: 64 bytes

– Endpoint 4 and 5: 256 bytes ping-pong

– Ping-pong Mode (two memory banks) for bulk endpoints

• Suspend/resume logic

– CAN Specification 2.0 Part A or 2.0 Part B Programmable for each Message

– Object configurable to receive (with overwrite or not) or transmit

– Local tag and mask filters up to 29-bit identifier/channel

– 32-bit access to data registers for each mailbox data object

– Uses a 16-bit time stamp on receive and transmit message

– Hardware concatenation of ID unmasked bitfields to speedup family ID processing

– 16-bit internal timer for time stamping and network synchronization

– Programmable reception buffer length up to 8 mailbox objects

– Priority management between transmission mailboxes

– Autobaud and listening mode

– Low power mode and programmable wake-up on bus activity or by the application

– Data, remote, error and overload frame handling

10.15 128-bit Advanced Encryption Standard

• Compliant with FIPS Publication 197, Advanced Encryption Standard (AES)

• 128-bit (AT91SAM7XC256/128) or 128-bit/192-bit/256-bit (AT91SAM7XC512) Cryptographic Key

• 12-clock Cycles Encryption/Decryption Processing Time (AT91SAM7XC256/128)

• 12/13/14-clock Cycles Encryption/Decryption Processing Time (AT91SAM7XC512)

• Support of the Five Standard Modes of Operation specified in the NIST Special Publication 800-38A:

– Electronic Codebook (ECB)

– Cipher Block Chaining (CBC)

– Cipher Feedback (CFB)

– Output Feedback (OFB)

6209F–ATARM–17-Feb-09

– Counter (CTR)

• 8-, 16-, 32-, 64- and 128-bit Data Sizes Possible in CFB Mode

• Last Output Data Mode allowing Message Authentication Code (MAC) generation

• Hardware Countermeasures against Differential Power Analysis attacks

• Connection to PDC Channel Capabilities Optimizes Data Transfers for all Operating Modes:

– One Channel for the Receiver, One Channel for the Transmitter

– Next Buffer Support

10.16 Triple Data Encryption Standard

• Single Data Encryption Standard (DES) and Triple Data Encryption

• Algorithm (TDEA or TDES) supports

• Compliant with FIPS Publication 46-3, Data Encryption Standard (DES)

• 64-bit Cryptographic Key

• Two-key or Three-key Algorithms

• 18-clock Cycles Encryption/Decryption Processing Time for DES

• 50-clock Cycles Encryption/Decryption Processing Time for TDES

• Support the Four Standard Modes of Operation specified in the FIPS Publication 81, DES

• Modes of Operation:

– Electronic Codebook (ECB)

– Cipher Block Chaining (CBC)

– Cipher Feedback (CFB)

– Output Feedback (OFB)

• 8-, 16-, 32- and 64- Data Sizes Possible in CFB Mode

• Last Output Data Mode allowing Optimized Message (Data) Authentication Code (MAC) generation

• Connection to PDC Channel Capabilities Optimizes Data Transfers for all Operating Modes:

– One Channel for the Receiver, One Channel for the Transmitter

– Next Buffer Support

10.17 Analog-to-Digital Converter

• 8-channel ADC

• 10-bit 384 Ksamples/sec. Successive Approximation Register ADC

• ±2 LSB Integral Non Linearity, ±1 LSB Differential Non Linearity

• Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs

• External voltage reference for better accuracy on low voltage inputs

• Individual enable and disable of each channel

• Multiple trigger sources

– Hardware or software trigger

– External trigger pin

– Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger

• Sleep Mode and conversion sequencer

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

– Automatic wakeup on trigger and back to sleep mode after conversions of all

enabled channels

• Four of eight analog inputs shared with digital signals

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

11. ARM7TDMI Processor Overview

11.1 Overview

The ARM7TDMI core executes both the 32-bit ARM® and 16-bit Thumb® instruction sets, allowing the user to trade off between high performance and high code density.The ARM7TDMI processor implements Von Neuman architecture, using a three-stage pipeline consisting of Fetch, Decode, and Execute stages.

The main features of the ARM7tDMI processor are:

• ARM7TDMI Based on ARMv4T Architecture

• Two Instruction Sets

–ARM

–Thumb

• Three-Stage Pipeline Architecture

– Instruction Fetch (F)

– Instruction

– Execute (E)

High-performance 32-bit Instruction Set

High Code Density 16-bit Instruction Set

Decode (D)

6209F–ATARM–17-Feb-09

11.2 ARM7TDMI Processor

For further details on ARM7TDMI, refer to the following ARM documents:

ARM Architecture Reference Manual (DDI 0100E)

ARM7TDMI Technical Reference Manual (DDI 0210B)

11.2.1 Instruction Type

Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state).

11.2.2 Data Type

ARM7TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to four-byte boundaries and half words to two-byte boundaries.

Unaligned data access behavior depends on which instruction is used where.

11.2.3 ARM7TDMI Operating Mode

The ARM7TDMI, based on ARM architecture v4T, supports seven processor modes:

User: The normal ARM program execution state

FIQ: Designed to support high-speed data transfer or channel process

IRQ: Used for general-purpose interrupt handling

Supervisor: Protected mode for the operating system

Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User mode. The non-user modes, or privileged modes, are entered in order to service interrupts or exceptions, or to access protected resources.

11.2.4 ARM7TDMI Registers

The ARM7TDMI processor has a total of 37registers:

• 31 general-purpose 32-bit registers

• 6 status registers

These registers are not accessible at the same time. The processor state and operating mode determine which registers are available to the programmer.

At any one time 16 registers are visible to the user. The remainder are synonyms used to speed up exception processing.

Register 15 is the Program Counter (PC) and can be used in all instructions to reference data relative to the current instruction.

R14 holds the return address after a subroutine call.

Abort mode: Implements virtual memory and/or memory protection

System: A privileged user mode for the operating system

Undefined: Supports software emulation of hardware coprocessors

R13 is used (by software convention) as a stack pointer.

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

Table 11-1. ARM7TDMI ARM Modes and Registers Layout

User and System Mode

R0 R0 R0 R0 R0 R0

R1 R1 R1 R1 R1 R1

R2 R2 R2 R2 R2 R2

R3 R3 R3 R3 R3 R3

R4 R4 R4 R4 R4 R4

R5 R5 R5 R5 R5 R5

R6 R6 R6 R6 R6 R6

R7 R7 R7 R7 R7 R7

R8 R8 R8 R8 R8

R9 R9 R9 R9 R9 R9_FIQ

R10 R10 R10 R10 R10

R11 R11 R11 R11 R11

R12 R12 R12 R12 R12 R12_FIQ

R13 R13_SVC R13_ABORT R13_UNDEF R13_IRQ R13_FIQ

R14 R14_SVC R14_ABORT R14_UNDEF R14_IRQ R14_FIQ

PC PC PC PC PC PC

Supervisor Mode Abort Mode

Undefined Mode

Interrupt Mode

Fast Interrupt Mode

R8_FIQ

R10_FIQ

R11_FIQ

CPSR CPSR CPSR CPSR CPSR CPSR

Registers R0 to R7 are unbanked registers. This means that each of them refers to the same 32bit physical register in all processor modes. They are general-purpose registers, with no special uses managed by the architecture, and can be used wherever an instruction allows a generalpurpose register to be specified.

Registers R8 to R14 are banked registers. This means that each of them depends on the current mode of the processor.

11.2.4.1 Modes and Exception Handling

All exceptions have banked registers for R14 and R13.

After an exception, R14 holds the return address for exception processing. This address is used to return after the exception is processed, as well as to address the instruction that caused the exception.

R13 is banked across exception modes to provide each exception handler with a private stack pointer.

The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without having to save these registers.

SPSR_SVC SPSR_ABORT SPSR_UNDEF SPSR_IRQ SPSR_FIQ

Mode-specific banked registers

6209F–ATARM–17-Feb-09

A seventh processing mode, System Mode, does not have any banked registers. It uses the User Mode registers. System Mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions.

11.2.4.2 Status Registers

All other processor states are held in status registers. The current operating processor status is in the Current Program Status Register (CPSR). The CPSR holds:

• four ALU flags (Negative, Zero, Carry, and Overflow)

• two interrupt disable bits (one for each type of interrupt)

• one bit to indicate ARM or Thumb execution

• five bits to encode the current processor mode

All five exception modes also have a Saved Program Status Register (SPSR) that holds the CPSR of the task immediately preceding the exception.

11.2.4.3 Exception Types

The ARM7TDMI supports five types of exception and a privileged processing mode for each type.

The types of exceptions are:

• fast interrupt (FIQ)

• normal interrupt (IRQ)

• memory aborts (used to implement memory protection or virtual memory)

• attempted execution of an undefined instruction

• software interrupts (SWIs)

Exceptions are generated by internal and external sources.

More than one exception can occur in the same time.

When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save state.

To return after handling the exception, the SPSR is moved to the CPSR, and R14 is moved to the PC. This can be done in two ways:

• by using a data-processing instruction with the S-bit set, and the PC as the destination

• by using the Load Multiple with Restore CPSR instruction (LDM)

11.2.5 ARM Instruction Set Overview

The ARM instruction set is divided into:

• Branch instructions

• Data processing instructions

• Status register transfer instructions

• Load and Store instructions

• Coprocessor instructions

• Exception-generating instructions

ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bit[31:28]).

Table 11-2 gives the ARM instruction mnemonic list.

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

Table 11-2. ARM Instruction Mnemonic List

Mnemonic Operation Mnemonic Operation

MOV Move CDP Coprocessor Data Processing

ADD Add MVN Move Not

SUB Subtract ADC Add with Carry

RSB Reverse Subtract SBC Subtract with Carry

CMP Compare RSC Reverse Subtract with Carry

TST Test CMN Compare Negated

AND Logical AND TEQ Test Equivalence

EOR Logical Exclusive OR BIC Bit Clear

MUL Multiply ORR Logical (inclusive) OR

SMULL Sign Long Multiply MLA Multiply Accumulate

SMLAL Signed Long Multiply Accumulate UMULL Unsigned Long Multiply

MSR Move to Status Register UMLAL Unsigned Long Multiply Accumulate

B Branch MRS Move From Status Register

BX Branch and Exchange BL Branch and Link

LDR Load Word SWI Software Interrupt

LDRSH Load Signed Halfword STR Store Word

LDRSB Load Signed Byte STRH Store Half Word

LDRH Load Half Word STRB Store Byte

LDRB Load Byte STRBT Store Register Byte with Translation

LDRBT Load Register Byte with Translation STRT Store Register with Translation

LDRT Load Register with Translation STM Store Multiple

LDM Load Multiple SWPB Swap Byte

SWP Swap Word MRC Move From Coprocessor

MCR Move To Coprocessor STC Store From Coprocessor

LDC Load To Coprocessor

11.2.6 Thumb Instruction Set Overview

The Thumb instruction set is a re-encoded subset of the ARM instruction set.

The Thumb instruction set is divided into:

• Branch instructions

• Data processing instructions

• Load and Store instructions

• Load and Store Multiple instructions

• Exception-generating instruction

In Thumb mode, eight general-purpose registers, R0 to R7, are available that are the same physical registers as R0 to R7 when executing ARM instructions. Some Thumb instructions also access to the Program Counter (ARM Register 15), the Link Register (ARM Register 14) and the

6209F–ATARM–17-Feb-09

Stack Pointer (ARM Register 13). Further instructions allow limited access to the ARM registers 8 to 15.

Table 11-3 gives the Thumb instruction mnemonic list.

Table 11-3. Thumb Instruction Mnemonic List

Mnemonic Operation Mnemonic Operation

MOV Move MVN Move Not

ADD Add ADC Add with Carry

SUB Subtract SBC Subtract with Carry

CMP Compare CMN Compare Negated

TST Test NEG Negate

AND Logical AND BIC Bit Clear

EOR Logical Exclusive OR ORR Logical (inclusive) OR

LSL Logical Shift Left LSR Logical Shift Right

ASR Arithmetic Shift Right ROR Rotate Right

MUL Multiply

B Branch BL Branch and Link

BX Branch and Exchange SWI Software Interrupt

LDR Load Word STR Store Word

LDRH Load Half Word STRH Store Half Word

LDRB Load Byte STRB Store Byte

LDRSH Load Signed Halfword LDRSB Load Signed Byte

LDMIA Load Multiple STMIA Store Multiple

PUSH Push Register to stack POP Pop Register from stack

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

12. Debug and Test Features

ICE

PDC

DBGU

PIO

DRXD

DTXD

TST

TMS

TCK

TDI

JTAGSEL

TDO

Boundary

TA P

ICE/JTAG

TA P

ARM7TDMI

Reset

and Test

POR

12.1 Description

The AT91SAM7XC Series features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel.

A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment.

12.2 Block Diagram

Figure 12-1. Debug and Test Block Diagram

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

12.3 Application Examples

ICE/JTAG Interface

Host Debugger

ICE/JTAG Connector

Terminal

RS232

Connector

AT91SAMXCxx

AT91SAM7XCxx-based Application Board

12.3.1 Debug Environment

Figure 12-2 shows a complete debug environment example. The ICE/JTAG interface is used for

standard debugging functions, such as downloading code and single-stepping through the program.

Figure 12-2. Application Debug Environment Example

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

12.3.2 Test Environment

Tester

JTAG

Interface

ICE/JTAG

Connector

AT91SAM7XCxx-based Application Board In Test

Test Adaptor

Chip 2Chip n

Chip 1

AT91SAM7XCxx

Figure 12-3 shows a test environment example. Test vectors are sent and interpreted by the tes-

ter. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain.

Figure 12-3. Application Test Environment Example

AT91SAM7XC512/256/128 Preliminary

12.4 Debug and Test Pin Description

Table 12-1. Debug and Test Pin List

Pin Name Function Type Active Level

NRST Microcontroller Reset Input/Output Low

TST Test Mode Select Input High

TCK Test Clock Input

TDI Test Data In Input

TDO Test Data Out Output

TMS Test Mode Select Input

JTAGSEL JTAG Selection Input

DRXD Debug Receive Data Input

DTXD Debug Transmit Data Output

Reset/Test

ICE and JTAG

Debug Unit

6209F–ATARM–17-Feb-09

12.5 Functional Description

12.5.1 Test Pin

One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test.

12.5.2 EmbeddedICE

12.5.3 Debug Unit

™

(Embedded In-circuit Emulator)

The ARM7TDMI EmbeddedICE is supported via the ICE/JTAG port. The internal state of the ARM7TDMI is examined through an ICE/JTAG port.

The ARM7TDMI processor contains hardware extensions for advanced debugging features:

• In halt mode, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM7TDMI registers. This data can be serially shifted out without affecting the rest of the system.

• In monitor mode, the JTAG interface is used to transfer data between the debugger and a simple monitor program running on the ARM7TDMI processor.

There are three scan chains inside the ARM7TDMI processor that support testing, debugging, and programming of the EmbeddedICE. The scan chains are controlled by the ICE/JTAG port.

EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed.

For further details on the EmbeddedICE, see the ARM7TDMI (Rev4) Technical Reference Manual (DDI0210B).

The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum.

The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel. The Debug Unit allows blockage of access to the system through the ICE interface.

A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration.

The AT91SAM7XC512 Debug Unit Chip ID value is 0x271C 0A40 on 32-bit width.

The AT91SAM7XC256 Debug Unit Chip ID value is 0x271B 0940 on 32-bit width.

The AT91SAM7XC128 Debug Unit Chip ID value is 0x271A 0740 on 32-bit width.

For further details on the Debug Unit, see the Debug Unit section.

12.5.4 IEEE 1149.1 JTAG Boundary Scan

IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology.

IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant.

It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed.

A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.

12.5.4.1 JTAG Boundary-scan Register

The Boundary-scan Register (BSR) contains 187 bits that correspond to active pins and associated control signals.

Each AT91SAM7XC input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad.

Table 12-2. AT91SAM7XC JTAG Boundary Scan Register

Bit

Number Pin Name Pin Type

187

186 OUTPUT

185 CONTROL

184

183 OUTPUT

182 CONTROL

181

180 OUTPUT

179 CONTROL

178

177 OUTPUT

176 CONTROL

175

174 OUTPUT

173 CONTROL

172

171 OUTPUT

170 CONTROL

169

168 OUTPUT

167 CONTROL

166

165 INPUT

164 OUTPUT

163

162 INPUT

161 OUTPUT

160 ERASE IN INPUT

AT91SAM7XC512/256/128 Preliminary

Associated BSR

Cells

INPUT

PA30/IRQ0/PCK2 IN/OUT

INPUT

PA0/RXD0 IN/OUT

INPUT

PA1/TXD0 IN/OUT

INPUT

PA3/RTS0/SPI1_NPCS2 IN/OUT

INPUT

PA2/SCK0/SPI1_NPCS1 IN/OUT

INPUT

PA4/CTS0/SPI1_NPCS3 IN/OUT

INPUT

PA5/RXD1 IN/OUT

CONTROL

PA6/TXD1 IN/OUT

CONTROL

PA7/SCK1/SPI0_NPCS1 IN/OUT

6209F–ATARM–17-Feb-09

Table 12-2. AT91SAM7XC JTAG Boundary Scan Register (Continued)

Bit

Number Pin Name Pin Type

159

158 OUTPUT

157 CONTROL

156

155 OUTPUT

154 CONTROL

153

152 OUTPUT

151 CONTROL

150

149 OUTPUT

148 CONTROL

147

146 OUTPUT

145 CONTROL

144

143 OUTPUT

142 CONTROL

141

140 OUTPUT

139 CONTROL

138

137 OUTPUT

136 CONTROL

135

134 OUTPUT

133 CONTROL

132

131 OUTPUT

130 CONTROL

129

128 OUTPUT

127 CONTROL

126

125 OUTPUT

124 CONTROL

123

122 OUTPUT

121 CONTROL

120

119 OUTPUT

118 CONTROL

PB27/TIOA2/PWM0/AD0 IN/OUT

PB28/TIOB2/PWM1/AD1 IN/OUT

PB29/PCK1/PWM2/AD2 IN/OUT

PB30/PCK2/PWM3/AD3 IN/OUT

PA8/RTS1/SPI0_NPCS2 IN/OUT

PA9/CTS1/SPI0_NPCS3 IN/OUT

PA10/TWD IN/OUT

PA11/TWCK IN/OUT

PA12/SPI0_NPCS0 IN/OUT

PA13/SPI0_NPCS1/PCK1 IN/OUT

PA14/SPI0_NPCS2/IRQ1 IN/OUT

PA15/SPI0_NPCS3/TCLK2 IN/OUT

PA16/SPI0_MISO IN/OUT

PA17/SPI0_MOSI IN/OUT

Associated BSR

Cells

INPUT

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

Table 12-2. AT91SAM7XC JTAG Boundary Scan Register (Continued)

Bit

Number Pin Name Pin Type

117

116 OUTPUT

115 CONTROL

114

113 OUTPUT

112 CONTROL

111

110 OUTPUT

109 CONTROL

108

107 OUTPUT

106 CONTROL

105

104 OUTPUT

103 CONTROL

102

101 OUTPUT

100 CONTROL

98 OUTPUT

97 CONTROL

95 OUTPUT

94 CONTROL

92 OUTPUT

91 CONTROL

89 OUTPUT

88 CONTROL

86 OUTPUT

85 CONTROL

83 OUTPUT

82 CONTROL

80 OUTPUT

79 CONTROL

77 OUTPUT

76 CONTROL

PA18/SPI0_SPCK IN/OUT

PB9/EMDIO IN/OUT

PB8/EMDC IN/OUT

PB14/ERX3/SPI0_NPCS2 IN/OUT

PB13/ERX2/SPI0_NPCS1 IN/OUT

PB6/ERX1 IN/OUT

PB5/ERX0 IN/OUT

PB15/ERXDV/ECRSDV IN/OUT

PB17/ERXCK/SPI0_NPCS3 IN/OUT

PB7/ERXER IN/OUT

PB12/ETXER/TCLK0 IN/OUT

PB0/ETXCK/EREFCK/PCK0

PB1/ETXEN PB1/ETXEN

PB2/ETX0 PB2/ETX0

PB0/ETXCK/ERE

FCK/PCK0

Associated BSR

Cells

INPUT

6209F–ATARM–17-Feb-09

Table 12-2. AT91SAM7XC JTAG Boundary Scan Register (Continued)

Bit

Number Pin Name Pin Type

74 OUTPUT

73 CONTROL

71 OUTPUT

70 CONTROL

68 OUTPUT

67 CONTROL

65 OUTPUT

64 CONTROL

62 OUTPUT

61 CONTROL

59 OUTPUT

58 CONTROL

56 OUTPUT

55 CONTROL

53 OUTPUT

52 CONTROL

50 OUTPUT

49 CONTROL

47 OUTPUT

46 CONTROL

44 OUTPUT

43 CONTROL

41 OUTPUT

40 CONTROL

38 OUTPUT

37 CONTROL

35 OUTPUT

34 CONTROL

PB10/ETX2/SPI1_NPCS1 IN/OUT

PB11/ETX3/SPI1_NPCS2 IN/OUT

PB16/ECOL/SPI1_NPCS3 IN/OUT

PB3/ETX1 PB3/ETX1

PA19/CANRX IN/OUT

PA20/CANTX IN/OUT

PA21/TF/SPI1_NPCS0 IN/OUT

PA22/TK/SPI1_SPCK IN/OUT

PB4/ECRS IN/OUT

PA23/TD/SPI1_MOSI IN/OUT

PA24/RD/SPI1_MISO IN/OUT

PA25/RK/SPI1_NPCS1 IN/OUT

PA26/RF/SPI1_NPCS2 IN/OUT

PB18/EF100/ADTRG IN/OUT

Associated BSR

Cells

INPUT

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

Table 12-2. AT91SAM7XC JTAG Boundary Scan Register (Continued)

Bit

Number Pin Name Pin Type

32 OUTPUT

31 CONTROL

29 OUTPUT

28 CONTROL

26 OUTPUT

25 CONTROL

23 OUTPUT

22 CONTROL

20 OUTPUT

19 CONTROL

17 OUTPUT

16 CONTROL

14 OUTPUT

13 CONTROL

11 OUTPUT

10 CONTROL

8 OUTPUT

7 CONTROL

5 OUTPUT

4 CONTROL

2 OUTPUT

1 CONTROL

PB19/PWM0/TCLK1 IN/OUT

PB20/PWM1/PCK0 IN/OUT

PB21/PWM2/PCK2 IN/OUT

PB22/PWM3/PCK2 IN/OUT

PB23/TIOA0/DCD1 IN/OUT

PB24/TIOB0/DSR1 IN/OUT

PB25/TIOA1/DTR1 IN/OUT

PB26/TIOB1/RI1 IN/OUT

PA27DRXD/PCK3 IN/OUT

PA28/DTXD IN/OUT

PA29/FIQ/SPI1_NPCS3 IN/OUT

Associated BSR

Cells

INPUT

6209F–ATARM–17-Feb-09

12.5.5 ID Code Register

Access: Read-only

31 30 29 28 27 26 25 24

VERSION PART NUMBER

23 22 21 20 19 18 17 16

PART NUMBER

15 14 13 12 11 10 9 8

PART NUMBER MANUFACTURER IDENTITY

76543210

MANUFACTURER IDENTITY 1

• VERSION[31:28]: Product Version Number

Set to 0x0.

• PART NUMBER[27:12]: Product Part Number

AT91SAM7XC512: 0x5B19

AT91SAM7XC256: 0x5B10

AT91SAM7XC128: 0x5B0F

• MANUFACTURER IDENTITY[11:1]

Set to 0x01F.

Bit[0] Required by IEEE Std. 1149.1.

Set to 0x1.

AT91SAM7XC512: JTAG ID Code value is 05B1_903F

AT91SAM7XC256: JTAG ID Code value is 05B1_003F

AT91SAM7XC128: JTAG ID Code value is 05B0_F03F

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

13. Reset Controller (RSTC)

NRST

Startup

Counter

proc_nreset

wd_fault

periph_nreset

SLCK

Reset

State

Manager

Reset Controller

brown_out

bod_rst_en

rstc_irq

NRST

Manager

exter_nreset

nrst_out

Main Supply

POR

WDRPROC

user_reset

Brownout

Manager

bod_reset

The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last.

The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets.

A brownout detection is also available to prevent the processor from falling into an unpredictable state.

13.1 Block Diagram

Figure 13-1. Reset Controller Block Diagram

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

13.2 Functional Description

External Reset Timer

URSTS

URSTEN

ERSTL

exter_nreset

URSTIEN

RSTC_MR

RSTC_SR

NRSTL

nrst_out

NRST

rstc_irq

Other

interrupt

sources

user_reset

13.2.1 Reset Controller Overview

The Reset Controller is made up of an NRST Manager, a Brownout Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals:

• proc_nreset: Processor reset line. It also resets the Watchdog Timer.

• periph_nreset: Affects the whole set of embedded peripherals.

• nrst_out: Drives the NRST pin.

These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required.

The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets.

The startup counter waits for the complete crystal oscillator startup. The wait delay is given by the crystal oscillator startup time maximum value that can be found in the section Crystal Oscillator Characteristics in the Electrical Characteristics section of the product documentation.

13.2.2 NRST Manager

The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 13-2 shows the block diagram of the NRST Manager.

Figure 13-2. NRST Manager

13.2.2.1 NRST Signal or Interrupt

The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager.

However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger.

The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read.

The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1.

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

13.2.2.2 NRST External Reset Control

rstc_irq

brown_out

bod_reset

bod_rst_en

BODIEN

RSTC_MR

BODSTS

RSTC_SR

Other

interrupt

sources

The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts

(ERSTL+1)

Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs

and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.

This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset.

13.2.3 Brownout Manager

Brownout detection prevents the processor from falling into an unpredictable state if the power supply drops below a certain level. When VDDCORE drops below the brownout threshold, the brownout manager requests a brownout reset by asserting the bod_reset signal.

The programmer can disable the brownout reset by setting low the bod_rst_en input signal, i.e.; by locking the corresponding general-purpose NVM bit in the Flash. When the brownout reset is disabled, no reset is performed. Instead, the brownout detection is reported in the bit BODSTS of RSTC_SR. BODSTS is set and clears only when RSTC_SR is read.

AT91SAM7XC512/256/128 Preliminary

The bit BODSTS can trigger an interrupt if the bit BODIEN is set in the RSTC_MR.

At factory, the brownout reset is disabled.

Figure 13-3. Brownout Manager

6209F–ATARM–17-Feb-09

13.2.4 Reset States

SLCK

periph_nreset

proc_nreset

Main Supply

POR output

NRST

(nrst_out)

EXTERNAL RESET LENGTH

= 2 cycles

Startup Time

MCK

Processor Startup

= 3 cycles

Any

Freq.

The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released.

13.2.4.1 Power-up Reset

When VDDCORE is powered on, the Main Supply POR cell output is filtered with a start-up counter that operates at Slow Clock. The purpose of this counter is to ensure that the Slow Clock oscillator is stable before starting up the device.

The startup time, as shown in Figure 13-4, is hardcoded to comply with the Slow Clock Oscillator startup time. After the startup time, the reset signals are released and the field RSTTYP in RSTC_SR reports a Power-up Reset.

When VDDCORE is detected low by the Main Supply POR Cell, all reset signals are asserted immediately.

Figure 13-4. Power-up Reset

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

13.2.4.2 User Reset

SLCK

periph_nreset

proc_nreset

NRST

(nrst_out)

>= EXTERNAL RESET LENGTH

MCK

Processor Startup

= 3 cycles

Any

Freq.

Resynch.

2 cycles

RSTTYP

Any XXX

Resynch.

2 cycles

0x4 = User Reset

The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system.

The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted.

The User Reset is left when NRST rises, after a two-cycle resynchronization time and a threecycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high.

When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset.

The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises.

Figure 13-5. User Reset State

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

13.2.4.3 Brownout Reset

SLCK

periph_nreset

proc_nreset

brown_out

or bod_reset

NRST

(nrst_out)

EXTERNAL RESET LENGTH

8 cycles (ERSTL=2)

MCK

Processor Startup

= 3 cycles

Any

Freq.

RSTTYP

Any

XXX

0x5 = Brownout Reset

Resynch.

2 cycles

When the brown_out/bod_reset signal is asserted, the Reset State Manager immediately enters the Brownout Reset. In this state, the processor, the peripheral and the external reset lines are asserted.

The Brownout Reset is left 3 Slow Clock cycles after the rising edge of brown_out/bod_reset after a two-cycle resynchronization. An external reset is also triggered.

When the processor reset is released, the field RSTTYP in RSTC_SR is loaded with the value 0x5, thus indicating that the last reset is a Brownout Reset.

Figure 13-6. Brownout Reset State

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

13.2.4.4 Software Reset

The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1:

The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles.

The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK.

AT91SAM7XC512/256/128 Preliminary

• PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.

• PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. Except for Debug purposes, PERRST must always be used in conjuction with PROCRST (PERRST and PROCRST set both at 1 simultaneously).

• EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR).

If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset.

If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP.

As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect.

6209F–ATARM–17-Feb-09

Figure 13-7. Software Reset

SLCK

periph_nreset

if PERRST=1

proc_nreset

if PROCRST=1

Write RSTC_CR

NRST

(nrst_out)

if EXTRST=1

EXTERNAL RESET LENGTH

8 cycles (ERSTL=2)

MCK

Processor Startup

= 3 cycles

Any

Freq.

RSTTYP

Any

XXX

0x3 = Software Reset

Resynch.

1 cycle

SRCMP in RSTC_SR

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

13.2.4.5 Watchdog Reset

Only if

WDRPROC = 0

SLCK

periph_nreset

proc_nreset

wd_fault

NRST

(nrst_out)

EXTERNAL RESET LENGTH

8 cycles (ERSTL=2)

MCK

Processor Startup

= 3 cycles

Any

Freq.

RSTTYP

Any

XXX

0x2 = Watchdog Reset

The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles.

When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR:

• If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST

• If WDRPROC = 1, only the processor reset is asserted.

The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum.

When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller.

Figure 13-8. Watchdog Reset

AT91SAM7XC512/256/128 Preliminary

line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state.

6209F–ATARM–17-Feb-09

13.2.5 Reset State Priorities

The Reset State Manager manages the following priorities between the different reset sources, given in descending order:

• Power-up Reset

•Brownout Reset

• Watchdog Reset

• Software Reset

• User Reset

Particular cases are listed below:

• When in User Reset:

• When in Software Reset:

• When in Watchdog Reset:

– A watchdog event is impossible because the Watchdog Timer is being reset by the

proc_nreset signal.

– A software reset is impossible, since the processor reset is being activated.

– A watchdog event has priority over the current state.

– The NRST has no effect.

– The processor reset is active and so a Software Reset cannot be programmed.

– A User Reset cannot be entered.

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

MCK

NRST

NRSTL

2 cycle

resynchronization

2 cycle

resynchronization

URSTS

read

RSTC_SR

Peripheral Access

rstc_irq

if (URSTEN = 0) and

(URSTIEN = 1)

13.2.6 Reset Controller Status Register

The Reset Controller status register (RSTC_SR) provides several status fields:

• RSTTYP field: This field gives the type of the last reset, as explained in previous sections.

• SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.

• NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge.

• URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is also detected on the Master Clock (MCK) rising edge (see Figure

13-9). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the

URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt.

• BODSTS bit: This bit indicates a brownout detection when the brownout reset is disabled (bod_rst_en = 0). It triggers an interrupt if the bit BODIEN in the RSTC_MR register enables the interrupt. Reading the RSTC_SR register resets the BODSTS bit and clears the interrupt.

Figure 13-9. Reset Controller Status and Interrupt

6209F–ATARM–17-Feb-09

13.3 Reset Controller (RSTC) User Interface

Table 13-1. Register Mapping

Offset Register Name Access Reset

0x00 Control Register RSTC_CR Write-only -

0x04 Status Register RSTC_SR Read-only 0x0000_0000

0x08 Mode Register RSTC_MR Read-write 0x0000_0000

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

13.3.1 Reset Controller Control Register Register Name: RSTC_CR

Access Type: Write-only

31 30 29 28 27 26 25 24

KEY

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

–––––– –

76543210 ––––EXTRSTPERRST–PROCRST

• PROCRST: Processor Reset

0 = No effect.

1 = If KEY is correct, resets the processor.

• PERRST: Peripheral Reset

0 = No effect.

1 = If KEY is correct, resets the peripherals.

• EXTRST: External Reset

0 = No effect.

1 = If KEY is correct, asserts the NRST pin.

•KEY: Password

Should be written at value 0xA5. Writing any other value in this field aborts the write operation.

6209F–ATARM–17-Feb-09

13.3.2 Reset Controller Status Register Register Name: RSTC_SR

Access Type: Read-only

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––SRCMPNRSTL

15 14 13 12 11 10 9 8

––––– RSTTYP

76543210 ––––––BODSTSURSTS

• URSTS: User Reset Status

0 = No high-to-low edge on NRST happened since the last read of RSTC_SR.

1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.

• BODSTS: Brownout Detection Status

0 = No brownout high-to-low transition happened since the last read of RSTC_SR.

1 = A brownout high-to-low transition has been detected since the last read of RSTC_SR.

• RSTTYP: Reset Type

Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.

RSTTYP Reset Type Comments

0 0 0 Power-up Reset VDDCORE rising

0 1 0 Watchdog Reset Watchdog fault occurred

0 1 1 Software Reset Processor reset required by the software

1 0 0 User Reset NRST pin detected low

1 0 1 Brownout Reset Brownout reset occurred

• NRSTL: NRST Pin Level

Registers the NRST Pin Level at Master Clock (MCK).

• SRCMP: Software Reset Command in Progress

0 = No software command is being performed by the reset controller. The reset controller is ready for a software command.

1 = A software reset command is being performed by the reset controller. The reset controller is busy.

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

13.3.3 Reset Controller Mode Register Register Name: RSTC_MR

Access Type: Read-write

31 30 29 28 27 26 25 24

KEY

23 22 21 20 19 18 17 16

–––––––BODIEN

15 14 13 12 11 10 9 8

–––– ERSTL

76543210 – – URSTIEN – – – URSTEN

• URSTEN: User Reset Enable

0 = The detection of a low level on the pin NRST does not generate a User Reset.

1 = The detection of a low level on the pin NRST triggers a User Reset.

• URSTIEN: User Reset Interrupt Enable

0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq.

1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.

• BODIEN: Brownout Detection Interrupt Enable

0 = BODSTS bit in RSTC_SR at 1 has no effect on rstc_irq.

1 = BODSTS bit in RSTC_SR at 1 asserts rstc_irq.

• ERSTL: External Reset Length

This field defines the external reset length. The external reset is asserted during a time of 2

(ERSTL+1)

allows assertion duration to be programmed between 60 µs and 2 seconds.

•KEY: Password

Should be written at value 0xA5. Writing any other value in this field aborts the write operation.

Slow Clock cycles. This

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

14. Real-time Timer (RTT)

SLCK

RTPRES

RTTINC

ALMS

16-bit

Divider

32-bit

Counter

ALMV

CRTV

RTT_MR

RTT_VR

RTT_AR

RTT_SR

RTTINCIEN

RTT_MR

ALMIEN

rtt_int

RTT_MR

set

RTT_SR

read

RTT_SR

reset

RTT_MR

reload

rtt_alarm

RTTRST

RTT_MR

RTTRST

14.1 Overview

The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt or/and triggers an alarm on a programmed value.

14.2 Block Diagram

Figure 14-1. Real-time Timer

AT91SAM7XC512/256/128 Preliminary

14.3 Functional Description

6209F–ATARM–17-Feb-09

The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR).

Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 Hz). The 32-bit counter can count up to 2 sponding to more than 136 years, then roll over to 0.

The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear.

seconds, corre-

The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time

Prescaler

ALMVALMV-10 ALMV+1

RTPRES - 1

RTT

APB cycle

read RTT_SR

ALMS (RTT_SR)

APB Interface

MCK

RTTINC (RTT_SR)

ALMV+2 ALMV+3

...

APB cycle

Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value.

The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF, after a reset.

The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to 32.768 Hz.

Reading the RTT_SR status register resets the RTTINC and ALMS fields.

Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter.

Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK):

Figure 14-2. RTT Counting

1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register.

2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the RTT_SR (Status Register).

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

14.4 Real-time Timer (RTT) User Interface

Table 14-1. Register Mapping

Offset Register Name Access Reset

0x00 Mode Register RTT_MR Read-write 0x0000_8000

0x04 Alarm Register RTT_AR Read-write 0xFFFF_FFFF

0x08 Value Register RTT_VR Read-only 0x0000_0000

0x0C Status Register RTT_SR Read-only 0x0000_0000

6209F–ATARM–17-Feb-09

14.4.1 Real-time Timer Mode Register Register Name: RTT_MR

Access Type: Read-write

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

–––––RTTRSTRTTINCIENALMIEN

15 14 13 12 11 10 9 8

RTPRES

76543210

RTPRES

• RTPRES: Real-time Timer Prescaler Value

Defines the number of SLCK periods required to increment the real-time timer. RTPRES is defined as follows:

RTPRES = 0: The Prescaler Period is equal to 2

RTPRES ≠ 0: The Prescaler Period is equal to RTPRES.

• ALMIEN: Alarm Interrupt Enable

0 = The bit ALMS in RTT_SR has no effect on interrupt.

1 = The bit ALMS in RTT_SR asserts interrupt.

• RTTINCIEN: Real-time Timer Increment Interrupt Enable

0 = The bit RTTINC in RTT_SR has no effect on interrupt.

1 = The bit RTTINC in RTT_SR asserts interrupt.

• RTTRST: Real-time Timer Restart

1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter.

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

14.4.2 Real-time Timer Alarm Register Register Name: RTT_AR

Access Type: Read-write

31 30 29 28 27 26 25 24

ALMV

23 22 21 20 19 18 17 16

ALMV

15 14 13 12 11 10 9 8

ALMV

76543210

ALMV

• ALMV: Alarm Value

Defines the alarm value (ALMV+1) compared with the Real-time Timer.

14.4.3 Real-time Timer Value Register Register Name: RTT_VR

Access Type: Read-only

31 30 29 28 27 26 25 24

CRTV

23 22 21 20 19 18 17 16

CRTV

15 14 13 12 11 10 9 8

CRTV

76543210

CRTV

• CRTV: Current Real-time Value

Returns the current value of the Real-time Timer.

6209F–ATARM–17-Feb-09

14.4.4 Real-time Timer Status Register Register Name: RTT_SR

Access Type: Read-only

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210 ––––––RTTINCALMS

• ALMS: Real-time Alarm Status

0 = The Real-time Alarm has not occurred since the last read of RTT_SR.

1 = The Real-time Alarm occurred since the last read of RTT_SR.

• RTTINC: Real-time Timer Increment

0 = The Real-time Timer has not been incremented since the last read of the RTT_SR.

1 = The Real-time Timer has been incremented since the last read of the RTT_SR.

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

15. Parallel Input/Output Controller (PIO)

15.1 Overview

The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product.

Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface.

Each I/O line of the PIO Controller features:

• An input change interrupt enabling level change detection on any I/O line.

• A glitch filter providing rejection of pulses lower than one-half of clock cycle.

• Multi-drive capability similar to an open drain I/O line.

• Control of the the pull-up of the I/O line.

• Input visibility and output control.

The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation.

6209F–ATARM–17-Feb-09

15.2 Block Diagram

Embedded

Peripheral

Embedded

Peripheral

PIO Interrupt

PIO Controller

Up to 32 pins

PMC

Up to 32

peripheral IOs

Up to 32

peripheral IOs

PIO Clock

APB

AIC

Data, Enable

PIN 31

PIN 1

PIN 0

Data, Enable

On-Chip Peripherals

PIO Controller

On-Chip Peripheral Drivers

Control & Command

Driver

Keyboard Driver

Keyboard Driver General Purpose I/Os External Devices

Figure 15-1. Block Diagram

Figure 15-2. Application Block Diagram

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

15.3 Product Dependencies

15.3.1 Pin Multiplexing

Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product.

15.3.2 External Interrupt Lines

The interrupt signals FIQ and IRQ0 to IRQn are most generally multiplexed through the PIO Controllers. However, it is not necessary to assign the I/O line to the interrupt function as the PIO Controller has no effect on inputs and the interrupt lines (FIQ or IRQs) are used only as inputs.

15.3.3 Power Management

The Power Management Controller controls the PIO Controller clock in order to save power. Writing any of the registers of the user interface does not require the PIO Controller clock to be enabled. This means that the configuration of the I/O lines does not require the PIO Controller clock to be enabled.

AT91SAM7XC512/256/128 Preliminary

However, when the clock is disabled, not all of the features of the PIO Controller are available. Note that the Input Change Interrupt and the read of the pin level require the clock to be validated.

After a hardware reset, the PIO clock is disabled by default.

The user must configure the Power Management Controller before any access to the input line information.

15.3.4 Interrupt Generation

For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller interrupt lines are connected among the interrupt sources 2 to 31. Refer to the PIO Controller peripheral identifier in the product description to identify the interrupt sources dedicated to the PIO Controllers.

The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled.

6209F–ATARM–17-Feb-09

15.4 Functional Description

Glitch

Filter

Peripheral B

Input

Peripheral A

Input

PIO_IFDR[0]

PIO_IFSR[0]

PIO_IFER[0]

Edge

Detector

PIO_PDSR[0] PIO_ISR[0]

PIO_IDR[0]

PIO_IMR[0]

PIO_IER[0]

PIO Interrupt

(Up to 32 possible inputs)

PIO_ISR[31]

PIO_IDR[31]

PIO_IMR[31]

PIO_IER[31]

Pad

PIO_PUDR[0]

PIO_PUSR[0]

PIO_PUER[0]

PIO_MDDR[0]

PIO_MDSR[0]

PIO_MDER[0]

PIO_CODR[0]

PIO_ODSR[0]

PIO_SODR[0]

PIO_PDR[0]

PIO_PSR[0]

PIO_PER[0]

PIO_BSR[0]

PIO_ABSR[0]

PIO_ASR[0]

Peripheral B

Output Enable

Peripheral A

Output Enable

Peripheral B

Output

Peripheral A

Output

PIO_ODR[0]

PIO_OSR[0]

PIO_OER[0]

Figure 15-3. I/O Line Control Logic

The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 15-3. In this description each signal shown represents but one of up to 32 possible indexes.

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

15.4.1 Pull-up Resistor Control

Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pullup Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled.

Control of the pull-up resistor is possible regardless of the configuration of the I/O line.

After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0.

15.4.2 I/O Line or Peripheral Function Selection

When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The register PIO_PSR (PIO Status Register) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the PIO_ABSR (AB Select Status Register). A value of 1 indicates the pin is controlled by the PIO controller.

If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit.

After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR resets at 1. However, in some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PIO_PSR is defined at the product level, depending on the multiplexing of the device.

15.4.3 Peripheral A or B Selection

The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The selection is performed by writing PIO_ASR (A Select Register) and PIO_BSR (Select B Register). PIO_ABSR (AB Select Status Register) indicates which peripheral line is currently selected. For each pin, the corresponding bit at level 0 means peripheral A is selected whereas the corresponding bit at level 1 indicates that peripheral B is selected.

Note that multiplexing of peripheral lines A and B only affects the output line. The peripheral input lines are always connected to the pin input.

After reset, PIO_ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode.

Writing in PIO_ASR and PIO_BSR manages PIO_ABSR regardless of the configuration of the pin. However, assignment of a pin to a peripheral function requires a write in the corresponding peripheral selection register (PIO_ASR or PIO_BSR) in addition to a write in PIO_PDR.

15.4.4 Output Control

6209F–ATARM–17-Feb-09

When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the I/O line is controlled by the peripheral. Peripheral A or B, depending on the value in PIO_ABSR, determines whether the pin is driven or not.

When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register).

The results of these write operations are detected in PIO_OSR (Output Status Register). When a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at 1, the corresponding I/O line is driven by the PIO controller.

The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data Register) and PIO_CODR (Clear Output Data Register). These write operations respectively set and clear PIO_ODSR (Output Data Status Register), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller.

Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven on the I/O line.

15.4.5 Synchronous Data Output

Controlling all parallel busses using several PIOs requires two successive write operations in the PIO_SODR and PIO_CODR registers. This may lead to unexpected transient values. The PIO controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Output Data Status Register). Only bits unmasked by PIO_OWSR (Output Write Status Register) are written. The masked bits in PIO_OWSR are set by writing to PIO_OWER (Output Write Enable Register) and cleared by writing to PIO_OWDR (Output Write Disable Register).

After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0.

15.4.6 Multi Drive Control (Open Drain)

Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line.

The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O line is controlled by the PIO controller or assigned to a peripheral function. PIO_MDSR (Multi-driver Status Register) indicates the pins that are configured to support external drivers.

After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0.

15.4.7 Output Line Timings

Figure 15-4 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by

directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. Figure 15-4 also shows when the feedback in PIO_PDSR is available.

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

Figure 15-4. Output Line Timings

2 cycles

APB Access

2 cycles

APB Access

MCK

Write PIO_SODR

Write PIO_ODSR at 1

PIO_ODSR

PIO_PDSR

Write PIO_CODR

Write PIO_ODSR at 0

15.4.8 Inputs

The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral.

AT91SAM7XC512/256/128 Preliminary

Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.

15.4.9 Input Glitch Filtering

Optional input glitch filters are independently programmable on each I/O line. When the glitch filter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automatically rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted. For pulse durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 Master Clock cycle. The filter introduces one Master Clock cycle latency if the pin level change occurs before a rising edge. However, this latency does not appear if the pin level change occurs before a falling edge. This is illustrated in Figure 15-5.

The glitch filters are controlled by the register set; PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines.

When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch filters require that the PIO Controller clock is enabled.

6209F–ATARM–17-Feb-09

Figure 15-5. Input Glitch Filter Timing

MCK

Pin Level

PIO_PDSR

if PIO_IFSR = 0

PIO_PDSR

if PIO_IFSR = 1

1 cycle 1 cycle 1 cycle

up to 1.5 cycles

2 cycles

up to 2.5 cycles up to 2 cycles

1 cycle

MCK

Pin Level

Read PIO_ISR

APB Access

PIO_ISR

APB Access

15.4.10 Input Change Interrupt

The PIO Controller can be programmed to generate an interrupt when it detects an input change on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask Register). As Input change detection is possible only by comparing two successive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or assigned to a peripheral function.

When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to generate a single interrupt signal to the Advanced Interrupt Controller.

When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled.

Figure 15-6. Input Change Interrupt Timings

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

15.5 I/O Lines Programming Example

The programing example as shown in Table 15-1 below is used to define the following configuration.

• 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor

• Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor

• Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts

• Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter

• I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor

• I/O lines 20 to 23 assigned to peripheral B functions, no pull-up resistor

• I/O line 24 to 27 assigned to peripheral A with Input Change Interrupt and pull-up resistor

Table 15-1. Programming Example

AT91SAM7XC512/256/128 Preliminary

PIO_PER 0x0000 FFFF

PIO_PDR 0x0FFF 0000

PIO_OER 0x0000 00FF

PIO_ODR 0x0FFF FF00

PIO_IFER 0x0000 0F00

PIO_IFDR 0x0FFF F0FF

PIO_SODR 0x0000 0000

PIO_CODR 0x0FFF FFFF

PIO_IER 0x0F00 0F00

PIO_IDR 0x00FF F0FF

PIO_MDER 0x0000 000F

PIO_MDDR 0x0FFF FFF0

PIO_PUDR 0x00F0 00F0

PIO_PUER 0x0F0F FF0F

PIO_ASR 0x0F0F 0000

PIO_BSR 0x00F0 0000

PIO_OWER 0x0000 000F

PIO_OWDR 0x0FFF FFF0

6209F–ATARM–17-Feb-09

15.6 Parallel Input/Output Controller (PIO) User Interface

Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically.

Table 15-2. Register Mapping

Offset Register Name Access Reset

0x0000 PIO Enable Register PIO_PER Write-only –

0x0004 PIO Disable Register PIO_PDR Write-only –

(1)

0x0008 PIO Status Register PIO_PSR Read-only

0x000C Reserved

0x0010 Output Enable Register PIO_OER Write-only –

0x0014 Output Disable Register PIO_ODR Write-only –

0x0018 Output Status Register PIO_OSR Read-only 0x0000 0000

0x001C Reserved

0x0020 Glitch Input Filter Enable Register PIO_IFER Write-only –

0x0024 Glitch Input Filter Disable Register PIO_IFDR Write-only –

0x0028 Glitch Input Filter Status Register PIO_IFSR Read-only 0x0000 0000

0x002C Reserved

0x0030 Set Output Data Register PIO_SODR Write-only –

0x0034 Clear Output Data Register PIO_CODR Write-only

Read-only

0x0038 Output Data Status Register PIO_ODSR

0x003C Pin Data Status Register PIO_PDSR Read-only

0x0040 Interrupt Enable Register PIO_IER Write-only –

0x0044 Interrupt Disable Register PIO_IDR Write-only –

0x0048 Interrupt Mask Register PIO_IMR Read-only 0x00000000

0x004C Interrupt Status Register

0x0050 Multi-driver Enable Register PIO_MDER Write-only –

0x0054 Multi-driver Disable Register PIO_MDDR Write-only –

0x0058 Multi-driver Status Register PIO_MDSR Read-only 0x00000000

0x005C Reserved

0x0060 Pull-up Disable Register PIO_PUDR Write-only –

0x0064 Pull-up Enable Register PIO_PUER Write-only –

0x0068 Pad Pull-up Status Register PIO_PUSR Read-only 0x00000000

0x006C Reserved

(4)

PIO_ISR Read-only 0x00000000

(2)

Read-write

–

(3)

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

Table 15-2. Register Mapping (Continued)

Offset Register Name Access Reset

0x0070 Peripheral A Select Register

0x0074 Peripheral B Select Register

0x0078 AB Status Register

0x007C to 0x009C

0x00A0 Output Write Enable PIO_OWER Write-only –

0x00A4 Output Write Disable PIO_OWDR Write-only –

0x00A8 Output Write Status Register PIO_OWSR Read-only 0x00000000

0x00AC Reserved

Notes: 1. Reset value of PIO_PSR depends on the product implementation.

2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines.

3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.

4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred.

5. Only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the second register.

Reserved

(5)

PIO_ASR Write-only –

PIO_BSR Write-only –

PIO_ABSR Read-only 0x00000000

6209F–ATARM–17-Feb-09

15.6.1 PIO Controller PIO Enable Register Name: PIO_PER

Access Type: Write-only

31 30 29 28 27 26 25 24

P31 P30 P29 P28 P27 P26 P25 P24

23 22 21 20 19 18 17 16

P23 P22 P21 P20 P19 P18 P17 P16

15 14 13 12 11 10 9 8

P15 P14 P13 P12 P11 P10 P9 P8

76543210

P7 P6 P5 P4 P3 P2 P1 P0

• P0-P31: PIO Enable

0 = No effect.

1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin).

15.6.2 PIO Controller PIO Disable Register Name: PIO_PDR

Access Type: Write-only

31 30 29 28 27 26 25 24

P31 P30 P29 P28 P27 P26 P25 P24

23 22 21 20 19 18 17 16

P23 P22 P21 P20 P19 P18 P17 P16

15 14 13 12 11 10 9 8

P15 P14 P13 P12 P11 P10 P9 P8

76543210

P7 P6 P5 P4 P3 P2 P1 P0

• P0-P31: PIO Disable

0 = No effect.

1 = Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin).

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

15.6.3 PIO Controller PIO Status Register Name: PIO_PSR

Access Type: Read-only

31 30 29 28 27 26 25 24

P31 P30 P29 P28 P27 P26 P25 P24

23 22 21 20 19 18 17 16

P23 P22 P21 P20 P19 P18 P17 P16

15 14 13 12 11 10 9 8

P15 P14 P13 P12 P11 P10 P9 P8

76543210

P7 P6 P5 P4 P3 P2 P1 P0

• P0-P31: PIO Status

0 = PIO is inactive on the corresponding I/O line (peripheral is active).

1 = PIO is active on the corresponding I/O line (peripheral is inactive).

15.6.4 PIO Controller Output Enable Register Name: PIO_OER

Access Type: Write-only

31 30 29 28 27 26 25 24

P31 P30 P29 P28 P27 P26 P25 P24

23 22 21 20 19 18 17 16

P23 P22 P21 P20 P19 P18 P17 P16

15 14 13 12 11 10 9 8

P15 P14 P13 P12 P11 P10 P9 P8

76543210

P7 P6 P5 P4 P3 P2 P1 P0

• P0-P31: Output Enable

0 = No effect.

1 = Enables the output on the I/O line.

6209F–ATARM–17-Feb-09

15.6.5 PIO Controller Output Disable Register Name: PIO_ODR

Access Type: Write-only

31 30 29 28 27 26 25 24

P31 P30 P29 P28 P27 P26 P25 P24

23 22 21 20 19 18 17 16

P23 P22 P21 P20 P19 P18 P17 P16

15 14 13 12 11 10 9 8

P15 P14 P13 P12 P11 P10 P9 P8

76543210

P7 P6 P5 P4 P3 P2 P1 P0

• P0-P31: Output Disable

0 = No effect.

1 = Disables the output on the I/O line.

15.6.6 PIO Controller Output Status Register Name: PIO_OSR

Access Type: Read-only

31 30 29 28 27 26 25 24

P31 P30 P29 P28 P27 P26 P25 P24

23 22 21 20 19 18 17 16

P23 P22 P21 P20 P19 P18 P17 P16

15 14 13 12 11 10 9 8

P15 P14 P13 P12 P11 P10 P9 P8

76543210

P7 P6 P5 P4 P3 P2 P1 P0

• P0-P31: Output Status

0 = The I/O line is a pure input.

1 = The I/O line is enabled in output.

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

15.6.7 PIO Controller Input Filter Enable Register Name: PIO_IFER

Access Type: Write-only

31 30 29 28 27 26 25 24

P31 P30 P29 P28 P27 P26 P25 P24

23 22 21 20 19 18 17 16

P23 P22 P21 P20 P19 P18 P17 P16

15 14 13 12 11 10 9 8

P15 P14 P13 P12 P11 P10 P9 P8

76543210

P7 P6 P5 P4 P3 P2 P1 P0

• P0-P31: Input Filter Enable

0 = No effect.

1 = Enables the input glitch filter on the I/O line.

15.6.8 PIO Controller Input Filter Disable Register Name: PIO_IFDR

Access Type: Write-only

31 30 29 28 27 26 25 24

P31 P30 P29 P28 P27 P26 P25 P24

23 22 21 20 19 18 17 16

P23 P22 P21 P20 P19 P18 P17 P16

15 14 13 12 11 10 9 8

P15 P14 P13 P12 P11 P10 P9 P8

76543210

P7 P6 P5 P4 P3 P2 P1 P0

• P0-P31: Input Filter Disable

0 = No effect.

1 = Disables the input glitch filter on the I/O line.

6209F–ATARM–17-Feb-09

15.6.9 PIO Controller Input Filter Status Register Name: PIO_IFSR

Access Type: Read-only

31 30 29 28 27 26 25 24

P31 P30 P29 P28 P27 P26 P25 P24

23 22 21 20 19 18 17 16

P23 P22 P21 P20 P19 P18 P17 P16

15 14 13 12 11 10 9 8

P15 P14 P13 P12 P11 P10 P9 P8

76543210

P7 P6 P5 P4 P3 P2 P1 P0

• P0-P31: Input Filer Status

0 = The input glitch filter is disabled on the I/O line.

1 = The input glitch filter is enabled on the I/O line.

15.6.10 PIO Controller Set Output Data Register Name: PIO_SODR

Access Type: Write-only

31 30 29 28 27 26 25 24

P31 P30 P29 P28 P27 P26 P25 P24

23 22 21 20 19 18 17 16

P23 P22 P21 P20 P19 P18 P17 P16

15 14 13 12 11 10 9 8

P15 P14 P13 P12 P11 P10 P9 P8

76543210

P7 P6 P5 P4 P3 P2 P1 P0

• P0-P31: Set Output Data

0 = No effect.

1 = Sets the data to be driven on the I/O line.

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

15.6.11 PIO Controller Clear Output Data Register Name: PIO_CODR

Access Type: Write-only

31 30 29 28 27 26 25 24

P31 P30 P29 P28 P27 P26 P25 P24

23 22 21 20 19 18 17 16

P23 P22 P21 P20 P19 P18 P17 P16

15 14 13 12 11 10 9 8

P15 P14 P13 P12 P11 P10 P9 P8

76543210

P7 P6 P5 P4 P3 P2 P1 P0

• P0-P31: Set Output Data

0 = No effect.

1 = Clears the data to be driven on the I/O line.

15.6.12 PIO Controller Output Data Status Register Name: PIO_ODSR

Access Type: Read-only or Read/Write

31 30 29 28 27 26 25 24

P31 P30 P29 P28 P27 P26 P25 P24

23 22 21 20 19 18 17 16

P23 P22 P21 P20 P19 P18 P17 P16

15 14 13 12 11 10 9 8

P15 P14 P13 P12 P11 P10 P9 P8

76543210

P7 P6 P5 P4 P3 P2 P1 P0

• P0-P31: Output Data Status

0 = The data to be driven on the I/O line is 0.

1 = The data to be driven on the I/O line is 1.

6209F–ATARM–17-Feb-09

15.6.13 PIO Controller Pin Data Status Register Name: PIO_PDSR

Access Type: Read-only

31 30 29 28 27 26 25 24

P31 P30 P29 P28 P27 P26 P25 P24

23 22 21 20 19 18 17 16

P23 P22 P21 P20 P19 P18 P17 P16

15 14 13 12 11 10 9 8

P15 P14 P13 P12 P11 P10 P9 P8

76543210

P7 P6 P5 P4 P3 P2 P1 P0

• P0-P31: Output Data Status

0 = The I/O line is at level 0.

1 = The I/O line is at level 1.

15.6.14 PIO Controller Interrupt Enable Register Name: PIO_IER

Access Type: Write-only

31 30 29 28 27 26 25 24

P31 P30 P29 P28 P27 P26 P25 P24

23 22 21 20 19 18 17 16

P23 P22 P21 P20 P19 P18 P17 P16

15 14 13 12 11 10 9 8

P15 P14 P13 P12 P11 P10 P9 P8

76543210

P7 P6 P5 P4 P3 P2 P1 P0

• P0-P31: Input Change Interrupt Enable

0 = No effect.

1 = Enables the Input Change Interrupt on the I/O line.

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

AT91SAM7XC512/256/128 Preliminary

15.6.15 PIO Controller Interrupt Disable Register Name: PIO_IDR

Access Type: Write-only

31 30 29 28 27 26 25 24

P31 P30 P29 P28 P27 P26 P25 P24

23 22 21 20 19 18 17 16

P23 P22 P21 P20 P19 P18 P17 P16

15 14 13 12 11 10 9 8

P15 P14 P13 P12 P11 P10 P9 P8

76543210

P7 P6 P5 P4 P3 P2 P1 P0

• P0-P31: Input Change Interrupt Disable

0 = No effect.

1 = Disables the Input Change Interrupt on the I/O line.

15.6.16 PIO Controller Interrupt Mask Register Name: PIO_IMR

Access Type: Read-only

31 30 29 28 27 26 25 24

P31 P30 P29 P28 P27 P26 P25 P24

23 22 21 20 19 18 17 16

P23 P22 P21 P20 P19 P18 P17 P16

15 14 13 12 11 10 9 8

P15 P14 P13 P12 P11 P10 P9 P8

76543210

P7 P6 P5 P4 P3 P2 P1 P0

• P0-P31: Input Change Interrupt Mask

0 = Input Change Interrupt is disabled on the I/O line.

1 = Input Change Interrupt is enabled on the I/O line.

6209F–ATARM–17-Feb-09

15.6.17 PIO Controller Interrupt Status Register Name: PIO_ISR

Access Type: Read-only

31 30 29 28 27 26 25 24

P31 P30 P29 P28 P27 P26 P25 P24

23 22 21 20 19 18 17 16

P23 P22 P21 P20 P19 P18 P17 P16

15 14 13 12 11 10 9 8

P15 P14 P13 P12 P11 P10 P9 P8

76543210

P7 P6 P5 P4 P3 P2 P1 P0

• P0-P31: Input Change Interrupt Status

0 = No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.

1 = At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.

15.6.18 PIO Multi-driver Enable Register Name: PIO_MDER

Access Type: Write-only

31 30 29 28 27 26 25 24

P31 P30 P29 P28 P27 P26 P25 P24

23 22 21 20 19 18 17 16

P23 P22 P21 P20 P19 P18 P17 P16

15 14 13 12 11 10 9 8

P15 P14 P13 P12 P11 P10 P9 P8

76543210

P7 P6 P5 P4 P3 P2 P1 P0

• P0-P31: Multi Drive Enable.

0 = No effect.

1 = Enables Multi Drive on the I/O line.

100

AT91SAM7XC512/256/128 Preliminary

6209F–ATARM–17-Feb-09

ATMEL AT91SAM9XE512 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

1. Description

1.1 Configuration Summary of the AT91SAM7XC512/256/128

2. AT91SAM7XC512/256/128 Block Diagram

3. Signal Description

4. Package

4.1 100-lead LQFP Package Outline

4.2 100-lead LQFP Pinout

4.3 100-ball TFBGA Package Outline

4.4 100-ball TFBGA Pinout

5. Power Considerations

5.1 Power Supplies

5.2 Power Consumption

5.3 Voltage Regulator

5.4 Typical Powering Schematics

6. I/O Lines Considerations

6.1 JTAG Port Pins

6.2 Test Pin

6.3 Reset Pin

6.4 ERASE Pin

6.5 PIO Controller Lines

6.6 I/O Lines Current Drawing

7. Processor and Architecture

7.1 ARM7TDMI Processor

7.2 Debug and Test Features

7.3 Memory Controller

7.4 Peripheral DMA Controller

8. Memory

8.1 AT91SAM7XC512

8.2 AT91SAM7XC256

8.3 AT91SAM7XC128

8.4 Memory Mapping

8.4.1 Internal RAM

8.4.2 Internal ROM

8.4.3 Internal Flash

8.5 Embedded Flash

8.5.1 Flash Overview

8.5.2 Embedded Flash Controller

8.5.3 Lock Regions

8.5.3.1 AT91SAM7XC512

8.5.3.2 AT91SAM7XC256

8.5.3.3 AT91SAM7XC128

8.5.4 Security Bit Feature

8.5.5 Non-volatile Brownout Detector Control

8.5.6 Calibration Bits

8.6 Fast Flash Programming Interface

8.7 SAM-BA Boot Assistant

9. System Controller

9.1 Reset Controller

9.1.1 Brownout Detector and Power-on Reset

9.2 Clock Generator

9.3 Power Management Controller

9.4 Advanced Interrupt Controller

9.5 Debug Unit

9.6 Periodic Interval Timer

9.7 Watchdog Timer

9.8 Real-time Timer

9.9 PIO Controllers

9.10 Voltage Regulator Controller

10. Peripherals

10.1 User Interface

10.2 Peripheral Identifiers

10.3 Peripheral Multiplexing on PIO Lines

10.4 PIO Controller A Multiplexing

10.5 PIO Controller B Multiplexing

10.6 Ethernet MAC

10.7 Serial Peripheral Interface

10.8 Two-wire Interface

10.9 USART

10.10 Serial Synchronous Controller

10.11 Timer Counter

10.12 Pulse Width Modulation Controller

10.13 USB Device Port

10.14 CAN Controller

10.15 128-bit Advanced Encryption Standard

10.16 Triple Data Encryption Standard