ATMEL AT91SAM9G20 User Manual
BDTIC www.bdtic.com/ATMEL
Features
• Incorporates the ARM926EJ-S
– DSP Instruction Extensions, ARM Jazelle
– 32-KByte Data Cache, 32-KByte Instruction Cache, Write Buffer
– CPU Frequency 400 MHz
– Memory Management Unit
– EmbeddedICE
™
, Debug Communication Channel Support
• Additional Embedded Memories
– One 64-KByte Internal ROM, Single-cycle Access at Maximum Matrix Speed
– Two 16-KByte Internal SRAM, Single-cycle Access at Maximum Matrix Speed
• External Bus Interface (EBI)
– Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash
• USB 2.0 Full Speed (12 Mbits per second) Device Port
– On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM
• USB 2.0 Full Speed (12 Mbits per second) Host and Double Port
– Single or Dual On-chip Transceivers
– Integrated FIFOs and Dedicated DMA Channels
• Ethernet MAC 10/100 Base T
– Media Independent Interface or Reduced Media Independent Interface
– 128-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
• Image Sensor Interface
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
– 12-bit Data Interface for Support of High Sensibility Sensors
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
• Bus Matrix
– Six 32-bit-layer Matrix
– Boot Mode Select Option, Remap Command
• Fully-featured System Controller, including
– Reset Controller, Shutdown Controller
– Four 32-bit Battery Backup Registers for a Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer
• Reset Controller (RSTC)
– Based on a Power-on Reset Cell, Reset Source Identification and Reset Output
Control
• Clock Generator (CKGR)
– Selectable 32,768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on
Battery Backup Power Supply, Providing a Permanent Slow Clock
– 3 to 20 MHz On-chip Oscillator, One up to 800 MHz PLL and One up to 100 MHz PLL
• Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization
Capabilities
– Two Programmable External Clock Signals
• Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Three External Interrupt Sources and One Fast Interrupt Source, Spurious
Interrupt Protected
• Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel, Programmable ICE
Access Prevention
– Mode for General Purpose 2-wire UART Serial Communication
™
ARM® Thumb® Processor
®
Technology for Java® Acceleration
AT91 ARM
®
Thumb
Microcontrollers
AT91SAM9G20
Summary
NOTE: This is a summary document.
The complete document is available on
the Atmel website at www.atmel.com.
6384CS–ATARM–11-Mar-09
• Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
• Watchdog Timer (WDT)
– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
• Real-time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
• One 4-channel 10-bit Analog-to-Digital Converter
• Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC)
– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
– All I/O Lines are Schmitt Trigger Inputs
• Peripheral DMA Controller Channels (PDC)
• One Two-slot MultiMedia Card Interface (MCI)
™
– SDCard/SDIO and MultiMediaCard
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC
Compliant
• One Synchronous Serial Controller (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
• Four Universal Synchronous/Asynchronous Receiver Transmitters (USART)
®
– Individual Baud Rate Generator, IrDA
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
– Full Modem Signal Control on USART0
Infrared Modulation/Demodulation, Manchester Encoding/Decoding
• Two 2-wire UARTs
• Two Master/Slave Serial Peripheral Interfaces (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
– Synchronous Communications
• Two Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
– High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2
• One Two-wire Interface (TWI)
– Compatible with Standard Two-wire Serial Memories
– One, Two or Three Bytes for Slave Address
– Sequential Read/Write Operations
– Master, Multi-master and Slave Mode Operation
– Bit Rate: Up to 400 Kbits
– General Call Supported in Slave Mode
– Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode
®
• IEEE
1149.1 JTAG Boundary Scan on All Digital Pins
• Required Power Supplies
– 0.9V to 1.1V for VDDBU, VDDCORE, VDDPLL
– 1.65 to 3.6V for VDDOSC
– 1.65V to 3.6V for VDDIOP (Peripheral I/Os)
– 3.0V to 3.6V for VDDUSB
– 3.0V to 3.6V VDDANA (Analog-to-digital Converter)
– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os)
• Available in a 217-ball LFBGA and 247-ball TFBGA RoHS-compliant Package
2
AT91SAM9G20 Summary
6384CS–ATARM–11-Mar-09
1. Description
AT91SAM9G20 Summary
The AT91SAM9G20 is based on the integration of an ARM926EJ-S processor with fast ROM
and RAM memories and a wide range of peripherals.
The AT91SAM9G20 embeds an Ethernet MAC, one USB Device Port, and a USB Host controller. It also integrates several standard peripherals, such as the USART, SPI, TWI, Timer
Counters, Synchronous Serial Controller, ADC and MultiMedia Card Interface.
The AT91SAM9G20 is architectured on a 6-layer matrix, allowing a maximum internal bandwidth
of six 32-bit buses. It also features an External Bus Interface capable of interfacing with a wide
range of memory devices.
The AT91SAM9G20 is an enhancement of the AT91SAM9260 with the same peripheral features. It is pin-to-pin compatible with the exception of power supply pins. Speed is increased to
reach 400 MHz on the ARM core and 133 MHz on the system bus and EBI.
6384CS–ATARM–11-Mar-09
3
2. AT91SAM9G20 Block Diagram
ARM926EJ-S Processor
JTAG Selection and Boundary Scan
In-Circuit Emulator
AIC
Fast SRAM
16 Kbytes
D0-D15
A0/NBS0
A2-A15, A18-A20
A16/BA0
A17/BA1
NCS0
NCS1/SDCS
NRD/CFOE
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NWR3/NBS3/CFIOW
SDCK, SDCKE
RAS, CAS
SDWE, SDA10
FIQ
IRQ0-IRQ2
DRXD
DTXD
MMU
APB
ROM
64 Kbytes
Peripheral
Bridge
24-channel
Peripheral
DMA
Bus Interface
A1/NBS2/NWR2
TST
System
Controller
XIN
TDI
TDO
TMS
TCK
JTAGSEL
ID
NANDOE, NANDWE
PMC
OSC
XOUT
PITWDT
DBGU
SLAVEMASTER
PDC
BMS
A23-A24
NCS5/CFCS1
A25/CFRNW
NCS4/CFCS0
NWAIT
CFCE1-CFCE2
EBI
Static
Memory
Controller
CompactFlash
NAND Flash
SDRAM
Controller
NCS2, NCS6, NCS7
NCS3/NANDCS
RTCK
ECC
Controller
ETXCK-ERXCK
ETXEN-ETXER
ECRS-ECOL
ERXER-ERXDV
ERX0-ERX3
ETX0-ETX3
MDC
MDIO
F100
10/100 Ethernet
MAC
FIFO
DMA
FIFO
SSC
PDC
USB
Device
DDM
DDP
TK
TF
TD
RD
RF
RK
TC0
TC1
TC2
TCLK0-TCLK2
TIOA0-TIOA2
TIOB0-TIOB2
SPI0
SPI1
PDC
USART0
USART1
USART2
USART3
USART4
USART5
RTS0-RTS3
SCK0-SCK2
TXD0-TXD5
RXD0-RXD5
CTS0-CTS3
PDC
TWI
TWCK
TWD
MCI
PDC
Transceiver
DPRAM
ICache
32K bytes
DCache
32K bytes
6-layer Matrix
NPCS2
NPCS1
SPCK
MOSI
MISO
NPCS0
NPCS3
SPI0_, SPI1_
MCCK
MCDA0-MCDA3
MCCDA
NRST
XIN32
XOUT32
VDDCORE
PIOA
PIOB
PIOC
DSR0
DCD0
DTR0
RI0
USB
OHCI
DMA
Transc.
Transc.
HDPA
HDMA
HDPB
HDMB
Image
Sensor
Interface
DMA
ISI_PCK
ISI_DO-ISI_D7
ISI_HSYNC
ISI_VSYNC
ISI_MCK
4-channel
10-bit
ADC
AD0-AD3
ADTRIG
ADVREF
VDDANA
GNDANA
PDC
D16-D31
RTT
OSC
RSTC
POR
4GPREG
SHDN
WKUP
SHDC
POR
RC
OSCSEL
VDDBU
MCDB0-MCDB3
MCCDB
TC3
TC4
TC5
TCLK3-TCLK5
TIOA3-TIOA5
TIOB3-TIOB5
Fast SRAM
16 Kbytes
PDC
A21/NANDALE, A22/NANDCLE
PLLA
Filter
Filter
PLLB
Figure 2-1. AT91SAM9G20 Block Diagram
4
AT91SAM9G20 Summary
6384CS–ATARM–11-Mar-09
AT91SAM9G20 Summary
3. Signal Description
Table 3-1. Signal Description List (Continued)
Active
Signal Name Function Type
Power Supplies
VDDIOM EBI I/O Lines Power Supply Power 1.65V to 1.95V or 3.0V to 3.6V
VDDIOP Peripherals I/O Lines Power Supply Power 1.65V to 3.6V
VDDBU Backup I/O Lines Power Supply Power 0.9V to 1.1V
VDDANA Analog Power Supply Power 3.0V to 3.6V
VDDPLL PLL Power Supply Power 0.9V to 1.1V
VDDOSC Oscillator Power Supply Power 1.65V to 3.6V
VDDCORE Core Chip Power Supply Power 0.9V to 1.1V
VDDUSB USB Power Supply Power 1.65V to 3.6V
GND Ground Ground
GNDANA Analog Ground Ground
GNDBU Backup Ground Ground
GNDUSB USB Ground Ground
GNDPLL PLL Ground Ground
Clocks, Oscillators and PLLs
XIN Main Oscillator Input Input
XOUT Main Oscillator Output Output
XIN32 Slow Clock Oscillator Input Input
XOUT32 Slow Clock Oscillator Output Output
OSCSEL Slow Clock Oscillator Selection Input
PCK0 - PCK1 Programmable Clock Output Output
Shutdown, Wakeup Logic
SHDN Shutdown Control Output
WKUP Wake-up Input Input
ICE and JTAG
NTRST Test Reset Signal Input Low Pull-up resistor
TCK Test Clock Input No pull-up resistor
TDI Test Data In Input No pull-up resistor
TDO Test Data Out Output
TMS Test Mode Select Input No pull-up resistor
JTAGSEL JTAG Selection Input
RTCK Return Test Clock Output
Level Comments
Accepts between 0V and
VDDBU.
Accepts between 0V and
VDDBU.
Pull-down resistor. Accepts
between 0V and VDDBU.
6384CS–ATARM–11-Mar-09
5
Table 3-1. Signal Description List (Continued)
Active
Signal Name Function Type
Reset/Test
NRST Microcontroller Reset I/O Low Pull-up resistor
TST Test Mode Select Input
BMS Boot Mode Select Input
Debug Unit - DBGU
DRXD Debug Receive Data Input
DTXD Debug Transmit Data Output
Advanced Interrupt Controller - AIC
IRQ0 - IRQ2 External Interrupt Inputs Input
FIQ Fast Interrupt Input Input
PIO Controller - PIOA - PIOB - PIOC
PA0 - PA31 Parallel IO Controller A I/O Pulled-up input at reset
PB0 - PB31 Parallel IO Controller B I/O Pulled-up input at reset
PC0 - PC31 Parallel IO Controller C I/O Pulled-up input at reset
External Bus Interface - EBI
D0 - D31 Data Bus I/O Pulled-up input at reset
A0 - A25 Address Bus Output 0 at reset
NWAIT External Wait Signal Input Low
Static Memory Controller - SMC
NCS0 - NCS7 Chip Select Lines Output Low
NWR0 - NWR3 Write Signal Output Low
NRD Read Signal Output Low
NWE Write Enable Output Low
NBS0 - NBS3 Byte Mask Signal Output Low
CompactFlash Support
CFCE1 - CFCE2 CompactFlash Chip Enable Output Low
CFOE CompactFlash Output Enable Output Low
CFWE CompactFlash Write Enable Output Low
CFIOR CompactFlash IO Read Output Low
CFIOW CompactFlash IO Write Output Low
CFRNW CompactFlash Read Not Write Output
CFCS0 - CFCS1 CompactFlash Chip Select Lines Output Low
Level Comments
Pull-down resistor. Accepts
between 0V and VDDBU.
No pull-up resistor
BMS = 0 when tied to GND.
BMS = 1 when tied to VDDIOP.
6
AT91SAM9G20 Summary
6384CS–ATARM–11-Mar-09
AT91SAM9G20 Summary
Table 3-1. Signal Description List (Continued)
Active
Signal Name Function Type
NAND Flash Support
NANDCS NAND Flash Chip Select Output Low
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low
NANDALE NAND Flash Address Latch Enable Output Low
NANDCLE NAND Flash Command Latch Enable Output Low
SDRAM Controller
SDCK SDRAM Clock Output
SDCKE SDRAM Clock Enable Output High
SDCS SDRAM Controller Chip Select Output Low
BA0 - BA1 Bank Select Output
SDWE SDRAM Write Enable Output Low
RAS - CAS Row and Column Signal Output Low
SDA10 SDRAM Address 10 Line Output
Multimedia Card Interface MCI
MCCK Multimedia Card Clock Output
MCCDA Multimedia Card Slot A Command I/O
MCDA0 - MCDA3 Multimedia Card Slot A Data I/O
MCCDB Multimedia Card Slot B Command I/O
MCDB0 - MCDB3 Multimedia Card Slot B Data I/O
Universal Synchronous Asynchronous Receiver Transmitter USARTx
SCKx USARTx Serial Clock I/O
TXDx USARTx Transmit Data I/O
RXDx USARTx Receive Data Input
RTSx USARTx Request To Send Output
CTSx USARTx Clear To Send Input
DTR0 USART0 Data Terminal Ready Output
DSR0 USART0 Data Set Ready Input
DCD0 USART0 Data Carrier Detect Input
RI0 USART0 Ring Indicator Input
Synchronous Serial Controller - SSC
TD SSC Transmit Data Output
RD SSC Receive Data Input
TK SSC Transmit Clock I/O
RK SSC Receive Clock I/O
TF SSC Transmit Frame Sync I/O
RF SSC Receive Frame Sync I/O
Level Comments
6384CS–ATARM–11-Mar-09
7
Table 3-1. Signal Description List (Continued)
Active
Signal Name Function Type
Timer/Counter - TCx
TCLKx TC Channel x External Clock Input Input
TIOAx TC Channel x I/O Line A I/O
TIOBx TC Channel x I/O Line B I/O
Serial Peripheral Interface - SPIx_
SPIx_MISO Master In Slave Out I/O
SPIx_MOSI Master Out Slave In I/O
SPIx_SPCK SPI Serial Clock I/O
SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low
SPIx_NPCS1-SPIx_NPCS3 SPI Peripheral Chip Select Output Low
Two-Wire Interface
TWD Two-wire Serial Data I/O
TWCK Two-wire Serial Clock I/O
USB Host Port
HDPA USB Host Port A Data + Analog
HDMA USB Host Port A Data - Analog
HDPB USB Host Port B Data + Analog
HDMB USB Host Port B Data - Analog
USB Device Port
DDM USB Device Port Data - Analog
DDP USB Device Port Data + Analog
Ethernet 10/100
ETXCK Transmit Clock or Reference Clock Input MII only, REFCK in RMII
ERXCK Receive Clock Input MII only
ETXEN Transmit Enable Output
ETX0-ETX3 Transmit Data Output ETX0-ETX1 only in RMII
ETXER Transmit Coding Error Output MII only
ERXDV Receive Data Valid Input RXDV in MII, CRSDV in RMII
ERX0-ERX3 Receive Data Input ERX0-ERX1 only in RMII
ERXER Receive Error Input
ECRS Carrier Sense and Data Valid Input MII only
ECOL Collision Detect Input MII only
EMDC Management Data Clock Output
EMDIO Management Data Input/Output I/O
Level Comments
8
AT91SAM9G20 Summary
6384CS–ATARM–11-Mar-09
AT91SAM9G20 Summary
Table 3-1. Signal Description List (Continued)
Active
Signal Name Function Type
Image Sensor Interface
ISI_D0-ISI_D11 Image Sensor Data Input
ISI_MCK Image Sensor Reference Clock Output
ISI_HSYNC Image Sensor Horizontal Synchro Input
ISI_VSYNC Image Sensor Vertical Synchro Input
ISI_PCK Image Sensor Data clock Input
Analog to Digital Converter
AD0-AD3 Analog Inputs Analog Digital pulled-up inputs at reset
ADVREF Analog Positive Reference Analog
ADTRG ADC Trigger Input
Note: No PLLRCA line present on the AT91SAM9G20.
4. Package and Pinout
Level Comments
• The AT91SAM9G20 is available in a 217-ball, 15 x 15 mm, LFBGA package (0.8 mm pitch)
(Figure 4-1).
• The AT91SAM9G20 is available in a 247-ball, 10 x 10 x 1.1 mm, TFBGA Green package, ,
(0.5 mm pitch) (Figure 4-2).
4.1 217-ball LFBGA Package Outline
Figure 4-1 shows the orientation of the 217-ball LFBGA package.
A detailed mechanical description is given in the section “AT91SAM9G20 Mechanical Characteristics” of the product datasheet.
Figure 4-1.
217-ball LFBGA Package (Top View)
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
6384CS–ATARM–11-Mar-09
Ball A1
ABCDEFGHJKLMNPRTU
9
4.2 217-ball LFBGA Pinout
Table 4-1. Pinout for 217-ball LFBGA Package
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name
A1 CFIOW/NBS3/NWR3 D5 A5 J14 TDO P17 PB5
A2 NBS0/A0 D6 GND J15 PB19 R1 NC
A3 NWR2/NBS2/A1 D7 A10 J16 TDI R2 GNDANA
A4 A6 D8 GND J17 PB16 R3 PC29
A5 A8 D9 VDDCORE K1 PC24 R4 VDDANA
A6 A11 D10 GNDUSB K2 PC20 R5 PB12
A7 A13 D11 VDDIOM K3 D15 R6 PB23
A8 BA0/A16 D12 GNDUSB K4 PC21 R7 GND
A9 A18 D13 DDM K8 GND R8 PB26
A10 A21 D14 HDPB K9 GND R9 PB28
A11 A22 D15 NC K10 GND R10 PA0
A12 CFWE/NWE/NWR0 D16 VDDBU K14 PB4 R11 PA4
A13 CFOE/NRD D17 XIN32 K15 PB17 R12 PA5
A14 NCS0 E1 D10 K16 GND R13 PA10
A15 PC5 E2 D5 K17 PB15 R14 PA21
A16 PC6 E3 D3 L1 GND R15 PA23
A17 PC4 E4 D4 L2 PC26 R16 PA24
B1 SDCK E14 HDPA L3 PC25 R17 PA29
B2 CFIOR/NBS1/NWR1 E15 HDMA L4 VDDOSC T1 NC
B3 SDCS/NCS1 E16 GNDBU L14 PA28 T2 GNDPLL
B4 SDA10 E17 XOUT32 L15 PB9 T3 PC0
B5 A3 F1 D13 L16 PB8 T4 PC1
B6 A7 F2 SDWE L17 PB14 T5 PB10
B7 A12 F3 D6 M1 VDDCORE T6 PB22
B8 A15 F4 GND M2 PC31 T7 GND
B9 A20 F14 OSCSEL M3 GND T8 PB29
B10 NANDWE F15 BMS M4 PC22 T9 PA2
B11 PC7 F16 JTAGSEL M14 PB1 T10 PA6
B12 PC10 F17 TST M15 PB2 T11 PA8
B13 PC13 G1 PC15 M16 PB3 T12 PA11
B14 PC11 G2 D7 M17 PB7 T13 VDDCORE
B15 PC14 G3 SDCKE N1 XIN T14 PA20
B16 PC8 G4 VDDIOM N2 VDDPLL T15 GND
B17 WKUP G14 GND N3 PC23 T16 PA22
C1 D8 G15 NRST N4 PC27 T17 PA27
C2 D1 G16 RTCK N14 PA31 U1 GNDPLL
C3 CAS G17 TMS N15 PA30 U2 ADVREF
C4 A2 H1 PC18 N16 PB0 U3 PC2
C5 A4 H2 D14 N17 PB6 U4 PC3
C6 A9 H3 D12 P1 XOUT U5 PB20
C7 A14 H4 D11 P2 VDDPLL U6 PB21
C8 BA1/A17 H8 GND P3 PC30 U7 PB25
C9 A19 H9 GND P4 PC28 U8 PB27
C10 NANDOE H10 GND P5 PB11 U9 PA12
C11 PC9 H14 VDDCORE P6 PB13 U10 PA13
C12 PC12 H15 TCK P7 PB24 U11 PA14
C13 DDP H16 NTRST P8 VDDIOP U12 PA15
C14 HDMB H17 PB18 P9 PB30 U13 PA19
C15 NC J1 PC19 P10 PB31 U14 PA17
C16 VDDUSB J2 PC17 P11 PA1 U15 PA16
C17 SHDN J3 VDDIOM P12 PA3 U16 PA18
D1 D9 J4 PC16 P13 PA7 U17 VDDIOP
D2 D2 J8 GND P14 PA9
D3 RAS J9 GND P15 PA26
D4 D0 J10 GND P16 PA25
10
AT91SAM9G20 Summary
6384CS–ATARM–11-Mar-09
4.3 247-ball TFBGA Package Outline
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Ball A1
Figure 4-2 shows the orientation of the 247-ball TFBGA package.
A detailed mechanical description is given in the section “AT91SAM9G20 Mechanical Characteristics” of the product datasheet.
AT91SAM9G20 Summary
Figure 4-2.
247-ball TFBGA Package (Bottom View)
6384CS–ATARM–11-Mar-09
11
4.4 247-ball TFBGA Package Pinout
Table 4-2. Pinout for 247-ball TFBGA Package
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name
A1 D13 F7 CFIOR/NBS1/NWR1 K10 GND P17 RTCK
A2 D12 F8 SDA10 K11 VDDIOM P18 PB16
A12 A9 F9 NBS0/A0 K12 GND R2 GND
A14 A13 F10 A6 K13 GND R3 PB29
A16 A20 F11 A12 K14 XOUT32 R5 PB26
A18 A22 F12 A15 K15 XIN32 R6 PB27
A19 NANDOE F13 BA1/A17 K17 HDPA R7 PA5
B1 D15 F14 PC10 K18 HDMA R8 GND
B2 D14 F15 PC14 L2 NC R9 PA12
B3 D10 F16 VDDUSB L3 NC R10 GND
B4 D9 F17 PC9 L5 ADVREF R11 PA19
B5 D7 F18 PC12 L6 PC2 R12 PA26
B6 D3 G2 PC26 L7 GND R13 PB1
B7 D2 G3 PC25 L8 GND R14 GND
B8 RAS G5 PC24 L9 GND R15 PB7
B9 CAS G6 PC21 L10 GND R17 PB14
B10 NWR2/NBS2/A1 G8 VDDCORE L11 VDDCORE R18 PB9
B11 A3 G9 A5 L12 GND T2 PA1
B13 A10 G10 VDDCORE L13 OSCSEL T3 PB10
B15 A18 G11 VDDCORE L14 GNDBU T17 PB19
B17 A21 G12 VDDCORE L15 GND T18 PB17
B19 VDDUSB G14 PC13 L17 NRST U2 GNDANA
C2 PC15 G15 GND L18 TCK U3 PB21
C3 D11 G17 GNDUSB M2 PC0 U4 PB28
C4 D8 G18 PC11 M3 PC1 U5 PB31
C5 SDCKE H2 PC31 M5 PC3 U6 PA4
C6 SDWE H3 PC30 M6 NTRST U7 PA3
C7 SDCK H5 PC28 M7 GND U8 PA9
C8 D1 H6 PC27 M8 GND U9 GND
C9 SDCS/NCS1 H7 PC29 M9 GND U10 PA15
C10A2 H8 GND M10PA16 U11 PA21
C11 A7 H9 GND M11 VDDCORE U12 PA25
C12 A11 H10 VDDIOM M12 GND U13 PA29
C14 A19 H11 VDDIOM M13 VDDIOP U14 PA27
C16 GNDUSB H12 GND M14 TST U15 PA31
C18 CFWE/NWE/NWR0 H13 VDDCORE M15 JTAGSEL U16 GND
D2 PC17 H14 SHDW M17 PB18 U17 PB2
D3 PC16 H15 VDDBU M18 TMS U18 GND
D13 A14 H17 HDPB N2 PB20 V1 PB12
D15 NANDWE H18 HDMB N3 PB13 V2 PB23
D17 CFOE/NRD J2 VDDOSC N5 PB11 V3 PB30
D19 NCS0 J3 VDDPLL N6 BMS V4 PA2
E2 PC18 J5 XOUT N8 GND V5 PA8
E3 PC19 J6 XIN N11 PA17 V6 PA10
E5 D6 J7 VDDPLL N12 PA23 V7 PA13
E6 D5 J8 GND N14 GND V8 VDDIOP
E7 D0 J9 VDDIOM N15 VDDIOP V9 PA14
E8 CFIOW/NBS3/NWR3 J10 VDDIOM N17 TDO V10 VDDIOP
E9 GND J11 VDDIOM N18 TDI V11 PA20
E10 A4 J12 GND P2 PB24 V12 PA22
E11 A8 J13 GND P3 PB22 V13 VDDIOP
E12 VDDIOM J14 WKUP P5 GND V14 PA30
E13 BA0/A16 J15 DDP P6 GND V15 PB0
E14 PC8 J17 DDM P7 PA6 V16 GND
E15 PC4 J18 VDDIOP P8 PA7 V17 PB4
E16 PC5 K2 GNDPLL P9 PA11 V18 GND
E18 PC7 K3 GND P10 GND V19 PB6
E19 PC6 K5 NC P11 PA18 W1 PB25
F2 PC22 K6 GNDPLL P12 PA24 W2 PA0
F3 PC23 K7 VDDANA P13 PA28 W18 PB8
F5 PC20 K8 GND P14 PB3 W19 PB15
F6 D4 K9 GND P15 PB5
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AT91SAM9G20 Summary
6384CS–ATARM–11-Mar-09
5. Power Considerations
5.1 Power Supplies
The AT91SAM9G20 has several types of power supply pins:
• VDDCORE pins: Power the core, including the processor, the embedded memories and the
peripherals; voltage ranges from 0.9V to 1.1V, 1.0V nominal.
• VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges between 1.65V and
1.95V (1.8V typical) or between 3.0V and 3.6V (3.3V nominal). The voltage range is
selectable by software.
• VDDIOP pins: Power the Peripherals I/O lines; voltage ranges from 1.65V to 3.6V.
• VDDBU pin: Powers the Slow Clock oscillator, the internal RC oscillator and a part of the
System Controller; voltage ranges from 0.9V to 1.1V, 1.0V nominal.
• VDDPLL pin: Powers the PLL cells; voltage ranges from 0.9V to 1.1V.
• VDDOSC pin: Powers the Main Oscillator cells; voltage ranges from 1.65V to 3.6V
• VDDANA pin: Powers the Analog to Digital Converter; voltage ranges from 3.0V to 3.6V, 3.3V
nominal.
• VDDUSB pin: Powers USB transceiver; voltage ranges from 3.0V to 3.6V.
Ground pins GND are common to VDDCORE, VDDIOM, VDDOSC and VDDIOP pins power
supplies. Separated ground pins are provided for VDDBU, VDDPLL, VDDUSB and VDDANA.
These ground pins are respectively GNDBU, GNDPLL, GNDUSB and GNDANA.
AT91SAM9G20 Summary
5.2 Power Consumption
The AT91SAM9G20 consumes about 4 mA of static current on VDDCORE at 25°C. This static
current rises at up to 18 mA if the temperature increases to 85°C.
On VDDBU, the current does not exceed 9 µA at 25°C. This static current rises at up to 18 µA if
the temperature increases to 85°C.
For dynamic power consumption, the AT91SAM9G20 consumes a maximum of 50 mA on
VDDCORE at maximum conditions (1.0V, 25°C, rises to 80mA at 85°C, processor running fullperformance algorithm out of high-speed memories).
5.3 Programmable I/O Lines
The power supplies pins VDDIOM accept two voltage ranges. This allows the device to reach its
maximum speed either out of 1.8V or 3.3V external memories.
The maximum speed is 133 MHz on the pin SDCK (SDRAM Clock) loaded with 10 pF. The other
signals (control, address and data signals) do not go over 66 MHz, loaded with 30 pF for power
supply at 1.8V and 50 pF for power supply at 3.3V.
The EBI I/Os accept two slew rate modes, Fast and Slow. This allows to adapt the rising and falling time on SDRAM clock, control and data to the bus load.
The voltage ranges and the slew rates are determined by programming VDDIOMSEL and IOSR
bits in the Chip Configuration registers located in the Matrix User Interface.
At reset, the selected voltage defaults to 3.3V nominal and power supply pins can accept either
1.8V or 3.3V. The user must make sure to program the EBI voltage range before getting the
device out of its Slow Clock Mode.
At reset, the selected slew rates defaults are Fast.
6384CS–ATARM–11-Mar-09
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