ASUS H61M-CS User Manual
Intel® 820 Chipset
Design Guide
July 2000
Order Number: 290631-004
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
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Intel may make changes to specifications and product descriptions at any time, without notice.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
®
The Intel
Current characterized errata are available on request.
I
Implementations of the I
North American Philips Corporation.
Alert on LAN and Wake on LAN are results of the IBM/Intel Advanced Manageability Alliance and are trademarks of IBM Corporation.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by:
Copyright © Intel Corporation, 2000
*Third-party brands and names are the property of their respective owners.
820 chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel.
calling 1-800-548-4725 or
by visiting Intel's website at http://www.intel.com.
2
C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and
Intel® 820 Chipset Design Guide
Contents
1 Introduction................................................................................................................1-1
1.1 About This Design Guide..............................................................................1-1
1.2 References....................................................................................................1-2
1.3 System Overview..........................................................................................1-2
1.3.1 Chipset Components .......................................................................1-3
1.3.2 Bandwidth Summary........................................................................1-4
1.3.3 System Configuration.......................................................................1-5
1.4 Platform Initiatives.........................................................................................1-8
1.4.1 Direct Rambus*................................................................................1-8
1.4.2 Streaming SIMD Extensions............................................................1-8
1.4.3 AGP 2.0 ...........................................................................................1-8
1.4.4 Hub Interface ...................................................................................1-8
1.4.5 Manageability...................................................................................1-9
1.4.6 AC’97.............................................................................................1-10
1.4.7 Low Pin Count (LPC) Interface......................................................1-11
2 Layout/Routing Guidelines......... ...... ....... ...... ...... ....... ...... ....... ...... .............................2-1
2.1 General Recommendations ............. ...... ....... ...... ....... ...... ....... ...... ....... ...... ...2-1
2.2 Component Quadrant Layout........................................................................2-1
2.3 Intel
2.4 Core Chipset Routing Recommendations.....................................................2-4
2.5 Source Synchronous Strobing ......................................................................2-5
2.6 Direct Rambus* Interface..............................................................................2-7
2.7 AGP 2.0 ......................................................................................................2-31
2.8 Hub Interface ..............................................................................................2-43
®
820 Chipset Component Placement ...................................................2-3
2.6.1 Stackup............................................................................................2-8
2.6.2 Direct Rambus* Layout Guidelines..................................................2-8
2.6.3 Direct Rambus* Reference Voltage...............................................2-25
2.6.4 High-speed CMOS Routing ...........................................................2-25
2.6.5 Direct Rambus* Clock Routing ......................................................2-28
2.6.6 Direct Rambus* Design Checklist..................................................2-28
2.7.1 AGP Interface Signal Groups.........................................................2-32
2.7.2 1X Timing Domain Routing Guidelines..........................................2-33
2.7.3 2X/4X Timing Domain Routing Guidelines.....................................2-33
2.7.4 AGP 2.0 Routing Summary............................................................2-35
2.7.5 AGP Clock Routing........................................................................2-36
2.7.6 General AGP Routing Guideline s ........................................... ...... .2-36
2.7.7 VDDQ Generation and TYPEDET# ...............................................2-37
2.7.8 V
2.7.9 Compensation................................................................................2-41
2.7.10 AGP Pull-ups .................................................................................2-41
2.7.11 Motherboard / Add-in Card Interoperability....................................2-42
2.8.1 Data Signals...................................................................................2-44
2.8.2 Strobe Signals................................................................................2-44
2.8.3 HREF Generation/Distribution .......................................................2-44
2.8.4 Compensation................................................................................2-45
Generation for AGP 2.0 (2X and 4X)....................................2-39
REF
Intel® 820 Chipset Design Guide iii
2.9 System Bus Design ....................................................................................2-46
2.9.1 100/133 MHz System Bus .............................................................2-46
2.9.2 System Bus Ground Plane Reference...........................................2-47
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM) .................................2-47
2.11 Processor CMOS Pullup Values................................... ...... ....... ...... ....... ....2-49
2.12 Additional Host Bus Guidelines ..................................................................2-52
2.13 Ultra ATA/66 ...............................................................................................2-56
2.13.1 Ultra ATA/66 Detection ..................................................................2-56
2.13.2 Ultra ATA/66 Cable Detection........................................................2-57
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements ................................2-60
2.14 AC’97..........................................................................................................2-61
2.14.1 AC’97 Signal Quality Requirements...............................................2-63
2.14.2 AC’97 Motherboard Implementation..............................................2-63
2.15 USB ............................................................................................................2-65
2.16 ISA (82380AB)............................................................................................2-66
2.16.1 ICH GPIO connected to 82380AB .................................................2-66
2.16.2 Sub Class Code.............................................................................2-66
2.17 IOAPIC Design Recommendation ..............................................................2-66
2.18 SMBus/Alert Bus.........................................................................................2-67
2.19 PCI..............................................................................................................2-67
2.20 RTC ............................................................................................................2-67
2.20.1 RTC Crystal ...................................................................................2-68
2.20.2 External Capacitors .......................................................................2-68
2.20.3 RTC Layout Considerations...........................................................2-69
2.20.4 RTC External Battery Connection..................................................2-69
2.20.5 RTC External RTCRST Circuit.......................................................2-70
2.20.6 RTC Routing Guidelines................................................................2-70
2.20.7 VBIAS DC Voltage and Noise Measurements...............................2-71
3 Advanced System Bus Design ..................................................................................3-1
3.1 Terminology and Definitions.........................................................................3-1
3.2 AGTL+ Design Guidelines............................................................................3-4
3.2.1 Initial Timing Analysis......................................................................3-5
3.2.2 Determine General Topology, Layout, and Routing Desired...........3-8
3.2.3 Pre-Layout Simulation .....................................................................3-8
3.2.4 Place and Route Board..................................................................3-10
3.2.5 Post-Layout Simulation..................................................................3-13
3.2.6 Validation.......................................................................................3-14
3.3 Theory.........................................................................................................3-15
3.3.1 AGTL+ ...........................................................................................3-15
3.3.2 Timing Requirements.......................... ...... ....... ...... ....... ...... ....... ....3-16
3.3.3 Cross-talk Theory ..........................................................................3-16
3.4 More Details and Insight.............................................................................3-19
3.4.1 Textbook Timing Equations ...........................................................3-19
3.4.2 Effective Impedance and Tolerance/Variation ...............................3-20
3.4.3 Power/Reference Planes, PCB Stackup, and High
Frequency Decoupling...................................................................3-20
3.4.4 Clock Routing ................................................................................3-23
iv Intel
®
820 Chipset Design Guide
3.5 Definitions of Flight Time Measurements/Corrections and Signal Quality..3-24
3.5.1 V
Guardband............................................................................3-24
REF
3.5.2 Ringback Levels.............................................................................3-24
3.5.3 Overdrive Region...........................................................................3-24
3.5.4 Flight Time Definition and Measurement .......................................3-25
3.6 Conclusion ..................................................................................................3-26
4 Clocking.....................................................................................................................4-1
4.1 Clock Generation................................... ....... ...... ....... ...... ....... ......................4-1
4.2 Component Placement and Interconnection Layout Requirements..............4-6
4.2.1 14.318 MHz Crystal to CK133 .........................................................4-6
4.2.2 CK133 to DRCG ..............................................................................4-6
4.2.3 MCH to DRCG .................................................................................4-7
4.2.4 DRCG to RDRAM Channel....... ....... ...... ....................................... ...4-8
4.2.5 Trace Length....................................................................................4-8
4.3 DRCG Impedance Matching Circuit............................................................4-10
4.3.1 DRCG Layout Example.......................... ....... ...... ....... ...... ....... .......4-11
4.4 AGP Clock Routing Guidelines...................................................................4-11
4.5 Series Termination Resistors for CK133 Clock Outputs.............................4-11
4.6 Unused Outputs..........................................................................................4-12
4.7 Decoupling Recommendation for CK133 and DRCG.................................4-12
4.8 DRCG Frequency Selection and the DRCG+.............................................4-12
4.8.1 DRCG Frequency Selection Table and Jitter Specification ...........4-12
4.8.2 DRCG+ Frequency Selection Schematic.......................................4-13
5 System Manufacturing ...............................................................................................5-1
5.1 In Circuit LPC Flash BIOS Programming......................................................5-1
5.2 LPC Flash BIOS Vpp Design Guidelines......................................................5-1
5.3 Stackup Requirement ...................................................................................5-1
5.3.1 Overview..........................................................................................5-1
5.3.2 PCB Materials..................... ...... ....... ...... ....................................... ...5-2
5.3.3 Design Process............. ...... ...... ....... ...... ....... ...... .............................5-2
5.3.4 Test Coupon Design Guidelines ......................................................5-3
5.3.5 Recommended Stackup...................................................................5-3
5.3.6 Inner Layer Routing .........................................................................5-3
5.3.7 Impedance Calculation Tools...........................................................5-4
5.3.8 Testing Board Impedance................................................................5-4
5.3.9 Board Impedance/Stackup Summa ry .... ....... ...... ....... ...... ....... ...... ...5-5
6 System Design Considerations..................................................................................6-1
6.1 Power Delivery..............................................................................................6-1
6.1.1 Terminology and Definitions ............................... ....... ...... ................ 6-1
®
6.1.2 Intel
820 Chipset Customer Reference Board Power Delivery......6-2
6.1.3 64/72Mbit RDRAM Excessive Power Consumption ........................6-5
6.2 Power Plane Splits........................................................................................6-7
6.3 Thermal Design Power .................................................................................6-7
®
6.4 Glue Chip 3 (Intel
820 Chipset Glue Chip) .................................................6-8
A Reference Design Schematics: Uni-Proc es sor... ....... ...... ....... ...... ....... ...... ....... ...... .. A -1
A.1 Reference Design Feature Set .................................................................... A-1
B Reference Design Schematics: Dual-Proces sor. ....... ...... ....... ...... ....... ...... ....... ...... .. B -1
B.1 Reference Design Feature Set .................................................................... B-1
Intel® 820 Chipset Design Guide v
Figures
1-1 Intel® 820 Chipset Platform Performance Desktop Block Diagram..............1-5
1-2 Intel
®
820 Chipset Platform Performance Desktop Block Diagram
(with ISA Bridge)...........................................................................................1-6
1-3 Intel
®
820 Chipset Platform Dual-Processor Performance Desktop
Block Diagram ..............................................................................................1-7
1-4 AC’97 Connections.....................................................................................1-11
2-1 MCH 324-uBGA Quadrant Layout (Top View)..............................................2-2
2-2 ICH 241-uBGA Quadrant Layout (Top View)................................................2-2
2-3 Sample ATX MCH/ICH Component Placement............................................2-3
2-4 Primary Side MCH Core Routing Example (ATX) ........................................2-4
2-5 Secondary Side MCH Core Routing Example (ATX)....................................2-5
2-6 D ata Strob ing Exam ple............................. ....... ...... ....... ...... ....... ...... ....... ......2-6
2-7 Effect of Crosstalk on Strobe Signal.............................................................2-6
2-8 RIMM Diagram..............................................................................................2-7
2-9 R SL Rout ing Dimensi ons.............. ...... ...... ....... ...... ....... ...... ....... ...................2-9
2-10 RSL Routing Diagram ...... ...... ....... ...... ...... ....... ...... ....... ...... ....... ...................2-9
2-11 Primary Side RSL Breakout Example.........................................................2-10
2-12 Secondary Side RSL Breakout Example....................................................2-11
2-13 Direct RDRAM Termination........................................................................2-11
2-14 Direct Rambus* Termination Example........................................................2-12
2-15 Incorrect Direct Rambus* Ground Plane Referencing................................2-13
2-16 Direct Rambus Ground Plane Reference ...................................................2-13
2-17 Connector Compensation Example............................................................2-16
1
2-18 Section A
2-19 Section A
2-20 Section B
2-21 Section B
, Top Layer.................................................................................2-17
1
, Bottom Layer ...........................................................................2-18
1
, Top Layer.................................................................................2-19
1
, Bottom Layer ...........................................................................2-20
2-22 RSL Signal Layer Alternation .....................................................................2-21
2-23 RDRAM Trace Length Matching Example..................................................2-22
2-24 "Dummy" Via vs. Real "Via"........................................................................2-23
2-25 RAMRef Generation Example Circuit ........................................................2-25
2-26 High-Speed CMOS Termination.................................................................2-26
2-27 SIO Routing Example.................................................................................2-26
2-28 RDRAM CMOS Shunt Transistor ..............................................................2-27
2-29 AGP 2X/4X Routing Example for Interfaces < 6”........................................2-34
2-30 Top Signal Layer.........................................................................................2-37
2-31 AGP VDDQ Generation Example Circuit...................... ...... ....... ...... ....... ....2-39
2-32 AGP 2.0 VREF Generation & Distribution ..................................................2-40
2-33 Hub Interface Signal Routing Example.......................................................2-43
2-34 Single Hub Interface Reference Divider Circuit ..........................................2-44
2-35 Locally generated Hub Interface Reference Dividers .................................2-45
®
2-36 Intel
2-37 Intel
Pentium® III Processor Dual Processor Configuration .....................2-46
®
Pentium® III Processor Uni-Processor Configuration ............ ....... ....2-46
2-38 Ground Plane Reference (Four Layer Motherboard)..................................2-47
2-39 Hole Locat ion s and Kee pou t Zones For Suppo rt Comp one nts . ...... ....... ....2-48
2-40 Grounding Pad Dimensions for the SECC2 GRM ......................................2-48
2-41 TCK/TMS Implementation Example for DP Designs ..................................2-52
2-42 Single Processor BREQ Strapping Requirements......................................2-52
2-43 Dual-Processor BREQ Strapping Requirements........................................2-53
vi Intel
®
820 Chipset Design Guide
2-44 BREQ0# Circuitry for DP Systems..............................................................2-53
2-45 HA7# Strapping Option Example Circuit (For Debug Purposes Only)........2-54
2-46 Host-Side IDE Cable Detection...................................................................2-57
2-47 Drive-Side IDE Cable Detection..................................................................2-58
2-48 Layout for Host- or Drive-Side IDE Cable Detection...................................2-59
2-49 Ultra ATA/66 Cable.....................................................................................2-59
2-50 Resistor Requirements for Primary IDE Connector....................................2-60
2-51 Resistor Requirements for Secondary IDE Connector ...............................2-61
2-52 Tee Topology AC'97 Trace Length Requirements......................................2-62
2-53 Daisy-Chain Topology AC'97 Trace Length Requirements ........................2-62
2-54 USB Data Signa ls ............... ....... ...... ...... ....... ....................................... ...... .2-65
2-55 PCI Bus Layout Example............................................................................2-67
2-56 External Circuitry for the ICH RTC..............................................................2-68
2-57 Diode Circuit Connecting RTC External Battery.........................................2-69
2-58 RTCRST External Circuit for the ICH RTC .................................................2-70
3-1 PICD[1,0] Uni-Processor Topology.............................................................3-12
3-2 PICD[1,0] Dual-Processor Topology...........................................................3-12
3-3 Test Load vs. Actual System Load .............................................................3-14
3-4 Aggressor and Victim Networks..................................................................3-17
3-5 Transmission Line Geometry: (A) Microstrip (B) Stripline...........................3-17
3-6 One Signal Layer and One Reference Plane..............................................3-21
3-7 Layer Switch with One Reference Plane ....................................................3-21
3-8 Layer Switch with Multiple Reference Planes (same type).........................3-21
3-9 Layer Switch with Multiple Reference Planes.............................................3-22
3-10 One Layer with Multiple Reference Planes.................................................3-22
3-11 Overdrive Region and V
Guardband.....................................................3-25
REF
3-12 Rising Edge Flight Time Measurement.......................................................3-25
®
4-1 Intel
4-2 Intel
820 Chipset Platform Clock Distribution .............................................4-2
®
820 Chipset Clock Routing Guidelines ...............................................4-4
4-3 CK133 to DRCG Routing Diagram ...............................................................4-6
4-4 MCH to DRCG Routing Diagram ..................................................................4-7
4-5 Direct Rambus* Clock Routing Dimensions..................................................4-7
4-6 Differential Clock Routing Diagram (Section ‘A’, ‘C’, & ‘D’)...........................4-9
4-7 Non-Differential Clock Routing Diagram (Section ‘B’)...................................4-9
4-8 Termination for Direct Rambus* Clocking Signals CFM/CFM# ....................4-9
4-9 DRCG Impedance Matching Network.........................................................4-10
4-10 DRCG Layout Example.................... ....................................... ...... ....... ...... .4-11
4-11 DRCG+ Frequency Selection .....................................................................4-13
5-1 28Ω Trace Geometry ....................................................................................5-2
5-2 Microstrip and Stripline Cross-section for 28 Ω Trace ..................................5-4
5-3 7 mil Stackup (Not Routable)........................................................................5-5
5-4 4.5 mil Stackup .............................................................................................5-5
®
6-1 Intel
820 Chipset Power Delivery Example.................................................6-2
6-2 1.8V and 2.5V Power Sequencing (Schottky Diode) ....................................6-4
6-3 Use a GPO to Reduce DRCG Frequency.....................................................6-6
6-4 Power Plane Split Example...........................................................................6-7
Intel® 820 Chipset Design Guide vii
Tables
1-1 Intel® 820 Chipset Platform Bandwidth Summary ........................................1-4
2-1 AG P 2X Data/ Strobe Assoc iatio n . ...... ...... ....... ...... ....... ...... ....... ...... ....... ......2-6
2-2 Placement Guidelines for Motherboard Routing Lengths.............................2-9
2-3 Copper Tab Area Calculation .....................................................................2-15
2-4 RSL Routing Layer Requirements..............................................................2-21
2-5 Line Matching and Via Compensation Example.........................................2-24
2-6 Signal List ...................................................................................................2-28
2-7 AGP 2.0 Data/Strobe Associations.............................................................2-33
2-8 AG P 2.0 Routing Su mma ry ............................. ...... ....... ...... ....... ...... ....... ....2-35
2-9 TYPDET#/VDDQ Relationship ...................................................................2-38
2-10 Connector/Add-in Card Interoperability ......................................................2-42
2-11 Voltage/Data Rate Interoperability..............................................................2-42
2-12 Segment Descriptions and Lengths for Figure 2-36 ...................................2-46
2-13 Proc esso r and 828 20 MCH Connecti on Chec kli st.............. ....... ...... ....... ....2- 49
®
2-14 Bus Request Connection Scheme for DP Intel
820 Chipset Designs.......2-52
2-15 ICH Codec Options.....................................................................................2-61
2-16 AC'97 SDIN Pulldown Resistors.................................................................2-63
3-1 AGTL+ Parameters for Example Calculations..............................................3-6
3-2 Example T
3-3 Example T
FLT_MAX
FLT_MIN
Calculations for 133 MHz Bus .......................................3-7
Calculations (Frequency Independent)...........................3-8
3-4 Trac e Width Spa ce Guidel ine s ........... ...... ....... ...... .....................................3-11
3-5 Host Clock Routing.....................................................................................3-12
®
4-1 Intel
4-2 Intel
4-3 Intel
820 Chipset Platform System Clocks..................................................4-1
®
820 Chipset Platform Clock Skews.....................................................4-3
®
820 Chipset Platform System Clock Cross-Reference .......................4-5
4-4 Placement Guidelines for Motherboard Routing Lengths.............................4-8
4-5 External DRCG Component Values ...........................................................4-10
4-6 Unused Output Termination........................................................................4-12
4-7 DRCG Ratio................................................................................................4-12
5-1 28Ω Stackup Examples ................................................................................5-3
5-2 3D Field Solver vs ZCALC............................................................................5-4
®
6-1 Intel
820 Chipset Component Thermal Design Power................................6-7
6-2 Glue Chip 3 Vendors ....................................................................................6-8
viii Intel
®
820 Chipset Design Guide
Revision History
Revision Description Date
-001 Initial Release. November 1999
• Added dual-processor schematics (Appendix B).
• Uni-processor schematics have been updated (Appendix A). See the
-002
-003
-004 • Minor edits for clarity July 2000
schematic revision history page at the end of Appendix A for details.
- The following update is not in the schematic revision history.
Cap C249 (schematic page 9) has been changed from 0.022 uF to
0.047 uF.
• Updated the text descriptions in the two paragraphs in Section 4.2.3,
“MCH to DRCG”.
• Updated the first paragraph in Section 2.6.2.5, “RSL Signal Layer
Alternation“.
December 1999
January 2000
Intel® 820 Chipset Design Guide ix
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x Intel
®
820 Chipset Design Guide
1
Introduction
This page is intentionally left blank.
Introduction
Introduction
The Intel® 820 Chipset Design Guide provides design recommendations for systems using the
®
Intel
820 chipset. This includes motherboard layout and routing guidelines, system design issues
and requirements, debug recommendations, and board schematics. The design recommendations
should be used during system design. The guidelines have been developed to ensure maximum
flexibility for board designers while reducing the risk of board-related issues.
The Intel board schematics in Append ix A (uni-processo r) and Appen dix B (dual-proces sor) can be
used as references for board designers. A feature list is provid ed at the beg inning o f each appe ndix.
Although these schematics cover specific designs, the co re schematics for each chip set co mpon ent
remains the same for most Intel
schematics for each chipset component, in addition to common motherboard options. Additional
flexibility is possible through other permutations of these options and components.
1.1 About This Design Guide
This design guide is intended for hardware designers who are experienced with PC architectures
and board design. The design guide assumes that the designer has a working knowledge of the
vocabulary and practices of PC hardware design.
•
This chapter introduces the designer to the purpose and organization of this design guide, and
provides a list of references of related documents. This chapter also provides an overview of
the Intel
•
Chapter 2, "Layout/Routing Guidelines"—This chapter provides a detailed set of motherboard
layout and routing guidelines for designing an Intel
motherboard functional units are covered (e.g., chipset component placement, system bus
routing, system memory layout, display cache interface, hub interface, IDE, AC’97, USB,
interrupts, SMBUS, PCD, LPC/FWH Flash BI OS, and RTC).
•
Chapter 3, "Advanced System Bus Design"— AGTL+ guidelines and theory of operation are
discussed. This chapter also provides more detail about the methodologies used to develop the
guidelines.
•
Chapter 4, "Clocking"— This chapter provides motherboard clocking guidelines (e.g., clock
architecture, routing, capacitor sites, clock power decoupling, and clock skew).
•
Chapter 5, "System Manufacturing"— This chapter includes board stackup requirements.
•
Chapter 6, "System Design Considerations"— This chapter includes guidelines regarding
power delivery, decoupling, thermal, and power sequencing.
•
Appendix A, "Reference Board Schematics: Uni-Processor "— This appendix provides a set
of schematics for Uni-processor designs. A feature list for the board design is also provided.
•
Appendix B, "Reference Board Schematics: Dual-Processor "— This appendix provid es a set
of schematics for dual-processor designs. A feature list for the board design is also provided.
®
820 chipset.
®
820 chipset platforms. The appendices provides a set of reference
®
820 chipset based platform. The
1
Intel®820 Chipset Design Guide 1-1
Introduction
1.2 References
•
Intel® 820 Chipset: Intel® 82820 Memory Controller Hub (MCH) Datasheet
(Order Number: 290630)
•
Intel® 82801AA (ICH) and Intel® 82801AB (ICH0) I/O Controller Hub Datasheet
(Order Number: 290655)
•
Intel® 82802AB/82802AC FirmWare Hub (FWH) Datasheet (Order Number: 290658)
•
Pentium® II Processor AGTL+ Guidelines (Order Number: 243330)
•
Pentium® II Processor Power Distribution Guideline (Order Number: 243332)
•
Pentium® II Processor Developer's Manual (Order Number: 243341)
•
Pentium® III Processor Specification Update (latest off of website)
•
AP 907 Pentium III processor Power Distribution Guideline s (Order Number 245085)
•
AP-585 Pentium II Processor AGTL+ Guidelines (Order Number: 243330)
•
AP-587 Pentium II Processor Power Distribution Guidelines (Order Number: 243332)
•
CK97 Clock Synthesizer Design Guidelines (Order Number 243867)
•
PCI Local Bus Specification, Revision 2.2
•
Universal Serial Bus Specification, Revision 1.0
•
VRM 8.4 DC-DC Converter Design Guidelines (when available)
1.3 System Overview
The Intel® 820 chipset is the third generation desktop chipset designed for Intel’s SC242
architecture and the first chipset to support the 4X capability of the AGP 2.0 I nterface Specification
and 400 MHz Direct RDRAM. The 400 MHz, 16 bit, double clocked Direct RDRAM interface
provides 1.6 GB/s access to main memory. A new chipset component interconnect, the hub
interface, is designed into the Intel
chipset components.
Support of AGP 4X, 400 MHz Direct RDRAM and the hub interface provides a balanced system
architecture for the Pentium III processor, minimizing bottlenecks and increasing system
performance. By increasing memory bandwidth to 1.6 GB/s through the use of 400 MHz Direct
RDRAM and increasing graphics bandwidth to 1 GB/s through the use of AGP 4X, the Intel
chipset delivers the data throughpu t necess ary to t ake advan t age of the hi gh perfo rmance provided
by the powerful Pentium III processor.
In addition, the Intel
infrastructure through the Firmware Hub component.
The ACPI compliant Intel
RAM, Suspend to Disk, and Soft-off power management states. Through the use of an appropriate
LAN device, Intel
troubleshooting.
The Intel
traditionally integrated into the I/O subsystem of Intel chipsets. This removes many of the conflicts
experienced when installing hardware and drivers into legacy ISA systems. The elimination of ISA
provides true plug-and-play for the Intel
was used for audio and modem devices. The addition of AC’97 allows the OEM to use software
®
820 chipset architecture removes the requirement for the ISA expansion bus that was
®
820 chipset architecture enables a new security and manageability
®
820 chipset platform can support the Full-on, Stop Grant, Suspend to
®
820 chipset also supports Wake on LAN* for remote administration and
®
820 chipset to provide more efficient communication between
®
®
820 chipset platform. Traditionally, the ISA interface
820
1-2 Intel
®
820 Chipset Design Guide
Introduction
configurable AC’97 audio and modem coder/decoders (codecs) instead of the traditional ISA
devices. The ISA bus can be implemented through the use of the optional 82380AB PCI-ISA
bridge.
The Intel
I/O Controller Hub (ICH). The MCH integrates the 133 MHz processor system bus controller,
AGP 2.0 controller, 400 MHz Direct RDRAM controller and a high-speed hub interface for
communication with the ICH. The ICH integrates an UltraATA/66 controller, USB host controller,
LPC interface controller, FWH Flash BIOS interface controller, PCI interface controller, AC’97
digital controller and a hub interface for communication with the MCH. The Intel
provides the data buffering and interface arbitration required to ensure that system interfaces
operate efficiently and provide the system bandwidth necessary to obtain peak performance with
the Pentium III processor.
®
820 chipset contains tw o core components: the Memory Controller Hub (MCH) and the
1.3.1 Chipset Components
This section provides an overview of the 82820 Memory Controller Hub (MCH) and the 82801AA
I/O Controller Hub (ICH). Additional functionality can be provided using the 82380AB PCI-ISA
bridge.
Memory Controller Hub (MCH)
The MCH provides the interconnect between the Direct R DRAM and the system log ic. It integrates
the following functions:
•
Support for single or dual SC242 processors with 100 MHz or 133 MHz System Bus
•
256 MHz, 300 MHz, 356 MHz or 400 MHz Direct RDRAM interface supporting 1 GB of
Direct RDRAM
•
4X, 1.5V AGP interface (3.3V 1X, 2X and 1.5V 1X, 2X devices also supported)
®
820 chipset
•
Downstream hub interface for access to the ICH
In addition, the MCH provides arbitration, buffering and coherency management for each of these
interfaces. Refer to Chapter 2, “Layout/Routing Guidelines” for more information regarding these
interfaces.
Intel®820 Chipset Design Guide 1-3
Introduction
I/O Controller Hub (ICH)
The I/O Controller Hub provides the I/O subsystem with access to the rest of the system.
Additionally, it integrates many I/O functions. The ICH integrates the following functions:
•
Upstream hub interface for access to the MCH
•
2 channel Ultra ATA/66 Bus Master IDE controller
•
USB controller
•
I/O APIC
•
SMBus controller
•
FWH interface (FWH Flash BIOS)
•
LPC interface
•
AC’97 2.1 interface
•
PCI 2.2 interface
•
Integrated System Management Controller
•
Alert on LAN*
The ICH also contains the arbitration and buffering necessary to ensure efficient utilization of these
interfaces. Refer to Chapter 2, “Layout/Routing Guidelines” for more information on these
interfaces.
ISA Bridge (82380AB)
For legacy needs, ISA support is an optional feature of the Intel® 820 chipset. Implementations that
require ISA support can benefit from the enhancements of the Intel
designs are not burdened with the complexity and cost of the ISA subsystem.
The Intel
®
820 chipset platform with optional ISA support takes advantage of the 82380AB ISA
bridge. The bridge is a PCI to ISA bridge and resides on the PCI bus of the ICH.
1.3.2 Bandwidth Summary
Table 1-1 provides a summary of the bandwidth requirements for the Intel® 820 chipset.
T a ble 1-1. Intel
®
820 Chipset Platform Bandwidth Summary
Interface
Processor Bus 133 1 133 8 1066
RDRAM 266/300/356/400 2 533/600/711/800 2 1066/1200/1422/1600
AGP 2.0 66 4 266 4 1066
Hub Interface 66 4 266 1 266
PCI 2.2 33 1 33 4 133
Clock Speed
(MHz)
Samples
Per Clock
Data Rate
(Mega-samples/s)
®
820 chipset while “ISA-less”
Data Width
(Bytes)
Bandwidth
(MB/s)
1-4 Intel
®
820 Chipset Design Guide
1.3.3 System Configuration
s
The following figures show typical platform configurations using the Intel® 820 chipset.
®
Figure 1-1. Intel
820 Chipset Platform Performance Desktop Block Diagram
4X AGP
Graphics
Controller
4 IDE Drives
2 USB Ports
AGP 2.0
Processor
82820
Memory
Controller Hub
(MCH)
Hub Interface
Introduction
Main
Memory
PCI Slot
PCI Bus
AC'97 Codec(s)
(optional)
Keyboard,
Mouse, FD,
PP, SP, IR
AC'97 2.1
Super I/O
82801AA
I/O Controller Hub
(ICH)
LPC I/F
GPIO
FWH Flash
BIOS
Intel®820 Chipset Design Guide 1-5
Introduction
s
s
Figure 1-2. Intel® 820 Chipset Platform Performance Desktop Block Diagram (with ISA Bridge)
Processor
82820
4X AGP
Graphics
Controller
4 IDE Drives
2 USB Ports
AGP 2.0
Memory
Controller Hub
(MCH)
Hub Interface
Main
Memory
PCI Slot
PCI Bus
AC'97 Codec(s)
(optional)
Keyboard,
Mouse, FD,
PP, SP, IR
AC'97 2.1
Super I/O
LPC I/F
82801AA
I/O Controller Hub
(ICH)
FWH Flash
BIOS
ISA Bridge
(optional)
GPIO
ISA Slot
1-6 Intel
®
820 Chipset Design Guide
Introduction
s
s
Figure 1-3. Intel® 820 Chipset Platform Dual-Processor Performance Desktop Block Diagram
Processor Processor
Optional 2-Way/MP
82820
4X AGP
Graphics
Controller
4 IDE Drives
2 USB Ports
AGP 2.0
Memory
Controller Hub
(MCH)
Hub Interface
Main
Memory
PCI Slot
PCI Bus
AC'97 Codec(s)
(optional)
Keyboard,
Mouse, FD,
PP, SP, IR
AC'97 2.1
Super I/O
LPC I/F
82801AA
I/O Controller Hub
(ICH)
FWH Flash
BIOS
ISA Bridge
(optional)
GPIO
ISA Slot
Intel®820 Chipset Design Guide 1-7
Introduction
1.4 Platform Initiatives
1.4.1 Direct Rambus
The Direct Rambus* (RDRAM) initiative provides the memory bandwidth necessary to obtain
optimal performance from the Pentium III processor as well as a high-performance AGP graphics
controller. The MCH RDRAM interface supports 266 MHz, 300 MHz, 356 MHz, and 400 MH z
operation; the latter delivers 1.6 GB/s of theoretical memory bandwidth; twice the memo ry
bandwidth of 100 MHz SDRAM systems. Coupled with the greater bandwidth, the RDRAM
protocol, which is heavily pipelined, provides substantially more efficient data transfer. The
RDRAM memory interface can achieve greater than 95% utilization of the 1.6 GB/s theoretical
maximum bandwidth.
In addition to RDRAM’s performance features, the new memory architecture provides enhanced
power management capabilities. The powerdown mode of operation enables Intel
based systems to cost-effectively support suspend-to-RAM.
*
1.4.2 Streaming SIMD Extensions
The Pentium III processor provides 70 new Streaming SIMD (single instruction, multiple data)
Extensions. The Pentium III new extensions are floating point SIMD extensions . Inte l MMX™
technology provides integer SIMD extensions. The Pentium III processor new extensions
complement the Intel MMX™ technology SIMD extensions and provide a performance boost to
floating-point intensive 3D applications.
1.4.3 AGP 2.0
®
820 chipset
The AGP 2.0 interface, along with Direct Rambus* memory technology, allows graphics
controllers to access main memory at over 1 GB/s; twice the AGP bandwidth of previous AGP
platforms. AGP 2.0 provides the infrastructure necessary for photor ealistic 3D. In conjun ction with
Direct Rambus
the next level of 3D graphics performance.
*
and the Pentium III processor new Streaming SIMD Extensions, AGP 2.0 delivers
1.4.4 Hub Interface
As I/O speeds increase, the demand placed on the PCI bus by the I/O bridge has become
significant. With the addition of AC’97 and ATA/66, coupled with the existing USB, I/O
requirements will begin to impact PCI bus performance. The Intel
architecture ensures that the I/O subsystem, both PCI and the integrated I/O features (IDE, AC’97,
USB, etc.), receives adequate bandwidth. By placing the I/O bridge on the hub interface instead of
PCI, the hub architecture ensures that both the I/O functions integrated into the ICH and the PCI
peripherals obtain the bandwidth necessary for peak performance. In addition, the hub interface’s
lower pin count allows a smaller package for the MCH and ICH.
®
820 chipset’s hub interface
1-8 Intel
®
820 Chipset Design Guide
1.4.5 Manageability
The Intel® 820 chipset platform integrates several functions designed to manage the system and
lower the total cost of ownership (TCO) of the system. These system management functions are
designed to report errors, diagn os e the s yst em, an d reco ver fro m s ystem locku ps without th e aid o f
an external microcontroller.
TCO Timer
The ICH integrates a programmable TCO T imer. This timer is used to d etect system locks. The firs t
expiration of the timer generates an SMI# which the system can use to recover from a software
lock. The second expiration of the timer causes a system reset to recover from a hardware lock.
CPU Present Indicator
The ICH looks for the CPU to fetch the first instruction after reset. If the CPU does not fetch the
first instruction, the ICH will reboot the system at the safe-mode frequency multiplier.
ECC Error Reporting
Upon detecting an ECC error, the MCH can send one of several messages to the ICH. The MCH
can instruct the ICH to generate either an SMI#, NMI#, SERR#, or TCO interrupt.
Introduction
Function Disable
The ICH provides the ability to disable the following functions: AC'97 Modem, AC'97 Audio,
IDE, USB or SMBus. Once disabled, these functions no longer decode I/O, memory, or PCI
configuration space. Also, no interrupts or power management events are generated from the
disabled functions.
Intruder Detect
The ICH provides an input signal (INTRUDER#) that can be attached to a switch that is activated
by the system case being opened. The ICH can be programmed to generate an SMI# or TCO
interrupt due to an active INTRUDER# signal.
SMBus
The ICH integrates an SMBus controller. The SMBus provides an interface to manage peripherals
(e.g., serial presence detection (SPD) on RIMMs and thermal sensors).
Alert on LAN*
The ICH supports Alert on LAN*. In response to a TCO event (intruder detect, thermal event, CPU
not booting) the ICH sends a mes sage over A LERTCLK and ALERTDAT A. A LAN contro ller can
decode this alert message and send a message over the network to alert the network manager.
Intel®820 Chipset Design Guide 1-9
Introduction
1.4.6 AC’97
The Audio Codec’97 (AC’97) Specification defines a digital link that can be used to attach an
audio codec (AC), a modem codec (MC), an audio/modem codec (AMC), or both an AC and an
MC. The AC’97 Specification defines the interface between the system logic and the audio or
modem codec known as the AC’97 Digital Link.
The ability to add cost-effective audio and modem solutions is important as the platform migrates
away from ISA. In addition, the AC’97 audio and modem components are software configurable.
This reduces configuration errors. Intel
only replaces ISA audio and modem functionality, but also improves overall platform integration
by incorporating the AC’97 digital link. Using Intel
reduces cost and eases migration from ISA.
®
820 chipset’s AC’97 (with the appropriate codecs) not
®
820 chipset’s integrated AC’97 digital link
By using an audio codec, the AC’97 digital link allows for cost-effective, high-quality, integrated
audio on the Intel
with the use of a modem codec. Several system options exist when implementing AC’97. Intel
®
820 chipset platform. In addition, an AC’97 soft modem can be implemented
®
820 chipset’s integrated digital link allows two external codecs to be connected to the ICH. The
system designer can provide audio with an audio codec (Figure 1-4a) or a modem with a modem
codec (Figure 1-4b). For systems requiring both audio and a modem, there are two solutions. The
audio codec and the modem codec can be integrated into a single Audio Modem Codec (AMC)
(Figure 1-4c), or separate audio and modem codecs can be connected to the ICH (Figure 1-4d).
Modem implementation for different co untries mu st b e con sidered as teleph one sy stems may var y.
By using a split design, the audio codec can be on-board and the modem codec can be placed on a
riser. With a single integrated codec, or AMC, both audio and modem can be routed to a connector
near the rear panel where the external ports can be located.
The digital link in the ICH is AC’97 Rev. 2.1 compliant, supporting two codecs with independent
PCI functions for audio and modem. Microphone input and left and right audio channels are
supported for a high quality two-speaker audio solution. Wake on ring from suspend is also
supported with an appropriate modem codec.
1-10 Intel
®
820 Chipset Design Guide
Figure 1-4. (a-d) AC’97 Connections
a) AC'97 With Audio Codec
Introduction
ICH
(241 mBGA)
b) AC'97 With Modem Codec
ICH
(241 mBGA)
c) AC'97 With Audio/Modem Codec
ICH
(241 mBGA)
d) AC'97 With Audio and Modem Codec
ICH
(241 mBGA)
AC'97 Digital
Link
AC'97 Digital
Link
AC'97 Digital
Link
AC'97
Digital Link
AC'97
Audio
Codec
AC'97
Modem
Codec
AC'97
Audio/
Modem
Codec
AC'97
Modem
Codec
AC'97
Audio
Codec
Audio Ports
Modem Port
Modem Port
Audio Ports
Modem Port
Audio Ports
1.4.7 Low Pin Count (LPC) Interface
In the Intel® 820 chipset platform, the super I/O component has migrated to the Low Pin Count
(LPC) interface. Migration to the LPC interface allows for lower cost super I/O designs. The LPC
super I/O component requires the same feature set as traditional super I/O components. It should
include a keyboard and mouse controller, floppy disk controller and serial and parallel ports. In
addition to the super I/O features, an integrated game port is recommended because the AC’97
interface does not provide support for a game port. In a system with ISA audio, the game port
typically existed on the audio card. The fifteen pin game port connect o r prov ides fo r two joys t ic ks
and a two-wire MPU-401 MIDI interface. Consult your super I/O vendor for a comprehensive list
of devices offered and features supported.
In addition, depending on system requirements, a device bay controller and USB hub could be
integrated into the LPC super I/O component. For systems requiring ISA support, an ISA-IRQ to
serial-IRQ converter is required. Potentially, this converter could be integrated into the super I/O.
Intel®820 Chipset Design Guide 1-11
Introduction
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1-12 Intel
®
820 Chipset Design Guide
2
Layout and Routing
Guidelines
This page is intentionally left blank.
Layout/Routing Guidelines
Layout/Routing Guidelines
This chapter documents motherboard layout and routing guidelines for Intel® 820 chipset based
systems. This section does not discuss the functional aspects of any bus, or the layout guidelines
for an add-in device.
Caution: If the guidelines listed in this document are not followed, it is very important that thorough
signal integrity and timing simulations are completed for each design. Even when the
guidelines are followed, critical signals should still be simulated to ensure proper signal integrity
and flight time. As bus speeds increase, it is imperative that the guidelines documented are
followed precisely. Any deviation from these guidelines must be simulated!
2.1 General Recommendations
The trace impedance typically noted (i.e., 60Ω ±10%) is the “nominal” trace impedance. That is,
the impedance of the trace when not subjected to the fields created by changing current in
neighboring traces. When calculating flight times, it is important to consider the minimum and
maximum impedance of a trace based on the switching of neighboring traces. Using wider spaces
between the traces can minimize this trace-to-trace coupling. In addition, these wider spaces reduce
crosstalk and settling time.
Coupling between two traces is a function of the coup led length , the d istance sep arating the traces ,
the signal edge rate, and the degree of mutual capacitance and inductance. In order to minimize the
effects of trace-to-trace coupling, the routing guidelines documented in this section should be
followed. In addition, the PCB should be fabricated as documented in Section 5.3, “Stackup
Requirement” on page 5-1 of this document.
2
All recommendations in this section (except where noted) assume 5 mil wide traces. If trace width
is greater than 5 mils then the trace spacing requirements must be adjusted accordingly (linearly).
For example, this section recommends routing most AGP signals with 5 mil traces on 20 mil spaces
(1:4). If 6 mil traces are used, then 24 mil spaces must be used (also 1:4). Using a wider trace (and
therefore wider spaces) will make routing more difficult.
Additionally, these routing guidelines are created using the stack-up described in section
Section 5.3, “Stackup Requirement” on page 5-1. If this stack-up is not used, extremely thorough
simulations of every interface must be completed. Using a thicker dielectric (prepreg) will make
routing very difficult or impossible.
2.2 Component Quadrant Layout
The quadrant layouts shown are approximate and the exact ball assignments should be used to
conduct routing analysis. These quadrant layouts are designed for use during component
placement.
Intel®820 Chipset Design Guide 2-1
Layout/Routing Guidelines
Figure 2-1. MCH 324-uBGA Quadrant Layout (Top View)
System Bus
AGP 2.0
(324-uBGA)
Hub Interface
Direct RDRAM
Figure 2-2. ICH 241-uBGA Quadrant Layout (Top View)
Pin #1 Corner
241 uBGA
AC'97,
SMBus
MCH
PCI
ICH
System Bus
Processor
Hub Interface
LPC
IDE
2-2 Intel
®
820 Chipset Design Guide
Layout/Routing Guidelines
2.3 Intel® 820 Chipset Component Placement
Notes:
The ATX placements and layo uts shown in
1.
Figure 2-3 is
chipset based system design.
2. The trace length limitation between critical connections will be addressed later in this
document.
3.
The figure is for reference only.
Figure 2-3. Sample ATX MCH/ICH Component Placement
AGP
2.0
Hub Interface
ICH
RDRAM Termination
recommended for single (UP) Intel® 820
Processor Host Bus
MCH
Direct
RDRAM
Intel®820 Chipset Design Guide 2-3
Layout/Routing Guidelines
2.4 Core Chipset Routing Recommendations
Figure 2-4 and Figure 2-5 show MCH core routing examples.
Figure 2-4. Primary Side MCH Core Routing Example (ATX)
2-4 Intel
®
820 Chipset Design Guide
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