Asus David Lewis schematic
5
4
3
2
1
SYSTEM PAGE REF.
PAGE
1 Block Diagram
2 System Setting
3 CPU(1)_DMI,PEG,FDI,CLK,MISC
4
D D
C C
B B
A A
CPU(2)_DDR3
5
CPU(3)_CFG,RSVD,GND
6
CPU(4)_PWR
7
CPU(5)_XDP
16
DDR3 SO-DIMM_0
17
DDR3 SO-DIMM_1
18
DDR3 CA_DQ VOLTAGE
19 VID controller
20
PCH_IBEX(1)SATA,IHDA,RTC,LPC
21
PCH_IBEX(2)_PCIE,CLK,SMB,PEG
22
PCH_IBEX(3)_FDI,DMI,SYS PWR
23
PCH_IBEX(4)_DP,LVDS,CRT
24
PCH_IBEX(5)_PCI,NVRAM,USB
25
PCH_IBEX(6)CPU,GPIO,MISC
PCH_IBEX(7)_POWER,GND
26
27
PCH_IBEX(8)_POWER,GND
28
PCH_SPI ROM,OTH
29
CLK_ICS9LPR362
30
EC_IT8512(1/2)
31
EC_IT8512(2/2)KB, TP
32
RST_Reset Circuit
33
HANKSVILLE
34
LAN_RJ45
36
CODEC-ALC663
37
AUD_Amp & Jack
38
AUD_FM2010
40
CB_R5C833
41
CB_R5C833
42
CB_4in1 CardReader
CB_NewCard
43
BUG_Debug
44
45
CRT_LCD Panel
46
CRT_D-Sub
Display Port
47
48
TV_HDMI
50
FAN_Fan & Sensor
51
XDD_HDD & ODD
USB_USB Port *2
52
MINICARD(WLAN)
53
LED_Indicator
56
DSG_Discharge
57
DC_DC & BAT Conn.
60
BT_Bluetooth
61
TUN_TV Tuner
64
ME_Conn & Skew Hole
65
ESA_ESATA
66
PCH_XDP, ONFI
67
VGA_MXM
70
VGA_LVDS Switch
71
PW_VCORE(MAX17034)
80
PW_SYSTEM(MAX17020)
81
PW_I/O_VTT_CPU&+1.1VM
82
PW_I/O_DDR & VTT& +1.8VS83
PW_I/O_3VM & ME_+VM_PWEGD
84
PW_+VGFX_CORE(MAX17028)
86
PW_CHARGER(MAX17015)
88
PW_DETECT
90
PW_LOAD SWITCH
91
PW_PROTECT
92
PW_SIGNAL93
PW_FLOWCHART
94
Content
5
David Lewis schematic Rev 1.1
BLOCK DIAGRAM
HDMI
HDMI
Page 39
Page 37
4
Page 48
Page 46
Page 45
Page 31
Page 31
HDMIHDMI
nVIDIA N11P-GS1
LVDS
CRT
CRT
CRTCRT
LVDS
LVDSLVDS
Debug Conn.
EC
ITE IT8571
SPI ROM
Azalia Codec
Realtek ALC680
Azalia Codec
Realtek ALC275
TPA3110D2
Page 30
Page 28
Page 70
LVDS
LVDS
LVDSLVDS
CRT
CRT
CRTCRT
PCIE x16
PCIE x16
PCIE x16PCIE x16
Page 44
SPI
SPI
SPISPI
Page 35
Azalia
Azalia
AzaliaAzalia
Page 36
Azalia
Azalia
AzaliaAzalia
Page 36
Page 37
Clock Generator
ICS9LRS3197
PWM Fan
CPU
Arrandale / Clarksfield
DMI x4
DMI x4FDI x8
DMI x4DMI x4
PCH
LPC
LPC
LPCLPC
FDI x8
FDI x8FDI x8
HM55
SATA
SATA
SATASATA
Page 29
3
Discharge Circuit
Page 50
Page 3~6
Page 20~28
ODD
HDD(1)
HDD(2)
ESATA
Reset Circuit
DDR3 800/1066MHz
DDR3 800/1066MHz
DDR3 800/1066MHzDDR3 800/1066MHz
PCIE x1
PCIE x1
PCIE x1PCIE x1
USB
USB
USBUSB
Page 51
Page 51
Page 51
Page 49
Page 57
Page 32
2
HDMI
CRT
LCD Panel
Touchpad
Keyboard
INT. MIC
Page 45
Line In
Amp.
MiniCard
WLAN
Shirley Peak/ Echo Peak
NEC uPD720200
GigaLAN
MiniCard
TV Tuner
TP
Bluetooth
CMOS Camera
USB Port(1)
USB Port(2)
DC & BATT. Conn.
Skew Holes
Page 60
Page 65
DDR3 SO-DIMM
DDR3 SO-DIMM
DDR3 SO-DIMM
Page 16~18
Page 53
USB3.0
Page 54
Page 33
Page 64
Page 61
Page 55
Page 65
Page 49
ASUSTeK COMPUTER INC. NB4
ASUSTeK COMPUTER INC. NB4
ASUSTeK COMPUTER INC. NB4
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
USB3.0
RJ45
Power
VCORE
System
1.5VS & 1.05VS
DDR & VTT
+2.5VS
Charger
Detect
Load Switch
Power Protect
Page 54
Page 54
Page 34
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
David Lewis
David Lewis
David Lewis
1
Page 80
Page 81
Page 82
Page 83
Page 84
Page 86
Page 90
Page 91
Page 92
Block Diagram
Block Diagram
Block Diagram
Daniel Huang
Daniel Huang
Daniel Huang
1 99Wednesday, April 07, 2010
1 99Wednesday, April 07, 2010
1 99Wednesday, April 07, 2010
Rev
Rev
Rev
1.01
1.01
1.01
5
PCH_IBEX
GPIO
D D
C C
B B
A A
PCH_IBEX
GPIO
GPIO 00
GPIO 01
GPIO [2:5]
GPIO 06
GPIO 07
GPIO 08
GPIO 09
GPIO 10
GPIO 11
GPIO 12
GPIO 13
GPIO 14
GPIO 15
GPIO 16 +3VS
GPIO 17 +3VSGPI
GPIO 18 +3VS
GPIO 19 +3VS
GPIO 20
GPIO 21
GPIO 22
GPIO 23
GPIO 24 +3VSUS
GPIO 25
GPIO 26
GPIO 27
GPIO 28
GPIO 29
GPIO 30
GPIO 31
GPIO 32
GPIO 33
GPIO 34
GPIO 35
GPIO 36
GPIO 37
GPIO 38
GPIO 39 +3VS
GPIO 40
GPIO 41
GPIO 42
GPIO 43
GPIO 44
GPIO 45
GPIO 46
GPIO 47
GPIO 48
GPIO 49
GPIO 50
GPIO 51
GPIO 52
GPIO 53
GPIO 54
GPIO 55
GPIO 56
GPIO 57
GPIO 58
GPIO 59
GPIO 60
GPIO 61
GPIO 62
GPIO 63
GPIO 64
GPIO 65
GPIO 66
GPIO 67
GPIO 72
GPIO 73
GPIO 74
GPIO 75
5
GPI
GPI
GPI
GPI
GPI
GPI
Native
Native
GPI
Native
GPI
Native
GPO
GPI
Native
GPI
Native
GPI
GPO
Native
GPO
Native
Native
GPO
GPO
Native
GPO
Native
GPIO
GPI
GPI
GPO
GPO
GPO
GPI
GPI
Native
Native
Native
Native
Native
Native
Native
GPI CLKREQ_PEG#
GPI
Native
Native
Native
GPO
Native
Native
GPO
GPIO
Native
Native
Native
Native
Native
Native
Native
Native
Native
Native
Native
Native
GPIO
Signal NameUse As Power
NC_TP
NC_TP
-
HPD_INTR#
USB3_SMI#
EXT_SMI#
USB_OC5#
USB_OC6#
EXT_SCI#
NC_TP
NC_TP
USB_OC7#
BT_LED
DGPU_HOLD_RST#
DGPU_PWROK
CLKREQ1_TV#
SATA1GP
CLKREQ2#_WLAN
SATA0GP
WLAN_LED
NC_TP
NC_TP
CLK_REQ3#
CLKREQ4_USB#
NC_TP
WLAN_ON#
- ÂME_SusPwrDnAck
ME_AC_PRESENT
PM_CLKRUN#
HDA_DOCK_EN#
STP_PCI#
SATA_CLK_REQ#
dGPU_PWR_EN#_GPIO36
DGPU_PRSNT#
PCB_ID0
PCB_ID1
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
CLK_REQ5#
NC_TP
NC_TP
NC_TP
PCH_TEMP_ALERT#GPO
PCI_REQ1#
PCI_GNT1#
dGPU_SELECT#
DGPU_PWM_SELECT#_R
PCI_REQ3#
PCI_GNT3#Native
CLKREQ_GLAN#
BT_ON
SML1_CLK
USB_OC0#
SML0ALERT#
NC_TP
NC_TP
NC_TP
NC_TP
NC_TP
EDID_SELECT#
NC_TP
PM_BATLOW#
CLK_REQ0#
SMLALERT#
SML1_DATA
4
Internal &
External
Pull-up/down
EXT PU
EXT PU
EXT PU
EXT PU
EXT PU (Not used)
EXT PU & INT PU
EXT PU (Not used)
EXT PU (Not used)
EXT PU
-
INT PD
EXT PU (Not used)
EXT PD
EXT PU (Not used)
EXT PD & INT TBD
EXT PD
EXT PU
EXT PD
EXT PU
-
INT PU
-
EXT PU (Not used)
EXT PD
-
-
EXT PU
EXT PU
EXT PU
ÂEXT PU
EXT PD
EXT PU/PD
EXT PD
EXT PD
EXT PD
EXT PU (Not used)
EXT PU (Not used)
EXT PU (Not used)
EXT PU (Not used)
EXT PU
EXT PU (Not used)
EXT PU (Not used)
EXT PD
EXT PU (Not used)
EXT PU
EXT PU (Not used)
INT PU
EXT PU/PD
EXT PU/PD
EXT PU
INT PU
EXT PD
EXT PU(DIODE)
EXT PU
EXT PU (Not used)
EXT PU
-
-
-
INT TBD
INT TBD
INT TBD
INT TBD
EXT PU (Not used)
EXT PU (Not used)
EXT PU (Not used)
EXT PU
4
+3VS
+3VS
+3VS
+3VS
+3VS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VS
+3VS
+3VS
+3VS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VS
+3VS
+5VS
+3VS
+5VS
+3VS
+5VS
+3VS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VS
+3VS
+3VS
+3VS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
EC
IT8512
3
EC GPIO
Use As Signal Name
GPA0
GPA1
GPA2
GPA3
GPA4
GPA5
GPA6
GPA7
GPB0
GPB1
GPB2
GPB3
GPB4
GPB5
GPB6
GPB7
GPC0
GPC1
GPC2
GPC3
GPC4
GPC5
GPC6
GPC7
GPD0
GPD1
GPD2
GPD3
GPD4
GPD5
GPD6
GPD7
GPE0
GPE1
GPE2
GPE3
GPE4
GPE5
GPE6
GPE7
GPF0
GPF1
GPF2
GPF3
GPF4
GPF5
GPF6
GPF7
GPG0
GPG1
GPG2
GPG6 ÂGPH0
GPH1
GPH2
GPH3
GPH4
GPH5
GPH6 CAP_LED#
GPI0
GPI1
GPI2
GPI3
GPI4
GPI5
GPI6
GPI7
GPJ0
GPJ1
GPJ2
GPJ4
GPJ5 LVDS_GPU_SW
O
PWR_LED#
O
CHG_LED#
CHG_FULL_LED#
ÂLCD_BL_PWM
O
FAN0_PWM
O
KB_LED_PWM
-
BATSEL_0
O
BATSEL_1
O
-
IO
SMB0_CLK
IO
SMB0_DAT
O
A20GATE
O
RCIN#
PM_RSMRST#
O
-
IO
SMB1_CLK
IO
SMB1_DAT
O
PM_PWRBTN#
AC_IN_OC#
I
OP_SD#
O
BAT1_IN_OC#
I
RFON_SW#
I
PWRLIMIT#
I
PM_SUSC#
I
I
BUF_PLT_RST#
O
EXT_SCI#
O
EXT_SMI#
LCD_BACKOFF#
O
FAN0_TACH
I
ÂVSUS_ON
O
EGAD (IT8301 Address/Data connect)
O
EGCS (IT8301 Cycle Start connect)
O
EGCLK (IT8301 Clock connect)
O
PWR_SW#
I
ÂLID_SW#
I
ÂPCH_SPI_OV
O
ÂEXP_GATE#
I
ÂTP_CLK
I
TP_DAT
IO
THRO_CPU
O
-
ÂPM_SUSB#
I
-
IO
PM_CLKRUN#
O
GFX_VR_ON
CHG_EN
O
O
SUSC_EC#
O
SUSB_EC#
O
-
O
-
I
SUS_PWRGD
I
ALL_SYSTEM_PWRGD
I
VRM_PWRGD
I
GFX_VR
I
-
I
-
I
-
O
CPU_VRON
O
PM_PWROK
O
VSET_EC
O
ISET_ECGPJ3
O
-
O
3
2
PCIE 1
PCIE 2
Minicard WLAN
PCIE 3
PCIE 4
PCIE 5
PCIE 6
GLAN
PCIE 7
PCIE 8
SATA 0
SATA HDD (1)
SATA1
SATA ODD
SATA4
SATA5
SM_BUS ADDRESS :
PCH Master
SM-Bus Device
Clock Generator(ICS9LRS3197)
SO-DIMM 0 1010000x ( A0 )
SO-DIMM 1
VID Controller(ASM8272)
WiFi/WiMax
EC Master (SMB1)
SM-Bus Device
CPU Thermal Sensor(G781) 1001100x ( 98 )
Device Identification
CPU Thermal Sensor P/N:
06G023048011
1st
S
S
S
Clock Gen P/N:
1st
06G011604010
S
S
ASUSTeK COMPUTER INC. NB4
ASUSTeK COMPUTER INC. NB4
ASUSTeK COMPUTER INC. NB4
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
USB 0 USB Port (1)
USB 1
USB 2
USB 3
USB 4
USB 5
USB 6
USB 7
USB 8
USB 9
USB 10
USB 11
USB 12
USB 13
SM-Bus Address
1101001x ( D2 )
1010001x ( A2 )
0011011x ( 36 )
N/A
SM-Bus Address
component name
G781F
component name
ICS9LRS3197
Size Project Name
Size Project Name
Size Project Name
C
C
C
1
USB Port (3)
USB Port (4)
Card Reader(2.0)
WiFi/WiMax
Camera
Bluetooth
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
David Lewis
David Lewis
David Lewis
1
System Setting
System Setting
System Setting
Daniel Huang
Daniel Huang
Daniel Huang
2 99Wednesday, April 07, 2010
2 99Wednesday, April 07, 2010
2 99Wednesday, April 07, 2010
Rev
Rev
Rev
1.01
1.01
1.01
5
U0301A
U0301A
FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7
FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7
A24
C23
B22
A21
B24
D23
B23
A22
D24
G24
F23
H23
D25
F24
E23
G23
E22
D21
D19
D18
G21
E19
F21
G18
D22
C21
D20
C18
G22
E20
F20
G19
F17
E17
C17
F18
D17
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]
FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]
FDI_FSYNC[0]
FDI_FSYNC[1]
FDI_INT
FDI_LSYNC[0]
FDI_LSYNC[1]
SOCKET989
SOCKET989
DMI_TXN022
DMI_TXN122
DMI_TXN222
DMI_TXN322
DMI_TXP022
DMI_TXP122
DMI_TXP222
DMI_TXP322
DMI_RXN022
DMI_RXN122
DMI_RXN222
D D
C C
DMI_RXN322
DMI_RXP022
DMI_RXP122
DMI_RXP222
DMI_RXP322
FDI_TXN[7:0]22
FDI_TXP[7:0]22
FDI_FSYNC022
FDI_FSYNC122
FDI_INT22
FDI_LSYNC022
FDI_LSYNC122
For Intel GFX display
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
DMI Intel(R) FDI
DMI Intel(R) FDI
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PCI EXPRESS -- GRAPHICS
PCI EXPRESS -- GRAPHICS
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
B26
A26
B27
A25
K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31
J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30
L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26
L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25
PEG_IRCOMP_R
EXP_RBIAS
PCIENB_RXN0
PCIENB_RXN1
PCIENB_RXN2
PCIENB_RXN3
PCIENB_RXN4
PCIENB_RXN5
PCIENB_RXN6
PCIENB_RXN7
PCIENB_RXN8
PCIENB_RXN9
PCIENB_RXN10
PCIENB_RXN11
PCIENB_RXN12
PCIENB_RXN13
PCIENB_RXN14
PCIENB_RXN15
PCIENB_RXP0
PCIENB_RXP1
PCIENB_RXP2
PCIENB_RXP3
PCIENB_RXP4
PCIENB_RXP5
PCIENB_RXP6
PCIENB_RXP7
PCIENB_RXP8
PCIENB_RXP9
PCIENB_RXP10
PCIENB_RXP11
PCIENB_RXP12
PCIENB_RXP13
PCIENB_RXP14
PCIENB_RXP15
PCIENB_TXN0
PCIENB_TXN1
PCIENB_TXN2
PCIENB_TXN3
PCIENB_TXN4
PCIENB_TXN5
PCIENB_TXN6
PCIENB_TXN7
PCIENB_TXN8
PCIENB_TXN9
PCIENB_TXN10
PCIENB_TXN11
PCIENB_TXN12
PCIENB_TXN13
PCIENB_TXN14
PCIENB_TXN15
PCIENB_TXP0
PCIENB_TXP1
PCIENB_TXP2
PCIENB_TXP3
PCIENB_TXP4
PCIENB_TXP5
PCIENB_TXP6
PCIENB_TXP7
PCIENB_TXP8
PCIENB_TXP9
PCIENB_TXP10
PCIENB_TXP11
PCIENB_TXP12
PCIENB_TXP13
PCIENB_TXP14
PCIENB_TXP15
4
R0301 49.9Ohm1%R0301 49.9Ohm1%
1 2
R0302 750Ohm1%R0302 750Ohm1%
1 2
CX0301 0.1UF/16VCX0301 0.1UF/16V
1 2
CX0302 0.1UF/16VCX0302 0.1UF/16V
1 2
CX0303 0.1UF/16VCX0303 0.1UF/16V
1 2
CX0304 0.1UF/16VCX0304 0.1UF/16V
1 2
CX0305 0.1UF/16VCX0305 0.1UF/16V
1 2
CX0306 0.1UF/16VCX0306 0.1UF/16V
1 2
CX0307 0.1UF/16VCX0307 0.1UF/16V
1 2
CX0308 0.1UF/16VCX0308 0.1UF/16V
1 2
CX0309 0.1UF/16VCX0309 0.1UF/16V
1 2
CX0310 0.1UF/16VCX0310 0.1UF/16V
1 2
CX0311 0.1UF/16VCX0311 0.1UF/16V
1 2
CX0312 0.1UF/16VCX0312 0.1UF/16V
1 2
CX0313 0.1UF/16VCX0313 0.1UF/16V
1 2
CX0314 0.1UF/16VCX0314 0.1UF/16V
1 2
CX0315 0.1UF/16VCX0315 0.1UF/16V
1 2
CX0316 0.1UF/16VCX0316 0.1UF/16V
1 2
CX0317 0.1UF/16VCX0317 0.1UF/16V
1 2
CX0318 0.1UF/16VCX0318 0.1UF/16V
1 2
CX0319 0.1UF/16VCX0319 0.1UF/16V
1 2
CX0320 0.1UF/16VCX0320 0.1UF/16V
1 2
CX0321 0.1UF/16VCX0321 0.1UF/16V
1 2
CX0322 0.1UF/16VCX0322 0.1UF/16V
1 2
CX0323 0.1UF/16VCX0323 0.1UF/16V
1 2
CX0324 0.1UF/16VCX0324 0.1UF/16V
1 2
CX0325 0.1UF/16VCX0325 0.1UF/16V
1 2
CX0326 0.1UF/16VCX0326 0.1UF/16V
1 2
CX0327 0.1UF/16VCX0327 0.1UF/16V
1 2
CX0328 0.1UF/16VCX0328 0.1UF/16V
1 2
CX0329 0.1UF/16VCX0329 0.1UF/16V
1 2
CX0330 0.1UF/16VCX0330 0.1UF/16V
1 2
CX0331 0.1UF/16VCX0331 0.1UF/16V
1 2
CX0332 0.1UF/16VCX0332 0.1UF/16V
1 2
PCIENB_RXN[15:0] 70
R0370,R0371,R0372 near U0301
PCIENB_RXP[15:0] 70
For EC request, to read PECI via EC.
Connection: R0317.2-->Q0301.1-->U3001.118
R0310 don't remove
PCIEG_RXN0
PCIEG_RXN1
PCIEG_RXN2
PCIEG_RXN3
PCIEG_RXN4
PCIEG_RXN5
PCIEG_RXN6
PCIEG_RXN7
PCIEG_RXN8
PCIEG_RXN9
PCIEG_RXN10
PCIEG_RXN11
PCIEG_RXN12
PCIEG_RXN13
PCIEG_RXN14
PCIEG_RXN15
PCIEG_RXP0
PCIEG_RXP1
PCIEG_RXP2
PCIEG_RXP3
PCIEG_RXP4
PCIEG_RXP5
PCIEG_RXP6
PCIEG_RXP7
PCIEG_RXP8
PCIEG_RXP9
PCIEG_RXP10
PCIEG_RXP11
PCIEG_RXP12
PCIEG_RXP13
PCIEG_RXP14
PCIEG_RXP15
PCIEG_RXN[15:0] 70
PCIEG_RXP[15:0] 70
+VTT_CPU
+VTT_CPU
H_THRMTRIP#25,32
H_CPUPWRGD7,25
H_DRAM_PWRGD22
H_VTTPWRGD58
H_PWRGD_XDP7
BUF_PLT_RST#7,24,30,32,33,45,53,54,64,70
3
+VTT_CPU
H_PECI25
H_PROCHOT_S#
R0340
R0340
56OHM
56OHM
H_CPURST#7
PM_SYNC#22
H_CATERR#
THRO_CPU
0Ohm
0Ohm
R0317
@R0317
@
0Ohm
0Ohm
R0308
R0308
R0322 68OHMR0322 68OHM
0Ohm
0Ohm
R0310
R0310
0Ohm
0Ohm
R0311
R0311
12
T0302T0302
0Ohm
0Ohm
R0314
R0314
0Ohm
0Ohm
R0309
R0309
0Ohm
0Ohm
R0315
R0315
0Ohm
0Ohm
R0316
R0316
R0318
R0318
1 2
1.5KOhm 1%
1.5KOhm 1%
R1.0
R030320Ohm 1% R030320Ohm 1%
12
R030420Ohm 1% R030420Ohm 1%
12
R030549.9Ohm 1% R030549.9Ohm 1%
12
R030649.9Ohm 1% R030649.9Ohm 1%
12
T0301T0301
12
12
12
H_PROCHOT_S#_R
12
12
1
12
VCCPWRGOOD_1_R
12
VCCPWRGOOD_0_R
12
VDDPWRGOOD_R
12
PLT_RST#_R
H_COMP3
H_COMP2
H_COMP1
H_COMP0
TP_SKTOCC#
1
R030749.9Ohm 1% R030749.9Ohm 1%
12
H_PECI_ISO
H_THRMTRIP#_R
H_CPURST#
PM_SYNC#_R
12
R0319
R0319
750Ohm
750Ohm
1%
1%
2
SKTOCC#:pulled to ground on processor.
may use to determine if CPU is present
U0301B
U0301B
AT23
AT24
AT26
AH24
AK14
AT15
AN26
AK15
AP26
AL15
AN14
AN27
AK13
AM15
AM26
AL14
G16
COMP3
COMP2
COMP1
COMP0
SKTOCC#
CATERR#
PECI
PROCHOT#
THERMTRIP#
RESET_OBS#
PM_SYNC
VCCPWRGOOD_1
VCCPWRGOOD_0
SM_DRAMPWROK
VTTPWRGOOD
TAPPWRGOOD
RSTIN#
SOCKET989
SOCKET989
MISC THERMAL
MISC THERMAL
DDR3
DDR3
PWR MANAGEMENT
PWR MANAGEMENT
CLOCKS
CLOCKS
MISC
MISC
JTAG & BPM
JTAG & BPM
BCLK
BCLK#
BCLK_ITP
BCLK_ITP#
PEG_CLK
PEG_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
PM_EXT_TS#[0]
PM_EXT_TS#[1]
PRDY#
PREQ#
TRST#
TDI_M
TDO_M
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
R1.1,item L11
CLKDREF
CLKDREF#
A16
B16
AR30
AT30
E16
D16
A18
A17
F6
AL1
AM1
AN1
AN15
AP15
+VTT_CPU
AT28
AP27
AN28
TCK
AP28
TMS
AT27
AT29
TDI
AR27
TDO
AR29
AP29
AN25
AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23
R0366 1KOhm
R0366 1KOhm
R0367 1KOhm
R0367 1KOhm
Place near R0328,R0329.
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_ITP_BCLK_R
CLK_ITP_BCLK#_R
CLK_EXP_P
CLK_EXP_N
CLKDREF
CLKDREF#
SM_RCOMP0
R0331 100Ohm1%R0331 100Ohm1%
SM_RCOMP1
R0332 24.9Ohm1%R0332 24.9Ohm1%
SM_RCOMP2
R0333 130OHM1%R0333 130OHM1%
PM_EXTTS#1
RN0301A
RN0301A
10KOHM
10KOHM
RN0301B
RN0301B
10KOHM
10KOHM
XDP_PREQ#
XDP_TCLK
XDP_TMS
XDP_TRST#
XDP_TDI_R
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M
H_DBR#_R
R0336 0OhmR0336 0Ohm
XDP_OBS0_R
RX0337 0OhmRX0337 0Ohm
XDP_OBS1_R
RX0338 0OhmRX0338 0Ohm
XDP_OBS2_R
RX0339 0OhmRX0339 0Ohm
XDP_OBS3_R
RX0340 0OhmRX0340 0Ohm
XDP_OBS4_R
RX0341 0OhmRX0341 0Ohm
XDP_OBS5_R
RX0342 0OhmRX0342 0Ohm
XDP_OBS6_R
RX0343 0OhmRX0343 0Ohm
XDP_OBS7_R
RX0344 0OhmRX0344 0Ohm
@
@
@
@
1 2
1 2
1 2
12
34
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
12
CLK selection
SL0317
SL0317
21
0402
0402
SL0318
SL0318
21
0402
0402
1
Main Board
CLK_ITP_BCLK 7
CLK_ITP_BCLK# 7
CLK_DREF 21
CLK_DREF# 21
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7
120MHz from PCH.
PM_EXTTS#0 14,15,16
Check here
XDP_DBRESET# 7,22
M_DRAMRST# 14,15,16
XDP_PRDY# 7
XDP_PREQ# 7
XDP_TCLK 7
XDP_TMS 7
XDP_TRST# 7
XDP_OBS[7:0] 7
12G011909890
R03911KOhm@R03911KOhm
3
JTAG MAPPING
XDP_TDI_R
XDP_TDO_M
12
XDP_TDI_M
XDP_TDO_R
BUF_PLT_RST#H_CPURST#
0402
0402
R0351 0Ohm
R0351 0Ohm
1 2
@
@
R0353
R0353
0Ohm
0Ohm
R0352 0Ohm@R0352 0Ohm@
1 2
0402
0402
SL0308
SL0308
21
XDP_TDI 7
XDP_TDO 7
DRAMPWROK: (DGU R1.52)
+1.5V
SL0309
SL0309
21
VDDPWRGOOD_R
2
R0320
R0320
1.1KOhm
1.1KOhm
1%
1%
1 2
12
R0321
R0321
3.01KOHM
3.01KOHM
1%
1%
CPU(1)_DMI,PEG,FDI,CLK,MISC
CPU(1)_DMI,PEG,FDI,CLK,MISC
CPU(1)_DMI,PEG,FDI,CLK,MISC
Title :
Title :
Title :
Daniel Huang
Daniel Huang
Daniel Huang
Engineer:
Engineer:
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Engineer:
David Lewis
David Lewis
David Lewis
1
3 99Thursday, April 15, 2010
3 99Thursday, April 15, 2010
3 99Thursday, April 15, 2010
Rev
Rev
Rev
1.01
1.01
1.01
Q0301
Q0301
H2N7002
H2N7002
1
1
1
+VTT_CPU
12
1 2
@
THRO_CPU 30
R1.1,item L8
R03230Ohm R03230Ohm
BCLK_CPU_P_PCH25
B B
BCLK_CPU_N_PCH25
CLK_DMI_PCH21
CLK_DMI#_PCH21
12
R03550Ohm R03550Ohm
12
R03590Ohm R03590Ohm
12
R03560Ohm R03560Ohm
12
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_EXP_P
CLK_EXP_N
FDI disable: (For discrete graphic)
1. NC:
FDI_TX#[0:7],FDI_TX[0:7],FDI_RX#[0:7],FDI_RX[0:7]
VCC_AXGSENSE,VSS_AXGSENSE
2. Pull-down to GND via 1KΩ ± 5% resistor:
FDI_FSYNC[0:1],FDI_LSYNC[0:1],FDI_INT,GFX_IMON
~15mW power saving.(DG R0.8 P.70)
3. Connected to GND:
VCCAXG,
4. Can be connected to GND directly:
DPLL_REF_CLK,DPLL_REF_CLK#
5. Connect to +V1.05S rail:
VCCFDIPLL
A A
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
FDI_INT
AUB Item1
1 2
1 2
1 2
1 2
1 2
R03641KOhm CFD R03641KOhm CFD
R03611KOhm CFD R03611KOhm CFD
R03651KOhm CFD R03651KOhm CFD
R03621KOhm CFD R03621KOhm CFD
R03631KOhm CFD R03631KOhm CFD
5
H_PROCHOT_S#80,85
PWRLIMIT#30,88
4
H_CPURST#
XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TDO_R
XDP_TCLK
XDP_TRST#
H_PROCHOT_S#
@
@
12
D0301 RB751V-40
D0301 RB751V-40
R1.1,item L10.
R0313 68OHM@R0313 68OHM@
R0345 51Ohm@R0345 51Ohm@
1 2
R0346 51Ohm@R0346 51Ohm@
1 2
R0347 51Ohm@R0347 51Ohm@
1 2
R0348 51OhmR0348 51Ohm
1 2
R0349 51Ohm@R0349 51Ohm@
1 2
R0350 51OhmR0350 51Ohm
1 2
32
3
3
D
D
G
G
S
S
2
2
5
4
3
2
1
Main Board
U0301C
U0301C
U0301D
U0301D
AA6
SA_CK[0]
M_A_DQ[63:0]15
D D
C C
B B
M_A_DQ0
A10
AM10
AR11
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AR14
AP14
AJ10
AL10
AK12
AK11
AL11
AL13
SA_DQ[0]
C10
SA_DQ[1]
C7
SA_DQ[2]
A7
SA_DQ[3]
B10
SA_DQ[4]
D10
SA_DQ[5]
E10
SA_DQ[6]
A8
SA_DQ[7]
D8
SA_DQ[8]
F10
SA_DQ[9]
E6
SA_DQ[10]
F7
SA_DQ[11]
E9
SA_DQ[12]
B7
SA_DQ[13]
E7
SA_DQ[14]
C6
SA_DQ[15]
H10
SA_DQ[16]
G8
SA_DQ[17]
K7
SA_DQ[18]
J8
SA_DQ[19]
G7
SA_DQ[20]
G10
SA_DQ[21]
J7
SA_DQ[22]
J10
SA_DQ[23]
L7
SA_DQ[24]
M6
SA_DQ[25]
M8
SA_DQ[26]
L9
SA_DQ[27]
L6
SA_DQ[28]
K8
SA_DQ[29]
N8
SA_DQ[30]
P9
SA_DQ[31]
AH5
SA_DQ[32]
AF5
SA_DQ[33]
AK6
SA_DQ[34]
AK7
SA_DQ[35]
AF6
SA_DQ[36]
AG5
SA_DQ[37]
AJ7
SA_DQ[38]
AJ6
SA_DQ[39]
SA_DQ[40]
AJ9
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
AK8
SA_DQ[44]
AL7
SA_DQ[45]
SA_DQ[46]
AL8
SA_DQ[47]
AN8
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
AM9
SA_DQ[52]
AN9
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
AC3
SA_BS[0]
AB2
SA_BS[1]
U7
SA_BS[2]
AE1
SA_CAS#
AB3
SA_RAS#
AE9
SA_WE#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_BS015
M_A_BS115
M_A_BS215
M_A_CAS#15
M_A_RAS#15
M_A_WE#15
SA_CK#[0]
SA_CKE[0]
SA_CK[1]
SA_CK#[1]
SA_CKE[1]
SA_CS#[0]
SA_CS#[1]
SA_ODT[0]
SA_ODT[1]
SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AA7
P7
Y6
Y5
P6
AE2
AE8
AD8
AF9
B9
D7
H7
M7
AG6
AM7
AN10
AN13
C9
F8
J9
N9
AH7
AK9
AP11
AT13
C8
F9
H9
M9
AH8
AK10
AN11
AR13
Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_CLK_DDR0 15
M_CLK_DDR#0 15
M_CKE0 15
M_CLK_DDR1 15
M_CLK_DDR#1 15
M_CKE1 15
M_CS#0 15
M_CS#1 15
M_ODT0 15
M_ODT1 15
M_A_DM[7:0] 15
M_A_DQS#[7:0] 15
M_A_DQS[7:0] 15
M_A_A[15:0] 15
M_B_DQ[63:0]14,16
M_B_DQ0
B5
AR10
AT10
SB_DQ[0]
A5
SB_DQ[1]
C3
SB_DQ[2]
B3
SB_DQ[3]
E4
SB_DQ[4]
A6
SB_DQ[5]
A4
SB_DQ[6]
C4
SB_DQ[7]
D1
SB_DQ[8]
D2
SB_DQ[9]
F2
SB_DQ[10]
F1
SB_DQ[11]
C2
SB_DQ[12]
F5
SB_DQ[13]
F3
SB_DQ[14]
G4
SB_DQ[15]
H6
SB_DQ[16]
G2
SB_DQ[17]
J6
SB_DQ[18]
J3
SB_DQ[19]
G1
SB_DQ[20]
G5
SB_DQ[21]
J2
SB_DQ[22]
J1
SB_DQ[23]
J5
SB_DQ[24]
K2
SB_DQ[25]
L3
SB_DQ[26]
M1
SB_DQ[27]
K5
SB_DQ[28]
K4
SB_DQ[29]
M4
SB_DQ[30]
N5
SB_DQ[31]
AF3
SB_DQ[32]
AG1
SB_DQ[33]
AJ3
SB_DQ[34]
AK1
SB_DQ[35]
AG4
SB_DQ[36]
AG3
SB_DQ[37]
AJ4
SB_DQ[38]
AH4
SB_DQ[39]
AK3
SB_DQ[40]
AK4
SB_DQ[41]
AM6
SB_DQ[42]
AN2
SB_DQ[43]
AK5
SB_DQ[44]
AK2
SB_DQ[45]
AM4
SB_DQ[46]
AM3
SB_DQ[47]
AP3
SB_DQ[48]
AN5
SB_DQ[49]
AT4
SB_DQ[50]
AN6
SB_DQ[51]
AN4
SB_DQ[52]
AN3
SB_DQ[53]
AT5
SB_DQ[54]
AT6
SB_DQ[55]
AN7
SB_DQ[56]
AP6
SB_DQ[57]
AP8
SB_DQ[58]
AT9
SB_DQ[59]
AT7
SB_DQ[60]
AP9
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
AB1
SB_BS[0]
W5
SB_BS[1]
R7
SB_BS[2]
AC5
SB_CAS#
Y7
SB_RAS#
AC6
SB_WE#
DDR SYSTEM MEMORY - B
DDR SYSTEM MEMORY - B
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_BS014,16
M_B_BS114,16
M_B_BS214,16
M_B_CAS#14,16
M_B_RAS#14,16
M_B_WE#14,16
SB_CK[0]
SB_CK#[0]
SB_CKE[0]
SB_CK[1]
SB_CK#[1]
SB_CKE[1]
SB_CS#[0]
SB_CS#[1]
SB_ODT[0]
SB_ODT[1]
SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
W8
W9
M3
V7
V6
M2
AB8
AD6
AC7
AD1
M_B_DM0
D4
M_B_DM1
E1
M_B_DM2
H3
M_B_DM3
K1
M_B_DM4
AH1
M_B_DM5
AL2
M_B_DM6
AR4
M_B_DM7
AT8
M_B_DQS#0
D5
M_B_DQS#1
F4
M_B_DQS#2
J4
M_B_DQS#3
L4
M_B_DQS#4
AH2
M_B_DQS#5
AL4
M_B_DQS#6
AR5
M_B_DQS#7
AR8
M_B_DQS0
C5
M_B_DQS1
E3
M_B_DQS2
H4
M_B_DQS3
M5
M_B_DQS4
AG2
M_B_DQS5
AL5
M_B_DQS6
AP5
M_B_DQS7
AR7
M_B_A0
U5
M_B_A1
V2
M_B_A2
T5
M_B_A3
V3
M_B_A4
R1
M_B_A5
T8
M_B_A6
R2
M_B_A7
R6
M_B_A8
R4
M_B_A9
R5
M_B_A10
AB5
M_B_A11
P3
M_B_A12
R3
M_B_A13
AF7
M_B_A14
P5
M_B_A15
N1
M_CLK_DDR2 16
M_CLK_DDR#2 16
M_CKE2 16
M_CLK_DDR3 16
M_CLK_DDR#3 16
M_CKE3 16
M_CS#2 16
M_CS#3 16
M_ODT2 16
M_ODT3 16
M_B_DM[7:0] 14,16
M_B_DQS#[7:0] 14,16
M_B_DQS[7:0] 14,16
M_B_A[15:0] 14,16
SOCKET989
SOCKET989
SOCKET989
SOCKET989
A A
CPU(2)_DDR3
CPU(2)_DDR3
CPU(2)_DDR3
Title :
Title :
Title :
Daniel Huang
Daniel Huang
Daniel Huang
Engineer:
Engineer:
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
David Lewis
David Lewis
David Lewis
1
Rev
Rev
Rev
1.01
1.01
1.01
4 99Thursday, April 15, 2010
4 99Thursday, April 15, 2010
4 99Thursday, April 15, 2010
5
4
3
2
1
Main Board
D D
DIMM0_VREF_DQ18
DIMM1_VREF_DQ18
T0578T0578
T0567T0567
T0566T0566
T0565T0565
T0569T0569
T0568T0568
T0571T0571
T0572T0572
T0574T0574
T0570T0570
C C
B B
T0575T0575
T0573T0573
T0576T0576
T0577T0577
T0592T0592
T0581T0581
T0580T0580
T0579T0579
T0583T0583
10mil trace
10mil trace
CFG0
1
CFG1
1
CFG2
1
CFG3
1
CFG4
1
CFG5
1
CFG6
1
CFG7
1
CFG8
1
CFG9
1
CFG10
1
CFG11
1
CFG12
1
CFG13
1
CFG14
1
CFG15
1
CFG16
1
CFG17
1
CFG18
1
H_RSVD17_R
R05010Ohm R05010Ohm
12
H_RSVD18_R
R05020Ohm R05020Ohm
12
T0513T0513
1
T0510T0510
1
T0511T0511
1
T0512T0512
1
T0514T0514
1
T0515T0515
1
AP25
AL25
AL24
AL22
AJ33
AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30
AG9
M27
L28
J17
H17
G25
G17
E31
E30
H16
B19
A19
A20
B20
AC9
AB9
J29
J28
A34
A33
C35
B35
U9
T9
C1
A3
U0301E
U0301E
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
SOCKET989
SOCKET989
AJ13
RSVD32
AJ12
RSVD33
AH25
RSVD34
AK26
RSVD35
AL26
RSVD36
AR2
RSVD37
AJ26
RSVD38
AJ27
RSVD39
AP1
RSVD40
AT2
RSVD41
AT3
RSVD42
AR1
RSVD43
AL28
RSVD45
AL29
RSVD46
AP30
RSVD47
AP32
RSVD48
AL27
RSVD49
AT31
RSVD50
AT32
RSVD51
AP33
RSVD52
AR33
RSVD53
AT33
RSVD54
AT34
RSVD55
AP35
RSVD56
AR35
RSVD57
AR32
RSVD58
E15
RSVD59
F15
RSVD60
RSVD61
RSVD62
RSVD63
RSVD64
RSVD65
RSVD66
RSVD67
RSVD68
RSVD69
RSVD70
RSVD71
RSVD72
RSVD73
RSVD74
RSVD75
RSVD76
RSVD77
RSVD78
RSVD79
RSVD80
RSVD81
RSVD82
RSVD83
RSVD84
RSVD85
RSVD86
A2
D15
C15
AJ15
AH15
AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3
V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9
AP34
RESERVED
RESERVED
RSVD64_R
RSVD65_R
SB_CK[2]
SB_CK#[2]
SB_CKE[2]
SB_CS#[2]
SB_ODT[2]
SB_CK[3]
SB_CK#[3]
SB_CKE[3]
SB_CS#[3]
SB_ODT[3]
1
1
1
1
1
1
1
1
1
T0504T0504
T0501T0501
T0506T0506
T0507T0507
T0503T0503
T0508T0508
T0509T0509
T0502T0502
T0505T0505
R0505 0OhmR0505 0Ohm
1 2
R0506 0OhmR0506 0Ohm
1 2
M_CLK_DDR4 14
M_CLK_DDR#4 14
M_CKE4 14
M_CS#4 14
M_ODT4 14
M_CLK_DDR5 14
M_CLK_DDR#5 14
M_CKE5 14
M_CS#5 14
M_ODT5 14
AT20
AT17
AR31
AR28
AR26
AR24
AR23
AR20
AR17
AR15
AR12
AP20
AP17
AP13
AP10
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11
AL34
AL31
AL23
AL20
AL17
AL12
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13
AG10
AE35
AR9
AR6
AR3
AP7
AP4
AP2
AM8
AM5
AM2
AL9
AL6
AL3
AJ8
AJ5
AJ2
AH9
AH6
AH3
AF8
AF4
AF2
U0301H
U0301H
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
SOCKET989
SOCKET989
VSS
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30
K27
K9
K6
K3
J32
J30
J21
J19
H35
H32
H28
H26
H24
H22
H18
H15
H13
H11
H8
H5
H2
G34
G31
G20
G9
G6
G3
F30
F27
F25
F22
F19
F16
E35
E32
E29
E24
E21
E18
E13
E11
E8
E5
E2
D33
D30
D26
D9
D6
D3
C34
C32
C29
C28
C24
C22
C20
C19
C16
B31
B25
B21
B18
B17
B13
B11
B8
B6
B4
A29
A27
A23
A9
U0301I
U0301I
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
SOCKET989
SOCKET989
VSS
VSS
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
NCTF
NCTF
TP_MCP_VSS_NCTF2
AT1
AR34
B34
B2
TP_MCP_VSS_NCTF6
B1
TP_MCP_VSS_NCTF7
A35
TP_MCP_VSS_NCTF1
AT35
T0564T0564
1
T0561T0561
1
T0563T0563
1
T0562T0562
1
CFG strapping information:
CFG[1:0]: PCI Express Port Bifurcation:(Clarksfield Only)
- 11 = 1 x 16 PEG (Default)
- 10 = 2 x 8 PEG
CFG[3]: PCIE Static Numbering Lane Reversal.(Auburndale Only)
- 1:Normal Operation (Default)
- 0:Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
CFG[4]: Embedded DisplayPort Detection.(Auburndale Only)
- 1:Disabled - No Physical Display Port attached to Embedded DisplayPort
- 0:Enabled - An external Display Port device is connected to the Embedded Display Port
CFG[7]: Fixed for PCI Express 2.0 jitter specifications.(Clarksfi eld)
Clarksfield (only for early samples pre-ES1) - Connect to GND with 3.01K Ohm /5% resistor
For a common motherboard design (for AUB and CFD),
the pull-down resistor should be used. Does not impact AUB functionality.
Unmount if Intel has fixed this issue.
A A
Note: (Auburndale)Hardware Straps are sampled on
the asserting edge of VCCPWRGOOD_0 and
VCCPWRGOOD_1 and latched inside the processor.
Note: (Clarksfield)Hardware Straps are sampled
after RSTIN# de-assertion.
5
CFG0
CFG3
CFG4
CFG7
4
@
@
R0535 3.01KOHM
R0535 3.01KOHM
R0536 3.01KOHM
R0536 3.01KOHM
R0537 3.01KOHM
R0537 3.01KOHM
R0538 3.01KOHM
12
1%
1%
@
@
12
1%
1%
@
@
12
1%
1%
@R0538 3.01KOHM
@
12
1%
1%
R1.1,item B1
CPU(3)_CFG,RSVD,GND
CPU(3)_CFG,RSVD,GND
CPU(3)_CFG,RSVD,GND
Title :
Title :
Title :
Daniel Huang
Daniel Huang
Daniel Huang
Engineer:
Engineer:
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Engineer:
David Lewis
David Lewis
David Lewis
1
Rev
Rev
Rev
1.1
1.1
1.1
5 93Thursday, April 15, 2010
5 93Thursday, April 15, 2010
5 93Thursday, April 15, 2010
5
U0301F
U0301F
+VCORE
AG35
VCC1
AG34
VCC2
AG33
VCC3
AG32
VCC4
AG31
VCC5
D D
C C
B B
A A
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
SOCKET989
SOCKET989
1.1V RAIL POWER
1.1V RAIL POWER
CPU CORE SUPPLY
CPU CORE SUPPLY
POWER
POWER
PROC_DPRSLPVR
CPU VIDS
CPU VIDS
VSS_SENSE_VTT
SENSE LINES
SENSE LINES
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VTT_SELECT
ISENSE
VCC_SENSE
VSS_SENSE
VTT_SENSE
PSI#
AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15
R0616 0OhmR0616 0Ohm
AN33
AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34
G15
VR_VID0
VR_VID1
VR_VID2
VR_VID3
VR_VID4
VR_VID5
VR_VID6
PM_DPRSLPVR_R
H_VTTVID1 82
1 2
VTT_TEST TBD
AN35
AJ34
AJ35
B15
A15
I_MON 80
VCCSENSE_R
VSSSENSE_R
VTT_SENSE
TP_VSS_SENSE_VTT
12
12
C060110UF/6.3V C060110UF/6.3V
+VTT_CPU
12
12
C068710UF/6.3V C068710UF/6.3V
C061722UF/6.3V C061722UF/6.3V
R0601 0OhmR0601 0Ohm
1
1
12
12
C060610UF/6.3V C060610UF/6.3V
C060210UF/6.3V C060210UF/6.3V
C060410UF/6.3V C060410UF/6.3V
12
C068910UF/6.3V C068910UF/6.3V
C068810UF/6.3V C068810UF/6.3V
C61822UF/ 6.3V C61822UF/6.3V
12
12
VR_VID[0:6] 80
1 2
+VCORE
T0632T0632
T0631T0631
4
C61410UF/6.3V@C61410UF/6.3V
12
12
12
12
12
C061310UF/6.3V C061310UF/6.3V
C060810UF/6.3V C060810UF/6.3V
C061110UF/6.3V C061110UF/6.3V
@
V1.1S_VTT (Arrandale)
V1.05S_VTT (Clarksfield)
7PCS 22UF 0805
8PCS 10UF 0805
+VTT_CPU
PM_PSI# 80
PM_DPRSLPVR 80
R0602
R0602
100Ohm
100Ohm
1%
1%
1 2
VCCSENSE 80
VSSSENSE 80
12
R0603
R0603
100Ohm
100Ohm
1%
1%
+VTT_CPU+VTT_CPUCC
C61510UF/6.3V@C61510UF/6.3V
@
DANIEL 0720
R0620
R0620
R0621
R0621
DANIEL 0720
3
+VGFX_CORE
12
12
12
R06070Ohm
R06070Ohm
C065122UF/6.3V
C065122UF/6.3V
C065022UF/6.3V
C065022UF/6.3V
CFD
CFD
ARD
ARD
ARD
ARD
CE605330UF/2V
CE605330UF/2V
CE606330UF/2V
CE606330UF/2V
CE607330UF/2V
12
ESR=6mOhm/Ir=3A
ESR=6mOhm/Ir=3A
PANASONIC/EEFSX0D331XE
PANASONIC/EEFSX0D331XE
CE607330UF/2V
12
+
+
+
+
@
@
ESR=6mOhm/Ir=3A
ESR=6mOhm/Ir=3A
PANASONIC/EEFSX0D331XE
PANASONIC/EEFSX0D331XE
VCCAXG
2PCS 22UF 0805
2PCS 10UF 0603
ESR=6mOhm/Ir=3A
ESR=6mOhm/Ir=3A
DANIEL 0720
PANASONIC/EEFSX0D331XE
PANASONIC/EEFSX0D331XE
12
+
+
C62010UF/6.3V c0603
C62010UF/6.3V c0603
12
12
C061910UF/6.3V c0603
C061910UF/6.3V c0603
C064922UF/6.3V
C064922UF/6.3V
C064822UF/6.3V
C064822UF/6.3V
ARD
ARD
ARD
ARD
ARD
ARD
ARD
ARD
1 2
1 2
DANIEL 0720
+VTT_CPU
12
12
C065422UF/6.3V C 065422UF/6.3V
C065522UF/6.3V C 065522UF/6.3V
+VTT_CPU
0Ohmr0603_h24
0Ohmr0603_h24
+VTT_CPU
0Ohmr0603_h24
0Ohmr0603_h24
12
12
12
12
12
C065722UF/6.3V C 065722UF/6.3V
C065822UF/6.3V C 065822UF/6.3V12C065622UF/6.3V C 065622UF/6.3V
C065922UF/6.3V C 065922UF/6.3V
AT21
AT19
AT18
AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16
AK21
AK19
AK18
AK16
AH21
AH19
AH18
AH16
AL21
AL19
AL18
AL16
AJ21
AJ19
AJ18
AJ16
J24
J23
H25
K26
J27
J26
J25
H27
G28
G27
G26
F26
E26
E25
U0301G
U0301G
VCCAXG1
VCCAXG2
VCCAXG3
VCCAXG4
VCCAXG5
VCCAXG6
VCCAXG7
VCCAXG8
VCCAXG9
VCCAXG10
VCCAXG11
VCCAXG12
VCCAXG13
VCCAXG14
VCCAXG15
VCCAXG16
VCCAXG17
VCCAXG18
VCCAXG19
VCCAXG20
VCCAXG21
VCCAXG22
VCCAXG23
VCCAXG24
VCCAXG25
VCCAXG26
VCCAXG27
VCCAXG28
VCCAXG29
VCCAXG30
VCCAXG31
VCCAXG32
VCCAXG33
VCCAXG34
VCCAXG35
VCCAXG36
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51
VTT52
VTT53
VTT54
VTT55
VTT56
VTT57
VTT58
SOCKET989
SOCKET989
SENSE
LINES
SENSE
LINES
GRAPHICS
GRAPHICS
GRAPHICS VIDs
GRAPHICS VIDs
FDI PEG & DMI
FDI PEG & DMI
POWER
POWER
VCCAXG_SENSE
VSSAXG_SENSE
GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]
GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
DDR3 - 1.5V RAILS
DDR3 - 1.5V RAILS
VTT59
VTT60
VTT61
VTT62
VTT63
VTT64
VTT65
1.1V1.8V
1.1V1.8V
VTT66
VTT67
VTT68
VCCPLL1
VCCPLL2
VCCPLL3
2
AR22
AT22
AM22
AP22
AN22
AP23
AM23
AP24
AN24
AR25
AT25
AM24
AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1
P10
N10
L10
K10
J22
J20
J18
H21
H20
H19
L26
L27
M26
GVR_VID0
GVR_VID1
GVR_VID2
GVR_VID3
GVR_VID4
GVR_VID5
GVR_VID6
GFX_VRON_EN
GFXVR_DPRSLPVR_R
VCC_AXG_SENSE 86
VSS_AXG_SENSE 86
GVR_PWR_MON
GVR_VID[0:6] 86
R0605@: R8621 does not have 4.7K pull-down.
R0605 4.7KOhm
R0605 4.7KOhm
1 2
R0612 0Ohm
R0612 0Ohm
1 2
R0617 0Ohm@R0617 0Ohm@
1 2
R0604 0OhmR0604 0Ohm
1 2
GVR_PWR_MON 86
12
12
12
C06211UF/ 10V C06211UF/10V
C06221UF/ 10V C06221UF/10V
C06231UF/ 10V C06231UF/10V
12
12
C0626
C0626
C0627
C0627
10UF/6.3V
10UF/6.3V
10UF/6.3V
10UF/6.3V
12
12
C066522UF/6.3V C066522UF/6.3V
12
12
12
C06281UF/ 10V C06281UF/10V
C06672.2UF/10V C06672.2UF/10V
C06291UF/ 10V C06291UF/10V
CFD
CFD
ARD
ARD
12
12
C06241UF/ 10V C06241UF/10V
C066422UF/6.3V C066422UF/6.3V
12
12
C06684.7UF/6.3V C06684.7UF/6.3V
R0613 1KOhm
R0613 1KOhm
12
C06251UF/ 10V C06251UF/10V
C068522UF/6.3V C 068522UF/6.3V
C066622UF/6.3V C 066622UF/6.3V
1 2
CFD
CFD
GFX_VR_ON 30,86
GFX_VR 30
R0606
R0606
1 2
10KOhm
10KOhm
12+CE0604330UF/2V
+
12
C068622UF/6.3V C 068622UF/6.3V
CE0604330UF/2V
ESR=6mOhm/Ir=3A
ESR=6mOhm/Ir=3A
PANASONIC/EEFSX0D331XE
PANASONIC/EEFSX0D331XE
+VTT_CPU
+VTT_CPU
+1.8VS
VCCPLL
1PCS 2.2UF 0805
2PCS 1.0UF 0805
1PCS 22 UF 0805
1PCS 4.7UF 0603
1
Main Board
GFXVR_DPRSLPVR 86
R0606@:Itel Checklist recommendation
+1.5V
DANIEL 0721
Processor Decoupling
Decoupling guide from Intel
Schematic R0.9: Schematic Checklist R0.7:
+VCORE
VCORE 22uF * 16pcs
10uF * 16pcs
470uF* 6pcs(2 no stuff).
12
12
C0640
C0640
C0641
C0641
22UF/6.3V
22UF/6.3V
22UF/6.3V
22UF/6.3V
8/5 delete C0646 (22UF,6.3V) for layout placement.
(+1.8VS,VCCPLL)
12
12
C0670
C0670
10UF/6.3V
10UF/6.3V
12
C0671
C0671
10UF/6.3V
10UF/6.3V
C0669
C0669
10UF/6.3V
10UF/6.3V
VCORE 22uF * 12pcs
12
C0635
C0635
22UF/6.3V
22UF/6.3V
12
C0672
C0672
10UF/6.3V
10UF/6.3V
10uF * 16pcs
470uF* 6pcs(2 no stuff).
12
12
C0636
C0636
C0637
C0637
22UF/6.3V
22UF/6.3V
22UF/6.3V
22UF/6.3V
12
C0673
C0673
10UF/6.3V
10UF/6.3V
12
C0647
C0647
22UF/6.3V
22UF/6.3V
12
12
C0677
C0677
10UF/6.3V
10UF/6.3V
5
4
3
C0678
C0678
10UF/6.3V
10UF/6.3V
12
C0679
C0679
10UF/6.3V
10UF/6.3V
12
C0680
C0680
10UF/6.3V
10UF/6.3V
12
C0681
C0681
10UF/6.3V
10UF/6.3V
12
C0682
C0682
10UF/6.3V
10UF/6.3V
12
C0683
C0683
10UF/6.3V
10UF/6.3V
2
CPU(4)_PWR
CPU(4)_PWR
CPU(4)_PWR
Title :
Title :
Title :
Daniel Huang
Daniel Huang
Daniel Huang
Engineer:
Engineer:
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Engineer:
David Lewis
David Lewis
David Lewis
1
6 99Thursday, April 15, 2010
6 99Thursday, April 15, 2010
6 99Thursday, April 15, 2010
Rev
Rev
Rev
1.01
1.01
1.01
5
4
3
2
1
Main Board
D D
CPU XDP connector
+VTT_CPU
J0701
J0701
31
1
SIDE1
32
SIDE2
FPC_CON_30P
FPC_CON_30P
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
C C
R1.3,item L21
1
1
CPUPWRGD_XDP
HBPM3#
HBPM2#
HBPM1#
HBPM0#
XDP_RST#_R
T0720T0720
T0721T0721
1 2
1 2
1
1
1
1
R071151Ohm R071151Ohm
12
1 2
T0716T0716
T0717T0717
T0718T0718
T0719T0719
R07090Ohm R07090Ohm
R07081KOhm R07081KOhm
R07071KOhm R07071KOhm
H_PWRGD_XDP 3
XDP_TRST# 3
H_CPUPWRGD 3,25
XDP_PREQ# 3
XDP_PRDY# 3
XDP_TDO 3
XDP_TDI 3
XDP_TMS 3
XDP_TCLK 3
XDP_DBRESET# 3,22
H_CPURST# 3
SMB_DAT_S 14, 15,16,28,29,53
SMB_CLK_S 14,15,16,28,29,53
CLK_ITP_BCLK# 3
CLK_ITP_BCLK 3
(45)
(54)
(39)
( 3)
( 5)
(52)
(56)
(58)
(57)
(48)
(46)
(42)
(40)
(44) +VTT_CPU
B B
T0722T0722
1
T0723T0723
1
T0724T0724
1
T0725T0725
1
T0726T0726
1
T0727T0727
1
T0728T0728
1
T0729T0729
1
T0730T0730
1
FFC
J0701
path
Put these test point near J0701.
Put it away from the FFC path.
A A
5
4
XDP_RST#_R
R0715 0Ohm @R0715 0Ohm @
XDP_OBS0 3
XDP_OBS1 3
XDP_OBS2 3
XDP_OBS3 3
XDP_OBS4 3
XDP_OBS5 3
XDP_OBS6 3
XDP_OBS7 3
PM_PWRBTN#_R 22
1 2
BUF_PLT_RST# 3,24,30,32,33,45,53,54,64,70
3
Title :
Title :
Title :
CPU(5)_XDP
CPU(5)_XDP
CPU(5)_XDP
James1_Wu
James1_Wu
Engineer:
Engineer:
M60J
M60J
M60J
1
Engineer:
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
James1_Wu
7 99Thursday, April 15, 2010
7 99Thursday, April 15, 2010
7 99Thursday, April 15, 2010
Rev
Rev
Rev
2.02
2.02
2.02
5
D D
C C
4
3
2
1
B B
A A
NB_****
NB_****
NB_****
Title :
Title :
Title :
Engineer:
Engineer:
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
David Lewis
David Lewis
David Lewis
1
Daniel Huang
Daniel Huang
Daniel Huang
8 99Wednesday, April 07, 2010
8 99Wednesday, April 07, 2010
8 99Wednesday, April 07, 2010
Rev
Rev
Rev
1.01
1.01
1.01
5
4
3
2
1
Main Board
D D
C C
B B
A A
Title :
Title :
Title :
NB_****
NB_****
NB_****
Daniel Huang
Daniel Huang
1
Daniel Huang
9 99Wednesday, April 07, 2010
9 99Wednesday, April 07, 2010
9 99Wednesday, April 07, 2010
Rev
Rev
Rev
1.01
1.01
1.01
Engineer:
Engineer:
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
David Lewis
David Lewis
David Lewis
5
4
3
2
1
Main Board
D D
C C
B B
A A
Title :
Title :
Title :
NB_****
NB_****
NB_****
Daniel Huang
Daniel Huang
1
Daniel Huang
10 99Wednesday, April 07, 2010
10 99Wednesday, April 07, 2010
10 99Wednesday, April 07, 2010
Rev
Rev
Rev
1.01
1.01
1.01
Engineer:
Engineer:
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
David Lewis
David Lewis
David Lewis
5
4
3
2
1
Main Board
D D
C C
B B
A A
Title :
Title :
Title :
NB_****
NB_****
NB_****
Daniel Huang
Daniel Huang
1
Daniel Huang
11 99Wednesday, April 07, 2010
11 99Wednesday, April 07, 2010
11 99Wednesday, April 07, 2010
Rev
Rev
Rev
1.01
1.01
1.01
Engineer:
Engineer:
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
David Lewis
David Lewis
David Lewis
5
4
3
2
1
Main Board
D D
C C
B B
A A
Title :
Title :
Title :
NB_****
NB_****
NB_****
Daniel Huang
Daniel Huang
1
Daniel Huang
12 99Wednesday, April 07, 2010
12 99Wednesday, April 07, 2010
12 99Wednesday, April 07, 2010
Rev
Rev
Rev
1.01
1.01
1.01
Engineer:
Engineer:
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
David Lewis
David Lewis
David Lewis
5
4
3
2
1
Main Board
D D
C C
B B
A A
Title :
Title :
Title :
NB_****
NB_****
NB_****
Daniel Huang
Daniel Huang
1
Daniel Huang
13 99Wednesday, April 07, 2010
13 99Wednesday, April 07, 2010
13 99Wednesday, April 07, 2010
Rev
Rev
Rev
1.01
1.01
1.01
Engineer:
Engineer:
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
David Lewis
David Lewis
David Lewis
5
M_B_DQ[6 3:0] 4,16
J1401A
M_B_A[15 :0]4,16
D D
M_B_BS04,16
M_B_BS14,16
M_B_BS24,16
M_B_CAS #4,16
M_CLK_D DR#45
M_CLK_D DR#55
M_CLK_D DR45
M_CLK_D DR55
M_CKE45
M_CKE55
M_B_DM[7:0]4,16
M_B_DQS [7:0]4,16
M_B_DQS #[7:0]4,16
C C
+1.5V
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS 0
M_B_DQS 1
M_B_DQS 2
M_B_DQS 3
M_B_DQS 4
M_B_DQS 5
M_B_DQS 6
M_B_DQS 7
M_B_DQS #0
M_B_DQS #1
M_B_DQS #2
M_B_DQS #3
M_B_DQS #4
M_B_DQS #5
M_B_DQS #6
M_B_DQS #7
J1401A
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
109
108
79
115
103
104
101
102
73
74
11
28
46
63
136
153
170
187
12
29
47
64
137
154
171
188
10
27
45
62
135
152
169
186
DDR3_D IMM_204P
DDR3_D IMM_204P
ARD
ARD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
BA0
BA1
BA2
CAS#
CK#0
CK#1
CK0
CK1
CKE0
CKE1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
SWAP
M_B_DQ5
5
DQ0
M_B_DQ6
7
DQ1
M_B_DQ3
15
DQ2
M_B_DQ2
17
DQ3
M_B_DQ0
4
DQ4
M_B_DQ1
6
DQ5
M_B_DQ4
16
DQ6
M_B_DQ7
18
DQ7
M_B_DQ1 0
21
DQ8
M_B_DQ8
23
DQ9
M_B_DQ1 1
33
DQ10
M_B_DQ1 4
35
DQ11
M_B_DQ9
22
DQ12
M_B_DQ1 2
24
DQ13
M_B_DQ1 5
34
DQ14
M_B_DQ1 3
36
DQ15
M_B_DQ1 7
39
DQ16
M_B_DQ2 0
41
DQ17
M_B_DQ1 8
51
DQ18
M_B_DQ2 3
53
DQ19
M_B_DQ2 1
40
DQ20
M_B_DQ1 6
42
DQ21
M_B_DQ1 9
50
DQ22
M_B_DQ2 2
52
DQ23
M_B_DQ2 8
57
DQ24
M_B_DQ3 1
59
DQ25
M_B_DQ2 6
67
DQ26
M_B_DQ2 5
69
DQ27
M_B_DQ2 4
56
DQ28
M_B_DQ2 9
58
DQ29
M_B_DQ3 0
68
DQ30
M_B_DQ2 7
70
DQ31
M_B_DQ3 6
129
DQ32
M_B_DQ3 2
131
DQ33
M_B_DQ3 9
141
DQ34
M_B_DQ3 5
143
DQ35
M_B_DQ3 7
130
DQ36
M_B_DQ3 3
132
DQ37
M_B_DQ3 4
140
DQ38
M_B_DQ3 8
142
DQ39
M_B_DQ4 1
147
DQ40
M_B_DQ4 4
149
DQ41
M_B_DQ4 2
157
DQ42
M_B_DQ4 3
159
DQ43
M_B_DQ4 5
146
DQ44
M_B_DQ4 0
148
DQ45
M_B_DQ4 6
158
DQ46
M_B_DQ4 7
160
DQ47
M_B_DQ5 2
163
DQ48
M_B_DQ5 0
165
DQ49
M_B_DQ5 4
175
DQ50
M_B_DQ5 5
177
DQ51
M_B_DQ4 8
164
DQ52
M_B_DQ5 3
166
DQ53
M_B_DQ5 1
174
DQ54
M_B_DQ4 9
176
DQ55
M_B_DQ6 0
181
DQ56
M_B_DQ5 7
183
DQ57
M_B_DQ6 1
191
DQ58
M_B_DQ6 3
193
DQ59
M_B_DQ5 8
180
DQ60
M_B_DQ5 6
182
DQ61
M_B_DQ5 9
192
DQ62
M_B_DQ6 2
194
DQ63
4
SMBus Slave Ad dress: A6H
R1.1
+1.5V
R1401 10KOhmR1 401 10KOhm
1 2
+3VS
R1403 10 KOhmR1403 10 KOhm
DANIEL 1105
Layout Note: Place these caps near SO DIMM 2
12
12
C1402
C1402
C1403
C1403
0.1UF/16V
0.1UF/16V
0.1UF/16V
0.1UF/16V
+3VS
12
12
C1407
C1407
C1406
C1406
0.1UF/16V
0.1UF/16V
2.2UF/10V
2.2UF/10V
PM_EXTT S#03 ,15,16
12
12
C1404
C1404
0.1UF/16V
0.1UF/16V
M_VREFC A_DIMM2
M_VREFD Q_DIMM2
M_DRAMRS T#3,1 5,16
12
C1405
C1405
0.1UF/16V
0.1UF/16V
DANIEL 0715
12
C1408
C1408
2.2UF/10V
2.2UF/10V
12
C1410
C1410
2.2UF/10V
2.2UF/10V
3
J1401B
0Ohm @
0Ohm @
12
12
C1409
C1409
0.1UF/16V
0.1UF/16V
C1411
C1411
0.1UF/16V
0.1UF/16V
J1401B
12
198
207
208
77
122
205
206
116
120
110
30
114
121
197
201
202
200
125
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
199
126
1
DDR3_D IMM_204P
DDR3_D IMM_204P
ARD
ARD
EVENT#
GND1
GND2
NC1
NC2
NP_NC1
NP_NC2
ODT0
ODT1
RAS#
RESET#
S#0
S#1
SA0
SA1
SCL
SDA
TEST
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDDSPD
VREFCA
VREFDQ
+0.75VS
2
VSS1
3
VSS2
8
VSS3
9
VSS4
13
VSS5
14
VSS6
19
VSS7
20
VSS8
25
VSS9
26
VSS10
31
VSS11
32
VSS12
37
VSS13
38
VSS14
43
VSS15
44
VSS16
48
VSS17
49
VSS18
54
VSS19
55
VSS20
60
VSS21
61
VSS22
65
VSS23
66
VSS24
71
VSS25
72
VSS26
127
VSS27
128
VSS28
133
VSS29
134
VSS30
138
VSS31
139
VSS32
144
VSS33
145
VSS34
150
VSS35
151
VSS36
155
VSS37
156
VSS38
161
VSS39
162
VSS40
167
VSS41
168
VSS42
172
VSS43
173
VSS44
178
VSS45
179
VSS46
184
VSS47
185
VSS48
189
VSS49
VSS50
VSS51
VSS52
+0.75VS
190
195
196
203
VTT1
204
VTT2
WE#
R1.1
113
M_B_WE # 4,16
R1402
R1402
M_ODT45
M_ODT55
M_B_RAS #4,16
M_CS#45
M_CS#55
SMB_CLK _S7,15 ,16,28,2 9,53
SMB_DAT _S7,15,1 6,28,29 ,53
2
1
Layout Note: Place these caps near SO DIMM 2
Layout Note: Place these caps near SO DIMM 2
12
+
+
12
C1401
C1401
10UF/6.3V
10UF/6.3V
12
C1416
C1416
10UF/6.3V
10UF/6.3V
CE1401
CE1401
@
@
330UF/2.5 V
330UF/2.5 V
12
12
C1412
C1412
1UF/6.3V
1UF/6.3V
12
12
C1417
C1417
C1418
C1418
10UF/6.3V
10UF/6.3V
10UF/6.3V
10UF/6.3V
12
12
C1420
C1420
C1419
C1419
10UF/6.3V
10UF/6.3V
10UF/6.3V
10UF/6.3V
C1413
C1413
1UF/6.3V
1UF/6.3V
12
12
C1415
C1415
C1414
C1414
1UF/6.3V
1UF/6.3V
1UF/6.3V
1UF/6.3V
DANIEL 0716
Title :
Title :
Title :
DDR3 SO-DIMM_2
DDR3 SO-DIMM_2
DDR3 SO-DIMM_2
Engineer:
Tommy_Chiang
Engineer:
Tommy_Chiang
Engineer:
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
Size Project Name
Size Project Name
Size Project Name
D
D
D
N62
N62
N62
Date: Sheet of
Thursday, April 15 , 2010
Date: Sheet of
Thursday, April 15 , 2010
Date: Sheet of
Thursday, April 15 , 2010
B B
Tommy_Chiang
14 93
14 93
14 93
Rev
Rev
Rev
1.01
1.01
1.01
A A
5
4
3
2
1
5
J1501A
M_A_A[15:0]4
D D
M_A_BS04
M_A_BS14
M_A_BS24
M_A_CAS#4
M_CLK_DDR#04
M_CLK_DDR#14
M_CLK_DDR04
M_CLK_DDR14
M_CKE04
M_A_DM[7:0]4
M_A_DQS[7:0]4
C C
M_A_DQS#[7:0]4
M_CKE14
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
J1501A
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12/BC#
119
A13
80
A14
78
A15
109
BA0
108
BA1
79
BA2
115
CAS#
103
CK#0
104
CK#1
101
CK0
102
CK1
73
CKE0
74
CKE1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
10
DQS#0
27
DQS#1
45
DQS#2
62
DQS#3
135
DQS#4
152
DQS#5
169
DQS#6
186
DQS#7
DDR3_DIMM_204P
DDR3_DIMM_204P
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
12G025532043
4
M_A_DQ6
5
M_A_DQ1
7
M_A_DQ3
15
M_A_DQ5
17
M_A_DQ4
4
M_A_DQ0
6
M_A_DQ2
16
M_A_DQ7
18
M_A_DQ12
21
M_A_DQ8
23
M_A_DQ11
33
M_A_DQ14
35
M_A_DQ13
22
M_A_DQ9
24
M_A_DQ15
34
M_A_DQ10
36
M_A_DQ17
39
M_A_DQ16
41
M_A_DQ18
51
M_A_DQ22
53
M_A_DQ21
40
M_A_DQ20
42
M_A_DQ23
50
M_A_DQ19
52
M_A_DQ24
57
M_A_DQ25
59
M_A_DQ30
67
M_A_DQ31
69
M_A_DQ28
56
M_A_DQ29
58
M_A_DQ27
68
M_A_DQ26
70
M_A_DQ37
129
M_A_DQ32
131
M_A_DQ35
141
M_A_DQ34
143
M_A_DQ36
130
M_A_DQ33
132
M_A_DQ39
140
M_A_DQ38
142
M_A_DQ40
147
M_A_DQ43
149
M_A_DQ42
157
M_A_DQ46
159
M_A_DQ44
146
M_A_DQ41
148
M_A_DQ47
158
M_A_DQ45
160
M_A_DQ49
163
M_A_DQ53
165
M_A_DQ55
175
M_A_DQ50
177
M_A_DQ52
164
M_A_DQ48
166
M_A_DQ54
174
M_A_DQ51
176
M_A_DQ61
181
M_A_DQ60
183
M_A_DQ59
191
M_A_DQ62
193
M_A_DQ56
180
M_A_DQ57
182
M_A_DQ63
192
M_A_DQ58
194
M_A_DQ[63:0] 4
0
1
2
3
4
5
6
7
3
SMBus Slave Address: A0H
12
12
R1503
R1503
R1501
R1501
10KOhm
10KOhm
10KOhm
10KOhm
+1.5V
Layout Note: Place these caps near SO DIMM 0
12
12
C1503
C1503
0.1UF/16V
0.1UF/16V
C1506
C1506
0.1UF/16V
0.1UF/16V
12
+3VS
12
12
C1505
C1505
2.2UF/10V
2.2UF/10V
C1502
C1502
0.1UF/16V
0.1UF/16V
PM_EXTTS#03,14,16
12
C1501
C1501
0.1UF/16V
0.1UF/16V
M_VREFCA_DIMM0
12
M_VREFDQ_DIMM0
12
2
M_DRAMRST#3,14,16
C1504
C1504
0.1UF/16V
0.1UF/16V
C1507
C1507
2.2UF/10V
2.2UF/10V
C1509
C1509
2.2UF/10V
2.2UF/10V
1
J1501B
R1502
R1502
0Ohm @
0Ohm @
M_ODT04
M_ODT14
M_A_RAS#4
M_CS#04
M_CS#14
SMB_CLK_S7,14,16,28,29,53
SMB_DAT_S7,14,16,28,29,53
12
C1508
C1508
0.1UF/16V
0.1UF/16V
12
C1510
C1510
0.1UF/16V
0.1UF/16V
J1501B
198
12
EVENT#
207
GND1
208
GND2
77
NC1
122
NC2
205
NP_NC1
206
NP_NC2
116
ODT0
120
ODT1
110
RAS#
30
RESET#
114
S#0
121
S#1
197
SA0
201
SA1
202
SCL
200
SDA
125
TEST
75
VDD1
76
VDD2
81
VDD3
82
VDD4
87
VDD5
88
VDD6
93
VDD7
94
VDD8
99
VDD9
100
VDD10
105
VDD11
106
VDD12
111
VDD13
112
VDD14
117
VDD15
118
VDD16
123
VDD17
124
VDD18
199
VDDSPD
126
VREFCA
1
VREFDQ
DDR3_DIMM_204P
DDR3_DIMM_204P
+0.75VS
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VTT1
VTT2
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
+0.75VS
190
195
196
203
204
113
WE#
R1.1
M_A_WE# 4
R1.1
12
12
C1512
C1512
1UF/10V
1UF/10V
12
C1513
C1513
1UF/10V
1UF/10V
C1514
C1514
1UF/10V
1UF/10V
12
C1511
C1511
1UF/10V
B B
+1.5V
12
+
+
CE1501
CE1501
@
@
330UF/2.5V
330UF/2.5V
1UF/10V
+1.5V
Layout Note: Place these caps near SO DIMM 0
12
12
C1516
C1516
10UF/6.3V
10UF/6.3V
12
C1517
C1517
10UF/6.3V
10UF/6.3V
5
12
C1515
C1515
10UF/6.3V
10UF/6.3V
A A
12
C1518
C1518
10UF/6.3V
10UF/6.3V
12
C1519
C1519
10UF/6.3V
10UF/6.3V
C1520
C1520
10UF/6.3V
10UF/6.3V
DDR3 SO-DIMM_0
DDR3 SO-DIMM_0
DDR3 SO-DIMM_0
Title :
Title :
Title :
Daniel Huang
Daniel Huang
Daniel Huang
Engineer:
Engineer:
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Thursday, April 15, 2010
Date: Sheet of
Thursday, April 15, 2010
Date: Sheet of
4
3
2
Thursday, April 15, 2010
Engineer:
David Lewis
David Lewis
David Lewis
1
15 98
15 98
15 98
Rev
Rev
Rev
1.1
1.1
1.1
5
M_B_DQ[6 3:0] 4 ,14
J1601A
M_B_A[15 :0]4,14
D D
M_B_BS04,14
M_B_BS14,14
M_B_BS24,14
M_B_CAS #4,14
M_CLK_D DR#24
M_CLK_D DR#34
M_CLK_D DR24
M_CLK_D DR34
M_CKE24
M_CKE34
M_B_DM[7:0]4,14
M_B_DQS [7:0]4,14
M_B_DQS #[7:0]4,14
C C
J1601A
M_B_A0
98
A0
M_B_A1
97
A1
M_B_A2
96
A2
M_B_A3
95
A3
M_B_A4
92
A4
M_B_A5
91
A5
M_B_A6
90
A6
M_B_A7
86
A7
M_B_A8
89
A8
M_B_A9
85
A9
M_B_A10
107
A10/AP
M_B_A11
84
A11
M_B_A12
83
A12/BC#
M_B_A13
119
A13
M_B_A14
80
A14
M_B_A15 M_B_DQ20
78
A15
109
BA0
108
BA1
79
BA2
115
CAS#
103
CK#0
104
CK#1
101
CK0
102
CK1
73
CKE0
74
CKE1
M_B_DM0
11
DM0
M_B_DM1
28
DM1
M_B_DM2
46
DM2
M_B_DM3
63
DM3
M_B_DM4
136
DM4
M_B_DM5
153
DM5
M_B_DM6
170
DM6
M_B_DM7
187
DM7
M_B_DQS 0
12
DQS0
M_B_DQS 1
29
DQS1
M_B_DQS 2
47
DQS2
M_B_DQS 3
64
DQS3
M_B_DQS 4
137
DQS4
M_B_DQS 5
154
DQS5
M_B_DQS 6
171
DQS6
M_B_DQS 7
188
DQS7
M_B_DQS #0
10
DQS#0
M_B_DQS #1
27
DQS#1
M_B_DQS #2
45
DQS#2
M_B_DQS #3
62
DQS#3
M_B_DQS #4
135
DQS#4
M_B_DQS #5
152
DQS#5
M_B_DQS #6
169
DQS#6
M_B_DQS #7
186
DQS#7
SWAP
M_B_DQ5
5
DQ0
M_B_DQ6
7
DQ1
M_B_DQ3
15
DQ2
M_B_DQ2
17
DQ3
M_B_DQ0
4
DQ4
M_B_DQ1
6
DQ5
M_B_DQ4
16
DQ6
M_B_DQ7
18
DQ7
M_B_DQ1 0
21
DQ8
M_B_DQ8
23
DQ9
M_B_DQ1 1
33
DQ10
M_B_DQ1 4
35
DQ11
M_B_DQ9
22
DQ12
M_B_DQ1 2
24
DQ13
M_B_DQ1 5
34
DQ14
M_B_DQ1 3
36
DQ15
M_B_DQ1 7
39
DQ16
41
DQ17
M_B_DQ1 8
51
DQ18
M_B_DQ2 3
53
DQ19
M_B_DQ2 1
40
DQ20
M_B_DQ1 6
42
DQ21
M_B_DQ1 9
50
DQ22
M_B_DQ2 2
52
DQ23
M_B_DQ2 8
57
DQ24
M_B_DQ3 1
59
DQ25
M_B_DQ2 6
67
DQ26
M_B_DQ2 5
69
DQ27
M_B_DQ2 4
56
DQ28
M_B_DQ2 9
58
DQ29
M_B_DQ3 0
68
DQ30
M_B_DQ2 7
70
DQ31
M_B_DQ3 6
129
DQ32
M_B_DQ3 2
131
DQ33
M_B_DQ3 9
141
DQ34
M_B_DQ3 5
143
DQ35
M_B_DQ3 7
130
DQ36
M_B_DQ3 3
132
DQ37
M_B_DQ3 4
140
DQ38
M_B_DQ3 8
142
DQ39
M_B_DQ4 1
147
DQ40
M_B_DQ4 4
149
DQ41
M_B_DQ4 2
157
DQ42
M_B_DQ4 3
159
DQ43
M_B_DQ4 5
146
DQ44
M_B_DQ4 0
148
DQ45
M_B_DQ4 6
158
DQ46
M_B_DQ4 7
160
DQ47
M_B_DQ5 2
163
DQ48
M_B_DQ5 0
165
DQ49
M_B_DQ5 4
175
DQ50
M_B_DQ5 5
177
DQ51
M_B_DQ4 8
164
DQ52
M_B_DQ5 3
166
DQ53
M_B_DQ5 1
174
DQ54
M_B_DQ4 9
176
DQ55
M_B_DQ6 0
181
DQ56
M_B_DQ5 7
183
DQ57
M_B_DQ6 1
191
DQ58
M_B_DQ6 3
193
DQ59
M_B_DQ5 8
180
DQ60
M_B_DQ5 6
182
DQ61
M_B_DQ5 9
192
DQ62
M_B_DQ6 2
194
DQ63
12G02554204D
DDR3_D IMM_204P
DDR3_D IMM_204P
+1.5V
12
+
+
CE1601
CE1601
330UF/2.5 V
330UF/2.5 V
+1.5V
Layout Note: Place th ese caps near SO DIM M 1
12
C1601
C1601
10UF/6.3V
10UF/6.3V
12
12
C1616
C1616
10UF/6.3V
10UF/6.3V
C1617
C1617
10UF/6.3V
10UF/6.3V
12
C1618
C1618
10UF/6.3V
10UF/6.3V
12
12
C1620
C1620
C1619
C1619
10UF/6.3V
10UF/6.3V
10UF/6.3V
10UF/6.3V
4
SMBus Slave Ad dress: A4H
+1.5V
Layout Note: Place th ese caps near SO DIM M 1
+3VS
12
C1606
C1606
2.2UF/10V
2.2UF/10V
12
C1602
C1602
0.1UF/16V
0.1UF/16V
3
J1601B
0Ohm @
0Ohm @
12
12
C1609
C1609
0.1UF/16V
0.1UF/16V
C1611
C1611
0.1UF/16V
0.1UF/16V
J1601B
12
198
207
208
77
122
205
206
116
120
110
30
114
121
197
201
202
200
125
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
199
126
1
DDR3_D IMM_204P
DDR3_D IMM_204P
EVENT#
GND1
GND2
NC1
NC2
NP_NC1
NP_NC2
ODT0
ODT1
RAS#
RESET#
S#0
S#1
SA0
SA1
SCL
SDA
TEST
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDDSPD
VREFCA
VREFDQ
2
VSS1
3
VSS2
8
VSS3
9
VSS4
13
VSS5
14
VSS6
19
VSS7
20
VSS8
25
VSS9
26
VSS10
31
VSS11
32
VSS12
37
VSS13
38
VSS14
43
VSS15
44
VSS16
48
VSS17
49
VSS18
54
VSS19
55
VSS20
60
VSS21
61
VSS22
65
VSS23
66
VSS24
71
VSS25
72
VSS26
127
VSS27
128
VSS28
133
VSS29
134
VSS30
138
VSS31
139
VSS32
144
VSS33
145
VSS34
150
VSS35
151
VSS36
155
VSS37
156
VSS38
161
VSS39
162
VSS40
167
VSS41
168
VSS42
172
VSS43
173
VSS44
178
VSS45
179
VSS46
184
VSS47
185
VSS48
189
VSS49
+0.75VS
190
VSS50
195
VSS51
196
VSS52
203
VTT1
204
VTT2
113
WE#
R1.1
M_B_WE # 4,14
12G02554204D
+0.75VS
R1.1
12
12
C1612
C1612
1UF/10V
1UF/10V
C1613
C1613
1UF/10V
1UF/10V
12
12
C1615
C1615
C1614
C1614
1UF/10V
1UF/10V
1UF/10V
1UF/10V
R1602
R1602
PM_EXTT S#03 ,14,15
M_ODT24
M_ODT34
M_B_RAS #4,14
M_DRAMRS T#3,1 4,15
M_CS#24
12
12
12
C1604
C1604
0.1UF/16V
0.1UF/16V
M_VREFC A_DIMM1
M_VREFD Q_DIMM1
M_CS#34
SMB_CLK _S7,14 ,15,28,2 9,53
SMB_DAT _S7,14,1 5,28,29 ,53
12
C1605
C1605
0.1UF/16V
0.1UF/16V
12
C1608
C1608
2.2UF/10V
2.2UF/10V
12
C1610
C1610
2.2UF/10V
2.2UF/10V
R1601
R1601
+3VS
10KOhm
10KOhm
R1603
R1603
10KOhm
10KOhm
12
C1603
C1603
0.1UF/16V
0.1UF/16V
12
C1607
C1607
0.1UF/16V
0.1UF/16V
2
1
B B
A A
Title :
Title :
Title :
DDR3 SO-DIMM_1
DDR3 SO-DIMM_1
DDR3 SO-DIMM_1
Engineer:
CH_Lin
Engineer:
CH_Lin
Engineer:
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
Size Project Name
Size Project Name
Size Project Name
D
D
D
M60JV
M60JV
M60JV
Date: Sheet of
Thursday, April 15 , 2010
Date: Sheet of
Thursday, April 15 , 2010
Date: Sheet of
5
4
3
2
Thursday, April 15 , 2010
1
CH_Lin
16 99
16 99
16 99
Rev
Rev
Rev
1.1
1.1
1.1
5
D D
C C
4
3
2
1
B B
A A
DDR3 TERMINATION
DDR3 TERMINATION
DDR3 TERMINATION
Title :
Title :
Title :
Daniel Huang
Daniel Huang
Daniel Huang
Engineer:
Engineer:
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Wednesday, April 07, 2010
Date: Sheet of
Wednesday, April 07, 2010
Date: Sheet of
5
4
3
2
Wednesday, April 07, 2010
Engineer:
David Lewis
David Lewis
David Lewis
1
17 96
17 96
17 96
Rev
Rev
Rev
1.01
1.01
1.01
5
4
3
2
1
For DDR3_VREF command & address.
Calpella Clarksfield DDR3 SO-DIMM VREFDQ
Platform Design Guide Change Details
D D
Default
M1
Near J1501<5000 mil
C C
Near J1601<5000 mil
Near J1401<5000 mil
B B
DDR3 Vref
Intel Document Number: 400755
+1.5V
R1807
R1807
1KOHM
1KOHM
12
C1811
C1811
0.1UF/10V
0.1UF/10V
12
C1802
C1802
0.1UF/10V
0.1UF/10V
12
C1804
C1804
0.1UF/10V
0.1UF/10V
1 2
12
GNDGND
+1.5V
1 2
12
GNDGND
+1.5V
1 2
12
GNDGND
R1808
R1808
1KOHM
1KOHM
R1812
R1812
1KOHM
1KOHM
R1811
R1811
1KOHM
1KOHM
R1818
R1818
1KOHM
1KOHM
R1819
R1819
1KOHM
1KOHM
R1809 0OhmR1809 0Ohm
R1810 0OhmR1810 0Ohm
R1820 0OhmR1820 0Ohm
1 2
1 2
1 2
M_VREF_DDR3
M_VREFDQ_DIMM0
M_VREFCA_DIMM0
M_VREFCA_DIMM1
M_VREFCA_DIMM2
M_VREFDQ_DIMM1
M_VREFDQ_DIMM2
R1802 0OhmR1802 0Ohm
1 2
R1813
R1813
0Ohm
0Ohm
@
@
1 2
DIMM0_VREF_DQ5
DIMM1_VREF_DQ5
DIMM1_VREF_DQ5
M3
M3: Processor Generated SO-DIMM VREFDQ
– New Requirement
Option: Mount=R1802,R1803,R1805,R1806
Unmount=R1801,R1804,R1809,M2 block
R1826
R1826
0Ohm
0Ohm
@
@
1 2
R1803 0OhmR1803 0Ohm
1 2
R1824 0OhmR1824 0Ohm
1 2
R1801 0OhmR1801 0Ohm
1 2
R1804 0OhmR1804 0Ohm
1 2
R1825 0OhmR1825 0Ohm
1 2
R1805 0Ohm
R1805 0Ohm
1 2
CFD
CFD
R1806 0Ohm
R1806 0Ohm
1 2
CFD
CFD
R1821 0Ohm
R1821 0Ohm
1 2
CFD
CFD
1
3
+5V
52
U1801
U1801
V+
V+
+
+
-
ÂV-
V-
LMV321IDBVR
LMV321IDBVR
@
@
GND
12
C1801
C1801
0.1UF/10V
0.1UF/10V
c0402
c0402
@
@
GND
4
DDR3 CA_DQ VOLTAGE
DDR3 CA_DQ VOLTAGE
DDR3 CA_DQ VOLTAGE
Title :
Title :
Title :
Daniel Huang
Daniel Huang
Daniel Huang
Engineer:
Engineer:
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Thursday, April 15, 2010
Date: Sheet of
Thursday, April 15, 2010
Date: Sheet of
4
3
2
Thursday, April 15, 2010
Engineer:
David Lewis
David Lewis
David Lewis
1
18 99
18 99
18 99
Rev
Rev
Rev
1.01
1.01
1.01
+1.5V
12
R1822
R1822
10KOhm
10KOhm
r0402_h16
r0402_h16
@
A A
5
12
C1803
C1803
0.1UF/10V
0.1UF/10V
c0402
c0402
@
@
GND
12
@
R1823
R1823
10KOhm
10KOhm
r0402_h16
r0402_h16
@
@
5
D D
C C
4
3
2
1
B B
A A
VID Controller
VID Controller
VID Controller
Title :
Title :
Title :
1
Daniel Huang
19 99Wednesday, April 07, 2010
19 99Wednesday, April 07, 2010
19 99Wednesday, April 07, 2010
Rev
Rev
Rev
1.01
1.01
1.01
Engineer:
Engineer:
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
ASUSTeK COMPUTER INC. NB1
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
David Lewis
David Lewis
David Lewis
5
4
3
2
1
RTC battery
D D
+VCC_RTC
R2005
R2005
1MOhm
1MOhm
1 2
C C
B B
HDA_DOCK_EN#
414044 Design Guide R1.11 Upda te: page9
GPIO33:
This signal should be only asserted low through an external
pull-down in manufacturing or debug environments ONLY.
Without connecting GPIO33,
customers may not be able to override SPI flash contents.
12G201100208
RTCRST# RC delay
should be 18ms~25ms
12
R2003
R2003
20KOhm
20KOhm
1%
1%
12
GND GND
12
R2004
R2004
20KOhm
20KOhm
1%
1%
12
TPM Settings
Clear ME RTC
Registers
Keep ME RTC
Registers
ACZ_BCLK_AUD36
ACZ_SYNC_AUD36
ACZ_RST#_AUD36,37
ACZ_SDOUT_AUD36
ACZ_SDIN0_AUD36
+RTCBAT
12
R2001 1KOhmR2001 1KOhm
3
4
BATT_HOLDER_2P
BATT_HOLDER_2P
BAT1
BAT1
GND
1
C2004
C2004
1UF/10V
1UF/10V
2
1
JRST2002
JRST2002
1
C2005
C2005
SGL_JUMP
SGL_JUMP
2
1UF/10V
1UF/10V
2
GNDGND
JRST2002
Shunt
Open
(Default)
R1.1,item B2
+3VA
JP2001
JP2001
112
1MM_OPEN_5MIL
1MM_OPEN_5MIL
+RTC_BAT
12
JRST2001
JRST2001
1
SGL_JUMP
SGL_JUMP
2
RX2021 33OhmRX2021 33Ohm
1 2
RX2022 33OhmRX2022 33Ohm
1 2
RX2023 33OhmRX2023 33Ohm
1 2
RX2024 33OhmRX2024 33Ohm
1 2
R20291KOhm @ R20291KOhm @
12
GND
+3VA_RTC
2
1
2
CMOS Settings
Clear CMOS
Keep CMOS
+VCC_RTC
D2001
D2001
3
12
C2003
GND
Request by CSC
for CMOS clear
function
JRST2001
Shunt
Open
(Default)
C2003
1UF/10V
1UF/10V
GND
GND
T2008T2008
BAT54C
BAT54C
HDA_SYNC: Select VCCVRM 1.5V or 1.8V
ACZ_BCLK
ACZ_SYNC
ACZ_RST#
ACZ_SDOUT
ACZ_SDIN
PCH_SPI_OV30
R1.1,item L4
+3VSUS_ORG
R1.2,item L5
MoW50 IbexPeak JTAG requirements:
C2001 12PF/50Vc0402C2001 12PF/50Vc0402
1 2
C2002 12PF/50Vc0402C2002 12PF/50Vc0402
1 2
R2008: For Xtal measurement
1
+3VS
1 2
32
3
3
D
D
Q2001
Q2001
H2N7002
H2N7002
1
1
1
G
G
2
2
GND
S
S
2
3
R2030
R2030
10KOhm
10KOhm
@
@
@
@
SPI_CLK28,30
SPI_CS#028,30
+3VS
SPI_SI28
14
R2009
R2009
0Ohm
0Ohm
1 2
12
TXC 15PF
CITIZEN 12PF
X2001
X2001
32.768Khz
32.768Khz
X2RTC
R20151KOhm @ R20151KOhm @
CITIZEN
R2008
R2008
+VCC_RTC
R1.3,item L20
T2002T2002
Shoud we connect to EC?
R2032 15OhmR2032 15Ohm
12
R2002
R2002
10MOhm
10MOhm
12
0Ohm
0Ohm
R2006 330KOhmR2006 330KOhm
T2001T2001
1
1
T2003T2003
T2007T2007
T2013T2013
HDA_DOCK_EN#
HDA_DOCK_RST#
12
1
SPI_SO28
12
1
1
X1_RTC
X2_RTC
RTCRST#
SRTCRST#
SM_INTRUDER#
ACZ_BCLK
ACZ_SYNC
ACZ_RST#
ACZ_SDIN
ACZ_SDIN1_MDC
ACZ_SDOUT
Internal PU 20K
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_RST#
SB_SPICS0#
SB_SPICS1#
U2001A
U2001A
B13
RTCX1
D13
RTCX2
C14
RTCRST#
D17
SRTCRST#
A16
INTRUDER#
A14
INTVRMEN
A30
HDA_BCLK
D29
HDA_SYNC
P1
SPKR
C30
HDA_RST#
G30
HDA_SDIN0
F30
HDA_SDIN1
E32
HDA_SDIN2
F32
HDA_SDIN3
B29
HDA_SDO
H32
HDA_DOCK_EN#/GPIO33
J30
HDA_DOCK_RST#/GPIO13
M3
JTAG_TCK
K3
JTAG_TMS
K1
JTAG_TDI
J2
JTAG_TDO
J4
JTAG_RST#
BA2
SPI_CLK
AV3
SPI_CS0#
AY3
SPI_CS1#
AY1
SPI_MOSI
AV1
SPI_MISO
IBEXPEAK-M
IBEXPEAK-M
RTCIHDA
RTCIHDA
SPI JTAG
SPI JTAG
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
FWH4/LFRAME#
LDRQ1#/GPIO23
LPC
LPC
SATA
SATA
SATAICOMPO
SATAICOMPI
SATA0GP/GPIO21
SATA1GP/GPIO19
LDRQ0#
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATALED#
D33
B33
C32
A32
C34
PCH_DRQ#0
A34
LPC_DRQ#1
F34
AB9
Primary master of SATA controller 1
AK7
AK6
SATA_TXN0_H
AK11
SATA_TXP0_H
AK9
Secondary master of SATA controller 1
AH6
AH5
SATA_TXN1_H
AH9
SATA_TXP1_H
AH8
AF11
AF9
SATA2,3:
AF7
AF6
EDS 1.0: SATA port2,port3 may not be available in all PCH SKUs.
AH3
AH1
AF3
AF1
Primary master of SATA controller 2
AD9
AD8
SATA_TXN4_H
AD6
SATA_TXP4_H
AD5
AD3
AD1
SATA_TXN5_H
AB3
SATA_TXP5_H
AB1
AF16
AF15
T3
Y9
V1
SATA0GP
SATA1GP
SATA_COMP
37.4Ohm
37.4Ohm
1 2
R2007
R2007
1%
1%
10KOhm
10KOhm
1 2
R2025
R2025
CX2002 0.01UF/16VMLCC 0.01UF/16V (0402) X7R 10% CX2002 0.01UF/16VMLCC 0.01UF /16V (0402) X7R 10%
CX2001 0.01UF/16VMLCC 0.01UF/16V (0402) X7R 10% CX2001 0.01UF/16VMLCC 0.01UF /16V (0402) X7R 10%
CX2004 0.01UF/16VMLCC 0.01UF/16V (0402) X7R 10% CX2004 0.01UF/16VMLCC 0.01UF /16V (0402) X7R 10%
CX2003 0.01UF/16VMLCC 0.01UF/16V (0402) X7R 10% CX2003 0.01UF/16VMLCC 0.01UF /16V (0402) X7R 10%
CX2006 0.01UF/16VMLCC 0.01UF/16V (0402) X7R 10% CX2006 0.01UF/16VMLCC 0.01UF /16V (0402) X7R 10%
CX2005 0.01UF/16VMLCC 0.01UF/16V (0402) X7R 10% CX2005 0.01UF/16VMLCC 0.01UF /16V (0402) X7R 10%
CX2008 0.01UF/16VMLCC 0.01UF/16V (0402) X7R 10% CX2008 0.01UF/16VMLCC 0.01UF /16V (0402) X7R 10%
CX2007 0.01UF/16VMLCC 0.01UF/16V (0402) X7R 10% CX2007 0.01UF/16VMLCC 0.01UF /16V (0402) X7R 10%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+3VS
SATA_LED# 31
PCH XDP
PCH XDP
T2005T2005
1
T2006T2006
1
LPC_AD0 30,44
LPC_AD1 30,44
LPC_AD2 30,44
LPC_AD3 30,44
LPC_FRAME# 30,44
INT_SERIRQ 30
SATA_RXN0 51
SATA_RXP0 51
SATA_TXN0 51
SATA_TXP0 51
SATA_RXN1 51
SATA_RXP1 51
SATA_TXN1 51
SATA_TXP1 51
SATA_RXN4 51
SATA_RXP4 51
SATA_TXN4 51
SATA_TXP4 51
SATA_RXN5 49
SATA_RXP5 49
SATA_TXN5 49
SATA_TXP5 49
DANIEL 0821
DANIEL 0821
Core power plane
+VTT_PCH_VCCIO
Strap information:
HDA_SPKR: No reboot strap
Low: Disable.
High:Enable
HDA_DOCK_EN#:
A A
1.Flash descriptor security :
Sampled low: override
Sampled high: in effect.
2.GPIO33 low on the rising edge of PWROK,
Will also disable Intel ME.
SPI_MOSI: iTPM strap.
Mount R2015: Enable
Unmount R2015: Disable(defa ult)
5
+3VSUS_ORG
4
VTAP Assumed as 1.1V
Change resister divider to 20/10K ?
R2016
@R2016
@
PCH_JTAG_TDO
12
200Ohm1%
200Ohm1%
R2017
@R2017
@
PCH_JTAG_TMS
12
200Ohm1%
200Ohm1%
R2018
@R2018
@
PCH_JTAG_TDI
12
200Ohm1%
200Ohm1%
PCH_JTAG_RST#
12
R2019
@R2019
@
20KOhm
20KOhm
1%
1%
R2020
1 2
100Ohm
100Ohm
R2021
1 2
100Ohm
100Ohm
R2022
1 2
100Ohm
100Ohm
R2023
R2023
1 2
10KOhm@
10KOhm@
1% @R2020
1% @
1% @R2021
1% @
1% @R2022
1% @
GND
Signal Name
JTAG_TDI
JTAG_TMS Suspend
JTAG_TCK Suspend
TRST# Suspend
JTAG_TDO Suspend
PCH_JTAG_TCK
3
Power Well
Suspend
R2014
R2014
1 2
4.7KOhm
4.7KOhm
Driver During Reset
Internal Pull-up
Internal Pull-up
Internal Pull-down
Internal Pull-up
GND
DANIEL 1026
+3VS
INT_SERIRQ
SATA0GP
SATA1GP
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
10KOhm
10KOhm
1 2
R2026
R2026
10KOhm
10KOhm
1 2
R2027
R2027
10KOhm
10KOhm
1 2
R2028
R2028
David Lewis
David Lewis
David Lewis
1
PCH XDP@?
PCH_IBEX(1)SATA,IHDA,RTC,LPC
PCH_IBEX(1)SATA,IHDA,RTC,LPC
PCH_IBEX(1)SATA,IHDA,RTC,LPC
Title :
Title :
Title :
Daniel Huang
Daniel Huang
Daniel Huang
Engineer:
Engineer:
Engineer:
20 99Thursday, April 15, 2010
20 99Thursday, April 15, 2010
20 99Thursday, April 15, 2010
Rev
Rev
Rev
1.3
1.3
1.3
5
PCIE_RXN1_TV64
PCIE_RXP1_TV64
PCIE_TXN1_C64
PCIE_TXP1_C64
D D
PCIE2: WLAN
PCIE4: USB30
PCIE6: LAN
PCIE_RXN2_WLAN53
PCIE_RXP2_WLAN53
PCIE_TXN2_C53
PCIE_TXP2_C53
PCIE_RXN4_USB3054
PCIE_RXP4_USB3054
PCIE_TXN4_C54
PCIE_TXP4_C54
PCIE_RXN6_GLAN33
PCIE_RXP6_GLAN33
PCIE_TXN6_C33
PCIE_TXP6_C33
PCIE_TXN1_TV
CX21010.1UF/16V CX21010.1UF/16V
12
PCIE_TXP1_TV
CX21020.1UF/16V CX21020.1UF/16V
12
PCIE_TXN2_WLAN
CX21030.1UF/16V CX21030.1UF/16V
12
PCIE_TXP2_WLAN
CX21040.1UF/16V CX21040.1UF/16V
12
PCIE_TXN4_USB30
CX21060.1UF/16V CX21060.1UF/16V
12
PCIE_TXP4_USB30
CX21050.1UF/16V CX21050.1UF/16V
12
PCIE_TXN6_GLAN
CX21110.1UF/16V CX21110.1UF/16V
12
12
PCIE_TXP6_GLAN
CX21120.1UF/16V CX21120.1UF/16V
Port 7 & 8 may not be available in all Ibex Peak SKUs
C C
CLK_PCIE_TV#_PCH64
CLK_PCIE_TV_PCH64
CLKREQ1_TV#64
CLK_PCIE_WLAN#_PCH53
CLK_PCIE_WLAN_PCH53
CLKREQ2_WLAN#53
CLK_PCIE_USB30N_PCH54
CLK_PCIE_USB30P_PCH54
CLKREQ4_USB30#54
CLK_PCIE_GLAN_N_PCH33
CLK_PCIE_GLAN_P_PCH33
B B
A A
CLKREQ_GLAN#33
Note: Place these
resisters near
to PCIe Slots
CLK_REQ0#
CLK_PCH_SRC1_N
RX210422Ohm RX210422Ohm
12
12
12
12
12
12
12
12
12
12
12
12
CLK_PCH_SRC1_P
RX210322Ohm RX210322Ohm
CLKREQ1_TV_N
R21080Ohm R21080Ohm
CLK_PCH_SRC2_N
RX21060Ohm RX21060Ohm
CLK_PCH_SRC2_P
RX21050Ohm RX21050Ohm
CLKREQ2_WLAN_N
R21130Ohm R21130Ohm
CLK_PCH_USB30_N
RX21070Ohm RX21070Ohm
CLK_PCH_USB30_P
RX21080Ohm RX21080Ohm
CLKREQ4_USB30#_H
R21150Ohm R21150Ohm
CLK_PCH_PEGB_N
RX21110Ohm RX21110Ohm
CLK_PCH_PEGB_P
RX21120Ohm RX21120Ohm
CLKREQ_GLAN#_H
R21560Ohm R21560Ohm
CLK_REQ3#
CLK_REQ5#
4
U2001B
U2001B
BG30
BJ30
BF29
BH29
AW30
BA30
BC30
BD30
AU30
AT30
AU32
AV32
BA32
BB32
BD32
BE32
BF33
BH33
BG32
BJ32
BA34
AW34
BC34
BD34
AT34
AU34
AU36
AV36
BG34
BJ34
BG36
BJ36
AK48
AK47
P9
AM43
AM45
U4
AM47
AM48
N4
AH42
AH41
A8
AM51
AM53
M9
AJ50
AJ52
H6
AK53
AK51
P13
IBEXPEAK-M
IBEXPEAK-M
R1.1,item 25
DGPU_PWROK25,79
PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5
PERN6
PERP6
PETN6
PETP6
PERN7
PERP7
PETN7
PETP7
PERN8
PERP8
PETN8
PETP8
CLKOUT_PCIE0N
CLKOUT_PCIE0P
PCIECLKRQ0#/GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
PCIECLKRQ1#/GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P
PCIECLKRQ2#/GPIO20
CLKOUT_PCIE3N
CLKOUT_PCIE3P
PCIECLKRQ3#/GPIO25
CLKOUT_PCIE4N
CLKOUT_PCIE4P
PCIECLKRQ4#/GPIO26
CLKOUT_PCIE5N
CLKOUT_PCIE5P
PCIECLKRQ5#/GPIO44
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
PEG_B_CLKRQ#/GPIO56
SMBus
SMBus
PCI-E*
PCI-E*
Link
Link
Controller
Controller
PEG
PEG
CLKOUT_DP_N/CLKOUT_BCLK1_N
CLKOUT_DP_P/CLKOUT_BCLK1_P
From CLK BUFFER
From CLK BUFFER
Clock Flex
Clock Flex
+3VA
12
R2129
R2129
1KOhmARD
1KOhmARD
32
3
3
D
D
ARD
ARD
Q2101
Q2101
1
1
1
2N7002
2N7002
G
G
S
S
2
2
GND
SMBALERT#/GPIO11
SMBCLK
SMBDATA
SML0ALERT#/GPIO60
SML0CLK
SML0DATA
SML1ALERT#/GPIO74
SML1CLK/GPIO58
SML1DATA/GPIO75
CL_CLK1
CL_DATA1
CL_RST1#
PEG_A_CLKRQ#/GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_BCLK_N
CLKIN_BCLK_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N/CKSSCD_N
CLKIN_SATA_P/CKSSCD_P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0/GPIO64
CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67
R2121
@R2121
@
CLKREQ_PEG#
1 2
0Ohm
0Ohm
B9
H14
C8
SML0ALERT#
J14
SML0_CLK
C6
SML0_DAT
G8
SML1ALERT#
M14
SML1_CLK
E10
SML1_DAT
G12
T13
T11
T9
H1
CLK_PCIE_PEG#_PCH_L
AD43
CLK_PCIE_PEG_PCH_L
AD45
AN4
AN2
CLK_DREF#_L
AT1
CLK_DREF_L
AT3
AW24
BA24
AP3
AP1
F18
E18
AH13
AH12
P41
J42
X1_25IN
AH51
X2_25OUT
AH53
XCLK_COMP
AF38
CLK_OUT0
T45
CLK_OUT1
P43
CLK_OUT2
T42
N50
3
R1.2,item L2
T2104T2104
1
T2105T2105
1
RX2141 0OhmRX2141 0Ohm
1 2
RX2140 0OhmRX2140 0Ohm
1 2
RX2116 0OhmRX2116 0Ohm
1 2
RX2115 0OhmRX2115 0Ohm
1 2
R2117 90. 9Ohm 1%R2117 90.9Ohm 1%
1 2
T2112T2112
1
T2111T2111
1
T2114T2114
1
T2113T2113
1
1
1
+VTT_PCH_VCCIO
DANIEL 0819
Check BIOS
DANIEL 1230
EXT_SCI# 30
SCL_3A 28
SDA_3A 28
R1.3,item L2
T2106T2106
T2107T2107
SML1_CLK 28
SML1_DAT 28
CL_CLK 53
CL_DATA 53
CL_RST# 53
CLKREQ_PEG# 70
CLK_PCIE_PEG#_PCH 70
CLK_PCIE_PEG_PCH 70
CLK_DMI#_PCH 3
CLK_DMI_PCH 3
CLK_DREF# 3
CLK_DREF 3
CLK_DMI# 29
CLK_DMI 29
CLK_PCH_BCLK# 29
CLK_PCH_BCLK 29
CLK_DOT96# 29
CLK_DOT96 29
CLK_SATA# 29
CLK_SATA 29
CLK_ICH14 29
CLK_PCI_FB 24
2
Check here
To EC
R1.2,item B1
ICS9LRS3197 output with integrated 33ohm sereis resistor
R2122
CFDR2122
CFD
1 2
0Ohm
0Ohm
C2101
C2101
Signal Name
PCIECLKRQ0#
PCIECLKRQ1#
PCIECLKRQ2#
PCIECLKRQ[7:3]#
PCH CLKREQ Setting:
Not connected to device.
GND
Connected to device.
Default : Clock free run. (PD 10K).
Reserver 10K PU for power saving purpose.
CLKREQ4_USB30#_H
R2151
R2151
0Ohm
0Ohm
ARD
ARD
1 2
R2120
ARDR2120
ARD
X225OUT
1 2
0Ohm
0Ohm
R2120: For Xtal measurement
15PF/50V
15PF/50V
X2101
X2101
4
2
25Mhz
25Mhz
ARD
ARD
1 3
C2102
C2102
15PF/50V
15PF/50V
1
R1.1,item L5
+3VSUS_ORG
10KOhm
EXT_SCI#
SML0ALERT#
SCL_3A
SDA_3A
SML0_CLK
SML0_DAT
SML1_CLK
SML1_DAT
SML1ALERT#
DG R1.1,page 43:
The pull-up resistor value for SML0DATA and SML0CLK
has been updated from 4.7 K ±5% to 2.2 K ±5% to support
400-kHz bus speed
CLK_REQ0#
CLK_REQ3#
CLK_REQ5#CLK_OUT3
CLKREQ2_WLAN_N
CLKREQ1_TV_N
CLKREQ_GLAN#_H
CLK_REQ4#_CB
CLKREQ1_TV_N
CLK_REQ4#_CB
CLKREQ2_WLAN_N
CLKREQ_GLAN#_H
CLKREQ_PEG#
CLKREQ4_USB30#_H
10KOhm
1 2
10KOhm
10KOhm
1 2
2.2KOhm
2.2KOhm
1 2
2.2KOhm
2.2KOhm
1 2
2.2KOhm
2.2KOhm
1 2
2.2KOhm
2.2KOhm
1 2
1 2
1 2
1 2
Power Well
Suspend
Core
Core
Suspend
Driver During Reset
External Pull-up
External Pull-up
External Pull-up
External Pull-up
R2138 10KOhmR2138 10KOhm
1 2
R2140 10KOhmR2140 10KOhm
1 2
R2141 10KOhmR2141 10KOhm
1 2
R2123 10KOhm@R2123 10KOhm@
1 2
R2135 10KOhm@R2135 10KOhm@
1 2
R2143 10KOhm
R2143 10KOhm
1 2
R2125 10KOhm@R2125 10KOhm@
1 2
R2127 10KOhmR2127 10KOhm
1 2
R2150 10KOhmR2150 10KOhm
1 2
R2149 10KOhm
R2149 10KOhm
1 2
R2144 10KOhmR2144 10KOhm
1 2
R2146 10KOhmR2146 10KOhm
1 2
R2139 10KOhmR2139 10KOhm
1 2
R2145 10KOhmR2145 10KOhm
1 2
R2130
R2130
R2131
R2131
R2132
R2132
R2133
R2133
R2148
R2148
R2147
R2147
R21364.7KOhm R21364.7KOhm
R21374.7KOhm R21374.7KOhm
R214210KOhm R214210KOhm
Value
10K
10K
10K
10K
+3VSUS_ORG
+3VS
+3VSUS_ORG
@
@
@
@
GND
PCH_IBEX(2)_PCIE,CLK,SMB,PEG
PCH_IBEX(2)_PCIE,CLK,SMB,PEG
PCH_IBEX(2)_PCIE,CLK,SMB,PEG
Title :
Title :
Title :
Daniel Huang
Daniel Huang
Daniel Huang
Engineer:
Engineer:
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
David Lewis
David Lewis
David Lewis
1
Rev
Rev
Rev
1.3
1.3
1.3
21 99Wednesday, April 21, 2010
21 99Wednesday, April 21, 2010
21 99Wednesday, April 21, 2010
5
AUXPWROK_R
12
R2255
R2255
10KOhm
D D
10KOhm
GND
DG R1.1,page 324
For platforms that do not support Intel LAN, LAN_RST# should be
pulled down to ground via a 8.2 kΩ to 10 kΩ pull-down resistor.
PM_CLKRUN#
R1.1,item L5
+3VSUS_ORG
R2251
PM_RI#
C C
Check pull-up power plane
PM_BATLOW#
PCIE_WAKE#
ME_SusPwrDnAck
R2251
1 2
10KOhm
10KOhm
R2252
R2252
1 2
8.2KOhm
8.2KOhm
R2253
R2253
1 2
1KOhm
1KOhm
R2260
R2260
1 2
10KOhm
10KOhm
4
+3VS
R2248
R2248
1 2
8.2KOhm
8.2KOhm
+3VS
XDP_DBRESET#3,7
EDS 1.0: Intel LAN
Enabled : LAN_RST# connected to the same source as MEPWROK
Disabled : LAN_RST# must be grounded
Disabled : SLP_LAN#-->NC.
P27. Disabled : VCCLAN connected to GND.
1 2
+VTT_PCH_ORG
R2203
R2203
1%
1%
49.9Ohm
49.9Ohm
1 2
DG 1.1,page40:
1KOhm
1KOhm
R2263
R2263
D2201 1SS355D2201 1SS355
1 2
Test use only
R1.1,item L15
R1.1,item L15
3
pre-ES1 not sup port
Reversal Featur e
DMI_RXN03
DMI_RXN13
DMI_RXN23
DMI_RXN33
DMI_RXP03
DMI_RXP13
DMI_RXP23
DMI_RXP33
DMI_TXN03
DMI_TXN13
DMI_TXN23
DMI_TXN33
DMI_TXP03
DMI_TXP13
DMI_TXP23
DMI_TXP33
DMI_COMP
R1.1,item L5
+3VS
R2276
R2276
10KOhm
10KOhm
R22620Ohm @ R22620Ohm @
ALL_SYSTEM_PWRGD30,58
No Intel AMT support
H_DRAM_PWRGD3
ME_SusPwrDnAck30
PM_PWRBTN#_R7
PM_PWRBTN#30
12
VRM_PWRGD30,58,80
PM_PWROK_PCH
ME_AC_PRESENT_PCH
+3VSUS_ORG
12
@
@
R1.3,item L15
T2201T2201
T2202T2202
1 2
R22450Ohm R22450Ohm
R22460Ohm R22460Ohm
R2256
R2256
10KOhm
10KOhm
SYS_RESET#
R22430Ohm R22430Ohm
12
12
1
1
R22580Ohm @R22580Ohm @
12
R22660Ohm @R22660Ohm @
12
R22570Ohm R22570Ohm
R22650Ohm R22650Ohm
MPWROK_R
12
AUXPWROK_R
PM_RSMRST#_RPM_RSMRST#_PCH
PM_BATLOW#
PM_RI#
12
12
U2001C
U2001C
BC24
DMI0RXN
BJ22
DMI1RXN
AW20
DMI2RXN
BJ20
DMI3RXN
BD24
DMI0RXP
BG22
DMI1RXP
BA20
DMI2RXP
BG20
DMI3RXP
BE22
DMI0TXN
BF21
DMI1TXN
BD20
DMI2TXN
BE18
DMI3TXN
BD22
DMI0TXP
BH21
DMI1TXP
BC20
DMI2TXP
BD18
DMI3TXP
BH25
DMI_ZCOMP
BF25
DMI_IRCOMP
T6
SYS_RESET#
M6
SYS_PWROK
B17
PWROK
K5
MEPWROK
A10
LAN_RST#
D9
DRAMPWROK
C16
RSMRST#
M1
SUS_PWR_ACK/GPIO30
P5
PWRBTN#
P7
ACPRESENT/GPIO31
A6
BATLOW#/GPIO72
F14
RI#
IBEXPEAK-M
IBEXPEAK-M
2
DMI
DMI
System Power Management
System Power Management
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT
FDI_FSYNC0
FDI
FDI
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
WAKE#
CLKRUN#/GPIO32
SUS_STAT#/GPIO61
SUSCLK/GPIO62
SLP_S5#/GPIO63
SLP_S4#
SLP_S3#
SLP_M#
TP23
PMSYNCH
SLP_LAN#
BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12
BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12
BJ14
BF13
BH13
BJ12
BG14
J12
Y1
PM_SUS_STAT#
P8
SUS_CLK
F3
SLP_S5#
E4
SLP_S4#_R
H7
SLP_S3#_R
P12
SLP_M#_R
K8
PM_SLP_DSW#
N2
BJ10
ME_PM_SLP_LAN#_PCH
F6
R1.1,item L9
R2240 0OhmR2240 0Ohm
1 2
R2239 0OhmR2239 0Ohm
1 2
T2208T2208
1
1
T2207T2207
R1.3,item L17
PCIE_WAKE# 33,53,54
T2203T2203
1
T2204T2204
1
T2205T2205
1
R1.3,item L17
T2206T2206
1
1
FDI_TXN0 3
FDI_TXN1 3
FDI_TXN2 3
FDI_TXN3 3
FDI_TXN4 3
FDI_TXN5 3
FDI_TXN6 3
FDI_TXN7 3
FDI_TXP0 3
FDI_TXP1 3
FDI_TXP2 3
FDI_TXP3 3
FDI_TXP4 3
FDI_TXP5 3
FDI_TXP6 3
FDI_TXP7 3
FDI_INT 3
FDI_FSYNC0 3
FDI_FSYNC1 3
FDI_LSYNC0 3
FDI_LSYNC1 3
PM_CLKRUN# 30
PM_SUSC# 30
PM_SUSB# 30
PM_SYNC# 3
B B
+3VSUS_ORG
09'MoW04:
Optional if ME FW is
Ignition FW
PM_PWROK_PCH
PM_RSMRST#_PCH
ME_AC_PRESENT_PCH
A A
5
R227410KOhm@R227410KOhm
R226110KOhm R226110KOhm
@
@
1 2
1 2
1 2
Power failure solution (S0-->G3,S5-->G3):
PM_PWROK,PM_RSMRST#: previous platform solution.
ME_PWROK,ME_AC_PRESENT: reserved for test.
R227310KOhm@R227310KOhm
R2269 10KOhmR2269 10KOhm
1 2
D2205 1SS355@D2205 1SS355@
1 2
R2270 10KOhmR2270 10KOhm
1 2
D2206 1SS355@D2206 1SS355@
1 2
R2275 10KOhm@R2275 10KOhm@
1 2
D2207 1SS355D2207 1SS355
1 2
D2202
D2202
D2207: Prevent EC drive hign,
1
SUS_PWRGD sink low in S5-->G3.
3
2
BAT54C
BAT54C
D2203
D2203
1
3
2
BAT54C
BAT54C
4
SUS_PWRGD 30,58,81
R225910KOhm R225910KOhm
12
GND
PM_PWROK 30
PM_RSMRST# 30
ME_AC_PRESENT 30
3
PCH_IBEX(3)_FDI,DMI,SYS PWR
PCH_IBEX(3)_FDI,DMI,SYS PWR
PCH_IBEX(3)_FDI,DMI,SYS PWR
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
Daniel Huang
Daniel Huang
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
David Lewis
David Lewis
David Lewis
1
Daniel Huang
22 99Thursday, April 15, 2010
22 99Thursday, April 15, 2010
22 99Thursday, April 15, 2010
Rev
Rev
Rev
1.3
1.3
1.3
5
PCH_IBEX(4)_DP,LVDS,CR
PCH_IBEX(4)_DP,LVDS,CR
PCH_IBEX(4)_DP,LVDS,CR
+3VS
L_CTRL _CLK
R2322 10KO hmR 2322 10KO hm
1 2
L_CTRL _DATA
R2323 10KO hmR 2323 10KO hm
1 2
EDID_C LK_PCH
R2324 2.2KO hm
R2324 2.2KO hm
1 2
@
EDID_D AT_PCH
Switchable GFX, set EDID_DAT_PCH to high.
set CFG[4] no connect (Disable)
D D
LVDS Disable: (For discrete graphic)
1. NC:
LVDSA_DATA [3:0], LVDSA_DATA# [3:0],
LVDSA_CLK, LVDSA_CLK#, LVDSB_DATA [3:0],
LVDSB_DATA# [3:0], LVDSB_CLK, LVDSB_CLK#
L_VDD_EN, L_BKLTEN, L_BKLTCTL, LVD_VREFH
LVD_VREFL, LVD_IBG, LVD_VBG
2. Connected to GND:
VccALVDS,VccTX_LVDS
C C
CRT Disable: (For discrete graphic)
1. NC:
CRT_RED,CRT_GREEN,CRT_BLUE
CRT_HSYCN,CRT_VSYNC
2. 1-kΩ ±0.5% pull-down to GND:
DAC_IREF
3. Connected to GND:
CRT_ITRN
4. Connect to +V3.3:
VCCADAC
@
R2325 2.2KO hm
R2325 2.2KO hm
1 2
@
@
CRT_B_ PCH35
CRT_G_ PCH35
CRT_R_ PCH35
50 ohm
JP2301SHOR T_PINJP 2301SHORT _PIN
1 2
JP2302SHOR T_PINJP 2302SHORT _PIN
1 2
JP2303SHOR T_PINJP 2303SHORT _PIN
1 2
AUB Item3
ARD
ARD
1%
1%
R2317150Ohm
R2317150Ohm
R2312150Ohm
R2312150Ohm
R2316150Ohm
R2316150Ohm
12
12
12
ARD
ARD
ARD
ARD
1%
1%
1%
1%
GND
LCD_BA CKEN_PC H3 5
L_VDDE N_PCH35
L_BKLT CTL_PC H35
EDID_C LK_PCH35
EDID_D AT_PCH35
T2301T2301
T2302T2302
GND
LVDS_L CLKN_PC H3 5
LVDS_L CLKP_P CH35
LVDS_L 0N_PCH35
LVDS_L 1N_PCH35
LVDS_L 2N_PCH35
LVDS_L 0P_PCH35
LVDS_L 1P_PCH35
LVDS_L 2P_PCH35
LVDS_UC LKN_PCH35
LVDS_UC LKP_PC H35
LVDS_U0 N_PCH35
LVDS_U1 N_PCH35
LVDS_U2 N_PCH35
LVDS_U0 P_PCH35
LVDS_U1 P_PCH35
LVDS_U2 P_PCH35
37.5 ohm
DDC_CL K_PCH35
DDC_DA TA_PCH35
CRT_HSYNC_ PCH35
CRT_VS YNC_PCH35
CRB R0.9,DG R0.8: 1K+/-0.5%
Intel checklist recommand:
1.02K PD resistor to 0.5%
R2321 1KO HM0.5%R 2321 1KOHM0.5%
GND
CRT_B_ PCH_H
CRT_G_ PCH_H
CRT_R_ PCH_H
4
U2001D
U2001D
T48
L_BKLTEN
T47
L_VDD_EN
Y48
L_BKLTCTL
AB48
L_DDC_CLK
Y45
L_CTRL _CLK
1
L_CTRL _DATA
1
12
12
12
ARD
ARD
L_DDC_DATA
AB46
L_CTRL_CLK
V48
L_CTRL_DATA
R23012.37KOHM 1%ARD R23 012.37KOHM 1 %ARD
AP39
LVD_IBG
R23020O hm @ R23020Ohm @
AP41
LVD_VBG
R23030O hm
R23030O hm
AT43
LVD_VREFH
AT42
LVD_VREFL
AV53
LVDSA_CLK#
AV51
LVDSA_CLK
BB47
BA52
AY48
AV47
BB48
BA50
AY49
AV48
AP48
AP47
AY53
AU52
AY51
AU50
AA52
AB53
AD53
AD48
12
AB51
GND
AT49
AT53
AT48
AT51
V51
V53
Y53
Y51
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
IBEXPE AK-M
IBEXPE AK-M
LVDS
LVDS
CRT
CRT
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
SDVO_INTN
SDVO_INTP
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BJ46
BG46
BJ48
BG48
BF45
BH45
T51
T53
BG44
BJ44
AU38
BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38
R1.1
Y49
AB49
BE44
BD44
AV40
BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36
U50
U52
BC46
BD46
AT38
BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36
DDPB_HPD: Vil2 max=0.8V,
Vih2 min=2V
TMDS_CT RLCLK 35
TMDS_CT RLDATA 3 5
TMDS_HPD 35
HDMI_TXN2 _PCH 35
HDMI_TXP 2_PCH 3 5
HDMI_TXN1 _PCH 35
HDMI_TXP 1_PCH 3 5
HDMI_TXN0 _PCH 35
HDMI_TXP 0_PCH 3 5
HDMI_CLK N_PCH 35
HDMI_CLK P_PCH 35
3
DANIEL 1228
2
1
SDVO
Display Port BDisplay Port CDisplay Port D
B B
A A
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
David Lewis
David Lewis
David Lewis
Daniel Huang
Daniel Huang
Daniel Huang
23 99Thursday, April 15 , 2010
23 99Thursday, April 15 , 2010
23 99Thursday, April 15 , 2010
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
Size Project Name
Size Project Name
Size Project Name
D
D
D
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
Rev
Rev
Rev
1.3
1.3
1.3
5
D D
EMI
C2401
C2401
0.1UF/16V
0.1UF/16V
C C
R1.1,item L3
PCI_PME#: Internal PU to suspend plane.
change to PCI_CLK4 to sync ICS364
CLK_PCI_FB21
CLK_KBCPCI_PCH30
R1.3,item L14
LPC
PCI
Reserved
R2442
R2442
10KOhm
10KOhm
@
@
5
CLK_DEBUG44
(PCH)
1 2
R2440
R2440
1KOhm
1KOhm
@
@
1 2
DANIEL 1026
GNT3#:
+3VS
R2443
R2443
10KOhm
10KOhm
@
@
1 2
R2441
R2441
1KOhm
1KOhm
@
@
1 2
This signal has a weak pull-up
GND
C240310PF/50V@C240310PF/50V
@
1 2
GND
Low=Enabled A16 swap override/
Top-Block swap override
High=Default
PCI_GNT3#
B B
GNT0#,GNT1#: Boot BIOS Strap.
Boot BIOS Strap
PCI_GNT0#PCI_GNT1# Boot BIOS Location
0 0
0 1
1 0
1 1 SPI
Sampled on rising edge of PWROK.
PCI_GNT0#
A A
PCI_GNT1#
This signal has a weak pull-up
The internal pull-up is disabled after PCIRST#
deasserted
CLOSE TO U2001
PCI_REQ1#
12
GND
T2408T2408
1
DGPU_PWM_SELECT#_R35
T2405T2405
1
T2406T2406
T2407T2407
T2413T2413
1
RX240147Ohm RX240147Ohm
1 2
RX240447Ohm RX240447Ohm
1 2
RX240633Ohm RX240633Ohm
12
A16 swap override Strap/
Top-Block swap override jumper
R2444 1KOhm@R2444 1KOhm@
1 2
4
U2001E
U2001E
H40
AD0
N34
AD1
C44
AD2
A38
AD3
C36
AD4
J34
AD5
A40
AD6
D45
AD7
E36
AD8
H48
AD9
E40
AD10
C40
AD11
M48
AD12
M45
AD13
F53
AD14
M40
AD15
M43
AD16
J36
AD17
K48
AD18
F40
AD19
C42
AD20
K46
AD21
M51
AD22
J52
AD23
K51
AD24
L34
AD25
F42
AD26
J40
AD27
G46
AD28
F44
AD29
M47
AD30
H36
AD31
J50
C/BE0#
G42
C/BE1#
H47
C/BE2#
G34
PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#
PCI_REQ0#
PCI_REQ1#
PCI_REQ3#
PCI_GNT0#
PCI_GNT1#
DGPU_PWM_SELECT#_R
PCI_GNT3#
PCI_INTE#
PCI_INTF#
PCI_INTG#
PCI_INTH#
PCI_RST#
PCI_SERR#
PCI_PERR#
PCI_IRDY#
PCI_PAR
1
PCI_DEVSEL#
PCI_FRAME#
PCI_LOCK#
PCI_STOP#
PCI_TRDY# USBRBIAS_PN
PCI_PME#
1
PLT_RST#
CLK_DBGPCI2_R
CLK_PCI_FB_R
CLK_KBCPCI_PCH_R
CLK_DEBUG_R
G38
H51
B37
A44
F51
A46
B45
M53
F48
K45
F36
H53
B41
K53
A36
A48
K6
E44
E50
A42
H44
F46
C46
D49
D41
C48
M7
D5
N52
P53
P46
P51
P48
C/BE3#
PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ0#
REQ1#/GPIO50
REQ2#/GPIO52
REQ3#/GPIO54
GNT0#
GNT1#/GPIO51
GNT2#/GPIO53
GNT3#/GPIO55
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
PCIRST#
SERR#
PERR#
IRDY#
PAR
DEVSEL#
FRAME#
PLOCK#
STOP#
TRDY#
PME#
PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
IBEXPEAK-M
IBEXPEAK-M
PCI
PCI
NV_DQ0/NV_IO0
NV_DQ1/NV_IO1
NV_DQ2/NV_IO2
NV_DQ3/NV_IO3
NV_DQ4/NV_IO4
NV_DQ5/NV_IO5
NV_DQ6/NV_IO6
NV_DQ7/NV_IO7
NV_DQ8/NV_IO8
NV_DQ9/NV_IO9
NV_DQ10/NV_IO10
NV_DQ11/NV_IO11
NVRAM
NVRAM
NV_DQ12/NV_IO12
NV_DQ13/NV_IO13
NV_DQ14/NV_IO14
NV_DQ15/NV_IO15
NV_WR#0_RE#
NV_WR#1_RE#
USB
USB
NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3
NV_DQS0
NV_DQS1
NV_ALE
NV_CLE
NV_RCOMP
NV_RB#
NV_WE#_CK0
NV_WE#_CK1
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
AY9
BD1
AP15
BD8
AV9
BG8
AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6
BD3
AY6
AU2
AV7
AY8
AY5
AV11
BF5
H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24
B25
D25
N16
J16
F16
L16
E14
G16
F12
T15
R1.2,item L1
GND
4
3
Place within 500 mils of PCH
USB_PN0 54
USB_PP0 54
USB_PN1 54
USB_PP1 54
USB_PN2 49
USB_PP2 49
USB_PN3 52
USB_PP3 52
USB_PN4 64
USB_PP4 64
USB_PN5 52
USB_PP5 52
Port 6,7 not avalibale in HM55
USB_PN8 53
USB_PP8 53
USB_PN9 55
USB_PP9 55
USB_PN11 52
USB_PP11 52
USB_PN12 61
USB_PP12 61
1 2
3
10
11
12
13
R2411
R2411
22.6Ohm 1%
22.6Ohm 1%
0
1
2
3
4
5
6
7
8
9
CHECK USB ASSIGNMENT
David Lewis Recommand settings
USB port (USB 3.0)
USB port (USB 3.0)
eSATA
USB port
TV Tuner
ELAN TEK USB
WiFi/WiMax
Camera
Card Reader(2.0)
LCM(2.0) or UWB(1.1/2.0)
3G
USB port (5th) or Docking
BT (1.1)
Place within 500 mils of ICH
GND
5 6
10KOHM
10KOHM
3 4
10KOHM
10KOHM
7 8
10KOHM
10KOHM
3 4
10KOHM
10KOHM
5 6
10KOHM
10KOHM
7 8
10KOHM
10KOHM
1 2
10KOHM
10KOHM
1 2
10KOHM
10KOHM
RN2407C
RN2407C
RN2408B
RN2408B
RN2408D
RN2408D
RN2407B
RN2407B
RN2408C
RN2408C
RN2407D
RN2407D
RN2407A
RN2407A
RN2408A
RN2408A
2
+3VSUS_ORG
R1.1,item L5
2
PLT_RST#
1
2
3 4
GND
R2413 0Ohm@R2413 0Ohm@
U2401
U2401
A
A
VCC
VCC
B
B
GND
GND
Y
Y
NC7SZ08P5X_NL
NC7SZ08P5X_NL
1 2
1
PCI_INTC#
PCI_INTA#
PCI_INTE#
PCI_STOP#
PCI_INTD#
PCI_SERR#
PCI_DEVSEL#
PCI_LOCK#
PCI_INTG#
PCI_IRDY#
PCI_REQ1#
PCI_REQ0#
PCI_INTB#
PCI_INTF#
PCI_REQ3#
PCI_TRDY#
PCI_INTH#
PCI_PERR#
PCI_FRAME#
+3V
5
BUF_PLT_RST# 3,7,30,32,33,45,53,54,64,70
Title :
Title :
Title :
Engineer:
Engineer:
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Engineer:
David Lewis
David Lewis
David Lewis
1
+3VS
RP2401A
RP2401A
1 5
10KOhm
10KOhm
RP2401B
RP2401B
RP2401C
RP2401C
RP2401D
RP2401D
RP2403G
RP2403G
RP2401F
RP2401F
RP2401G
RP2401G
RP2401H
RP2401H
RP2401E
RP2401E
RP2403H
RP2403H
RP2403A
RP2403A
RP2402A
RP2402A
RP2402B
RP2402B
RP2402C
RP2402C
RP2402D
RP2402D
RP2403C
RP2403C
RP2403D
RP2403D
RP2403E
RP2403E
RP2403F
RP2403F
RP2403B
RP2403B
RP2402F
RP2402F
RP2402G
RP2402G
RP2402H
RP2402H
RP2402E
RP2402E
10
2 5
10KOhm
10KOhm
10
3 5
10KOhm
10KOhm
10
4 5
10KOhm
10KOhm
10
8 5
10KOhm
10KOhm
10
7 5
10KOhm
10KOhm
10
8 5
10KOhm
10KOhm
10
9 5
10KOhm
10KOhm
10
6 5
10KOhm
10KOhm
10
9 5
10KOhm
10KOhm
10
1 5
10KOhm
10KOhm
10
1 5
10KOhm
10KOhm
10
2 5
10KOhm
10KOhm
10
3 5
10KOhm
10KOhm
10
4 5
10KOhm
10KOhm
10
3 5
10KOhm
10KOhm
10
4 5
10KOhm
10KOhm
10
6 5
10KOhm
10KOhm
10
7 5
10KOhm
10KOhm
10
2 5
10KOhm
10KOhm
10
7 5
10KOhm
10KOhm
10
8 5
10KOhm
10KOhm
10
9 5
10KOhm
10KOhm
10
6 5
10KOhm
10KOhm
10
PCH_IBEX(5)_PCI,NVRAM,USB
PCH_IBEX(5)_PCI,NVRAM,USB
PCH_IBEX(5)_PCI,NVRAM,USB
Daniel Huang
Daniel Huang
Daniel Huang
24 99Thursday, April 15, 2010
24 99Thursday, April 15, 2010
24 99Thursday, April 15, 2010
Rev
Rev
Rev
1.3
1.3
1.3
5
4
3
2
1
+3VS
+3VS
+3VS
12
12
R2536
R2536
R2538
10KOhm
10KOhm
R2535
R2535
10KOhm
10KOhm
R2538
@
@
10KOhm
10KOhm
PCB_ID0
PCB_ID1
12
R2537
R2537
10KOhm
10KOhm
GND
@
D D
R1.3,item L7
C C
@
12
GND
12
R2540
R2540
10KOhm
10KOhm
R1.2,item B1
USB3_SMI#
GPIO 27:Enable VCCVRM,Low=disable.
Default internal pull up.
GPIO 28: Default internal PU 20K.
USB3_SMI#54
GPIO 15: Default internal PD 20K.
WLAN_ON#53
dGPU_PWR_EN#_GPIO3635
T2600T2600
1
T2592T2592
1
R1.3,item L2
dGPU_HOLD_RST#35
DGPU_PWROK21,79
WLAN_LED31
USB20_SEL54
R1.3,item L7
dGPU_PRSNT#35
EXT_SMI#30
T2595T2595
GPIO0
T2596T2596
1
GPIO1
T2590T2590
1
DGPU_HPD_INTR#_R
USB3_SMI#
1
BT_ON61
PM_LANPHY_EN
1
1
DGPU_PWROK
VRM_EN
1
R1.3,item L1
1
DGPU_PRSNT#
PCB_ID0
PCB_ID1
CLK_REQ6#
1
CLK_REQ7#
1
EMAIL_LED
1
R25040Ohm R25040Ohm
12
STP_PCI#
SATA_CLK_REQ#
T2593T2593
T2591T2591
T2548T2548
T2578T2578
T2597T2597
T2598T2598
T2599T2599
PCH_TEMP_ALERT#30,32
R1.1,item L5
+3VSUS_ORG
EXT_SMI#
CLK_REQ6#
CLK_REQ7#
PM_LANPHY_EN
PCH XDP
R1.2,item B1
B B
R1.3,item L1
dGPU_PWR_EN#_GPIO36
PCH_TEMP_ALERT#
DGPU_HPD_INTR#_R
GPIO0
GPIO1
STP_PCI#
EMAIL_LED
R253210KOhm R253210KOhm
12
R253410KOhm R253410KOhm
12
R253910KOhm R253910KOhm
12
R254110KOhm@R254110KOhm
12
@
+3VS
R255010KOhm@R255010KOhm
12
@
R254910KOhm R254910KOhm
12
R254810KOhm R254810KOhm
12
R254410KOhm R254410KOhm
12
R254510KOhm R254510KOhm
12
R254610KOhm R254610KOhm
12
R254710KOhm R254710KOhm
12
2
4
5
3
U2001F
U2001F
Y3
BMBUSY#/GPIO0
C38
TACH1/GPIO1
D37
TACH2/GPIO6
J32
TACH3/GPIO7
F10
GPIO8
K9
LAN_PHY_PWR_CTRL/GPIO12
T7
GPIO15
AA2
SATA4GP/GPIO16
F38
TACH0/GPIO17
Y7
SCLOCK/GPIO22
H10
MEM_LED/GPIO24
AB12
GPIO27
V13
GPIO28
M11
STP_PCI#/GPIO34
V6
SATACLKREQ#/GPIO35
AB7
SATA2GP/GPIO36
AB13
SATA3GP/GPIO37
V3
SLOAD/GPIO38
P3
SDATAOUT0/GPIO39
H3
PCIECLKRQ6#/GPIO45
F1
PCIECLKRQ7#/GPIO46
AB6
SDATAOUT1/GPIO48
AA4
SATA5GP/GPIO49
F8
GPIO57
A4
VSS_NCTF_1
A49
VSS_NCTF_2
A5
VSS_NCTF_3
A50
VSS_NCTF_4
A52
VSS_NCTF_5
A53
VSS_NCTF_6
B2
VSS_NCTF_7
B4
VSS_NCTF_8
B52
VSS_NCTF_9
B53
VSS_NCTF_10
BE1
VSS_NCTF_11
BE53
VSS_NCTF_12
BF1
VSS_NCTF_13
BF53
VSS_NCTF_14
BH1
VSS_NCTF_15
BH2
VSS_NCTF_16
BH52
VSS_NCTF_17
BH53
VSS_NCTF_18
BJ1
VSS_NCTF_19
BJ2
VSS_NCTF_20
BJ4
VSS_NCTF_21
BJ49
VSS_NCTF_22
BJ5
VSS_NCTF_23
BJ50
VSS_NCTF_24
BJ52
VSS_NCTF_25
BJ53
VSS_NCTF_26
D1
VSS_NCTF_27
D2
VSS_NCTF_28
D53
VSS_NCTF_29
E1
VSS_NCTF_30
E53
VSS_NCTF_31
IBEXPEAK-M
IBEXPEAK-M
MISC
MISC
CLKOUT_BCLK0_N/CLKOUT_PCIE8N
CLKOUT_BCLK0_P/CLKOUT_PCIE8P
GPIO
GPIO
CPU
CPU
NCTF
NCTF
RSVD
RSVD
CLKOUT_PCIE6N
CLKOUT_PCIE6P
CLKOUT_PCIE7N
CLKOUT_PCIE7P
A20GATE
PECI
RCIN#
PROCPWRGD
THRMTRIP#
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
NC_1
NC_2
NC_3
NC_4
NC_5
INIT3_3V#
TP24
AH45
AH46
AF48
AF47
U2
AM3
AM1
BG10
T1
BE10
BD10
BA22
TP1
AW22
TP2
BB22
TP3
AY45
TP4
AY46
TP5
AV43
TP6
AV45
TP7
AF13
TP8
M18
TP9
N18
AJ24
AK41
AK42
M32
N32
M30
N30
H12
AA23
AB45
AB38
AB42
AB41
T39
P6
TP_PCH_SST
C10
INT3_3V#
R2523
R2523
1 2
0Ohm
0Ohm
PM_THRMTRIP#
T2588T2588
1
T2589T2589
1
T2582T2582
1
T2584T2584
1
T2583T2583
1
T2585T2585
1
T2587T2587
1
T2586T2586
1
T2580T2580
1
T2581T2581
1
T2579T2579
1
T2577T2577
1
A20GATE 30
BCLK_CPU_N_PCH 3
BCLK_CPU_P_PCH 3
H_PECI 3
RCIN# 30
H_CPUPWRGD 3,7
+VTT_CPU
R2525
R2525
56OHM
56OHM
CHECK HERE
1 2
R2501
R2501
@
@
1 2
56OHM
56OHM
R1.2,item B1 08'WW46 MoW
H_THRMTRIP# 3,32
DGPU_PWROK
SATA_CLK_REQ#
R1.2,item B1 08'WW50 MoW
A A
R2533 10KOhmR2533 10KOhm
R2531 10KOhmR2531 10KOhm
12
12
5
GND
PCH_IBEX(6)CPU,GPIO,MISC
PCH_IBEX(6)CPU,GPIO,MISC
PCH_IBEX(6)CPU,GPIO,MISC
Title :
Title :
Title :
Daniel Huang
Daniel Huang
Daniel Huang
Engineer:
Engineer:
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet
Date: Sheet of
4
3
2
Date: Sheet of
Engineer:
David Lewis
David Lewis
David Lewis
1
Rev
Rev
Rev
1.3
1.3
1.3
of
25 99Thursday, April 15, 2010
25 99Thursday, April 15, 2010
25 99Thursday, April 15, 2010
5
U2001H
U2001H
AB16
VSS[0]
AA19
VSS[1]
AA20
VSS[2]
AA22
VSS[3]
AM19
VSS[4]
AA24
VSS[5]
AA26
VSS[6]
AA28
VSS[7]
AA30
VSS[8]
AA31
VSS[9]
AA32
VSS[10]
AB11
VSS[11]
AB15
VSS[12]
AB23
VSS[13]
D D
C C
B B
AB30
VSS[14]
AB31
VSS[15]
AB32
VSS[16]
AB39
VSS[17]
AB43
VSS[18]
AB47
VSS[19]
AB5
VSS[20]
AB8
VSS[21]
AC2
VSS[22]
AC52
VSS[23]
AD11
VSS[24]
AD12
VSS[25]
AD16
VSS[26]
AD23
VSS[27]
AD30
VSS[28]
AD31
VSS[29]
AD32
VSS[30]
AD34
VSS[31]
AU22
VSS[32]
AD42
VSS[33]
AD46
VSS[34]
AD49
VSS[35]
AD7
VSS[36]
AE2
VSS[37]
AE4
VSS[38]
AF12
VSS[39]
Y13
VSS[40]
AH49
VSS[41]
AU4
VSS[42]
AF35
VSS[43]
AP13
VSS[44]
AN34
VSS[45]
AF45
VSS[46]
AF46
VSS[47]
AF49
VSS[48]
AF5
VSS[49]
AF8
VSS[50]
AG2
VSS[51]
AG52
VSS[52]
AH11
VSS[53]
AH15
VSS[54]
AH16
VSS[55]
AH24
VSS[56]
AH32
VSS[57]
AV18
VSS[58]
AH43
VSS[59]
AH47
VSS[60]
AH7
VSS[61]
AJ19
VSS[62]
AJ2
VSS[63]
AJ20
VSS[64]
AJ22
VSS[65]
AJ23
VSS[66]
AJ26
VSS[67]
AJ28
VSS[68]
AJ32
VSS[69]
AJ34
VSS[70]
AT5
VSS[71]
AJ4
VSS[72]
AK12
VSS[73]
AM41
VSS[74]
AN19
VSS[75]
AK26
VSS[76]
AK22
VSS[77]
AK23
VSS[78]
AK28
VSS[79]
IBEXPEAK-M
IBEXPEAK-M
GND GND
+VTT_PCH_1.5VS_1.8VS
+1.5VS
+1.8VS
+VTT_PCH_ORG
R2619 0Ohm@R2619 0Ohm@
R2620 0OhmR2620 0Ohm
R2646 0Ohm@R2646 0Ohm@
12
12
12
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47
R2617 0OhmR2617 0Ohm
R2613 0OhmR2613 0Ohm
+VTT_PCH
+VTT_PCH_ORG
+VCCAFDI_VRM
12
+1.8VS_VCCADMI_VRM
12
3MM_OPEN_5MIL
3MM_OPEN_5MIL
1MM_OPEN_5MIL
1MM_OPEN_5MIL
2MM_OPEN_5MIL
2MM_OPEN_5MIL
JP2601
JP2601
112
JP2602
JP2602
2
JP2603
JP2603
112
2
112
2
4
5.172A
1.524A
S0 max
3.208A
S0 max
+VTT_PCH_ORG
+VTT_PCH_VCCIO
+VTT_PCH_ORG
+VTT_PCH_VCC
+VTT_PCH_VCCIO
+VTT_PCH_ORG
L2605 1KOhm/100MhzL2605 1KOhm/100Mhz
2 1
+VTT_PCH_VCCDPLL_FDI
0Ohm
0Ohm
12
R2606
R2606
+VTT_PCH_VCCIO
L2601 1KOhm/100Mhz
L2601 1KOhm/100Mhz
+VTT_PCH_VCCIO
+VTT_PCH_VCCAPLL_FDI
12
C2608
C2608
10UF/6.3V
10UF/6.3V
GND
+VTT_PCH_VCCDPLL_EXP
0Ohm
0Ohm
12
R2602
R2602
2 1
@
@
+VTT_PCH_VCC_EXP
12
12
C2607
C2607
C2606
C2606
1UF/6.3V
1UF/6.3V
10UF/6.3V
10UF/6.3V
+VCCAFDI_VRM
3
+VTT_PCH_VCC
+VTT_PCH_VCCDPLL_EXP
@ C2602
@
12
12
12
C2603
C2603
C2604
C2604
C2605
C2605
1UF/6.3V
1UF/6.3V
1UF/6.3V
1UF/6.3V
GND
+3VS
1.524A
S0 max
12
C2650
C2650
10UF/6.3V
10UF/6.3V
GND
+VTT_PCH_VCCAPLL_EXP
2mA
S0 idle
12
C2602
10UF/6.3V
10UF/6.3V
GND
1UF/6.3V
1UF/6.3V
+3VS_VCCA3GBG
0Ohm
0Ohm
1 2
R2618
R2618
GND
12
C2601
C2601
1UF/6.3V
1UF/6.3V
AB24
AB26
AB28
AD26
AD28
AF26
AF28
AF30
AF31
AH26
AH28
AH30
AH31
AJ30
AJ31
AK24
BJ24
AN20
AN22
AN23
AN24
AN26
AN28
BJ26
BJ28
AT26
AT28
AU26
AU28
AV26
AV28
AW26
AW28
BA26
BA28
BB26
BB28
BC26
BC28
BD26
BD28
BE26
BE28
BG26
BG28
BH27
AN30
AN31
AN35
AT22
BJ18
AM23
U2001G
U2001G
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCIO[24]
VCCAPLLEXP
VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
VCCIO[50]
VCCIO[51]
VCCIO[52]
VCCIO[53]
VCCIO[54]
VCCIO[55]
VCC3_3[1]
VCCVRM[1]
VCCFDIPLL
VCCIO[1]
IBEXPEAK-M
IBEXPEAK-M
POWER
POWER
VCC CORE
VCC CORE
PCI E*
PCI E*
FDI
FDI
DMI
DMI
NAND / SPI
NAND / SPI
CRTLVDS
CRTLVDS
HVCMOS
HVCMOS
2
VCCADAC[1]
VCCADAC[2]
VSSA_DAC[1]
VSSA_DAC[2]
VCCALVDS
VSSA_LVDS
VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]
VCC3_3[2]
VCC3_3[3]
VCC3_3[4]
VCCVRM[2]
VCCDMI[1]
VCCDMI[2]
VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]
VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]
69mA
S0 max
AE50
AE52
AF53
AF51
AH38
AH39
AP43
AP45
AT46
AT45
AB34
AB35
AD35
AT24
AT16
AU16
AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15
AM8
AM9
AP11
AP9
+V_NVRAM_VCCQ
300mA
S0 max
GND
59mA
59mA
S0 max
S0 max
GND
12
C2611
ARD C2611
ARD
0.01UF/16V
0.01UF/16V
GND GND GND
357mA
S0 max
12
C2613
C2613
0.1UF/16V
0.1UF/16V
GND
+1.8VS_VCCADMI_VRM
+VTT_CPU_VCC_DMI
61mA
S0 max
12
C2648
C2648
1UF/6.3V
1UF/6.3V
GND
156mA
S0 max
12
C2614
C2614
0.1UF/16V
0.1UF/16V
+3VM_VCCPEP
GND
12
C2615
C2615
0.1UF/16V
0.1UF/16V
GND
R2621 0OhmR2621 0Ohm
R2622 0Ohm@R2622 0Ohm@
+VCCA_DAC_1_2
12
12
R2607
R2607
C2609
C2609
ARD
ARD
ARD
ARD
@
@
0Ohm
0Ohm
0.01UF/16V
0.01UF/16V
+3VS_VCCA_LVDS
0Ohm
0Ohm
12
R2601
R2601
0OhmCFD
0OhmCFD
GND
12
C2612
ARD C2612
ARD
0.01UF/16V
0.01UF/16V
+V_NVRAM_VCCPNAND
85mA
S0 max
12
12
12
C2616
C2616
ARD
ARD
0.1UF/16V
0.1UF/16V
GND
ARD
ARD
+1.8VS_VCCT_LVD
+3VS_VCC_GIO
R2614
R2614
1 2
0Ohm
0Ohm
0Ohm
0Ohm
1 2
R2643
R2643
@
@
R2615
R2615
1 2
0Ohm
0Ohm
R2616
R2616
1 2
0Ohm
0Ohm
+1.8VS
+3VS
12
C2610
C2610
10UF/6.3V
10UF/6.3V
GNDGNDGND
R2610
R2610
12
ARD C2649
ARD
R2611
R2611
1 2
0Ohm
0Ohm
L2611 1KOhm/100MhzL2611 1KOhm/100Mhz
21
L2610
L2610
21
@
@
1KOhm/100Mhz
1KOhm/100Mhz
+3VS
12
C2649
22UF/6.3V
22UF/6.3V
+3VS
+VTT_CPU
+V_NVRAM_VCCQ
check power plane
1
12
0Ohm
0Ohm
CFD
CFD
R2644
R2644
GND
R1.2,item L2
+VTT_PCH_ORG
+3VSUS_ORG
+3VS
+1.5VS
+1.8VS
L26081KOhm/100Mhz
L26081KOhm/100Mhz
21
ARD
ARD
R1.3,item L10
A A
PCH_IBEX(7)_POWER,GND
PCH_IBEX(7)_POWER,GND
PCH_IBEX(7)_POWER,GND
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
Daniel Huang
Daniel Huang
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet of
Wednesday, April 07, 2010
Date: Sheet of
Wednesday, April 07, 2010
Date: Sheet of
5
4
3
2
Wednesday, April 07, 2010
David Lewis
David Lewis
David Lewis
1
Daniel Huang
26 99
26 99
26 99
Rev
Rev
Rev
1.3
1.3
1.3
U2001I
U2001I
AY7
VSS[159]
B11
VSS[160]
B15
VSS[161]
B19
VSS[162]
B23
VSS[163]
B31
VSS[164]
B35
VSS[165]
B39
VSS[166]
B43
VSS[167]
B47
VSS[168]
B7
VSS[169]
BG12
VSS[170]
BB12
VSS[171]
BB16
VSS[172]
BB20
VSS[173]
BB24
VSS[174]
BB30
D D
C C
B B
A A
+VTT_PCH_VCCA_B_DPL
VSS[175]
BB34
VSS[176]
BB38
VSS[177]
BB42
VSS[178]
BB49
VSS[179]
BB5
VSS[180]
BC10
VSS[181]
BC14
VSS[182]
BC18
VSS[183]
BC2
VSS[184]
BC22
VSS[185]
BC32
VSS[186]
BC36
VSS[187]
BC40
VSS[188]
BC44
VSS[189]
BC52
VSS[190]
BH9
VSS[191]
BD48
VSS[192]
BD49
VSS[193]
BD5
VSS[194]
BE12
VSS[195]
BE16
VSS[196]
BE20
VSS[197]
BE24
VSS[198]
BE30
VSS[199]
BE34
VSS[200]
BE38
VSS[201]
BE42
VSS[202]
BE46
VSS[203]
BE48
VSS[204]
BE50
VSS[205]
BE6
VSS[206]
BE8
VSS[207]
BF3
VSS[208]
BF49
VSS[209]
BF51
VSS[210]
BG18
VSS[211]
BG24
VSS[212]
BG4
VSS[213]
BG50
VSS[214]
BH11
VSS[215]
BH15
VSS[216]
BH19
VSS[217]
BH23
VSS[218]
BH31
VSS[219]
BH35
VSS[220]
BH39
VSS[221]
BH43
VSS[222]
BH47
VSS[223]
BH7
VSS[224]
C12
VSS[225]
C50
VSS[226]
D51
VSS[227]
E12
VSS[228]
E16
VSS[229]
E20
VSS[230]
E24
VSS[231]
E30
VSS[232]
E34
VSS[233]
E38
VSS[234]
E42
VSS[235]
E46
VSS[236]
E48
VSS[237]
E6
VSS[238]
E8
VSS[239]
F49
VSS[240]
F5
VSS[241]
G10
VSS[242]
G14
VSS[243]
G18
VSS[244]
G2
VSS[245]
G22
VSS[246]
G32
VSS[247]
G36
VSS[248]
G40
VSS[249]
G44
VSS[250]
G52
VSS[251]
AF39
VSS[252]
H16
VSS[253]
H20
VSS[254]
H30
VSS[255]
H34
VSS[256]
H38
VSS[257]
H42
VSS[258]
IBEXPEAK-M
IBEXPEAK-M
+VTT_PCH_VCCA_A_DPL
5
+VTT_PCH_VCCA_A_DPL
+VTT_PCH_VCCA_A_DPL
0Ohm
0Ohm
R2748
R2748
@
@
12
GND
12
GND
5
12
+VTT_PCH_VCCA_B_DPL
C2746
C2746
1UF/6.3V
1UF/6.3V
C2747
C2747
1UF/6.3V
1UF/6.3V
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]
12
+
+
CE2703
CE2703
@
@
220UF/4V
220UF/4V
ESR=40mOhm/Ir=1.9A
ESR=40mOhm/Ir=1.9A
GND
12
+
+
CE2704
CE2704
@
@
220UF/4V
220UF/4V
ESR=40mOhm/Ir=1.9A
ESR=40mOhm/Ir=1.9A
GND
H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14
1.998A+344mA
S0 max
+1.05VS +1.05VM_ORG
JP2701
JP2701
2
112
2MM_OPEN_5MIL
2MM_OPEN_5MIL
+3VS +3VS_VCC3_3
JP2702
JP2702
2
112
1MM_OPEN_5MIL
1MM_OPEN_5MIL
+3VSUS +3VSUS_ORG
JP2703
JP2703
2
112
1MM_OPEN_5MIL
1MM_OPEN_5MIL
+5VSUS +5VSUS_ORG
JP2704
JP2704
2
112
1MM_OPEN_5MIL
1MM_OPEN_5MIL
R1.1,item L5
GNDGND
+VTT_PCH_ORG
L2706
L2706
21
1KOhm/100Mhz
1KOhm/100Mhz
?
L2707
L2707
21
1KOhm/100Mhz
1KOhm/100Mhz
?
4
R1.3,item L17
357mA
S0 max
200mA
S0 max
R2742 0OhmR2742 0Ohm
1 2
+VTT_CPU
4
+VTT_PCH_ORG
+1.05VM_ORG
Disable Intel LAN
+1.05VM_ORG
+VTT_PCH_1.5VS_1.8VS+VCCPLLVRM
+VTT_PCH_VCCIO
R1.1,item L5
R2728 0OhmR2728 0Ohm
12
L2704 1KOhm/100Mhz
L2704 1KOhm/100Mhz
2 1
@
@
344mA
12
S0 max
GND
R2722
R2722
0Ohm
0Ohm
@
@
S0 max
12
C2702
C2701
C2701
22UF/6.3V
22UF/6.3V
C2722
C2722
0.1UF/16V
0.1UF/16V
+VTT_PCH_SSCVCC
+VTT_CPU_VCCPCPU
C2702
22UF/6.3V
22UF/6.3V
12
+VTT_PCH_VCCA_A_DPL
GND
+VTT_PCH_VCCA_B_DPL
12
C2729
C2729
1UF/6.3V
1UF/6.3V
GND
+3VSUS_ORG
R2726 0OhmR2726 0Ohm
+3VS_VCC3_3
>1mA
S0 max
12
C2752
C2752
4.7UF/6.3V
4.7UF/6.3V
+VCC_RTC
GND
52mA
S0 max
12
12
@
@
@
@
C2718
C2718
10UF/6.3V
10UF/6.3V
GND
12
R2724
R2724
0Ohm
0Ohm
C2751
C2751
GND
0.1UF/16V
0.1UF/16V
+1.1VM_VCCEPW
12
GNDGND
DCPRTC
+VTT_PCH_1.5VS_1.8VS
12
C2723
C2723
1UF/6.3V
1UF/6.3V
GND
12
C2725
C2725
0.1UF/16V
0.1UF/16V
GND
12
+3VS_VCCPCORE
12
C2731
C2731
0.1UF/16V
0.1UF/16V
GND
2mA
S0 max
12
C2733
C2733
0.1UF/16V
0.1UF/16V
GND
3
+VTT_PCH_VCCA_CLK
C2717
C2717
1UF/6.3V
1UF/6.3V
+1.05VM_VCCAUX
GND
GND
12
C2721
C2721
1UF/6.3V
1UF/6.3V
GND
72mA
S0 max
73mA
S0 max
12
C2724
C2724
1UF/6.3V
1UF/6.3V
GND
+VCCSST
+V1.05A_INT_VCCSUS
12
+3VA_VCCPSUS
12
C2727
C2727
0.1UF/16V
0.1UF/16V
GND
12
C2728
C2728
0.1UF/16V
0.1UF/16V
GND
GND
GND
3
TP_PCH_VCCDSW
12
12
C2720
C2720
1UF/6.3V
1UF/6.3V
C2726
C2726
0.1UF/16V
0.1UF/16V
GND
12
C2730
C2730
0.1UF/16V
0.1UF/16V
12
C2732
C2732
0.1UF/16V
0.1UF/16V
AP51
AP53
AF23
AF24
AD38
AD39
AD41
AF43
AF41
AF42
AU24
BB51
BB53
BD51
BD53
AH23
AH35
AF34
AH34
AF32
AT18
AU18
Y20
V39
V41
V42
Y39
Y41
Y42
AJ35
V12
Y22
P18
U19
U20
U22
V15
V16
Y16
A12
U2001J
U2001J
VCCACLK[1]
VCCACLK[2]
VCCLAN[1]
VCCLAN[2]
DCPSUSBYP
VCCME[1]
VCCME[2]
VCCME[3]
VCCME[4]
VCCME[5]
VCCME[6]
VCCME[7]
VCCME[8]
VCCME[9]
VCCME[10]
VCCME[11]
VCCME[12]
V9
DCPRTC
VCCVRM[3]
VCCADPLLA[1]
VCCADPLLA[2]
VCCADPLLB[1]
VCCADPLLB[2]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[2]
VCCIO[3]
VCCIO[4]
DCPSST
DCPSUS
VCCSUS3_3[29]
VCCSUS3_3[30]
VCCSUS3_3[31]
VCCSUS3_3[32]
VCC3_3[5]
VCC3_3[6]
VCC3_3[7]
V_CPU_IO[1]
V_CPU_IO[2]
VCCRTC
IBEXPEAK-M
IBEXPEAK-M
POWER
POWER
Clock and Miscellaneous
Clock and Miscellaneous
CPU
CPU
RTC PCI/GPIO/LPC
RTC PCI/GPIO/LPC
USB
USB
PCI/GPIO/LPC
PCI/GPIO/LPC
SATA
SATA
HDA
HDA
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]
VCCSUS3_3[28]
VCCIO[56]
V5REF_SUS
V5REF
VCC3_3[8]
VCC3_3[9]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]
VCCSATAPLL[1]
VCCSATAPLL[2]
VCCIO[9]
VCCVRM[4]
VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]
VCCSUSHDA
V24
V26
Y24
Y26
V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26
U23
V23
F24
K49
J38
L38
M36
N36
P36
U35
AD13
AK3
AK1
AH22
AT20
AH19
AD20
AF22
AD19
AF20
AF19
AH20
AB19
AB20
AB22
AD22
AA34
Y34
Y35
AA35
L30
2
2
12
GND
+VCCPLLVRM
10mil trace at least
+VTT_PCH_VCCUSBCORE
12
C2734
C2734
1UF/6.3V
1UF/6.3V
+3VSUS_VCCPUSB
GND
163mA
S0 max
12
C2735
C2735
0.1UF/16V
0.1UF/16V
GND
CLOSE TO U2001
EMI
C2737
C2737
0.1UF/16V
0.1UF/16V
+5VSUS_PCH_VCC5REFSUS
+5VS_PCH_VCC5REF
12
C2739
C2739
1UF/6.3V
1UF/6.3V
GND
12
C2740
C2740
0.1UF/16V
0.1UF/16V
GND
12
C2741
C2741
0.1UF/16V
0.1UF/16V
GND
+VTT_PCH_VCC_SATA
12
C2745
C2745
1UF/6.3V
1UF/6.3V
GND
+VTT_PCH_VCCIO
R2730 0OhmR2730 0Ohm
1 2
R1.1,item L5
+3VSUS_ORG+VTT_PCH_VCCIO
12
C2750
C2750
0.1UF/16V
0.1UF/16V
GND
+3VS_VCCPPCI
+VTT_PCH_VCCAPLL
12
C2744
C2744
1UF/6.3V
1UF/6.3V
GND
CLOSE TO U2001
EMI
12
C2753
C2753
0.1UF/16V
0.1UF/16V
GND
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
Date: Sheet of
Date: Sheet of
Date: Sheet of
R1.1,item L5
1
2
D2701
D2701
BAT54C
BAT54C
3
+3VS_VCC3_3
+3VS_VCC3_3
12
@
@
GND
+3VSUS_HDA +3VSUS_ORG
Size Project Name
Size Project Name
Size Project Name
C
C
C
Wednesday, April 07, 2010
Wednesday, April 07, 2010
Wednesday, April 07, 2010
+5VSUS_ORG
R2731
R2731
1 2
12
100Ohm
100Ohm
C2738
C2738
1UF/6.3V
1UF/6.3V
GND
1KOhm/100Mhz
1KOhm/100Mhz
12
@
@
C2742
C2743
C2743
10UF/6.3V
10UF/6.3V
C2742
10UF/6.3V
10UF/6.3V
GND
R2749 0OhmR2749 0Ohm
1 2
1
EMI
12
C2748
C2748
0.1UF/16V
0.1UF/16V
GND
2
R1.2,item L5
L2705
L2705
21
@
@
+1.05VM_ORG
R1.1,item L5
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
David Lewis
David Lewis
David Lewis
1
R1.1,item L5
+3VSUS_ORG
12
C2749
C2749
0.1UF/16V
0.1UF/16V
+3VS
1
D2702
D2702
BAT54C
BAT54C
DG R1.11 P.11:
3
R2732
R2732
1 2
100Ohm
100Ohm
+VTT_PCH_ORG
+VTT_PCH_VCCIO
PCH_IBEX(8)_POWER,GND
PCH_IBEX(8)_POWER,GND
PCH_IBEX(8)_POWER,GND
Daniel Huang
Daniel Huang
Daniel Huang
27 99
27 99
27 99
+5VS
Rev
Rev
Rev
1.3
1.3
1.3
5
4
3
2
1
PCH SPI ROM
R1.2,item L6
D D
12G06100008K
12G06100008K
+3VSUS_ORG
J2802
J2802
1
SPI_CS#_CON
SPI_SO_CON SPI_SI_CON
SPI_SO20
15ohm @ PCH
SPI_CS#020,30
C C
SPISO
SPICS#1
For IT8541
Change to SPI_CS#0 when
only one SPI ROM
R2811
R2811
15Ohm
15Ohm
R2813
R2813
15Ohm
15Ohm
1 2
12
12
3 4
5 6
7
HEADER_2X4P_K8
HEADER_2X4P_K8
R2809
R2809
3.3KOhm
3.3KOhm
SPISO1
+3VM_SPI_WP1#
2
@
@
1
2
3
U2802
U2802
CE#
VDD
SO
HOLD#
WP#
VSS4SI
SST25VF032B
SST25VF032B
(32Mb)
SCK
SPI_CLK_CON
+3VSUS_ORG
8
+3VM_SPI_11
7
SPICLK1
6
SPISI1
5
SMBUS Link device:
[M52J] SPD, CLKGEN,DEBUG,WLAN,
CPU XDP,PCH XDP,VID CONTROLLER
[G50J] FM2010,GAME LED,
+3VS
SPI_CLK 20,30
SPI_SI 20
5
12
R2810
R2810
C2801
C2801
3.3KOhm
3.3KOhm
0.1UF/16V
1 2
0.1UF/16V
R2812 0OhmR2812 0Ohm
1 2
For IT8541
Place nearby SPI ROM
EC_SI_PCH 30
EC_SCK_PCH 20,30
EC_SO_PCH 30
EC_SCE#_PCH 20,30
SCL_3A21
PCH
SDA_3A21
SMB1_CLK30,77
EC PCH
SMB1_DAT30,77
3 4
Q2801B
Q2801B
UM6K1N
UM6K1N
3 4
Q2802B
Q2802B
UM6K1N
UM6K1N
+12VS
2
6 1
Q2801A
Q2801A
UM6K1N
UM6K1N
+12VSUS
5
2
6 1
Q2802A
Q2802A
UM6K1N
UM6K1N
R1.1
+12VS
+3VS
1 2
4.7KOhm
4.7KOhm
R2807
R2807
1 2
4.7KOhm
4.7KOhm
R2808
R2808
SMB_CLK_S 7,14,15,16,29,53
SMB_DAT_S 7, 14,15,16,29,53
SML1_CLK 21
SML1_DAT 21
B B
2
6 1
Q2803A
Q2803A
UM6K1N
U2803 Truth table:
PM_RSMRST#=H, S=1, A--C connect. (SPI1--SB)
PM_RSMRST#=L, S=0, A--B connect. (SPI1--EC)
OE=1, S=X, switch disabled.
UM6K1N
3 4
Q2803B
Q2803B
UM6K1N
UM6K1N
5
1 2
4.7KOhm
4.7KOhm
R2814
R2814
1 2
4.7KOhm
4.7KOhm
R2806
R2806
SMB1_CLK_S 50
CPU Thermal
SMB1_DAT_S 50
DANIEL 1229
8512 8541
R3002,
R2858,
R3003,
R2859,
R3004,
R2860,
R3005,
3
R2855
R2857
U2803
R2848
C2804
U3003,
R3053,
R3043,
C3019
R2861,
R2849,
R2850,
R2851,
R2852,
R2440
R2441
DNI
Mount
DNI Mount
SUBSYSTEM ID : SB_
2
Title :
Title :
Title :
PCH_SPI ROM,OTH
PCH_SPI ROM,OTH
PCH_SPI ROM,OTH
Engineer:
Engineer:
Engineer:
Daniel Huang
Daniel Huang
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
ASUSTeK COMPUTER INC. NB6
Size Project Name
Size Project Name
Size Project Name
C
C
C
David Lewis
David Lewis
Date: Sheet of
Date: Sheet of
Date: Sheet of
David Lewis
Thursday, April 15, 2010
Thursday, April 15, 2010
Thursday, April 15, 2010
1
Daniel Huang
28 99
28 99
28 99
Rev
Rev
Rev
1.3
1.3
1.3
A A
SUBSYSTEM ID : ROM
5
4
R2853,
R2854,
R2827,
R2828,
R2846
R3002,
R3003,
R3004,
R3005,
R2855
R2857
U3003,
R3053,
R3043,
C3019
R2858,
R2859,
R2860,
R2861,
R2440
R2441
R2849,
R2850,
R2851,
R2852,
5
R1.3,item L1
Layout note:
R2916R2917
FSLC
1
R2916
R2916
10KOhm
10KOhm
@
@
R2917
R2917
10KOhm
10KOhm
FSLC
+VDD_3.3
1 2
12
D D
RX2907
R2916,R2917:as close as possible
to the net FSLC of RX2907.
BCLK
C C
133 0
100
4
CLK_PWRGD#80
R2.0
1
1
1
+VDD_3.3
3
3
G
G
2
2
Check power
R2906: For Xtal measurement
R2920
R2920
1MOhm
1MOhm
1 2
CLK_ICH1421
SMB_DAT_S7,14,15,16,28,53
SMB_CLK_S7,14,15,16,28,53
X2_CLK
X1_CLK
@
@
12
32
D
D
S
S
R2925
R2925
10KOhm
10KOhm
RX2907
RX2907
33Ohm
33Ohm
CLK_PWRGD
Q2901
Q2901
2N7002
2N7002
12
3
R2907
12
R2907
620Ohm
620Ohm
C2910
C2910
18PF/50V
18PF/50V
R2.0
X2901 14.31818MhzX2901 14.31818Mhz
X1_CLK X2_CLK
1 3
2
4
12
C2914
C2914
18PF/50V
18PF/50V
GNDGND GND
ICS9LRS3197 output with integrated 33ohm sereis resistor
+VDD_IO
CLK_PCH_BCLK 21
CLK_PCH_BCLK# 21
U2901
24
U2901
23
22
21
20
19
18
17
ICS9LRS3197AKLFT
ICS9LRS3197AKLFT
GNDCPU
CPUT0_LPR
CPUT1_LPR
VDDCPU_IO
CPUC0_LPR
CPUC1_LPR
VDDCPU_3.3
VDDSRC_3.3
CPU_STOP#
VDDSRC_IO
SRCC1_LPR
SRCT1_LPR
GNDSRC
SATAC_LPR
SATAT_LPR
GNDSATA
+VDD_3.3
FSLC
25
CLKPWRGD/PD#_3.3
26
GNDREF
27
X2
28
X1
29
VDDREF_3.3
30
REF_3L/FSLC_3.3**
31
SDATA_3.3
32
SCLK_3.3
33
GND1
34
GND2
+VDD_1.5
2
+1.5VS
12
12
@
@
@
@
R2924
R2924
10KOhm
10KOhm
R2983
R2983
R2982
R2982
0Ohm
0Ohm
0Ohm
0Ohm
@
@
@
@
+VDD_IO
STP_CPU#
16
15
14
13
12
11
10
9
1 2
1 2
ICS9LRS3197 output with integrated 33ohm sereis resistor
R2923
R2923
10KOhm
10KOhm
R1.2
DANIEL0308
+VDD_3.3
12
R2926
R2926
10KOhm
10KOhm
CLK_DMI# 21
CLK_DMI 21
CLK_SATA# 21
CLK_SATA 21
1
R1.2
R2918
R2918
Clock_select_uc30
B B
A A
1 2
1KOhm
1KOhm
@
@
+3VS
+VTT_CPU +VDD_IO
+VDD_1.5
DANIEL0308
L2902
L2902
21
L2903
L2903
12
C2903
C2903
10UF/10V
10UF/10V
21
120Ohm/100Mhz
120Ohm/100Mhz
120Ohm/100Mhz
120Ohm/100Mhz
Layout note:
VDD_3.3: 5pin -->0.1uF to each pin
VDD_IO : 2pin -->0.1uF to each pin
+VDD_3.3
+3VS_VDDPCIEX
VDDDOT96MHz_3.31GNDDOT96MHz2DOT96T_LPR3DOT96C_LPR4VDD_27MHz527MHz_nonSS627MHz_SS7GND27MHz
12
C2904
C2904
0.1UF/16V
0.1UF/16V
12
C2905
C2905
10UF/10V
10UF/10V
8
NV27M_SSC 78
NV27M_NOSSC 78
CLK_DOT96# 21
CLK_DOT96 21
12
12
C2909
C2909
0.1UF/16V
0.1UF/16V
C2906
C2906
0.1UF/16V
0.1UF/16V
12
C2926
C2926
0.1UF/16V
0.1UF/16V
+VDD_3.3
+3VS
+1.5VS
L2905
L2905
120Ohm/100Mhz
120Ohm/100Mhz
L2906
21
120Ohm/100Mhz
120Ohm/100Mhz
21
@L2906
@
12
C2912
C2912
0.1UF/16V
0.1UF/16V
12
C2913
C2913
0.1UF/16V
0.1UF/16V
12
+VDD_1.5
C2911
C2911
0.1UF/16V
0.1UF/16V
CLK_ICS9LRS3197
CLK_ICS9LRS3197
CLK_ICS9LRS3197
Title :
Title :
Title :
James1_Wu
James1_Wu
James1_Wu
Engineer:
Engineer:
ASUSTeK COMPUTER INC. NB4
ASUSTeK COMPUTER INC. NB4
ASUSTeK COMPUTER INC. NB4
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
David Lewis
David Lewis
David Lewis
1
Rev
Rev
Rev
1.3
1.3
1.3
of
29 99Wednesday, April 21, 2010
29 99Wednesday, April 21, 2010
29 99Wednesday, April 21, 2010
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