Arcam CD192DAC Schematic
ITEM101 1 BLANK PCB 10DACL954PB
ITEM102 4 M Screw Torx M3x10MM ST ZPHA3V10A
ITEM103 4 Nut M3 Full Stzp (1000)HJ3A00A
ITEM104 4 Washer M3 Plain ST BLKHL3AB To be mounted on bottom side under screw head
Via type Bottom pad
P107
P101
CON101
1
2
C109
10N
100V
0805
+18V(U)
C110
10N
100V
0805
C120
100N
100V
MKS2
C145
10N
100V
0805
C101
33P
100V
0805
LM317T
TO-220
C150
100UF
50V
YXF
C112
100N
50V
0805
C114
10N
100V
0805
C115
10N
100V
0805
This symbol represents Chassis ground
C102
33P
100V
0805
D103
1N4148
DO-35
REG102
CON102
MOLEX
52045
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
C116
10N
100V
0805
ADJ
C125
100UF
25V
ZA
C103
33P
100V
0805
P122
DGND
R109
270R
0W125
0805
R111
820R
0W125
0805
P127
P128
Via type
Bottom pad
P126
C104
33P
100V
0805
Via type
P115
P116
P133
RLY401C
NEC
EB2-12NU
MOLEX
52045
D104
1N4148
DO-35
+5VD
P129
P130
Bottom pad
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DGND
Actual = 5.13V
L101
6U8
2.1A 8RHT2
L102
6U8
2.1A 8RHT2
D107
1N4148
DO-35
C151
22N
100V
MKS2
Via type
P114
P108
P102
P103
P104
P105
P106
C105
10N
100V
0805
C106
10N
100V
0805
P123
C152
2200UF
10V
ZL
Place C146 & C148 close to inductors
Bottom pad
+18V(U)
P117
P118
-18V(U)
SCLK_MECH
P109
SDATA_MECH
P110
LRCLK_MECH
P111
1 2
P112
DE_EMPH
C107
10N
100V
+3V3D_24MHZ
0805
DE_EMPH
Low = No De-emphasis
High = 44.1kHz de-emphasis
---------------------------
Can tie DE_EMPH high to force SRC
bypass. Then also need to force
DACs to no de-emphasis.
+5VA
C157
2200UF
10V
ZL
AGND
C146
100N
50V
0805
C148
100N
50V
0805
IC101A
74VHC14M
SO-14
C118
100UF
25V
ZA
C122
100UF
25V
ZA
P136
R101
0R0
0W125
0805
R102
0R0
0W125
0805
IC101B
3 4
74VHC14M
SO-14
NF
C111
100N
50V
0805
C117
100N
50V
0805
LM317T
TO-220
LM337T
TO-220
P113
L954C2_A
L954C2_1.2-10DAC-SRC_Clock_Gen.sch
SCLK_MECH
SDATA_MECH
LRCLK_MECH
RESET#
D101
1N4148
DO-35
REG101
REG104
P137
D108
1N4148
DO-35
ADJ
C124
100UF
25V
ZA
C127
100UF
25V
ZA
ADJ
RESET#
DE_EMPH1
DE_EMPH1
IC101G
VCC
GND
74VHC14M
SO-14
P119
P131
+3V3D
14
7
DGND
R105
240R
0W125
0805
R107
2K2
0W125
0805
R108
2K2
0W125
0805
R106
240R
0W125
0805
C108
100N
50V
0805
ITEM105 1 Pad Damping 15x6x3MM SorbothaneE802AP
ITEM106 1 Pad Damping 15x6x3MM SorbothaneE802AP
ITEM107 1 Pad Damping 15x6x3MM SorbothaneE802AP
ITEM108 1 Pad Damping 15x6x3MM SorbothaneE802AP
ITEM109 1 Pad Damping 15x6x3MM SorbothaneE802AP
MECH_CLOCK
MCLK_DAC_L1
MCLK_DAC_L2
MCLK_DAC_R1
MCLK_DAC_R2
SCLK_DAC
SDATA_DAC
LRCLK_DAC
DE_EMPH#
IC101C
5 6
74VHC14M
SO-14
IC101D
89
74VHC14M
SO-14
IC101E
1011
74VHC14M
SO-14
IC101F
1213
74VHC14M
SO-14
DGND
Actual = 12.93V
P120
D102
1N4148
C119
DO-35
100UF
25V
SMIC
C123
100UF
25V
D109
SMIC
1N4148
DO-35
P132
DGND
Force DE-EMPH low at this point
to prevent DACs from applying
de-emphasis when the rest of the
circuit is forced into bypass.
Place these 6 at plane
C149
100N
100V
MKS2
C153
1000UF
16V
YXF
C141
100N
100V
MKS2
C154
1000UF
16V
YXF
R103
0R0
0W125 0805
R104
0R0
0W125 0805
+12VA
-12VA
NF
C155
3300UF
25V
YK
C156
3300UF
25V
YK
DE_EMPH2
NF
P121
AGND
NF
L954C3_A
L954C3_1.2-10DAC-DACs.sch
MCLK_DAC_L1
MCLK_DAC_L2
MCLK_DAC_R1
MCLK_DAC_R2
SCLK_DAC
SDATA_DAC
LRCLK_DAC
DE_EMPH#
DE_EMPH2
P138
RESET#
Connection point for +5VA
(if required for testing)
P135
+3V3D
DGND
DACL1_OUTL+
DACL1_OUTL-
DACL1_OUTR+
DACL1_OUTR-
DACL2_OUTL+
DACL2_OUTL-
DACL2_OUTR+
DACL2_OUTR-
DACR1_OUTL+
DACR1_OUTL-
DACR1_OUTR+
DACR1_OUTR-
DACR2_OUTL+
DACR2_OUTL-
DACR2_OUTR+
DACR2_OUTR-
Power to SPDIF RX board
+12VA
-12VA
AGND
DRAWING TITLE
2 3 4 2 5
A & R Cambridge Ltd.
Pembroke Avenue
Waterbeach
Cambridge CB5 9PB
Fit on top of relay RLY401
Cut in half. Place one half on top of C119 and the other on top of C123
Cut in half. Place one half on top of C152 and the other on top of C157
Cut in half. Place one half either side of crystal X201
Cut in half. Place one half either side of crystal X202
DGND AGND
NF
CON103
1
2
3
4
5
6
7
8
AMP
CT
FIX103
Dia 3.5mm
1
P140
C130
10N
100V
0805
R113
0R0
NF
0W125
0805
R114
0R0
NF
0W125
0805
DGND AGND
Other AGND/DGND j oins on DAC sheet
FIX101
Dia 3.5mm
FIX102
1
Dia 3.5mm
C128
10N
100V
0805
10DAC - Top level and PSU
Filename:
L954C1_1.2-10DAC-Top_level_and_PSU.prj
Notes:
Contact Engineer:
L954C4_A
L954C4_1.2-10DAC-Analogue_out.sch
DACL1_OUTL+
DACL1_OUTL-
DACL1_OUTR+
DACL1_OUTR-
DACL2_OUTL+
DACL2_OUTL-
DACL2_OUTR+
DACL2_OUTR-
DACR1_OUTL+
DACR1_OUTL-
DACR1_OUTR+
DACR1_OUTR-
DACR2_OUTL+
DACR2_OUTL-
DACR2_OUTR+
DACR2_OUTR-
C135
C136
C137
10N
10N
100V
0805
+5VD
1
C129
10N
100V
0805
Contact Tel: 01223 203200Mark Tweedale
10N
100V
100V
0805
0805
FD101 FD102
Place C147 close to inductor
L103
6U8
2.1A
8RHT2
C147
100N
50V
0805
FIX104
1
Dia 3.5mm
03_E109 MJT None to this sheet 1.210/04/03
03_E079 MJT
03_E061 MJT Production release 1.0
ECO No. DESCRIPTION OF CHANGE
DGND
10 DAC
C131
10N
100V
0805
C138
10N
100V
0805
INITIALS
Printed:
C144
100UF
25V
YK
FIX105
Dia 3.5mm
C139
10N
100V
0805
TOOL101 TOOL102 TOOL103 TOOL104
P134
LM1086CT-ADJ
TO-220
C113
100N
50V
0805
1
C132
10N
100V
0805
Listening tests complete. C155/C156/R113 NF,
C119/C123 changed, sorbothane added.
20/02/03
DATE
10-Apr-2003
C140
10N
100V
0805
REG103
FIX106
Dia 3.5mm
14Sheet of
D105
1N4148
DO-35
C142
C143
10N
10N
100V
100V
0805
0805
Actual = 3.33V
+3V3D
P125
ADJ
P124
C126
100UF
25V
YK
FIX107
1
Dia 3.5mm
C133
10N
100V
0805
DRAWING NO.
R110
120R
0W125
0805
R112
200R
0W125
0805
1
AGND
D106
1N4148
DO-35
C134
10N
100V
0805
P139
L954CT
DGND
C121
1000UF
35V
ZL
1.107/03/03
ISSUE
group delay
pre-emphasis
SRC
other.)
RECLOCKING
SDATA_MECH
SCLK_MECH
LRCLK_MECH
+3V3D
L207
P222
70R@100MHz
C211
100N
50V
0805
DGND
+3V3D
L208
P223
70R@100MHz
C212
100N
50V
0805
DGND
+3V3D_24MHZ +3V3D_24MHZ
IC208G
14
VCC
GND
74HCU04D
SO-14
C215
100N
50V
7
0805
5V to 3V3 translator
Fit this resistor only i f using '541 instead
IC203A
1
DGND
R284
0R0
0W125
0805
R285
0R0
0W125
0805
VCC
GND
OE
11
CP
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
74VHC574M
SO-20
C235
10UF
50V
YK
33.8688 MHz clock
C236
10UF
50V
YK
24.576 MHz clock
20
C216
100N
50V
10
0805
P273
IC212B
74VHC541M
SO-20
Default SRC Reset setup: Assumes SRC passes clocks and data.
Fit this resistor only i f using '541 instead
R207
NF
100R
0W125
0805
19
P280
Q0
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
P208
P209
P210
-3dB at 160kHz
DGND
16.9344 MHz
MECH_CLOCK
R266 0R0
R267 0R0
R268 0R0
P230
Place these two '541s very close with their outputs with resistors
facing each other. (They will be 180 degrees rotated relative to each
R270
0R0
0W125
0805
DGND
C225
100N
50V
0805
DGNDDGNDDGNDDGNDDGND
P281
R209
100R
0W125
0805
DGND
MCLK_COUNT1
C232
10N
100V
0805
IC213A
1
OE1
19
OE2
P255
P250
2
I0
3
I1
P254
4
I2
5
I3
6
I4
7
I5
8
I6
9
I7
74VHC541M
SO-20
Don't need 16MHz clock for counters
and buffer when data is emphasised
IC212A
1
OE1
19
OE2
P263
2
I0
3
I1
4
I2
5
I3
6
I4
7
I5
8
I6
9
I7
74VHC541M
SO-20
DRAWING TITLE
2 3 4 2 5
A & R Cambridge Ltd.
Pembroke Avenue
Waterbeach
Cambridge CB5 9PB
P284
P282
R210
R211
NF
100R
100R
0W125
0W125
0805
0805
R283
0R0
0W125
0805
P217
DE_EMPH#
O0
O1
O2
O3
O4
O5
O6
O7
O0
O1
O2
O3
O4
O5
O6
O7
12345
MCLK_COUNT2
All resistors 62mW , 1206 quad pack
P257
1 8
P260
2 7
18
P272
17
16
15
P259
14
P262
1 8
13
12
P261
2 7
11
P258
P256
P265
5 4
P268
6 3
18
P270
17
16
15
P267
14
P271
5 4
13
12
P269
6 3
11
P266
P264
All resistors 62mW , 1206 quad pack
10DAC - SRC and Clock Gen
Filename:
Notes:
Contact Engineer:
DGND
IC208A
74HCU04D
SO-14
R226
100R
0W125
0805
R227
100R
0W125
0805
C224
100N
50V
0805
IC201A
1
OE
11
CP
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
74VHC574M
SO-20
R206
100R
0W125 0805
P299
MECH_CLOCK
TR203
MMUN2211LT1
SOT-23
DGND
IC201B
VCC
GND
74VHC574M
SO-20
R217
100R
0W125
0805
DE_EMPH#
DGND
DE_EMPH1
+3V3D_SRC_IO
20
10
IC204A
DGND
P288
DGND
P289
R256
0R0
0W125
0805
C220
100N
50V
0805
10
11
12
14
15
NF
NF
1
2
NF
74VHC08M
SO-14
R249
0R0
0W125
0805
R248
0R0
NF
0W125
0805
4
SDATA_I
5
SCLK_I
6
LRCLK_I
SMODE_IN_0
SMODE_IN_1
SMODE_IN_2
9
BYPASS
MUTE_I
MUTE_O
P297
R280
1M0
0W125
0805
IC209F
74HC04D
SO-14
R281
1M0
0W125
0805
IC208F
74HCU04D
SO-14
IC206B
VCC
GND
74VHC161M
SO-16
DE_EMPH#
RESET#
If either go low, SRC
resets
Place t hese
63
RP206C
100R
.
R286
0R0
0W125 0805
C233
10N
100V
0805
Was C240
R214
0R0
0W125 0805
C234
10N
100V
0805
14
7
resistors
close to the
inputs of the
DGND DGND
RP205A
1 8
100R
RP205B
2 7
100R
RP205C
100R
RP205D
100R
P225
R265
15R
0W125
0805
P251
R275
1K5
0W125
0805
P240
R269
15R
0W125
0805
P253
R276
1K5
0W125
0805
C218
100N
50V
0805
RP206D
5 4
100R
L209
1U8
TR201
BFS17H
SOT-23
L210
2U7
TR202
BFS17H
SOT-23
63
54
P248
C242
39P
100V
0805
DGND
P247
C244
56P
100V
0805
DGND
IC213B
VCC
GND
74VHC541M
SO-20
P201
Sets i/p format to Right Justified, 16 bit
+3V3D_SRC_IO
DGND
SRC_CLOCK
20
10
DGNDDGNDDGNDDGNDDGND
C219
100N
50V
0805
C245
1N0
100V
0805
C246
1N0
100V
0805
R215
0R0
0W125
0805
+3V3D_33MHZ
+3V3D_24MHZ
Internal
pull-up.
High for short
.
P202
P203
P287
R224
0R0
0W125
0805
R277
120K
0W125
0805
P226
R279
100K
0W125
0805
DGND
R278
120K
0W125
0805
P241
R282
100K
0W125
0805
DGND
+3V3D_COUNT +3V3D_COUNT +3V3D_COUNT
IC207B
16
VCC
8
GND
74VHC161M
SO-16
P204 P205 P206
R201
NF
100R
0W125
0805
19
P274
Q0
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
C213
100N
50V
0805
C214
100N
50V
0805
IC211C
74HC74D
SO-14
RP206A
RP206B
100R
100R
1 8
2 7
P275
P276
P285
P286
All resistors 62mW , 1206 quad pack
DE_EMPH1
DE_EMPH1
This line from the mech is
high when data has
P245
+3V3_33XTAL
Was C237
R271
10K
0W125
0805
R272
10K
0W125
0805
R273
10K
0W125
0805
R274
10K
0W125
0805
+3V3D_33MHZ +3V3D_33MHZ +3V3D_33MHZ
14
VCC
7
GND
P229
X201
33.8688MHz 3OT
HC49
C241
33P
100V
0805
+3V3_24XTAL
P249
X202
24.576MHz 3OT
HC49
C243
47P
100V
0805
C217
100N
50V
0805
P224
P239
IC209G
VCC
GND
74HC04D
SO-14
+3V3D_SRC_CORE
3
P2003
R250
NF
0R0
0W125
0805
P207
P2002
13
1
RESET
GRPDLYS
MCLK_I2MCLK_O3MMODE_026MMODE_127MMODE_228DGND8DGND
P298
C208
NF
100N
50V
0805
DGND
P2004
R223
1213
100R
0W125
0805
1 2
P2005
R236
1213
100R
0W125
0805
16
C221
100N
50V
8
0805
C201
100N
50V 0805
+3V3D_SRC_IO
22
7
VDD_CORE
SMODE_OUT_0
SMODE_OUT_1
WLNGTH_OUT_ 0
WLNGTH_OUT_ 1
21
DGND
IC209E
74HC04D
SO-14
P252
IC209A
74HC04D
SO-14
P242
IC202B
VCC
GND
74VHC574M
SO-20
Place caps as close to SRC as poss
C202
100N
DGND
50V
0805
IC205
VDD_IO
23
SDATA_O
25
SCLK_O
24
LRCLK_O
19
18
17
16
20
TDM_IN
DGND
AD1896YRS
SSOP-28
R216
P2001
1011
100R
0W125
0805
P2009
+3V3D_33MHZ
10
12
D
P227
11
CLK
13
Connect external MCLK here
P244
C222
100N
50V
0805
20
10
R202
100R
0W125
0805
P2006
+3V3D_33MHZ
SRC_CLOCK
IC211B
Q
SD
Q
RD
74HC74D
SO-14
DE_EMPH1
9
8
P277
P278
P279
33.8688 MHZ
P216
SRC_CLOCK
R203
100R
0W125
0805
P228
R225
100R
0W125
0805
R208
100R
0W125
0805
+3V3D_SRC_IO
NF
IC204E
VCC
GND
74VHC08M
SO-14
+3V3D_SRC_CORE
DE_EMPH1
P283
14
C223
NF
100N
50V
7
0805
DE_EMPH#
MCLK_BYPASS
Sets o/p format to I2S
Sets o/p format to 24 bit s
DGND
IC210A
2 4
74HCT1G04GW
SOT-353
IC209B
3 4
74HC04D
SO-14
DE_EMPH#
RECLOCKING
TR204
MMUN2211LT1
SOT-23
DGND
IC203B
VCC
GND
74VHC574M
SO-20
R204
330R
0W125 0805
R205
100R
0W125 0805
1 2
P2007P2010
P2008
+3V3D_SRC_IO
20
10
+3V3D
C203
100N
50V
0805
DGND
+3V3D
C204
100N
50V
0805
DGND
P243
+3V3D_COUNT
NFNF
CON201
AMP
high=count
CT
DGND
+3V3D_COUNT
DGND
RP201A
100R
RP201B
100R
RP201C
100R
63
RP201D
100R
54
RP202A
100R
RP202B
100R
RP202C
100R
63
RP202D
100R
54
100R
RP203D
RP203C
100R
RP203B
100R
27
RP203A
100R
18
RP204D
100R
RP204C
100R
RP204B
100R
27
RP204A
100R
18
L954C2_1.2-10DAC-SRC_Clock_Gen.sch
+3V3D_SRC_IO
L201
P211
70R@100MHz
L202
70R@100MHz
IC207A
9
PE
1
MR
10
CET
7
CEP
2
CP
3
P0
4
P1
5
P2
P36TC
74VHC161M
SO-16
IC206A
9
PE
1
MR
10
CET
7
CEP
2
CP
3
P0
4
P1
5
P2
P36TC
74VHC161M
SO-16
R219 / R221 for 192kHz (Default)
R220 / R222 for 96kHz upsampling
Contact Tel: 01223 203200Mark Tweedale
C226
47UF
35V
YK
+3V3D_SRC_CORE
P212
C227
47UF
35V
YK
14
P291
Q0
13
P292
Q1
12
Q2
11
Q3
P290
15
P218
14
Q0
13
Q1
12
P293
Q2
11
P294
Q3
15
C238
47P
100V
0805
DGND
03_E109 MJT R226 changed to 100R for EMC. 1.210/04/03
03_E079 MJT Listening tests complete. IC209/IC211 changed to HC famil y. 1.107/03/03
03_E061 MJT Production release 1.020/02/03
+3V3D +3V3D
C205
100N
50V
0805
DGND DGND
SDATA_DAC
SCLK_DAC
LRCLK_DAC
DE_EMPH1
MCLK_COUNT_BUFF
R219
100R
P219
0W125
0805
R220
100R
0W125
0805
R218
100R
0W125
0805
R221
100R
0W125
0805
R222
100R
0W125
0805
ECO No. DESCRIPTION OF CHANGE
P220
NF
NF
MCLK_COUNT1
MCLK_COUNT2
MCLK_COUNT_BUFF
MCLK_DAC_L1
MCLK_DAC_L2
MCLK_DAC_R1
MCLK_DAC_R2
MCLK_BYPASS
Rememb er, may need l arger caps
on MCLK_COUNT1/2 for delay.
C239
47P
100V
0805
+3V3D_33MHZ
2
D
3
CLK
DGND
+3V3D_33MHZ
DATE
INITIALS
Printed:
10-Apr-2003
+3V3D_COUNT
L203
P213 P214
70R@100MHz
4
Q
SD
Q
RD
1
11
DGND
P231
MCLK_COUNT1
P232
MCLK_COUNT2
P233
MCLK_COUNT_BUFF
P234
MCLK_DAC_L1
P235
MCLK_DAC_L2
P236
MCLK_DAC_R1
P237
MCLK_DAC_R2
P238
MCLK_BYPASS
IC211A
5
6
74HC74D
SO-14
24Sheet of
C228
47UF
35V
YK
+3V3D
DGND
IC202A
1
OE
CP
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
74VHC574M
SO-20
+5VD
DGND
19
Q0
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
L206
70R@100MHz
C209
100N
50V
0805
IC209C
5 6
74HC04D SO-14
IC209D
74HC04D SO-14
DGND DGND
C206
100N
50V
0805
C207
100N
50V
0805
R212
100R
0W125
0805
P295
P296
IC210B
74HCT1G04GW
SOT-353
89
DRAWING NO.
L204
70R@100MHz
L205
70R@100MHz
R213
100R
0W125
0805
5
VCC
3
GND
4
5
9
10
12
13
DGND
3 4
5 6
+3V3D_33MHZ
C229
47UF
35V
YK
+3V3D_24MHZ
P215
C230
47UF
35V
YK
SDATA_DAC
SCLK_DAC
LRCLK_DAC
P221
C210
100N
50V
0805
IC204B
NF
6
74VHC08M
SO-14
IC204C
NF
8
74VHC08M
SO-14
IC204D
NF
11
74VHC08M
SO-14
IC208B
74HCU04D SO-14
IC208C
74HCU04D SO-14
IC208D
89
74HCU04D SO-14
IC208E
1011
74HCU04D SO-14
L954CT
ISSUE
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