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NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
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II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
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REV.
APPLE COMPUTER INC.
SCALE
NONE
8/4/03
7/28/03
7/22/03
7/9/03
203) CHANGED J12 (SOUND) TO 516S0144 (NEW PIN PLATING SPEC)
201) CHANGED J10 (OPTICAL DRIVE) TO 516S0140 (NEW PIN PLATING SPEC)
202) CHANGED J13 (HARD DRIVE) TO 516S0140 (NEW PIN PLATING SPEC)
200) CHANGED J20 (AIRPORT) TO 516S0142 (NEW PIN PLATING SPEC)
199) CHANGED J9 (CARDBUS) TO 516S0141 (NEW PIN PLATING SPEC)
117) changed 2.5V_SLEEP FET (U48) and 1.8V_SLEEP FET (U6) to higher current part (Si6467BDQ - 376S0161)
104) add NO STUFF to R300 to complete 3V sequecing on wake from sleep fix
82) CHANGED U55 TO MM1571J FOR COST SAVINGS
83) changed L72,L73,L74 to 90 ohm ferrites
84) added 10K pullup to +5V_MAIN to SND_HP_MUTE
85) repinout Sousaphone connector
86) remore redundant pullups on FANL_TACH and FANR_TACH
87) added TP to all NC on NEC USB2 part for NAND tree testing
80) updated power constraints with new fan net names
81) change Q58 on pg19 to Q80 to consolidate parts
LEFT FAN (CPU) AND FAN 2 CONNECTS TO THE RIGHT FAN (GPU)
77) moved XW15 to connect to CPU_VCORE_SLEEP_UF (before positioning resistor)
44) move CPU thermal sensor (Q39) to input 1 on fan controller and power supply sensor (Q66) to input 2
REV 0.01 - 03/06/2003
3/3
3) added jumpers at 1.5V, 1.8V, 2.5V, 3.3V, 5V, and PBUS supply outputs
5) removed dedicated boot banger circuit (U5400,U5200,RP46,U9,U1000)
10) changed Vcore stuffing options to 1.4V/1.025V using analog mux to support slewing
23) ***BOARD RENUMBERED***
29) update sscg/nosscg stuffing option on intrepid boot straps
6/9/03
38) changed Vcore inductor (L36) to molded core part (152S0125)
46) added FET inverters (Q78) to PWM outputs of fan controller (U3) to prevent spinup at boot
61) changed L38 and L41 to 4.7uH (152S0137)
62) added Q81, R308, R309, and R310 for power sequencing (no stuff)
69) added 15.4K R616 and 10K R672 for 2.5V switcher feedback divider
98) change R321 to 499ohm to set 5mV Vcore offset
73) changed CPU_VCORE_SLEEP location back to across bypass caps to correct after adding reference resistor
18) added pads for 0 ohm between chassis and digital gnd near ENET connector for EMC
24) integrated M10 pages from Q16 schematic and renumbered them
14) changed R164 (DAC1RSET) to 107 ohm pulldown
17) added pads for 0.1uF cap from +Adapter to digital gnd for EMC
21) REMOVED ALL RELATIVE_PROPAGATION_DELAY AND PROPAGATION_DELAY PROPERTIES TO
13) changed stuffing options for GPU PCI ID to 0x319
12) changed comments to eliminate references to L3 in power supply section
11) changed stuffing to set Vcore offset to 0mV by default
1) Initial check-in of Enterprise schematic after conversion to Concept 14.2
76) changed drain/source polarity of Q76 (FET from +BATT to Pbus)
3/10
3/18
3/19
20) removed BOM table for MAP31
7) changed cpu PLL config to 1083/833
9) changed C550 to 138S0536 to limit AVL
16) changed fan controller to ADT7460
15) added 10K pulldown to U43 pin A21
22) changed CHGND on R616 to CHGND1
31) add Vcore DAC resistors (R288,R289,R290,R292) for no mux case
67) added Q82, R607, R455, R417, and C886 for 1.5V sleep sequencing
35) changed bootrom part number to 341S1255
36) changed C756 to 128S0025 (Sanyo only 6.3V 330uF)
50) changed TMDS data chokes to 90 ohms (155S0128)
53) changed Q48 to Si7892DP (376S0120)
68) added Q83 and 100K R608 for 1.8V sequencing
64) changed L36 to 1.2uH 18.3A (152S0125)
60) changed D18 to 1N914
58) changed R364 to 102K
57) changed R416 to 2.2ohms
54) changed D24 to B340LB (371S0132)
3/28
4/10
4/18
4/21
4/28
48) changed TMDS data chokes to 90 ohm (155S0128)
43) move BS1 to bottom side
47) added FET (Q79) for +3V_Sleep for M10 power sequencing
63) changed Q49 and Q50 to Si7860DP (376S0119)
65) added R331 1mohm sense resistor to CPU Vcore
66) added C885 and C884 , 1000uF CPU Vcore outpur caps
30) removed D31 between +Batt and 24V_Pbus
78) changed Fan control nets to FanL and FanR from Fan1 and Fan2
49) changed C762 and C766 to 4.7uF 1206 caps
28) update PLL CFG high 0010 1.25GHz
27) added RP27,RP28,RP32, and RP57 for TMDS series termination
26) added DP7 for M10 power sequencing
19) corrected path to correct for last checkin
low 1011 833MHz
25) updated physical constraints for M10 power nets
42) add 165 ohm chokes on TMDS data pairs at connector (L ,L , and L )
40) added seperate 1_8V_GPU_TPVDD filter and LDO (U54)
71) removed Q44 (5V sound sleep fet)
70) changed pinout of sound connector for sousaphone
72) changed Q31 to invert headphone Mute to sousaphone
75) fixed unnamed net (LTC3411_SHDN_SEQ)
52) changed Q51 to Si7860DP (376S0119)
51) changed C762 and C766 to 4.7uF 1206
45) added trace from Vcore to fan controller ADC input
41) replace disctrete LCL with single chip LCL filters (155S0154) for VGA (L ,L , and L )
37) add pads for 90 ohm chokes to FWB path close to connector (route through the pads)
34) change I2C pullups (R29 and R102) to 1K
33) change C640 and C646 to 0.01uF (Apple # 132S1047) for FW check config
32) change intrepid PLL LDO stuffing back to 1.8V main
56) added Q58, R307, and C515 for GPU Vcore control inverter
59) added 0.1uF 50V C883 to RS- of Max4172 (NO stuff)
4/28
74) changed D5 to schottky diode (MBR0540)
4/27
2) added 8 new 10uF vcore caps
39) changed Pbus inductor (L37) to molded core part (152S0126)
PRERPARE FOR CONSTRAINT BACK ANNOTATION
8) changed reset to U56 (clock slewing chip) to MAIN_RESET_L
4) added 8 more 0.1uF vcore byapass caps
6) updated firewire to phy to rev A prt number
3/11
97) change R337 to 470K and remove No Stuff and no stuff R336 to change Vcore DAC to 1.35V/1.15V
96) remove NO STUFF on R477 (set 5V and 3.3V switcher in pulse skipping mode)
95) swap INT_AUDIO_TO_SND and SND_TO_AUDIO on Sousaphone connector (J12)
100) no stuff Q79 to disable 3V_SLEEP sequencing to work around wake from sleep bug with M10
*** rev 03 released for EVT ***
*** rev 02 released for EVT ***
99) change L72,L73,L74 to 155S0165 (D part for EVT only)
*** rev 01 released for EVT ***
88) added NEC_USB bomoption to 0 ohm resistor on NEC_AVSS_F
94) add CHGND4 and SLEEP_LED functional test points
92) change L30 to 152S0139 (Tokin CPI-1050-2R2) 11A
91) updated various text notes with correct reference designators
90) no stuff R322 to eliminate 3V_sleep pump up
93) remove FANR_TACH functional test point
89) repinout Sousaphone connector (J12)
5/7
5/6
5/1
4/28
4/30
79) SWAPPED CONNECTIONS SO THAT OUTPUT 1 FROM FAN CONTROLLER CONNECTS TO
150) changed R205,R218,R211,R219,R210,R220,R204,R214 to 162 ohm 1% (TMDS common-mode termination)
140) modified Vcore offset select circuit with Takashi’s changes - changed Gnd reference to VCORE_GND_SNS
137) changed Q83 into dual (2N7002DW) and added R810 to invert 3V_5V_ON before switching RUN/SS
133) added C902 and R804 to prevent latch-up condition in GPU Vcore circuit when using powermiser
130) added LC filter on SND_AMP_MUTE for EMI (L76 and C898)
129) added LC filter on SND_TO_AUDIO for EMI (L82 and C897)
121) NO STUFF R631 to remove MAIN_RESET_L from clock slewing chip
118) added 10K pulldown (R720) on FW_PHY_PD_INT for when R698 is removed
115) added NO STUFF BOM option to R300 to avoid sleep wake problem
112) added U56, U57, R718,R714 for VGA Hsync and VGA Vsync buffering
111) added R698 as 0 ohm jumper between FW_PHY_PD and Intrepid
110) added R711 as pullup to +3V_GPU on AUXWIN signal from M10 (U44)
109) changed SND_HP_MUTE_INV gate/inversion FETS to pullup to +3V_MAIN
102) fixed NO STUFF BOM option for R291
105) changed R376 to 158K and R321 to 2.74K to set CPU_VCORE offset to 35mV
*** rev 04 released for EVT ***
107) removed redundant 3V_GPU pullup R687 (Intrepid side AGP_INT_L pullup)
6/5/03
6/4/03
5/22
5/19/03
175) swapped DN<0> and DP<0> on RP27 for layout
173) changed GPU_MEM_IO to +GPU_MEM to connect ATI Vref to correct memory voltage
170) added R255 and R251 to strap GPU_DVODMODE correctly for 1.8V DVO
169) added L16, C304, C327, C647 for filtering GPU VDDR4
166) added R231. R232, and C284 for Vref for U5
165) added R235 and R237 as options for MAIN_RESET_L to U5
164) added L15, C255, C233, C218 for 3V Vcc filtering for SIL1162 (U5)
163) added L13, C14, C129, C131, C133 for 3V PVCC filtering for SIL1162 (U5)
162) added L14, C130, C132, and C165 for 3V AVCC filtering for SIL1162 (U5)
161) added R41 to create +3V_GPU_SI power for SIL1162 (U5)
160) added U5 to use as external TMDS transmitter (DVI)
159) changed L30 to 3 pin symbol
158) added R234 and INT_TMDS option to maintain internal TMDS capability
157) changed R228 to pullup to 1.8V for DVO interface conpatibility
155) removed NO STUFF from C903 (cap on input to second part of THERM_OC_L buffer)
148) changed R612 to 10K to prevent UIDE DMACK from floating
149) changed C80,C88,C81,C89,C82,C102,C79,C87 to NO STUFF (TMDS common-mode termination)
151) changed RP27,RP32,RP28,RP57 to 10ohm (TMDS series termination)
*** released for EVT2 6/10/03 ***
154) removed NO STUFF from R638 (pullup on slewing chip FSEL)
156) CHANGED R321 TO 1K FOR VCORE OFFSET OF 12MV (VCORE = 1.30V -30MV/+100MV)
*** released for EVT2 6/13/03 ***
143) added cap on gate of the second FET in Q87 for possible turn on delay (C903)
144) changed inner shield of FWB connector J26 to connect to chassis gnd
146) changed R321 to 2.49K to set Vcore offset to +25mV
147) added 10 ohm resistor (R814) and 1uF cap (C904) to filter power to ADT7460 (Gary Leo)
152) fixed NO STUFF on R291
131) added LC filter on SND_HW_RESET_L for EMI (L78 and C900)
142) removed redundant pullup on THERM_L_OC (R780)
132) added LC filter on SND_SCLK for EMI (L79 and C901)
134) removed R331 (CPU Vcore positioning resistor)
136) add Vcore offset change circuit to modify offset in low (Q86,R805,R806,R807,R808,R809)
138) rotated J26 (FW B connector)
139) changed D29 to B340B (3A part - 371S0159)
6/19/03
6/18/03
6/10/03
6/13/03
6/6/03
6/9/03
168) added RP58, RP59, RP60, RP61 for series termination of SIL1162 TMDS output
189) changed GND reference for input side of Q86 to digital GND (the other FET in Q856 remains on VCORE_GNDSNS
198) NO STUFF’ed C908 (Q56 gate shoot-thru cap)
196) rotated L70 and L71 for layout (PCB symbol problem)
195) changed R321 to 3.01K 1% to set high Vcore offset to 30mV
192) changed R325 to 470K to set the low Vcore to 1.10V
191) added R279 to power TMDS PLL from LVDS filter when using external TMDS transmitter
6/25/03
184) No STUFF’ed C651 and C678
188) changed R517 to 100K
6/23/03
114) added NO STUFF BOM option to R223 to correct for sense of GPU_VCORE_CNTL
135) changed C728,C729,C730,C731,C732,C733,C734,C884,C885 to 220uF Rubycon caps (128S0024)
141) added double inverter to buffer THERM _L_OC (added Q87,R811,R812)
145) changed R336 and R325 to 0 ohm to set Vcore VID to 1.3V/1.15V
153) removed NO STUFF from C80,C88,C81,C89,C82,C102,C79,C87 (TMDS common-mode termination)
106) changed both AGP_NV_INT_L and AGP_ATI_INT_L to AGP_INT_L
113) changed L72,L73,L74 to 155S0164 (new high speed part)
116) Intgrated new 1.8V switcher (LTC3412)(U58)(353S0650) and inductor (L75- 152S0142)
108) added R699,R701,R707,R708 as 10k pulldowns to Intrepid USB ports A and C when NEC_USB is stuffed
55) changed L30 to 2.2uH Tokin inductor (152S0139)
*** released for DVT 6/26/03 ***
197) changed Q53,Q54,Q55 to IRF7832 (376S0148) for better thermal performance
194) changed R809 to 1.5K 1% to set low Vcore offset to 10mV
193) stuffed Vcore offset switch (R807,R805,R809,Q86)
190) added C908 to prevent gate shoot-thru on Q56
6/24/03
7/2/03
103) add NO STUFF to R223 to correct startup level of GPU_VCORE_CNTL
6/3/03
120) added R721 as jumper between +2_5V_SLEEP and +2_5V_GPU
128) added LC filter on INT_AUDIO_TO_SND for EMI (L81 and C896)
127) added LC filter on SND_CLKOUT for EMI (80 and C899)
126) added LC filter on SND_SYNC for EMI (L77 and C895)
125) removed gnd caps (C651 and C647) on I2S clock at sound connector (J12)
123) changed I2C 0 and 1 pullups (RP12) to 2.2K to improve rise/fall times (sensor check config errors)
124) added CRITICAL flag to new 1.8V switcher (U58), inductor (L75), 1.8V sleep FET (U6), and 2.5V sleep FET (48)
167) added R66, R99, R202, R212, R222, R224, R88, R110, R223 as straps for U5
186) added C906 to prevent shoot-thru on Q64 (currently NO STUFF’ed)
185) added C688,C690,C846,C905 for thermal pair filtering at fan controller
183) added R331 as CPU Vcore sense resistor (1 mohm 1% 2512)
ADAPTER DETECT CIRCUIT DIVIDERS TO REDUCE SHUTDOWN CURRENT
182) CHANGED R491 TO 52.3K 1%, R475 TO 127K 1%, AND R476 TO 4.7M 5% IN A29
180) changed C890 to 100pF for improved transient response (Takashi)
179) NO STUFF’ed C895,C899,C896,C897,C898,C900, and C901 to fix no sound problem
(124S0024 WILL BE DELETED AS A DUPLICATE IN THE LIBRARY)
178) CHANGED C728,C731,C734,C733,C730,C732,C729,C885,C885 TO 128S0022
176) corrected un-named nets in TMDS common-mode filters
174) swapped TMDS CLKN and CLKP on RP57 and RP58 for layout
172) added C681, C668, C678, C651 to filter the thermal sensor diff pairs
122) changed FWB connector to new part with extra ground tabs (514S0059)
119) changed R728 and R729 to 1210 0ohm resistors to support switching the entire memory bus between 1.8V and 2.5V
REVISION HISTORY
101) added BOM table to define correct part number for M10 without heatspreader (338S0133)
187) added C907 to prevent shoot-thru on Q68 (currently NO STUFF’ed)
181) Removed bypass traces on FWB chokes and stuffed L70 and L71
177) added physical constriants for new Silicon Image power rails
171) added R268 to connect L16 to +3V_GPU_FLT when not using SIL1162
215) UPDATED CAP MATERIAL TYPES
IMMUNITY TO 3.3V PGOOD SIGNAL DROPOUT
ON VCORE
1_32_VCORE (60MV OFFSET)
220) CHANGED R321 TO 4.02K 1% FOR 1_30_VCORE (40MV OFFSET) AND TO 6.34K 1% FOR
212) CHANGED 197S0040 TO PRIMARY AND 197S0008 AS ALTERNATE FOR Y4 (LMU)
210) CHANGED 197S0037 TO PRIMARY AND 197S0603 AS ALTERNATE FOR Y3 (ETHERNET)
218) CHANGED 126S0036 FROM ALT TO PRIMARY, REPLACING 126S0035 FOR CPU VCORE INPUT CAPS
IMMUNITY TO 3.3V PGOOD SIGNAL DROPOUT
230) CHANGED C883 TO 132S0100 TO CORRECT FOR USE OF OEM PART NUMBER
229) CHANGED C728-C734,C884,C885 TO 128S0022 TO REMOVE DUPLICATE PART NUMBER
228) ADDED 197S0052 AS ALTERNATE FOR G1 (98 MHZ FW OSCILLATOR)
221) CHANGED R304 TO 470K AND R329 AND R325 TO 0 OHM TO CHANGE LOW VID TO 1.05V
222) CHANGED C611 TO 2200PF, C610 TO 100PF, AND R519 TO 12.7K 1% TO INCREASE
223) NO STUFF C590 TO INCREASE IMMUNITY TO 3.3V PGOOD SIGNAL DROPOUT
224) CHANGED C583 TO 2200PF, C576 TO 100PF, AND R481 TO 15.0K 1% TO INCREASE
225) NO STUFF C566 TO INCREASE IMMUNITY TO 3.3V PGOOD SIGNAL DROPOUT
9/4/03
219) CHANGED R99 TO NO STUFF TO FIX I2C ADDRESS OF SIL1162 TMDS TRANSMITTER
*** RELEASED FOR PRODUCTION 7/28/03 ***
217) CHANGED TMDS TERMINATION FROM 2X 162 TO 2X 49.9 OHMS PER PAIR
216) CHANGED FROM 715 PIN TO 667 PIN SYMBOL FOR U44 (M10)
214) ADDED 1_32V_VCORE AND 1_30V_VCORE BOM OPTIONS FOR 2 DIFFERENT CPU VCORE SPECS
213) CHANGED 197S0041 TO PRIMARY AND 197S0604 AS ALTERNATE FOR Y6 (PMU)
211) CHANGED 197S0038 TO PRIMARY AND 197S0608 AS ALTERNATE FOR Y5 (NEC USB2)
209) CHANGED 197S0035 TO PRIMARY AND 197S0004 AS ALTERNATE FOR Y1 (INTREPID)
208) REMOVED POWER JUMPERS XW25,XW17,XW16,XW10,XW14,XW18
207) CORRECTED C889 TO CONNECT TO INPUT (PIN 1) OF U55
205) ADDED BOM TABLE TO PUT 0 OHM 402 ON L77,L80,L81,L82,L76,L78,L79
204) CHANGED J8 (MODEM) TO 516S0143 (NEW PIN PLATING SPEC)
051-6531
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B