Apple macbook m79 Schematic

8 7
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
D
6
5
4
M97 MLB SCHEMATIC
REFERENCED FROM T18
08/27/2008
3
REV
A
2 1
ZONE
625211
DESCRIPTION OF CHANGE
ECN
PRODUCTION RELEASED
CK APPD
DATE
08/29/08
ENG APPD
?
DATE
D
Sync
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
M97_MLB
M97_MLB
Date
01/04/2008
01/04/2008
01/04/2008
12/14/2007
03/19/2008
01/04/2008
C
B
Date
Sync
04/14/2008
CHANGZHANG
01/18/2008
YUAN.MA
05/28/2008
YUAN.MA
06/26/2008
T18_MLB
05/28/2008
YUAN.MA
05/09/2008
CHANGZHANG
04/21/2008
BEN
02/04/2008
YUNWU
04/07/2008
YUNWU
03/20/2008
YUNWU
01/18/2008
CHANGZHANG
04/22/2008
YUAN.MA
05/09/2008
YUAN.MA
06/26/2008
YUNWU
05/02/2008
CHANGZHANG
07/01/2008
AUDIO
07/03/2008
AUDIO
07/01/2008
AUDIO
07/01/2008
AUDIO
07/01/2008
AUDIO
03/13/2008
n
JACK
01/31/2008
RAYMOND
02/08/2008
RAYMOND
01/31/2008
RAYMOND
01/31/2008
RAYMOND
01/31/2008
RAYMOND
02/08/2008
RAYMOND
01/23/2008
RAYMOND
04/22/2008
YUAN.MA
04/04/2008
YUAN.MA
04/04/2008
NMARTIN
04/18/2008
AMASON
06/30/2008
AMASON
08/12/2008
YITE
06/30/2008
YITE
Page
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
36 37 38
40 41 42 43 44 45
47 48
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
(.csa)
45
SATA Connectors
46
External USB Connectors
48
Front Flex Support
49
SMC39
50
SMC Support
51
LPC+SPI Debug Connector
52
M97 SMBUS CONNECTIONS
53
VOLTAGE SENSING
54
Current Sensing
55
Thermal Sensors
56
Fan46
57
WELLSPRING 1
58
WELLSPRING 2
59
SMS49
61
SPI ROM50
62
AUDIO: CODEC
63
AUDI0: MIKEY
66
AUDI0: SPEAKER AMP
67
AUDIO: JACK
68
AUDIO: JACK TRANSLATORS
69
DC-In & Battery Connectors
70
PBUS Supply/Battery Charger
72
5V/3.3V SUPPLY
73
1.5V/0.75V DDR3 SUPPLY
74
IMVP6 CPU VCore Regulator
75
MCP VCORE REGULATOR
76
CPU VTT(1.05V) SUPPLY
77
MISC POWER SUPPLIES
78
POWER SEQUENCING
79
POWER FETS
90
LVDS CONNECTOR
93
DISPLAYPORT SUPPORT
94
DisplayPort Connector
97
LCD BACKLIGHT DRIVER
98
l
LCD Backlight Support
i
Contents
i
m
Sync
T17_MLB
T18_MLB
DRAGON
M97_MLB
M97_MLB
BEN
M97_MLB
BEN
M97_MLB
T18_MLB
T18_MLB
RAYMOND
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
RAYMOND
BEN
BEN
BEN
T18_MLB
YITE
YITE
SUMA
SUMA
SUMA
Date
08/22/2007
12/12/2007
03/13/2008
04/04/2008
04/21/2008
12/12/2007
12/12/2007
03/31/2008
12/12/2007
04/04/2008
04/04/2008
04/04/2008
04/04/2008
04/04/2008
04/04/2008
04/04/2008
06/26/2008
04/04/2008
03/08/2008
04/04/2008
12/12/2007
04/05/2008
03/31/2008
06/30/2008
05/09/2008
04/04/2008
04/22/2008
03/13/2008
05/23/2008
07/01/2008
04/04/2008
Page
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
(.csa)
Page
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
10
TABLE_TABLEOFCONTENTS_ITEM
11
TABLE_TABLEOFCONTENTS_ITEM
12
TABLE_TABLEOFCONTENTS_ITEM
13
TABLE_TABLEOFCONTENTS_ITEM
14
C
B
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
1
1 2 3 4 5 6 7 8 9
Table of Contents
2
System Block Diagram
3
Power Block Diagram
4
BOM Configuration
5
Revision History
6
JTAG Scan Chain
7
FUNC TEST
8
Power Aliases
9
SIGNAL ALIAS
10
CPU FSB
11
CPU Power & Ground
12
CPU Decoupling
13
eXtended Debug Port (XDP)
14
MCP CPU Interface
15
MCP Memory Interface
16
MCP Memory Misc
17
MCP PCIe Interfaces
18
MCP Ethernet & Graphics
19
MCP PCI & LPC
20
MCP SATA & USB
21
MCP HDA & MISC
22
MCP Power & Ground
24
MCP79 A01 Silicon Support
25
MCP Standard Decoupling
26
MCP Graphics Support
28
SB Misc
29
FSB/DDR3 Vref Margining
31
DDR3 SO-DIMM Connector A
32
DDR3 SO-DIMM Connector B
33
DDR3 Support
34
Right Clutch Connector
35
VENICE CONNECTOR
37
Ethernet PHY (RTL8211CL)
38
Ethernet & AirPort Support
39
ETHERNET CONNECTOR
Contents
(.csa)
100
71 72 73 74 75 76 77 78
CPU/FSB Constraints
101
Memory Constraints
102
MCP Constraints 1
103
MCP Constraints 2
104
Ethernet Constraints
106
SMC Constraints
107
M97 SPECIAL CONSTRAINTS
109
M97 RULE DEFINITIONS
ry
a
Contents
PVT BUILD
P
A
Schematic / PCB #’s
PART NUMBER
051-7537
820-2327 PCBF,MLB,M97
QTY
DESCRIPTION
SCHEM,MLB,M97
8
REFERENCE DES
SCH1
PCB1
CRITICAL
CRITICAL
CRITICAL
7 6
re
BOM OPTION
DIMENSIONS ARE IN MILLIMETERS
XX
X.XX
X.XXX
ANGLES
DO NOT SCALE DRAWING
THIRD ANGLE PROJECTION
5
4
3
DRAFTER
QA APPD
RELEASE
METRIC
MATERIAL/FINISH
APPLICABLE
DESIGN CK
SCALE
NONE
SIZE
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
TITLE
DRAWING NUMBER
D
APPLE INC.
SCHEM,MLB,M97
051-7537
SHT
1
REV.
A
A
OF
109
1
8 7
6
U1000
INTEL CPU
2.X OR 3.X GHZ
PENRYN
PG 9
5
U1300
XDP CONN
PG 12
4
3
2 1
FSB
D
PG 13
GPIOs
CLK
SYNTH
J4510
SATA Conn
PG 38
HD
J4520
SATA Conn
PG 38
C
ODD
J9000
LVDS CONN
J9400
DISPLAY PORT
CONN
PG 71
PG 71
1.05V/3GHZ.
1.05V/3GHZ.
SATA
PG 19
LVDS OUT
RGB OUT
DP OUT
HDMI OUT
DVI OUT
TMDS OUT
PG 17
UP TO 20 LANES3
PG 16
PCI-E
FSB INTERFACE
NVIDIA
MCP79
U1400
B
RGMII
PG 17
(UP TO FOUR PORTS)
800/1067/1333 MHz
PCI
PG 18
64-Bit
l
MAIN
MEMORY
PG 14
Misc
PG 24
SPI
PG 20
LPC
PG 18
PWR
CTRL
USB
PG 19
(UP TO 12 DEVICES)
i
SMB
PG 20
HDA
PG 20
2 UDIMMs
DDR2-800MHZ DDR3-1067/1333MHZ
J4720
Bluetooth
PG 40
4
3 8 9 2
10 5 6 7
m
J2900
DIMM
PG 25,26
U6100
J4700
TRACKPAD/
KEYBOARD
PG 40
DIMM’s
SPI
Boot ROM
PG 52
J4710
J4900
B,0
IR
i
PG 40
BSB
SMC
PG 41
n
J4710
CAMERA
PG 40
J6950
U4900
J5650,5600,5610,5611,5660,5720,5730,5750
FAN CONN AND CONTROL
Ser
FanADC
Prt
J3900,4635,4655
EXTERNAL
Connectors
SMB
CONN
PG 44
DC/BATT
PG 60
TEMP SENSOR
PG 41
POWER SENSE
PG 45
PG 48,49
J5100
Port80,serial
a
USB
PG 39
POWER SUPPLY
ry
LPC Conn
PG 43
D
C
B
re
P
A
J3400 U3900
Mini PCI-E
AirPort
PG 28
8
7 6
U3700
GB
E-NET
88E1116
PG 31
E-NET
Conn
PG 33
5
U6301 U6500U6400
Line In
Amp
PG 54
U6200
HEADPHONE
Amp Amp
J6800,6801,6802,6803
4
Audio Codec
PG 53
Audio Conns
PG 59
Line Out
PG 56PG 55
U6600,6605,6610,6620
Speaker
Amps
PG 57
System Block Diagram
SYNC_MASTER=T18_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
APPLE INC.
3
2
D
SCALE
NONE
051-7537
SHT
SYNC_DATE=12/12/2007
OF
2
109
1
A
REV.
A
8 7
6
5
4
3
M97 POWER SYSTEM ARCHITECTURE
2 1
D
ADAPTER
3S2P
(9 TO 12.6V)
C
PCI_RESET0#
15-1
B
A
AC
IN
J6950
MCP79
PM_SLP_S4_L
SLP_S3#
U1400
PM_SLP_S3_L
RC
DELAY
RC
DELAY
RC
DELAY
RC
DELAY
DCIN(16.5V)
11
15
15
Q3801
PM_SLP_S3_L
P1V8S0_EN
MCPDDR_EN
CPUVTTS0_EN
MCPCORES0_EN
6A FUSE
SMC_DCIN_ISENSE
BATT_POS_F
11-1
11-3
RC DELAY
11-2
RC DELAY
PM_ENET_EN_L
Q3802
16-3
16-2
16-3
16-4
01
U7970
A
Q7050
P3V3S3_EN
DDRREG_EN
P5VLTS3_EN
16
WOL_EN SMC_ADAPTER_EN
P1V05S0_EN
(S0)
P3V3S0_EN
(S0)
PBUSVSENS_EN
(S0)
P5VRTS0_EN_L
(S0)
CHGR_EN
(S5)
ENABLES
VIN
PBUS SUPPLY/ BATTERY CHARGER
ISL6258A
U7000
PPVBAT_G3H_CHGR_OUT
CHGR_BGATE
04-1
=DDRREG_EN
=DDTVTT_EN
P
16-2
16-2
16-2
16-1
SMC
U4900
BKLT_EN
VOUT
P16
P60
PPVBAT_G3H_CHGR_REG
01
PPBUS_G3H
04
SMC_PM_G2_EN
(S5)
02
VIN
GOSHAWK6P
U9701
ENA
ENETADD_EN
P1V2ENET_EN
re
02
VIN
1.5V
S5 S3
0.75V
TPS51116
U7300
MCPCORES0_EN
P5VLTS3_EN
11-2
D6905
D6905
U5403
SMC_BATT_ISENSE
A
RC DELAY
Q7800
PPVOUT_S0_LCDBKLT
VOUT
1.2V YUKON
U3850
VIN
RUN1
LTC34074
RUN2
VOUT1
VOUT2
14
02
7A FUSE
02
IMVP_VR_ON
25
06
P1V05_S5_EN
P5VRTS0_EN_L
05
P3V3S5_EN_L
SMC_PM_G2_EN
(1.9V) PPVOUT_ENET_AVDD_REG
VOUT1
(0.8A MAX CURRENT)
PP1V2_ENET_REG
VOUT2
(0.8A MAX CURRENT)
S3 TO S0
FETS
(Q7901 & Q7971)
MCP_CORE
EN2
EN1
VIN
5V (LT)
ISL6236
U7500
VOUT2
VOUT1
PPVIN_G3H_P3V42G3H
PBUS_VSENSE
PPBUS_G3H
CPUVTTS0_EN
(S0)
CPU VCORE
VIN
ISL9504B
VR_ON
U7400
02
VIN
EN1
EN2
TPS51125
PGOOD1,2
VOUT
PGOOD
5V
VOUT1
(RT)
VOUT2
3.3V
U7200
VREG3
P5V3V3_PGOOD
06
i
l
PP1V5_S0_FET
PP1V5_S3_REG
(12A MAX CURRENT)
PP0V75_S0_REG
(1A MAX CURRENT)
PPVCORE_S0_MCP_REG_R
(25A MAX CURRENT)
PP5VLT_S3_REG
(7A MAX CURRENT)
02
Q5315
V
U5480
A
SMC_CPU_ISENSE
VR_PWRGOOD_DELAY
P1V05S0_EN
1.05V (S5)
TPS62510
VOUT
U7750
PP5VRT_S0_REG
(4A MAX CURRENT)
PP3V3_S5_REG
(4A MAX
m
R5491
20
12
EN_PSV
CPUVTT
(1.05V)
TPS51117
V
PP1V05_S5_REG
08
CURRENT)
PP1V5_S0
R5490
ENABLE
3.425V G3HOT LT3470
VIN
U7600
PGOOD
SMC_CPU_VSENSE
1.05V SO
(Q7951 TO Q7953)
PPVCORE_S0_MCP
PP5VLT_S3
VOUT
U6990
02
VOUT
CPUVTTS0_PGOOD
PPVCORE_CPU_S0_REG
(44A MAX CURRENT)
28
FETS
Q7910
P3V3S3_EN
Q7930
P3V3S0_EN
Q3810
P3V3ENET_EN_L
21
PP3V42_G3H_REG
PPCPUVTT_S0_REG_R
(8A MAX CURRENT)
PP1V05_S0_FET
n
i
P3V3_ENET_FET
1.8V LDO
TPS79918DRV
U7760
PP1V8_S0_REG
03
23
R5492
26
22
PP3V3_S0_FET
PP3V3_S0 PP1V5_S0 PP1V05_S0
SMC PWRGD
RN5VD30A-F
U5000
a
VIN
EN
PP3V3_S3_FET
18
S0PGOOD_PWROK
19-1
04
PPCPUVTT_S0
4.6V AUDIO MAX8902A
U6201
PP5VRT_S0
PP3V3_S5
MCPCORESO_PGOOD
CPUVTTS0_PGOOD
P5V_LT_S3_PGOOD
RST*
V1 V2 V3
LTC2909
U7870
VOUT
P5V3V3_PGOOD
MCP79
MCP_PS_PWRGD
29
ry
PP4V6_AUDIO_ANALOG
U2850
17
07
13
RSMRST_PWRGD
09
24
SMC_ONOFF_L
05
ALL_SYS_PWRGD
SLP_S5_L SLP_S4_L SLP_S3_L
PS_PWRGD
CPUPWRGD(GPIO49)
U1400
CPU
U1000
SMC
RSMRST_OUT(P15)
PWRGD(P12)
IMVP_VR_ON(P16)
RSMRST_IN(P13)
PWR_BUTTON(P90)
P17(BTN_OUT)
SLP_S5_L(P95) SLP_S4_L(P94) SLP_S3_L(P93)
U4900
Power Block Diagram
SYNC_MASTER=DRAGON
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE INC.
LPC_RESET_L
CPU_PWRGD
PM_RSMRST_L
IMVP_VR_ON
RST*
SIZE
D
SCALE
06-1
31
30
FSB_CPURST_L
32
PM_PWRBTN_L SMC_RESET_L
DRAWING NUMBER
NONE
051-7537
SHT
10
25
SYNC_DATE=03/13/2008
3
PWRBTN*
PLTRST* RSMRST*
CPU_RESET#
PWRGOOD
RESET*
99ms DLY
PLT_RST*
NOTICE OF PROPRIETARY PROPERTY
D
C
B
A
REV.
A
OF
109
8
7 6
5
4
3
2
1
8 7
6
5
4
3
2 1
BOM Variants
BOM NUMBER
BOM Groups
D
Module Parts
PART NUMBER
C
Programmable Parts
B
Alternate Parts
PART NUMBER
152S0796 152S0685
152S0694 152S0138
104S0018 104S0023
BOM NAME
630-9554
630-9314
BOM GROUP
M97_COMMON
M97_MCP
M97_MISC
M97_PROGPARTS
M97_DEBUG_ENG
M97_DEBUG_PVT
M97_DEBUG_PROD
QTY
ALTERNATE FOR PART NUMBER
128S0218128S0093
152S0516152S0874
152S0586152S0847
514-0607514-0612
514-0608514-0613
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
337S3622
337S3624 CRITICAL
337S3625 CRITICAL
337S3646
337S3653 CRITICAL
337S3639
338S0540
338S0591
338S0603
338S0600
338S0635
338S0570
338S0563
341S2287 CRITICAL SMC_PROG
335S0610
341S2285
338S0375
341S2093
337S2983
341S2348
PCBA,MLB,BETTER,M97
PCBA,MLB,BEST,M97
DESCRIPTION
PDC,QJGL,QS,2.0,25W,1066,M0,3M,BGA
PDC,QDYD,QS,2.26,25W,1066,M0,3M,BGA
PDC,QDYJ,QS,2.4,25W,1066,M0,3M,BGA
PDC,SLG8E,PRQ,2.0,25W,1066,M0,3M,BGA
PDC,SL3BU,PRQ,2.26,25W,1066,C0,3M,BGA
PDC,SLB4N,PRQ,2.4,25W,1066,M0,3M,BGA
IC,GMCP,MCP79,35X35MM,BGA1437,A01
IC,GMCP,MCP79,35X35MM,BGA1437,A01P
IC,GMCP,MCP79,35X35MM,BGA1437,A01Q
IC,GMCP,MCP79,35X35MM,BGA1437,B01
IC,GMCP,MCP79,35X35MM,BGA1437,B02
IC,RTL8211CL,GIGE TRANSCEIVER,48P,TQFP
IC,SMC,HS8/2117,9X9MM,TLP,HF
IC,SMC,M97
IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP
IC,PRGRM,EFI BOOTROM,UNLOCK,M97
IC,CY7C63833,ENCORE II,USB CONTROLLER
IC,IR CONTROLLER,M97
IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794
IC,WELLSPRING CONTROLLER,M97
BOM OPTION
REF DES
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
BOM OPTIONS
COMMON,ALTERNATE,M97_MCP,M97_MISC,M97_DEBUG_PVT,M97_PROGPARTS
MCP_B02,MCP_PROD,MEMRESET_HW,MEMRESET_MCP,BOOT_MODE_USER,MCPSEQ_SMC,MCP_CS1_NO
ONEWIRE_PU,BKLT_PLL_NOT,DP_ESD,ENG_BMON,MIKEY
BOOTROM_PROG,SMC_PROG,IR_PROG,WELLSPRING_PROG
SMC_DEBUG_YES,XDP,XDP_CONN,LPCPLUS,VREFMRGN,TPAD_DEBUG
SMC_DEBUG_YES,XDP,LPCPLUS,NO_VREFMRGN
SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN
COMMENTS:
CYNTEC AS ALTERNATE
CYNTEC AS ALTERNATE
MAGLAYERS AS ALTERNATE
DELTA AS ALTERNATE
DALE/VISHAY AS ALTERNATE
KEMET AS ALTERNATE
MAGLAYERS AS ALTERNATE
MAGLAYERS AS ALTERNATE
FOXLINK AS ALTERNATE
FOXLINK AS ALTERNATE
REFERENCE DES
U1000
U1000
U1000
U1000 CPU_2_0GHZ
U1000
U1000 CPU_2_4GHZ
U1400
U1400
U1400
U1400
U1400
U3700
U4900
U4900
U6100
U6100
U4800
U4800
U5701
U5701
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL IR_BLANK
CRITICAL
CRITICAL
CRITICAL
BOM OPTIONS
M97_COMMON,CPU_2_0GHZ,EEE_2KA
M97_COMMON,CPU_2_4GHZ,EEE_1DJ
BOM OPTION
CPU_2_0GHZ_QS
CPU_2_26GHZ_QS
CPU_2_4GHZ_QS
CPU_2_26GHZ
SMC_BLANK
BOOTROM_BLANK
BOOTROM_PROG
WELLSPRING_BLANK
WELLSPRING_PROG
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
MCP_A01
MCP_A01P
MCP_A01Q
MCP_B01
MCP_B02
IR_PROG
re
Bar Code Labels / EEE #’s
l
PART NUMBER
826-4393
826-4393
826-4393
i
QTY
1
1
1
DESCRIPTION
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
i
m
REFERENCE DES
[EEE:2K9]
[EEE:2KA]
[EEE:1DJ]
CRITICAL
CRITICAL
CRITICAL
CRITICAL
a
n
BOM OPTION
EEE_2K9
EEE_2KA
EEE_1DJ
ry
M97 BOARD STACK-UP
Top
2 3 4 5 6 7 8
9 10 11
BOTTOM
SIGNAL GROUND
SIGNAL(High Speed) SIGNAL(High Speed)
GROUND
POWER POWER
GROUND
SIGNAL(High Speed)
SIGNAL(High Speed) GROUND SIGNAL
D
C
B
P
A
8
7 6
5
4
3
SYNC_MASTER=M97_MLB
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE INC.
2
BOM Configuration
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SIZE
D
SCALE
NONE
SHT
051-7537
4
1
A
REV.
A
OF
109
8 7
Revision History
6
5
4
3
2 1
D
D
ry
C
C
a
n
i
B
re
P
A
NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.
8
7 6
l
5
i
m
4
B
A
SYNC_MASTER=M97_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
APPLE INC.
3
2
D
SCALE
NONE
SHT
051-7537
5
1
REV.
OF
109
A
A
IN
B1
OE*
VCCB
B2 B3 B4
GND
A4
A3
A2
A1
VCCA
OUT
OUT
IN
IN
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
and/or level translator
To XDP connector
U1000
CPU
From XDP connector
or via level translator
From XDP connector
XDP connector
1.05V TO 3.3V LEVEL TRANSLATOR (M97: ON ICT FIXTURE)
XDP connector
U1400
MCP
6C7
10A6 10C6 13B3 71A3
NLSV4T244
JTAG_ALLDEV
U0600
10
7
8
9
1
12
6
5
4
3
2
UQFN
11
JTAG_ALLDEV
C0601
1
0.1UF
20%
2
CERM 402
10V
JTAG_ALLDEV
2
402
1
C0602
CERM
10V
20%
0.1UF
402
5%
MF-LF
1/16W
0
R0603
XDP
13B3
2
1
R0602
0
1/16W
5%
MF-LF
402
NOSTUFF
JTAG_ALLDEV
5%
10K
1/16W MF-LF
R0601
1
2
402
13C3
402
5%
MF-LF
1/16W
0
R0604
XDP
6C7
10B6 10C6 13B3 71A3
10B6 10C6 13B3 71A3
6C7
10A6 10C6 13B6 71A3
JTAG Scan Chain
SYNC_DATE=04/04/2008
SYNC_MASTER=BEN
6
109
A
051-7537
JTAG_MCP_TDO
JTAG_MCP_TDO_CONN
JTAG_MCP_TRST_L
JTAG_MCP_TMS
JTAG_MCP_TCK
XDP_TDO
XDP_TDO_CONN
JTAG_MCP_TDI
XDP_TMS
XDP_TRST_L
XDP_TMS
XDP_TCK XDP_TDI
=PP3V3_S0_XDP
XDP_TRST_L
XDP_TCK
=PP1V05_S0_CPU
JTAG_LVL_TRANS_EN_L
71A3
71A3
71A3
13D6
13B3
13B3
13B6
12B6
23C5
71A3
23C5
10C6
10C6
10C6
11C6
21B7
21B7
21B7
10C6
21B7
10B6
13D6
10A6
10A6
10D5
21B7 13C3
13C3
13B6
10B6
13C3
6C6
8C5
6C6
6C6
8D7
Preliminary
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
(NEED 4 TP)
RIGHT CLUTCH CONN
IPD_FLEX_CONN
DEBUG VOLTAGE
(NEED TO ADD 4 GND TP)
(NEED TO ADD 4 GND TP)
(NEED TO ADD 3 GND TP)
KBD BACKLIGHT CONN
(NEED TO ADD 2 GND TP)
KEYBOARD CONN
(NEED TO ADD 1 GND TP)
SATA HDD CONN
SPEAKER FUNC_TEST
(NEED TO ADD 2 GND TP)
(NEED 3 TP)
FRONT FLEX CONN
(NEED 3 TP)
SATA ODD CONN
THERMAL FUNC_TEST
(NEED 3 TP)
(NEED 3 TP)
(NEED 3 TP)
Functional Test Points
MIC FUNC_TEST
Fan Connectors
(NEED TO ADD 3 GND TP)
LVDS FUNC_TEST
(NEED TO ADD 5 GND TP)
(NEED 4 TP)
(NEED TO ADD 4 GND TP)
DC POWER CONN
BATT POWER CONN
BATT SIGNAL CONN
(NEED TO ADD 4 GND TP)
(NEED TO ADD 3 GND TP)
I12 I15 I16
I226
I227
I228
I229
I230
I231
I232 I233
I237
I238
I239
I245
I246 I247
I248
I249
I250
I251
I252
I253 I254
I255
I256 I257
I258
I259
I260
I261
I262
I264
I265
I266
I267
I268
I269
I270
I271
I272
I273 I274
I275
I276
I278
I279
I280
I281 I282
I283
I284
I285
I286
I287
I288
I289
I290
I291
I292
I293
I294
I295
I296
I297
I298
I299
I300
I301 I302
I303
I304
I305
I306
I307
I308
I309
I310 I311
I312
I313
I314
I315
I316
I317
I318
I319
I320
I321
I322
I323 I324
I325
I326
I327
I328 I329
I330 I331
I332
I333
I334
I335
I336
I337
I338
I339
I340
I341
I342
I343
I344 I345
I346
I347
I348
I349
I350
I351
I352
I353
I354 I355
I356
I357
I358
I359
I360
I361
I362
I363
I364
I365
I366
I367
I368
I369
I370 I371
I372
I373
I374
I375
I376
I377
I378
I379
I380
I381
I382
I383
I384
I385
I386
I387
I388
I389
I390
I391
I392
I393
7
A
109
051-7537
SYNC_MASTER=M97_MLB
FUNC TEST
SMC_BS_ALRT_L
TRUE
SMBUS_SMC_BSA_SCL
TRUE
SMBUS_SMC_BSA_SCL
TRUE
GND_BATT_CONN
TRUE
PP18V5_DCIN_FUSE
TRUE
SATA_ODD_R2D_N
TRUE
SATA_ODD_R2D_P
TRUE
SATA_ODD_D2R_C_N
TRUE
ADAPTER_SENSE
TRUE
SATA_ODD_D2R_C_P
TRUE
LED_RETURN_6
TRUE
LED_RETURN_5
TRUE
LED_RETURN_4
TRUE
LED_RETURN_3
TRUE
LED_RETURN_1
TRUE
LVDS_IG_A_CLK_F_P
TRUE
PP3V3_S0_LCD_F
TRUE
PPVOUT_S0_LCDBKLT
TRUE
LVDS_IG_A_DATA_N<1>
TRUE
LVDS_IG_A_DATA_N<2>
TRUE
LVDS_IG_A_DATA_P<0>
TRUE
LVDS_IG_A_DATA_N<0>
TRUE
PP3V3_LCDVDD_SW_F
TRUE
LVDS_IG_DDC_CLK
TRUE
LVDS_IG_DDC_DATA
TRUE
MCPTHMSNS_D2_N
TRUE
MCPTHMSNS_D2_P
TRUE
SPKRAMP_SUB_P_OUT
TRUE
SPKRAMP_SUB_N_OUT
TRUE
MIC_LO_CONN
TRUE
MIC_HI_CONN
TRUE
FAN_RT_PWM
TRUE
PP5VRT_S0
TRUE
FAN_RT_TACH
TRUE
TRUE
PP3V42_G3H
PP5V_SW_ODD
TRUE
LED_RETURN_2
TRUE
TRUE
IR_RX_OUT
TRUE
PP5V_S3_IR_R
TRUE
SMC_LID_R
TRUE
SYS_LED_ANODE_R
TRUE
PP3V42_G3H_LIDSWITCH_R
PPVBAT_G3H_CONN_F
TRUE
TRUE
SMC_BIL_BUTTON_DB_L
TRUE
SMBUS_SMC_BSA_SCL
TRUE
SMBUS_SMC_BSA_SCL
SPKRAMP_R_P_OUT
TRUE
SPKRAMP_R_N_OUT
TRUE
LVDS_IG_A_DATA_P<2>
TRUE
LVDS_IG_A_CLK_F_N
TRUE
SMC_ODD_DETECT
TRUE
LVDS_IG_A_DATA_P<1>
TRUE
PCIE_MINI_R2D_N
TRUE
PCIE_CLK100M_MINI_CONN_P
TRUE
PCIE_CLK100M_MINI_CONN_N
TRUE
USB_CAMERA_CONN_P
TRUE
SMBUS_SMC_A_S3_SDA
TRUE
CONN_USB2_BT_P
TRUE
CONN_USB2_BT_N
TRUE
MINI_RESET_CONN_L
TRUE
SMBUS_SMC_A_S3_SCL
TRUE
PCIE_MINI_D2R_N
TRUE TRUE
PCIE_MINI_R2D_P
TRUE
PCIE_MINI_D2R_P
TRUE
PP5V_S3_BTCAMERA_F
SPKRAMP_L_P_OUT
TRUE
TRUE
USB_CAMERA_CONN_N
PP5V_WLAN
TRUE
SPKRAMP_L_N_OUT
TRUE
MIC_SHLD_CONN
TRUE
SATA_HDD_R2D_P
TRUE TRUE
SATA_HDD_R2D_N
SATA_HDD_D2R_C_P
TRUE
Z2_CS_L
TRUE
TPAD_GND_F
TRUE
PP18V5_S3
TRUE
TRUE
PP3V3_S3_LDO
Z2_MOSI
TRUE
Z2_DEBUG3
TRUE
Z2_MISO
TRUE TRUE
Z2_BOOST_EN Z2_HOST_INTN
TRUE TRUE
Z2_BOOT_CFG1
TRUE
Z2_CLKIN Z2_KEY_ACT_L
TRUE
Z2_RESET
TRUE
PSOC_MOSI
TRUE
PSOC_MISO
TRUE
PSOC_SCLK
TRUE
SMBUS_SMC_A_S3_SDA
TRUE
SMBUS_SMC_A_S3_SCL
TRUE TRUE
PSOC_F_CS_L
PICKB_L
TRUE
TRUE
PP3V3_S3
TRUE
WS_KBD1
TRUE
PP3V42_G3H
TRUE
WS_KBD2
TRUE
WS_KBD3
TRUE
WS_KBD4
TRUE
WS_KBD6
TRUE
WS_KBD5
TRUE
WS_KBD7
TRUE
WS_KBD9
TRUE
WS_KBD8
TRUE
WS_KBD11
TRUE
WS_KBD10
TRUE
WS_KBD12
TRUE
WS_KBD13
WS_KBD14
TRUE TRUE
WS_KBD15_CAP
TRUE
WS_KBD17
TRUE
WS_KBD16_NUM
TRUE
WS_KBD19
TRUE
WS_KBD18
TRUE
WS_KBD20
TRUE
WS_KBD22
TRUE
WS_KBD21
TRUE
WS_KBD_ONOFF_L
TRUE
WS_KBD23
TRUE
WS_LEFT_SHIFT_KBD
TRUE
WS_LEFT_OPTION_KBD
TRUE
WS_CONTROL_KBD
TRUE
KBDLED_ANODE
Z2_SCLK
TRUE
TRUE
SATA_HDD_D2R_C_N
PPCPUVTT_S0
TRUE
PP1V8_S0
TRUE
PP3V3_S0
TRUE
PP1V5_S3
TRUE
PP5VLT_S3
TRUE
PP1V1R1V05_S5
TRUE
PP3V3_S5
TRUE
PP3V42_G3H
TRUE TRUE
PP3V3_ENET_PHY
PPBUS_G3H
TRUE
PP1V2R1V05_ENET
TRUE
PP5V_WLAN
TRUE
PP5V_SW_ODD
TRUE
PP3V3_S5_AVREF_SMC
TRUE
PP18V5_S3
TRUE
PP3V3_S3_LDO
TRUE TRUE
PP3V3_LCDVDD_SW_F
PPVOUT_S0_LCDBKLT
TRUE TRUE
BKL_VREF_4V9
PPVCORE_S0_CPU
TRUE
TRUE
PM_SLP_S3_L
PP3V3_S3
TRUE
PP1V5_S0
TRUE
TRUE
SATA_ODD_R2D_N
PP0V75_S0
TRUE
PPVCORE_S0_MCP
TRUE
SMC_PM_G2_EN
TRUE
TRUE
PP5V_S0_HDD_FLT
PCIE_WAKE_L
TRUE
MINI_CLKREQ_Q_L
TRUE
PP3V3_G3_RTC
TRUE
PP5V_S0_HDD_FLT
TRUE
TRUE
PP4V6_AUDIO_ANALOG
TRUE
PM_SLP_S4_L
PP5VRT_S0
TRUE
PP1V05_S0
TRUE
68D8 64D5
69C1
48C7
69C1
69C8
41A5
64C8
56A8
76D3
76D3
73A3
69B3
73B3
73B3
73B3
73B3
8D1
76D3
76D3
73B3
73B3
76D3
76D3
73D3
73D3
48C4
48D3
48C3
76D3
76D3
8D1
47C2
47C2
47C2
8D1
48D3
48C3
69B3
69C4
39C5
73A3
31C7
26D4
52D6
40A2
40B2
42C5
42C5
36B5
73A3
73A3
73A3
69B1
69B1
69B1
69B1
69C1
73B3
66B2
66C2
66C2
66C2
66C2
66C2
66C5
66B5
77D3
77D3
54C2
54C2
54D2
54D2
8D5
7C3
36D3
69B1
38C4
42C5
42C5
54C2
54C2
66C2
73B3
39B8
66C2
73D3
73D3
73D3
74C3
42D2
74B3
74B3
42D2
31C7
73D3
31C7
54C2
74C3
31C5
54C2
55A6
73A3
73A3
73A3
48C3
48C3
48C1
48B4
48C3
48C3
48C3
48C5
48C3
48C3
48C3
48C1
48C1
48C1
48C1
48C1
42D2
42D2
48C1
48C1
8D3
47D2
7C3
47D2
47D2
47D2
47D2
47D2
47D2
47D2
47D2
47C6
47D2
47C6
47C6
47C6
47C6
47D7
47D7
47D7
47D7
47D7
47D7
47B5
47B5
47B5
48C3
73A3
7B5
31C5
36D3
40B6
48C1
48B4
66C2
66B2
69B6
34B7
8D3
36B5
64D8
36A7
23C5
22A5
36A7
51D3
39C5
8D5
39C5
7A7
7A7
56A8
56D6
7C5
36B5
36B5
56D7
36B5
66B3
66B3
66B3
66B3
66B3
66B2
66C3
7C3
18B3
18B3
18B3
18B3
7C3
18A3
18A3
45B5
45B5
53B2
53B2
54B1
54B1
46B4
7D3
46C4
7B5
7C3
66B3
38A4
38B6
38B6
38B6
38B6
56A8
56A5
7A7
7A7
53C3
53C3
18B3
66B2
36B7
18B3
31C7
31C8
31C8
31B7
7B5
31B7
31B7
31A7
7B5
17B6
31C7
17B6
31B7
53B2
31B7
7C3
53A2
54D2
36A7
36A7
36A7
47C8
48B4
7C3
7C3
47C8
47C8
47C8
48C3
47D8
47C8
47B6
47C8
47C8
47C8
47C8
47C8
7C5
7D5
47C8
47D8
7D3
47C6
7A7
47C6
47C6
47C6
47C6
47C6
47C6
47C6
47C6
47C2
47C6
47C2
47C2
47C2
47C2
47C2
47C2
47C2
47C2
47C2
47C2
47C2
47C2
47C2
47B3
47B3
47B3
48A4
47C8
36A7
8D7
8B7
8C5
8D3
8C3
8B3
8B3
7A7
8B1
8C1
8B1
7D5
7B7
39D4
7C5
7C5
7C7
7C7
69A8
8D7
21C3
7B5
8B7
7B7
8C7
8C7
39D5
7C3
17B6
31C7
21C8
7C5
51A3
21C3
7D7
8C7
Preliminary
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
"G3H" RAILS
(MCP VCORE REG. OUTPUT)
"S0,S0M" RAILS
(DDR PWR AFTER SENSE RES.)
(CPU VCORE PWR)
(MCP VCORE AFTER SENSE RES)
206 mA (A01)
206 mA (A01)
PEX & SATA AVDD/DVDD aliases
(DDR PWR REG. OUTPUT)
"S3" RAILS
43 mA (A01)
57 mA (A01)
127 mA (A01)
206 mA (A01)
127 mA (A01)
127 mA (A01)
"ENET" RAILS
(BEFORE HIGH SIDE SENSING RES.)
(AFTER HIGH SIDE CPU VCORE
& CPU VTT SENSING RES.)
"S5" RAILS
Power Aliases
SYNC_MASTER=BEN
A
109
8
051-7537
=PP3V3_S5_SMBUS_MCP_1
=PP1V05_S5_REG
=PP3V3_S5_MCPPWRGD
=PP3V3_S5_ROM
=PP3V3_S5_MCP
=PP3V3_S5_LCD
=PP1V05_S0_MCP_PEX_DVDD
=PP3V3_S3_SMS
=PP3V3_S3_TPAD
=PP3V3_S3_MCP_GPIO
=PP3V3_S3_WLAN
=PP3V3_S3_VREFMRGN
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
PP3V3_S3
=PP5V_S0_CPU_IMVP
=PP5V_S3_EXTUSB
=PPBUS_S0_LCDBKLT =PPVIN_S0_MCPCORES0
=PPVIN_S5_1V5S30V75S0
=PPVIN_S5_CPU_IMVP
=PPVIN_S0_CPUVTTS0
=PPCPUVCORE_VTT_ISNS
=PPCPUVCORE_VTT_ISNS_R
=PPBUS_G3HRS5
=PPVIN_S3_5VLTS3
=PPVIN_S0_5VRTS0
=PPVIN_S5_3V3S5
=PPBUS_G3H
=PPVIN_S0_MCPREG_VIN
=PP18V5_G3H_CHGR
=PP18V5_DCIN_CONN
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 MM
MAKE_BASE=TRUE
VOLTAGE=12.6V
PPBUS_G3H_CPU_ISNS
VOLTAGE=12.6V
PPBUS_G3H
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 MM
MAKE_BASE=TRUE
PP18V5_G3H
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM
MAKE_BASE=TRUE
VOLTAGE=18.5V
=PP3V42_G3H_RTC_D
=PP3V42_G3H_BMON_ISNS
=PP1V05_S0_MCP_FSB
MAKE_BASE=TRUE
VOLTAGE=1.1V
MIN_LINE_WIDTH=0.6 MM
PP1V05_S0
MIN_NECK_WIDTH=0.2 MM
=PPVCORE_S0_CPU_VSENSE
=PP1V5_S3_MEM_A =PP1V5_S3_MEM_B
VOLTAGE=1.5V
PP1V5_S3
MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm
=PP1V5_FC_CON
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE
VOLTAGE=1.5V
PP1V5_S0_R
=PP1V5_S0_VMON
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 MM
PP1V1R1V05_S5
MIN_LINE_WIDTH=0.6 MM
MAKE_BASE=TRUE
=PP1V05_S0_MCP_SATA_DVDD1
=PP1V05_S0_MCP_SATA_DVDD0
=PP1V05_S0_MCP_SATA_AVDD1
=PP1V05_S0_MCP_SATA_AVDD0
=PP1V05_S0_MCP_PEX_DVDD1
=PP1V05_S0_MCP_PEX_DVDD0
=PP1V05_S0_MCP_PEX_AVDD1
=PP1V05_S0_MCP_PEX_AVDD0
=PP3V3_S5_MCP_GPIO
=PP1V05_S5_P1V05S0FET
=PP1V05_ENET_P1V05ENETFET
=PP3V42_G3H_TPAD =PP3V42_G3H_BATT
=PP5V_S0_HDD
=PP0V75_S0_MEM_VTT_B
=PP1V05_S0_MCP_PEX_DVDD
=PP1V5_S3_MEMRESET
=PP3V42_G3H_SMCUSBMUX
=PP1V5_S0_CPU
=PP1V8R1V5_S0_MCP_MEM
=PPVCORE_S0_CPU
=PP3V3_S0_ODD
=PPVIN_S5_SMCVREF =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_PWRCTL =PP3V42_G3H_CHGR
=PP3V42_G3H_REG
=PP3V42_G3H_LIDSWITCH
=PP1V5_S3_REG
=PP3V3_S3_FET
=PP1V05_S0_MCP_SATA_DVDD
=PP1V05_S0_MCP_PLL_UF
=PP1V5_S0_FET_R
=PP3V3R1V8_S0_MCP_IFP_VDD
=PP1V05_S0_FET
=PP1V5_S3_P1V5S0FET
=PP0V75_S0_MEM_VTT_A
=PP1V05_S0_MCP_HDMI_VDD =PP1V05_S0_VMON
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm
PP0V75_S0
MAKE_BASE=TRUE
VOLTAGE=0.75V
=PPVTT_S0_VTTCLAMP
=PP1V5_S0_FET
=PP5V_S0_LPCPLUS
=PP1V8_S0_REG
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 MM VOLTAGE=1.8V
PP1V8_S0
MIN_NECK_WIDTH=0.2 mm
=PP0V75_S0_REG
=PP1V05_S0_MCP_AVDD_UF
=PP1V05_S0_MCP_SATA_DVDD
PP1V05_S0_MCP_SATA_AVDD
MAKE_BASE=TRUE
=PP3V3_S5_LPCPLUS
=PP3V3_S5_SMC
=PP5V_S3_MCPDDRFET
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
PP3V3_ENET_PHY
VOLTAGE=3.3V
PP1V2R1V05_ENET
VOLTAGE=1.05V MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
=PP3V3_ENET_MCP_RMGT
=PP3V3_ENET_FET
=PP3V3_ENET_PHY
=PP1V05_ENET_FET
=PP1V05_ENET_MCP_PLL_MAC =PP1V05_ENET_MCP_RMGT =PP1V05_ENET_PHY
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.3 MM
PPVCORE_S0_CPU
VOLTAGE=1.25V
MIN_LINE_WIDTH=0.6 MM
=PP1V05_S0_CPU
=PPCPUVTT_S0_REG
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.6 MM
PPVCORE_S0_MCP_R
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 MM
=PPVCORE_S0_MCP_REG_R
PPVCORE_S0_MCP
MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM
=PPVCORE_S0_MCP
PP1V05_S0_MCP_PEX_AVDD
MAKE_BASE=TRUE
=PPVCORE_S0_CPU_REG
=PP1V5_S0
=PP1V5_S0_MEM_MCP
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm
PP1V5_S0
MAKE_BASE=TRUE
VOLTAGE=1.5V
=PP5V_S3_AUDIO_AMP
=PP5V_S3_AUDIO
=PP5V_S3_1V5S30V75S0
=PP5V_S3_BTCAMERA
=PP5V_S3_SYSLED =PP5V_S3_TPAD
=PP5VLT_S3_REG
=PP3V3_S5_MCP_A01 =PP3V3_S5_PWRCTL
=PP3V3_S5_P3V3S3FET
=PP3V3_S5_P1V05ENETFET
=PP3V3_S5_P3V3S0FET =PP3V3_S5_P1V05S5 =PP3V3_S5_P1V05FET
=PP3V3_S5_MEMRESET
MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.05V
PPCPUVTT_S0
=PP5VRT_S0_REG
PP5VRT_S0
MIN_LINE_WIDTH=0.6 mm VOLTAGE=5V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm
=PP1V05_S5_MCP_VDD_AUXC
=PP3V3_S5_REG
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.3 MM VOLTAGE=0.75V
PPVTT_S3_DDR_BUF
MIN_NECK_WIDTH=0.2 MM
=PP5V_S3_WLAN
=PP5V_S3_VTTCLAMP
=PP5V_S3_IR
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
PP5VLT_S3
VOLTAGE=5V MAKE_BASE=TRUE
=PP3V3_S3_SMBUS_SMC_MGMT
=PP3V3_S3_PDCISENS
PP3V42_G3H
VOLTAGE=3.42V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
MAKE_BASE=TRUE
=PP3V3_S3_SMBUS_SMC_A_S3
=PP5V_S0_FAN_RT
=PP3V3_S5_P3V3ENETFET
=PP5V_S0_ODD
=PP3V3_S0_MCP_VPLL_UF
=PP3V3_S0_HDCPROM
=PP3V3R1V5_S0_MCP_HDA
=PP3V3_S0_FET
=PPVCORE_S0_MCP_VSENSE
=PP1V05_S0_SMC_LS
=PP3V3_S0_XDP =PP3V3_S0_MCP =PP3V3_S0_MCP_DAC_UF
=PP3V3_S0_LPCPLUS =PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_MCP_PLL_UF
=PPVTT_S3_DDR_BUF
=PP5V_S3_P1V05S0FET
=PP3V3_S0_SMC =PP3V3_S0_MCPTHMSNS =PP3V3_S0_CPUTHMSNS
=PPMCPCORE_S0_REG
=PP5V_S0_CPUVTTS0
=PP5V_S0_DP_AUX_MUX
=PP5V_S0_KBDLED
=PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_SMBUS_MCP_0 =PP3V3_S0_FAN_RT =PP3V3_S0_AUDIO
=PP3V3_S0_IMVP
=PP3V3_S0_LCD =PP3V3_S0_MCP_GPIO
=PP5VR3V3_S0_MCPCOREISNS
=PP3V3_S5_DP_PORT_PWR
MIN_LINE_WIDTH=0.6 mm
PP3V3_S5
MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE
VOLTAGE=3.3V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 mm VOLTAGE=3.3V
PP3V3_S0
MIN_NECK_WIDTH=0.2 mm
=PP3V3_S0_DPCONN
=PPSPD_S0_MEM_B
=PPSPD_S0_MEM_A
=PP3V3_S0_VMON
=PP3V3_S0_PWRCTL
=PP3V3_S0_MCPDDRISNS =PP3V3_S0_CPUVTTISNS =PPVIN_S0_P1V8S0 =PP3V3_FC_CON =PP3V3_S0_TPAD
=PP3V3_S0_SMBUS_MCP_1
24C8
49D7
13D6
55B5
47D2
22D3
47C5
41D5
40D8
24B6
12B6
61B1
54D8
50C6
47C5
60D8
14B7
47C2
24C8
12D6
64D8
57D5
41C7
40C7
24A6
11C6
44D7
53D8
7C3
24A8
24B8
52D6
21A4
41C7
24B8
24D8
49D6
47B5
7D3
60D4
58C6
56D1
14A2
20C1
47B5
56B3
24D8
12B6
16C7
11D6
36D5
64D3
57C6
24D6
25D7
25D7
24D6
41C3
40C1
18D3
24C6
10D5
65A6
24D8
53C8
55D4
41B4
64C4
7D7
24C8
38D7
7B5
21D8
13D6
22B3
59D7
40D2
51D8
19D1
68B8
42C7
63B4
26B8
41B5
22B3
66C8
8B7
49B7
47A6
21A3
31A6
27D8
7B5
60D8
37C7
70D8
61C3
59C2
60C2
62C6
44B7
44B8
43B8
61D8
58B6
58B3
57C1
61C6
57D8
56B8
7C3
26D8
44A8
9C2
7D3
43D8
28D7
29D7
7D3
32C3
64A8
7C3
20B6
20B6
20A6
20B6
17A6
17B6
17A3
17B3
18C7
65B6
34C4
47B3
56A3
36A5
29A4
8A8
30C6
37B8
11B6
16C3
11B5
36B7
40B8
42C5
64B3
57A8
56B4
38B4
59B1
65D6
8A8
24C4
44C8
18B6
65A5
65D3
28A4
18A6
64A8
7D3
65B3
65D1
41D5
63C2
7D3
59C8
24D4
8B7
24C2
41B7
39D4
65D4
7C3
7C3
18C7
34D2
33D7
34B2
24A8
18D3
33D2
7D3
6D8
62C2
44D8
7D3
22D5
24D1
60D1
44C7
29B3
7D3
53B8
51A7
59C5
31B3
40B8
48C8
61C8
23C4
64B3
65D8
34C5
65C8
63B7
65A8
30C6
7D3
58B8
7D3
22A3
58B1
31C1
65A3
38B4
7D3
42B5
59B3
7A7
42D3
46C5
34D5
36D5
25B7
25B8
21D3
65C6
43D8
40D3
6D8
21C2
25D4
41C3
42D5
24B6
27D3
65B8
40A1
45C6
45D6
61C1
62C8
67B6
48A5
42C3
42D8
46C5
51A7
60D8
66C5
18C1
44D7
68D8
7C3
7D3
68A8
29A8
28A8
64B8
64A5
44C7
44B7
63C5
32C3
48A6
42C8
Preliminary
OUT
IN
OUT
OUT
OUT
OUT
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
VENICE BOARD STANDOFFS
DP HOTPLUG PULL-DOWN
FOR VENICE CARD
PCI-E ALIASES
UNUSED GPU LANES
UNUSED CRT & TV-OUT INTERFACE
UNUSED USB PORTS
AIRPORT CARD PRESENT SIGNAL
Extra FSB Pull-ups
Exist in MRB but not Intel designs. Here for CYA.
If found to be necessary, will move to page14.csa
LVDS ALIASES
UNUSED LVDS SIGNALS
1 1 1
(RSVD)
BSEL<2..0>
0 1 0
0 0 0
0 1 1 1 0 0
0 0 1
1 0 1 1 1 0
FSB MHZ
100
266 133
333
200
(166)
(400)
CPU FSB FREQUENCY STRAPS
BELOW CPU
LEFT OF CPU
BELOW MCP
UNUSED FW LANE
UNUSED EXPRESS CARD LANE
ETHERNET ALIASES
UNUSED ADDRESS PINS
SO-DIMM ALIASES
ABOVE CPU
DACS ALIASES
MISC MCP79 ALIASES
FAN STANDOFF
HEATSINK STANDOFFS
AUDIO CHASSIS GND
MLB MOUNTING SCREW HOLES
LAN ALIASES
USB ALIASES
EMI IO POGO PINS
EMI POGO PINS
1
3R2P5
Z0912
OMIT
Z0909
1
3R2P5
OMIT
1
OMIT
Z0911
3R2P5
1
3R2P5
OMIT
Z0908
STDOFF-4.5OD.98H-1.1-3.48-TH
1
Z0901
STDOFF-4.5OD.98H-1.1-3.48-TH
Z0904
1
STDOFF-4.5OD.98H-1.1-3.48-TH
Z0902
1
1
Z0903
STDOFF-4.5OD.98H-1.1-3.48-TH
R0930
47K
402
MF-LF
5% 1/16W
2
1
14A7 10A4 10B4 71C3
402
20K
1/16W
5% MF-LF
2
1
R0940
3R2P5
OMIT
1
Z0913
10B8 14A3 71C3
10B8 14A3 71C3
10D6 13B2 14A3 71C3
10D6 14B6 71C3
10B2 14A3 60C7 71B3
MF-LF
1/16W
NO STUFF
62
1
402
5%
2
R0960
MCP_A01&MCP_A01P&MCP_A01Q
1
5%
2
MF-LF
1/16W
402
220
R0950
1
2
200
MF-LF
5%
1/16W
NO STUFF
402
R0970
1/16W MF-LF
NO STUFF
150
1
402
5%
2
R0980
1
2
MF-LF
5%
1/16W
150
402
NO STUFF
R0990
STDOFF-4.5OD.98H-1.1-3.48-TH
Z0905
1
VENICE
Z0916
1
STDOFF-4.0OD3.0H-TH
VENICE
Z0915
1
STDOFF-4.0OD3.0H-TH
VENICE
Z0914
1
STDOFF-4.0OD3.0H-TH
1
TH
OMIT
Z0906
SL-3.10X2.70
1
3R2P5
OMIT
Z0910
1
SM
ZS0901
1.4DIA-SHORT-EMI-MLB-M97-M98
1
SM
ZS0905
2.0DIA-TALL-EMI-MLB-M97-M98
1
SM
2.0DIA-TALL-EMI-MLB-M97-M98
ZS0906
1
SM
2.0DIA-TALL-EMI-MLB-M97-M98
ZS0904
1
SM
ZS0907
2.0DIA-TALL-EMI-MLB-M97-M98
1
SM
1.4DIA-SHORT-EMI-MLB-M97-M98
ZS0902
1
SM
ZS0900
1.4DIA-SHORT-EMI-MLB-M97-M98
1
SM
ZS0903
1.4DIA-SHORT-EMI-MLB-M97-M98
SIGNAL ALIAS
SYNC_MASTER=M97_MLB
9
A
109
051-7537
MAKE_BASE=TRUE
VOLTAGE=0V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
PCIE_CLK100M_FC_P
MAKE_BASE=TRUE
USB_EXTC_N
=GND_CHASSIS_AUDIO_JACK
GND_CHASSIS_AUDIO
MAKE_BASE=TRUE
FW_PME_L
TP_FW_PME_L
MAKE_BASE=TRUE
TP_GMUX_JTAG_TCK_L
MAKE_BASE=TRUE
TP_GMUX_JTAG_TDO
MAKE_BASE=TRUE
TP_USB_EXCARD_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_USB_MINI_N
MEM_B_A<15>
MAKE_BASE=TRUE
PM_SLP_RMGT_L
=RTL8211_REGOUT
MAKE_BASE=TRUE
TP_FW_CLKREQ_L
CRT_IG_HSYNC
CRT_IG_B_COMP_PB
CRT_IG_R_C_PR
PCIE_EXCARD_R2D_C_N PCIE_EXCARD_PRSNT_L
MAKE_BASE=TRUE
TP_PCIE_EXCARD_R2D_C_N
PEG_CLK100M_P
MAKE_BASE=TRUE
TP_PEG_CLK100M_N
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PEG_D2R_P<15:0>
=PEG_D2R_P<15:0>
FW_CLKREQ_L
PCIE_FW_R2D_C_N
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PEG_R2D_C_P<15:0>
PCIE_CLK100M_FW_P
=GND_CHASSIS_AUDIO_MIC
TP_MEM_A_A15
MAKE_BASE=TRUE MAKE_BASE=TRUE
TP_MEM_B_A15
TP_PCIE_FW_R2D_C_P
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PEG_R2D_C_N<15:0>
MCP_TV_DAC_VREF
MCP_CLK27M_XTALOUT
MAKE_BASE=TRUE
TP_PCIE_EXCARD_D2R_N
PCIE_FW_D2R_P
MEM_A_A<15>
CRT_IG_VSYNC
NC_CRT_IG_VSYNC
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NC_CRT_IG_HSYNC
MAKE_BASE=TRUE
CRT_IG_G_Y_Y
NC_CRT_IG_G_Y_Y
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MCP_CLK27M_XTALIN
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MCP_TV_DAC_VREF
MCP_TV_DAC_RSET
MAKE_BASE=TRUE
NC_MCP_TV_DAC_RSET
NO_TEST=TRUE
PEG_PRSNT_L
=P3V3ENET_EN
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CRT_IG_R_C_PR
=PEG_R2D_C_P<15:0>
=P1V05ENET_EN
TP_PP3V3_ENET_PHY_VDDREG
MAKE_BASE=TRUE
=PP3V3_ENET_PHY_VDDREG
MAKE_BASE=TRUE
NC_RTL8211_REGOUT
=RTL8211_ENSWREG
MAKE_BASE=TRUE
TP_PEG_PRSNT_L
CPU_DPRSTP_L
FSB_CPURST_L
=PP1V05_S0_MCP_FSB
LVDS_IG_B_CLK_N
NC_LVDS_IG_B_DATA_P<3:0>
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_B_CLK_N
NO_TEST=TRUE
NO_TEST=TRUE
NC_LVDS_IG_B_DATA_N<3:0>
MAKE_BASE=TRUE
LVDS_IG_A_DATA_P<3> LVDS_IG_A_DATA_N<3> LVDS_IG_B_CLK_P
NO_TEST=TRUE
NC_LVDS_IG_B_CLK_P
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_A_DATA_P3
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_A_DATA_N3
=MCP_BSEL<0:2>
CPU_BSEL<0:2>
MAKE_BASE=TRUE
PEG_CLK100M_N
MAKE_BASE=TRUE
TP_PEG_CLK100M_P
MAKE_BASE=TRUE
TP_PCIE_FW_D2R_P
MAKE_BASE=TRUE
TP_PCIE_FW_D2R_N
PCIE_FW_D2R_N PCIE_FW_R2D_C_P
MAKE_BASE=TRUE
TP_PCIE_FW_PRSNT_L
PCIE_FW_PRSNT_L
MAKE_BASE=TRUE
TP_PCIE_FW_R2D_C_N
TP_PCIE_CLK100M_FW_N
MAKE_BASE=TRUE
PCIE_CLK100M_FW_N
PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_N
TP_PCIE_EXCARD_R2D_C_P
MAKE_BASE=TRUE
PCIE_EXCARD_R2D_C_P
EXCARD_CLKREQ_L
PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N
PCIE_MINI_PRSNT_L
USB_EXCARD_N
TP_USB_EXTD_N
MAKE_BASE=TRUE
TP_USB_EXCARD_P
MAKE_BASE=TRUE
USB_EXCARD_P
TP_PE4_PRSNT_L
TP_PCIE_PE4_D2RP TP_PCIE_PE4_D2RN
TP_PCIE_PE4_R2D_CN
MAKE_BASE=TRUE
TP_USB_EXTC_N
TP_USB_EXTC_P
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_PCIE_CLK100M_FW_P
=PEG_R2D_C_N<15:0>
USB_MINI_P
USB_EXTC_P
PCIE_FC_D2R_P
MAKE_BASE=TRUE
USB_MINI_N
TP_USB_MINI_P
MAKE_BASE=TRUE
TP_USB_EXTD_P
MAKE_BASE=TRUE
USB_EXTD_N
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CRT_IG_B_COMP_PB
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MCP_CLK27M_XTALOUT
MCP_CLK27M_XTALIN
MAKE_BASE=TRUE
NC_PEG_D2R_N<15:0>
NO_TEST=TRUE
=PEG_D2R_N<15:0>
CPU_NMI
CPU_INTR
FSB_BREQ0_L
LVDS_IG_B_DATA_N<3:0>
LVDS_IG_B_DATA_P<3:0>
GMUX_JTAG_TMS
FC_PRSNT_L
MAKE_BASE=TRUE
TP_PCIE_EXCARD_PRSNT_L
MAKE_BASE=TRUE
TP_PCIE_EXCARD_D2R_P
MAKE_BASE=TRUE
TP_EXCARD_CLKREQ_L
MAKE_BASE=TRUE
TP_PCIE_CLK100M_PE4P
TP_PE4_CLKREQ_L
TP_PCIE_CLK100M_PE4N
TP_PCIE_PE4_R2D_CP
TP_PCIE_CLK100M_EXCARD_P
MAKE_BASE=TRUE
PCIE_CLK100M_FC_N
MAKE_BASE=TRUE
PCIE_FC_D2R_N
MAKE_BASE=TRUE
PCIE_FC_R2D_C_N
MAKE_BASE=TRUE
PCIE_FC_R2D_C_P
MAKE_BASE=TRUE
FC_CLKREQ_L
MAKE_BASE=TRUE
TP_PCIE_CLK100M_EXCARD_N
MAKE_BASE=TRUE
GMUX_JTAG_TCK_L GMUX_JTAG_TDO
MCP_MII_PD
MAKE_BASE=TRUE
HPLUG_DET2
MAKE_BASE=TRUE
=MCP_MII_RXER =MCP_MII_COL =MCP_MII_CRS
=DVI_HPD_GMUX_INT
MAKE_BASE=TRUE
TP_CPU_PECI_MCP
CPU_PECI_MCP
TP_GMUX_JTAG_TMS
MAKE_BASE=TRUE
TP_GMUX_JTAG_TDI
MAKE_BASE=TRUE
GMUX_JTAG_TDI
USB_EXTD_P
24C8 22D3 14B7
73D3
54B8
17D6
55A4
17D3
14A2
31D7
17D3
73D3
17D6
73C3
73D3
73D3
73D3
32C5
20C3
54A8
19B7
29C5
21C3
33C2
18B3
18C3
18C3
17B3
17C6
17C3
17C6
17C6
17B3
17C3
54A3
18C6
18C6
17B6
28C5
18B3
18C3
18C6
17C6
34C5
17C3
34B5
33C2
33C6
8D7
18B3
18B3
18B3
18B3
17C3
17B6
17B3
17C6
17C3
17B6
17B6
17B3
17C6
17C3
17C3
17C6
20C3
20C3
17B6
17B6
17B6
17B3
17C3
20D3
20C3
32B5
20D3
20D3
18C6
17C6
18B3
18B3
19D4
32B3
17B3
17B6
17B3
17B3
32C5
32B5
32C6
32C6
32C5
17B6
17B6
18D6
18C6
18C6
18B6
14B6
19D4
20D3
Preliminary
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
IN IN IN
IN
OUT
IN
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
OUT OUT
OUT
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
BI BI BI BI BI
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
BI
BI BI BI
BI BI BI
BI
BI
BI BI
BI BI BI BI BI
BI
OUT
OUT
OUT
OUT
OUT
IN
IN IN IN IN IN
IN IN
IN IN
OUT
IN IN
IN
IN
IN IN
IN
IN
OUT
BI BI BI BI
TEST7
TEST6
DSTBP1* DINV1*
D31*
D30*
D25*
D11* D12* D13* D14*
DSTBP0* DINV0*
D9*
D8*
D7*
D6*
D19*
D18*
D0*
D32* D1* D2*
D5*
D16*
D20* D21* D22* D23* D24*
D26* D27* D28* D29*
DSTBN1*
GTLREF
TEST3 TEST4 TEST5
BSEL0 BSEL1 BSEL2
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*
D47*
DSTBN2* DSTBP2*
DINV2*
D48*
D49*
D50*
D51*
D52*
D53*
D54*
D55*
D56*
D57*
D58*
D59*
D60*
D61*
D62*
D63*
DSTBN3* DSTBP3*
DINV3*
COMP0 COMP1 COMP2 COMP3
DPRSTP*
DPSLP*
DPWR*
PWRGOOD
SLP*
PSI*
D17*
D4*
D3*
DSTBN0*
D15*
D10*
TEST2
TEST1
2 OF 4
DATA GRP 3 DATA GRP 2
MISC
DATA GRP 0DATA GRP 1
LOCK*
INIT*
A20M*
A6*
A3* A4*
A14*
A16*
REQ0* REQ1* REQ2* REQ3* REQ4*
BCLK1
BCLK0
THERMTRIP*
THERMDA
PROCHOT*
DBR*
TRST*
TMS
TDO
TDI
TCK
PREQ*
PRDY*
BPM3*
BPM2*
BPM1*
BPM0*
HITM*
HIT*
TRDY*
RS2*
RS1*
RS0*
RESET*
IERR*
BR0*
DBSY*
DRDY*
DEFER*
BNR*
RSVD4
RSVD3
RSVD2
RSVD1
RSVD0
SMI*
LINT1
LINT0
STPCLK*
FERR*
ADSTB1*
A35*
A34*
A33*
A32*
A31*
A30*
A29*
A28*
A19*
A18*
A17*
ADSTB0*
A13*
A12*
BPRI*
A20* A21* A22* A23* A24*
A26* A27*
A9*
A8*
A7*
A11*
A25*
THERMDC
IGNNE*
ADS*
A10*
A15*
A5*
RSVD5 RSVD6 RSVD7 RSVD8
1 OF 4
CONTROL
THERMAL
XDP/ITP SIGNALS
H CLK
ADDR GROUP1
ICH
RESERVED
ADDR GROUP0
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
CHANGE CPU FROM SOCKET TO BGA SYMBOL
SYNC FROM T18
CPU JTAG Support
PLACEMENT_NOTE (all 4 resistors):
402
MF-LF
54.9
1/16W
1%
2
1
R1000
402
MF-LF
1/16W
5%
68
2
1
R1002
1/16W
1%
MF-LF
1K
402
PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU.
2
1
R1005
402
1/16W
2.0K
MF-LF
1%
PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.
2
1
R1006
402
MF-LF
1/16W
1%
54.9
Place within 12.7mm of CPU
2
1
R1023
402
MF-LF
1/16W
1%
27.4
Place within 12.7mm of CPU
2
1
R1022
54.9
1% 1/16W MF-LF
402
Place within 12.7mm of CPU
2
1
R1021
402
MF-LF
1/16W
1%
27.4
Place within 12.7mm of CPU
2
1
R1020
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14D6 71D3
14D6 71D3
14D6 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14D6 71D3
14D6 71D3
14D6 71D3
9B2
14A3 60C7 71B3
14A3 71B3
14A3 71B3
14A3 71B3
60C7
13C7 14A3 71B3
14D3 71D3
14D3 71D3
14D3 71D3
14D3 71D3
14D3 71D3
14D3 71D3
14D3 71D3
14D3 71D3
14D3 71D3
14D3 71D3
14D3 71D3
14D3 71D3
14D3 71D3
14D3 71D3
14D3 71D3
14D3 71D3
14D6 71D3
14D6 71D3
14D6 71D3
14D3 71D3
14D3 71D3
14D3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14D6 71D3
14D6 71D3
14D6 71D3
9C2
71C3
9C2
71C3
9C2
71C3
14D6 71D3
14D6 71D3
14D6 71D3
14D6 71D3
14C6 71D3
14C6 71D3
14C6 71D3
14C6 71D3
14C6 71D3
14C6 71D3
14C6 71D3
14C6 71D3
14C6 71D3
14C6 71D3
14B6 71C3
14B6 71C3
14B6 71C3
14B6 71C3
14B6 71C3
14B6 71C3
14C6 71C3
14C6 71C3
14C6 71C3
14C6 71C3
14C6 71C3
14C6 71C3
14C6 71C3
14C6 71C3
14C6 71C3
14C6 71C3
14C6 71C3
14C6 71C3
14C6 71C3
14C6 71C3
14C6 71C3
14B6 71C3
14B6 71C3
14B6 71C3
14B3 71C3
14B3 71C3
14B6 71C3
14B6 71C3
9B2
14B6 71C3
14B6 71C3
14B6 71C3
14B6 71C3
13C6 71A3
13C6 71A3
13C6 71A3
13C6 71A3
13C6 71A3
13C6 71A3
6C4
10B6 71A3
13B3 26A3
14B6 40D4 60C8 71B3
45D5 77D3
14B7 40C4 71B3
14A3 71C3
9B2
13B2 14A3 71C3
14A6 71C3
14A6 71C3
14A6 71C3
14B6 71C3
6C6 6C7
10A6 13B6 71A3
6C6
10B6 13B3 71A3
6C6 6C7
10B6 13B3 71A3
6C6 6C7
10A6 13B3 71A3
45D5 77D3
14B3 71B3
14B3 71B3
14A3 71C3
14A3 71C3
9B2
14A3 71C3
9B2
14A3 71C3
14A3 71B3
14A3 71B3
14B7 71C3
402
0
1/16W MF-LF
5%
NO STUFF
21
R1010
402
1K
MF-LF
5%
1/16W
NO STUFF
2
1
R1011
1/16W
1%
MF-LF
402
54.9
2
1
R1001
402
1%
MF-LF
1/16W
54.9
21
R1090
402
54.9
1/16W MF-LF
1%
21
R1091
402
54.9
1/16W MF-LF
1%
21
R1093
14C6 71C3
14B6 71C3
14B6 71C3
14B6 71C3
402
649
1/16W MF-LF
1%
21
R1094
NO STUFF
1/16W
5%
1K
MF-LF 402
2
1
R1012
402
16V
10%
0.1uF
X5R
NO STUFF
PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU.
2
1
C1014
OMIT
PENRYN
FCBGA
C3
A26
AF1
AF26
C24
D25
C23
D7
D6
AE6
AD26
AF24
AA26
M26
H26
AE25
Y26
L26
J26
D24
B5
E5
AC20
U22
N24
H25
G24
K24
E23
AC23
AF22
AD23
AC22
E25
AD21
AE21
AC25
AF23
AE22
AD20
AC26
AB21
AB22
AA21
G25
AD24
AE24
AB25
AA24
AA23
W25
W24
Y23
W22
Y25
F23
U23
U25
T22
V23
V26
V24
AB24
Y22
N25
T25
G22
L25
R24
T24
P22
P23
P25
M23
L22
M24
L23
E26
R23
P26
K25
N22
H23
K22
F26
H22
J23
J24
F24
E22
Y1
AA1
U26
R26
C21
B23
B22
U1000
402
1%
MF-LF
1/16W
54.9
PLACEMENT_NOTE=Place R1092 near ITP connector (if present)
21
R1092
PENRYN
OMIT
FCBGA
AB6
G2
AB5
C7
B25
A24
AB3
AA6
AC5
D5
A3
D3
D22
D2
F6
B2
V3
T2
N5
M4
G3
F4
F3
C1
L1
J3
K2
H2
K3
D21
AC1
AC2
H4
B4
C6
B3
C4
D20
E4
G6
A5
F21
H5
E1
C20
F1
G5
AC4
AD1
AD3
AD4
E2
A21
A22
V1
M1
H1
J1
N2
M3
K5
L4
L5
AA3
AB2
AA4
W3
V4
U2
J4
Y4
W5
W2
T3
T5
R4
U1
Y5
U4
A6
W6
R3
U5
Y2
R1
P1
P4
L2
P2
P5
N3
U1000
109
051-7537
A
10
CPU FSB
SYNC_MASTER=T18_MLB
SYNC_DATE=12/12/2007
XDP_TDI
XDP_TDO
XDP_TMS
FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_DSTB_L_N<0> FSB_DSTB_L_P<0> FSB_DINV_L<0>
FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_DSTB_L_N<1> FSB_DSTB_L_P<1> FSB_DINV_L<1>
CPU_BSEL<0> CPU_BSEL<1> CPU_BSEL<2>
TP_CPU_TEST5
TP_CPU_TEST3
TP_CPU_TEST6
TP_CPU_TEST7
FSB_CPUSLP_L CPU_PSI_L
CPU_PWRGD
FSB_DPWR_L
CPU_DPSLP_L
CPU_DPRSTP_L
FSB_DINV_L<3>
FSB_DSTB_L_N<3> FSB_DSTB_L_P<3>
FSB_D_L<63>
FSB_D_L<62>
FSB_D_L<61>
FSB_D_L<60>
FSB_D_L<59>
FSB_D_L<58>
FSB_D_L<57>
FSB_D_L<56>
FSB_D_L<55>
FSB_D_L<54>
FSB_D_L<53>
FSB_D_L<52>
FSB_D_L<51>
FSB_D_L<50>
FSB_D_L<49>
FSB_D_L<48>
FSB_DINV_L<2>
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_D_L<47>
FSB_D_L<46>
FSB_D_L<45>
FSB_D_L<44>
FSB_D_L<43>
FSB_D_L<42>
FSB_D_L<41>
FSB_D_L<40>
FSB_D_L<39>
FSB_D_L<38>
FSB_D_L<37>
FSB_D_L<36>
FSB_D_L<35>
FSB_D_L<34>
FSB_D_L<33>
FSB_D_L<32>
XDP_TRST_L
XDP_TCK
CPU_GTLREF CPU_TEST1 CPU_TEST2
CPU_TEST4
CPU_COMP<1>
CPU_COMP<0>
CPU_COMP<2> CPU_COMP<3>
=PP1V05_S0_CPU
FSB_LOCK_L
CPU_INIT_L
FSB_A_L<3> FSB_A_L<4>
FSB_A_L<14>
FSB_A_L<16>
FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>
FSB_CLK_CPU_N
FSB_CLK_CPU_P
PM_THRMTRIP_L
CPU_THERMD_P
CPU_PROCHOT_L
XDP_DBRESET_L
XDP_TRST_L
XDP_TMS
XDP_TDO
XDP_TDI
XDP_TCK
XDP_BPM_L<5>
XDP_BPM_L<4>
XDP_BPM_L<3>
XDP_BPM_L<2>
XDP_BPM_L<1>
XDP_BPM_L<0>
FSB_HITM_L
FSB_HIT_L
FSB_TRDY_L
FSB_RS_L<2>
FSB_RS_L<1>
FSB_RS_L<0>
FSB_CPURST_L
CPU_IERR_L
FSB_BREQ0_L
FSB_DBSY_L
FSB_DRDY_L
FSB_DEFER_L
FSB_BNR_L
TP_CPU_RSVD_B2
TP_CPU_RSVD_V3
TP_CPU_RSVD_T2
TP_CPU_RSVD_N5
TP_CPU_RSVD_M4
FSB_ADSTB_L<0>
FSB_A_L<13>
FSB_A_L<12>
FSB_BPRI_L
FSB_A_L<9>
FSB_A_L<8>
FSB_A_L<7>
FSB_A_L<11>
CPU_THERMD_N
FSB_ADS_L
FSB_A_L<10>
FSB_A_L<15>
FSB_A_L<5>
TP_CPU_RSVD_F6 TP_CPU_RSVD_D2 TP_CPU_RSVD_D22 TP_CPU_RSVD_D3
FSB_A_L<17> FSB_A_L<18> FSB_A_L<19>
FSB_A_L<21>
FSB_A_L<20>
FSB_A_L<22> FSB_A_L<23> FSB_A_L<24>
FSB_A_L<26>
FSB_A_L<25>
FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32> FSB_A_L<33> FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<1>
CPU_A20M_L CPU_FERR_L CPU_IGNNE_L
CPU_STPCLK_L
CPU_SMI_L
CPU_NMI
CPU_INTR
FSB_A_L<6>
71A3
71A3
71A3
13D6
71A3
13B3
13B3
13B6
12B6
13B3
71A3
10C6
10C6
10C6
11C6
10C6
10C6
6C7
6C7
6C7
71B3
8D7
6C6
6C4
6C6
6C6
6C6
27B1
71A3
71A3
71A3
71B3
6D8
71B3
Preliminary
OUT OUT OUT OUT OUT OUT OUT
OUT
OUT
VCC
VCCP
VCCA
VID0 VID1 VID2 VID3 VID4 VID5 VID6
VCCSENSE
VSSSENSE
VCC
3 OF 4
VSS VSS
4 OF 4
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
2500 mA (after VCC stable)
4500 mA (before VCC stable)
(Socket-P KEY)
41 A (SV HFM)
130 mA
(CPU CORE POWER)
(CPU INTERNAL PLL POWER 1.5V)
(CPU IO POWER 1.05V)
23 A (LV Design Target)
44 A (SV Design Target)
(BR1#)
CHANGE CPU FROM SOCKET TO BGA SYMBOL
SYNC FROM T18
Current numbers from Merom for Santa Rosa EMTS, doc #20905.
30.4 A (SV LFM)
60C7 71A3
60C7 71A3
60C7 71A3
60C7 71A3
60C7 71A3
60C7 71A3
R1101
1
2
MF-LF 402
100
1% 1/16W
PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs.
60C7 71A3
60A5 71A3
60A5 71A3
U1000
A7
A9
B9 B10
B12
B14 B15
B17
B18 B20
C9 C10
A10
C12
C13 C15
C17
C18
D9
D10
D12 D14
D15
A12
D17
D18
E7
E9
E10
E12 E13
E15
E17 E18
A13
E20
F7
F9
F10 F12
F14
F15 F17
F18
F20
A15
AA7
AA9
AA10
AA12
AA13 AA15
AA17
AA18 AA20
AB9
A17
AC10 AB10
AB12 AB14
AB15
AB17 AB18
AB20
AB7
AC7
A18
AC9
AC12
AC13 AC15
AC17 AC18
AD7
AD9 AD10
AD12
A20
AD14 AD15
AD17
AD18 AE9
AE10 AE12
AE13
AE15 AE17
B7
AE18
AE20 AF9
AF10 AF12
AF14 AF15
AF17
AF18 AF20
B26 C26
G21 V6
R21
R6
T21 T6
V21
W21
J6
K6 M6
J21 K21
M21
N21 N6
AF7
AD6 AF5
AE5
AF4 AE3
AF3
AE2
AE7
FCBGA
OMIT
PENRYN
U1000
A4 A8
B11
W1
W4 W23
W26 Y3
Y6 Y21
Y24
AA2 AA5
B13
AA8
AA11 AA14
AA16
AA19 AA22
AA25 AB1
AB4
AB8
B16
AB11
AB13
AB16 AB19
AB23
AB26 AC3
AC6
AC8
AC11
B19
AC14
AC16 AC19
AC21
AC24 AD2 AD5 AD8
AD11 AD13
B21
AD16
AD19 AD22
AD25
AE1
AE4 AE8
AE11
AE14 AE16
B24
AE19
AE23 AE26
A2 AF6
AF8
AF11 AF13
AF16
AF19
C5
AF21
A25
AF25
B1
C8
C11
C14
A11
C16
C19
C2 C22
C25
D1
D4
D8
D11
D13
A14
D16 D19
D23
D26
E3
E6
E8
E11 E14
E16
A16
E19
E21 E24
F5
F8
F11
F13 F16
F19
F2
A19
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
A23
J2
J5
J22
J25
K1
K4
K23 K26
L3
L6
AF2
L21
L24
M2
M5
M22 M25
N1
N4
N23
N26
B6
P3
P6
P21 P24
R2
R5 R22
R25 T1
T4
B8
T23 T26
U3 U6
U21 U24
V2
V5
V22 V25
FCBGA
PENRYN
OMIT
R1100
1
2
MF-LF 402
100
1% 1/16W
PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs.
CPU Power & Ground
SYNC_MASTER=T18_MLB
SYNC_DATE=12/12/2007
051-7537
A
11
109
=PPVCORE_S0_CPU
CPU_VID<6>
CPU_VID<5>
CPU_VID<4>
CPU_VID<3>
=PP1V5_S0_CPU
=PP1V05_S0_CPU
CPU_VID<2>
CPU_VID<1>
CPU_VID<0>
=PPVCORE_S0_CPU
CPU_VCCSENSE_P
CPU_VCCSENSE_N
13D6 12B6
12D6
10D5
12D6
11B5
12B6
8D7
11D6
8D7
8B7
6D8
8D7
Preliminary
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
PLACEMENT_NOTE (C1200-C1219):
1x 10uF, 1x 0.01uF
VCCA (CPU AVdd) DECOUPLING
VCCP (CPU I/O) DECOUPLING
1x 330uF, 6x 0.1uF 0402
SYNC FROM T18 REMOVE NO STUFF CAPS C1220 TO C1231
CPU VCore HF and Bulk Decoupling
REMOVE C1244 & C1245 CHANGE C1240-C1243 AND C1260 FROM 128S0241(9 MILLI-OHM) TO 128S0231(6 MILLI-OHM)
PLACEMENT_NOTE (C1240-C1243):
4X 330UF. 20X 22UF 0805
805
Place inside socket cavity on secondary side.
2
1
C1206
22UF
20%
6.3V CERM-X5R
CRITICAL
32
1
C1260
20%
330UF
CRITICAL
POLY-TANT
PLACEMENT_NOTE=Place C1260 between CPU & NB.
D2T-SM2
2.0V
1
C1204
805
22UF
20%
6.3V CERM-X5R
Place inside socket cavity on secondary side.
2
CRITICAL
2
1
C1216
805
22UF
20%
6.3V CERM-X5R
Place inside socket cavity on secondary side.
CRITICAL
22UF
2
1
C1214
805
20%
6.3V CERM-X5R
Place inside socket cavity on secondary side.
CRITICAL
2
1
C1208
805
22UF
20%
6.3V CERM-X5R
Place inside socket cavity on secondary side.
CRITICAL
2
1
C1203
CERM-X5R
6.3V
20%
22UF
805
Place inside socket cavity on secondary side.
CRITICAL
2
1
C1207
CERM-X5R
6.3V
20%
22UF
805
Place inside socket cavity on secondary side.
CRITICAL
22UF
2
1
C1202
805
20%
6.3V CERM-X5R
Place inside socket cavity on secondary side.
CRITICAL
C1201
2
1
CERM-X5R
6.3V
20%
22UF
805
Place inside socket cavity on secondary side.
CRITICAL
2
1
C1213
CERM-X5R
6.3V
20%
805
22UF
Place inside socket cavity on secondary side.
CRITICAL
2
1
C1212
22UF
805
20%
6.3V CERM-X5R
Place inside socket cavity on secondary side.
CRITICAL
2
1
C1211
CERM-X5R
6.3V
20%
22UF
805
Place inside socket cavity on secondary side.
CRITICAL
2
1
C1219
CERM-X5R
6.3V
20%
22UF
805
Place inside socket cavity on secondary side.
CRITICAL
2
1
C1200
805
22UF
20%
6.3V CERM-X5R
Place inside socket cavity on secondary side.
CRITICAL
22UF
C1210
2
1
805
20%
6.3V CERM-X5R
Place inside socket cavity on secondary side.
CRITICAL
2
CERM
1
C1261
20%
0.1UF
402
10V
2
1
C1205
CERM-X5R
6.3V
20%
22UF
805
Place inside socket cavity on secondary side.
CRITICAL
2
1
C1209
CERM-X5R
6.3V
20%
22UF
805
Place inside socket cavity on secondary side.
CRITICAL
2
1
C1215
CERM-X5R
6.3V
20%
22UF
805
Place inside socket cavity on secondary side.
CRITICAL
2
1
C1217
CERM-X5R
6.3V
20%
22UF
805
Place inside socket cavity on secondary side.
CRITICAL
2
1
C1262
20% CERM
0.1UF
402
10V
2
1
C1263
20% CERM
0.1UF
402
10V
2
1
C1264
20% CERM
0.1UF
402
10V
2
1
C1265
20% CERM
0.1UF
402
10V
2
1
C1266
20% CERM
0.1UF
402
10V
2
1
C1218
805
22UF
20%
6.3V CERM-X5R
Place inside socket cavity on secondary side.
CRITICAL
2
1
C1251
PLACEMENT_NOTE=Place C1281 near CPU pin B26.
0.01UF
16V CERM 402
10%
2
1
C1250
10uF
20% X5R
603
6.3V
3 2
1
C1240
Place on secondary side.
POLY-TANT
330UF
20%
CRITICAL
D2T-SM2
2.0V 2.0V
D2T-SM2
20%
330UF
CRITICAL
POLY-TANT
Place on secondary side.
C1241
1
23
2.0V
Place on secondary side.
1
23
CRITICAL
C1242
330UF
20%
POLY-TANT D2T-SM2
2.0V
D2T-SM2
20%
330UF
CRITICAL
POLY-TANT
Place on secondary side.
C1243
1
23
051-7537
A
12
109
SYNC_MASTER=RAYMOND
SYNC_DATE=03/31/2008
CPU Decoupling
=PP1V5_S0_CPU
=PPVCORE_S0_CPU
=PP1V05_S0_CPU
13D6 11C6
11D6
10D5
11B6
11B5
8D7
8B7
8D7
6D8
Preliminary
IN
BI
BI
BI BI
OUT
IN
BI
IN
IN IN
OUT
OUT OUT
BI BI
BI BI
BI BI
BI BI
OUT
IN
IN IN
IN OUT OUT OUT
OUT
NC
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
RENAME XDP_TDO TO XDP_TDO_CONN
RENAME JTAG_MCP_TDO TO JTAG_MCP_TDO_CONN
CHANGE STANDARD XDP CONNECTOR TO SMALLER ONE 516S0625
VCC_OBS_CD
TCK0
VCC_OBS_AB
HOOK3
516S0625
MCP79-specific pinout
SYNC FROM T18
OBSDATA_C0
OBSDATA_D3
TDO
TDI
ITPCLK/HOOK4 ITPCLK#/HOOK5
RESET#/HOOK6 DBR#/HOOK7
OBSFN_C0
OBSFN_D0
SCL
SDA
OBSFN_B1
OBSDATA_A0
OBSFN_A1
OBSFN_A0
OBSFN_B0
TRSTn
HOOK2
HOOK1
TMS XDP_PRESENT#
OBSDATA_B0 OBSDATA_D0
OBSDATA_A3
OBSDATA_D2
OBSDATA_C2
OBSFN_C1
OBSDATA_A2
TCK1
PWRGD/HOOK0
OBSDATA_B3
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
OBSDATA_C3
OBSDATA_C1
OBSDATA_B1
OBSDATA_B2
OBSDATA_D1
OBSFN_D1
OBSDATA_A1
10B2 14A3 71B3
1K
402
MF-LF
XDP
5%
1/16W
21
R1399
21C3 42D8 74B3
21C3 42D8 74B3
XDP
1%
MF-LF
54.9
402
1/16W
2
1
R1315
402
16V
10%
0.1uF
X5R
XDP
2
1
C1300
CRITICAL
6-1747769-0
F-ST-SM
9
87
60
6
59
58
5655
5453
5251
50
5
49
4847
4645
4443
4241
40
4
39
3837
3635
3433
3231
3029
2827
2625
2423
2221
2019
1817
1615
1413
1211
10
1
64
63
62
61
J1300
XDP_CONN
2
3
57
402
16V
10%
0.1uF
X5R
XDP
2
1
C1301
10C5 71A3
10C6 71A3
6C6 6C7
10A6 10C6 71A3
9B2
10D6 14A3 71C3
XDP
402
MF-LF
1/16W
5%
1K
PLACEMENT_NOTE=Place close to CPU to minimize stub.
21
R1303
10C6 71A3
10C6 71A3
10C6 71A3
10C6 71A3
6C5
21B7
6C5
21B7 23C5
6C5
21B7 23C5
19D7 74D3
19D7 74D3
19D7 74D3
19D7 74D3
19D7 74D3
19D7 74D3
19D7 74D3
19D7 74D3
6C5
21B7
6C3
14A3 71B3
14A3 71B3
6C3
6C6 6C7
10A6 10C6 71A3
6C6
10B6 10C6 71A3
6C6 6C7
10B6 10C6 71A3
10C6 26A3
19C4 23C5
SYNC_DATE=12/12/2007
051-7537
SYNC_MASTER=T18_MLB
13
A
109
eXtended Debug Port (XDP)
TP_XDP_OBSDATA_B0
XDP_BPM_L<2>
=PP3V3_S0_XDP =PP1V05_S0_CPU
FSB_CLK_ITP_P FSB_CLK_ITP_N
FSB_CPURST_L
CPU_PWRGD
XDP_BPM_L<4>
XDP_OBS20
XDP_DBRESET_L
XDP_TDO_CONN XDP_TRST_L XDP_TDI XDP_TMS
XDP_BPM_L<1>
XDP_BPM_L<5>
XDP_BPM_L<3>
XDP_BPM_L<0>
TP_XDP_OBSFN_B0 TP_XDP_OBSFN_B1
TP_XDP_OBSDATA_B1
TP_XDP_OBSDATA_B2 TP_XDP_OBSDATA_B3
XDP_PWRGD
PM_LATRIGGER_L JTAG_MCP_TCK
SMBUS_MCP_0_DATA SMBUS_MCP_0_CLK
XDP_TCK
XDP_CPURST_L
MCP_DEBUG<7>
MCP_DEBUG<6>
MCP_DEBUG<5>
JTAG_MCP_TMS
JTAG_MCP_TDI
MCP_DEBUG<3>
JTAG_MCP_TRST_L
JTAG_MCP_TDO_CONN
MCP_DEBUG<0> MCP_DEBUG<1>
MCP_DEBUG<2>
MCP_DEBUG<4>
12B6 11C6 10D5
8C5
8D7
6D8
6D8
71A3
Preliminary
IN IN IN
IN
OUT
BI
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
BI BI BI
BI BI BI
BI BI BI
BI BI BI
BI BI
BI
BI
BI
BI
BI
BI BI BI
BI
BI
BI
IN
BI
OUT
OUT OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT OUT OUT OUT OUT
OUT
OUT OUT OUT OUT OUT
OUT OUT
IN
BI BI
CPU_BR0#
CPU_BNR#
BCLK_OUT_NB_N
CPU_BR1#
CPU_REQ4#
CPU_ADS#
CPU_A27#
CPU_A26#
CPU_A25#
CPU_A34#
CPU_D62#
CPU_D61#
CPU_D60#
CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_A32#
CPU_A22# CPU_A23# CPU_A24#
CPU_REQ3#
CPU_REQ2#
CPU_DBI3#
CPU_D14#
CPU_D13#
CPU_D12#
CPU_D11#
CPU_D10#
CPU_DPWR#
CPU_RS1#
BCLK_VML_COMP_GND
CPU_COMP_VCC
CPU_TRDY#
CPU_PROCHOT#
CPU_BSEL0
CPU_RS2#
CPU_BSEL1
BCLK_IN_P
BCLK_OUT_CPU_N
CPU_PWRGD
CPU_DSTBP0#
CPU_DSTBP1#
CPU_DBI1#
CPU_DBI0#
CPU_DSTBN1#
CPU_DSTBN0#
CPU_DBI2#
CPU_DSTBP2# CPU_DSTBN2#
CPU_DSTBP3#
CPU_A4#
CPU_DSTBN3#
CPU_A3#
CPU_A5#
CPU_A9#
CPU_A8#
CPU_A6# CPU_A7#
CPU_A12#
CPU_A14#
CPU_A13#
CPU_A11#
CPU_A15# CPU_A16#
CPU_A19#
CPU_A17# CPU_A18#
CPU_A20# CPU_A21#
CPU_A35#
CPU_A33#
CPU_ADSTB0#
CPU_REQ0#
CPU_LOCK#
CPU_HIT# CPU_HITM#
CPU_FERR#
CPU_THERMTRIP#
CPU_PECI
CPU_COMP_GND
CPU_D0# CPU_D1#
CPU_D3#
CPU_D2#
CPU_D4# CPU_D5# CPU_D6#
CPU_D8#
CPU_D7#
CPU_D9#
CPU_D15#
CPU_D17# CPU_D18#
CPU_D16#
CPU_D19# CPU_D20# CPU_D21#
CPU_D23#
CPU_D22#
CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36#
CPU_D38#
CPU_D37#
CPU_D39# CPU_D40# CPU_D41#
CPU_D43#
CPU_D42#
CPU_D44# CPU_D45# CPU_D46# CPU_D47#
CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59#
CPU_D63#
CPU_BPRI#
CPU_DEFER#
BCLK_OUT_CPU_P
BCLK_OUT_ITP_P BCLK_OUT_ITP_N
BCLK_OUT_NB_P
BCLK_IN_N
CPU_A20M#
CPU_NMI
CPU_INTR
CPU_SMI#
CPU_RESET#
CPU_SLP#
CPU_DPSLP#
CPU_STPCLK# CPU_DPRSTP#
CPU_D51#
CPU_D50#
CPU_D49#
CPU_D48#
CPU_ADSTB1#
CPU_IGNNE#
CPU_INIT#
BCLK_VML_COMP_VDD
CPU_RS0#
+V_DLL_DLCELL_AVDD +V_PLL_MCLK +V_PLL_FSB +V_PLL_CPU
CPU_A10#
CPU_BSEL2
CPU_DBSY# CPU_DRDY#
CPU_REQ1#
FSB
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
Loop-back clock for delay matching.
(MCP_BSEL<2>) (MCP_BSEL<1>) (MCP_BSEL<0>)
20 mA 29 mA 15 mA
206 mA
270 mA (A01)
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
9C1
9C1
9C1
10C8 71C3
9B2
10D6 13B2 71C3
10B2 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
10D8 71D3
10D8 71D3
10D8 71D3
10D8 71D3
10D8 71D3
10D8 71D3
10D8 71D3
10D8 71D3
10D8 71D3
10D8 71D3
10D8 71D3
10D8 71D3
10D8 71D3
10D8 71D3
10C8 71C3
10C8 71C3
10C8 71C3
10C8 71C3
10C8 71C3
10C8 71C3
10C8 71C3
10C8 71C3
10C8 71C3
10C8 71C3
10C8 71C3
10C8 71C3
10C8 71C3
10C8 71C3
10C8 71C3
10C8 71C3
10C8 71C3
10C4 71D3
10C4 71D3
10C4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
10D8 71C3
10C8 71C3
10D8 71C3
10D8 71C3
10D8 71C3
10D8 71C3
10D8 71C3
10D6 71C3
10D6 71C3
9B2
10D6 71C3
10D6 71C3
10C6 71C3
10D6 71C3
10D6 71C3
10C6 71C3
10D6 71C3
10D6 71C3
10D6 71C3
10D6 71C3
10B6 71B3
10B6 71B3
13C3 71B3
13B3 71B3
10D6 71C3
10D6 71C3
10C8 71C3
10C8 71C3
10D6 71C3
9B2
10B8 71C3
9B2
10B8 71C3
10B8 71B3
10B2 13C7 71B3
10A2 71B3
10B2 71B3
10B2 71B3
10B8 71B3
9B2
10B2 60C7 71B3
9C4
10C5 40D4 60C8 71B3
10C6 40C4 71B3
10C8 71C3
10C8 71C3
49.9
1/16W
1%
402
MF-LF
R1436
1
2
1/16W
1%
402
MF-LF
49.9
R1431
1
2
49.9
MF-LF
402
1%
1/16W
R1430
1
2
49.9
1/16W
1%
402
MF-LF
R1435
1
2
NO STUFF
1K
402
5% 1/16W MF-LF
R1422
1
2
1K
NO STUFF
402
MF-LF
5%
1/16W
R1421
1
2
1K
5%
402
MF-LF
NO STUFF
1/16W
R1420
1
2
1/16W
402
MF-LF
62
5%
R1415
1
2
1/16W
402
MF-LF
54.9
1%
R1410
1
2
NO STUFF
150
1/16W
402
MF-LF
5%
R1440
1
2
OMIT
MCP79-TOPO-B
(1 OF 11)
BGA
U1400
AK41
AJ40
G41
G42
AL42
AL43
AK42
AL41
AM40
AM39
AF35
AG35
AG39 AE33
AG37 AG38
AG34
AN38 AL39
AG33
AL33
AF41
AJ33
AN36
AJ35 AJ37
AJ36 AJ38
AL37
AL34 AN37
AC34
AJ34
AL38 AL35
AN34
AR39 AN35
AE38
AE34
AC37 AE37
AE35
AB35
AD42
AE36
AK35
AD43
AA41
AE40
AL32
F41
D42
F42
AM42
AM43
Y43
W42
R42 T39
T42 T41
R41
T43 W35
AA37
W33 W34
Y40
AA36
AA34 AA38
AA35 U38
U36
U35 U33
U34
W38
W41
R33
U37
N34 N33
R34 R35
P35
R39 R37
R38
Y39
L37 L39
L38
N36 N38
J39 J38
J37
L42 M42
V42
P41
N41 N40
M40
H40 K42
H41 L41
H43
H42
Y41
K41
J40
H39 M43
Y42 P42
U41
V41
V35
N35
J41
AD39
AA40
AN32
AN33 AM32
AD41
U40
W37
L36
M41
T40
W39
N37
M39
AH40
AB42 AD40
AH39
AH42 AF42
AC43
AG41
E41
AJ41
AH43
AC38
AA33 AC39
AC33
AC35
H38
AC41 AB41
AC42
AM33
AH41
AG42
AG43
AE41
AG27
AH28
AG28
AH27
1/16W
402
MF-LF
62
5%
R1416
1
2
A
SYNC_DATE=04/04/2008
MCP CPU Interface
051-7537
109
14
SYNC_MASTER=T18_MLB
PM_THRMTRIP_L
FSB_D_L<13>
MCP_BCLK_VML_COMP_GND
FSB_DPWR_L
CPU_DPSLP_L
FSB_D_L<38>
FSB_D_L<43>
FSB_D_L<45>
CPU_DPRSTP_L
CPU_STPCLK_L
FSB_CPUSLP_L
FSB_CPURST_L
CPU_PWRGD
CPU_SMI_L
CPU_NMI
CPU_INTR
CPU_INIT_L
CPU_IGNNE_L
CPU_A20M_L
FSB_CLK_MCP_P FSB_CLK_MCP_N
FSB_CLK_ITP_N
FSB_CLK_ITP_P
FSB_CLK_CPU_N
FSB_CLK_CPU_P
FSB_DEFER_L
FSB_BPRI_L
FSB_D_L<63>
FSB_D_L<62>
FSB_D_L<61>
FSB_D_L<60>
FSB_D_L<59>
FSB_D_L<58>
FSB_D_L<57>
FSB_D_L<56>
FSB_D_L<55>
FSB_D_L<54>
FSB_D_L<53>
FSB_D_L<52>
FSB_D_L<51>
FSB_D_L<50>
FSB_D_L<49>
FSB_D_L<48>
FSB_D_L<47>
FSB_D_L<46>
FSB_D_L<44>
FSB_D_L<42>
FSB_D_L<41>
FSB_D_L<40>
FSB_D_L<39>
FSB_D_L<37>
FSB_D_L<36>
FSB_D_L<35>
FSB_D_L<34>
FSB_D_L<33>
FSB_D_L<32>
FSB_D_L<31>
FSB_D_L<30>
FSB_D_L<29>
FSB_D_L<28>
FSB_D_L<27>
FSB_D_L<26>
FSB_D_L<25>
FSB_D_L<24>
FSB_D_L<23>
FSB_D_L<22>
FSB_D_L<21>
FSB_D_L<20>
FSB_D_L<19>
FSB_D_L<18>
FSB_D_L<17>
FSB_D_L<16>
FSB_D_L<15>
FSB_D_L<12>
FSB_D_L<11>
FSB_D_L<10>
FSB_D_L<9>
FSB_D_L<8>
FSB_D_L<6>
FSB_D_L<5>
FSB_D_L<4>
FSB_D_L<3>
FSB_D_L<2>
FSB_D_L<1>
FSB_D_L<0>
MCP_CPU_COMP_GND
MCP_CPU_COMP_VCC
MCP_BCLK_VML_COMP_VDD
FSB_RS_L<2>
FSB_RS_L<1>
CPU_PROCHOT_L
CPU_PECI_MCP
FSB_TRDY_L
FSB_LOCK_L
FSB_HITM_L
FSB_HIT_L
FSB_REQ_L<4>
FSB_REQ_L<3>
FSB_REQ_L<2>
FSB_REQ_L<1>
FSB_REQ_L<0>
FSB_ADSTB_L<1>
FSB_ADSTB_L<0>
FSB_A_L<35>
FSB_A_L<32>
FSB_A_L<31>
FSB_A_L<30>
FSB_A_L<29>
FSB_A_L<28>
FSB_A_L<27>
FSB_A_L<26>
FSB_A_L<24>
FSB_A_L<23>
FSB_A_L<22>
FSB_A_L<21>
FSB_A_L<20>
FSB_A_L<19>
FSB_A_L<18>
FSB_A_L<17>
FSB_A_L<16>
FSB_A_L<15>
FSB_A_L<14>
FSB_A_L<13>
FSB_A_L<12>
FSB_A_L<11>
FSB_A_L<9>
FSB_A_L<8>
FSB_A_L<7>
FSB_A_L<6>
FSB_A_L<5>
FSB_A_L<4>
FSB_A_L<3>
FSB_DINV_L<3>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>
FSB_DINV_L<2>
FSB_DSTB_L_N<2>
FSB_DSTB_L_P<2>
FSB_DINV_L<1>
FSB_DSTB_L_N<1>
FSB_DSTB_L_P<1>
FSB_DINV_L<0>
FSB_DSTB_L_N<0>
FSB_DSTB_L_P<0>
=PP1V05_S0_MCP_FSB
PP1V05_S0_MCP_PLL_FSB
FSB_D_L<14>
FSB_D_L<7>
FSB_A_L<10>
FSB_A_L<25>
FSB_A_L<34>
FSB_A_L<33>
FSB_DBSY_L FSB_DRDY_L
FSB_BNR_L
FSB_RS_L<0>
CPU_FERR_L
FSB_BREQ0_L
FSB_ADS_L
FSB_BREQ1_L
=PP1V05_S0_MCP_FSB
=MCP_BSEL<2>
=MCP_BSEL<0>
=MCP_BSEL<1>
24C8
24C8
22D3
22D3
14B7
14A2
9C2
9C2
71B3
71B3
71B3
71B3
71B3
71B3
8D7
24C2
71C3
8D7
Preliminary
0A
MEMORY
MEMORY PARTITION 0
CONTROL
MCKE0A_1 MCKE0A_0
MODT0A_1 MODT0A_0
MCS0A_0#
MCS0A_1#
MCLK0A_0_N
MCLK0A_0_P
MCLK0A_1_N
MCLK0A_2_N
MCLK0A_1_P
MCLK0A_2_P
MA0_0
MA0_1
MA0_2
MA0_3
MA0_4
MA0_5
MA0_6
MA0_8 MA0_7
MA0_9
MA0_10
MA0_11
MA0_13 MA0_12
MA0_14
MBA0_2
MBA0_0
MBA0_1
MWE0#
MCAS0#
MRAS0#
MDQS0_0_P MDQS0_0_N
MDQS0_1_P
MDQS0_2_N
MDQS0_1_N
MDQS0_2_P
MDQS0_3_N
MDQS0_4_P
MDQS0_3_P
MDQS0_4_N
MDQS0_5_N
MDQS0_5_P
MDQS0_6_N
MDQS0_6_P
MDQS0_7_N
MDQS0_7_P
MDQM0_2 MDQM0_1 MDQM0_0
MDQM0_3
MDQM0_4
MDQ0_0
MDQM0_7
MDQM0_5
MDQM0_6
MDQ0_1
MDQ0_4 MDQ0_3 MDQ0_2
MDQ0_5
MDQ0_6
MDQ0_9 MDQ0_8 MDQ0_7
MDQ0_10
MDQ0_11
MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12
MDQ0_16
MDQ0_21 MDQ0_20
MDQ0_18
MDQ0_19
MDQ0_17
MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22
MDQ0_26
MDQ0_29 MDQ0_28 MDQ0_27
MDQ0_30
MDQ0_31
MDQ0_35 MDQ0_34
MDQ0_32
MDQ0_36
MDQ0_33
MDQ0_41
MDQ0_37
MDQ0_38
MDQ0_40 MDQ0_39
MDQ0_42
MDQ0_47 MDQ0_46
MDQ0_43
MDQ0_45 MDQ0_44
MDQ0_51 MDQ0_50 MDQ0_49
MDQ0_52
MDQ0_48
MDQ0_55 MDQ0_54 MDQ0_53
MDQ0_56
MDQ0_57
MDQ0_61 MDQ0_60
MDQ0_58
MDQ0_59
MDQ0_62
MDQ0_63
OUT
OUT
OUT OUT OUT OUT OUT OUT
BI
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
OUT OUT OUT
OUT OUT OUT
OUT OUT OUT
OUT OUT OUT
OUT OUT OUT
OUT OUT OUT
OUT OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
BI BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI BI BI BI
BI BI
BI
BI
BI BI BI
BI
BI
BI BI BI BI BI BI
BI
BI
OUT OUT OUT
OUT OUT OUT
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
MEMORY
CONTROL
1A
MEMORY PARTITION 1
MDQ1_63
MDQ1_60 MDQ1_59
MDQ1_62
MDQ1_58
MDQ1_61
MDQ1_57
MDQ1_53
MDQ1_56 MDQ1_55 MDQ1_54
MDQ1_52
MDQ1_49
MDQ1_51 MDQ1_50
MDQ1_48 MDQ1_47 MDQ1_46
MDQ1_43
MDQ1_44
MDQ1_45
MDQ1_42 MDQ1_41
MDQ1_37
MDQ1_38
MDQ1_39
MDQ1_36 MDQ1_35
MDQ1_32
MDQ1_33
MDQ1_34
MDQ1_31 MDQ1_30
MDQ1_27
MDQ1_28
MDQ1_29
MDQ1_22
MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23
MDQ1_17
MDQ1_19
MDQ1_20
MDQ1_18
MDQ1_21
MDQ1_16
MDQ1_12
MDQ1_13
MDQ1_14
MDQ1_15
MDQ1_11 MDQ1_10
MDQ1_7
MDQ1_8
MDQ1_9
MDQ1_3
MDQ1_6
MDQ1_2
MDQ1_4
MDQ1_5
MDQ1_1
MDQM1_6 MDQM1_5
MDQ1_0
MDQM1_7
MDQM1_4 MDQM1_3
MDQM1_0
MDQM1_1
MDQM1_2
MDQ1_40
MDQS1_7_P
MDQS1_6_N
MDQS1_6_P
MDQS1_7_N
MDQS1_5_N
MDQS1_5_P
MDQS1_4_P
MDQS1_3_P
MDQS1_4_N
MDQS1_2_P
MDQS1_3_N
MDQS1_1_P
MDQS1_2_N
MDQS1_1_N MDQS1_0_P MDQS1_0_N
MRAS1# MCAS1#
MWE1#
MBA1_2 MBA1_1 MBA1_0
MA1_14 MA1_13 MA1_12 MA1_11 MA1_10
MA1_9 MA1_8 MA1_7 MA1_6 MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0
MCLK1A_2_P
MCLK1A_1_P
MCLK1A_2_N
MCLK1A_0_P
MCLK1A_1_N
MCS1A_1# MCS1A_0#
MCLK1A_0_N
MODT1A_1 MODT1A_0
MCKE1A_0
MCKE1A_1
BI BI BI
BI
BI
BI BI BI
BI
BI
BI BI BI
BI
BI
BI BI BI BI BI BI
BI
BI
BI BI BI
BI
BI
BI BI BI
BI
BI
BI BI BI
BI
BI
BI BI BI BI BI BI
BI
BI
OUT
BI
OUT OUT OUT OUT OUT OUT OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
BGA
MCP79-TOPO-B
OMIT
(2 OF 11)
U1400
AR19
AT19
AN19
AW21
AN23
AU15
AR23
AU19
AV19
AN21
AR21
AP21
AU21
AR22
AV21
AW17
AP19
AP23
AP17
AT23
AU23
BC20
BB20
AY24
BA24
AV33
AW33
AR18
AT15
AP35
AR35
AV31
AT31
AW37
AV37
AR33
AU31
AN31
AV29
AN29
AV27
AW38
AR31
AP31
AR29
AP29
AR27
AP27
AR25
AP25
AU27
AT27
AV38
AU25
AR26
AU13
AR14
AT11
AR11
AW13
AV13
AV11
AU11
AR38
AV9
AU9
AY5
AW6
AP11
AW9
AU8
AU7
AV5
AU6
AR37
AR5
AN10
AW5
AV6
AR7
AR6
AN7
AN6
AL7
AL6
AV39
AN9
AP9
AL9
AL8
AW39
AU37
AT37
AR34
AV35
AW29
AN27
AN13
AR10
AU5
AN5
AT39
AU39
AU35
AT35
AU29
AU30
AW25
AV25
AR13
AP13
AW8
AW7
AR9
AR8
AL11
AL10
AV15
AP15
AV17
AR17
28B5 72C3
28A7 72C3
28B7 72C3
28B5 72C3
28C2 72C3
28B4 72C3
28C2 72C3
28C4 72C3
28D4 72D3
28A5 72D3
28A5 72D3
28A7 72D3
28A7 72D3
28A7 72D3
28A7 72D3
28A5 72D3
28A5 72D3
28B5 72D3
28B7 72D3
28B5 72D3
28B7 72D3
28B7 72D3
28B5 72D3
28B7 72D3
28B5 72D3
28B7 72D3
28B7 72D3
28B7 72D3
28B7 72D3
28B5 72D3
28B5 72D3
28B5 72D3
28B5 72D3
28B5 72D3
28B7 72D3
28B5 72D3
28B5 72D3
28B5 72D3
28B7 72D3
28B7 72D3
28B7 72D3
28C2 72D3
28C4 72D3
28C2 72D3
28C2 72D3
28C2 72D3
28C4 72D3
28C4 72D3
28C4 72D3
28B4 72D3
28B2 72D3
28B4 72D3
28C4 72D3
28B2 72D3
28C2 72D3
28C2 72D3
28B4 72D3
28C4 72D3
28C2 72D3
28C2 72D3
28C4 72D3
28C2 72D3
28C4 72D3
28C2 72D3
28C4 72D3
28C4 72D3
28C4 72D3
28D2 72D3
28D2 72D3
28C2 72D3
28C2 72D3
28C4 72D3
28C5 72D3
28C7 72D3
28C7 72D3
28C7 72D3
28C5 72D3
28C7 72D3
28C5 72D3
28C7 72D3
28C5 72D3
28C7 72D3
28C5 72D3
28C7 72D3
28C7 72D3
28C5 72D3
28C5 72D3
28C5 72D3
28C7 72D3
28C7 72D3
28C5 72D3
28C7 72D3
28C7 72D3
28C5 72D3
28C5 72D3
28C7 72D3
28C7 72D3
28C7 72D3
28C5 72D3
28C5 72D3
28C5 72D3
28D5 72D3
28D7 72D3
28A5 72C3
28A5 72C3
28B7 72C3
28B7 72C3
28B5 72C3
28B5 72C3
28B7 72C3
28B7 72C3
28C4 72C3
28C4 72C3
28B2 72C3
28B2 72C3
28C4 72C3
28C4 72C3
28C2 72C3
28C2 72C3
29A5 72A3
29A5 72A3
29B7 72A3
29B7 72A3
29B5 72A3
29B5 72A3
29B7 72A3
29B2 72A3
29B7 72A3
29B2 72A3
29C4 72A3
29C4 72A3
29C4 72A3
29C4 72A3
29C2 72A3
29C2 72A3
29A5 72B3
29A5 72B3
29A7 72B3
29A7 72B3
29A5 72B3
29A7 72B3
29A5 72B3
29B7 72B3
29A7 72B3
29B7 72B3
29B7 72B3
29B5 72B3
29B5 72B3
29B5 72B3
29B7 72B3
29B7 72B3
29B5 72B3
29C5 72B3
29C7 72B3
29C7 72B3
29C7 72B3
29C5 72B3
29C7 72B3
29C5 72B3
29C7 72B3
29C7 72B3
29C5 72B3
29C7 72B3
29C7 72B3
29C7 72B3
29C5 72B3
29C5 72B3
29C7 72B3
29C5 72B3
29C7 72B3
29C5 72B3
29C7 72B3
29C5 72B3
29C5 72B3
29C5 72B3
29C7 72B3
29C7 72B3
29C7 72B3
29C5 72B3
29C5 72B3
29C5 72B3
29D5 72B3
29D7 72B3
BGA
MCP79-TOPO-B
OMIT
(3 OF 11)
U1400
BA18
BB25
BA17
BC28
AW28
BA14
BA29
BA25
BB26
BA26
BA27
AY27
BA28
AY28
BB28
BB17
BB18
BB29
BA15
BB30
AY31
AY19
BA19
BA22
BB22
BB42
BA42
BB16
BB14
AP42
AR41
BC40
BA40
AV41
AV42
AW40
BB40
AY39
BA38
BB36
BA36
AU41
AY40
BA39
AW36
BC36
AY35
BA34
BB32
BA32
AY36
BA35
AU40
AW32
BC32
BA12
AY12
BB9
BB8
AW12
BB12
BB10
BA9
AN40
AY8
BA7
BC4
BB4
BC8
BA8
BA5
BB5
BB2
BA3
AP41
AW3
AW4
BC3
BB3
AY3
AY4
AU3
AU2
AR3
AR4
AT41
AV3
AV2
AT3
AT4
AT40
AW41
AW42
AR42
AY43
BB38
BB34
BA11
AY7
BA2
AT5
AT43
AT42
AY42
BA43
BA37
BB37
BA33
BB33
AY11
BA10
BA6
BB6
AY1
AY2
AT1
AT2
AY15
BB13
AW16
BA16
29B7 72B3
29B7 72B3
29B5 72B3
29B5 72B3
29B5 72B3
29B7 72B3
29B5 72B3
29B7 72B3
29B7 72B3
29B5 72B3
29B5 72B3
29B7 72B3
29B5 72B3
29B7 72B3
29B5 72B3
29B4 72B3
29B2 72B3
29C2 72B3
29B4 72B3
29B2 72B3
29B4 72B3
29C4 72B3
29C2 72B3
29C2 72B3
29C4 72B3
29C2 72B3
29C4 72B3
29C4 72B3
29C2 72B3
29C4 72B3
29C2 72B3
29C4 72B3
29C4 72B3
29C4 72B3
29C2 72B3
29C2 72B3
29C2 72B3
29C4 72B3
29C2 72B3
29C2 72B3
29C4 72B3
29D2 72B3
29D2 72B3
29C4 72B3
29D4 72B3
29C2 72B3
29A7 72A3
29C4 72B3
29B5 72A3
29B7 72B3
29B5 72B3
29B4 72B3
29C2 72B3
29C2 72B3
29C4 72B3
109
051-7537
A
15
SYNC_MASTER=T18_MLB
SYNC_DATE=04/04/2008
MCP Memory Interface
MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>
MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>
MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>
MEM_B_CKE<0>
MEM_B_CKE<1>
MEM_B_ODT<0>
MEM_B_ODT<1>
MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_CLK_N<0>
MEM_B_CLK_P<0>
MEM_B_CLK_N<1>
MEM_B_CLK_P<1>
TP_MEM_B_CLK2N
TP_MEM_B_CLK2P
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>
MEM_B_WE_L
MEM_B_CAS_L
MEM_B_RAS_L
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
MEM_B_DQS_N<1>
MEM_B_DQS_P<1>
MEM_B_DQS_N<2>
MEM_B_DQS_P<2>
MEM_B_DQS_N<3>
MEM_B_DQS_P<3>
MEM_B_DQS_N<4>
MEM_B_DQS_P<4>
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
MEM_A_CKE<0>
MEM_A_CKE<1>
MEM_A_ODT<0>
MEM_A_ODT<1>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_CLK_N<0>
MEM_A_CLK_P<0>
MEM_A_CLK_N<1>
MEM_A_CLK_P<1>
TP_MEM_A_CLK2N
TP_MEM_A_CLK2P
MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BA<2>
MEM_A_WE_L
MEM_A_CAS_L
MEM_A_RAS_L
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>
MEM_A_DQS_N<3>
MEM_A_DQS_P<3>
MEM_A_DQS_N<4>
MEM_A_DQS_P<4>
MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
Preliminary
MCLK1B_2_P
MCLK1B_1_N
MCLK1B_0_P
MCLK1B_1_P
MCLK1B_2_N
MCS1B_1#
MCS1B_0#
MCLK1B_0_N
MODT1B_0
MCKE1B_1
MCKE1B_0
MODT1B_1
MRESET0#
GND55 GND56 GND57 GND58
GND60
GND59
GND61 GND62 GND63 GND64
GND52 GND53 GND54
GND51
GND49 GND50
GND48
GND47
GND46
GND44 GND45
GND43
GND42
GND41
GND39 GND40
GND38
GND37
GND36
GND35
GND33 GND34
GND32
GND31
GND30
GND28 GND29
GND27
GND26
GND25
GND24
GND18 GND19
GND17
GND16
GND15
GND13 GND14
GND10
GND12
GND11
GND8 GND9
GND7
GND6
GND5
GND2 GND3 GND4
GND1
MEM_COMP_VDD MEM_COMP_GND
MODT0B_0 MODT0B_1
MCKE0B_1
MCKE0B_0
MCLK0B_0_N
MCS0B_0# MCS0B_1#
MCLK0B_2_N
MCLK0B_1_P
MCLK0B_0_P
MCLK0B_1_N
MCLK0B_2_P
+V_PLL_XREF_XS
+V_PLL_CORE +V_VPLL
+VDD_MEM1 +VDD_MEM2 +VDD_MEM3 +VDD_MEM4 +VDD_MEM5 +VDD_MEM6 +VDD_MEM7 +VDD_MEM8
+VDD_MEM9 +VDD_MEM10 +VDD_MEM11
+VDD_MEM14 +VDD_MEM15 +VDD_MEM16 +VDD_MEM17 +VDD_MEM18 +VDD_MEM19 +VDD_MEM20
+VDD_MEM22
+VDD_MEM21
+VDD_MEM23 +VDD_MEM24 +VDD_MEM25 +VDD_MEM26
+VDD_MEM30
+VDD_MEM27
+VDD_MEM29
+VDD_MEM31 +VDD_MEM32 +VDD_MEM33 +VDD_MEM34
+VDD_MEM38 +VDD_MEM39 +VDD_MEM40 +VDD_MEM41
+VDD_MEM43 +VDD_MEM44 +VDD_MEM45
+VDD_MEM42
+V_PLL_DP
+VDD_MEM13
+VDD_MEM12
+VDD_MEM28
+VDD_MEM37
+VDD_MEM36
+VDD_MEM35
GND21
GND20
GND22 GND23
MEMORY CONTROL 0B
MEMORY CONTROL 1B
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
4771 mA (A01, DDR3)
17 mA 12 mA
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
19 mA
TP or NC for DDR2.
39 mA
87 mA (A01)
1%
40.2
1/16W
402
MF-LF
R1610
1
2
MF-LF
402
1%
1/16W
40.2
R1611
1
2
(4 OF 11)
MCP79-TOPO-B
OMIT
BGA
U1400
AA22
AA39
AB22
AB7
AD22
AE20 AF24
AG24 AH35
AK7
AM28
AP12
AT25
AP30
AR36 AU10
F28
BC21
AY9
BC9 D34
F24
G30
G32 H31
K7
M38
M5
M6
M7 M9
N39
N8
P10
P33
P34 P37
P4
P40
P7
R36
R40 R43
R5
T10
T18
T20
AK11
T24
T26
T33
T34
T35 T37
T38
T6
T7
T9
U18 U20
U22
V10
V34
W5
AV23
AN25
BA30
BA31
BB21
BA21
BC24
BB24
AU34
AU33
AY20
BA20
BA23
AY23
BB41
BA41
AU17 AR15
BC16 BA13
AM41
AN41
AN17
AN15
AY16
BC13
AY32
U27
U28
T27
T28
AM17
AN20 AN24
AT17
AP16 AN22
AP20
AP24 AV16
AR16 AR20
AM19
AR24
AW15 AP22
AP18
AU16 AN18
AU24
AT21 AY29
AV24
AM21
AU20
AU22
AW27 BC17
AV20
AY17 AY18
AM15
AU18 AY25
AM23
AY26 AW19
AW24
BC25 AL30
AM31
AM25 AM27
AM29 AN16
BC29
30B6
MCP Memory Misc
16
109
A
051-7537
SYNC_DATE=04/04/2008
SYNC_MASTER=T18_MLB
TP_MEM_B_CKE<3>
TP_MEM_B_CKE<2>
TP_MEM_B_CS_L<2>
MCP_MEM_RESET_L
=PP1V8R1V5_S0_MCP_MEM
MCP_MEM_COMP_GND
TP_MEM_A_CLK4N
TP_MEM_A_CLK3P
TP_MEM_A_ODT<2> TP_MEM_A_ODT<3>
TP_MEM_A_CKE<2> TP_MEM_A_CKE<3>
TP_MEM_A_CLK5P TP_MEM_A_CLK5N
TP_MEM_A_CLK4P
TP_MEM_A_CLK3N
TP_MEM_A_CS_L<2> TP_MEM_A_CS_L<3>
PP1V05_S0_MCP_PLL_CORE
TP_MEM_B_CLK5P TP_MEM_B_CLK5N
TP_MEM_B_CLK4P TP_MEM_B_CLK4N
TP_MEM_B_CLK3P TP_MEM_B_CLK3N
TP_MEM_B_CS_L<3>
TP_MEM_B_ODT<2> TP_MEM_B_ODT<3>
=PP1V8R1V5_S0_MCP_MEM
MCP_MEM_COMP_VDD
24C8
24C8
16C7
16C3
8B7
72A3
24B2
8B7
72A3
Preliminary
PE0_RX0_P
PE0_RX2_N
+AVDD0_PEX11
+AVDD0_PEX7 +AVDD0_PEX8
+AVDD1_PEX3
+AVDD1_PEX2
+AVDD1_PEX1
+AVDD0_PEX13
+AVDD0_PEX12
+AVDD0_PEX10
+AVDD0_PEX9
+AVDD0_PEX6
+AVDD0_PEX5
+AVDD0_PEX4
+AVDD0_PEX3
+AVDD0_PEX2
+AVDD0_PEX1
+V_PLL_PEX
+DVDD1_PEX2
+DVDD1_PEX1
+DVDD0_PEX8
+DVDD0_PEX7
+DVDD0_PEX6
+DVDD0_PEX5
+DVDD0_PEX4
+DVDD0_PEX3
+DVDD0_PEX2
+DVDD0_PEX1
PE0_RX0_N
PE0_RX2_P
PE0_RX4_P
PE0_RX6_P
PEB_PRSNT#
PE1_TX3_N
PE1_TX3_P
PE1_TX2_N
PE1_TX1_N
PE1_TX2_P
PE1_TX0_N
PE1_TX1_P
PE6_REFCLK_N
PEX_RST0#
PE1_TX0_P
PE5_REFCLK_N
PE5_REFCLK_P
PE6_REFCLK_P
PE4_REFCLK_N
PE4_REFCLK_P
PE3_REFCLK_N
PE2_REFCLK_N
PE1_REFCLK_N
PE2_REFCLK_P
PE0_REFCLK_N
PE0_REFCLK_P
PE1_REFCLK_P
PE0_TX15_N
PE0_TX14_N PE0_TX15_P
PE0_TX13_N PE0_TX14_P
PE0_TX12_N
PE0_TX12_P
PE0_TX13_P
PE0_TX11_N
PE0_TX11_P
PE0_TX10_N
PE0_TX9_N PE0_TX10_P
PE0_TX8_N
PE0_TX8_P
PE0_TX9_P
PE0_TX7_N
PE0_TX7_P
PE0_TX6_N
PE0_TX5_N
PE0_TX6_P
PE0_TX4_N
PE0_TX5_P
PE0_TX3_N
PE0_TX3_P
PE0_TX4_P
PE0_TX2_N
PE0_TX2_P
PE0_TX0_N
PE0_TX1_N
PE0_TX1_P
PE0_TX0_P
PEX_CLK_COMP
PE1_RX3_N
PE1_RX3_P
PE1_RX2_N
PE1_RX0_N
PE1_RX1_P
PE1_RX2_P
PE1_RX1_N
PE_WAKE#
PE1_RX0_P
PE0_PRSNT_16#
PE0_RX13_N PE0_RX14_P
PE0_RX15_P
PE0_RX14_N
PE0_RX15_N
PE0_RX12_P
PE0_RX11_P
PE0_RX13_P
PE0_RX11_N
PE0_RX12_N
PE0_RX10_N
PE0_RX8_P
PE0_RX9_P
PE0_RX10_P
PE0_RX8_N
PE0_RX9_N
PE0_RX5_N
PE0_RX7_P
PE0_RX6_N
PE0_RX7_N
PE0_RX3_P
PE0_RX5_P
PE0_RX3_N
PE0_RX4_N
PE0_RX1_P PE0_RX1_N
PEC_PRSNT#
PEC_CLKREQ#/GPIO_50
PE3_REFCLK_P
PED_CLKREQ#/GPIO_51
PED_PRSNT#
PEB_CLKREQ#/GPIO_49
PEE_CLKREQ#/GPIO_16 PEE_PRSNT#/GPIO_46
PEF_CLKREQ#/GPIO_17 PEF_PRSNT#/GPIO_47
PEG_CLKREQ#/GPIO_18 PEG_PRSNT#/GPIO_48
PCI EXPRESS
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
OUT OUT
OUT OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT OUT
OUT
OUT
IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN IN
IN IN
OUT
OUT
OUT OUT
OUT OUT
OUT OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
Int PU
Int PU
Int PU
Int PU
Int PU
Int PU
Int PU
Int PU
Int PU
Int PU
Int PU
Int PU
84 mA (A01)
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
Int PU
206 mA (A01, AVDD0 & 1)
If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX. If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.
57 mA (A01, DVDD0 & 1)
Int PU (S5)
MCP79-TOPO-B
(5 OF 11)
OMIT
BGA
U1400
Y12
AC12 AD12
V12
W12
AA12 AB12
M12 P12
R12
N12 T12
U12
M13 N13
P13
T17
W19 U17
V19 W16
W17
W18 U16
T19 U19
T16
C9
D11
E11
E7
F7
L8
L9
L6
L7
N10
N11
P9
N9
N6
N7
N4
N5
C7
D7
F6
E6
F5
E5
E3
E4
D3
C3
H5
G5
J6
J7
J4
J5
L10
L11
D4
C5
J1
H1
J3
J2
K3
K2
L3
L4
M3
M4
M1
M2
B4
C4
A3
A4
B2
B3
D1
C1
E1
D2
F2
E2
F4
F3
H4
G3
H2
H3
F11
G11
J9
K9
G9
H9
E9
F9
G7
H7
C8
D8
A8
B8
B7
A7
C6
B6
J10
J11
F13
G13
H13
J13
K14
L14
M14
N14
F17
D5 D9
E8
C10
M15 B10
L16 L18
M16
M18
M17
M19
A11
K11
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
7D5
31C7 73D3
7D5
31C7 73D3
9D6
9D6
7D5
23C5 31C7
9D6
9D6
9C6
9C6
31D7
9C6
31D7
9C6
9C6
31C5 73D3
31C5 73D3
9D6
9D6
9C6
9C6
9C6
9C6
31C5 73D3
31C5 73D3
9C6
9C6
9D6
2.37K
402
MF-LF
1% 1/16W
NO STUFF
PLACEMENT_NOTE=Place within 12.7mm of U1400
R1710
1
2
26C4
9C4
9C4
SYNC_MASTER=T18_MLB
MCP PCIe Interfaces
17
109
A
051-7537
SYNC_DATE=04/04/2008
TP_MCP_GPIO_18
PCIE_EXCARD_PRSNT_L
MINI_CLKREQ_L
=PP1V05_S0_MCP_PEX_AVDD1
=PP1V05_S0_MCP_PEX_AVDD0
=PP1V05_S0_MCP_PEX_DVDD1
=PP1V05_S0_MCP_PEX_DVDD0
PCIE_FW_D2R_N
=PEG_D2R_P<0>
=PEG_D2R_N<2>
PP1V05_S0_MCP_PLL_PEX
=PEG_D2R_N<0>
=PEG_D2R_P<2>
=PEG_D2R_P<4>
=PEG_D2R_P<6>
PCIE_MINI_PRSNT_L
TP_PCIE_PE4_R2D_CN
TP_PCIE_PE4_R2D_CP
PCIE_EXCARD_R2D_C_N
PCIE_FW_R2D_C_N
PCIE_EXCARD_R2D_C_P
PCIE_MINI_R2D_C_N
PCIE_FW_R2D_C_P
TP_PCIE_CLK100M_PE6N
PCIE_RESET_L
PCIE_MINI_R2D_C_P
TP_PCIE_CLK100M_PE5N
TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE4P
PCIE_CLK100M_EXCARD_N
PCIE_CLK100M_FW_N
PCIE_CLK100M_MINI_N
PCIE_CLK100M_FW_P
PEG_CLK100M_N
PEG_CLK100M_P
PCIE_CLK100M_MINI_P
=PEG_R2D_C_N<15>
=PEG_R2D_C_N<14> =PEG_R2D_C_P<15>
=PEG_R2D_C_N<13> =PEG_R2D_C_P<14>
=PEG_R2D_C_N<12>
=PEG_R2D_C_P<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_N<11>
=PEG_R2D_C_P<11>
=PEG_R2D_C_N<10>
=PEG_R2D_C_N<9> =PEG_R2D_C_P<10>
=PEG_R2D_C_N<8>
=PEG_R2D_C_P<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_N<7>
=PEG_R2D_C_P<7>
=PEG_R2D_C_N<6>
=PEG_R2D_C_N<5> =PEG_R2D_C_P<6>
=PEG_R2D_C_N<4> =PEG_R2D_C_P<5>
=PEG_R2D_C_N<3>
=PEG_R2D_C_P<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_N<2>
=PEG_R2D_C_P<2>
=PEG_R2D_C_N<0>
=PEG_R2D_C_N<1>
=PEG_R2D_C_P<1>
=PEG_R2D_C_P<0>
MCP_PEX_CLK_COMP
TP_PCIE_PE4_D2RN
TP_PCIE_PE4_D2RP
PCIE_EXCARD_D2R_N
PCIE_MINI_D2R_N
PCIE_FW_D2R_P
PCIE_EXCARD_D2R_P
PCIE_WAKE_L
PCIE_MINI_D2R_P
PEG_PRSNT_L
=PEG_D2R_N<13> =PEG_D2R_P<14>
=PEG_D2R_P<15>
=PEG_D2R_N<14>
=PEG_D2R_N<15>
=PEG_D2R_P<12>
=PEG_D2R_P<11>
=PEG_D2R_P<13>
=PEG_D2R_N<11>
=PEG_D2R_N<12>
=PEG_D2R_N<10>
=PEG_D2R_P<8>
=PEG_D2R_P<9>
=PEG_D2R_P<10>
=PEG_D2R_N<8>
=PEG_D2R_N<9>
=PEG_D2R_N<5>
=PEG_D2R_P<7>
=PEG_D2R_N<6>
=PEG_D2R_N<7>
=PEG_D2R_P<3>
=PEG_D2R_P<5>
=PEG_D2R_N<3>
=PEG_D2R_N<4>
=PEG_D2R_P<1> =PEG_D2R_N<1>
PCIE_FW_PRSNT_L
FW_CLKREQ_L
PCIE_CLK100M_EXCARD_P
EXCARD_CLKREQ_L
TP_PE4_CLKREQ_L
TP_MCP_GPIO_17
TP_PE4_PRSNT_L
GMUX_JTAG_TCK_L
GMUX_JTAG_TDO
8A6
8A6
8A6
8A6
24C2
9B6
9B6
9B6
9B6
73C3
9B6
9B6
9C6
9C6
Preliminary
IN
BI
OUT
IN IN IN IN
IN IN
OUT
OUT OUT
OUT
OUT
OUT
OUT
OUT
OUT OUT OUT OUT OUT OUT
OUT OUT
IN IN
OUT OUT
OUT OUT OUT
OUT OUT
IN
IN OUT
IN IN IN
GPIO_7/NFERR*/IGPU_GPIO_7
+V_DUAL_MACPLL
+VDD_HDMI
+V_PLL_HDMI
+V_PLL_IFPAB
+VDD_IFPB
+VDD_IFPA
+V_TV_DAC
+V_RGB_DAC
+V_DUAL_RMGT2
MII_COMP_GND
MII_COMP_VDD
LCD_PANEL_PWR/GPIO_58
LCD_BKL_ON/GPIO_59
LCD_BKL_CTL/GPIO_57
XTALOUT_TV
GPIO_6/FERR*/IGPU_GPIO_6
HDMI_TXC_P/ML0_LANE3_P HDMI_TXC_N/ML0_LANE3_N
HDMI_TXD0_P/ML0_LANE2_P HDMI_TXD0_N/ML0_LANE2_N HDMI_TXD1_P/ML0_LANE1_P HDMI_TXD1_N/ML0_LANE1_N HDMI_TXD2_P/ML0_LANE0_P HDMI_TXD2_N/ML0_LANE0_N
HPLUG_DET2/GPIO_22
IFPA_TXC_N
XTALIN_TV
DDC_DATA2/GPIO_24
DDC_CLK2/GPIO_23
RGB_DAC_RSET RGB_DAC_VREF
TV_DAC_VREF
DP_AUX_CH0_P DP_AUX_CH0_N
HPLUG_DET3
HDMI_RSET HDMI_VPROBE
RGMII_MDIO
BUF_25MHZ
DDC_DATA0
DDC_CLK0
RGB_DAC_RED
RGB_DAC_GREEN
RGB_DAC_BLUE
RGB_DAC_HSYNC RGB_DAC_VSYNC
TV_DAC_RED
TV_DAC_GREEN
IFPA_TXC_P
IFPA_TXD0_P IFPA_TXD0_N
IFPA_TXD2_P
IFPA_TXD1_P IFPA_TXD1_N
IFPA_TXD3_P
IFPA_TXD2_N
IFPB_TXC_P IFPB_TXC_N
IFPB_TXD5_P
IFPB_TXD4_P IFPB_TXD4_N
IFPB_TXD6_P
IFPB_TXD5_N
IFPB_TXD6_N IFPB_TXD7_P IFPB_TXD7_N
DDC_DATA3
DDC_CLK3
IFPAB_RSET
IFPAB_VPROBE
TV_DAC_RSET
RGMII_RXD0
RGMII_INTR/GPIO_35
RGMII_RXD3
RGMII_RXCTL/MII_RXDV
RGMII_RXC/MII_RXCLK
RGMII_RXD2
RGMII_RXD1
MII_RESET#
RGMII_MDC
RGMII_PWRDWN/GPIO_37
MII_RXER/GPIO_36 MII_COL/GPIO_20/MSMB_DATA MII_CRS/GPIO_21/MSMB_CLK
TV_DAC_BLUE
TV_DAC_HSYNC/GPIO_44 TV_DAC_VSYNC/GPIO_45
+V_DUAL_RMGT1
MII_VREF
RGMII_TXCTL/MII_TXEN
RGMII_TXC/MII_TXCLK
RGMII_TXD3
RGMII_TXD2
RGMII_TXD1
RGMII_TXD0
+3.3V_DUAL_RMGT1 +3.3V_DUAL_RMGT2
IFPA_TXD3_N
LAN
DACS
FLAT PANEL
BI
OUT
OUT OUT
OUT OUT OUT
OUT
OUT OUT OUT OUT OUT
OUT OUT
OUT OUT OUT
OUT
OUT OUT OUT OUT OUT
OUT
BI
OUT
BI
OUT
OUT
OUT
OUT OUT
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
In MCP79 these pins have undocumented internal
GPIOs 57-59 (if LCD panel is used):
by default, pull-downs (1K or stronger) must be used.
pull-ups (~10K to 3.3V S0). To ensure pins are low
Alias to GMUX_INT for systems with GMUX. Alias to HPLUG_DET2 for other systems. Pull-down (20k) required in all cases.
=DVI_HPD_GMUX_INT:
Alias to DVI_HPD for systems using IFP for DVI.
(See below)
(See below)
NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.
NOTE: 20K pull-down required on DP_HPD_DET.
level-shifters.
NOTE: HDMI port requires level-shifting. IFP interface can be used to provide HDMI or dual-channel TMDS without
Interface Mode
DP_IG_ML_P/N<0>
DP_IG_DDC_DATA DP_IG_HPD DP_IG_AUX_CH_P/N
NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.
Dual-channel TMDS: Power +VDD_IFPx at 3.3V
131 mA (A01)
83 mA (A01)
MII, RGMII products will enable
WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases
RGB DAC Disable:
TV / Component
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
LVDS: Power +VDD_IFPx at 1.8V
95 mA (A01)
16 mA (A01)
8 mA
8 mA
DP_IG_AUX_CH_P/N
=MCP_HDMI_HPD
TMDS_IG_HPD
=MCP_HDMI_DDC_DATA
=MCP_HDMI_TXD_P/N<2>
=MCP_HDMI_TXD_P/N<1>
=MCP_HDMI_DDC_CLK
MCP Signal
=MCP_HDMI_TXD_P/N<0>
=MCP_HDMI_TXC_P/N
TMDS/HDMI
TMDS_IG_TXC_P/N TMDS_IG_TXD_P/N<0>
TMDS_IG_DDC_CLK
TMDS_IG_TXD_P/N<1> TMDS_IG_TXD_P/N<2>
TMDS_IG_DDC_DATA
TP_DP_IG_AUX_CHP/N
DP_IG_DDC_CLK
DP_IG_ML_P/N<2> DP_IG_ML_P/N<1>
DP_IG_ML_P/N<3>
DisplayPort
5 mA (A01)
RGB ONLY
avoids a leakage issue since
feature via software. This
NOTE: All Apple products set strap to
Network Interface Select
Interface
RGMII
MII 0
1
ENET_TXD<0>
DDC_CLK0/DDC_DATA0 pull-ups still required.
Okay to float all TV_DAC signals.
TV DAC Disable:
Y / Y
DDC_CLK0/DDC_DATA0 pull-ups still required.
Okay to float all RGB_DAC signals.
Okay to float XTALIN_TV and XTALOUT_TV.
103 mA 103 mA
206 mA (A01)
Comp / Pb
MCP79 requires a S5 pull-up.
C / Pr
190 mA (A01, 1.8V)
24A4
33B6 75D3
34A5 75D3
33C1 75D3
33C1 75D3
33C1 75D3
33B1 75D3
33C1 75D3
33B1 75D3
33B7 75C3
9D4
9D4
69A8 70A7
66B8
70B7 70C8
67D3
67D3
67D3
67D3
67D3
67D3
67D3
67D3
67C7 73B3
67B7 73B3
9B4
67D3
25C7 73B3
25C7 73B3
9D4
9D4
9D4
9D4
9D4
1% 1/16W MF-LF
402
49.9
R1810
1
2
1/16W MF-LF
49.9
402
1%
R1811
1
2
67A5
9D4
9D4
9C4
9C4
9C4
(6 OF 11)
BGA
MCP79-TOPO-B
OMIT
U1400
E23
B31
C30
D31
A31
B30
E31
C43
D43
E16
B15
J31
E35
D35
F35
G35
G33
F33
H33
J33
J30
C31 F31
C35
B35
A32
B32
C32
D32
C33
D33
C34
B34
E32
G31
K31
L31
H29
J29
K29
L29
K30
L30
M30
N30
G39
E37 F40
B26
B27
C27
B22
J23
F23
E28
J24
K24
T23
U23
V23
M29
M28
J32
K32
T25
M27 M26
B40
A39
A40
B39
C39
B38
A41
J22
D21
C21
G23
A23
C22
C23
B23
E24 A24
D24 C26
B24
C24 C25
D25
C36
B36
D36
A36
E36 A35
C37
C38
D38
10K
402
1/16W
5%
MF-LF
R1850
1
2
402
5%
100K
1/16W MF-LF
R1861
1
2
402
MF-LF
5%
1/16W
100K
R1860
1
2
41C3
5%
47K
402
MF-LF
1/16W
R1820
1
2
33C6 75C3
66B3 73B3
66B3 73B3
7C7
66C2 73B3
7C7
66C2 73B3
7C7
66C2 73B3
33C6 75C3
7C7
66C2 73B3
7C7
66C2 73B3
7C7
66C2 73B3
9D4
9D4
9C4
9C4
9C4
9C4
9C4
33C6 75C3
9C4
9C4
9C4
9C4
9C4
7C7
66C5
7C7
66B5
67D3
67D3
25C6 73A3
33B6 75C3
25C6 73A3
33C8 75D3
33B6 75C3
33B6 75D3
18
109
A
051-7537
SYNC_DATE=04/04/2008
SYNC_MASTER=T18_MLB
MCP Ethernet & Graphics
=DVI_HPD_GMUX_INT
LVDS_IG_BKL_PWM
MCP_CLK27M_XTALOUT
TP_MCP_RGB_DAC_RSET TP_MCP_RGB_DAC_VREF
LPCPLUS_GPIO
=PP1V05_ENET_MCP_RMGT
=PP3V3_S5_MCP_GPIO
=PP3V3_ENET_MCP_RMGT
=PP3V3_S0_MCP_GPIO
=PP3V3_ENET_MCP_RMGT
ENET_TXD<0> ENET_TXD<1> ENET_TXD<2> ENET_TXD<3>
ENET_CLK125M_TXCLK ENET_TX_CTRL
MCP_MII_VREF
CRT_IG_VSYNC
CRT_IG_HSYNC
CRT_IG_B_COMP_PB
=MCP_MII_CRS
=MCP_MII_COL
=MCP_MII_RXER
TP_ENET_PWRDWN_L
ENET_MDC
ENET_RESET_L
ENET_RXD<1> ENET_RXD<2>
ENET_CLK125M_RXCLK ENET_RX_CTRL
ENET_RXD<3>
TP_ENET_INTR_L
ENET_RXD<0>
MCP_TV_DAC_RSET
MCP_IFPAB_VPROBE
MCP_IFPAB_RSET
=MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA
LVDS_IG_B_DATA_N<3>
LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<2>
LVDS_IG_B_DATA_N<1> LVDS_IG_B_DATA_P<2>
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_CLK_N
LVDS_IG_B_CLK_P
LVDS_IG_A_DATA_N<2> LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_CLK_P
CRT_IG_G_Y_Y
CRT_IG_R_C_PR
TP_MCP_RGB_VSYNC
TP_MCP_RGB_HSYNC
TP_MCP_RGB_BLUE
TP_MCP_RGB_GREEN
TP_MCP_RGB_RED
MCP_DDC_CLK0 MCP_DDC_DATA0
MCP_CLK25M_BUF0_R
ENET_MDIO
=MCP_HDMI_HPD
DP_IG_AUX_CH_N
DP_IG_AUX_CH_P
MCP_TV_DAC_VREF
LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA
MCP_CLK27M_XTALIN
=MCP_HDMI_TXD_N<2>
=MCP_HDMI_TXC_P
LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR
MCP_MII_COMP_VDD MCP_MII_COMP_GND
PP3V3_S0_MCP_DAC
=PP3V3R1V8_S0_MCP_IFP_VDD
PP3V3_S0_MCP_VPLL
=PP1V05_S0_MCP_HDMI_VDD
PP1V05_ENET_MCP_PLL_MAC
DP_IG_CA_DET
MCP_HDMI_VPROBE
MCP_HDMI_RSET
LVDS_IG_A_DATA_N<3>
LVDS_IG_A_CLK_N
=MCP_HDMI_TXD_P<2>
=MCP_HDMI_TXD_N<1>
=MCP_HDMI_TXD_P<1>
=MCP_HDMI_TXD_P<0>
=MCP_HDMI_TXC_N
=MCP_HDMI_TXD_N<0>
24B6
24B6
24A6
21A4
24A6
24C6
20C1
18D3
19D1
18C7
25D7
25D7
8B1
8A3
8B1
8C5
8B1
75D3
75D3
25D2
8A7
25B5
8B7
24A6
Preliminary
OUT
OUT
BI BI BI BI
LPC PCIGND
PCI_INTW# PCI_INTX# PCI_INTY# PCI_INTZ#
GND65
LPC_DRQ1#/GPIO_19
LPC_PWRDWN#/GPIO_54/EXT_NMI#
PCI_TRDY#
LPC_DRQ0# LPC_SERIRQ
PCI_AD4
PCI_AD0
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD5 PCI_AD6
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD10 PCI_AD11
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD15 PCI_AD16 PCI_AD17
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD21 PCI_AD22
PCI_AD25
PCI_AD23
PCI_AD26
PCI_AD29
PCI_AD31
GND66 GND67
GND69
GND68
GND70 GND71 GND72
GND74
GND73
GND75 GND76 GND77
GND79
GND78
GND80 GND81
GND84
GND83
GND82
GND85 GND86 GND87
GND89
GND88
GND90 GND91 GND92
GND94
GND93
GND95 GND96 GND97
PCI_GNT0#
PCI_CBE2#
PCI_CBE0#
PCI_CBE3#
PCI_IRDY#
PCI_FRAME#
PCI_DEVSEL#
PCI_PAR
PCI_SERR# PCI_STOP#
PCI_RESET0# PCI_RESET1#
PCI_CLK2
PCI_CLK1
PCI_CLK0
PCI_CLKIN
LPC_FRAME#
LPC_AD1
LPC_AD0
LPC_RESET0#
LPC_CLK0
LPC_AD3
LPC_AD2
GND99
GND98
GND100
GND102
GND101
GND104
GND103
GND105 GND106 GND107
GND109
GND108
GND110 GND111 GND112
GND115
GND114
GND113
GND116 GND117
GND120
GND119
GND118
GND121 GND122 GND123
GND125
GND124
GND126 GND127 GND128
GND130
GND129
PCI_AD30
PCI_AD27
PCI_AD24
PCI_CLKRUN#/GPIO_42
PCI_AD28
PCI_GNT2#/GPIO_41/RS232_DTR# PCI_GNT3#/GPIO_39/RS232_RTS#
PCI_GNT4#/GPIO_53/RS232_SOUT#
PCI_GNT1#/FANCTL2
PCI_CBE1#
PCI_PERR#/GPIO_43/RS232_DCD#
PCI_REQ3#/GPIO_38/RS232_CTS# PCI_REQ4#/GPIO_52/RS232_SIN#
PCI_PME#/GPIO_30
PCI_REQ2#/GPIO_40/RS232_DSR#
PCI_REQ0# PCI_REQ1#/FANRPM2
IN
BI
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
BI BI BI BI BI BI BI BI
OUT
OUT OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
Int PU (S5)
Int PU
Int PU
Int PU
Strap for Boot ROM Selection (See HDA_SDOUT)
39C8 41D5 74C3
26D4 74C3
39C8 41D5 74C3
39C8 41D5 74C3
39C8 41D3 74C3
39C8 41D3 74C3
BGA
(7 OF 11)
MCP79-TOPO-B
OMIT
U1400
AB18 H34
AB20 AB21
AB23
AB24 AB25
AB26
AB27 AB28
AB34
AB37 AB4
AB40 AC22
AC36
AC40 AB33
AC5
AD16 AD17
AD18
AD19 AD20
AD24 AD25
AD26
AD27 AD28
AD33
AD34
U24
U26
U39
U4
U8 V16
V17
V18 V20
V22
V24 V26
V27
V28 V33
V37
V4
V40
V7 W20
W22
W24 W36
W40
W43 Y16
Y17 Y18
Y19
Y20 Y22
Y24
Y25
Y26
Y27
AD3 AD2
AD1 AD5
AE9
AE1
AE2
AD4 AE12
AE5
AE6
AC3
AE10
AC9
AC10 AC11
AA1
AA5
Y5
W3
W6
W4
W7
AC4
V3
W8
V2
W9
U3
W11
U2
U5
U1
U6
AE11
T5
U7
AB3
AC6
AB2 AC7
AC8 AA2
AA3 AA6
AA11
W10
R6 R7
R8
R9
AD11
AA9
Y4
R3
U10 R4
U11 P3
P2
N3
N2
N1
AA10
Y1 AB9
T1
T2
V9
T3
U9
T4
R10
R11
AA7
Y2
Y3
39C5 41D5
39C8 41D3 26C4 74C3
39C5 41D3
PLACEMENT_NOTE=Place close to pin R8
MF-LF 402
1/16W
5%
22
R1910
1
2
402
MF-LF1/16W
5%
8.2K
R1989
1 2
402
MF-LF1/16W
5%
8.2K
R1991
1 2
402
MF-LF1/16W
5%
8.2K
R1990
1 2
402
MF-LF1/16W
5%
8.2K
R1994
1 2
8.2K
5%
1/16W MF-LF
402
R1992
1 2
19D2
MF-LF 402
1/16W
5%
10K
R1961
1
2
1/16W MF-LF
402
22
5%
R1960
1 2
5%
1/16W MF-LF22402
R1950
1 2
5%
1/16W MF-LF22402
R1951
1 2
22
5%
1/16W MF-LF
402
R1952
1 2
402
MF-LF1/16W
5%
22
R1953
1 2
26C4
9C4
19D2
19D2
13B6 23C5
13C3 74D3
13C3 74D3
13C3 74D3
13C3 74D3
13C3 74D3
13C3 74D3
13C3 74D3
13C3 74D3
52C7
9C4
9C4
051-7537
A
109
19
MCP PCI & LPC
SYNC_DATE=04/04/2008
SYNC_MASTER=T18_MLB
GMUX_JTAG_TDI
GMUX_JTAG_TMS
TP_PCI_INTX_L
TP_PCI_INTZ_L
FW_PME_L TP_LPC_DRQ0_L LPC_SERIRQ
PM_CLKRUN_L
=PP3V3_S0_MCP_GPIO
MCP_RS232_SIN_L
MCP_DEBUG<7>
MCP_DEBUG<6>
MCP_DEBUG<5>
MCP_DEBUG<4>
MCP_DEBUG<3>
MCP_DEBUG<2>
MCP_DEBUG<1>
MCP_DEBUG<0>
MCP_RS232_SIN_L
AUD_IPHS_SWITCH_EN
CRTMUX_SEL_TV_L
TP_PCI_AD<12> TP_PCI_AD<13> TP_PCI_AD<14>
TP_PCI_AD<16> TP_PCI_AD<17> TP_PCI_AD<18> TP_PCI_AD<19> TP_PCI_AD<20> TP_PCI_AD<21> TP_PCI_AD<22> TP_PCI_AD<23> TP_PCI_AD<24> TP_PCI_AD<25> TP_PCI_AD<26> TP_PCI_AD<27> TP_PCI_AD<28> TP_PCI_AD<29> TP_PCI_AD<30> TP_PCI_AD<31>
TP_PCI_INTW_L
TP_PCI_TRDY_L
TP_PCI_INTY_L
TP_PCI_AD<15>
PCI_REQ0_L PCI_REQ1_L
TP_PCI_AD<8>
TP_PCI_AD<10> TP_PCI_AD<11>
TP_PCI_AD<9>
TP_PCI_PERR_L
MEM_VTT_EN_R
PCI_CLK33M_MCP
TP_PCI_CLK1 PCI_CLK33M_MCP_R
LPC_PWRDWN_L
LPC_RESET_L
LPC_FRAME_R_L
LPC_CLK33M_SMC_R
LPC_AD_R<3>
LPC_AD_R<2>
LPC_AD_R<1>
LPC_AD_R<0>
TP_PCI_CLK0
TP_PCI_RESET1_L
PM_LATRIGGER_L
TP_PCI_STOP_L
TP_PCI_SERR_L
TP_PCI_PAR
TP_PCI_IRDY_L
TP_PCI_FRAME_L
TP_PCI_DEVSEL_L
TP_PCI_C_BE_L<3>
TP_PCI_C_BE_L<2>
TP_PCI_C_BE_L<1>
TP_PCI_C_BE_L<0>
MCP_RS232_SOUT_L
TP_PCI_GNT1_L
TP_PCI_GNT0_L
LPC_AD<0>
LPC_FRAME_L
LPC_AD<2> LPC_AD<3>
LPC_AD<1>
MCP_RS232_SOUT_L
PCI_REQ0_L PCI_REQ1_L CRTMUX_SEL_TV_L
21A4 18C1
74D3
74D3
74D3
74D3
8C5
19D7
19D2
19D2
74C3
74C3
41C1
19D4
19D7
19D7
19D7
Preliminary
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
IN IN IN IN
SATA_B0_RX_N
SATA_A0_RX_P
SATA_A1_TX_P
GND160
GND158 GND159
GND157
GND156
GND155
GND153 GND154
GND152
GND151
GND150
GND148 GND149
GND147
GND146
GND145
GND143 GND144
GND142
GND141
GND140
GND139
GND136
GND133 GND134
GND132
GND131
USB_RBIAS_GND
USB11_N
USB11_P
USB10_N
USB10_P
USB9_N
USB9_P
USB7_N
USB8_N
USB8_P
USB7_P
USB6_N
USB6_P
USB5_N
USB4_N
USB4_P
USB5_P
USB2_N
USB2_P
USB0_N
USB1_N
USB1_P
USB0_P
SATA_TERMP
SATA_LED#
SATA_C1_RX_N SATA_C1_RX_P
SATA_C0_TX_P
SATA_B1_RX_N SATA_B1_RX_P
SATA_B1_TX_N
SATA_B1_TX_P
SATA_B0_TX_N
SATA_B0_RX_P
SATA_B0_TX_P
SATA_A1_RX_N SATA_A1_RX_P
SATA_A1_TX_N
SATA_A0_TX_P
GND138
GND137
GND135
USB3_P USB3_N
USB_OC0#/GPIO_25
USB_OC1#/GPIO_26 USB_OC2#/GPIO_27/MGPIO USB_OC3#/GPIO_28/MGPIO
SATA_A0_RX_N
SATA_A0_TX_N
SATA_C1_TX_N
SATA_C1_TX_P
SATA_C0_RX_P
SATA_C0_RX_N
SATA_C0_TX_N
+V_PLL_USB
+V_PLL_SATA
+DVDD0_SATA1 +DVDD0_SATA2 +DVDD0_SATA3 +DVDD0_SATA4
+DVDD1_SATA2
+AVDD0_SATA1 +AVDD0_SATA2 +AVDD0_SATA3 +AVDD0_SATA4 +AVDD0_SATA5 +AVDD0_SATA6 +AVDD0_SATA7 +AVDD0_SATA8 +AVDD0_SATA9
+AVDD1_SATA1 +AVDD1_SATA2 +AVDD1_SATA3 +AVDD1_SATA4
+DVDD1_SATA1
SATA
USB
OUT OUT
IN
IN
OUT OUT
IN IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
19 mA (A01)
84 mA (A01)
External C
ExpressCard
External B
IR
Bluetooth
Camera
External A
External D
AirPort (PCIe Mini-Card)
Geyser Trackpad/Keyboard
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
43 mA (A01, DVDD0 & 1)
127 mA (A01, AVDD0 & 1)
If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA. If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.
37A8 74C3
37A8 74C3
9B6
9B6
9B6
9B6
31B5 74C3
31B5 74C3
38C7 74B3
38C7 74B3
47B8 74B3
47B8 74B3
31B5 74B3
31B5 74B3
37A4 74B3
37A4 74B3
9B6
9B6
9B6
9B6
37C7
37C7
40B4
MF-LF
1% 1/16W
402
2.49K
R2010
1
2
806
MF-LF
1%
1/16W
402
R2060
1
2
5%
8.2K
MF-LF
1/16W
402
R2053
1
2
402
1/16W MF-LF
5%
8.2K
R2052
1
2
5%
8.2K
1/16W
402
MF-LF
R2051
1
2
402
1/16W MF-LF
5%
8.2K
R2050
1
2
(8 OF 11)
MCP79-TOPO-B
OMIT
BGA
U1400
AD35
AD37 AD38
AE22
AE24 AE39
AE4
AD6 AF16
AF17 AF18
AF20
AF22 AF26
AF27
AF28 AF33
AF34
AF37 AF40
AG18 AG20
AG22
AG26 AG36
AG40
AH18 AH20
AH22
AH24
AJ12
AN11 AK12
AK13
AL12 AM11
AM12 AN12
AL13
AN14
AL14
AM13 AM14
AF19 AG16
AG17
AG19
AH17 AH19
AE16
L28
AJ5
AJ4
AJ6
AJ7
AJ9 AK9
AJ10
AJ11
AJ2 AJ1
AJ3
AK2
AL4 AK3
AL3
AM4
AM2 AM3
AM1
AN1
AN3
AN2
AP2
AP3
E12
AE3
D29
C29
G25
F25
L23
K23
D28
C28
B28
A28
G29
F29
L27
K27
J27
J26
G27
F27
E27
D27
L25
K25
J25
H25
L21
K21 J21
H21
A27
36A3 73A3
36A3 73A3
36A3 73A3
36A3 73A3
36C2 73A3
36C2 73A3
36B2 73A3
36B2 73A3
SYNC_MASTER=T18_MLB
MCP SATA & USB
051-7537
A
109
20
SYNC_DATE=04/04/2008
=PP1V05_S0_MCP_SATA_AVDD1
=PP1V05_S0_MCP_SATA_AVDD0
=PP1V05_S0_MCP_SATA_DVDD1
=PP1V05_S0_MCP_SATA_DVDD0
SATA_ODD_D2R_P
SATA_ODD_D2R_N
SATA_ODD_R2D_C_N
SATA_ODD_R2D_C_P
SATA_HDD_D2R_N SATA_HDD_D2R_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_C_P
TP_SATA_C_D2RP
TP_SATA_C_D2RN
PP1V05_S0_MCP_PLL_SATA
=PP3V3_S5_MCP_GPIO
USB_EXTC_OC_L
USB_EXTB_OC_L
USB_EXTA_OC_L
TP_USB_11N
TP_USB_11P
TP_USB_10P
USB_EXTC_N
USB_EXCARD_N
USB_EXCARD_P
USB_EXTB_N
USB_EXTB_P
USB_BT_N
USB_BT_P
USB_TPAD_N
USB_TPAD_P
USB_IR_N
USB_IR_P
USB_CAMERA_N
USB_CAMERA_P
USB_EXTD_N
USB_EXTD_P
USB_MINI_N
USB_MINI_P
USB_EXTA_N
USB_EXTA_P
MCP_SATA_TERMP
TP_SATA_F_D2RP
TP_SATA_F_D2RN
TP_SATA_F_R2D_CN
TP_SATA_F_R2D_CP
TP_SATA_E_D2RN
TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP
TP_SATA_D_D2RP
TP_SATA_D_D2RN
TP_SATA_D_R2D_CN
TP_SATA_D_R2D_CP
TP_SATA_C_R2D_CN
TP_SATA_C_R2D_CP
TP_SATA_E_D2RP
TP_MCP_SATALED_L
TP_USB_10N
USB_EXTC_P
EXCARD_OC_L
MCP_USB_RBIAS_GND
PP3V3_S0_MCP_PLL_USB
18C7
8A6
8A6
8A6
8A6
24B2
8A3
73A3
74B3
24B4
Preliminary
OUT
OUT
OUT
BI
BI
OUT
OUT
OUT
OUT
OUT OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
IN IN
OUT
IN
IN IN IN
OUT
HDA_SDATA_IN1/GPIO_2/PS2_KB_CLK
HDA_SDATA_IN2/GPIO_3/PS2_KB_DATA
MCP_VID2/GPIO_15
MCP_VID1/GPIO_14
MCP_VID0/GPIO_13
THERM_DIODE_N
EXT_SMI/GPIO_32#
FANCTL1/GPIO_62
FANRPM1/GPIO_63
FANCTL0/GPIO_61
FANRPM0/GPIO_60
SIO_PME#
KBRDRSTIN#
PKG_TEST
TEST_MODE_EN
BUF_SIO_CLK
CPUVDD_EN
SMB_DATA0
SMB_CLK0
SPKR
HDA_RESET#
HDA_SYNC
HDA_BITCLK
HDA_SDATA_OUT
XTALIN_RTC
XTALOUT
XTALOUT_RTC
JTAG_TRST#
XTALIN
JTAG_TCK
JTAG_TMS
CPU_VLD
JTAG_TDI JTAG_TDO
RTC_RST#
PS_PWRGD
PWRGD_SB
INTRUDER#
LID# LLB#
PWRBTN# RSTBTN#
CPU_DPRSLPVR
SLP_S5#
SLP_S3#
HDA_DOCK_RST#/GPIO_5/PS2_MS_DATA
HDA_DOCK_EN#/GPIO_4/PS2_MS_CLK
A20GATE
GPIO_12/SUS_STAT#/ACCLMTR
HDA_SDATA_IN0
GPIO_1/PWRDN_OK/SPI_CS1
HDA_PULLDN_COMP
THERM_DIODE_P
SLP_RMGT#
SMB_CLK1/MSMB_CLK
SMB_DATA1/MSMB_DATA
SMB_ALERT#/GPIO_64
SPI_CS0/GPIO_10 SPI_CLK/GPIO_11
SPI_DI/GPIO_8 SPI_DO/GPIO_9
SUS_CLK/GPIO_34
+V_DUAL_HDA1 +V_DUAL_HDA2
+V_PLL_NV_H +V_PLL_SP_SPREF
HDA
MISC
OUT
IN
IN
OUT
IN
IN
OUT
IN
OUT
OUT
IN
IN
IN
IN
IN IN
IN
OUT
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
(MGPIO2)
(MGPIO3)
Int PU (S5)
Int PU (S5)
17 mA
20 mA
37 mA (A01)
7 mA (A01)
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
HDA Output Caps
For EMI Reduction on HDA interface
PCI
not use LPC for BootROM override.
LPC_FRAME# high for SPI1 ROM override.
SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L
Int PU
Int PU (S5)
Int PU
Int PU
25 MHz
42 MHz 0
LPC ROMs. So Apple designs will
0
1
HDA_SYNC
24 MHz
0
1
1
0
SPI_CLKSPI_DO
0
1
1
14.31818 MHz
BUF_SIO_CLK Frequency
Frequency
31 MHz
NOTE: Straps not provided on this page.
1 MHz
SPI Frequency Select
Frequency
NOTE: MCP79 does not support FWH, only
LPC
SPI0
SPI1
I/F
HDA_SDOUT
BIOS Boot Select
R1961 and R2160 selects SPI0 ROM by default, LPC+ debug card pulls
1
1
0
0
LPC_FRAME#
0
1
0
1
Int PU
Int PD
Int PD
Int PD
Int PU (S5)
NOTE: MCP79 rev A01 does not support SPI1 option. Rev B01 will.
Int PU
Int PU (S5)
(MXM_OK for MXM systems)
SAFE mode: For ROMSIP recovery
USER mode: Normal
Connects to SMC for automatic recovery.
41A5 41C8 74A3
7C3
34B7 39C5 41A5 64D5 68D8
7C3
39C5 40A2 64C8
13B6 42D8 74B3
42C8 74B3
13B6 42D8 74B3
42C8 74B3
21A3 61A8
45C5 77D3
21A3 61A8
21A3 61A8
21A3 31D5 34C7
45B5 77D3
9D1
60D8 71B3
23B5 39B8
51C7 74A3
51C7 74B3
51B7 74A3
51C7 74A3
51C7 74A3
49.9K
402
1% 1/16W MF-LF
R2121
1
2
1/16W
402
MF-LF
49.9K
1%
R2120
1
2
402
1/16W
1%
MF-LF
1K
R2190
1
2
26B4 74A3
23C5 39C5
23C5 39B8
1/16W
22
5%
402
MF-LF
R2170
1 2
22
402
1/16W
5%
MF-LF
R2171
1 2
402
1/16W MF-LF
22
5%
R2173
1 2
1/16W MF-LF
10K
5%
402
R2163
1
2
402
1/16W
5%
8.2K
MF-LF
R2160
1
2
1/16W
402
BOOT_MODE_SAFE
MF-LF
10K
5%
R2180
1
2
1/16W
BOOT_MODE_USER
MF-LF 402
10K
5%
R2181
1
2
MF-LF
1/16W
22
5%
402
R2172
1 2
41B1
402
1% 1/16W MF-LF
49.9
R2110
1
2
10K
5%
MF-LF
1/16W
402
R2150
1
2
6C5
13C3 23C5
6C5
13C3 23C5
6C5
13C3
6C5
13B6
6C4
CERM 402
5% 50V
10PF
C2171
1
2
CERM 402
5%
10PF
50V
C2173
1
2
CERM
402
5%
10PF
50V
C2170
1
2
CERM
402
5%
10PF
50V
C2172
1
2
OMIT
MCP79-TOPO-B
(9 OF 11)
BGA
U1400
K13
AE7
M22
C17 D17
C18
A12
C12
B12
D12
L26
L24
E15
K17
L17
A15
K15
G15
J14
J15
F15
L15
B20
G19
E19 F19
J19
J18
L13
M25
M24
L20
M20
M21
J16
K16
AE18
AE17
L22
E20
C16
D20
D16
C20
C19
J17
G17
H17
M23
L19
G21
K19
F21
D13
C14
C15
B14
C13
B18
K22
C11
B11
A16
A19
B16
B19
36C6
21A4 52C7
26A5 26A8
34B7 39D5 40B2
21A4 28A5 29A5 39B8
100K
5%
MF-LF
1/16W
402
R2147
1
2
MF-LF 402
1/16W
5%
10K
R2142
1
2
10K
5%
MF-LF
1/16W
402
R2141
1
2
402
1/16W MF-LF
5%
22K
R2157
1
2
402
1/16W MF-LF
5%
22K
R2156
1
2
MF-LF
5%
22K
1/16W
402
R2155
1
2
100K
1/16W
5%
MF-LF 402
R2151
1
2
402
100K
5%
MF-LF
1/16W
R2154
2
1
10K
5% 1/16W
402
MF-LF
R2143
1
2
402
1/16W MF-LF
5%
10K
R2140
1
2
23B5
21A4 40D4
26C7
26C7
26B7
26C7
26A5
39C8
23C5 39C8
23C5 26A1
41A5 41B7 74A3
41A5 41C7 74A3
41B7 74A3
051-7537
A
109
21
SYNC_MASTER=T18_MLB
SYNC_DATE=06/26/2008
MCP HDA & MISC
MCP_SPKR
=PP3V3_S0_MCP
PM_SLP_S4_L
PM_SLP_S3_L
AUD_I2C_INT_L
HDA_SYNC_R
TP_MLB_RAM_SIZE
TP_MLB_RAM_VENDOR
SMC_ADAPTER_EN
SMC_IG_THROTTLE_L
MEM_EVENT_L
=PP3V3_S0_MCP_GPIO
SMC_WAKE_SCI_L
MEM_EVENT_L ODD_PWR_EN_L
HDA_RST_R_L
HDA_SYNC
ARB_DETECT
SM_INTRUDER_L
PM_RSMRST_L
JTAG_MCP_TRST_L
MCP_TEST_MODE_EN
JTAG_MCP_TMS
MCP_VID<1> MCP_VID<2>
HDA_BIT_CLK_R
HDA_RST_R_L
HDA_SDOUT_R
HDA_SYNC_R
=PP3V3R1V5_S0_MCP_HDA
PP3V3_G3_RTC
HDA_SDOUT
HDA_BIT_CLK
HDA_RST_L
TP_MCP_KBDRSTIN_L
PM_SYSRST_DEBOUNCE_L
MCP_THMDIODE_N
SMBUS_MCP_0_CLK
SPI_MOSI_R
SPI_MISO
PM_CLK32K_SUSCLK_R
JTAG_MCP_TCK
MCP_CLK25M_XTALIN MCP_CLK25M_XTALOUT
RTC_CLK32K_XTALIN RTC_CLK32K_XTALOUT
SPI_CS0_R_L
PP1V05_S0_MCP_PLL_NV
MCP_HDA_PULLDN_COMP
TP_SB_A20GATE
PM_SLP_RMGT_L
MCP_VID<1>
SMC_RUNTIME_SCI_L
SPI_CLK_R
=SPI_CS1_R_L_USE_MLB
HDA_BIT_CLK_R
HDA_SDOUT_R
PM_BATLOW_L
SMBUS_MCP_0_DATA
MCP_VID<2>
AP_PWR_EN
SMBUS_MCP_1_DATA
JTAG_MCP_TDO
JTAG_MCP_TDI
MCP_PS_PWRGD
RTC_RST_L
PM_PWRBTN_L
TP_MCP_LID_L
SMBUS_MCP_1_CLK
MCP_THMDIODE_P
MCP_VID<0>
MCP_CPUVDD_EN
HDA_SDIN0
PM_DPRSLPVR
MCP_VID<0>
MCP_CPU_VLD
MCP_GPIO_4 AUD_I2C_INT_L
=PP3V3_S3_MCP_GPIO
AP_PWR_EN
MCP_GPIO_4
=PP3V3R1V5_S0_MCP_HDA
ARB_DETECT
TP_MCP_BUF_SIO_CLK
SMC_IG_THROTTLE_L
39B8
24B8
29A5
19D1
24A8
26D4
34C7
24A8
22B3
74A3
40D4
28A5
18C1
74A3
61A8
61A8
74B3
74A3
74A3
74A3
21D3
22A5
74B3
74A3
61A8
52C7
31D5
21D8
8C5
21A7
21B3
21B3
8C5
21A7
21B3
21C3
21C3
21D4
21D4
21D4
21C4
8B5
7C3
24A2
74A3
21A7
21A7
23C5
21C3
21C3
21C3
8D3
21B3
21A4
8B5
21A4
Preliminary
GND
GND161
GND165 GND166
GND164
GND163
GND162
GND167 GND168
GND171
GND170
GND169
GND172 GND173
GND176
GND175
GND174
GND177 GND178
GND181
GND180
GND179
GND182 GND183 GND184
GND187
GND186
GND185
GND188 GND189
GND192
GND191
GND190
GND193 GND194
GND197
GND196
GND195
GND198
GND202
GND201
GND200
GND199
GND203
GND206 GND207
GND205
GND204
GND208
GND212
GND211
GND210
GND209
GND213 GND214
GND217
GND216
GND215
GND218 GND219
GND222
GND221
GND220
GND223 GND224 GND225
GND228
GND227
GND226
GND229 GND230
GND233
GND232
GND231
GND234 GND235
GND238
GND237
GND236
GND239 GND240
GND243
GND242
GND241
GND244
GND248
GND247
GND246
GND245
GND249
GND252
GND251
GND250 GND342
GND341
GND343
GND340
GND339
GND338
GND337
GND336
GND335
GND334
GND333
GND331 GND332
GND330
GND329
GND328
GND326 GND327
GND325
GND324
GND323
GND321 GND322
GND320
GND319
GND318
GND316 GND317
GND315
GND314
GND313
GND311
GND310
GND312
GND309
GND308
GND305 GND306 GND307
GND304
GND303
GND301
GND300
GND302
GND299
GND298
GND296
GND295
GND297
GND294
GND293
GND292
GND291
GND290
GND289
GND288
GND287
GND285 GND286
GND284
GND283
GND282
GND280 GND281
GND279
GND278
GND277
GND275 GND276
GND274
GND273
GND272
GND270
GND269
GND271
GND268
GND267
GND264 GND265 GND266
GND263
GND262
GND259 GND260 GND261
GND258
GND257
GND255
GND254
GND256
GND253
+VTT_CPUCLK
+VDD_CORE42
+3.3V_DUAL_USB2
+VTT_CPU17
+VTT_CPU16
+VTT_CPU15
+VTT_CPU14
+VTT_CPU13
+VTT_CPU12
+VTT_CPU11
+VTT_CPU10
+VTT_CPU1
+VDD_CORE7
+VDD_CORE1 +VDD_CORE2 +VDD_CORE3 +VDD_CORE4 +VDD_CORE5 +VDD_CORE6
+VDD_CORE13 +VDD_CORE14 +VDD_CORE15 +VDD_CORE16 +VDD_CORE17 +VDD_CORE18 +VDD_CORE19
+VDD_CORE21 +VDD_CORE22 +VDD_CORE23 +VDD_CORE24 +VDD_CORE25 +VDD_CORE26 +VDD_CORE27 +VDD_CORE28 +VDD_CORE29 +VDD_CORE30
+VDD_CORE32 +VDD_CORE33 +VDD_CORE34 +VDD_CORE35 +VDD_CORE36 +VDD_CORE37
+VDD_CORE39 +VDD_CORE40 +VDD_CORE41
+VDD_CORE47 +VDD_CORE48 +VDD_CORE49 +VDD_CORE50 +VDD_CORE51 +VDD_CORE52 +VDD_CORE53 +VDD_CORE54
+VTT_CPU51
+VTT_CPU50
+VTT_CPU47
+VTT_CPU46
+VTT_CPU45
+VTT_CPU43
+VTT_CPU42
+VTT_CPU41
+VTT_CPU40
+VTT_CPU39
+VTT_CPU38
+VTT_CPU37
+VTT_CPU36
+VTT_CPU35
+VTT_CPU34
+VTT_CPU32
+VTT_CPU31
+VTT_CPU30
+VTT_CPU29
+VTT_CPU28
+VTT_CPU26
+VTT_CPU25
+VTT_CPU24
+VTT_CPU23
+VTT_CPU22
+VTT_CPU21
+VTT_CPU20
+VTT_CPU19
+VTT_CPU18
+VTT_CPU9
+VTT_CPU8
+VTT_CPU7
+VTT_CPU6
+VTT_CPU5
+VTT_CPU4
+VTT_CPU3
+VDD_CORE38
+VTT_CPU33
+VTT_CPU27
+VDD_CORE55 +VDD_CORE56 +VDD_CORE57 +VDD_CORE58 +VDD_CORE59 +VDD_CORE60 +VDD_CORE61 +VDD_CORE62 +VDD_CORE63 +VDD_CORE64 +VDD_CORE65 +VDD_CORE66 +VDD_CORE67 +VDD_CORE68 +VDD_CORE69 +VDD_CORE70 +VDD_CORE71 +VDD_CORE72 +VDD_CORE73 +VDD_CORE74 +VDD_CORE75 +VDD_CORE76 +VDD_CORE77 +VDD_CORE78 +VDD_CORE79 +VDD_CORE80 +VDD_CORE81
+VBAT
+3.3V_1
+3.3V_8
+3.3V_DUAL1 +3.3V_DUAL2 +3.3V_DUAL3 +3.3V_DUAL4
+3.3V_DUAL_USB1
+3.3V_DUAL_USB3 +3.3V_DUAL_USB4
+VDD_AUXC1
+VDD_AUXC3
+VDD_AUXC2
+VDD_CORE43
+VTT_CPU2
+VDD_CORE46
+VDD_CORE45
+VDD_CORE44
+VTT_CPU52
+VDD_CORE31
+VTT_CPU49
+VTT_CPU48
+VTT_CPU44
+3.3V_7
+3.3V_6
+3.3V_5
+3.3V_4
+3.3V_3
+3.3V_2
+VDD_CORE20
+VDD_CORE12
+VDD_CORE11
+VDD_CORE10
+VDD_CORE9
+VDD_CORE8
POWER
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
1182 mA (A01)
450 mA (A01)
266 mA (A01)
16 mA
10 uA (G3)
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
80 uA (S0)
23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V)
250 mA
1139 mA
43 mA
105 mA (A01)
BGA
OMIT
MCP79-TOPO-B
(11 OF 11)
U1400
AH26 AH33
AH34 AH37
AH38
AJ39
AJ8
AK10
AK33 AK34
AK37
AK4 AK40
AL36 AL40
AL5
AM10 AM16
AM18
AM20 AM22
AM24
AM26 AM30
AM34 AM35
AM37
AM38
AM5
AM6
AM7
AM9
AP26
AN28 AN30
AN39
AN4
Y7
AP10 AU26
AP14
AU14 AP28
AP32
AP34 AP36
AP37
AP4
AP40
AP7 AW23
AR28
AR32 AR40
AT10
AR12 AT13
AT29 AT33
AT6
AT7
AT9
AY21
AY22
L12
AU12
AU28 AP33
AU32 AR30
AU36
AU38
AU4
G28
F20 AV28
AV32
AV36
AV4
AV7 AW11
G20
AR43 AW43
AY10
AV12 AY30
AY33
AY34 AY37
AY38 AY41
AV40 BA1
BA4 AW31
AY6
L35 BC33
BC37
BC41 AY14
BC5
C2 D10
D14 D15
D18
D19 D22
D23
D26 D30
D37
D6 E13
E17 E21
E25
E29 E33
F12
F16 F32
F8
G10 G12
G14 G16
BC12
G22 G24
AW20
G34 G4
G43
G6 G8
H11 H15
AW35
H23 AN8
G40
J12 J8
K10
K12 K18
K26 K37
K4
K40 K8
AU1
L40 L43
L5
M10 M34
M35 M37
Y28
Y33 Y34
Y35
Y37 Y38
AB17
AB16 AN26
AD7 M11
AA4
AB19 AY13
P11
Y6 T11
V11
Y11 AH16
T22
(10 OF 11)
BGA
MCP79-TOPO-B
OMIT
U1400
AD10
AE8 AB10
AD9
Y10 AB11
AA8
Y9
G18
H19
J20 K20
G26 H27
J28
K28
A20
T21
U21
V21
AA25
AA26
AA27
AA28 AC16
AC17 AC18
AC19
AC20 AC21
AA17
AC23
AC24 AC25
AC26
AC27 AC28
AD21 AD23
W27
V25
AA18
U25
AE19
AE21 AE23
AE25
AE26 AE27
AE28 AF10
AF11
AA19
AH12
AF2
AF21
AF23 AF25
AF3
AF4 AF7
AH23
AF9
AA20
AG10
AG11 AG12
AG21
AG23 AG25
AG3
AG4
AA21
AG6 AG7
AG5
AG8
AG9 AH1
AH10
AH11
W26
AH2
AA23
W28
AH25
Y21
AH21
AH3
AH4 AH5
AH6
AH7 AH9
AA24
W21 W23
Y23
W25
AF12
AA16
R32
P31
AF32
AE32 AH32
AJ32 AK31
AK32
AD32 AL31
AB32
AC32
B41 B42
C40
C41 C42
D39 D40
D41
E38 E39
E40
F37
F38 F39
G36
G37 G38
H35 H37
J34
J35
J36
K33
K34
K35 L32
L33
L34 M31
M32 M33
N31
N32
P32 Y32
AA32
T32 U32
V32
W32
AG32
SYNC_DATE=04/04/2008
SYNC_MASTER=T18_MLB
051-7537
A
109
22
MCP Power & Ground
=PP1V05_S0_MCP_FSB
=PPVCORE_S0_MCP
PP3V3_G3_RTC
=PP3V3_S0_MCP
=PP1V05_S5_MCP_VDD_AUXC
=PP3V3_S5_MCP
24C8 14B7 61B1 14A2 44D7
26D4
24B8
9C2
24D8
21C8
21C2
24C8
24B8
8D7 8C8
7C3
8C5
8B3
8A3
Preliminary
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
These internal pull-ups are missing in Revs A01 & A01P.
3.3V Interface Pull-ups
RADAR 5925345
MCP_SAFE_MODE SIGNAL TO SUPPORT ROM FAILURE OVERRIDE
1
MCP_A01&MCP_A01P&MCP_A01Q
402
MF-LF1/16W
5%
10K
R2402
2
21
R2401
402
MF-LF1/16W
5%
10K
MCP_A01&MCP_A01P&MCP_A01Q
21
R2400
MCP_A01&MCP_A01P&MCP_A01Q
5%
1/16W MF-LF
402
10K
21
R2404
5%
1/16W MF-LF
402
10K
MCP_A01&MCP_A01P&MCP_A01Q
21
R2413
MCP_A01&MCP_A01P&MCP_A01Q
5%
1/16W MF-LF
402
10K
21
R2405
MCP_A01&MCP_A01P&MCP_A01Q
1/16W MF-LF
402
10K
5%
13B6 19C4
7D5
17B6 31C7
6C5
13C3 21B7
6C5
13C3 21B7
21B7 26A1
21C7
21C7 39C5
21C7 39B8
21B7 39C8
21C7 39B8
R2430
402
21
5%
MF-LF
1/16W
0
39B5
21
R2412
5%
1/16W MF-LF
402
10K
MCP_A01&MCP_A01P&MCP_A01Q
MCP_A01&MCP_A01P&MCP_A01Q
21
R2411
402
MF-LF1/16W
5%
10K
21
R2410
MCP_A01&MCP_A01P&MCP_A01Q
10K
402
MF-LF1/16W
5%
2
R2403
5%
1/16W MF-LF
402
10K
1
MCP_A01&MCP_A01P&MCP_A01Q
SYNC_DATE=03/08/2008
SYNC_MASTER=T18_MLB
MCP79 A01 Silicon Support
051-7537
A
109
24
SMC_MCP_SAFE_MODE
MCP_SPKR
=PP3V3_S5_MCP_A01
JTAG_MCP_TMS
JTAG_MCP_TDI
SMC_RUNTIME_SCI_L
PM_PWRBTN_L
TP_MCP_LID_L
MAKE_BASE=TRUE
MCP_LID_L
PCIE_WAKE_L
PM_BATLOW_L
SMC_WAKE_SCI_L
PM_SYSRST_DEBOUNCE_L
PM_LATRIGGER_L
41B4
21C3
8A3
Preliminary
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)
NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)
5 mA (A01)
MCP SATA (DVDD) Power
NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF) Apple: 4x 2.2uF 0402 (8.8 uF)
1182 mA (A01)
7 mA (A01)
19 mA (A01)
333 mA (A01)
4771 mA (A01, DDR3)
MCP Core Power
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
MCP 3.3V Power
MCP Memory Power
MCP FSB (VTT) Power
Apple: 1x 2.2uF 0402 (2.2 uF)
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF) Apple: 7x 2.2uF 0402 (15.4 uF)
Apple: 2x 2.2uF 0402 (4.4 uF)
Apple: 5x 2.2uF 0402 (11 uF)
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
MCP 1.05V AUX Power
5 mA (A01)
MCP 3.3V/1.5V HDA Power
266 mA (A01)
MCP 3.3V AUX/USB Power
Apple: 1x 2.2uF 0402 (2.2 uF)
MCP79 Ethernet VRef
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
MCP 3.3V Ethernet Power
270 mA (A01)
MCP 1.05V RMGT Power
(No IG vs. EG data)
23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V)
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
MCP PCIE (DVDD) Power
105 mA (A01) 131 mA (A01)
83 mA (A01)
84 mA (A01)
84 mA (A01)
87 mA (A01)
37 mA (A01)
562 mA (A01)
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
206 mA (A01)
127 mA (A01)
43 mA (A01)57 mA (A01)
450 mA (A01)
19 mA (A01)
4V
4.7UF
20% X5R
402
C2582
1
2
20%
4.7UF
4V X5R 402
C2588
1
2
4.7UF
20%
4V X5R 402
C2584
1
2
4V
4.7UF
20% X5R
402
C2586
1
2
CERM 402-LF
20%
2.2UF
6.3V
C2555
1
2
4.7UF
4V
20% X5R
402
C2502
1
2
X5R 402-1
1UF
10% 10V
C2507
1
2
X5R 402-1
1UF
10% 10V
C2506
1
2
X5R 402-1
1UF
10% 10V
C2505
1
2
X5R 402-1
1UF
10% 10V
C2504
1
2
0.1UF
CERM
20%
402
10V
C2511
1
2
0.1UF
CERM
20%
402
10V
C2510
1
2
0.1UF
CERM
20%
402
10V
C2509
1
2
0.1UF
CERM
20%
402
10V
C2508
1
2
0.1UF
CERM
20%
402
10V
C2513
1
2
0.1UF
CERM
20%
402
10V
C2512
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2536
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2535
1
2
2.2UF
6.3V
20%
402-LF
CERM
C2534
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2533
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2532
1
2
20%
2.2UF
6.3V
402-LF
CERM
C2531
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2530
1
2
X5R 402-1
1UF
10% 10V
C2517
1
2
X5R 402-1
1UF
10% 10V
C2516
1
2
4.7UF
4V
20% X5R
402
C2515
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2572
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2571
1
2
4V
4.7UF
20% X5R
402
C2520
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2570
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2574
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2573
1
2
CERM 402-LF
20%
2.2UF
6.3V
C2576
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2575
1
2
2.2UF
6.3V
20%
402-LF
CERM
C2553
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2552
1
2
2.2UF
6.3V
20%
402-LF
CERM
C2551
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2550
1
2
0.1UF
20% CERM
402
10V
C2549
1
2
0.1UF
20% CERM
402
10V
C2548
1
2
0.1UF
20% CERM
402
10V
C2547
1
2
0.1UF
20% CERM
402
10V
C2546
1
2
0.1UF
20% CERM
402
10V
C2545
1
2
0.1UF
20% CERM
402
10V
C2544
1
2
0.1UF
20% CERM
402
10V
C2543
1
2
20% CERM
0.1UF
402
10V
C2542
1
2
0.1UF
CERM
20%
402
10V
C2541
1
2
20%
4.7UF
4V X5R 402
C2540
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2562
1
2
CERM 402-LF
20%
2.2UF
6.3V
C2564
1
2
4.7UF
20%
4V X5R 402
C2580
1
2
0603
30-OHM-5A
L2570
1 2
30-OHM-5A
0603
L2575
1 2
30-OHM-1.7A
0402
L2582
1 2
30-OHM-1.7A
0402
L2584
1 2
30-OHM-1.7A
0402
L2588
1 2
0402
30-OHM-1.7A
L2586
1 2
0402
30-OHM-1.7A
L2555
1 2
4.7UF
4V
20% X5R
402
C2500
1
2
4.7UF
4V
20% X5R
402
C2501
1
2
30-OHM-1.7A
0402
L2580
1 2
CERM
20%
0.1uF
402
10V
C2526
1
2
CERM
20%
0.1uF
402
10V
C2525
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2560
1
2
CERM
0.1UF
20%
402
10V
C2589
1
2
CERM
0.1UF
20%
402
10V
C2590
1
2
20%
4.7UF
4V X5R 402
C2595
1
2
30-OHM-1.7A
0402
L2595
1 2
1.47K
1/16W
1%
MF-LF
402
R2590
1
2
0.1UF
CERM
20%
402
10V
C2591
1
2
MF-LF
1%
1/16W
1.47K
402
R2591
1
2
18D3
CERM
20%
0.1uF
402
10V
C2521
1
2
0.1uF
20% CERM
402
10V
C2518
1
2
0.1uF
CERM
20%
402
10V
C2519
1
2
20% CERM
0.1UF
402
10V
C2581
1
2
CERM
0.1UF
20%
402
10V
C2583
1
2
20% CERM
0.1UF
402
10V
C2585
1
2
20% CERM
0.1UF
402
10V
C2587
1
2
CERM
20%
0.1UF
402
10V
C2596
1
2
CERM
20%
0.1uF
402
10V
C2529
1
2
20%
4.7uF
4V X5R 402
C2528
1
2
4.7UF
4V
20% X5R
402
C2503
1
2
SYNC_DATE=04/04/2008
SYNC_MASTER=T18_MLB
MCP Standard Decoupling
25
A
051-7537
109
=PP1V05_S0_MCP_PLL_UF
=PP1V05_S0_MCP_PEX_DVDD
=PP1V05_S0_MCP_SATA_DVDD
=PP3V3_ENET_MCP_RMGT
=PPVCORE_S0_MCP
=PP3V3_S0_MCP_PLL_UF
=PP1V05_ENET_MCP_RMGT
=PP1V05_S5_MCP_VDD_AUXC
=PP1V8R1V5_S0_MCP_MEM
=PP1V05_S0_MCP_FSB
=PP1V05_S0_MCP_AVDD_UF
=PP3V3_S5_MCP
=PP3V3R1V5_S0_MCP_HDA
=PP3V3_S0_MCP
MCP_MII_VREF
=PP3V3_ENET_MCP_RMGT
=PP1V05_ENET_MCP_PLL_MAC
PP1V05_ENET_MCP_PLL_MAC
MIN_LINE_WIDTH=0.4 MM
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
PP1V05_S0_MCP_PLL_FSB
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
VOLTAGE=1.05V
PP1V05_S0_MCP_PLL_SATA
PP1V05_S0_MCP_PLL_PEX
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
PP3V3_S0_MCP_PLL_USB
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
VOLTAGE=1.05V
PP1V05_S0_MCP_PEX_AVDD
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
VOLTAGE=1.05V
PP1V05_S0_MCP_SATA_AVDD
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
PP1V05_S0_MCP_PLL_CORE
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM
PP1V05_S0_MCP_PLL_NV
VOLTAGE=1.05V
22D3
24A6
61B1
14B7
24B6
18D3
44D7
16C7
14A2
21D8
22B3
18D3
8B7 8B7
18C7
22D5
18D3 22A3
16C3
9C2
22B3
21D3
21C2
18C7
8B7
8A8 8A8
8B1
8C8
8B5
8B1 8B3
8B7
8D7
8B7
8A3
8B5
8C5
8B1
8B1
18C6
14A6
20B6
17A6
20C3
8A8
8A8
16C6
21C7
Preliminary
A2
A1
SCL
A0
VCC
SDA
WP
GND
IN
BI
SCL
SDA
WP
VCC
GND
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
206 mA (A01) 206 mA (A01)
HDCP ROM
16 mA (A01)
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 2x 2.2uF 0402 (4.4 uF)
NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
16 mA (A01)
95 mA (A01)
190 mA (A01, 1.8V)
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: ???
REMOVE MCP 27MHZ CRYSTAL CRICUIT SINCE NOT SUPPORTING TV-OUT
SYNC FROM T18
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.
REMOVE DAC TERMINATIONS R2665,C2665 AND R2670 TO R2672
WF: Open question on which packge option(s) nVidia can support.
CHANGE C2651 TO R2651 TO GND PP3V3_S0_MCP_DAC
NOSTUFF PP3V3_S0_MCP_DAC RAIL COMPONENTS (L2650 AND C2650)
NO STUFF
C2650
1
2
CERM 402-LF
20%
2.2UF
6.3V
NO STUFF
L2650
1 2
0402
30-OHM-1.7A
C2620
1
2
402
NO STUFF
0.1UF
20% 10V
CERM
NO STUFF
402
1K
1% 1/16W MF-LF
R2630
2
1
C2630
1
2
0.1UF
10V
NO STUFF
CERM
402
20%
C2615
1
2
X5R 402
4V
4.7UF
20%
C2640
1
2
603
20%
6.3V
4.7UF
CERM
L2640
1 2
0402
30-OHM-1.7A
C2641
1
2
0.1uF
CERM 402
20% 10V
C2616
1
2
10V
0.1UF
CERM 402
20%
NOSTUFF
U2695
1
2
3
4
6
5
8
7
AT24C08
SOIC
C2690
1
2
CERM
20%
0.1UF
10V
402
R2690
1
2
402
1/16W
5%
MF-LF
10K
42C6
42C6
NOSTUFF
U2690
2
1
3
4
5
SOT23
AT24C01B
MF-LF
1/16W
5%
0
R2651
1
2
402
R2620
1
2
MF-LF
1K
1% 1/16W
402
C2610
1
2
6.3V
2.2UF
20%
402-LF
CERM
051-7537
A
109
26
MCP Graphics Support
SYNC_MASTER=T18_MLB
SYNC_DATE=12/12/2007
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
PP3V3_S0_MCP_DAC
VOLTAGE=3.3V
=PP3V3_S0_HDCPROM
MCP_IFPAB_RSET MCP_IFPAB_VPROBE
MIN_LINE_WIDTH=0.4 MM
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 MM
PP3V3_S0_MCP_VPLL
MCP_HDMI_VPROBE
MCP_HDMI_RSET
=PP1V05_S0_MCP_HDMI_VDD
=PP3V3R1V8_S0_MCP_IFP_VDD
=I2C_HDCPROM_SDA =I2C_HDCPROM_SCL
HDCPROM_WP
HDCPROM_WP
=PP3V3_S0_MCP_VPLL_UF
=PP3V3_S0_MCP_DAC_UF
73A3
73A3 73B3
73B3
18A6
18B6 18C3
8B5
18A3
18A3
18A6
18A6
18A6
8B7
8A7
25A8
25A7
8C5
8C5
Preliminary
IN
OUT
OUT
OUT
IN
OUT
IN
IN
IN
OUT
OUT
IN
NC NC
OUT
OUT
IN
OUT
OUT
OUT
IN
IN
OUT
Y
B
A
IN
IN
IN
OUT
OUT
OUT
VIN
GND
VOUTEN
NC
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
10K pull-up to 3.3V S0 inside MCP
Reset Button
but results in MCP79 ROMSIP sequence happening after CPU powers up.
SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for
LPC Reset (Unbuffered)
REMOVE R2824 AND NET PCI_CLK33M_SLOT_A
CHANGE Y2810 AND U2850 TO SMALLER PARTS
REMOVE UNUSED PCIE RESET SIGNALS
ALIAS MEM_VTT_EN TO =DDRVTT_EN
CHANGE RESET BUTTOM TO RESET PADS
SYNC FROM T18
PCIE Reset (Unbuffered)
MCP S0 PWRGD & CPU_VLD
MCP 25MHz Crystal
MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections,
MCPSEQ_MIX is cross between MLB and internal power sequencing, which results in earlier ROMSIP and MCP FSB I/O interface initialization.
VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).
NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.
CHANGE RTC COIN CELL TO LDO & SUPERCAP
RTC Power Sources
Platform Reset Connections
PLACE C2800 AT COOLEST SPOT ON MLB
PLACE C2819 CLOSE TO MCP79
RTC Crystal
12pF
C2810
402
CERM
5%
50V
21
402
C2811
1 2
12pF
5%
50V
CERM
1
2
NO STUFF
R2811
10M
402
MF-LF
5%
1/16W
19B3 74C3
R2883
1 2
33
MF-LF
5%
1/16W
402
PLACEMENT_NOTE=Place close to U1400
PLACEMENT_NOTE=Place close to U1400
R2881
1 2
33
5% 1/16W MF-LF
402
402
5%
1
MF-LF
1/16W
2
0
R2891
41D5
39C8
31A6
21B7
21B7
17B3
33
MF-LF
1/16W
5%
402
PLACEMENT_NOTE=Place close to U1400
21
R2826
402
PLACEMENT_NOTE=Place close to U1400
33
1/16W
5%
MF-LF
21
R2825
19B3 74C3
C2815
5%
1 2
12pF
50V
CERM
402
402
CERM
50V
5%
21
C2816
12pF
SM-3.2X2.5MM
1
42
3
CRITICAL
Y2815
25.0000M
MF-LF
5%
1/16W
R2816
NO STUFF
1M
402
2
1
21B7
21B7
39C5 74A3
22
1/16W
5%
MF-LF
402
PLACEMENT_NOTE=Place close to U1400
21
R2829
21B3 74A3
70C8
R2892
21
MF-LF
1/16W
5%
0
402
59C8 65A3
R2870
1 2
MF-LF
1/16W
5%
402
33
19C4
41D3 74C3
39C8 74C3
21B7 23C5
X5R
10%
1UF
10V
402
NO STUFF
2
1
C2899
33
402
MF-LF
1/16W
5%
21
R2899
NO STUFF
0
MF-LF
1/16W
5%
402
SILK_PART=SYS RST
2
1
R2890
0
XDP
MF-LF
1/16W
5%
402
21
R2898
39B8
10C6 13B3
27A5
R2871
1 2
MF-LF
5%
0
402
1/16W
Y2810
1 4
CRITICAL
32.768K
7X1.5X1.4-SM
C2800
0.08F
1
2
SM
3.3V XHHG
2%
1
2
0
5%
402
MF-LF
1/16W
R2815
2
1
0
5% 1/16W MF-LF
402
R2810
3
5
1
4
2
SOT665
TC7SZ08AFEAPE
U2850
21B3
60C7
39D8 64A4
21
R2851
402
0
1/16W
5%
MF-LF
MCPSEQ_MIX
2
1
C2850
402
20% CERM
0.1UF
MCPSEQ_SMC
10V
21
R2850
402
0
1/16W
5%
MF-LF
PLACEMENT_NOTE=Place close to U1400
MCPSEQ_SMC
21B7
21
R2852
MF-LF
5%
1/16W
0
402
MCPSEQ_MIX
21
R2853
MF-LF
5%
1/16W
0
402
MCPSEQ_SMC
21B7
0
1/16W MF-LF
5%
402
21
R2872
32B3
402
100
R2819
MF-LF
21
1UF
X5R
10%
2
1
402
10V
C2870
1
2
53
4
TSOT-23-5
MIC5232-2.8YD5
U2801
2
1
C2871
10% 10V X5R 402
0.47UF
C2819
10%
1UF
1
CERM 402
2
6.3V
PLACEMENT_NOTE=PLACE C2819 CLOSE TO MCP79
051-7537
28
A
109
SB Misc
SYNC_MASTER=RAYMOND
SYNC_DATE=04/05/2008
=PP3V42_G3H_RTC_D
RTC_CLK32K_XTALOUT
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.3 mm VOLTAGE=3.3V
PP3V3_G3_RTC
PP3V3_G3_SUPERCAP
MEM_VTT_EN_R
MAKE_BASE=TRUE
MEM_VTT_EN =DDRVTT_EN
PCIE_RESET_L
FC_RESET_L
MINI_RESET_L
MCP_CLK25M_XTALOUT
MCP_CLK25M_XTALIN
=PP3V3_S5_MCPPWRGD
VR_PWRGOOD_DELAY
S0_AND_IMVP_PGOOD
ALL_SYS_PWRGD
LPC_CLK33M_SMC_R
MCP_CPUVDD_EN
MCP_CPU_VLD
MCP_PS_PWRGD
MCP_CLK25M_XTALOUT_R
RTC_CLK32K_XTALOUT_R
XDP_DBRESET_L
PM_SYSRST_DEBOUNCE_L
PM_SYSRST_L
PM_CLK32K_SUSCLK_R
PM_CLK32K_SUSCLK
LPC_CLK33M_LPCPLUS
LPC_CLK33M_SMC
LPC_RESET_L
BKLT_PLT_RST_L
PCA9557D_RESET_L
DEBUG_RESET_L
SMC_LRESET_L
RTC_CLK32K_XTALIN
22A5 21C8
8D1
7C3
8A3
Preliminary
V-
V+
V-
V+
V-
V+
V-
V+
V-
V+
V-
V+
RESET*
A0 A1 A2
SCL SDA
P0 P1 P2
P5 P6 P7
P3 P4
THRM
VCC
GND
PAD
NC NC
NC
IN
IN
BI
VDD
VOUTD
VOUTC
VOUTB
VOUTA
SCL
SDA
A0
A1
GND
IN
BI
NC
NC
OUT
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
DAC channel A B A B C
Max DAC code 0x87 0x87 0x87 0x87 0x55
Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA
Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV
Signal aliases required by this page:
- =PPVTT_S3_DDR_BUF
- =PP3V3_S5_VREFMRGN
- =I2C_VREFDACS_SDA
- =I2C_PCA9557D_SDA
Min DAC code 0x00 0x00 0x00 0x00 0x00
- =I2C_PCA9557D_SCL
- =I2C_VREFDACS_SCL
(per DAC LSB)
Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA
Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V
Place close to U1000.AD26
Place close to J3100.1
MEM A VREF CAMEM A VREF DQ
Page Notes
10mA max load
- =PP3V3_S3_VREFMRGN
Power aliases required by this page:
Place close to J3200.1
Place close to J3200.126
VREFMRGN
MEM B VREF DQ
ADDR=0x30(WR)/0x31(RD)
Required zero ohm resistors when no VREF margining circuit stuffed
ADDR=0x98(WR)/0x99(RD)
NO_VREFMRGN
BOM options provided by this page:
SO-DIMM A and SO-DIMM B Vref settings should be margined separately
(i.e. not simultaneously) due to current limitation of TPS51116 regulator.
Place close to J3100.126
MEM B VREF CA
CPU FSB VREF
B4
B1
C4
C1
C2
C3
U2903
UCSP
MAX4253
21
R2904
402
100
1% 1/16W MF-LF
21
R2906
MF-LF
402
1% 1/16W
100
21
R2910
402
MF-LF
1/16W
1%
100
21
R2914
100
402
1%
1/16W MF-LF
21
R2912
402
100
MF-LF
1%
1/16W
B4
B1
C4
C1
C2
C3
UCSP
MAX4253
U2904
B4
B1
A1
A2
A3
U2904
UCSP
MAX4253
A4
CERM 402
1
10V
20%
2
0.1UF
VREFMRGN
C2902
B4
B1
A4
A1
A2
A3
U2903
UCSP
MAX4253
B4
B1
C4
C1
C2
C3
U2902
UCSP
MAX4253
B4
B1
A4
A1
A2
A3
U2902
UCSP
MAX4253
1%
200
1/16W MF-LF
R2911
1 2
402
1%
200
1/16W MF-LF
R2909
1 2
402
1%
200
1/16W MF-LF
R2905
1 2
402
1%
200
1/16W MF-LF
R2903
1 2
402
R2902
5%
402
100K
1/16W
1 2
MF-LF
R2901
402
MF-LF
100K
5%
1/16W
1 2
R2907
100K
402
5%
1 2
MF-LF
1/16W
U2901
PCA9557
VREFMRGN
QFN
8
17
11
10
16
14
13
12
9
7
6
2
1
5
4
3
15
20% 10V
VREFMRGN
C2904
1
2
402
CERM
0.1UF
402
1/16W
5%
1 2
MF-LF
100K
R2908
26C1
42A3
42A3
MSOP
DAC5574
9
6
8
510
4
2
1
VREFMRGN
7
3
U2900
42B3
42B3
CERM
20%
0.1UF
VREFMRGN
402
10V
C2901
1
2
20%
6.3V CERM 402-LF
2.2UF
C2900
VREFMRGN
CERM
VREFMRGN
0.1UF
10V
20%
C2905
1
2
402
1/16W
100K
21
R2913
5%
402
MF-LF
VREFMRGN
C2903
CERM
10V 402
1
2
20%
0.1UF
10B4 71B3
CRITICALR2903
NO_VREFMRGN
1116S0004
RES,MTL FILM,0,5%,0402,SM,LF
1 CRITICAL
NO_VREFMRGN
116S0004 R2909
RES,MTL FILM,0,5%,0402,SM,LF
CRITICAL1
NO_VREFMRGN
116S0004
RES,MTL FILM,0,5%,0402,SM,LF
R2911
CRITICAL1
NO_VREFMRGN
116S0004
RES,MTL FILM,0,5%,0402,SM,LF
R2905
SYNC_DATE=03/31/2008
29
109
A
051-7537
SYNC_MASTER=BEN
FSB/DDR3 Vref Margining
VREFMRGN_CPUFSB
VREFMRGN_CPUFSB_BUF
VREFMRGN_CA_SODIMMA_EN
VREFMRGN_CPUFSB_EN
VREFMRGN_DQ_SODIMMA_EN
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_CA_SODIMMB_EN
=I2C_PCA9557D_SCL =I2C_PCA9557D_SDA
=I2C_VREFDACS_SDA
=I2C_VREFDACS_SCL
PCA9557D_RESET_L
VREFMRGN_DQ_SODIMMA_EN
VREFMRGN_DQ_SODIMM
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_CA_SODIMMA_EN
VREFMRGN_CA_SODIMMB_EN
VREFMRGN_CPUFSB_EN
VREFMRGN_CA_SODIMMB_BUF
VREFMRGN_CA_SODIMMA_BUF
VREFMRGN_DQ_SODIMMA_BUF
VREFMRGN_CA_SODIMM
CPU_GTLREF
=PP3V3_S3_VREFMRGN
VREFMRGN_DQ_SODIMMB_BUF
PP0V75_S3_MEM_VREFDQ_A
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
PP0V75_S3_MEM_VREFDQ_B
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.3 mm
PP0V75_S3_MEM_VREFCA_A
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
PP0V75_S3_MEM_VREFCA_B
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
=PPVTT_S3_DDR_BUF
59D7
27C3
27B3
27D3
27C3
27B3
27A5
27A5
27A5
27A5
27A5
8D3
28D5
29D5
28B3
29B3
8C4
Preliminary
A6
A7
A11
A5
DQ33
VDD
A10/AP
VDD
VSS
SA1
VTT
VSS
DQS4* DQS4
VSS
DQ35
VSS
CK0*
SA0
VSS DQ58 DQ59
DM7
VSS
DQ57
DQ56
DQ50 DQ51
VSS
DQS6* DQS6
VSS
DQ49
DQ48
DQ43
VSS
DM5
VSS DQ42
SDA SCL
VTT
VSS
EVENT*
DQ62
VSS
DQ63
DQS7*
DQS7
DQ60 DQ61
VSS
VSS
DQ55
DQ54
DM6
VSS
DQ53
VSS
DQ52
DQ47
VSS
DQS5
VSS
DQ46
DQ41
VSS DQ40
DQ34
VSS
DQ32
TEST
VDD
VDD
S1*
A13
CAS*
WE*
BA0
VDD
VDD CK0
A1
A3
VDD
VDD A8
A9
A12/BC*
VDD
BA2
NC
VDD
CKE0
VSS
DQS5*
VSS DQ44 DQ45
DQ39
DQ38
VSS
VSS
DM4
VSS
DQ37
DQ36
VREFCA
VDD ODT1
NC
S0*
ODT0
BA1
RAS*
VDD
CK1*
VDD
VDD
A0
CK1
A2
VDD
A4
VDD
VDD
A14
A15
CKE1
VDD
VSS
VDDSPD
KEY
(SYMBOL 2 OF 2)
BI BIBI
BI
IN
BI BI
BI BI
BI BI
IN
BI
IN
BI
BI BI
IN
BI BI
BI BI
BI BI
BI BI
DQ16
DM3
DQ26 DQ27
DQ4
DQ31
DQ30
DQS3
DQS3*
DQ29
DQ28
DQ23
DQ22
DM2
DQ21
DQ20
DQ15
DQ14
RESET*
DM1
DQ13
DQ12
DQ7
DQ6
DQS0
DQS0*
DQ5
DQ24 DQ25
DQ19
DQ18
DQS2
DQS2*
DQ17
DQ11
DQ10
DQS1
DQS1*
DQ8 DQ9
DM0
DQ0 DQ1
VREFDQ
DQ3
DQ2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
KEY
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
(SYMBOL 1 OF 2)
IN
BI BI
BI BI
BI
BI
BI
BI
BI BI
BI
BI
IN IN
IN
IN
IN
IN
IN IN
IN IN
IN
IN
IN
IN
BI BI
BI BI
IN
BI BI
IN
BI
BI
IN
BI BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI BI
BI BI
BI
BI
BI
BI
OUT
BI IN
IN
IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
BI BI
BI BI
BI BI
BI
IN
BI
BI BI
BI BI
BI BI
BI BI
IN
BI BI
BI BI
NC
NC
NC
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
SPD ADDR=0xA0(WR)/0xA1(RD)
- =PP1V5_S0_MEM_A
- =PP0V75_S0_MEM_VTT_A
DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)
Signal aliases required by this page:
BOM options provided by this page:
(NONE)
- =I2C_SODIMMA_SCL
"Factory" (top) slot
Page Notes
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
- =PP1V5_S3_MEM_A
Power aliases required by this page:
- =I2C_SODIMMA_SDA
516-0201
516-0201
20%
10UF
C3100
1
2
6.3V X5R 603
6.3V
20%
10UF
C3101
X5R
1
2
603
76
F-RT-THB
199
185
74
78 80 82
88
92 94 96
102
98 100
106
104
112
110
108
116
114
122
120
118
126
130 132
128
136
134
138 140 142
148
146
144
152
150
73 75 77 79 81 83 85
89
87
93 95 97
101
99
111
109
113 115
119 121
117
123 125
129
133
141
147
145
149
158
156
154
162
160
164
168
166
172
170
174 176 178
184
182
180
188
186
194
190 192
198
196
204
202
200
157
155
153
161
159
163 165 167
171
169
173
177
175
181 183
179
187
193
191
189
197
103
151
143
139
137
135
127
203
201
195
124
107
105
131
91
84 86
90
J3100
DDR3-SODIMM-DUAL-M97-3
15B7 72D3
15B7 72D3
10V
20%
402
CERM
C3131
1
2
0.1UF2.2UF
20%
6.3V
402-LF
1
2
CERM
C3130
15B7 72D3
15B7 72D3
15A5 72D3
15D5 72C3
15D5 72C3
15B7 72D3
15B7 72D3
15B7 72D3
15B7 72D3
15A7 72C3
15B7 72D3
29C2 30C3
15B7 72D3
15C7 72D3
15C7 72D3
15A7 72C3
15C7 72D3
15C7 72D3
15B7 72D3
15B7 72D3
15D5 72C3
15D5 72C3
15B7 72D3
15C7 72D3
F-RT-THB 15 17
3
1
7
5
9 11 13
19
23
21
25 27 29
33
31
35
43
41
45
49
47
51 53 55
59
57
2
6 8 10 12 14 16 18 20 22 24 26 28 30
34
32
36 38 40
44
42
46 48 50
54
52
56 58 60 62 64 66 68 70 72
4
71
69
67
65
63
61
39
37
J3100
DDR3-SODIMM-DUAL-M97-3
CRITICAL
15A7 72C3
15B7 72D3
15B7 72D3
15B7 72D3
15B7 72D3
15D5 72C3
15B7 72D3
15D5 72C3
15B7 72D3
15C7 72D3
15C7 72D3
15D5 72C3
15D5 72C3
9D2
15C5 72D3
15B5 72D3
15C5 72D3
15B5 72D3
15B5 72D3
15B5 72D3
15B5 72D3
15B5 72D3
15B5 72D3
15C5 72D3
15C5 72D3
15A5 72D3
15B5 72D3
15C7 72D3
15C7 72D3
15B7 72D3
15B7 72D3
15A7 72C3
15C7 72D3
15B7 72D3
15A5 72D3
15C7 72D3
15C7 72D3
15A7 72C3
15C7 72D3
15C7 72D3
15C7 72D3
15C7 72D3
15D5 72C3
15C7 72D3
15D5 72C3
0.1UF
CERM 402
20% 10V
C3136
1
2
CERM
2.2UF
6.3V
20%
402-LF
C3135
1
2
15D7 72D3
15C7 72D3
15D7 72D3
15B7 72C3
15D7 72D3
15D7 72D3
15D7 72D3
15D7 72D3
15D5 72C3
15D5 72C3
15D7 72D3
15D7 72D3
21A4 21B3 29A5 39B8
CERM 402-LF
6.3V
2.2UF
20%
C3151
1
2
42D6
42D6
6.3V
2.2UF
20%
402-LF
CERM
C3150
1
2
15A5 72D3
15C5 72D3
15C5 72D3
15B5 72D3
15B5 72D3
15B5 72D3
15B5 72D3
15B5 72D3
15B5 72D3
15B5 72D3
15C5 72D3
15C5 72D3
15C5 72D3
15C5 72D3
15C5 72D3
15B5 72D3
15C7 72D3
15C7 72D3
15D5 72C3
15D5 72C3
15C7 72D3
15C7 72D3
15C7 72D3
15B7 72C3
15C7 72D3
15C7 72D3
15C7 72D3
15D7 72D3
15D7 72D3
15D5 72C3
15D5 72C3
15D7 72D3
15D7 72D3
15B7 72C3
15D7 72D3
15D7 72D3
15D7 72D3
15D7 72D3
R3141
MF-LF
1/16W
402
5%
10K
1
2
402
R3140
5% 1/16W MF-LF
10K
1
2
6.3V
402-LF
CERM
20%
2.2UF
C3140
1
2
2
1
0204-1
6.3V X6S-CERM
0.1UF
20%
C3110
2
1
0204-1
0.1UF
20%
6.3V X6S-CERM
C3117
2
1
0204-1
0.1UF
20%
6.3V X6S-CERM
C3116
2
1
0204-1
X6S-CERM
0.1UF
20%
6.3V
C3115
2
1
0204-1
0.1UF
20%
6.3V X6S-CERM
C3114
2
1
0204-1
0.1UF
20%
6.3V X6S-CERM
C3113
2
1
0204-1
0.1UF
20%
6.3V X6S-CERM
C3112
2
1
0204-1
X6S-CERM
6.3V
0.1UF
20%
C3111
31
109
A
051-7537
DDR3 SO-DIMM Connector A
SYNC_DATE=06/30/2008
SYNC_MASTER=BEN
=PP1V5_S3_MEM_A
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<11>
MEM_A_A<5>
MEM_A_DQ<33>
MEM_A_A<10>
MEM_A_SA<1>
=PP0V75_S0_MEM_VTT_A
MEM_A_DQS_N<4> MEM_A_DQS_P<4>
MEM_A_DQ<38>
MEM_A_CLK_N<0>
MEM_A_SA<0>
MEM_A_DQ<58> MEM_A_DQ<59>
MEM_A_DM<7>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<54> MEM_A_DQ<51>
MEM_A_DQS_N<6> MEM_A_DQS_P<6>
MEM_A_DQ<52>
MEM_A_DQ<49>
MEM_A_DQ<46>
MEM_A_DM<5>
MEM_A_DQ<47>
=I2C_SODIMMA_SDA =I2C_SODIMMA_SCL
MEM_EVENT_L
MEM_A_DQ<62> MEM_A_DQ<63>
MEM_A_DQS_N<7> MEM_A_DQS_P<7>
MEM_A_DQ<57> MEM_A_DQ<56>
MEM_A_DQ<50>
MEM_A_DQ<55>
MEM_A_DM<6>
MEM_A_DQ<48>
MEM_A_DQ<53>
MEM_A_DQ<42>
MEM_A_DQS_P<5>
MEM_A_DQ<43>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<34>
MEM_A_DQ<32>
MEM_A_CS_L<1>
MEM_A_A<13>
MEM_A_CAS_L
MEM_A_WE_L
MEM_A_BA<0>
MEM_A_CLK_P<0>
MEM_A_A<1>
MEM_A_A<3>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<12>
MEM_A_BA<2>
MEM_A_CKE<0>
MEM_A_DQS_N<5>
MEM_A_DQ<40> MEM_A_DQ<41>
MEM_A_DQ<39>
MEM_A_DQ<35>
MEM_A_DM<4>
MEM_A_DQ<36>
MEM_A_DQ<37>
PP0V75_S3_MEM_VREFCA_A
MEM_A_ODT<1>
MEM_A_CS_L<0> MEM_A_ODT<0>
MEM_A_BA<1> MEM_A_RAS_L
MEM_A_CLK_N<1>
MEM_A_A<0>
MEM_A_CLK_P<1>
MEM_A_A<2>
MEM_A_A<4>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_CKE<1>
=PPSPD_S0_MEM_A
MEM_A_DQ<25>
MEM_A_DM<2>
MEM_A_DQ<23> MEM_A_DQ<16>
MEM_A_DQ<4>
MEM_A_DQ<22>
MEM_A_DQ<19>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<31>
MEM_A_DQ<27>
MEM_A_DM<3>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<14>
MEM_A_DQ<11>
MEM_RESET_L
MEM_A_DM<1>
MEM_A_DQ<13>
MEM_A_DQ<9>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQ<5>
MEM_A_DQ<20> MEM_A_DQ<21>
MEM_A_DQ<30>
MEM_A_DQ<26>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQ<24>
MEM_A_DQ<15>
MEM_A_DQ<10>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQ<8> MEM_A_DQ<12>
MEM_A_DM<0>
MEM_A_DQ<0>
PP0V75_S3_MEM_VREFDQ_A
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<1>
8D3
8C7
27C1
8B5
27D1
Preliminary
IN
BI
BI BI
OUT
BI IN
IN
IN
IN IN
IN IN
IN
IN IN
IN IN
IN IN
IN IN
BI BI
BI BI
BI BI
BI
IN
BI BI
BI BI
BI BI
BI BI
IN
BI BI
BI BI
BI
VDD
A1
A3
VDD
A5
A8
VDD
A9
VDD
A12/BC*
VSS
DQ42 DQ43
DQ48 DQ49
VSS
VSS
DQ41
DQS4*
DM5
VDD
CKE1
A15 A14
VDD
A11
A7
A6
VDD
A4
A2
CK1
A0
VDD
VDD
CK1*
VDD
RAS*
BA1
ODT0
S0*
NC
ODT1
VDD
VREFCA
VDD
DQ36 DQ37
VSS
DM4
VSS
VSS DQ38 DQ39
DQ45
DQ44
VSS
DQS5*
VSS
CKE0
VDD NC
BA2
CK0
VDD
BA0
WE*
A13 S1*
VDD
VDD
TEST
DQ33
DQ32
VSS
DQ34
DQ40
VSS
DQ46
VSS
DQS5
VSS
DQ47
DQ52
VSS
DQ53
VSS
DM6
DQ54 DQ55
VSS
VSS
DQ61
DQ60
DQS7
DQS7*
DQ63
VSS DQ62
EVENT*
VSS
VTT
SCL
SDA
VSS
DQS6
DQS6*
VSS
DQ51
DQ50
A10/AP
VDD
CK0*
DQ35
VSS
DQS4
VSS
CAS*
VDD
DM7
VSS
DQ56
MTG PIN
MTG PIN MTG PIN MTG PIN MTG PIN
MTG PIN
MTG PIN
VSS
DQ57
VTT
SA1
SA0
DQ58
VSS
DQ59
VSS
VDDSPD
MTG PIN
MTG PINS
KEY
(2 OF 2)
DQ2 DQ3
VREFDQ
DQ1
DQ0
DM0
DQ9
DQ8
DQS1* DQS1
DQ10 DQ11
DQ17
DQS2* DQS2
DQ18 DQ19
DQ25
DQ24
DQ5
DQS0*
DQS0
DQ6 DQ7
DQ12 DQ13
DM1
RESET*
DQ14 DQ15
DQ20 DQ21
DM2
DQ22 DQ23
DQ28 DQ29
DQS3*
DQS3
DQ30 DQ31
DQ4
DQ27
DQ26
DM3
DQ16
(1 OF 2)
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
KEY
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BI
IN
BI BI
BI BI
BI BI
IN
BI
IN
BI
BI
BI BI
IN
BI BI
BI BI
BI BI
BI
BI
BI
IN
BI BI
BI BI
BI
BI
BI
BI
BI
BI BI
BI BI
IN IN
IN
BI
IN
IN IN
IN IN
IN IN
IN IN
IN IN
BI BI
BI BI
IN
BI BI
IN
BI BI
IN
BI
BI BI
BI BI
BI BI
BI BI
BI
IN
BI
BI BI
BI
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
Power aliases required by this page:
- =PP1V5_S3_MEM_B
Signal aliases required by this page:
BOM options provided by this page:
- =PP0V75_S0_MEM_VTT_B
Page Notes
- =PP1V5_S0_MEM_B
DDR3 GROUND RETURN CAPS (MCP SIDE)
- =I2C_SODIMMB_SDA
- =I2C_SODIMMB_SCL
"Expansion" (bottom) slot
(NONE)
DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)
SPD ADDR=0xA2(WR)/0xA3(RD)
516S0706
516S0706
15B1 72B3
X6S-CERM
C3214
0.1UF
20%
6.3V 0204-1
1
2
15D1 72A3
15D3 72B3
15D3 72B3
21A4 21B3 28A5 39B8
2
C3251
2.2UF
CERM 402-LF
6.3V
20%
1
42D6
42D6
C3250
2.2UF
6.3V
20%
402-LF
CERM
2
1
X6S-CERM
C3210
6.3V
0.1UF
20%
0204-1
1
2
C3201
20%
X5R
6.3V
10UF
603
2
1
C3231
10V
20%
402
CERM
0.1UF
2
1
603
6.3V
10UF
20%
1
2
X5R
C3200
15A1 72B3
15C1 72B3
15C1 72B3
15B1 72B3
15B1 72B3
15B1 72B3
15B1 72B3
15B1 72B3
15B1 72B3
15C1 72B3
15C1 72B3
15C1 72B3
15C1 72B3
15C1 72B3
15B1 72B3
15C3 72B3
15C3 72B3
15D1 72A3
C3213
X6S-CERM
0.1UF
6.3V
20%
0204-1
1
2
15D1 72A3
15C3 72B3
15C3 72B3
15C3 72B3
15B3 72B3
15C3 72B3
15C3 72B3
15D3 72B3
X6S-CERM
C3212
6.3V
20%
0.1UF
0204-1
1
2
15D3 72B3
15D1 72A3
15D1 72A3
15D3 72B3
15D3 72B3
15B3 72A3
15D3 72B3
15D3 72B3
15D3 72B3
15D3 72B3
C3230
CERM 402-LF
6.3V
20%
2.2UF
1
2
R3241
10K
1/16W MF-LF
5%
402
2
1
1
2
MF-LF
1/16W
402
5%
10K
R3240
1
2
C3240
20%
CERM 402-LF
6.3V
2.2UF
C3229
X6S-CERM
0.1UF
20%
6.3V 0204-1
1
2
C3228
X6S-CERM
0.1UF
20%
6.3V 0204-1
1
2
C3227
X6S-CERM
20%
6.3V
0.1UF
0204-1
1
2
C3226
X6S-CERM
0.1UF
20%
6.3V 0204-1
1
2
C3225
X6S-CERM
0.1UF
20%
6.3V 0204-1
1
2
15B3 72B3
C3224
X6S-CERM
0.1UF
20%
6.3V 0204-1
1
2
C3223
X6S-CERM
6.3V
0.1UF
20%
0204-1
1
2
C3222
X6S-CERM
6.3V
0.1UF
20%
0204-1
1
2
F-RT-BGA3
205
199
195
193
189 191
197
201 203
183
179
206
212211
210209
207 208
181
185 187
94
115
127
137 139
143
103 105 107
175 177
173
169 171
155
200 202 204
196 198
192
190
194
186 188
180 182 184
178
176
174
170 172
166 168
164
160 162
154 156 158
145 147
141
133
129 131
125
123
117
121
119
113
109 111
101
79
77
75
73
150 152
144 146 148
142
140
138
134 136
128
132
130
124 126
118 120 122
114 116
108 110 112
104 106
100
98
102
96
92
88 90
86
84
82
80
78
74 76
153
135
149 151
167
165
163
159
157
161
83
81
85 87 89 91 93 95 97 99
DDR3-SODIMM
J3200
15 17
3
1
7
5
9 11 13
19
23
21
25 27 29
33
31
35
43
41
45
49
47
51 53 55
59
57
2
6 8 10 12 14 16 18 20 22 24 26 28 30
34
32
36 38 40
44
42
46 48 50
54
52
56 58 60 62 64 66 68 70 72
4
71
69
67
65
63
61
39
37
F-RT-BGA3
CRITICAL
DDR3-SODIMM
J3200
15B3 72B3
X6S-CERM
C3211
6.3V
20%
0.1UF
0204-1
1
2
15A1 72B3
15D1 72A3
15D1 72A3
15B3 72B3
15B3 72B3
15B3 72B3
15B3 72B3
15A3 72B3
15B3 72B3
28C2 30C3
15B3 72B3
15C3 72B3
15B3 72B3
15B3 72B3
15A3 72B3
15B3 72B3
15C3 72B3
15C3 72B3
15C3 72B3
15D1 72A3
15D1 72A3
15C3 72B3
15C3 72B3
15C3 72B3
15A3 72B3
15B3 72B3
15B3 72B3
15B3 72B3
15B3 72B3
15D1 72A3
15B3 72B3
15B3 72B3
15D1 72A3
15B3 72B3
15B3 72B3
15B3 72B3
15D1 72A3
15D1 72A3
9D2
15C1 72B3
15C1 72B3
15B3 72B3
15B1 72B3
15B1 72B3
15B1 72B3
15B1 72B3
15B1 72B3
15B1 72B3
15B1 72B3
15C1 72B3
15C1 72B3
15B1 72B3
X6S-CERM
C3217
6.3V
20%
0.1UF
0204-1
1
2
15A1 72B3
15C3 72B3
15B3 72B3
15C3 72B3
15C3 72B3
15A3 72B3
15C3 72B3
15C3 72B3
15A1 72B3
15C3 72B3
X6S-CERM
C3216
20%
6.3V
0.1UF
0204-1
1
2
15C3 72B3
15A3 72B3
15C3 72B3
15C3 72B3
15C3 72B3
15D1 72A3
15D1 72A3
15C3 72B3
CERM
2
1
402
C3236
0.1UF
20% 10V
2.2UF
C3235
6.3V CERM
20%
402-LF
2
1
X6S-CERM
C3215
0.1UF
6.3V
20%
0204-1
1
2
15C3 72B3
15D3 72B3
15D3 72B3
15D3 72B3
15B3 72A3
15D3 72B3
15D3 72B3
15D3 72B3
15D1 72A3
SYNC_MASTER=BEN
32
109
A
051-7537
SYNC_DATE=05/09/2008
DDR3 SO-DIMM Connector B
MEM_B_DM<7>
=PP0V75_S0_MEM_VTT_B
=PP1V5_S3_MEM_B
MEM_B_DQS_N<2>
MEM_B_DQ<22>
MEM_B_DQ<24>
=PP1V5_S0_MEM_MCP
MEM_B_DQ<20>
MEM_B_DM<3>
MEM_B_DQ<26>
MEM_B_DQ<4>
MEM_B_DQ<27>
MEM_B_DQ<30>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQ<25>
MEM_B_DQ<29>
MEM_B_DQ<23>
MEM_B_DQ<18>
MEM_B_DM<2>
MEM_B_DQ<21>
MEM_B_DQ<16>
MEM_B_DQ<11>
MEM_B_DQ<8>
MEM_RESET_L
MEM_B_DM<1>
MEM_B_DQ<9>
MEM_B_DQ<12>
MEM_B_DQ<2>
MEM_B_DQ<7>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQ<5>
MEM_B_DQ<28>
MEM_B_DQ<19>
MEM_B_DQS_P<2>
MEM_B_DQ<17>
MEM_B_DQ<10>
MEM_B_DQ<15>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQ<13> MEM_B_DQ<14>
MEM_B_DM<0>
MEM_B_DQ<1> MEM_B_DQ<0>
PP0V75_S3_MEM_VREFDQ_B
MEM_B_DQ<6>
=PPSPD_S0_MEM_B
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_SA<1>
MEM_B_DQ<58>
MEM_B_DQ<56>
MEM_B_CAS_L
MEM_B_DQS_P<4>
MEM_B_DQ<39>
MEM_B_CLK_N<0>
MEM_B_A<10>
MEM_B_DQ<55> MEM_B_DQ<54>
MEM_B_DQS_N<6> MEM_B_DQS_P<6>
=I2C_SODIMMB_SDA =I2C_SODIMMB_SCL
MEM_B_DQ<62> MEM_B_DQ<57>
MEM_B_DQS_P<7>
MEM_B_DQ<63> MEM_B_DQ<59>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DM<6>
MEM_B_DQ<48>
MEM_B_DQ<52>
MEM_B_DQ<43>
MEM_B_DQS_P<5>
MEM_B_DQ<42>
MEM_B_DQ<45>
MEM_B_DQ<35>
MEM_B_DQ<37> MEM_B_DQ<32>
MEM_B_CS_L<1>
MEM_B_A<13>
MEM_B_WE_L
MEM_B_BA<0>
MEM_B_CLK_P<0>
MEM_B_BA<2>
MEM_B_CKE<0>
MEM_B_DQS_N<5>
MEM_B_DQ<40> MEM_B_DQ<44>
MEM_B_DQ<34>
MEM_B_DQ<38>
MEM_B_DM<4>
MEM_B_DQ<33>
MEM_B_DQ<36>
PP0V75_S3_MEM_VREFCA_B
MEM_B_ODT<1>
MEM_B_CS_L<0> MEM_B_ODT<0>
MEM_B_BA<1>
MEM_B_CLK_N<1>
MEM_B_A<0>
MEM_B_CLK_P<1>
MEM_B_A<2>
MEM_B_A<4>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<11>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_CKE<1>
MEM_B_DM<5>
MEM_B_DQS_N<4>
MEM_B_DQ<41>
MEM_B_DQ<49>
MEM_B_DQ<53>
MEM_B_DQ<46>
MEM_B_A<12> MEM_B_A<9>
MEM_B_A<8> MEM_B_A<5>
MEM_B_A<3> MEM_B_A<1>
MEM_B_RAS_L
MEM_B_DQ<3>
MEM_B_DQ<31>
MEM_B_SA<0>
MEM_B_DQ<47>
MEM_EVENT_L
MEM_B_DQS_N<7>
8C7
8D3
8B7
27C1
8B5
27C1
Preliminary
IN
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
avoid glitch on MEM_RESET_L.
before 1.5V starts to rise to
3.3V input must be stable before
MCP79 cannot control this signal directly since it must be high in sleep and MCP MEM rails are not powered in sleep.
DDR3 RESET Support
1/16W
5%
MF-LF
1K
402
R3310
1
2
CERM
0.1UF
MEMRESET_HW
402
10V
C3300
1
2
20%
5%
10K
MEMRESET_HW
1/16W MF-LF
402
R3300
1
2
16C3
MEMRESET_MCP
MF-LF
5% 1/16W
0
402
R3309
1
2
MMDT3904-X-G
MEMRESET_HW
SOT-363-LF
Q3305
5
3
4
R3305
1/16W
5%
MEMRESET_HW
MF-LF
20K
402
2
1
MEMRESET_HW
SOT-363-LF
MMDT3904-X-G
Q3305
2
6
1
28C2 29C2
5%
20K
MEMRESET_HW
1/16W MF-LF
402
R3301
1
2
DDR3 Support
SYNC_DATE=04/04/2008
SYNC_MASTER=T18_MLB
33
109
A
051-7537
MCP_MEM_RESET_L
MEM_RESET_L
MEM_RESET_RC_L
MEM_RESET
=PP1V5_S3_MEMRESET
=PP3V3_S5_MEMRESET
8D3
8A3
Preliminary
OUT
S
G
D
IN
IN
BI
NC NC
IN IN
IN
IN
OUT
OUT
BI
BI
OUT OUT
Y
B
A
IN
NC
NC
SYM_VER-1
SYM_VER-1
SYM_VER-1
D
S G
D
S G
OUT
OUT
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
CAMERA
206 mA nominal max
BLUETOOTH
ALS
AIRPORT
1000 mA peak
750 mA nominal max
5V S3 WLAN FET
26 mOhm @4.5V
0.8 A (EDP)
FDC606P
P-TYPE
MOSFET
LOADING
RDS(ON)
CHANNEL
275 mA peak
518S0610
7D5
17B6 23C5
SOT-6
FDC606P_G
4
3
6521
Q3450
20347-325E-12
CRITICAL
F-RT-SM
9
8
7
6
5
4
32
31
30
3
29
28
27
26
25
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
J3401
0402-LF
FERR-120-OHM-1.5A
2 1
L3405
34C6
42D1
42D1
FERR-120-OHM-1.5A
0402-LF
2 1
L3404
CERM
402
20% 10V
0.1uF
2
1
C3452
16V
0.1uF
10% X5R 402
PLACEMENT_NOTE=Place close to J3401.
21
C3430
17B3 73D3
17B3 73D3
402
0.1uF
X5R16V
PLACEMENT_NOTE=Place close to J3401.
10%
21
C3431
17C3 73D3
17C3 73D3
20D3 74C3
20D3 74C3
20% 10V
402
0.1uF
CERM
PLACEMENT_NOTE=Place close to Q3450.
2
1
C3421
20C3 74B3
20C3 74B3
7D5
17B6 73D3
7D5
17B6 73D3
SOT665
TC7SZ08AFEAPE
4
5
3
1
2
U3401
26C1
SOT-553
74LVC1G17DRL
4
5
13
2
U3402
PLACEMENT_NOTE=Place close to Q3450.
10V
805
10UF
X5R
20%
2
1
C3420
402
MF-LF
1/16W
33K
5%
2
1
R3453
402
MF-LF
5% 1/16W
62K
2
1
R3454
402
CERM
1UF
6.3V
10%
2
1
C3453
CRITICAL
PLACEMENT_NOTE=Place close to J3401.
DLP11S
90-OHM-100MA
4 3
21
L3401
CRITICAL
L3402
1 2
34
DLP0NS
90-OHM
PLACEMENT_NOTE=Place close to J3401.
CRITICAL
L3403
1 2
34
PLACEMENT_NOTE=Place close to J3401.
90-OHM DLP0NS
SOT563
SSM6N15FEAPE
1
2
6
Q3401
SOT563
SSM6N15FEAPE
4
5
3
Q3401
17C6
9C6
17C6
21A3 21B3 34C7
402
10% 16V
0.1UF
X5R
21
C3450
402
10% X5R
16V
0.033UF
2
1
C3451
1/16W
5%
402
MF-LF
100K
21
R3450
1/16W
10K
MF-LF
5%
402
2
1
R3451
0.1uF
402
CERM
20% 10V
PLACEMENT_NOTE=Place close to J3401.
2
1
C3422
051-7537
SYNC_DATE=04/22/2008
SYNC_MASTER=YITE
A
109
34
Right Clutch Connector
MINI_CLKREQ_Q_L
MINI_RESET_CONN_L
CONN_USB2_BT_N
=PP3V3_S3_WLAN
I2C_ALS_SDA
PP5V_WLAN_F
WLAN_SMIT_RC
WLAN_SMIT_BUF
USB_CAMERA_P
USB_BT_N
MINI_RESET_L
PCIE_CLK100M_MINI_P
PCIE_WAKE_L
I2C_ALS_SCL
=PP5V_S3_BTCAMERA
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V
PCIE_CLK100M_MINI_N
PM_WLAN_EN_L
MIN_LINE_WIDTH=1 mm VOLTAGE=5V
MIN_NECK_WIDTH=0.5 mm
=PP5V_S3_WLAN
P5VWLAN_SS
PP5V_WLAN_F
MIN_NECK_WIDTH=0.5 mm
MIN_LINE_WIDTH=1 mm VOLTAGE=5V
CONN_USB2_BT_P
MINI_CLKREQ_L
PCIE_MINI_R2D_C_N
PCIE_MINI_R2D_C_P
PCIE_CLK100M_MINI_CONN_P
AP_PWR_EN
USB_CAMERA_N
PCIE_CLK100M_MINI_CONN_N
PCIE_MINI_R2D_N
PCIE_MINI_R2D_P
PCIE_MINI_D2R_N
PCIE_MINI_D2R_P
PCIE_MINI_PRSNT_L
USB_CAMERA_CONN_N
USB_CAMERA_CONN_P
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm
PP5V_WLAN
VOLTAGE=5V
USB_BT_P
MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V
PP5V_S3_BTCAMERA_F
MIN_NECK_WIDTH=0.25 mm
73D3
73D3
73D3
73D3
74C3
74C3
7D5
7C5
7C5
8D3
31C3
8C3
8C3
31A5
7D5
7D5
7D5
7D5
7D5
7D5
7C3
7D5
Preliminary
IN IN
OUT
OUT
NC
NC NC
NC
OUT
IN
IN
OUT OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
Venice Connector
9B5
73D3
9B5
73C3
9C5
26C1
25
26
24
23
1
5
7
9
11
13
15
17
19
21
3
2
4
6
8
10
16
18
20
22
M-ST-SM
503219-0221
CRITICAL
J3501
14
12
VENICE
9C5
9B5
73D3
9B5
73D3
1
10%
PLACEMENT_NOTE=Place close to J3501.
C3572
X5R16V
0.1uF
2
402
VENICE
0.1uF
X5R16V 40210%
1 2
C3573
PLACEMENT_NOTE=Place close to J3501.
VENICE
9B5
73D3
9B5
73D3
SYNC_DATE=03/13/2008
SYNC_MASTER=YITE
VENICE CONNECTOR
051-7537
A
35
109
PCIE_FC_R2D_P PCIE_FC_R2D_N
=PP1V5_FC_CON
FC_PRSNT_L FC_RESET_L
PCIE_CLK100M_FC_N
PCIE_CLK100M_FC_P
=PP3V3_FC_CON
FC_CLKREQ_L
PCIE_FC_D2R_N
PCIE_FC_D2R_P
PCIE_FC_R2D_C_P PCIE_FC_R2D_C_N
73D3
73D3
8B7
8B5
Preliminary
IN IN IN IN
IN
IN BI
IN
IN
BI
BI
BI
BI
BI BI
BI BI
OUT
OUT OUT OUT OUT
OUT
IN
IN
TXD[2]
TXCTL
AVDD33
FB12
DVDD12
AVDD12
RXC
MDIO
GND
TXD[3]
RXD[0]
MDI+[0]
CKXTAL1 CKXTAL2
CLK125
RSET
PHYRSTB*
MDC
RXCTL
MDI-[2]
MDI+[2]
MDI+[3]
MDI+[1] MDI-[1]
ENSWREG
TXD[1]
TXD[0]
RXD[3]/AN1
RXD[1]/TXDLY
TXC
MDI-[3]
LED1/PHYAD1
LED2/RXDLY
LED0/PHYAD0
RXD[2]/AN0
MDI-[0]
REGOUT
VDDREG
DVDD33
REFERENCE
RGMII/MII
MEDIA DEPENDENT
MANAGEMENT
CLOCK
RESET
LED
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
ENET_RESET_L IS NOT ASSERTED WHEN WOL IS ACTIVE. HENCE, RC (C3725 AND R3725) ARE NOT STUFFED.
Alias to =PP3V3_ENET_PHY for internal switcher.
Reserved for EMI per RealTek request.
PLACE R3796 CLOSE TO U1400, PIN D24
Alias to GND for external 1.05V supply.
If internal switcher is used, must place inductor within 5mm of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.
NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.
1x 0.1uF caps within 5mm of U3700 pins 44 & 45.
If internal switcher is used, must place 1x 22uF &
Configuration Settings:
PHYAD = 01 (PHY Address 00001) AN[1:0] = 11 (Full auto-negotiation)
TXDLY = 0 (No TXCLK Delay)
RXDLY = 0 (RXCLK transitions with data)
WF: Marvell numbers, update for Realtek
(221mA typ - 1000base-T) ( 7mA typ - Energy Detect)
(19mA typ - Energy Detect)
(43mA typ - 1000base-T)
WF: Marvell numbers, update for Realtek
If internal switcher is not used, VDDREG and REGOUT can float.
0
MF-LF
5%
1/16W
402
R3724
1 2
20% CERM
402
10V
NO STUFF
0.1UF
C3725
1
2
2.49K
1%
1/16W
402
MF-LF
R3730
1
2
5%
4.7K
1/16W
NO STUFF
402
MF-LF
R3725
1
2
10K
5%
MF-LF
1/16W
402
R3720
1
2
CRITICAL
FERR-120-OHM-1.5A
0402-LF
L3705
1
2
0.1UF
16V X5R 402
10%
C3705
1
2
0.1UF
16V X5R 402
10%
C3706
1
2
0.1UF
16V X5R 402
10%
C3700
1
2
16V
0.1UF
X5R 402
10%
C3701
1
2
0.1UF
16V X5R 402
10%
C3702
1
2
18D3 75C3
18D3 75C3
18D3 75C3
18D3 75C3
18C3 75C3
18C3 75D3
18C3 75D3
18C3 75C3
34A3 75D3
35B7 75C3
35C7 75C3
35B7 75C3
35C7 75C3
35B7 75C3
35C7 75C3
35C7 75C3
35C7 75C3
MF-LF
5%
1/16W
22
402
R3790
1 2
402
MF-LF1/16W
5%
22
R3791
1 2
402
MF-LF1/16W
5%
22
R3792
1 2
402
22
MF-LF1/16W
5%
R3793
1 2
402
22
MF-LF1/16W
5%
R3794
1 2
402
22
MF-LF1/16W
5%
R3795
1 2
18D6 75D3
18D6 75D3
18D6 75D3
18D6 75D3
18D6 75D3
18D6 75D3
402
4.7K
MF-LF
5%
1/16W
R3755
1
2
402
4.7K
MF-LF
5%
1/16W
R3756
1
2
9D2
402
MF-LF
5%
4.7K
1/16W
R3752
1
2
402
4.7K
MF-LF
5% 1/16W
R3757
1
2
1/16W
5%
4.7K
MF-LF
402
R3750
1
2
MF-LF
4.7K
5% 1/16W
402
R3751
1
2
0.1UF
16V X5R 402
10%
C3715
1
2
16V
0.1UF
X5R 402
10%
C3716
1
2
FERR-120-OHM-1.5A
0402-LF
CRITICAL
L3715
1
2
0.1UF
16V X5R
10%
402
C3711
1
2
0.1UF
16V X5R 402
10%
C3710
1
2
10%
402
X5R
0.1UF
16V
C3714
1
2
402
5%
CERM
50V
10PF
NO STUFF
C3790
1
2
MF-LF
402
1/16W
5%
0
R3796
1 2
18D3 75D3
TQFP
OMIT
CRITICAL
RTL8211CLGR
U3700
10
40
6
41
42 43
32
28
36
152137
39
3
7
203347
34 35 38
30
2
1
5
4
9
8
12
11
31
29
48
46
19
13
14 16 17 18
22
27
23 24 25 26
44
45
SYNC_DATE=05/23/2008
Ethernet PHY (RTL8211CL)
SYNC_MASTER=SUMA
A
37
109
051-7537
ENET_TXD<2>
PP3V3_ENET_PHYAVDD
MIN_LINE_WIDTH=0.6 MM VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
PP1V05_ENET_PHYAVDD
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
=PP1V05_ENET_PHY
ENET_CLK125M_RXCLK_R
ENET_RXD_R<0>
ENET_MDI_P<0>
TP_RTL8211_CLK125
ENET_RXCTL_R
ENET_MDI_N<2>
ENET_MDI_P<2>
ENET_MDI_P<3>
ENET_MDI_P<1> ENET_MDI_N<1>
ENET_TXD<1>
ENET_RXD_R<3>
ENET_RXD_R<1>
ENET_MDI_N<3>
RTL8211_PHYAD1 RTL8211_RXDLY
RTL8211_PHYAD0
ENET_RXD_R<2>
ENET_MDI_N<0>
=RTL8211_REGOUT
=PP3V3_ENET_PHY_VDDREG
=PP3V3_ENET_PHY
ENET_CLK125M_RXCLK
ENET_RXD<0> ENET_RXD<1> ENET_RXD<2> ENET_RXD<3>
ENET_RX_CTRL
ENET_CLK125M_TXCLK
TP_RTL8211_CKXTAL2
RTL8211_RSET
ENET_TX_CTRL
ENET_MDC
ENET_RESET_L
RTL8211_PHYRST_L
ENET_TXD<3>
ENET_MDIO
ENET_CLK125M_TXCLK_R
=RTL8211_ENSWREG
ENET_TXD<0>
RTL8211_CLK25M_CKXTAL1
8B1
75D3
75D3
75D3
75D3
75D3
75D3
9D2
9D2
8B1
75D3
Preliminary
G
DS
IN
OUT
OUT
D
SG
IN
D
S G
IN
IN
D
SG
D
SG
D
S
G
D
SG
IN
D
SG
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
WLAN Enable Generation
"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))
NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
I(max) = 1.7A (85C)
Rds(on) = 90mOhm max
@ 2.5V Vgs:
3.3V ENET FET
1.05V ENET FET
MOBILE:
RTL8211 25MHz Clock
1.8V Vgs
=P1V05ENET_EN. Nets separated on
Recommend aliasing PM_SLP_RMGT_L and
ARB for alternate power options.
Non-ARB:
=P3V3ENET_EN. Nets separated on
Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.
NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.
Recommend aliasing PM_SLP_RMGT_L and
ARB for alternate power options.
Pull-up is with power FET.
CRITICAL
NTR4101P
SOT-23-HF
2
1
3
Q3810
10%
402
0.01UF
16V
CERM
2 1
C3810
0.033UF
10%
402
X5R
16V
2
1
C3811
MF-LF
402
100K
5%
1/16W
21
R3810
18C3 75D3
402
22
MF-LF
5%
1/16W
PLACEMENT_NOTE=Place close to U1400
21
R3895
33B6 75D3
16V
0.01UF
CERM 402
10%
2
1
C3841
0.1UF
20%
CERM
10V
402
2
1
C3840
31C1
SSM6N15FEAPE
SOT563
4
5
3
Q3805
21C7 39D5 40B2
6
1
2
SOT563
SSM6N15FEAPE
Q3801
21A3 21B3 31D5
7C3
21C3 39C5 41A5 64D5 68D8
SSM6N15FEAPE
SOT563
1
2
6
Q3805
SOT563
SSM6N15FEAPE
1
2
6
Q3841
69.8K
1/16W
1%
402
MF-LF
2
1
R3842
SI2312BDS
SOT23
CRITICAL
2
1
3
Q3840
10K
5%
402
MF-LF
1/16W
2
1
R3800
3
4
5
SOT563
SSM6N15FEAPE
Q3801
9D2
SSM6N15FEAPE
SOT563
4
5
3
Q3841
9D2
10K
402
1/16W
1%
MF-LF
21
R3841
5%
1/16W
1 2
100K
402
MF-LF
R3840
Ethernet & AirPort Support
051-7537
A
109
38
SYNC_MASTER=SUMA
SYNC_DATE=07/01/2008
AP_PWR_EN
P1V05ENET_SS
P1V05ENET_EN_L_RC
=P3V3ENET_EN
SMC_ADAPTER_EN
PM_WLAN_EN_L
AC_OR_S0_L
=P1V05ENET_EN
=PP1V05_ENET_FET
P3V3ENET_EN_L
MCP_CLK25M_BUF0_R
RTL8211_CLK25M_CKXTAL1
P3V3ENET_SS
=PP3V3_ENET_FET
PM_SLP_S3_L
=PP1V05_ENET_P1V05ENETFET
P1V05ENET_EN_L
=PP3V3_S5_P3V3ENETFET
=PP3V3_S5_P1V05ENETFET
8B2
8B2
8B3
8A3
8A3
Preliminary
BI
BI
BI
BI
BI
BI
BI
BI
RX
TX
RX
TX
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
- COPY THIS PAGE FROM K36 CSA.39
PLACE ONE CAP EACH NEAR PINS 3 AND 4 OF T3901 AND T3902
ETHERNET CONNECTOR
514-0596
33B3 75C3
33B3 75C3
33B3 75C3
33B3 75C3
33B3 75C3
33B3 75C3
33B3 75C3
33B3 75C3
1 2
4
12
11
10
9
6
5
3
7 8
F-RT-TH
RJ45-M97-2
J3900
CRITICAL
0.1UF
10%
402
16V X5R
2
1
C3902
X5R
10%
402
16V
0.1UF
2
1
C3900
402
0.1UF
X5R
16V
10%
2
1
C3901
0.1UF
402
16V X5R
10%
2
1
C3903
402
1%
1/16W MF-LF
75
21
R3900
75
402
1%
MF-LF1/16W
21
R3901
75
MF-LF
402
1/16W
1%
21
R3902
MF-LF
1%751/16W
402
21
R3903
2KV
10%
1206
CERM
CRITICAL
1000PF
2
1
C3910
CRITICAL
TLA-6T213HF
SM
9
8
76
5
4
3
2
12
11
10
1
T3902
CRITICAL
TLA-6T213HF
SM
9
8
76
5
4
3
2
12
11
10
1
T3901
ETHERNET CONNECTOR
SYNC_DATE=04/04/2008
SYNC_MASTER=SUMA
39
A
051-7537
109
ENET_MDI_TRAN_P<1>
ENET_MDI_TRAN_N<1>
ENET_CONN_CTAP
ENET_MDI_N<1>
ENET_MDI_TRAN_P<3>
ENET_CENTER_TAP<3>
ENET_CENTER_TAP<1>
ENET_MDI_P<3>
ENET_MDI_N<2>
ENET_MDI_P<2>
ENET_MDI_N<0>
ENET_CENTER_TAP<0>
ENET_MDI_N<3>
ENET_MDI_P<1>
ENET_MDI_TRAN_P<2>
ENET_MDI_P<0>
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
ENET_BOB_SMITH_CAP
ENET_MDI_TRAN_P<0>
ENET_MDI_TRAN_N<0>
ENET_CENTER_TAP<2>
ENET_MDI_TRAN_N<3>
ENET_MDI_TRAN_N<2>
75C3
75C3
75C3
75C3
75C3
75C3
75C3
75C3
Preliminary
SGD
IN
OUT
OUT
SYM_VER-1
SYM_VER-1
IN
IN
OUT
OUT
SYM_VER-1
IN
OUT
SYM_VER-1
NC NC
NC
NC
NC NC
D
SG
D
SG
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
518S0654
Indicates disc presence
516S0617
ensure the drive is unpowered in S3/S5.
NOTE: 3.3V must be S0 if 5V is S3 or S5 to
SATA ODD Port
SATA HDD Port
ODD Power Control
SOT-6
FDC606P_G
CRITICAL
Q4590
1 2 5 6
3
4
20D6 73A3
20D6 73A3
20D6 73A3
402
0.01UF
16V10%
CERM
PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520
C4521
1 2
402
CERM
10% 16V
0.01UF
PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79
C4520
1 2
DLP11S
90-OHM-100MA
PLACEMENT_NOTE=Place FL4525 close to J4500
FL4525
1 2
34
90-OHM-100MA
DLP11S
PLACEMENT_NOTE=Place FL4520 close to J4500
FL4520
12
3 4
402
CERM
10% 16V
0.01UF
PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500
C4526
1 2
21
C4525
PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526
0.01UF
16V10%
CERM
402
16V
10%
CERM
402
0.01UF
C4596
1 2
20D6 73A3
20D6 73A3
0.01UF
16V10%
CERM
C4510
402
21
0.01UF
16V10%
CERM
C4511
402
21
20D6 73A3
20D6 73A3
DLP11S
CRITICAL
FL4502
1 2
34
90-OHM-100MA
21B3
55560-0168
M-ST-SM-LF
CRITICAL
J4500
1
10
1112 1314
16
2
34 56 78 9
15
10%
402
CERM
0.068UF
10V
C4595
1
2
33K
MF-LF
1/16W
5%
402
R4590
1
2
7B7
39B8
402
10V
0.1UF
20% CERM
C4502
1
2
DLP11S
90-OHM-100MA
FL4501
12
3 4
CRITICAL
21
0603
FERR-70-OHM-4A
L4500
CRITICAL
0.01UF
16V10%
CERM
C4515
402
21
0.01UF
16V10%
CERM
C4516
402
21
10V CERM
20%
402
1
2
C4501
0.1UF
402
100K
5% 1/16W MF-LF
R4595
1 2
F-ST-SM
CRITICAL
20374020E31
J4501
1
10 11 12 13
15 16 17 18 19
2
20
21
22
3 4 5 6 7 8 9
14
SOT563
SSM6N15FEAPE
Q4596
6
2
1
5%
100K
402
1/16W MF-LF
R4596
5%
100K
402
1/16W MF-LF
R4597
SOT563
SSM6N15FEAPE
Q4596
3
5
4
20D6 73A3
051-7537
A
109
45
SATA Connectors
SYNC_MASTER=CHANGZHANG
SYNC_DATE=04/14/2008
VOLTAGE=5V
MIN_NECK_WIDTH=0.4mm
MIN_LINE_WIDTH=0.6mm
PP5V_SW_ODD
ODD_PWR_SS
=PP5V_S0_ODD
ODD_PWR_EN_LS5V_L
ODD_PWR_EN
SATA_ODD_R2D_C_P
SATA_ODD_D2R_P
SATA_ODD_R2D_C_N
SATA_ODD_D2R_N
SATA_ODD_D2R_UF_P
SATA_ODD_D2R_UF_N
SATA_ODD_R2D_UF_P
SATA_ODD_R2D_UF_N
SATA_ODD_R2D_P SATA_ODD_R2D_N
SATA_ODD_D2R_C_N SATA_ODD_D2R_C_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_C_P
SATA_HDD_D2R_P
SATA_HDD_D2R_N
SATA_HDD_D2R_UF_P
SATA_HDD_D2R_UF_N
SATA_HDD_R2D_UF_N
SATA_HDD_R2D_UF_P
ODD_PWR_EN_L
SMC_ODD_DETECT
=PP3V3_S0_ODD
=PP3V3_S0_ODD
=PP5V_S0_HDD
SATA_HDD_D2R_C_N
SATA_HDD_R2D_P
PP5V_S0_HDD_FLT
SATA_HDD_D2R_C_P
SATA_HDD_R2D_N
PLACEMENT_NOTE=Place C4510 close to MCP79 PLACEMENT_NOTE=Place C4511 next to C4510
PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501
PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501
PLACEMENT_NOTE=Place FL4501 close to J4501
PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501
PLACEMENT_NOTE=Place C4515 next to C4516 PLACEMENT_NOTE=Place C4516 close to J4501
PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501
73A3
7C3
73A3
7C5
73A3
73A3
36B7
36D5
73A3
73A3
7C5
73A3
73A3
7B7
8D5
73A3
73A3
73A3
73A3
7B7
7B7
7B7
7B7
73A3
73A3
73A3
73A3
8C5
8C5
8D5
7C5
7C5
7C3
7C5
7C5
Preliminary
OUT
BI
BI
SYM_VER-1
IN OUT
IN
SYM_VER-1
BI
BI
OUT
IOIONC
GND
VBUS
NC
IOIONC
GND
VBUS
NC
VCC
GND
SELOE*
D+ D-
Y+ Y-
M+ M-
IN
OUT2
TPAD
GND
OUT1
OC1*
EN2
EN1
OC2*
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
STUFF R4690 IF USING TPS2064(ACTIVE HIGH ENABLE)
STUFF R4691 IF USING TPS2060(ACTIVE LOW ENABLE)
We can remove C4690 later if the output cap of the 5V_S5 regulator is close enough.
Port Power Switch
USB/SMC Debug Mux
CAN NOSTUFF C4696 AND C4616 AFTER CHARACTERIZATION
We can add protection to 5V if we want, but leaving NC for now
USB PORT A (FRONT PORT)
SEL=1 Choose USB
Place L4600 and L4605 at connector pin
SEL=0 Choose SMC
USB PORT B (BACK PORT)
514-0606
514-0606
FERR-220-OHM-2.5A
0603
PLACEMENT_NOTE=NEAR J4600
CRITICAL
2
L4605
1
CASE-B2-SM
1
2
20%
6.3V
CRITICAL
C4696
100UF
POLY-TANT
603
X5R
C4695
1
2
6.3V
10UF
20%
CERM
20%
1
2
402
0.1UF
10V
C4691
20C2
20D3 74C3
20D3 74C3
SMC_DEBUG_YES
CERM
20% 10V
0.1UF
C4650
2
1
402
10K
2
1
1/16W
R4650
5%
402
MF-LF
CRITICAL
DLP0NS
90-OHM
L4600
21
3
PLACEMENT_NOTE=NEAR J4600
4
39B8 39C5 40B2 41C3
39B8 39C5 40B2 41C5
39B8
SMC_DEBUG_NO
1/16W MF-LF
0
5%
402
R4651
1 2
R4652
SMC_DEBUG_NO
0
402
5% 1/16W MF-LF
21
20%
C4605
CERM
402
16V
0.01uF
1
2
402
16V
20% CERM
1
2
C4615
0.01uF
L4615
FERR-220-OHM-2.5A
1 2
0603
CRITICAL
PLACEMENT_NOTE=NEAR J4610
CRITICAL
90-OHM
L4610
DLP0NS
21
34
PLACEMENT_NOTE=NEAR J4610
20%
6.3V 603
C4617
2
10UF
X5R
1
C4616
1
2
100UF
CRITICAL
20% POLY-TANT
6.3V CASE-B2-SM
20C3 74B3
20C3 74B3
20C2
CRITICAL
D4600
SLP1210N6
42 3
6
RCLAMP0502N
1
5
D4610
RCLAMP0502N
CRITICAL
SLP1210N6
1
5 42 3
6
20% X5R
10UF
1
2
C4690
603
NOSTUFF
6.3V
1 2
4
3
5 6
7 8
F-RT-TH-M97-3
USB
J4600
CRITICAL
1 2
4
3
5 6
7 8
F-RT-TH-M97-3
J4610
USB
CRITICAL
93
10
8
7 6
1 2
5 4
TQFN
CRITICAL
PI3USB102ZLE
U4650
SMC_DEBUG_YES
64C6
1/16W
5% MF-LF
R4691
0
402
2
1
NOSTUFF
5% 1/16W MF-LF
402
1
R4690
2
0
TPS2064DGN
U4690
CRITICAL
6
91
7
8
4
3 5
2
MSOP
External USB Connectors
SYNC_MASTER=YUAN.MA
051-7537
A
109
46
SYNC_DATE=01/18/2008
USB_EXTA_MUXED_P
USB_EXTB_N
USB_EXTB_P
CONN_USB_EXTA_P
CONN_USB_EXTA_N
CONN_USB_EXTB_N
VOLTAGE=5V
MIN_NECK_WIDTH=0.5 mm
MIN_LINE_WIDTH=0.5 mm
PP5V_S3_RTUSB_A_F
CONN_USB_EXTB_P
PP5V_S3_RTUSB_B_F
VOLTAGE=5V
MIN_NECK_WIDTH=0.5 mm
MIN_LINE_WIDTH=0.5 mm
USB_EXTA_MUXED_N
USB_DEBUGPRT_EN_L
=PP3V42_G3H_SMCUSBMUX
=USB_PWR_EN
SMC_TX_L
SMC_RX_L
USB_EXTA_P USB_EXTA_N
=PP5V_S3_EXTUSB
USB_EXTB_OC_L
USB_PWR_EN_R
USB_EXTA_OC_L
PP5V_S3_RTUSB_A_ILIM
MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=5V
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm
PP5V_S3_RTUSB_B_ILIM
74C3 74C3
74C3
74B3
74B3
74C3
8D1
8C3
Preliminary
IN
P0_3/INT1 P0_4/INT2 P0_5/TIO0 P0_6/TIO1
P0_7
P0_2/INT0
P0_1
THRM_PAD
NC
P1_7
P1_6/MISO
P1_5/SMOSI
P1_4/SCLK
P3_1
P3_0
P1_3/SSEL
P1_2/VREG
VDD
P1_1/D-
P1_0/D+
VSS
NC
P2_1
P2_0
P0_0
BI
BI
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
7A7
38A4
2
1
C4801
0.1UF
402
16V
10%
X7R-CERM
13
16
33
22
21
8
9
26
25
24
23
20
18
15
14
32
1
2
3
4
5
6
7
31
30
29
28
27
19
17
12
11
10
U4800
CRITICAL
OMIT
CY7C63833
QFN
2
1
C4803
402-1
X5R
10V
10%
1UF
20D3 74B3
20D3 74B3
21
R4808
402
MF-LF
1/16W
5%
PLACE R4808 NEAR J4800
4.7
PLACE R4806 NEAR J4800
MF-LF
1/16W
402
5%
R4806
10
21
21
R4800
MF-LF
5%
100
1/16W
402
PLACE R4807 NEAR J4800
5%
100
MF-LF
402
R4807
2
1/16W
1
10% 50V
0.001UF
CERM 402
C4808
1
2
PLACE C4808 NEAR J4800
PLACE R4805 NEAR J4800
MF-LF
1/16W
402
10
5%
R4805
1 2
PLACE C4807 NEAR J4800
10% 50V
0.001UF
CERM 402
C4807
1
2
PLACE C4806 NEAR J4800
X7R-CERM
10% 16V
0.1UF
C4806
1
2
402
PLACE C4805 NEAR J4800
16V
10%
0.1UF
C4805
1
2
X7R-CERM 402
CRITICAL
J4800
FF18-6A-R11AD-B-3H
6
5
4
3
2
1
F-RT-SM
2
1
C4804
10%
402
50V
0.001UF
CERM
051-7537
A
109
48
SYNC_DATE=05/28/2008
SYNC_MASTER=YUAN.MA
Front Flex Support
IR_RX_OUT_RC
IR_RX_OUT
=PP5V_S3_IR
USB_IR_P
DIFFERENTIAL_PAIR=USB2_IR
USB_IR_N
DIFFERENTIAL_PAIR=USB2_IR
IR_VREF_FILTER
SYS_LED_ANODE
SMC_LID
=PP5V_S3_IR
=PP3V42_G3H_LIDSWITCH
PP3V42_G3H_LIDSWITCH_R PP5V_S3_IR_R
SMC_LID_R SYS_LED_ANODE_R
IR_RX_OUT
CYPRESS ’ENCORE II’ USB CONTROLLER
P/N 338S0375
518S0692
47A5
38B4
40C2
38D7
38C4
8C3
40A6
39B5
8C3
8D1
7A7
7A7
7A7
7A7
7A7
Preliminary
IN
IN
IN
OUT
OUT
OUT
IN
IN
OUT
IN IN IN IN IN IN IN IN
IN
IN
OUT
IN
OUT
BI
IN
IN
OUT
BI OUT
IN
IN
OUT
IN
OUT OUT OUT OUT
IN
IN
IN
IN
IN IN
IN
IN
IN IN
IN
IN
IN
IN
OUT
IN
IN
BI BI BI BI BI BI
OUT OUT
OUT
IN
IN
OUT
IN
IN
BI
BI
OUT
IN
OUT
OUT
P13 P14 P15 P16 P66
P10 P11 P12
P17
P20 P21 P22 P23 P24 P25 P26 P27
P30 P31 P32 P33 P34
P36 P37
P40 P41 P42 P43 P44 P45 P46 P47
P50 P51 P52
P60 P61 P62 P63 P64 P65
P67
P70 P71 P72 P73 P74 P75 P76 P77
P80 P81
P84 P85 P86
P90 P91 P92 P93 P94 P95 P96 P97
P35
P83
P82
(1 OF 3)
PA5
PA4
PA0 PA1 PA2 PA3
PA6 PA7
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
PE0 PE1 PE2 PE3 PE4 PF0
PF1 PF2 PF3 PF4 PF5 PF6 PF7
PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7
PH0 PH1 PH2 PH3 PH4 PH5
(2 OF 3)
RES*
NMI
VSS
VCLVCC
NC
MD2
MD1
ETRST
AVSS
AVREF
AVCC
EXTAL
XTAL
(3 OF 3)
NC
OUT
OUT
OUT
NC
NC NC NC
NC
NC
NC
NC NC
NC NC NC
NC
NC
NC
NC
NC
NC NC
NC NC
NC
NC NC
IN
OUT
OUT
OUT
OUT
BI BI BI BI
IN IN IN
OUT
BI
IN IN IN IN
BI
BI
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
those designated as inputs require pull-ups.
Otherwise, TP/NC okay (was ISENSE_CAL_EN)
SMC_IG_THROTTLE_L for MG systems.
SMC_PB3:
(See below)
NOTE: Unused pins have "SMC_Pxx" names. Unused
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
(DEBUG_SW_1) (DEBUG_SW_2)
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
pins designed as outputs can be left floating,
NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.
(OC)
(OC)
NOTE: P94 and P95 are shorted, P95 could be spare.
22UF
805
CERM
20%
6.3V
C4902
1
2
19C3 41D3
40D6 41C3
40A3 40C2 40C7 47C3
10%
402
CERM-X5R
0.47UF
PLACEMENT_NOTE=Place C4907 close to U4900 pin F1
6.3V
C4907
1
2
10V 402
0.1UF
CERM
20%
C4903
1
2
10V
402
PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15
0.1UF
CERM
20%
C4920
1
2
402
MF-LF
5%
1/16W
4.7
PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15
R4999
1 2
10V 402
0.1UF
CERM
20%
C4904
1
2
SM
XW4900
12
21B7 23C5
60C7
10V 402
0.1UF
CERM
20%
C4905
1
2
21B7
64B1
26A8 64A4
40C5
10V 402
0.1UF
CERM
20%
C4906
1
2
44B1
43D6
40B2
40D5
44B1
43B4
44A4
40B2
7A7
40B2 56A8
40B2 40D5 56C1
37A8 39C5 40B2 41C5
37A8 39C5 40B2 41C3
7C3
64D8
42B5
402
1/16W
5%
MF-LF
10K
R4909
1
2
41C3
41C5
402
1/16W
5%
10K
MF-LF
R4901
1
2
402
10K
MF-LF
5% 1/16W
R4902
1
2
402
1/16W
5%
MF-LF
0
NO STUFF
R4903
1
2
402
1/16W
5%
MF-LF
10K
R4998
1
2
37A6
40B2 56C2
21C7 23B5
7B7
36B7
40A2
21C7 23C5
40B5
46B5
40D5
40D5
40D5
40B2
40B2
40B2
46C5
49B4
49B4
40D5
49B4
40D5
40C5
40D5
40B2 41C3
40B2
40B2 41D3
40B2 41C5
40B2 41D5
38B4 40C2 47A5
42C6
42C6
42D3
42D3
42C3
42C3
40C2
40C2
40C5
40C5
37A8 39B8 40B2 41C3
37A8 39B8 40B2 41C5
40B5
40B2
19B7 41D3
21A4 21B3 28A5 29A5
26B3
41C5
21C7 23C5
19B7 41D5
LGA-HF
OMIT
HS82117
U4900
B12
A13 A12
B13
D11 C13
C12
D10
D13
E11
D12 F11
E13
E12 F13
E10
A9
D9 C8
B7 A8
D8
D7 D6
D4
A5
B4 A1
C2 B2
C1
C3
G2 F3
E4
L13
K12 K11
J12
K13 J10
J11
H12
N10
M11
L10 N11
N12
M13 N13
L12
A7
B6 C7
D5 A6
B5
C6
J4 G3
H2
G1 H4
G4 F4
F1
OMIT
HS82117
LGA-HF
U4900
N3
N1
M3 M2
N2
L1 K3
L2
B8
C9 B9
A10 C10
B10
C11
G11
G13
F12 H13
G10 G12
H11
J13
M10
N9
K10
L8 M9
N8
K9 L7
K1
J3
K2 J1
K4
K5
N5 M6
L5
M5 N4
L4 M4
M8
N7
K8 K7
K6
N6 M7
L6
E2 F2
J2
A4 B3
C4
A11
HS82117
LGA-HF
OMIT
U4900
M12
L11
L9
H3
A2
D1 H1
E5
E3
D3
B1M1H10
E1
D2
L3
F10
B11
C5
A3
40D5
49B7
21C7 34B7 40B2
56B1
40D5
40A8
23B4
40D5
19B3 41D5 74C3
19B3 41D5 74C3
19B3 41D3 74C3
19B3 41D3 74C3
19C3 41D5 74C3
26D1
26C1 74C3
48A6
42D6
7C3
21C3 34B7 41A5 64D5 68D8
7C3
21C3 40A2 64C8
40A2
26B1 74A3
42D6
42B5
40D1
SYNC_DATE=06/26/2008
SYNC_MASTER=T18_MLB
051-7537
A
109
49
SMC
ALL_SYS_PWRGD
SMC_EXCARD_PWR_EN
RSMRST_PWRGD
SMC_PH2
LPC_PWRDWN_L
SMC_RX_L SMB_MGMT_CLK
SMC_ONOFF_L
PM_SLP_S5_L
SMC_BC_ACOK
PM_CLKRUN_L
SMC_GPU_VSENSE
SMC_GPU_ISENSE
SMC_DCIN_ISENSE SMC_PBUS_VSENSE SMC_BATT_ISENSE SMC_NB_MISC_ISENSE
SMC_WAKE_SCI_L
SMC_PROCHOT_3_3_L SMC_BIL_BUTTON_L
GND_SMC_AVSS
SMC_PA5
SMC_PA0
SYS_ONEWIRE PM_BATLOW_L
ALS_RIGHT
SMS_ONOFF_L
SMB_MGMT_DATA
PM_SLP_S4_L
SMB_0_S0_DATA
PP3V3_S5_AVREF_SMC =PP3V3_S5_SMC
SMC_RESET_L
SMC_NMI
SMC_VCL
SMC_KBC_MDE
SMC_MD1
SMC_TRST_L
PP3V3_S5_SMC_AVCC
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM
SMC_EXTAL
SMC_XTAL
SMC_PA1
PM_SYSRST_L
SMC_ODD_DETECT
SMC_FAN_0_CTL SMC_FAN_1_CTL SMC_FAN_2_CTL SMC_FAN_3_CTL SMC_FAN_0_TACH SMC_FAN_1_TACH SMC_FAN_2_TACH SMC_FAN_3_TACH
SMS_X_AXIS SMS_Y_AXIS SMS_Z_AXIS SMC_ANALOG_ID SMC_NB_CORE_ISENSE SMC_NB_DDR_ISENSE ALS_LEFT
SMC_TDI
SMB_A_S3_DATA
SMB_B_S0_DATA
LPC_CLK33M_SMC
SMC_SYS_KBDLED
SMC_TX_L SMC_RX_L SMB_0_S0_CLK
SMC_PM_G2_EN
SMC_CPU_VSENSE
SMC_BS_ALRT_L PM_SLP_S3_L
PM_CLK32K_SUSCLK
SMC_TMS
SMC_TCK
SMC_P26
SMC_TDO
LPC_AD<2>
LPC_AD<1>
SMC_GFX_THROTTLE_L
USB_DEBUGPRT_EN_L MEM_EVENT_L
SMB_B_S0_CLK
PM_RSMRST_L
PM_PWRBTN_L
LPC_AD<0>
LPC_AD<3>
SMC_ADAPTER_EN
SMC_CPU_ISENSE
SMC_EXCARD_CP
SMC_LID
ALS_GAIN
SMC_PROCHOT
SMB_A_S3_CLK
SMB_BSA_DATA
IMVP_VR_ON
SMC_TX_L
SMC_P24
ESTARLDO_EN
SMC_CASE_OPEN
LPC_FRAME_L SMC_LRESET_L
LPC_SERIRQ
SMC_SYS_LED
SMC_P41
SMC_THRMTRIP
SMB_BSA_CLK
=SMC_SMS_INT
SMC_MCP_SAFE_MODE
SMC_RSTGATE_L
SMC_GFX_OVERTEMP_L
SMC_EXCARD_OC_L
SMC_PB3
SMC_RUNTIME_SCI_L
44D5 44C5 44B5 44B2 44A4 44A1
49D7
43D6
40D8
43C6
40C7
43B5
40B6
40C1
40B2
40B6
40A2
40C2
7C3
8D1
40A6
40A6
40C2
40D5
40D5
40D5
40C5
Preliminary
D
S G
IN
OUT
BI
OUT
IN
D
S G
OUT
IN
OUT
IN
IN
D
SG
OUT
GND
OUT
IN
02
D
SG
OUT
CD
GND
NC
OUT
IN
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
System (Sleep) LED Circuit
SMC FSB to 3.3V Level Shifting
TO CPU
Debug Power "Button"
PLACE R5015,R5001 ON BOTTOM SIDE
PLACE R5016 ON TOP SIDE
TO SMC
SMC Crystal Circuit
SMC AVREF Supply
SMC Reset "Button" / Brownout Detect
NC
SSM6N15FEAPE
Q5059
SOT563
5
3
4
5%
402
1
0
MF-LF
1/16W
R5095
2
21
R5070
10K
1/16W5%MF-LF
402
21
R5071
100K
MF-LF
5%
1/16W
402
21
R5072
10K
5%
MF-LF1/16W
402
21
R5073
10K
402
1/16W5%MF-LF
21
R5074
100K
402
1/16W MF-LF
5%
21
R5075
ONEWIRE_PU
402
1/16W5%MF-LF
2.0K
21
R5076
402
100K
1/16W5%MF-LF
21
R5077
402
10K
1/16W5%MF-LF
2
R5078
402
MF-LF
5%
1/16W
10K
1
5%
1/16W MF-LF
402
1 2
R5079
10K
10K
5%
402
MF-LF1/16W
R5080
1 2
21
R5085
10K
5%
1/16W MF-LF
402
21
R5086
10K
1/16W MF-LF
402
5%
21
R5088
402
10K
1/16W5%MF-LF
21
R5090
1/16W MF-LF
402
100K
5%
39A5
10C6 14B7 71B3
SILK_PART=PWR_BTN
603
5%
MF-LF
0
1/10W
2
R5015
1
NOSTUFF
1
6
2
Q5060
BC847BV-X-F SOT563-HF
2
1
R5061
3.3K
402
5% 1/16W MF-LF
402
MF-LF
1
1/16W
3.3K
5%
R5062
2
2
1
R5060
5% 1/16W MF-LF 402
470
10C5 14B6 60C8 71B3
39C5
39A5
SSM6N15FEAPE
Q5059
SOT563
6
2
1
21
R5091
402
MF-LF
5%
1/16W
100K
21
R5092
402
1/16W5%MF-LF
100K
39B8 20C2
39B5 49C7
21
R5089
5%
10K
402
MF-LF1/16W
1
2
5X3.2-SM
20.00MHZ
Y5010
CRITICAL
C5011
15pF
21
CERM
5%
50V
402
21
402
50V
15pF
5%
C5010
CERM
4
3
5
Q5060
BC847BV-X-F SOT563-HF
21
R5087
470K
MF-LF
402
1/16W
5%
R5016
SILK_PART=PWR_BTN
2
1
1/10W
0
MF-LF
5%
603
NOSTUFF
39B5
6
2
1
SOT563
SSM6N15FEAPE
Q5032
1.47K
402
2
1
MF-LF
1/16W
1%
R5032
523
402
2
1
1/16W MF-LF
1%
R5031
20
R5030
MF-LF
1/16W
1%
402
2
1
10%
0.47UF
402
6.3V
2
1
C5020
CERM-X5R
38B4
Q5030
1
3
2
SOD
2SA2154MFV-YAE
SOT23-3
REF3333
21
3
VR5020
CRITICAL
6.3V X5R
10uF
20%
603
2
1
C5025
CERM
0.01UF
402
10% 16V
2
1
C5026
1/10W
5%
0
MF-LF 603
SILK_PART=SMC_RST
2
1
R5001
NOSTUFF
1
2
3
5
4
SOT553-5
SN74LVC1G02
U5001
1
0.01UF
402
CERM
16V
10%
2
C5001
10V
20%
CERM
402
0.1uF
2
1
C5000
3
Q5032
SOT563
SSM6N15FEAPE
4
5
1/16W
R5000
1
2
5%
MF-LF
1K
402
39C3 41C3
21
402
MF-LF1/16W
5%
10K
R5051
21
402
MF-LF1/16W
5%
10K
R5052
10K
5%
1/16W MF-LF
402
1 2
R5050
21
402
MF-LF1/16W
5%
10K
R5053
21
MF-LF
402
1/16W
5%
10K
R5055
10K
5%
402
MF-LF1/16W
1 2
R5054
SOT23-5-HF
2
4
5
3
1
CRITICAL
U5000
NCP303LSN
39C5 40C2 40C7 47C3
SYNC_DATE=05/28/2008
SYNC_MASTER=YUAN.MA
A
SMC Support
051-7537
50
109
353S1381 353S1278
ALL
Intersil ISL60002-33
=PP3V3_S5_SMC
SMC_RESET_L
SMC_MANUAL_RST_L
SMC_SYS_LED
MIN_LINE_WIDTH=0.4 mm
VOLTAGE=0V
GND_SMC_AVSS
MIN_NECK_WIDTH=0.2 mm
=PP3V3_S5_SMC
SMC_XTAL
SMS_INT_L
MAKE_BASE=TRUE
SMC_CASE_OPEN
=PP3V3_S0_SMC
SMC_ADAPTER_EN
SMC_EXCARD_CP
CPU_PROCHOT_BUF
SMC_PROCHOT_3_3_L
SMC_LID
SMC_ONOFF_L
SMC_PA0
=PP3V3_S0_SMC
SMC_PA1
SMC_TPAD_RST_L
SMC_ONOFF_L
SMC_EXTAL
=PPVIN_S5_SMCVREF
SYS_LED_ANODE
=SMC_SMS_INT
PM_SLP_S4_L
PM_SLP_S5_L
SMC_TMS
SYS_ONEWIRE SMC_BS_ALRT_L
SMC_ONOFF_L
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm
PP3V3_S5_AVREF_SMC
SMC_TPAD_RST
SMC_FAN_1_CTL
SMC_FAN_2_CTL
ALS_LEFT
SMC_NB_DDR_ISENSE
SMC_GPU_VSENSE
SMC_NB_CORE_ISENSE
SMC_P41
SMC_P26
MAKE_BASE=TRUE
SMC_BC_ACOK
SMC_GFX_THROTTLE_L
ESTARLDO_EN
ALS_GAIN
SMC_RSTGATE_L
SMC_EXCARD_PWR_EN
SMC_EXCARD_OC_L
NC_ALS_RIGHT
MAKE_BASE=TRUE
EXCARD_OC_L
PM_THRMTRIP_L
SMC_THRMTRIP
SMC_PROCHOT
MAKE_BASE=TRUE
SMC_MCP_DDR_ISENSE
MAKE_BASE=TRUE
SMC_MCP_VSENSE
TP_SMC_P41
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_BMON_MUX_SEL
MAKE_BASE=TRUE
TP_SMC_RSTGATE_L
MAKE_BASE=TRUE
TP_SMC_EXCARD_PWR_EN
CPU_PROCHOT_L
CPU_PROCHOT_L_R
=PP1V05_S0_SMC_LS
SMC_RX_L
SMC_PH2
SMC_GPU_ISENSE SMC_NB_MISC_ISENSE
SMC_FAN_3_TACH
SMC_TX_L
=PP3V3_S5_SMC
SMC_FAN_2_TACH
SMC_FAN_1_TACH
SMC_TDI
SMC_TDO
SMC_TCK SMC_BC_ACOK
SMC_GFX_OVERTEMP_L
MAKE_BASE=TRUE
NC_SMC_FAN_1_CTL
NC_SMC_FAN_2_CTL
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_SMC_P24
NC_ALS_GAIN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_SMC_ANALOG_ID
=PP5V_S3_SYSLED
SYS_LED_L_VDIV
SYS_LED_L
SYS_LED_ILIM
SMC_PA5
MAKE_BASE=TRUE
SMC_MCP_CORE_ISENSE
MAKE_BASE=TRUE
SMC_CPU_FSB_ISENSE
SMC_ANALOG_ID
ALS_RIGHT
=CHGR_ACOK
NC_ESTARLDO_EN
MAKE_BASE=TRUE
SMC_IG_THROTTLE_L
MAKE_BASE=TRUE
NC_SMC_FAN_3_CTL
MAKE_BASE=TRUE
SMC_PB3
NC_SMC_PB3
MAKE_BASE=TRUE
SMC_FAN_3_CTL
SMC_P24
44D5 44C5 44B5 44B2 44A4
49D7
44A1
49D7
49D7
40C7
43D6
40D8
47C3
64C8
47C3
41C3
41C5
40D8
40C1
43C6
40C1
39D5
47A5
40C7
39C5
56A8
40C2
56C1
39C5
39C5
40C7
56C1
39D4
43B5
39D4
40D2
34B7
39B5
40A3
40A1
21C3
41D5
56C2
39C5
40A3
39D4
40B2
39B8
39B8
39D4
41D3
41C5
41C3
40D5
21B3
8D1
39C2
8D1
39C3
39B5
8B5
21C7
39B8
38B4
39C5
39B8
8B5
39B8
47B1
39C3
8D1
7C3
39C5
39B5
39B8
7A7
39C5
7C3
39A8
39A8
39A8
39A8
39C5
39A8
39C8
39C8
39C5
39B8
39C8
39A5
39D8
39D8
44C5
43D6
44A5
8D7
37A8
39A5
39C5
39C5
39A8
37A8
8D1
39A8
39A8
39B5
39B5
39B5
39C5
39A8
8C3
39B8
44D5
44B5
39A8
39A8
57B5
21A4
39B8
39A8
39C8
Preliminary
BI
IN
BI
IN OUT OUT OUT
BI BI
IN
OUT
OUT
IN OUT OUT
IN OUT
IN
GS
D
OUT
D
SG
D
SG
OUT
OUT
OUT OUT
OUT
IN
IN
OUT
IN
OUT
IN
IN
OUT OUT
OUT OUT
VCC
GND
SEL OE*
D+ D-
Y+ Y-
M+ M-
BI
VCC
GND
SEL OE*
D+ D-
Y+ Y-
M+ M-
IN
OUT
IN
BI
IN
OUT
IN
OUT
IN
OUT
OUT
IN
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
MCP79 Internal SPI MUX Support
LPC+SPI Connector
NOT SUPPORTED IN REV A01 OR B01 MCP79 SILICON
Keep very short
ENSURES MCP79 SPI_DO OR SPI_CLK INPUT IS LOW WHEN STRAP IS LATCHED.NOT NEEDED FOR B01 OR LATER.
SPI Frequency Clamp
MCP SPI Override Options
MCP79 REV A01 REQUIRES EXTERNAL MUX, REV B01 STILL DOES NOT SUPPORT INTERNAL MUX
To Frank Card
From Frank Card
516S0573
Pull-up on debug card
not compatible with button-mashing.
SLP_S3# nVidia recommendation,
Alternate SPI ROM Support
SPI MUX BYPASS
SEL HIGH OUTPUTS TO D (ON BOARD ROM) SEL LOW OUTPUTS TO M (FRANKCARD ROM)
MUX SEL CONTROLLED BY FRANKCARD SWITCH ONCE CS1 IS SUPPORTED IN MCP
21C7
41B5
19B7 39C8
19C3 39C5
39B5 40B2
39B5 40B2
39C3 40D6
J5100
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
31
32
33
34
4
5
6
7
8
9
55909-0374
CRITICAL
LPCPLUS
M-ST-SM
19B3 39C8 74C3
19B3 39C8 74C3
41C5 74A3
19C5
41B5 74A3
19C3 39C8 74C3
19B7 39C5
39B5 40B2
39C1
R5141
1
2
MCP_CS1_YES
MF-LF
402
5%
1/16W
470
Q5140
3
1
2
MCP_CS1_YES
SOD-VESM-HF
SSM3J16FV
50C4 74A3
R5140
1
2
1/16W
5%
402
MF-LF
100K
R5142
1 2
MCP_CS1_NO
0
402
1/16W
5%
PLACEMENT_NOTE=Place near J5100
MF-LF
R5161
1 2
402
MF-LF
1/16W
5%
0
NO STUFF
R5162
1 2
1/16W MF-LF
5%
0
402
MCP_A01&MCP_A01Q
Q5160
6
2
1
MCP_A01&MCP_A01Q
SSM6N15FEAPE
SOT563
R5163
1
2
MCP_A01&MCP_A01Q
100K
5%
402
1/16W MF-LF
Q5160
3
5
4
SOT563
MCP_A01&MCP_A01Q
SSM6N15FEAPE
39C1
50C5 74A3
37A8 39B8 39C5 40B2
18B7
R5147
1 2
MCP_CS1_YES
PLACEMENT_NOTE=PLACE NEXT TO U5120
402
5%
0
MF-LF
1/16W
39C1
37A8 39B8 39C5 40B2
41D5 74A3
41D3
41A8 50C3
50C6
26B1 74C3
R5144
1
2
5%
MF-LF
1/16W
20K
402
MCP_CS1_NO
R5160
1 2
MCP_A01&MCP_A01Q
0
402
5% 1/16W MF-LF
7C3
21C3 34B7 39C5 64D5 68D8
41D3 74A3
41D5 74A3
41A8 50C6
41A8 50C3
C5114
1
2
0.1UF
CERM
20% 10V
402
LPCPLUS
U5110
6
7
3
4
5
8
10
9
2
1
CRITICAL
PI3USB102ZLE
LPCPLUS
TQFN
19B3 39C8 74C3
R5126
1 2
MCP_CS1_NO
0
5%
1/16W
MF-LF
402
R5127
1 2
MCP_CS1_NO
0
5%
MF-LF
1/16W
402
C5124
1
2
LPCPLUS
0.1UF
10V 402
CERM
20%
U5120
6
7
3
4
5
8
10
9
2
1
LPCPLUS
PI3USB102ZLE
CRITICAL
TQFN
R5190
1
2
MF-LF
5%
1/16W
10K
402
21B3 74A3
21B3 41A5 74A3
21B3 41C7 74A3
19B3 39C8 74C3
21B3 41C8 74A3
21B3 41B7 74A3
R5146
1 2
PLACEMENT_NOTE=PLACE NEXT TO U1400
5%
MF-LF
1/16W
0
402
MCP_CS1_YES&LPCPLUS_NOT
R5157
1 2
LPCPLUS_NOT
402
0
MF-LF
5%
1/16W
R5156
1 2
LPCPLUS_NOT
402
1/16W
5%
MF-LF
0
R5158
1 2
LPCPLUS_NOT
402
1/16W
5%
MF-LF
0
21B3 41A5 74A3
R5191
1
2
1/16W MF-LF
5%
10K
402
41C5 41C7
21B3 41A5 74A3
41C5 50C6
41C5 50C3
41B5 50C3
41C5 74A3
SYNC_MASTER=CHANGZHANG
SYNC_DATE=05/09/2008
051-7537
51
109
A
LPC+SPI Debug Connector
SPI_CLK_R
SPI_MOSI_R
=PP3V3_S5_ROM
SPI_MOSI_MUX
SPI_MISO_MUX
SPI_CLK_MUX
SPI_MISO
SPI_CLK_R
SPI_MOSI_R
SPI_CS0_R_L
SPIROM_USE_MLB
SPI_MISO
=PP3V3_S5_LPCPLUS
=PP3V3_S5_LPCPLUS
SPI_ALT_CS_L_MUX
SPI_MLB_CS_L_MUX
SPI_ALT_MISO
SPI_ALT_CLK SPI_ALT_MOSI
SPI_MOSI_MUX
SPI_CLK_MUX
SPI_MISO_MUX
SPI_MLB_CS_L
PM_SLP_S3_L
=PP3V3_S5_ROM
SPI_ALT_CS_L
SMC_MD1 SMC_TX_L
=PP5V_S0_LPCPLUS
LPCPLUS_GPIO
SMC_NMI SMC_RX_L
SPIROM_USE_MLB
MCP_SPI_FORCE_L
=PP3V3_S5_MCP_A01
MCP_SPI_FORCE
MCP_FORCE_SPI_DO_L
SPI_CLK
MAKE_BASE=TRUE
SPI_CS1_R_L_USE_MLB
=PP3V3_S5_LPCPLUS
=PP3V3_S0_LPCPLUS
LPC_FRAME_R_L
LPC_FRAME_PU
SMC_TMS DEBUG_RESET_L
SMC_TRST_L
SMC_TDO
LPC_AD<1>
LPC_AD<0>
SPI_ALT_MOSI
PM_CLKRUN_L
LPC_FRAME_L
SPI_ALT_MISO
=PP3V3_S5_LPCPLUS
SMC_RESET_L
LPC_AD<2>
LPC_CLK33M_LPCPLUS
LPC_AD<3>
SPIROM_USE_MLB SPI_ALT_CLK
SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK
SPI_MOSI
=SPI_CS1_R_L_USE_MLB
41D5
41D5
41D5
41C7
50C6
41C3
41C7
50C6
41C7
41C3
41B5
41D3
41B7
41C3
41C7
41D3
23C4
41B7
41B7
8A3
41C5
8D1
8D1
8A3
8D5
41C7
8A3
74A3
8D1
8C5
8D1
Preliminary
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
(MASTER)
(Write: 0x12 Read: 0x13)
Battery Charger
ISL6258A - U7000
SMC
MCP79
EMC1403-5: U5535
SMC
U4900
(MASTER)(MASTER)
J3100
SO-DIMM "A"
The bus formerly known as "Battery B"
U4900
SMC
(MASTER)
(Write: 0x90 Read: 0x91)
TRACKPAD
J5800
J3401
ALS
(Write: 0x52 Read: 0x53)
(Write: 0xA0 Read: 0xA1)
EMC1403-5: U5515
CPU Temp
(Write: 0x98 Read: 0x99)
SMC "B" SMBus Connections
Margin Control
(Write: 0x30 Read: 0x31)
(Write: 0x98 Read: 0x99)
(Write: 0x70 Read: 0x71)
U2900
Vref DACs
SMS
U5930
U2901
(MASTER)
SMC
(MASTER)
(See Table)
U4900
SMC
U4900
U4900
MCP Temp
Battery Manager - (Write: 0x16 Read: 0x17)
SMC "Battery A" SMBus Connections
Battery
BATTERY & BIL
J6950 & J6955
U1400
SMC "Management" SMBus Connections
SMC "A" SMBus Connections
NOTE: SMC RMT bus remains powered and may be active in S3 state
(Write: 0x98 Read: 0x99)
SMC "0" SMBus Connections
MCP79
U1400
Battery LED Driver - (Write: 0x36 Read: 0x37)
Battery Temp - (Write: 0x90 Read: 0x91)
Read: 0xA1-0xAF)
(WRITE: 0X72 READ: 0X73)
U6860
Mikey
U2690 OR U2695
(All 8 addresses used)
(Write: 0xA0-0xAE,
HDCP ROM
(MASTER?)
(Write: 0xA2 Read: 0xA3)
J3200
SO-DIMM "B"
MCP79 SMBUS "0" CONNECTIONS
MCP79 SMBUS "1" CONNECTIONS
5%
402
4.7K
R5200
1
2
1/16W MF-LF
R5201
MF-LF
5% 1/16W
402
4.7K
1
2
R5280
1K
1/16W MF-LF
5%
402
2
1
R5281
1K
MF-LF
5% 1/16W
402
2
1
2
1
R5261
4.7K
402
5% 1/16W MF-LF
2
1
R5260
4.7K
5%
MF-LF
1/16W
402
MF-LF
1K
R5271
1/16W
5%
402
2
1
MF-LF
1K
R5270
1/16W
5%
402
2
1
4.7K
MF-LF 402
1/16W
1
2
5%
R5251
1
4.7K
1/16W
5%
R5250
2
402
MF-LF
1
2
402
5%
2.0K
1/16W MF-LF
R5231
1
2
402
5%
2.0K
MF-LF
R5230
1/16W
2
1
R5290
1/16W
4.7K
402
5%
MF-LF
2
1
R5291
MF-LF 402
1/16W
5%
4.7K
1
NOSTUFF
1/16W
R5232
10K
MF-LF
5%
2
402
1/16W
10K
R5233
NOSTUFF
5%
1
2
402
MF-LF
M97 SMBUS CONNECTIONS
SYNC_DATE=04/21/2008
SYNC_MASTER=BEN
051-7537
109
52
A
SMBUS_MCP_1_CLK
MAKE_BASE=TRUE
=PP3V3_S0_SMBUS_MCP_1
MAKE_BASE=TRUE
SMBUS_MCP_1_DATA
=I2C_SODIMMB_SCL
=PP3V3_S5_SMBUS_MCP_1
=I2C_HDCPROM_SDA
=I2C_MIKEY_SDA
=I2C_MIKEY_SCL
=I2C_HDCPROM_SCL
=I2C_MCPTHMSNS_SCL
=I2C_MCPTHMSNS_SDA
MAKE_BASE=TRUE
SMBUS_MCP_0_DATA
SMBUS_MCP_0_CLK
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
=SMBUS_BATT_SDA
=PP3V42_G3H_SMBUS_SMC_BSA
=I2C_VREFDACS_SCL
SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMBUS_SMC_B_S0_SCL
SMB_A_S3_CLK
=PP3V3_S0_SMBUS_SMC_B_S0
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SCL
=PP3V3_S0_SMBUS_SMC_0_S0
=I2C_SODIMMB_SDA
SMB_BSA_CLK
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SCL
SMB_BSA_DATA
=SMBUS_BATT_SCL
=PP3V3_S0_SMBUS_MCP_0
SMB_0_S0_CLK
MAKE_BASE=TRUE
SMBUS_SMC_MGMT_SDA
=I2C_SMS_SDA
MAKE_BASE=TRUE
SMBUS_SMC_MGMT_SCL
=I2C_SMS_SCL
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA
=I2C_VREFDACS_SDA
SMB_B_S0_DATA
SMB_B_S0_CLK
=I2C_CPUTHMSNS_SDA
=I2C_CPUTHMSNS_SCL
=I2C_TPAD_SCL
=I2C_TPAD_SDA
I2C_ALS_SCL
I2C_ALS_SDA
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUE
SMB_MGMT_CLK
=PP3V3_S3_SMBUS_SMC_MGMT
=I2C_SODIMMA_SDA
SMB_A_S3_DATA
=I2C_SODIMMA_SCL
=PP3V3_S3_SMBUS_SMC_A_S3
=SMBUS_CHGR_SDA
=SMBUS_CHGR_SCL
SMB_0_S0_DATA
SMB_MGMT_DATA
74B3
74B3
76D3
76D3
74B3
74B3
21C3
21C3
56A6
76D3
56A6
7C5
7D5
21C3
8B5
21C3
29A5
8A3
25A6
52C7
52C7
25A6
45B3
45B3 13B6
13B6
76D3
56A3
8D1
27C7
76D3
76D3
39A5
8C5
76D3
76D3
8C5
29A5
39A5
7A7
39A5
56A3
8C5
39B8
76D3
49C6
76D3
49C6
27A8
27A8
27C7
39A5
39A5
45D3
45D3
48C1
48C1
31B6
31B6
7B5
7B5
39C5
8D3
28A5 39A5
28A5
8D3
57C6
57C6
39B5
39C8
Preliminary
OUT
D
N-CHANNEL
P-CHANNEL
G
G
S
S
D
IN
OUT
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
MCP Voltage Sense / Filter
CPU Voltage Sense / Filter
divider when high.
PBUS VOLTAGE SENSE ENABLE & FILTER
Place RC close to SMC
Place RC close to SMC
RTHEVENIN = 4573 OHMS
Place RC close to SMC
Enables PBUS VSense
40D4
1
2
20%
X5R
6.3V
C5359
0.22UF
402
2
402
R5359
MF-LF
1/16W
4.53K
1
1%
Q5315
NTUD3127CXXG
SOT-963
3
6
2
1
5
4
64C1
MF-LF
100K
402
1/16W
1%
2
1
R5316
R5315
1/16W
1%
402
2
1
100K
MF-LF
39C5
0.22UF
C5385
X5R
20%
6.3V
1
2
402
27.4K
1/16W
R5385
1
2
MF-LF
402
1%
2
R5386
1
5.49K
402
MF-LF
1/16W
1%
1 2
SM
PLACEMENT_NOTE=Place near U1400 center
XW5359
39C5
MF-LF
R5309
1 2
402
1%
1/16W
4.53K
X5R
C5309
1
2
6.3V
20%
0.22UF
402
1
SM
XW5309
PLACEMENT_NOTE=Place near U1000 center
2
051-7537
109
53
A
SYNC_DATE=02/04/2008
SYNC_MASTER=YUNWU
VOLTAGE SENSING
MIN_LINE_WIDTH=0.20 mm MIN_NECK_WIDTH=0.20 mm
PPBUS_G3HRS5_VSENSE
VOLTAGE=18.5V
=PBUSVSENS_EN
PBUSVSENS_EN_L
=PPVCORE_S0_MCP_VSENSE
GND_SMC_AVSS
SMC_PBUS_VSENSE
GND_SMC_AVSS
CPUVSENSE_IN
SMC_CPU_VSENSE
GND_SMC_AVSS
=PPVCORE_S0_CPU_VSENSE
PBUSVSENS_EN_L_DIV
=PPBUS_G3HRS5
MCPVSENSE_IN
SMC_MCP_VSENSE
44D5
44D5
44D5
44C5
44C5
44C5
44B5
44B5
44B5
44B2
44B2
44B2
44A4
44A4
44A4
44A1
44A1
44A1
43D6
43D6
43C6
43C6
43B5
43B5
40B6
40B6
40B6
8C7
39C2
39C2
39C2
8D7
8C1
Preliminary
V+
REFIN+
IN-
OUT
GND
OUT
OUT
IN
OUT
V+
REFIN+
IN-
OUT
GND
IN
OUT
V+
REFIN+
IN-
OUT
GND
OUT
IN
OUT
OUT
IN
V+
REFIN+
IN-
OUT
GND
IN
OUT
IN
OUT
VER 1
VCC
A
1
0
B1
GND
B0
SEL
IN
OUT
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
Place RC close to SMC
ACROSS R7008
CPU VCore Load Side Current Sense / Filter
BATTERY TO PBUS (BATTERY DISCHARGE)
PLACE U5413, R5423, R5431, C5459 NEAR SMC (U4900)
MCP MEM VDD Current Sense Filter
Place RC close to SMC
PLACE U5403 AND C5418 NEAR R7008
NOTE: MONITORING CURRENT FROM
LOAD SIDE
REGULATOR SIDE
INA213 has gain of 50V/V
BMON CURRENT SENSE
MCP VCore Current Sense
Place RC close to SMC
MCP VCore Current Sense Filter
Place RC close to SMC
PLACE R5491 AND C5390 CLOSE TO SMC
For production, stuff R5330 and unstuff U5313
For engineering, stuff U5313 and unstuff R5330
DC-IN (AMON) CURRENT SENSE
MCP MEM VDD Current Sense
CPU 1.05V AND CPU VCORE HIGH SIDE CURRENT SENSE
3
SC70
U5400
INA213
2
5
4
6
1
CERM
0.1uF
C5415
1
10V
2
20%
402
40D4
X5R
6.3V
0.22UF
C5472
402
20%
1
2
4
2
R5490
0.001
1% 1W MF
1206
1 3
8C8
22D5
24D8 61B1
8C8
C5416
1
10V CERM
0.1uF
20%
402
2
8B8
INA210
U5401
3
SC70
2
5
4
6
1
0.002
1206
1/4W
R5491
2
MF
1 3
1%
4
8B8
40D4
X5R
0.22UF
402
1
2
6.3V
20%
C5435
C5417
0.1uF
402
10V
20% CERM
2
1
3
U5402
SC70
INA213
5
4
6
1
2
8C2
R5492
1W
0.5%
0.01
4
21
3
0612
MF
8C1
40D4
1
C5436
2
6.3V X5R 402
0.22UF
20%
39C5
1
1/16W
402
2
MF-LF
1%
R5418
4.53K
R5416
402
MF-LF
1/16W
1%
2
4.53K
1
1/16W
402
1%
MF-LF
4.53K
21
R5417
0.1uF
C5418
ENG_BMON
402
20%
2
1
10V CERM
ENG_BMON
6
INA213
3
1
U5403
SC70
2
4
5
57B5
PROD_BMON
0
1/16W MF-LF
5%
402
R5431
5%
100K
R5423
402
MF-LF
2
1
ENG_BMON
1/16W
0.1uF
C5459
1
CERM
20% 10V
402
2
ENG_BMON
MF-LF
1%
1/16W
402
21
R5401
4.53K
X5R
20%
6.3V
402
1
2
0.22UF
C5490
39C5
0.22UF
6.3V
2
1
402
20%
X5R
C5470
60C7
R5480
17.4K
MF-LF
402
2
1
1%
1/16W
402
1/16W
6.19K
MF-LF
21
1%
R5471
39C5
4.53K
MF-LF
1/16W
R5481
402
21
1%
2
1
402
0.22UF
20%
6.3V X5R
C5487
U5413
ENG_BMON
NC7SB3157P6XG
2
3
1
4
6
5
SC70
40D4
57B3 77D3
57B3 77D3
SYNC_MASTER=YUNWU
051-7537
109
A
SYNC_DATE=04/07/2008
Current Sensing
54
=PPCPUVCORE_VTT_ISNS
=PPCPUVCORE_VTT_ISNS_R
ISNS_CPUVTT_P
ISNS_CPUVTT_N
=PP3V3_S0_CPUVTTISNS
IMVP6_IMON
CHGR_AMON
SMC_DCIN_ISENSE
SMC_BMON_MUX_SEL
GND_SMC_AVSS
CHGR_BMON
BMON_INA_OUT
SMC_BATT_ISENSE
GND_SMC_AVSS
CPUVTT_IOUT
SMC_MCP_DDR_ISENSE
GND_SMC_AVSS
GND_SMC_AVSS
SMC_MCP_CORE_ISENSE
SMC_CPU_ISENSE
MCPDDR_IOUT
SMC_CPU_FSB_ISENSE
MCPCORE_IOUT
GND_SMC_AVSS
CHGR_CSO_R_N
CHGR_CSO_R_P
BMON_AMUX_OUT
=PP3V42_G3H_BMON_ISNS
GND_SMC_AVSS
=PP1V5_S0_FET_R
ISNS_P1V5S0MCP_P
ISNS_P1V5S0MCP_N
=PP1V5_S0
=PP3V3_S0_MCPDDRISNS
=PPVCORE_S0_MCP_REG_R
ISNS_PVCORES0MCP_N
=PPVCORE_S0_MCP
ISNS_PVCORES0MCP_P
=PP5VR3V3_S0_MCPCOREISNS
44D5
44D5
44C5
44D5
44D5
44D5
44C5
44B5
44B5
44C5
44C5
44C5
44B2
44B2
44B2
44B5
44B5
44B5
44A4
44A4
44A4
44B2
44B2
44A4
44A1
44A1
44A1
44A1
44A4
44A1
43D6
43D6
43D6
43D6
43D6
43D6
43C6
43C6
43C6
43C6
43C6
43C6
43B5
43B5
43B5
43B5
43B5
43B5
40B6
40B6
40B6
40B6
40B6
40B6
77D3
77D3
77D3
8B5
39C2
39C2
39C2
39C2
39C2
8D1
39C2
77D3
77D3
8B5
61C4
77D3
8B5
Preliminary
ALERT*
SMCLK
SMDATA
GND
DN1
DP1
DN2
DP2
THERM*
VDD
BI
BI
BI
BI
ALERT*
SMCLK
SMDATA
GND
DN1
DP1
DN2
DP2
THERM*
VDD
BI
BI
BI
BI
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
PLACEMENT NOTE: PLACE U5515 NEAR CPU
CPU T-Diode Thermal Sensor
PLACEMENT NOTE: PLACE U5535 NEAR MCP
DETECT FIN-STACK TEMPERATURE
INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE
DETECT HEAT-PIPE TEMPERATURE
REPLACED 518S0521 WITH 518S0519
INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE
MCP T-Diode Thermal Sensor
DETECT CPU DIE TEMPERATURE
DETECT MCP DIE TEMPERATURE
C5540
SIGNAL_MODOL=EMPTY
50V
10%
0.0022uF
402
CERM
1
2
CRITICAL
TSSOP
EMC1403-1-AIZL
1
7
9
10
6
4
2
5
3
8
U5515
42C1
42C1
402
10K
MF-LF
5% 1/16W
2
1
R5517
402
1/16W
5%
MF-LF
10K
2
1
R5516
10K
MF-LF
5% 1/16W
402
2
1
R5537
MF-LF
1/16W
5%
10K
402
2
1
R5536
42D3
42D3
10V CERM 402
20%
2
1
C5535
0.1uF
CRITICAL
EMC1403-1-AIZL
TSSOP
1
7
9
10
6
4
2
5
3
8
U5535
402
1
2
CERM
0.0022uF
SIGNAL_MODOL=EMPTY
10% 50V
C5521
402
1
2
0.0022uF
50V
10%
CERM
C5522
SIGNAL_MODOL=EMPTY
10C6 77D3
10C6 77D3
21C3 77D3
21C3 77D3
CRITICAL
4
2
1
3
M-RT-SM
J5590
78171-0002
1
2
3
Q5501
BC846BMXXH
20%
402
CERM
10V
0.1uF
2
1
C5515
402
MF-LF
5%
1/16W
47
21
R5515
0.0022uF
10%
1
2
C5520
CERM
50V
402
SIGNAL_MODOL=EMPTY
21
5%
MF-LF
402
1/16W
R5535
47
051-7537
A
109
55
Thermal Sensors
SYNC_MASTER=YUNWU
SYNC_DATE=03/20/2008
CPUTHMSNS_D2_N
=PP3V3_S0_CPUTHMSNS
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm VOLTAGE=3.3V
PP3V3_S0_MCPTHMSNS_R
CPU_THERMD_N
CPUTHMSNS_D2_P
MCPTHMSNS_THERM_L
MCP_THMDIODE_P
MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V
MIN_LINE_WIDTH=0.25 mm
PP3V3_S0_CPUTHMSNS_R
=PP3V3_S0_MCPTHMSNS
MCP_THMDIODE_N
MCPTHMSNS_D2_P
MCPTHMSNS_D2_N
CPUTHMSNS_ALERT_L
CPUTHMSNS_THERM_L
=I2C_CPUTHMSNS_SCL
=I2C_MCPTHMSNS_SCL
=I2C_CPUTHMSNS_SDA
CPU_THERMD_P
=I2C_MCPTHMSNS_SDA
MCPTHMSNS_ALERT_L
77D3
77D3
77D3
8B5
77D3
8B5
7C7
7C7
Preliminary
D
GS
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
5V DC TACH
MOTOR CONTROL GND
518S0521
NC
NC
402
MF-LF
5%
1/16W
47K
21
R5665
47K
1/16W MF-LF
402
5%
2
1
R5660
100K
402
MF-LF
1/16W
5%
2
1
R5661
1
2
3
SOD-VESM-HF
Q5660
SSM3K15FV
J5601
M-RT-SM
78171-0004
CRITICAL
4
3
2
1
6
5
SYNC_DATE=01/18/2008
SYNC_MASTER=CHANGZHANG
Fan
A
56
109
051-7537
SMC_FAN_0_TACH
FAN_RT_TACH
SMC_FAN_0_CTL
=PP3V3_S0_FAN_RT
=PP5V_S0_FAN_RT
FAN_RT_PWM
39A8
7D7
39A8
8C5
8D5
7D7
Preliminary
D
G S
P2_4
P2_6
VDD
P0_4
P0_2
P2_0
P2_2
P0_0
P2_3 P2_1 P4_7 P4_5 P4_3 P4_1 P3_7 P3_5 P3_3 P3_1 P5_7 P5_5 P5_3 P5_1
P1_1
P1_3
P1_5
P1_7
P7_7
VSSD+D-
VDD
P7_0
P1_0
P1_2
P1_4
P1_6
P5_0
P5_2
P5_4
P5_6
P3_0
P3_2
P3_4
P4_0
P4_2
P4_4
P4_6
P3_6
P2_5
P2_7
P0_3
VSS
P0_5
P0_7
P0_6
PAD
THRML
(SYM-VER2)
P0_1
Y
C
B
A
IN
OUT
IN
Y
B
A
Y
B
A
Y
B
A
NC
NC
NC
NC
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
APN 518S0430
60MA MAX 60MA MAX
8MA (TYP)
14MA (MAX)
PSOC PROGRAMMING CONNECTOR
TEST POINTS ARE FOR ON BOARD PROGRAMMING
4MA (MAX)
3V3 LDO
VDD
16.32E-6 W
0.0255 V
36E-3 W
0.72E-3 W
0.012 V
0.6 V
0.204 V
SPI HOST TO Z2
4.7 OHM
TMP102
PLACE C5704, C5705 & C5706
VDD PIN 49
TPAD BUTTONS DISABLE
ISOLATION CIRCUIT
PLACE THESE COMPONENTS CLOSE TO J5800
U5701 CHIP DECOUPLING
THE TPAD BUTTONS WILL BE DISABLE
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
KEYBOARD CONNECTOR
WHEN THE LID IS CLOSED LID OPEN => SMC_LID_LC ~ 3.42V
LID CLOSE => SMC_LID_LC < 0.50V
APN 337S2983
APN 518S0637
TO MLB CONNECTOR
USB INTERFACES TO MLB
75.2E-6 W
294E-6 W
96E-6 W
0.255E-6 W
0.012 V
0.021 V
0.0188 V
POWERV_SNS
1.5 OHM
0.2 OHM
10 OHM
2.55 KOHM
R_SNS
10UA 80UA
CURRENT
VIN
VOUT
V+
PIN NAME
IC
PSOC
18V BOOSTER
ISSP CLOCK
ISSP DATA
PLACE C5701, C5702 & C5703
ISSP SCLK/I2C SCL
CLOSE TO U5701
VDD PIN 22
CLOSE TO U5701
SMC_MANUAL_RESET LOGIC
VDD
APN 311S0406
PSOC USB CONTROLLER
ISSP SDATA/I2C SDA
KEYBOARD SCANNER
TRACKPAD PICK BUTTONS
Q5701
SOD-VESM-HF
3
SSM3K15FV
1
2
16V
2
402
10%
0.1UF
C5758
1
X7R-CERM
R5771
5%
33K
MF-LF
1/16W
402
2
1
R5770
33K
1/16W
5%
MF-LF 402
2
1
R5769
33K
5%
1/16W MF-LF 402
2
1
603
X5R
6.3V
20%
4.7UF
C5706
1
2
1
C5705
10% 16V X7R-CERM
0.1UF
402
2
1
402
CERM
50V
100PF
C5704
5%
2
16V X7R-CERM 402
10%
0.1UF
C5703
1
2
C5702
100PF
5% 50V CERM 402
2
1
C5701
6.3V
603
X5R
4.7UF
1
2
20%
MF-LF
1/16W
5%
402
21
R5702
24
12
19
54
38
MLF
CY8C24794
U5701
20
21
4546475248
51
25182617271628
15
41
42
1
43
44
33
34
35
8
36
37
6
5
39
4
40
2914
3013
31
32
24
235722 49
7
3
53
55
56
2
50
OMIT
CRITICAL
11
10
9
402
1
R5701
MF-LF
2
5%
1/16W
24
6
3
1
2
5
4
SC70
SN74LVC1G10
U5703
CRITICAL
1 2
402
1/16W
1.5
R5704
5%
MF-LF
38B4 39B5 40C2
CERM
PLACEMENT_NOTE=NEAR J5713
20%
0.1UF
10V
402
C5710
1
2
21
R5710
1K
5% 1/16W MF-LF
402
470
1/16W
402
MF-LF
1%
R5714
1 2
1/16W MF-LF
10K
402
1%
R5715
1 2
F-RT-SM1
FH19C-4S-0.5SH25
J5702
5
6
1 2 3 4
CRITICAL
TPAD_DEBUG
8C3
47A6 47B5 47C5
32
31
F-RT-SM
FF14-30A-R11B-B-3H
CRITICAL
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
4
5
6
7
8
9
J5713
3
2
SOT665
4
5
U5726
1
TC7SZ08AFEAPE
CRITICAL
3
5
1
4
2
SOT665
U5727
TC7SZ08AFEAPE
CRITICAL
C5727
0.1UF
20% 10V
CERM
402
2 1
10V
CERM
20%
C5726
0.1UF
402
2 1
3
5
1
4
2
U5725
TC7SZ08AFEAPE
SOT665
CRITICAL
0.1UF
CERM
20%
C5725
10V
402
2 1
WELLSPRING 1
A
SYNC_DATE=04/22/2008
SYNC_MASTER=YUAN.MA
051-7537
109
57
ISSP_SDATA_P1_0
ISSP_SCLK_P1_1
ISSP_SDATA_P1_0
ISSP_SCLK_P1_1
TP_P7_7
Z2_CLKIN
USB_TPAD_R_N
DIFFERENTIAL_PAIR=USB2_TPAD
PP3V3_S3_PSOC
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
USB_TPAD_N
=PP3V3_S3_TPAD
WS_LEFT_OPTION_KBD
=PP3V3_S3_TPAD
=PP3V42_G3H_TPAD
WS_CONTROL_KEY
TP_P4_5 Z2_DEBUG3
PSOC_MISO
PSOC_SCLK
Z2_CS_L
WS_KBD_ONOFF_L
SMC_ONOFF_L
WS_KBD1
WS_CONTROL_KBD
PICKB_L BUTTON_DISABLE Z2_HOST_INTN
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
PP3V3_S3_PSOC
WS_KBD20
WS_LEFT_OPTION_KEY
=PP3V42_G3H_TPAD
=PP3V42_G3H_TPAD
DIFFERENTIAL_PAIR=USB2_TPAD
USB_TPAD_R_P
Z2_BOOT_CFG1
Z2_RESET
Z2_MISO
SMC_TPAD_RST_L
WS_KBD18
WS_KBD15_C
WS_KBD16N
WS_KBD7
Z2_KEY_ACT_L
WS_KBD19
WS_KBD21
WS_KBD23
Z2_MOSI
WS_KBD13
TP_PSOC_P1_3
WS_KBD4
WS_KBD3
WS_KBD9
WS_KBD10
WS_KBD12
WS_KBD14
WS_KBD15_C
=PP3V3_S3_TPAD
WS_KBD5
USB_TPAD_P
WS_KBD22
WS_KBD11
TP_PSOC_SCL
PP3V3_S3_PSOC
TP_PSOC_SDA
Z2_SCLK
WS_KBD8
WS_KBD7
WS_CONTROL_KBD
WS_LEFT_OPTION_KBD
=PP3V42_G3H_TPAD
WS_LEFT_SHIFT_KBD
WS_KBD23
WS_KBD22
WS_KBD19 WS_KBD20 WS_KBD21
WS_KBD9 WS_KBD10
WS_KBD12
WS_KBD11
WS_KBD13
WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM
WS_KBD17
WS_KBD18
WS_KBD6
WS_KBD5
WS_KBD2
WS_KBD1
WS_KBD8
WS_LEFT_SHIFT_KBD
WS_LEFT_SHIFT_KEY
WS_KBD16N
WS_KBD17
BUTTON_DISABLE
SMC_LID
WS_KBD6
WS_CONTROL_KBD
=PP3V3_S3_TPAD
PSOC_MOSI
PSOC_F_CS_L
=PP3V42_G3H_TPAD
WS_CONTROL_KEY
WS_LEFT_SHIFT_KEY
WS_LEFT_OPTION_KEY
WS_KBD4
WS_KBD3
WS_KBD2
=PP3V3_S3_TPAD
=PP3V3_S3_TPAD
47D2
47D2
47C5
47C5
47D2
47C5
47C5
47C2
40C7
47C5
47C2
47D2
47C5
47C5
47C2
47D2
47B5
47C2
47B5
47B5
40C2
47C2
47C2
47C2
47C2
47B5
47C5
47B5
47B5
47B5
47B5
47C2
47C2
47B5
47B5
47B5
48C3
47D7
74B3
47A6
47B3
47A6
47B3
48C3
48C1
48C1
48C3
40A3
47C6
47B5
48C1
48C3
47B3
47B5
47B6
47B5
47B3
48C3
48C1
48C3 47D2
48C1
48C3
47C2
47D2
47D2
47D2
47D2
47C2
47C2
47B5
47D2
74B3
47C2
47D7
48C3
47C6
47C6
47B3
47B3
47B3
47B3
47D7
47D7
47D7
47D7
47D7
47C6
47C6
47C6
47C6
47C6
47C6
47C6
47D7
47C6
47C6
47D2
47D2
47D2
47B5
47C2
47D2
47B3
47A6
48C1
48C1
47B3
47C6
47C6
47C6
47A6
47C6
47B8
47C6
47C6
7B5
74B3
47B6
20D3
8C3
7A5
8C3
8D1
47B4
7C5
7B5
7B5
7C5
7A5
39C5
7B5
7A5
7B5
47A5
7B5
7A5
7A5
47A8
47B4
8D1
8D1
74B3
7B5
7B5
7C5
40C7
47C6
47C6
7B5
7B5
7C5
7A5
7B5
7B5
7A5
7A5
7A5
7A5
47C3
8C3
7B5
20D3
7A5
47A8
7C5
7A5
7B5
7A5
7A5
8D1
7A5
7A5
7A5
7A5
7A5
7A5
7A5
7A5
7A5
7A5
7A5
7A5
7A5
7A5
7A5
7A5
7B5
7B5
7B5
7B5
7A5
7A5
47B4
47C3
7A5
47D8
7B5
7A5
8C3
7B5
7B5
8D1
47C8
47D8
47D8
7B5
7B5
7B5
8C3
Preliminary
SYM_VER-1
CTRL
PGND
THRML
L
VIN
DO
FB
SW
PAD
GND
VDD
VOUT
GND
CE
IN
THRML
CAP
SW
LED
VIN
CTRL
PAD
GND
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
KEYBOARD BACKLIGHT DRIVNG AND DETECTION
APN 371S0313
BOOSTER +18.5VDC FOR SENSORS
- RIPPLE TO MEET ERS
- 100-300 KHZ CLEAN SPECTRUM
- STARTUP TIME LESS THAN 2MS
- R5812,R5813,C5818 MODIFIED
BOOSTER DESIGN CONSIDERATION:
APN 353S1364
To detect Keyboard backlight, SMC will
R5853 ALWAYS PRESENT
tristate SMC_SYS_KBDLED:
LOW = keyboard backlight present
HIGH= keyboard backlight not present
BOM OPTION: KBDLED_YES TURNED ON FOR BEST MLB CONFIG
APN 516S0689
IPD FLEX CONNECTOR
- DROOP LINE REGULATION
- POWER CONSUMPTION
APN 353S1401
on keyboard backlight flex
3V3 LDO FOR IPD
APN 152S0504
KBD BACKLIGHT CONNECTOR
J5815 pin 1 is grounded
APN 518S0691
PLACEMENT_NOTE=NEAR J5800
2
1
C5800
CERM 402
10V
20%
0.1UF
NO STUFF
CRITICAL
L5800
0.01H-0.3A-80V SM-HF
4
32
1
PLACEMENT_NOTE=NEAR J5800
9
8 7
6 5
4 3
22 21
20
2
19
18 17
16 15
14 13
12 11
10
1
J5800
55560-0227
M-ST-SM
CRITICAL
B0520WSXG
SOD-323
D5802
2
1
C5819
1UF
X5R
25V
10%
603-1
1/16W MF-LF
R5806
0
5%
402
21
2
1
C5816
0.1UF
16V X7R-CERM
10%
402
402
MF-LF21/16W
5%
R5805
0
1
C5817
2
1
2.2UF
10%
603
X5R
16V
2
9
8
716
4
3 5
U5805
TPS61045
QFN
CRITICAL
CRITICAL
L5801
3.3UH-870MA
VLF3010AT-SM-HF
2
1
R5811
100K
MF-LF
1% 1/16W
402
16V
603
10%
2.2UF
C5853
1
X5R
2
CRITICAL
MLF
MM3243DRRE
VR5802
1
4
2
3
R5836
1%
1/6W
MF
402-HF
0.2
1
2
0.1UF
X7R-CERM 402
16V
10%
C5838
1
2
20%
6.3V X5R 603
4.7UF
C5854
1
2
1%
21
402
MF-LF
1/16W
10
R5873
39B8
MF-LF
R5854
1/16W
5%
4.7K
402
2
1
R5853
5% 1/16W MF-LF
470K
402
2
1
1
6
2
7
4
5
3
U5850
CRITICAL
DFN
LT3491
NO STUFF
1/16W
R5852
10K
2
402
MF-LF
5%
1
402-1
X5R
10V
10%
1UF
C5850
1
2
R5855
1
402
MF-LF
1/16W
1%
10
2
L5850
CRITICAL
10UH-0.58A-0.35OHM
21
1098AS-SM
1UF
X5R 603
35V
10%
C5855
1
2
J5815
CRITICAL
FF18-4A-R11AD-B-3H
1
4
3
2
F-RT-SM
2
1
402
39PF
C5818
CERM
50V
5%
1
2
402
1%
1M
R5812
1/16W MF-LF
1
2
402
71.5K
R5813
1%
MF-LF
1/16W
603
5%
21
1/10W
0
R5800
MF-LF
R5801
0
603
MF-LF
5%
1/10W
1 2
WELLSPRING 2
SYNC_MASTER=YUAN.MA
109
58
051-7537
A
SYNC_DATE=05/09/2008
PP5V_S3_TPAD_F
PP5V_S3_VR
0.20MM
INPUT_SW
0.50MM
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
PP5V_S3_BOOSTER
TPAD_GND_F
PP18V5_S3_SW
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
BOOST_SW
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM SWITCH_NODE=TRUE
BOOST_FB
SMC_SYS_KBDLED
SMC_KDBLED_PRESENT_L
=PP5V_S3_TPAD
TPAD_GND_F
TPAD_GND_F
VOLTAGE=0V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
VOLTAGE=3V3
MIN_NECK_WIDTH=0.20MM
PP5V_S3_TPAD_F
MIN_LINE_WIDTH=0.50MM
KBDLED_ANODE
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM
=PP3V3_S0_TPAD
MIN_NECK_WIDTH=0.25 MM SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.3 MM
KBDLED_SW
PP3V3_S3_LDO_R
PP3V3_S3_LDO
SMC_KDBLED_PRESENT_L
KBDLED_CAP
MIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.25 MM
Z2_BOOST_EN
Z2_SCLK
Z2_RESET
PP5V_S3_TPAD_F
PP3V3_S3_LDO
0.20MM
0.50MM
Z2_CLKIN
Z2_BOOT_CFG1
Z2_HOST_INTN
Z2_BOOST_EN
Z2_MISO
Z2_MOSI
Z2_CS_L
PICKB_L
PP18V5_S3
Z2_DEBUG3
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
=I2C_TPAD_SCL
0.20MM
0.50MM
PP18V5_S3
=I2C_TPAD_SDA
PSOC_F_CS_L
Z2_KEY_ACT_L
TPAD_GND_F
0.20MM
0.50MM
=PP5V_S0_KBDLED
48C7
48C4
48C7
48C3
48C3
48C3
48B4
48C1
48D3
48C4
48D6
48B4
48B4
48D6
7C5
48C3
47C8
47C8
48C7
7C5
47B6
47C8
47D8
48C5
47C8
47C8
47C8
47D8
7C5
47C8
47C8
47C8
47C8
7C5
47C8
47C8
48B4
48C7
7C5
48A6
8C3
7C5
48B6
7A5
8B5
7C3
48A4
7C5
7C5
7B5
48B6
7C3
7B5
7B5
7B5
7C5
7C5
7C5
7C5
7B5
7C3
7C5
7B5
7B5
7B5
42D1
7C3
42D1
7B5
7B5
7C5
8D5
Preliminary
OUT
OUT
OUT
OUT
VDDIO
SDI
SDO
VDD
GND
INT
SCK
RESERVED
CSB
NC
FS PD ST
RES RES
GND
NC
NC NC
NC
NC NC
VOUTX
VOUTY
VOUTZ
VDD
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC
Stuff R5931 AND NoStuff R5932 to use U5930
NC
Pull-up required if SMS_INT_L not used.
NC
NC NC
Circle indicates pin 1 location when placed
Front of system
Desired orientation when placed on board top-side:
Digital SMS
+X
+Y
+Z (up)
in correct orientation
Front of system
+X
+Y
+Z (up)
NC
NC
NC
NC NC NC
NC
NoStuff R5931 AND Stuff R5932 if U5930 is not used
in correct orientation
Circle indicates pin 1 location when placed
placed on board top-side:
Analog SMS
Desired orientation when
1/16W
ENG_DIGSMS
R5931
5%
2
1
10K
402
MF-LF
16V
10%
2
CERM
0.01UF
1
402
C5923
39A8
39A8
39A8
C5922
402
X5R
16V
10%
0.1UF
2
1
603
2
1
20%
10UF
4V
C5926
X5R
40B4
ENG_DIGSMS
CRITICAL
LGA
9
8
7
11
2
1
3
4
6
10
5
12
273141043
U5930
ENG_DIGSMS
0.022UF
16V CERM-X5R
10%
C5931
1
402
2
ENG_DIGSMS
0.1UF
402
X5R
16V
10%
C5932
1
2
15
14
1 5 2
4
7
9
3 6
16
11 13
12
10
LGA
U5920
AP344ALH
8
CRITICAL
C5925
0.01UF
1
402
16V
10%
2
CERM
C5924
1
0.01UF
10% CERM
2
16V 402
39C8
402
R5922
10K
1/16W
5%
1
2
MF-LF
1
10K
5%
2
1/16W MF-LF
402
R5921
402
5%
10K
1
R5932
PROD_DIGSMS
2
MF-LF
1/16W
SYNC_DATE=06/26/2008
SYNC_MASTER=YUNWU
SMS
109
051-7537
59
A
MAKE_BASE=TRUE
SMS_PWRDN
SMS_SELFTEST
SMS_ONOFF_L
SMS_INT_L
=I2C_SMS_SDA
SMS_Y_AXIS
SMS_X_AXIS
=PP3V3_S5_SMC
=PP3V3_S3_SMS
=I2C_SMS_SCL
SMS_Z_AXIS
=PP3V3_S3_SMS
40D8 40C7 40C1 39D4
49B7
49D6
42A3
8D1
8C3
42A3
8C3
Preliminary
ININ
IN
GND
VCC
WP*/ACC
CE*
SI/SIO0
HOLD*
SCLK
SO/SIO1
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
1
0
1
SPI_CLK
0
SPI_MOSI
1
0
1
0
42 MHz
1 MHz
25 MHz
Frequency
MCP79 SPI Frequency Select
31 MHz
41A8 41C5
R6100
1
2
5%
3.3K
1/16W MF-LF
402
R6190
1
2
MF-LF
5%
1/16W
10K
402
NO STUFF
R6150
1 2
402
0
1/16W
5%
MF-LF
PLACEMENT_NOTE=PLACE CLOSE TO U6100
41A8 41C5
41B5
U6100
1
4
7
6
5
2
8
3
32MBIT
MX25L3205DM2I-12G
CRITICAL
OMIT
SOP
41A8 41B5
R6152
1 2
402
0
1/16W
5%
MF-LF
PLACEMENT_NOTE=PLACE CLOSE TO U6100
R6105
1 2
402
0
1/16W
5%
MF-LF
PLACEMENT_NOTE=PLACE CLOSE TO U6100
R6191
1
2
10K
1/16W
5% MF-LF
402
NO STUFF
C6100
1
2
20%
402
CERM
10V
0.1UF
R6101
1
2
402
MF-LF
3.3K
5% 1/16W
SYNC_DATE=05/02/2008
SYNC_MASTER=CHANGZHANG
SPI ROM
051-7537
A
109
61
SPI_MISO_MUX
SPI_MOSI_MUX
SPI_CLK_MUX
SPI_MISO_R
SPI_CLK
SPI_HOLD_L
SPI_MOSI
SPI_MLB_CS_L
SPI_WP_L
=PP3V3_S5_ROM
with R6190, R6191, R5190 and R5191
Any of the 4 frequencies can be selected
25MHz is selected with R5190 and R5191
41C7
74A3 74A3
41B5
74A3
41A1 41B1
8A3
Preliminary
IN
IN IN
IN
OUT
PORT-B-VREFO2
PORT-A-VREFO/DCVOL
PORT-E-L
THRM_PAD
AVSS1
SYNC
CD-R
PORT-F-VREFO
PORT-E-VREFO PORT-B-VREFO
PORT-C-VREFO
PORT-B-R
PORT-B-L
PORT-E-R
PORT-H-R
PORT-H-L
PORT-G-R
PORT-G-L
JDREF
VREF
PORT-D-R
PORT-D-L
PORT-C-R
PORT-C-L
SPDIFO
PORT-F-R
PORT-F-L
DVSS
CD-GND
BEEP
AVSS2
AVDD2
AVDD1
SDATA_IN
CD-L
SENSE_A SENSE_B
GPIO1/DMIC-L
BCLK
DVDD
NC
SPDIFI/EAPD/MIDI-I/DMIC-R
PORT-A-L PORT-A-R
RESET*
GPIO0/DMIC-CLK
SDATA_OUT
DVDD_IO
REV B3
OUTS
OUT
SELB
SELA
BP
IN
GNDENPAD
THRML
IN IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
IN
IN IN
OUT
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
APPLE P/N 353S1538
AUDIO CODEC
AUDIO 4.6V REGULATOR
APPLE P/N 353S1897
PLACE XW6200 AND XW6201 NEAR U6201
STAR GND PT. FOR AUDIO SYSTEM
PORT C RT=SUB. SPKR SIGNAL SOURCE
ALIAS OF PP3V3_SO, MIN_LINE_WIDTH=0.6MM, MIN_NECK_WIDTH=0.2MM
PORT D=HP SIGNAL SOURCE
PORT B=L AND R SPKR AMP. SIGNAL SOURCE
PORT A = LINE INPUT
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
HP AMP. SHDN CONTROL
PORT F VREF=MIC BIAS
PORT F= MIC INPUT
PORT E = MIKEY MIC INPUT
SPKR. AMP. SHDN CONTROL
C6208
402
0.1UF
X5R
16V
10%
2
1
CRITICAL
1
0.001UF
C6212
CERM
10%
402
2
50V
FERR-220-OHM
1
0402
2
L6201
CRITICAL
R6205
1
MF-LF 402
1/16W
20.0K
1%
2
CERM
6.3V
10%
1
1UF
2
C6200
CRITICAL
402
CRITICAL
FERR-220-OHM
1
0402
L6200
2
1
20%
C6221
10UF
X5R
CRITICAL
2
603
6.3V
R6202
1K
21
402
1/16W MF-LF
5%
1
X5R
2
C6220
16V 402
10%
0.1UF
CRITICAL
L6202
1 2
0402
FERR-220-OHM
R6209
2
402
5% 1/16W MF-LF
100K
1
CRITICAL
28
35
17 30
20
ALC885Q-VB3-GR
43
23
3
13
10
6
40
44
12
QFN
27
49
48
34
8
11
45
16
31
14
29
24
21
33
41
37
2
4
9
19
42
38
5
47
36
39
U6200
1
22
26
15
46
7
32
18
25
R6270
100K
5% 1/16W
402
MF-LF
1
2
7
U6201
4
6
8
1
2
3
5
9
MAX8902A
TDFN
CRITICAL
0.01UF
10%
603-1
X7R
2
1
50V
C6224
C6222
603
X5R
6.3V
20%
2
1
10UF
CRITICAL
2
1
25V X7R 402
10%
0.01UF
C6201
SM
XW6200
21
10%
C6207
2
1
402
X7R
25V
0.01UF
1
402
0.01UF
C6206
X7R
25V
2
10%
2
1
402
X7R
10% 25V
0.01UF
C6225
402
X7R
25V
10%
C6223
0.01UF
1 2
402
22
MF-LF
1/16W
5%
R6206
CRITICAL
1
2
TANT
20%
C6204
6.3V
100UF
1
2
C6205
CRITICAL
100UF
20%
6.3V TANT CASE-AL1
1 2
SM
XW6201
R6204
402
MF-LF
12
5%
22
1/16W
1
2
SMA-HF
C6210
CRITICAL
3.3UF
10% 16V TANT
5%
10K
1/16W 402
2
1
R6210
MF-LF
X7R
C6203
0.01UF
25V
10%
402
1
2
R6203
100K
5% 1/16W MF-LF
2
1
402
0
1
NO STUFF
2
402
MF-LF
1/16W
5%
R6201
SYNC_MASTER=AUDIO
AUDIO: CODEC
62
A
109
051-7537
SYNC_DATE=07/01/2008
AUD_GPIO_0
MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V
MIN_LINE_WIDTH=0.30 MM
GND_AUDIO_CODEC
HDA_SYNC HDA_SDOUT
CODEC_DVDD
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM
AUD_SENSE_A AUD_SENSE_B
AUD_BI_PORT_A_R AUD_BI_PORT_F_L
AUD_BI_PORT_F_R AUD_VREF_PORT_F
AUD_BI_PORT_E_L
AUD_BI_PORT_B_R
NC_AUD_VREF_PORT_D
NO_TEST
NO_TEST
NC_AUD_BI_PORT_G_L
MIN_NECK_WIDTH=0.20MM VOLTAGE=4.6V
PP4V6_AUDIO_ANALOG
MIN_LINE_WIDTH=0.30MM
AUD_SPDIF_I
NO_TEST
NC_AUD_VREF_PORT_E
AUD_BI_PORT_A_L
AUD_VREF_PORT_B
NO_TEST
NC_AUD_VREF_PORT_A
AUD_SPDIF_OUT
AUD_BI_PORT_B_L
AUD_CODEC_VREF
NO_TEST
NC_AUD_BI_PORT_G_R
NC_AUD_VREF_PORT_C
NO_TEST
CODEC_SDATA_IN
HDA_BIT_CLK
HDA_RST_L
BEEP
GND_AUDIO_CODEC
HDA_SDIN0
NO_TEST
NC_AUD_BI_PORT_H_R
AUD_BI_PORT_C_R
AUD_SPDIF_O
NO_TEST
NC_BAL_IN_L
NC_AUD_BI_PORT_H_L
NO_TEST
NO_TEST
NC_AUD_BI_PORT_C_L
AUD_BI_PORT_D_L AUD_BI_PORT_D_R
NO_TEST
NC_BAL_IN_R
AUD_GPIO_1
=PP3V3_S0_AUDIO
VOLTAGE=3.3V
NO_TEST
NC_BAL_IN_COM
=PP5V_S3_AUDIO
VOLTAGE=5V
PP4V6_ENABLE
AVDD_ADC_DAC
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.30MM PP5V_S3_AUDIO_F
GND_AUDIO_CODEC
PP4V6_AUDIO_ANALOG
=PP3V3_S0_AUDIO
MAX8902_BP
NO_TEST
NC_VRP
AUD_CODEC_JDREF
GND_SPKR_AMP
55C4
55C4
55C4
55B8
55B8
55B8
55B5
55B5
55B5
55B4
55B4
55B4
55A8
55A8
55A8
55A4
55A4
55A4
55A2
55A2
55A2
54B3
54B3
54B3
53C8
53C8
53C8
53B8
53B8
53B8
53A8
53A8
53A8
52C6
52C6
55B5
52C6
55B5
52C3
52C3
54D8
52C3
54D8
52B6
52D6
53C8
52B6
52D6
52B6
52D6
52D6
53C4
51D3
74A3
74A3
55C8
51A3
53B8
74B3
74A3
51B7
74A3
51A7
55D4
51D3
51D3
51D8
53B3
55D3
51A7
21C2
21D2
55A8
55C8
55A1
55A4
55A4
55B4
52C6
53C8
7C3
54B3
55B1
53A8
54D3
53A8
21D2
21D2
51A7
21D7
53B8
55C4
55B4
8C5
8C3
51B7
7C3
8C5
53A4
Preliminary
IN
OUT
IN
IN
OUT
BI
IN
GND THM
ENABLE
AVDD
SDA
MICBIAS
DETECT
BYPASS
INT*
SCL
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
TABLE_5_ITEM
PLACE R6301, R6305, R6306, R6307, AND R6308 OUTSIDE AUDIO SECTION TO CONSERVE AUDIO AREA
MIKEY RECEIVER CKT
47K PULL-UP ON MCP PAGE (R2142)
R6301
100K
5%
1/16W
MF-LF
402
MIKEY
402
2.2K
5% 1/16W MF-LF
MIKEY
R6303
10K
R6302
1% MF-LF
402
1/16W
MIKEY
SM
XW6300
54D3 51C3
54D3
402
5%
0
MF-LF
R6306
MIKEY
1/16W
19D7
21A4 21C3
42B6
42B6
402
MF-LF
1/16W
0
5%
MIKEY
R6308
0
5%
1/16W
MIKEY
MF-LF
402
R6307
MIKEY
C6300
2.2UF
16V X5R 603
CRITICAL
10%
0402
FERR-1000-OHM
L6300
NO STUFF
MIKEY
402
MF-LF
R6305
5%
1/16W
0
5%
0
MF-LF
402
1/16W
NOSTUFF
R6300
U6300
CRITICAL
CD3275
8
MIKEY
9
11
4
3
5
1
2
7
6
DRC
10
MIKEY
L6301
FERR-1000-OHM
0402
C6302
402
25V X7R
10%
MIKEY
0.01UF
CRITICAL
MIKEY
402
2.2UF
C6301
TANT
6.3V
20%
10%
402
CERM
50V
OMIT
0.001UF
C6304
C6303
MIKEY
402
10% 16V
0.1UF
5% 1/16W
402
OMIT
100K
R6304
MF-LF
?
MIKEYC6304
1
100PF 50V 10% 0402 CAPACITOR
MIKEYR6304
1
100K 5% 0402 RESISTOR
?
?
NOMIKEY
R6304
1
0 OHMS 5% 0402 RESISTOR
AUDI0: MIKEY
SYNC_MASTER=AUDIO
SYNC_DATE=07/03/2008
051-7537
A
109
63
?
NOMIKEY
C6304
1
0 OHMS 5% 0402 RESISTOR
PP4V6_AUDIO_ANALOG
HS_MIC_BIAS
=I2C_MIKEY_SCL
HS_SCL
HS_MIC_HI
HS_SDA
HS_RST
HS_INT_L
HS_MIC_LO
HS_SW_DET
=I2C_MIKEY_SDA
AUD_I2C_INT_L
AUD_IPHS_SWITCH_EN
AUD_BI_PORT_E_L
GND_AUDIO_CODEC
HS_RX_BP
GND_AUDIO_CODEC
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM
AVDD_S0_HS
GND_AUDIO_CODEC
=PP3V3_S0_AUDIO
55C4
55C4
55C4
55B8
55B8
55B8
55B5
55B5
55B5
55B4
55B4
55B4
55A8
55A8
55A8
55A4
55A4
55A4
55A2
55A2
55A2
54B3
54B3
54B3
53C8
53C8
53C8
53B8
53B8
53B8
53A8
53A8
53A8
52C6
52C6
52C3
55B5
52C3
52B6
52B6
54D8
51D3
51D3
51D3
51D3
51D8
51A3
51B7
51B7
51B7
51A7
7C3
51A7
51A7
51A7
8C5
Preliminary
IN
IN
IN
IN
GND
PGND
VDD
PVDD
IN-
IN+
SYNC
OUT-
OUT+
SHDN*
THRML
PAD
GND
PGND
VDD
PVDD
IN-
IN+
SYNC
OUT-
OUT+
SHDN*
THRML
PAD
GND
PGND
VDD
PVDD
IN-
IN+
SYNC
OUT-
OUT+
SHDN*
THRML
PAD
IN
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
80 HZ < FC < 132 HZ 12DB
SUB
169 HZ < FC < 282 HZ
SATELLITE & SUB TWEETER AMPLIFIER
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
SATELLITE
APN:353S1595
GAIN
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
X7R
C6610
CRITICAL
402
1 2
10%
16V
0.047UF
51C3
51C7
51C3 53B8 53C8
402
2
CERM
1
6.3V
10%
C6607
1uF
0402
FERR-1000-OHM
L6620
1 2
0402
1
FERR-1000-OHM
L6610
2
2
C6606
1UF
402
1
6.3V
CERM
10%
FERR-1000-OHM
0402
L6630
1 2
51C3
1
6.3V
C6609
10%
1uF
402
2
CERM
10
U6630
TDFN1
1
74
5
3
2
9
8
6
11
CRITICAL
MAX9705
MAX9705
CRITICAL
TDFN1
7
1
6
5
8 9
2 3
4
11
10
U6610
CRITICAL
MAX9705
10
U6620
437
2
9
8
5
6
1
TDFN1
11
CRITICAL
C6611
0.047UF
402
1
2
16V
10% X7R
CERM
6.3V
C6608
1
2
1uF
10%
402
2
1
402
1UF
CERM
C6602
6.3V
10%
R6601
NO STUFF
1
100
5% MF-LF
402
2
1/16W
CERM
402
C6604
6.3V 2
1UF
1
10%
5%
R6602
MF-LF
1
2
1/16W 402
NO STUFF
100
R6603
0
MF-LF
1
5%
402
1/16W
2
MF-LF
R6604
1/16W
1
2
5%
0
402
R6605
NO STUFF
1/16W
1 2
0
402
MF-LF
5%
R6606
NO STUFF
MF-LF
402
5%
0
1/16W
21
R6607
402
MF-LF
0
1 2
1/16W
5%
NO STUFF
1
2
100UF
20%
C6601
CRITICAL
TANT
6.3V
1
2
CRITICAL
C6603
100UF
6.3V TANT
20%
100UF
1
2
TANT
20%
6.3V
CRITICAL
C6605
R6608
2
1/16W MF-LF
1
402
5%
0
R6609
1/16W
0
1
402
5%
MF-LF
2
5%
1/16W
1 2
402
MF-LF
0
R6610
51C3 53A8 53B8
51C3 53A8 53C8
402
1/16W
100K
R6611
5% MF-LF
0.047UF
402
CRITICAL
10%
16V
X7R
C6630
16V
10% X5R
0.1UF
CRITICAL
C6620
402
C6631
402
CRITICAL
X7R
16V
0.047UF
10%
C6621
10% X5R
402
16V
0.1UF
CRITICAL
AUDI0: SPEAKER AMP
SYNC_MASTER=AUDIO
SYNC_DATE=07/01/2008
051-7537
109
66
A
AUD_VREF_PORT_B
GND_AUDIO_CODEC
=PP5V_S3_AUDIO_AMP
SPKRAMP_SYNC2
GND_SPKR_AMP
GND_AUDIO_CODEC
MAX9705_L_N
GND_SPKR_AMP
MAX9705_SUB_N
SPKRAMP_SUB_SHDN
AUD_SPKRAMP_INSUB
AUD_SPKRAMP_INL_L
AUD_SPKRAMP_INL
AUD_SPKRAMP_INSUB_L
SPKRAMP_SYNC1
AUD_BI_PORT_B_L
MIN_NECK_WIDTH=0.20 MM SPKRAMP_SUB_P_OUT
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.30 mm
SPKRAMP_SUB_N_OUT
SPKRAMP_SYNC2
SPKRAMP_L_SHDN
AUD_VREF_PORT_B
GND_AUDIO_CODEC
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_L_P_OUT
SPKRAMP_SYNC1
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.30 mm
SPKRAMP_R_P_OUT
AUD_SPKRAMP_INR_L
AUD_BI_PORT_C_R
=PP5V_S3_AUDIO_AMP
VOLTAGE=5V
=PP5V_S3_AUDIO_AMP
AUD_BI_PORT_B_R
AUD_SPKRAMP_INR
AUD_VREF_PORT_B
SPKRAMP_R_SHDN
MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM
GND_SPKR_AMP
MAX9705_R_N
SPKRAMP_L_N_OUT
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.30 mm
SPKRAMP_R_N_OUT
55C4
55C4
55C4
55B8
55B8
55B8
55B5
55B5
55B5
55B4
55B4
55B4
55A8
55A8
55A8
55A4
55A4
55A4
55A2
55A2
55A2
54B3
54B3
54B3
53C8
53C8
53B8
53A8
53B8
53A8
52C6
52C6
52C6
52C3
52C3
52C3
52B6
52B6
52B6
51D3
53D8
53C4
51D3
53C4
51D3
53D8
53C8
53B3
51B7
53C8
53B3
51B7
53A4
54C2
54C2
51B7
54C2
54C2
53B8
53B8
53A4
54C2
54C2
51A7
8C3
53B3
51A6
51A7
51A6
53C4
7C7
7C7
53A4
51A7
7C7
53A3
7C7
8C3
8C3
51A6
7C7
7C7
Preliminary
IN
IN IN
IN
IN
IN
OUT
OUT
OPERATING VOLTAGE 3.3
A - VIN
SHELL
POF
B - VCC C - GND
AUDIO
SHIELD
PINS
AUDIO
PINS
SHELL
SHIELD
POF
A - VDD B - GND
C - VOUT
OPERATING VOLTAGE 3.3
OUT
OUT
OUT
BI
BI
OUT
IN
BI
BI
OUT
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
MIC EMI FILTER
APN:518S0521
MIC CONNECTOR
APN:518S0520
CHASSIS GND BAND AID
C6760 - C6763 ARE FOR FILTERING POTENTIAL FSB NOISE COUPLED ON SPKR LINES
APN:518S0519
AUDIO JACK 2: LINE IN CONNECTOR, SPDIF RX
SPEAKER CONNECTOR
AUDIO JACK 1: LO/HP CONNECTOR, SPDIF TX
APN:514-0607
APN:514-0608
C6700
1
2
10%
1UF
402
6.3V
CERM
7C7
53B2
7C7
53B2
7C7
53C3
7C7
53C3
XW6700
21
SM
XW6701
2
SM
1
7C7
53A2
7C7
53B2
6
78171-0004
M-RT-SM
4
3
2
1
5
J6703
CRITICAL
M-RT-SM
2
1
CRITICAL
J6702
4
78171-0002
3
0402
21
FERR-1000-OHM
L6770
0402
L6772
21
FERR-1000-OHM
55A6
55A6
0402-LF
FERR-120-OHM-1.5A
L6751
CRITICAL
21
21
L6771
0402
FERR-1000-OHM
L6773
0402
21
FERR-1000-OHM
6.8V-100PF
402
1
2
CRITICAL
DZ6770
6.8V-100PF
CRITICAL
2
1
402
DZ6771
6.8V-100PF
402
DZ6702
CRITICAL
2
1
402
CRITICAL
1
2
DZ6704
6.8V-100PF
DZ6705
402
6.8V-100PF
1
2
CRITICAL
6.8V-100PF
1
DZ6703
402
2
CRITICAL
CRITICAL
DZ6753
402
2
1
6.8V-100PF
6.8V-100PF
CRITICAL
DZ6752
402
1
2
0402
FERR-1000-OHM
2
L6754
1
DZ6754
CRITICAL
1
2
6.8V-100PF
402
6.8V-100PF
DZ6755
1
2
402
CRITICAL
R6790
1
402
1/16W MF-LF
5%
0
2
22
MF-LF
402
1/16W
5%
R6749
CRITICAL
J6701
78171-0003
M-RT-SM 4
2 3
1
5
1 2
L6756
FERR-1000-OHM
0402
C6761
5%
100PF
402
CERM
50V
100PF
C6760
50V CERM 402
5%
C6762
100PF
50V CERM
5%
402
C6763
100PF
50V 402
5% CERM
0
NOSTUFF
MF-LF
R6760
402
1/16W
5%
R6750
1/16W
402
MF-LF
2
10K
5%
1
F-RT-TH3
5
6
3
1
4
9
7 8
2
10
12 13
11
CRITICAL
J6700
AUDIO-JACK-TRANS-M97
F-RT-TH3
5 2 1 3 4
6
8
7
10 11 12
9
AUDIO-RCVR-M97
J6750
CRITICAL
0402
FERR-1000-OHM
L6710
FERR-1000-OHM
0402
L6709
52B3
52C3
DZ6706
CRITICAL
402
6.8V-100PF
R6755
0
402
MF-LF
1/16W
5%
5% 1/16W MF-LF
0
R6756
402
402
1
4.7
5%
MF-LF
R6751
1/16W
2
5% 1/16W MF-LF
402
0
R6754
5% 1/16W MF-LF
402
0
R6753
5% 1/16W MF-LF
402
0
R6752
0
R6707
402
MF-LF
1/16W
5%
5% 1/16W MF-LF
402
0
R6705
0
402
MF-LF
1/16W
5%
R6704
R6703
0
402
MF-LF
1/16W
5%
R6706
0
402
MF-LF
1/16W
5%
MF-LF
R6702
0
402
1/16W
5%
402
C6756
5%
2
1
50V
CERM
100PF
C6750
1
2
10%
6.3V
CERM
1UF
402
51C2
55A3
55B3
55A8
51C3
55C1 55D1
FERR-120-OHM-1.5A
L6701
0402-LF
21
CRITICAL
FERR-1000-OHM
1
0402
2
L6704
L6706
0402
21
FERR-1000-OHM
55B6 55B8
55C8
2
R6700
10K
MF-LF
1
5%
402
1/16W
4.7
R6701
2
MF-LF
5%
1/16W
402
1
C6705
1
2
100PF
CERM
5% 402
50V
AUDIO: JACK
SYNC_MASTER=AUDIO
109
A
67
051-7537
SYNC_DATE=07/01/2008
AUD_CONNJ1_SLEEVEDET
GND_AUDIO_CODECAUD_J2_COM
MIC_LO_CONN_F
MIC_LO
AUD_LO_GND
MIN_LINE_WIDTH=0.4MM
AUD_CONNJ1_SLEEVE_F
MIN_NECK_WIDTH=0.2MM
AUD_SPDIF_OUT
AUD_CONNJ1_MIC_F
AUD_CONNJ1_TIPDET
AUD_CONNJ1_MIC
AUD_CONNJ1_TIP
MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.2MM
PP3V3_S0_AUDIO_SPDIF
MIN_LINE_WIDTH=0.2MM
AUD_CONNJ1_RING
MIN_NECK_WIDTH=0.15MM
AUD_CONNJ1_SLEEVE
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
AUD_CONNJ1_TIP_F
MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.2MM
AUD_CONNJ1_RING_F
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.15MM
AUD_J1_COM
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
AUD_CONNJ1_TIPDET_F
AUD_PORTA_L
AUD_CONNJ2_SLEEVE_F
AUD_J2_TIPDET_R
AUD_CONNJ2_TIPDET_F
=GND_CHASSIS_AUDIO_JACK
AUD_CONNJ2_TIP_F
AUD_CONNJ2_TIPDET
AUD_CONNJ2_TIP
AUD_CONNJ2_SLEEVEDET
PP3V3_S0_AUDIO_SPDIF
AUD_CONNJ2_SLEEVEDET_F
AUD_CONNJ2_RING
AUD_CONNJ2_RING_F
AUD_J2_OPT_OUT
AUD_SPDIF_I
AUD_CONNJ2_SLEEVE
AUD_PORTA_R
=GND_CHASSIS_AUDIO_JACK
AUD_LO_AMP_OUTR
AUD_CONNJ1_SLEEVEDET_F
AUD_LO_AMP_OUTL
AUD_J1_SLEEVEDET_R
=PP3V3_S0_AUDIO
=GND_CHASSIS_AUDIO_MIC
MIC_SHLD_CONN
MIC_LO_CONN
MIC_HI_CONN
MIC_HI_CONN_F
MIC_LO_CONN
MIC_HI
AUD_J1_TIPDET_R
MIC_HI_CONN
SPKRAMP_L_P_OUT SPKRAMP_L_N_OUT
SPKRAMP_SUB_N_OUT
SPKRAMP_R_N_OUT
SPKRAMP_R_P_OUT
HS_MIC_HI
HS_MIC_LO
SPKRAMP_SUB_P_OUT
55C4 55B8 55B5 55B4 55A8 55A4
55A2 53C8 53B8 53A8 52C6 52C3
55B5
52B6
52D6
51D3
51D8
51B7
54B8
54A8
51A7
55A4
55A6
54B1
54D2
54D2
54B1
51A7
55C1
54B8
9C8
54D8
9C8
8C5
9C8
7D7
7D7
7D7
7D7
7D7
Preliminary
IN
IN
OUT
IN
IN
IN
IN
OUT
IN
IN
OUT
IN
IN
OUT
SVSS
INL
SHDN*
INR
VDD
PVSS
PGND
SGND
THRM
OUTR
OUTL
C1P C1N
PAD
D
SG
D
SG
D
SG
D
SG
D
G S
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
VREF_B(100%)
PLACE C6852 NEAR U6200
MIC INPUT CIRCUITRY
NC
HP/LO AMP
APN:353S1637
PLACE CLOSE TO U6801
NC
LINE-IN (PORT A) DETECT
0X15 (21,PORTA)
DET ASSIGNMENT
VREF_F (80%)
0X16 (22, PORTG)
0X14 (20,PORTD) N/A
N/A
VREF
N/A N/A N/A
N/A
DET ASSIGNMENT
VREF_B(100%)
0X19 (25,PORTF)
0X15 (21,PORTA)
MUTE CONTROL
PIN COMPLEX
0X1F (31,SPDIF IN)
GPIO 0
0X0A (10)
0X07 (7)
CONVERTER 0X08 (8)
N/A
0X1A (26,PORTC)
MUTE CONTROL 0X08 (8) 0X07 (7) N/A
0X05 (5)
0X02 (2)
CONVERTER
0X08 (8) N/A
0X07 (7)
0X0F (15)
0X0D (13)
0X0C (12)
MIXER
VOLUME
N/A
N/A
0X24 (36)
0X23 (35)
SAT SPKRS
SPDIF IN
SUB SPKR SPDIF OUT
MIC IN
FUNCTION LINE IN
FUNCTION HP OUT
PORT A LI
MAX9724 GAIN/FILTER COMPONENTS
PORT D HP/LO
0X18 (24,PORTB)
PLACE L6800/C6800 CLOSE TO Q6800
0X03 (3) 0X06 (6)
PORT D DETECT
NC
PORT G DETECT(SPDIF DELEGATE)
PIN COMPLEX
0X1E (30,SPDIF OUT)
VOLUME
CODEC INPUT SIGNAL PATHS
CODEC OUTPUT SIGNAL PATHS
0X14 (20,PORTD)
AV_PB = -1 V/V, FC_HPF=5.28HZ, FC_LPF=34.45KHZ
X5R
10%
402
2
16V
C6801
1
0.1UF
402
MF-LF
5%
1/16W
1 2
47K
R6802
51C7
51C7
51C2 55A8
54C3
C6850
0.1uF
2
CRITICAL
10% X5R 402
16V
1
0
402
5%
1/16W
NO STUFF
21
R6853
MF-LF
SM
21
XW6800
5%
MF-LF
402
1/16W
0
21
R6854
2.2K
1 2
5%
MF-LF
1/16W
R6855
402
5% 1/16W MF-LF
100K
402
2
1
R6852
R6851
330
1
5%
MF-LF
1/16W
402
2
680PF
402
10%
50V
CERM
2
1
CRITICAL
C6851
54B3
54B3
7D7
54D2
C6800
1
2
402
0.1UF
X5R
16V
10%
L6800
1
0402
2
FERR-1000-OHM
1/16W
5%
MF-LF
1
402
2
100K
R6803
R6861
270K
402
MF-LF
1/16W
2
1
5%
C6802
CERM
10%
16V
402
0.01UF
2
1
51C2
54C3 55B6
C6811
402X5R
16V
10%
2
1
0.1UF
R6812
1/16W MF-LF
402
5%
47K
21
54A3
NO STUFF
100PF
50V
5%
CERM
402
2
1
C6852
CRITICAL
402
R6850
1 2
MF-LF
6.81K
1%
1/16W
10UF
CRITICAL
1
2
20%
C6853
6.3V
X5R 603
2
5%
1
R6801
270K
1/16W
402
MF-LF
1
R6811
1/16W
5%
402
2
MF-LF
270K
51C3 54A3
27.4K
402
MF-LF
1/16W
2
1%
1
R6836
54A3
1
2
402
1% 1/16W MF-LF
27.4K
R6837
51C3
5%
2
1/16W
402
0
MF-LF
NO STUFF
1
R6856
10
CRITICAL
TQFN
MAX9724A
12
972
11
8
6
1
U6801
13
3
4
5
SM
21
XW6880
2
1
402-1
C6884
10% 10V
CRITICAL
X5R
1UF
2
1
402-1
CRITICAL
10V
10% X5R
1UF
C6885
1UF
10%
2
1
402-1
C6882
CRITICAL
X5R
10V
C6880
0.1UF
10%
402
16V
2
1
0402-LF
21
L6880
FERR-120-OHM-1.5A
1%
402
MF-LF
1/16W
2
1
2.21K
R6880
1% MF-LF
2
1
402
R6881
2.21K
1/16W
603
6.3V
20%
10UF
2
1
C6881
X5R
1/16W
5%
0
NO STUFF
1
402
MF-LF
2
R6882
CRITICAL
C6832
2.2UF
20%
402
TANT
6.3V
CRITICAL
C6833
2.2UF
20%
402
TANT
6.3V
1 2
402
TANT
CRITICAL
C6886
20%
2.2UF
6.3V
1 2
402
20%
TANT
CRITICAL
2.2UF
C6889
6.3V
1
2
6
Q6800
SOT563
SSM6N15FEAPE
5
4
3
SOT563
SSM6N15FEAPE
Q6800
Q6801
SSM6N15FEAPE
5
4
SOT563
3
2
1
6
SSM6N15FEAPE
SOT563
Q6801
Q6802
SOD-VESM-HF
2
1
SSM3K15FV
3
1 2
402
21K
R6884
1% 1/16W MF-LF
1 2
402
220PF
CERM
25V
C6891
CRITICAL
5%
1 2
402
220PF
CERM
25V
CRITICAL
C6888
5%
1 2
402
MF-LF
1%
R6883
13.7K
1/16W
1 2
402
21K
MF-LF
1/16W
1%
R6888
1 2
402
MF-LF
13.7K
1%
1/16W
R6886
R6805
MF-LF
1/16W 402
1%
10K
1% 1/16W
402
MF-LF
5.11K
R6806
1%
39.2K
402
1/16W MF-LF
R6813
R6885
MF-LF
1/16W 402
10K
5%
SYNC_DATE=07/01/2008
A
68
109
051-7537
AUDIO: JACK TRANSLATORS
SYNC_MASTER=AUDIO
AUD_LO_AMP_INL_M
AUD_LO_AMP_OUTL
GND_AUDIO_CODEC
MAX9724_SVSS
AUD_LO_AMP_INL_C
AUD_PORTG_DET_LAUD_PORTD_DET_L
AUD_OUTJACK_INSERT_L
AUD_SENSE_B
AUD_SENSE_A
GND_AUDIO_CODEC
GND_AUDIO_CODEC
AUD_PORTA_L
GND_AUDIO_CODEC
AUD_LO_AMP_INR_M
AUD_SENSE_A
AUD_J1_SLEEVEDET_R
AUD_BI_PORT_F_L MAKE_BASE=TRUE
AUD_BI_PORT_F_R
GND_AUDIO_CODEC
MIC_INMIC_HI
AUD_J1_SLEEVEDET_R
GND_AUDIO_CODEC
AUD_INJACK_INSERT_L
PP3V3_S0_AUDIO_F
PP3V3_S0_AUDIO_F
=PP3V3_S0_AUDIO
AUD_J1_TIPDET_R
AUD_LO_AMP_OUTR
AUD_BI_PORT_D_L
AUD_BI_PORT_D_R
AUD_LO_AMP_INR_C
AUD_BI_PORT_A_L
=PP5V_S3_AUDIO
PP3V3_S0_AUDIO_F
MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM
AUD_PP5V_F
AUD_J2_TIPDET_R
AUD_PORTA_R
AUD_BI_PORT_A_R
PP3V3_S0_AUDIO_F
AUD_J1_DET_RC
AUD_J2_DET_RC
GND_AUDIO_CODEC
MIN_LINE_WIDTH=0.2MM
AUD_LO_AMP_OUTL
MIN_NECK_WIDTH=0.15MM
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM
AUD_LO_AMP_OUTR
MAX9724_C1P
=GND_CHASSIS_AUDIO_MIC
VREF_PORT_F_R
AUD_VREF_PORT_F
MIC_SHLD_CONN
GND_AUDIO_CODEC
MIC_LO
AUD_J1_SLEEVEDET_INV
AUD_LO_AMP_INL_M
MAX9724_C1N
AUD_LO_AMP_INR_M
AUD_GPIO_0
AUD_LO_GND
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
55C4
55C4
55B8
55B8
55B8
55C4
55C4
55C4
55C4
55C4
55B5
55B5
55B5
55B8
55B8
55B8
55B8
55B8
55B4
55B4
55B4
55B5
55B5
55B4
55B5
55B5
55A8
55A8
55A8
55B4
55A8
55A8
55B4
55B4
55A4
55A4
55A4
55A8
55A4
55A4
55A4
55A8
55A2
55A2
55A2
55A4
55A2
55A2
55A2
55A2
54B3
54B3
54B3
54B3
54B3
54B3
54B3
54B3
53C8
53C8
53C8
53C8
53C8
53C8
53C8
53C8
53B8
53B8
53B8
53B8
53B8
53B8
53B8
53B8
53A8
53A8
53A8
53A8
53A8
53A8
53A8
53A8
52C6
52C6
52C6
52C6
52C6
52C6
52C6
52C6
52C3
52C3
52C3
52C3
52C3
52C3
54D8
52C3
52C3
52B6
52B6
52B6
52B6
52B6
52B6
52D6
52B6
52B6
51D3
51D3
51D3
51D3
51D3
51D3
55C8
55C8 51D8
55B8
55C8
51D3
51D3
55D1
51B7
51B7
51B7
51B7
55C8
51B7
55B8
51B7
55B8
55B8 51A7
55D1
51A7
55B4
55B4
51B7
55C1
55B1
54A3
51B7
55D3 54C3
51A7
51A7
51A7
51A7
55D3
51C2
51C3
51C3
51A7
54C3
51A7
55B4
55A8
8C5
54C3
8C3
55A8
55A8
51A7
54C3
54C3
9C8
51C3
51A7
55C2
55B2
51C7
54B3
Preliminary
V-
V+
BI
D
S G
D
S G
G
D
S
N-CHN
G
P-CHN
S
D
IN
NC
FB
BIAS
SW
SHDN*
NC
VIN
BOOST
GND
NC
NC
BI
OUT
BI
D
G S
NC
NC
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
Vgs(max) = 8V
If ADAPTER_SENSE > Vth then turn off FET
<Ra>
Vgs = 4.74V @ 13V DCIN
Vgs is met when SYS_ONEWIRE is high or low.
SYS_ONEWIRE doesn’t drive unpowered U6990
Q6920 used as bilateral switch to ensure
Vth = Vdcin * (Rb / (Ra + Rb)) Vth = Vdcin / 2
<Vth>
<Rb>
<Ra>
Vout = 3.425V
TO SMC
BIL BUTTON DEBOUNCE CIRCUIT
(Switcher limit)
200mA max output
518S0588
VOLTAGE DIVIDER FROM DCIN ENSURES Q6910
Vgs = 7.30V @ 20V DCIN
Supply needs to guarantee 3.31V delivered to SMC VRef generator
<Rb>
3.425V "G3Hot" Supply
Vout = 1.25V * (1 + Ra / Rb)
1-Wire OverVoltage Protection
BATTERY SIGNAL CONNECTOR
(SMC_BIL_BUTTON_L)
BATTERY POWER CONNECTOR
516S0698
MagSafe DC Power Jack
518S0656
adapter detects system and enables 16.5V output.
Q6910 restricts system load to 10K-70K window until
1
2
402
180K
MF-LF
5%
1/16W
R6911
C6910
1
2
402
CERM
50V
10%
0.001UF
R6917
1
2
402
270K
1/16W
5%
MF-LF
R6915
1
2
1/16W
5%
MF-LF
270K
402
C6915
1
2
402
25V
10% X5R
0.1UF
R6913
1
2
5%
MF-LF
402
1/16W
100K
R6912
1
2
402
470K
MF-LF
5%
1/16W
R6918
1
2
402
270K
MF-LF
5%
1/16W
C6917
1
2
CERM
10%
0.001UF
50V
402
U6915
CRITICAL
LM397
SOT23-5-HF
5
4
3
2
1
R6920
1
2
402
1/16W
1% MF-LF
24.3K
C6905
1
0.01UF
603
50V
20% CERM
2
R6914
1
2
1/16W
100K
5%
402
MF-LF
39B8 40B2
Q6920
3
5
4
SOT563
CRITICAL
SSM6N15FEAPE
Q6920
6
2
1
SOT563
SSM6N15FEAPE
CRITICAL
Q6910
6
2
1
CRITICAL
SOT-963
NTUD3127CXXG
CRITICAL
Q6910
3
5
4
NTUD3127CXXG
SOT-963
R6910
1 2
1/16W
5%
MF-LF
1K
402
39C5 40B2 40D5
R6916
1
2
402
MF-LF
270K
5%
1/16W
CRITICAL
C6999
1
2
6.3V
20% CERM
805
22UF
CRITICAL
L6995
33UH
CDPH4D19FHF-SM
1 2
C6994
1
2
X5R
6.3V
20%
402
0.22uF
R6995
1
2
402
1/16W
1%
MF-LF
348K
1
2
50V 402
CERM
5%
22pF
C6995
R6996
1
2
402
1/16W
1%
MF-LF
200K
C6990
10% 25V X5R
2
1
805
10UF
U6990
CRITICAL
LT3470ETS8
TSOT23-8
2
1
3 6
5 7
8
4
R6905
1 2
805
5%
1/8W
47
MF-LF
5
3
2
1
M-RT-SM
78048-0573
J6900
CRITICAL
4
D6905
HN2D01JEAPE
SOT665
1
3
5
4
2
42C3 56A6
8D1
56B3
42C3 56A6
SM-LF
21
FERR-50-OHM
L6951
L6950
1 2
SM-LF
FERR-50-OHM
Q6915
3
1
2
SSM3K15FV
SOD-VESM-HF
CRITICAL
R6928
1 2
402
MF-LF
0
1/16W
5%
C6953
1
2
402
50V
CERM
5%
47PF
C6952
1
2
5%
CERM
50V 402
47PF
CERM
0.001UF
50V 402
10%
2
1
C6954
1
10%
0.1UF
X5R 402
2
25V
C6950
C6951
1
2
402
X5R
25V
10%
0.1UF
SOT-553
2
351
4
74LVC1G17DRL
U6960
0.1UF
10% X5R
16V
2
1
402
C6960
MF-LF
5%
1/16W
10K
1 2
402
R6960
C6961
402
1
2
0.01UF
10% X7R
25V
39C5
J6955
78171-0005
CRITICAL
M-RT-SM
6
1 2
4 5
3
7
47PF
5%
50V
CERM
C6956
2
1
402
F-RT-SM
10
CRITICAL
BAT-M98
J6950
3
1 2
4 5 6 7 8 9
11
1206-1
1 2
CRITICAL
F6905
6AMP-24V
CRITICAL
RCLAMP2402B
D6950
3
2
1
SC-75
69
109
051-7537
A
DC-In & Battery Connectors
SYNC_MASTER=JACK
SYNC_DATE=03/13/2008
=SMBUS_BATT_SCL =SMBUS_BATT_SDA
GND_BATT_CONN
VOLTAGE=0V
MIN_NECK_WIDTH=0.4 mm
MIN_LINE_WIDTH=0.6 mm
=PP18V5_DCIN_CONN
MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V
MIN_LINE_WIDTH=1mm
PP18V5_DCIN_FUSE
PPVBAT_G3H_CONN_F
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V
SMC_BIL_BUTTON_DB_L
P3V42G3H_FB
=SMBUS_BATT_SDA
=PP3V42_G3H_BATT
BATT_POS_F
=SMBUS_BATT_SCL
ADAPTER_SENSE_R
=PP3V42_G3H_REG
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
P3V42G3H_SW
P3V42G3H_BOOST
SMC_BIL_BUTTON_L
ONEWIRE_EN
=PP3V42_G3H_BATT
SYS_ONEWIRE_BILAT
=PP18V5_DCIN_CONN
VOLTAGE=18.5V
MIN_NECK_WIDTH=0.3 mm
MIN_LINE_WIDTH=0.3 mm
PPDCIN_S5_P3V42G3H
VOLTAGE=18.5V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm
PPVIN_G3H_P3V42G3H
VOLTAGE=12.6V
MIN_NECK_WIDTH=0.3 mm
BATT_POS_F
MIN_LINE_WIDTH=0.6 MM
ADAPTER_SENSE
ONEWIRE_ESD
ONEWIRE_DCIN_DIV
SYS_ONEWIRE
SMC_BC_ACOK
SMC_BC_ACOK_RC
ONEWIRE_OVERVOLT
ONEWIRE_PWR_EN_L_DIV
VOLTAGE=18.5V
PP18V5_DCIN_ONEWIRE
MIN_LINE_WIDTH=0.25mm MIN_NECK_WIDTH=0.20mm
ONEWIRE_PWR_EN_L
SMC_BS_ALRT_L
56A3
56A3
56B8
57A2
56A3
56D1
57A2
42C3
42C3
7A7
8C2
7B7
7B7
7A7
56B8
8D2
8D1
8C2
56A7
7B7
Preliminary
GND
VCC
D
SG
D
SG
CSON
CSOP
VNEG
VCOMP
ICOMP
VREF ACIN
SDA
VHST SCL
VDDP
BGATE
VDD
ACOK
THRM_PAD
AGATE
AGND
AMON BMON
BOOT
CSIN
CSIP
DCIN
LGATE
PGND
PHASE
UGATE
TRKL*
D
G
S
D
G
S
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
(CHGR_CSO_R_N)
(CHGR_ACIN)
BATTERY INRUSH FETS
NC
NC
(CHGR_CSOP)
(CHGR_CSON)
TO SYSTEM
(??? limited)
MAX CURRENT = 7A
TO BATTERY
PWM FREQ. = 400 kHz
AMON PULLDOWN LOGIC
PBUS SUPPLY / BATTERY CHARGER
1W
CRITICAL
R7020
0.5%
0.02
MF 0612
2
1
1
1/16W
4.7
R7040
5% MF-LF
402
2
25V X5R
10%
402
0.1UF
2
1
C7025
1 2
402-1
C7041
1UF
10% X5R
10V
C7023
X5R
10% 25V
1UF
603-1
1
2
C7022
10% X5R
1UF
25V 603-1
1
2
1
2
CASE-D2-SM
POLY-TANT
20%
22UF
25V
C7020
CRITICAL
1
2
CASE-D2-SM
POLY-TANT
20%
22UF
25V
C7021
CRITICAL
1
C7040
1UF
2
402-1
10V X5R
10%
C7047
2
1
402-1
1UF
10% 10V X5R
25V X5R 402
0.1UF
10%
2
1
C7010
10%
0.01UF
402
CERM
16V
2
1
C7044
402
1/16W MF-LF
56.2K
1%
2
1
R7045
402
10%
0.001UF
CERM
50V
2
1
C7045
3.01K
1/16W
1%
402
MF-LF
2
1
R7046
CERM
50V 402
10%
2
1
C7046
470PF
2
XW7000
SM
1
2
1
402
0.001UF
50V
C7026
10% X7R
1
C7063
0.1UF
402
25V
10% X5R
2
402
MF-LF
1/16W
1%
57.6K
2
1
R7060
402
R7099
2
100K
MF-LF
5%
1/16W
1
R7098
1
1/16W
100K
5%
MF-LF
402
2
CRITICAL
2
U7060
1
SOT23-5
TL331
5
4
3
1
10%
0.1UF
C7060
2
402
25V X5R
Q7070
6
2
1
SSM6N15FEAPE
SOT563
Q7070
3
5
4
SSM6N15FEAPE
SOT563
XW7021
SM
1 2
SM
21
XW7020
10V
2
CERM
402
10%
C7024
0.047UF
1
R7021
MF-LF 402
5%
1/16W
10
21
R7023
1
5%
1/16W 402
MF-LF
10
2
10% 402
2
1
C7061
0.1UF
25V X5R
C7062
10% X5R
402
2
1
0.1UF
25V
R7062
MF-LF
1/16W
62K
5%
2
1
402
R7001
62K
MF-LF
402
1/16W
5%
21
C7043
10% X5R
0.1UF
21
16V 402
1/16W
402
30.1K
1%
MF-LF
2
1
R7010
MF-LF
R7011
1%
1/16W
9.31K
402
2
1
1
2
402
1K
MF-LF
1/16W
5%
R7073
R7074
1
2
MF-LF
402
1/16W
1M
5%
R7075
1
2
NOSTUFF
MF-LF
5%
1M
402
1/16W
1/16W
MF-LF
1.82K
2
1
R7061
402
1%
1 2 3
5
4
CRITICAL
LFPAK-HF
RJK0305DPB
Q7020
LFPAK-HF
RJK0305DPB
Q7021
CRITICAL
4
1 2 3
5
7AMP
1206
1 2
CRITICAL
F7000
2
603-1
C7011
X5R
10% 25V
1
1UF
CRITICAL
C7008
POLY-TANT CASED2E-SM
33UF
16V
20%
2
1
R7031
10
1/16W MF-LF
5%
402
10
1/16W MF-LF
402
5%
R7047
21
25
QFN
22
24
2
CRITICAL
20
ISL6258A
4
8
12
19
7
13
29
10
11
23
5
18 17
28 27
15
16
9
26
6
1
14
3
U7000
402
X5R
16V
10%
0.033UF
2
1
C7042
IHLP4040DZ-SM
4.7UH-9.5A
CRITICAL
21
L7000
5
2
HAT1127H
LFPAK-SM
CRITICAL
31
4
Q7000
1
LFPAK-SM
CRITICAL
HAT1127H
32
4
5
Q7001
1SS418
SOD-723-HF
D7010
21
Q7050
3
21
4
5 6 7 8
FDS6681Z
CRITICAL
SO-8
CERM
402
50V
2
1
C7028
20%
0.001UF
CERM
402
20% 50V
2
1
C7027
0.001UF
Q7052
CRITICAL
FDS6681Z
8765
4
1 2
3
SO-8
C7052
2
1
402
10% X5R
0.1UF
16V
R7053
MF-LF 1/16W
5%
330K
402
1 2
R7052
1M
1/16W
MF-LF
402
5%
1 2
CRITICAL
R7008
0612
43
21
MF
1W
0.01
0.5%
C7050
1
2
0.01uF
16V
10%
402
CERM
C7051
1
2
X5R
16V
10%
402
0.1UF
PBUS Supply/Battery Charger
SYNC_DATE=01/31/2008
109
A
051-7537
70
SYNC_MASTER=RAYMOND
CHGR_CSIN
CHGR_CSIP
CHGR_BGATE
CHGR_BOOT CHGR_UGATE
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
CHGR_PHASE
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
CHGR_AGATE
GND_CHGR_SGND
GND_CHGR_SGND
CHGR_LGATE
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.3 MM
MIN_LINE_WIDTH=0.6 MM
PPVDCIN_G3H_PRE2
CHGR_CSOP
CHGR_VCOMP
CHGR_VDD_L
CHGR_AMON
CHGR_VDD
CHGR_VDD_R
=PP3V42_G3H_CHGR
CHGR_CSON
=PP18V5_G3H_CHGR
CHGR_CSO_R_P
CHGR_DCIN
MIN_NECK_WIDTH=0.25 MM
PPVBAT_G3H_CHGR_REG
MIN_LINE_WIDTH=0.6 MM
BATT_POS_INRUSH
BATT_POS_GATE
PPVBAT_G3H_CHGR_OUT
BATT_POS_F
CHGR_BGATE
CHGR_LOWCURRENT_REF
=PPBUS_G3H
=SMBUS_CHGR_SCL
CHGR_VCOMP_R
CHGR_CSIN_XW7021
CHGR_DCIN
CHGR_AMON CHGR_BMON
CHGR_CSIP_XW7020
CHGR_VNEG_R
GND_CHGR_SGND
CHGR_LOWCURRENT_GATE_R
CHGR_LOWCURRENT_GATE
CHGR_VDD
=PP3V42_G3H_CHGR
MIN_LINE_WIDTH=0.6 MM
PP18V5_S5_CHGR_SW_R
MIN_NECK_WIDTH=0.3 MM
=CHGR_ACOK
CHGR_VNEG
CHGR_ICOMP
CHGR_ACIN
=SMBUS_CHGR_SDA
CHGR_SGATE
CHGR_VDDP
CHGR_AMON
=PP3V42_G3H_CHGR
MIN_NECK_WIDTH=0.3 MM
MIN_LINE_WIDTH=0.6 MM
PPVDCIN_G3H_PRE
PPVBAT_G3H_CHGR_OUT
CHGR_CSO_R_N
57D4
57D5
57D4
57D5
57B5
57C6
57C4
57C4
57B5
57C6
77D3
56B8
57A8
57B8
57A8
57A8
57A8
77D3
57A4
57B6
57B8
44B3
57C6
8D1
8C1
44A8
57D8
57B1
56A7
57C5
8C2
42C3
57C5
44B3
44A6
57B6
57A8
8D1
40D4
42B3
44B3
8D1
57A5
44A8
Preliminary
Q1
Q2
SW
IN
IN
D
SG
D
SG
S
D
G
S
D
G
DRVH1
SKIPSEL
VBST1
GND
THRM_PAD
ENTRIP1
VFB1
VO1
DRVL1
LL1
EN0
VCLK
ENTRIP2
PGOOD
VO2
VFB2
DRVL2
LL2
DRVH2
VBST2
VREG5
VREG3
VREF
VIN
TONSEL
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
Place XW7201 between Pin 15 and Pin 25 of U7200.
ROUTING NOTE:
ROUTING NOTE:
<RD>
VOUT = (2 * RC / RD) + 2
<RA>
NC
NC
<RC><RB>
MAX CURRENT = 4A
ROUTING NOTE:
Place XW7205 by C7252.
ROUTING NOTE:
Place XW7204 by Pin 2 of L7220.
Place XW7203 by Pin1 OF L7260.
ROUTING NOTE:
Place XW7202 by C7292.
PWM FREQ. = 375 KHZ MAX CURRENT = 4A
PWM FREQ. = 300 KHZ
5V_RT/3.3V POWER SUPPLY
SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.
VOUT = (2 * RA / RB) + 2
2
1
C7273
10UF
20% 603
X5R
6.3V
SM
1 2
XW7201
FDMS9600S
Q7220
CRITICAL
10
7
6 5
8
1
9 4 3 2
MLP
64D1
64D6
1
2
6
SSM6N15FEAPE
SOT563
Q7221
4
5
3
Q7221
SOT563
SSM6N15FEAPE
2 1
SM
XW7202
SM
2 1
XW7203
XW7205
SM
2 1
XW7204
SM
2 1
2 1
402
X5R
10% 16V
C7220
0.1UF
1
2
CASE-B2-SM
POLY-TANT
C7251
6.3V
150UF
20%
CRITICAL
2
1
C7250
20%
6.3V X5R
10UF
603
16V
33UF
20%
CRITICAL
POLY-TANT CASED2E-SM
2
1
C7240
21
3.3UH
IHLP
L7260
CRITICAL
21
1/16W MF-LF 402
1%
6.49K
R7270
1
402
10K
1% 1/16W MF-LF
R7269
2
X5R
25V
10%
1UF
C7241
603-1
1
2
1
2
CASE-B2-SM
POLY-TANT
20%
6.3V
150UF
CRITICAL
C7252
2 1
C7260
0.1UF
16V
10% X5R
402
MF-LF
21
R7267
1/16W 402
1%
15.0K
MF-LF
1%
10K
21
402
R7268
1/16W
25V
10% X5R
1UF
603-1
1
2
C7281
33UF
C7280
16V
CRITICAL
20% POLY-TANT
CASED2E-SM
2
1
1
2
CASE-B2-SM
POLY-TANT
6.3V
20%
150UF
CRITICAL
C7292
1
2
CASE-B2-SM
POLY-TANT
C7291
150UF
20%
6.3V
CRITICAL
2
1
C7290
10UF
20% X5R
603
6.3V
SI7110DN
Q7260
CRITICAL
5
4
3 12
PWRPK-1212-8-HF
IHLP2525CZ
1 2
4.7UH-5.5A
L7220
CRITICAL
CRITICAL
Q7261
SI7110DN
5
4
3 12
PWRPK-1212-8-HF
3
TPS51125
17
8
7
16
52
18
22
4
23
20
6
13
12
21
14
QFN
9
5V3V3S5_REG5
25
15
11
10
U7200
1
24
19
CRITICAL
3V3S5_VFB
2
1%
402
MF-LF
1/16W
1
75K
R7271 R7272
57.6K
2
1
1/16W
1%
MF-LF 402
25V
10%
1UF
X5R
C7272
603-1
1
2
6.3V
2
1
C7270
10UF
X5R
20% 603
10% 402
0.22UF
2
1
CERM
10V
C7271
SYNC_MASTER=RAYMOND
051-7537
72
109
A
SYNC_DATE=02/08/2008
5V/3.3V SUPPLY
=PP5VRT_S0_REG
VOLTAGE=5V
P5V3V3_PGOOD
=PPVIN_S0_5VRTS0
=PP3V3_S5_REG
VOLTAGE=3.3V
5V3V3S5_REG3
3V3S5_VFB_R7270
=P3V3S5_EN_L
MIN_NECK_WIDTH=0.2 MM
3V3S5_LL
MIN_LINE_WIDTH=0.6 MM
GND_5VRT3V3S5_SGND
=PPVIN_S5_3V3S5
5VRTS3_3V3S5_VREF
3V3S5_VBST
=P5VRTS0_EN_L
5VRT_S0_LL
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
5VRT_S0_DRVH
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
GND_5VRT3V3S5_SGND
3V3S5VO2
3V3S5_DRVH
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
3V3S5DRVL
5VRT_S0_VO1
3V3S5_ENTRIP
=PPVIN_S0_5VRTS0
5VRT_S0_VFB_XW7203
5VRT_S0_ENTRIP
5VRT_S0_VFB
5VRT_S0_DRVL
5VRT_S0_VBST
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
58C6
58B6
8D6
64A5
8C1
8B4
58C4
8C1
58A5
8C1
Preliminary
VDDQSET
S3
COMP
VTT
THRM_PAD
DRVH
LL
PGND
CS_GND
CS
PGOOD
NC1
S5
NC0
GND
VTTGND
MODE
DRVL
VTTREF VLDOIN
VBST V5IN
VDDQSNS
VTTSNSV5FILT
SYM (1 OF 2)
S
D
G
S
D
G
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
1.5V/0.75V(DDR3) POWER SUPPLY
VOUT = 0.75V * (1 + RA / RB)
1.5VHIGH
LOW 0.0V
1.5V
0.75V
PP0V75_S0
PWM FREQ. = 400 KHZ
ROUTING NOTE:ROUTING NOTE:
PUT 6 VIAS UNDER THE THERMAL PAD
Q7321 PIN1,2.3
CONNECT CS_GND TO USING KEVIN CONNECTION.
ROUTING NOTE:
NC
NC
<RB>
<RA>
Pin 3 and Pin 25
Place XW7300 between of U7300.
ROUTING NOTE:
Place XW7302 by Q7321.
ROUTING NOTE:
Place XW7301 by L7320.
PUT ONE BULK CAP NEXT TO THE LOAD
MAX CURRENT = 12A
PM_SLP_S3_L
S3
HIGH HIGH
PM_SLP_S4_L
LOW
LOW
PP1V5_S3
0.0V
0.0VS5/G3HOT
S0
STATE
ROUTING NOTE:
Place XW7303 by C7308.
CRITICAL
U7300
16
17
21
19
3
20
4 7
12
18
1310
11
25
14
9
8
23
24
1
5
TPS51116
QFN
6
22
15
2
1 2
SM-IHLP-1
1.0UH-13A-5.6M-OHM
L7320
CRITICAL
1 2
5% 1/16W
402
0
R7300
MF-LF
1
2
16V 402
X5R
10%
0.1uF
C7309
1
2
CASED2E-SM
POLY-TANT
33UF
CRITICAL
20% 16V
C7330
C7342
330UF
20%
CRITICAL
2.5V POLY-TANT CASE-D2E-SM
2
1
C7341
1
2
10UF
6.3V X5R 603
20%
C7302
1
2
6.3V X5R
10UF
20% 603
R7310
1
2
402
10.7K
1/16W
1% MF-LF
R7307
1 2
4.7
5% 1/16W MF-LF 402
XW7300
1 2
SM
R7321
1
402
1/16W
0.1%
20K
MF
2
R7322
1 2
MF 402
0.1%
20K
1/16W
C7303
1 2
5%
NO STUFF
50V
100PF
CERM 402
C7301
1
2
10UF
X5R 603
20%
6.3V
10%
C7340
1 2
0.033UF
16V 402
X5R
CRITICAL
C7307
1
2
X5R-CERM
20%
22UF
6.3V 603
CRITICAL
C7308
1
2
20%
22UF
X5R-CERM
6.3V 603
X5R
C7300
1 2
402-1
1UF
10V
10%
1
2
CASE-C2-SM1
POLY-TANT
CRITICAL
2.5V
20%
330UF
C7343
CRITICAL
Q7320
SI7110DN
PWRPK-1212-8-HF
21 3
4
5
CRITICAL
Q7321
SI7108DN
PWRPK-1212-8-HF
21 3
4
5
R7399
100K
1/16W
1 2
402
MF-LF
5%
1
2
CASED2E-SM
POLY-TANT
CRITICAL
33UF
20% 16V
C7331
X5R
1UF
25V
10%
C7332
603-1
1
2
C7333
1
2
402
0.001UF
20% CERM
50V
C7344
1
2
CERM
50V
20% 402
0.001UF
XW7301
1 2
SM
XW7302
1 2
SM
XW7303
2
SM
1
SYNC_MASTER=RAYMOND
1.5V/0.75V DDR3 SUPPLY
SYNC_DATE=01/31/2008
A
109
73
051-7537
1V5S3_VDDQSNS
=PPVIN_S5_1V5S30V75S0
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=1 mm
1V5S3_DRVH
1V5S3_VTTSNS
1V5S3_VBST
1V5S3_VDDQSET
1V5S3_CS
=DDRVTT_EN
1V8S3_VBST_RC
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm
1V5S3_DRVL
MIN_LINE_WIDTH=1 mm
1V5S3_LL
MIN_NECK_WIDTH=0.25 mm
=PP5V_S3_1V5S30V75S0
=PPVTT_S3_DDR_BUF
GND_1V5S3_CSGND
=PP3V3_S3_PDCISENS
=PP0V75_S0_REG
1V5S3_V5FILT
=DDRREG_EN
GND_1V5S3_SGND
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=1.5 mm
VOLTAGE=1.5V
=PP1V5_S3_REG
DDRREG_PGOOD
65A3
27D3
8C1
26C1
8C3
8C4
8D3
8C8
64C6
8D4
64A2
Preliminary
IN
IN
IN
OUT
IN
VID0
DPRSTP*
NC
VW
COMP
FB
FB2
RBIAS
VR_TT* NTC
VR_ON PGOOD
PSI*
RTN
VSEN
DFB
DROOP
VO
OCSET
VSUM
ISEN2
VID1
VID3 VID2
VID4
VID5
VID6
PGND2
VIN VDD
PVCC
LGATE2
PHASE2
UGATE2
ISEN1
PGND1
LGATE1
UGATE1
PHASE1
BOOT1 BOOT2
3V3
VDIFF
SOFT
TPAD
GND
CLK_EN*
IMON
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
MIN_NECK_WIDTH
ERT-J0EV474J
MIN_LINE_WIDTH
(IMVP6_COMP)
FROM SMC
(IMVP6_FB)
ERT-J1VR103J
(IMVP6_VO)
MIN_LINE_WIDTH MIN_NECK_WIDTH
MPC1055LR36
1 1 0
0
0
DPRSTP*
10 1
1 0
PSI*
1 0
MPC1055LR36
DCR=0.8MOHM
1-PHASE DCM
1-PHASE DCM
1-PHASE CCM
2-PHASE CCM
(IMVP6_VSUM)
(IMVP6_ISEN2)
MIN_NECK_WIDTH
(IMVP6_PHASE1)
(IMVP6_PHASE2)
DCR=0.8MOHM
LOAD LINE SLOPE = -2.1 MV/A
MAX CURRENT = 44A
PWM FREQ. = 300 KHZ
DPRSLPVR
(IMVP6_ISEN1)
(GND)
(NC)
(IMVP6_VW)
NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY.
R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED
MIN_LINE_WIDTH
(GND)
IMVP6 CPU VCORE REGULATOR
OPERATION MODE
(IMVP6_VO)
2
1
C7400
NO STUFF
402
50V
0.0022UF
10% CERM
2
1
XW7400
OMIT
SM
21
R7400
402
MF-LF
1% 1/16W
10K
2
1
R7401
3.65K
1/16W MF-LF 402
1%
2
1
C7415
0.1UF
X5R
16V 402
10%
R7416
13.7K
1/16W
2
1
1% MF-LF
402
2
1
R7415
402
MF-LF
1/16W
11K
1%
21
R7405
MF-LF
1%
10K
1/16W 402
21
C7404
402
6.3V CERM-X5R
10%
0.22uF
2
1
R7443
MF-LF
3.65K
402
1% 1/16W
21
L7401
MPC1055-SM
0.36UH-30A-0.80MOHM
CRITICAL
21
L7400
CRITICAL
0.36UH-30A-0.80MOHM
MPC1055-SM
2
1
C7402
0.0022UF
10% 50V CERM
402
NO STUFF
2
1
C7427
402
X5R
16V
10%
0.1UF
21
R7420
5% 1/16W MF-LF 402
10
21
R7412
1/16W
10
402
MF-LF
5%
2
1
C7426
402
10%
1UF
CERM
6.3V
2
1
C7496
0.01UF
16V
10% CERM
402
21
R7421
1/16W MF-LF
10
5%
402
2
1
C7430
16V
10%
402
X5R
0.1uF
MF-LF
21
R7413
1% 1/16W
NO STUFF
1K
402
MF-LF
2
1
1K
1/16W
1%
402
R7409
2
255
MF-LF
1/16W
1%
402
R7411
1
2
1
CERM
50V
470PF
402
10%
C7414
2
1
R7414
97.6K
MF-LF
1/16W
1%
402
2
1
C7413
220PF
5% 25V
402
CERM
2
1
C7407
10% CERM
50V
0.001UF
402
1/16W
R7410
2
402
1%
1
MF-LF
6.81K
1 2
402
5.36K
MF-LF
1/16W
1%
R7417
1K
R7418
2
1
1/16W 402
1% MF-LF
2
1
C7429
5%
402
CERM
180pF
50V
2
1
C7428
402
0.22UF
6.3V
10% CERM-X5R
2
10%
0.068UF
1
C7431
402
CERM
10V
0.01UF
21
C7432
NO STUFF
10% 16V
402
CERM
C7433
0.018UF
21
X7R 402
10% 16V
MF-LF
1/16W
R7422
2
1
402
5%
0
2
1
R7423
402
5%
0
1/16W MF-LF
1
402
CERM-X5R
10.0V
10%
C7434
2
0.12UF
2
1
C7435
X5R
6.3V
20%
603
10UF
NO STUFF
4.02K
21
R7427
402
1% 1/16W MF-LF
402
21
C7410
CERM
0.01uF
NO STUFF
16V
10%
C7405
21
0.015uF
16V
10%
402
X7R
R7408
21
147K
1% 1/16W MF-LF 402
2
1
50V 402
CERM
10%
0.001UF
C7406
10%
CERM 402
2
1
C7416
50V
NO STUFF
0.001UF
2
1
R7430
1/16W MF-LF
1%
402
3.92K
21
C7421
10%
6.3V 402
0.22uF
CERM-X5R
21
C7403
0.22uF
10%
6.3V 402
CERM-X5R
21
R7404
MF-LF 402
1
5% 1/16W
21
R7407
402
MF-LF
1/16W
1
5%
2
1
R7431
CRITICAL
10KOHM-5%
0603-LF
1% 1/16W
2
1
R7445
402
499
MF-LF
CRITICAL
21
R7426
NO STUFF
470K
402
21
R7425
402
0
5% 1/16W MF-LF
21
402
MF-LF
0
5% 1/16W
R7424
NO STUFF
R7406
0
21
1/16W 402
MF-LF
5%
33UF
16V
CRITICAL
20%
C7409
POLY-TANT CASED2E-SM
2
1
33UF
20% 16V
CRITICAL
C7417
POLY-TANT CASED2E-SM
2
1
CRITICAL
20%
33UF
16V
C7401
POLY-TANT CASED2E-SM
2
1
CRITICAL
20%
33UF
16V
C7408
POLY-TANT CASED2E-SM
2
1
2
1
603-1
10% 25V
1UF
X5R
C7418
2
1
603-1
C7411
X5R
10% 25V
1UF
31 2
5
4
LFPAK-HF
CRITICAL
RJK0305DPB
Q7400
321
4
5
Q7401
CRITICAL
RJK0328DPB
LFPAK-HF
1 2 3
5
4
LFPAK-HF
RJK0305DPB
CRITICAL
Q7402
321
4
5
Q7403
CRITICAL
LFPAK-HF
RJK0328DPB
14
ISL9504BCRZ
21
3
CRITICAL
U7400
9
19
5
44
18
20
43 42 41 40 39 38 37
13
22
27
35
49
7
15
4
31
2
28
34
1
29
33
8
6
25
30
32
23
24
12 11
16
46 45
17
10
47
26
36
48
QFN
21
R7452
402
MF-LF
1/16W
1%
10K
NO STUFF
10K
21
R7451
1%
402
MF-LF
1/16W
NO STUFF
R7447
2
1
402
2.0K
5% 1/16W
MF-LF
2
1
50V
0.001UF
20% 402
CERM
C7420
2
1
C7419
CERM
402
20%
0.001UF
50V
CERM
20%
0.001UF
50V
C7422
2
1
402
50V
0.001UF
20%
CERM
2
1
402
C7423
SYNC_DATE=01/31/2008
051-7537
74
109
A
IMVP6 CPU VCore Regulator
SYNC_MASTER=RAYMOND
IMVP6_PHASE2
1.5 MM
0.25 MM
IMVP6_LGATE1
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.25 MM
PPVIN_S5_IMVP6_VIN
IMVP6_VSUM
IMVP6_FB2 IMVP6_FB
IMVP6_VW
GND_IMVP6_SGND
VOLTAGE=0V
IMVP6_OCSET
IMVP6_DROOP
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V
PP5V_S0_IMVP6_VDD
=PP5V_S0_CPU_IMVP
IMVP6_RTN
CPU_VCCSENSE_N
IMVP6_DFB
IMVP6_ISEN2
=PP3V3_S0_IMVP
0.25 MM 0.25 MM
IMVP6_ISEN1
IMVP6_VDIFF_RC
IMVP6_VDIFF
IMVP6_RBIAS
=PPVCORE_S0_CPU_REG
IMVP6_COMP
0.25 MM 0.25 MM
IMVP6_PHASE2
CPU_DPRSTP_L
CPU_VID<2>
IMVP_VR_ON
IMVP_DPRSLPVR
IMVP6_ISEN1
=PPVIN_S5_CPU_IMVP
IMVP6_VSUM
0.20 MM0.25 MM
0.20 MM0.25 MM
IMVP6_FB
0.20 MM0.25 MM
IMVP6_VDIFF
0.20 MM0.25 MM
IMVP6_RBIAS
0.25 MM 0.20 MM
IMVP6_VO
0.50 MM 0.20 MM
GND_IMVP6_SGND
IMVP6_BOOT1_RC
IMVP6_BOOT1
0.25 MM 0.25 MM
IMVP6_BOOT1
0.25 MM
1.5 MM
IMVP6_UGATE1
IMVP6_LGATE1
IMVP6_UGATE1
IMVP6_BOOT2
IMVP6_NTC_R
CPU_VCCSENSE_P
CPU_PROCHOT_L
IMVP6_VO_R
0.20 MM0.25 MM
IMVP6_COMP
0.25 MM
IMVP6_FB2
0.20 MM
IMVP6_BOOT2
0.25 MM0.25 MM
0.20 MM
IMVP6_OCSET
0.25 MM
IMVP6_LGATE2
0.25 MM 0.25 MM
IMVP6_UGATE2
0.25 MM0.25 MM
IMVP6_BOOT2_RC
VR_PWRGOOD_DELAY
PM_DPRSLPVR
CPU_VID<4> CPU_VID<3>
=PPVIN_S5_CPU_IMVP
CPU_VID<6> CPU_VID<5>
IMVP6_COMP_RC
=PPVIN_S5_CPU_IMVP
0.25 MM
1.5 MM
IMVP6_PHASE1
IMVP6_VSEN
IMVP6_VO
IMVP6_LGATE2
IMVP6_UGATE2
IMVP6_PHASE1
GND_IMVP6_SGND
IMVP6_VR_TT
CPU_PSI_L
IMVP6_SOFT
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.25 MM
PP3V3_S0_IMVP6_3V3
CPU_VID<0>
CPU_VID<1>
IMVP6_NTC
IMVP6_IMON
IMVP6_ISEN2
0.25 MM 0.25 MM
IMVP6_VW
0.25 MM0.25 MM
IMVP6_RTN
0.25 MM 0.25 MM
0.25 MM0.25 MM
IMVP6_VSEN
0.20 MM0.25 MM
IMVP6_DROOP
0.20 MM
IMVP6_DFB
0.25 MM
0.20 MM0.25 MM
IMVP6_SOFT
71B3
71B3
14A3
60D8
40D4
60D4
60D8
60C8
71A3
10B2
71A3
60D4
60C8
71A3
14B6
71B3
71A3
71A3
60C2
71A3
71A3
60C2
60B7
71A3
71A3
60A6
60C6
60A4
60A4
60A4
60A4
60A4
60A4
60A4
8D5
60A4
11A5
60A4
60A6
8C5
60C6
60A4
60A4
8D8
60A4
60C6
9B2
11B6
39C8
71B3 60A8
8C1
60C6
60B7
60B7
60B7
60B6
60B7
60A8
60C6
60C6
60A8
60A8
60A6
11A5
10C5
60B7
60B7
60C6
60B6
60C6
60C6
26A8
21C7
11B6
11B6
8C1
11B6
11B6
8C1
60C6
60A4
60A4
60A6
60A6
60A8
60A4
10A2
60A4
11B6
11B6
44B3
60C6
60B7
60B6
60B5
60B6
60B6
60C7
Preliminary
D
SG
D
SG
IN OUT OUT IN
IN IN IN
S
D
G
S
D
G
D
G S
LDOREFIN
LDO
PGND
GND
TONSEL
EN_LDO V5DRV1
VBST1
DRVL1
VSW
EN1
LL1
DRVH1
VOUT1
TRIP1 SKIPSEL
VBST2 DRVH2
LL2 DRVL2 VOUT2
EN2
THRM_PAD
VIN
VFB1
TRIP2
REFIN2
PGOOD2
PGOOD1
VREF2
V5DRV
VREF3
V5FILT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
(MCPCORES0_UGATE)
(=P5VLTS3_EN)
<Rc> <Rd>
<Ra>
Rev A01 Production
VID<2:0> Voltage Voltage MCP Target
MCP VCORE/5V_S3 LEFT REGULATOR
MCP79 Rev A01 requires higher core & analog voltage
7A MAX OUTPUT
FREQ = 400 KHZ
VOUT = 5V
(P5VLTS3_LGATE)
(=P5VLTS3_EN)
(=PP5VLT_S3_REG)
CONNECTING IT TO AFTER SENSE RESISTOR INSTEAD OF BEFORE
PLACE C7565 AND C7568 ONE CLOSE TO U7500 AND ANOTHER CLOSE TO MCP.
(Q7560 Limit)
Max Current: 25A?
Vout = See below
(P5VLTS3_UGATE)
111 +0.876V +0.719V +0.70V
<Re>
<Ra>
Vout = 2.0V * Req / (Ra + Req)
(MCPCORES0_PHASE)
Added C7568 bulk cap on output.
Tied TON to REF. Changed Q7510 to 376S0674. C7500 changed to 138S0638.
L7560 changed from T18 MLB inductor to 152S0782.
Changed Q7565 to 376S0637.
000 +1.224V +1.060V +1.05V
110 +0.913V +0.752V +0.75V
M97 DIFFERENCES FROM LAST SYNC ON 12/05/07 TO T18 MLB:
C7568 NEEDS TO BE PLACE CLOSE TO LOAD SIDE
FREQ = 300 KHZ
Req = Rb || Rc || Rd || Re
Vout = 0.7V * (1 + Ra / Rb)
<Rb>
(MCPCORES0_LGATE)
<Rb>
101 +0.952V +0.789V +0.80V
010 +1.101V +0.937V +0.95V
001 +1.159V +0.994V +1.00V
(P5VLTS3_BOOT)
Max load 100mA
(P5VLTS3_PHASE)
(Q7510 LIMIT)
100 +0.995V +0.830V +0.85V
011 +1.049V +0.885V +0.90V
Changed R7514 to 280K, R7564 to 180K.
(Internal 10-ohm path
(SGND)
Max load 50uA
from PVCC to VCC)
REGULATE TO AFTER SENSE RES
2
1
C7569
50V CERM
10%
0.0027UF
402
10% 25V
603-1
X5R
1UF
C7561
1
2
CRITICAL
C7560
33UF
16V
20%
POLY-TANT
CASED2E-SM
2
1
RJK0305DPB
CRITICAL
Q7560
5
4
1 2 3
LFPAK-HF
CERM
1UF
6.3V
402
10%
C7501
2
1
C7566
X5R
20%
10UF
4V
603
2
1
CRITICAL
2.5V
20%
330UF
POLY-TANT
C7565
CASE-C2-SM
10UF
X5R
20% 4V
603
C7567
1
2
5
LFPAK-HF
RJK0328DPB
Q7565
4
1 2 3
CRITICAL
MCP_PROD
R7582
1/16W MF
110K
0.1%
402
2
1
SOT563
SSM6N15FEAPE
Q7580
6
2
1
C7564
0.22UF
5%
10V 603
CERM-X7R
1
2
R7581
MCP_PROD
1/16W MF
237K
0.1%
402
2
1
SSM6N15FEAPE
3
5
4
SOT563
Q7580
R7580
1/16W
MCP_PROD
MF
475K
0.1%
402
2
1
10V
0.1UF
20%
402
CERM
C7592
1
2
402
10V
0.1UF
20%
CERM
C7591
1
2
C7590
10V
0.1UF
20%
402
CERM
1
2
402
X5R-CERM
20%
6.3V
4.7UF
C7502
1
2
CERM
1UF
C7503
10%
6.3V
402
R7570
MCP_PROD
48.7K
MF
0.1%
402
2
1
1/16W
MCP_PROD
R7571
54.9K
1/16W
MF
0.1%
402
2
1
180K
5%
MF-LF
402
1/16W
1
2
R7530
0.1UF
402
20% 10V
C7530
1
2
CERM
SM
XW7500
1 2
1/16W
7.5K
402
5%
MF-LF
R7591
1 2
7.5K
MF-LF
5%
1/16W
402
R7590
1 2
5%
7.5K
MF-LF
402
1/16W
R7592
1 2
X5R
10%
C7500
25V
805
10UF
1
2
603-1
1UF
25V
10% X5R
1
2
C7511
CRITICAL
C7510
16V
33UF
20%
POLY-TANT
CASED2E-SM
2
1
C7514
0.1UF
10% 50V
603-1
X7R
1
2
PLACEMENT_NOTE=Place next to C7516
SM
XW7501
2
1
C7520
50V
CERM
1
2
402
5%
NO STUFF
100PF
R7521
61.9K
1/16W
1%
402
MF-LF
1
2
NO STUFF
MF-LF
1/16W
R7522
5%
0
1
2
402
64B6
64A5
64A5
64C1
21A3 21C3
21A3 21C3
21A3 21C3
10V 805
X5R
C7516
1
2
10UF
20%
MPL104-SM
0.6UH-30A-1.5MOHM
L7500
21
CRITICAL
5
4
3 12
Q7510
CRITICAL
PWRPK-1212-8-HF
SI7110DN
1
2
CASE-B2-SM
POLY-TANT
6.3V
CRITICAL
C7517
150UF
20%
1
2
CASE-B2-SM
POLY-TANT
6.3V
20%
C7515
150UF
CRITICAL
1
2
MF-LF
5%
1/16W
402
180K
R7520
L7520
CRITICAL
3.3UH
IHLP
1 2
5
4
3 12
PWRPK-1212-8-HF
PWRPK-1212-8-HF
SI7110DN
Q7511
CRITICAL
SSM3K15FV
SOD-VESM-HF
3
1
2
Q7582
402
1
2
C7518
20% 50V
0.001UF
CERM
0.001UF
402
1
2
50V CERM
C7512
20%
1
C7562
402
2
20% 50V CERM
0.001UF
50V
20%
402
C7570
CERM
0.001UF
C7568
330UF
20%
2.5V
CRITICAL
POLY-TANT CASE-C2-SM
31
12
QFN
27
20
13
16
U7500
17
26
5
19
1
28
32
6
30
23
25
29
10
15
14
9
18
4
2
22821
33
CRITICAL
3
24
7
SN0802043
11
1UF
402
2
1
10%
6.3V CERM
C7504
R7582
1
RES,MTL FILM,1/16W,100K,1,0402,SMD,LF
114S0411
MCP_A01P&MCP_A01Q
114S0458
R7580
1
RES,MTL FILM,1/16W,301K,1,0402,SMD,LF
MCP_A01P&MCP_A01Q
MCP_A01
1
R7571
114S0401
RES,MTL FILM,1/16W,78.7K,1,0402,SMD,LF
RES,MTL FILM,1/16W,40.2K,1,0402,SMD,LF
114S0373
1
MCP_A01P&MCP_A01Q
R7570
MCP_A01
1
R7570
114S0383
RES,MTL FILM,1/16W,49.9K,1,0402,SMD,LF
MCP_A01
R7580
RES,MTL FILM,1/16W,549K,1,0402,SMD,LF
1
114S0484
RES,MTL FILM,1/16W,237K,1,0402,SMD,LF
114S0447
R7581
1
MCP_A01P&MCP_A01Q
RES,MTL FILM,1/16W,84.5K,1,0402,SMD,LF
114S0404
1
R7571
MCP_A01P&MCP_A01Q
1
114S0423
RES,MTL FILM,1/16W,133K,1,0402,SMD,LF
R7582
MCP_A01
RES,MTL FILM,1/16W,274K,1,0402,SMD,LF
R7581
1
114S0454
MCP_A01
MCP VCORE REGULATOR
75
109
A
051-7537
SYNC_DATE=01/31/2008
SYNC_MASTER=RAYMOND
ISNS_PVCORES0MCP_N
=PPMCPCORE_S0_REG
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM VOLTAGE=0V
GND_MCPREG_SGND
P5VLTS3_LGATE
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE
=PP5VLT_S3_REG
MCPCORES0_REFIN
VOLTAGE=2V
PP2V_S0_MCPREG_REF
MCPCORES0_ILIM
=MCPCORES0_EN
GATE_NODE=TRUE
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
MCPCORES0_UGATE
PP5V_S0_MCPREG_VCC
VOLTAGE=5V
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
=PPVIN_S0_MCPREG_VIN
P5VLTS3_UGATE
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
GATE_NODE=TRUE
P5VLTS3_PHASE
MIN_LINE_WIDTH=0.6MM SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2MM
P5V_LT_S3_PGOOD
PP5V_S3_MCPREG_LDO
VOLTAGE=5V
MCP_VID<1>
PP5V_S3_MCPREG_LDO
PP5V_S0_MCPREG_VCC
MCP_VID1_L
P5VLTS3_VSNS
MCP_VID0_RC MCP_VID1_RC
MCP_VID2_L
=PPVCORE_S0_MCP
=PPVIN_S0_MCPCORES0
MCPCORES0_PGOOD
MCP_VID<0>
MCP_VID<2>
VOLTAGE=12.6V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
=PPVIN_S3_5VLTS3
P5VLTS3_FB
MCP_VID2_RC
MCP_VID0_L
MCPREG_VREF3
MCPCORES0_BOOT
GATE_NODE=TRUE
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
MCPCORES0_LGATE
MCPCORES0_PHASE
MIN_LINE_WIDTH=0.5 MM SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2 MM
=P5VLTS3_EN
P5VLTS3_ILIM
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
P5VLTS3_BOOT
44D7 24D8
77D3
22D5
44D8
8C8 8C4
61B6
8C1
61C6
61C5
61C5
8C8
8C1
8C1
Preliminary
S
D
G
S
D
G
THRM_PAD
VFB
TRIP
VOUT
EN_PSV
GND
PGND
V5DRV
V5FILT
DRVL
DRVH
LL
TON
VBST
PGOOD
SYM (2 OF 2)
IN
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
(=PPCPUVTT_S0_REG)
(=PPCPUVTT_S0_REG)
CPUVTT POWER SUPPLY
Place XW7600 between Pin 7 and Pin 15 of U7600.
ROUTING NOTE:
8A max output
Vout = 1.052V
<Ra>
<Rb>
(GND)
ROUTING NOTE:
(CPUVTTS0_VFB)
Place XW7601 by C7660.
Vout = 0.75V * (1 + Ra / Rb)
F = 400 KHZ
Q7620
CRITICAL
SI7110DN
PWRPK-1212-8-HF
21 3
4
5
CRITICAL
SI7108DN
4
31
PWRPK-1212-8-HF
Q7621
5
2
CASE-C2-SM
2.5V
20%
CRITICAL
2
1
C7660
330UF
POLY-TANT
X5R
20%
603
6.3V
2
1
C7665
10UF
SM
2
1
XW7665
PLACEMENT_NOTE=Place XW7665 next to L7620
402
CERM
50V
5%
100PF
2
1
NO STUFF
C7670
R7670
MF-LF
1% 1/16W
8.45K
402
2
1
402
1/16W
1%
20.0K
2
1
R7671
MF-LF
1/16W
402
1%
MF-LF
187K
2
1
R7603
X5R
1
603-1
C7695
1UF
10% 25V
2
1
2
CASED2E-SM
POLY-TANT
C7630
CRITICAL
20% 16V
33UF
0.1UF
C7603
10%
2
50V
603-1
X7R
1
C7604
6.3V
603
X5R-CERM
4.7UF
10%
2
1
TPS51117RGY_QFN14
QFN
CRITICAL
3
5
14
4
10
11
2
15
6
8
12
7
1
9
13
U7600
XW7600
SM
21
X5R
1UF
10V
402-1
1
2
C7601
10%
64C1
64A5
1
R7604
6.65K
402
MF-LF
1% 1/16W
2
1/16W
402
MF-LF
1%
301
21
R7601
50V
0.001UF
20%
CERM
402
2
1
C7696
50V
CERM
402
0.001UF
20%
2
1
C7661
SM-IHLP-1
CRITICAL
1.0UH-13A-5.6M-OHM
21
L7620
SM
2
1
XW7601
SYNC_DATE=02/08/2008
SYNC_MASTER=RAYMOND
A
051-7537
76
109
CPU VTT(1.05V) SUPPLY
=PP5V_S0_CPUVTTS0
SWITCH_NODE=TRUE
CPUVTTS0_LL
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
=PPVIN_S0_CPUVTTS0
CPUVTTS0_PGOOD
CPUVTTS0_TRIP
MIN_NECK_WIDTH=0.2MM
CPUVTTS0_VBST
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
CPUVTTS0_DRVL
GATE_NODE=TRUE
=CPUVTTS0_EN
CPUVTTS0_VOUT
CPUVTTS0_VFB
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
GND_CPUVTTS0_SGND
MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V
MIN_LINE_WIDTH=0.6 mm
PP5V_S0_CPUVTTS0_V5FILT
=PPCPUVTT_S0_REG
MIN_NECK_WIDTH=0.2MM
CPUVTTS0_DRVH
GATE_NODE=TRUE
MIN_LINE_WIDTH=0.6MM
CPUVTTS0_VSNS
CPUVTTS0_TON
65A6
8D5
8C1
8D8
Preliminary
THRM_PAD
PVINAVIN
PG
MODE
OVT FB
AGND PGND
SWEN
VI
SW
EN
FB
GND
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
MCP79 Rev A01 requires higher voltage
VOUT = 0.6V * (1 + Ra / Rb)
VOUT = 1.102V
Vout = 1.05V MAX Current = 1.5A FREQ = 1Mhz
<Ra>
<Rb>
MAX CURRENT = 200MA
INPUT RAIL IS 3.3V S0
1.8V S0 SWITCHER
MCP 1.05V_S5 AUXC SUPPLY
CRITICAL
U7750
TPS62510
5
BQA
11
1
10
2
87
4
6
9
3
0.1UF
10% X5R
402
16V
2
1
C7781
402
1
MF-LF
1
1/16W
5%
2
R7722
CRITICAL
6.3V
22UF
20% 805
CERM
2
1
C7720
50V
5% CERM
402
2
1
C7782
22PF
1 2
1V05S5_SW
2.2UH-3.25A
IHLP1616BZ-SM
L7720
CRITICAL
1% 1/16W MF-LF
R7781
MCP_PROD
392K
402
2
1
SM
21
XW7700
1
2
301K
1/16W MF-LF
1% 402
R7780
22UF
CRITICAL
20%
6.3V CERM 805
2
1
C7783
21
PCAA031B-SM
10UH-0.55A-330MOHM
CRITICAL
L7760
C7762
6.3V X5R
20%
10uF
2
1
603
10uF
20% X5R
6.3V
C7760
2
1
603
CRITICAL
SOT23-5
53
4
1
2
U7760
TPS62202
SYNC_DATE=01/23/2008
SYNC_MASTER=RAYMOND
MISC POWER SUPPLIES
109
77
051-7537
A
114S0464
1
RES,MTL FILM,1/16W,348K,1%,0402,SMD,LF
R7781
MCP_A01&MCP_A01P&MCP_A01Q
=PP3V3_S5_P1V05S5
1V05S5_FB
=PP1V05_S5_REG
=PPVIN_S0_P1V8S0
=PP1V8_S0_REG
=P1V8S0_EN
P1V8S0_SW
=P1V05_S5_EN
1V05S5_SGND
P1V05_S5_PGOOD
1V05S5_AVIN
8A3
8B4
8B5
8B8
64C1
64D6
64B1
Preliminary
OUT
D
G S
D
G S
OUT
Y
B
A
OUT
OUT
IN
OUT
SENSE
CT
VDD
GND
RESET*
MR*
IN
ADJ1
SEL
ADJ2
REF
VCC
TMR
GND
THRM_PAD
RST*
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
IN
IN
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT
Run (S0)
(PM_SLP_S3_L)
(PM_SLP_S3_L_BUF)
VOLTAGE MONITOR
OTHER S0 RAILS PGOOD
1.5V S0 AND 1.05V S0 ENABLE
3.3V_S0, 1.8V_S0 ENABLE
MCPDDR, CPUVTT,MCPCORES0 ENABLE
Power Control Signals
1
S3 ENABLE
TPS3808 MR* HAS INTERNAL PULLUP
Unused PGOOD signal
TIE TMR TO GND
NC
(S0PGOOD_PWROK)
(PM_SLP_S3_L)
(PM_S4_STATE_L)
1.5V 1.05V COMPARED TO 0.5V
TRST = 200MS
LTC2909 THRESHOLD IS 95% (3.136V)
0
0
0
PM_SLP_S3_L
1 1
PM_SLP_S4_L
0
1
1
00
State
Sleep (S3)
Soft-Off (S5)
Battery Off (G3Hot)
1
SMC_PM_G2_ENABLE
3.3V 1.05V S5 ENABLE
58A7
20%
12
10V
CERM
C7858
0.1UF
NO STUFF
402
SSM3K15FV
SOD-VESM-HF
1
2
3
Q7813
SSM3K15FV
1
2
3
SOD-VESM-HF
Q7800
R7802
1
MF-LF
2
402
5%
100K
1/16W
26A8 39D8
2
68K
R7813
1
402
5%
1/16W MF-LF
NO STUFF
10V
2
1
402
0.068UF
CERM
10%
C7813
2
1
402
C7884
NO STUFF
0.47UF
6.3V
10%
CERM-X5R
5%
R7884
MCP_A01&MCP_A01P&MCP_A01Q
MF-LF
402
1/16W
1
0
2
3
5
1
4
2
SOT665
U7859
NO STUFF
TC7SZ08AFEAPE
65A8
C7802
0.068UF
2
1
402
10% 10V CERM
NO STUFF
MF-LF
5%
5.1K
R7801
402
2 1
1/16W
63B7
61B8
R7812
0
21
402
5%
MF-LF
1/16W
NO STUFF
2
10%
0.47UF
1
402
6.3V
C7812
CERM-X5R
61B8
1
2
402
R7840
1/16W MF-LF
5%
100K
6
4
5
2
1
3
SOT23-6
U7840
TPS3808G33DBVRG4
C7840
2
1
402
20%
CERM
10V
0.1uF
2
1
402
C7841
50V
CERM
20%
0.001UF
2
1
402
6.3V
0.47UF
10%
CERM-X5R
C7801
58A2
LTC2909
U7870
8
1
7
6
3
2
5
9
4
DFN
2
1
C7870
20% 10V
0.1uF
CERM
402
100
R7859
MF-LF
1/16W
5%
402
2 1
58A5
37B7
65C8
65B8
1/16W
1
2
402
100K
MF-LF
5%
R7800
7C3
39D5
7C3
21C3 39C5 40A2
21
1/16W MF-LF
5%
R7811
5.1K
402
C7810
CERM-X5R
10%
402
6.3V
1
0.47UF
2
59B8
43B7
R7810
2
1/16W
5%
100K
1
402
MF-LF
63C4
R7883
5.1K
2
1
5% 1/16W MF-LF
402
1/16W
402
0
2
1
MF-LF
5%
R7882
33K
2
402
1
R7881
MF-LF
5%
1/16W
22K
2
402
R7880
5%
1/16W MF-LF
1
0.47UF
C7883
2
1
6.3V
10%
CERM-X5R 402
6.3V
C7882
NO STUFF
2
1
0.47UF
CERM-X5R
10%
402
C7881
2
1
402
6.3V
10%
0.47UF
CERM-X5R
C7880
2
402
0.47UF
CERM-X5R
6.3V
10%
1
62B7
7C3
21C3 34B7 39C5 41A5 68D8
R7879
1/16W
5%
MF-LF
100K
1
2
402
61B8
MF-LF
10K
402
1/16W
R7820
2
1
5%
61B8
62B7
65C4
SYNC_DATE=04/22/2008
SYNC_MASTER=YUAN.MA
POWER SEQUENCING
051-7537
109
A
78
P1V8S0_EN
MAKE_BASE=TRUE
=PBUSVSENS_EN
MAKE_BASE=TRUE
ALL_SYS_PWRGD
=PP3V42_G3H_PWRCTL
RSMRST_PWRGD
CT
=MCPCORES0_EN
=MCPDDR_EN
=CPUVTTS0_EN
=P1V8S0_EN
=P3V3S0_EN
=P5VRTS0_EN_L
P5V_LT_S3_PGOOD
CPUVTTS0_PGOOD
MCPCORES0_PGOOD
P5V3V3_PGOOD
=PP3V3_S0_PWRCTL
=P1V05_S5_EN
=DDRREG_EN
=P5VLTS3_EN
DDRREG_PGOOD
TP_DDRREG_PGOOD
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PM_G2_P1V05S5_EN
=P3V3S5_EN_L
S0PGOOD_PWROK
=PP1V05_S0_VMON
=PP1V5_S0_VMON
PM_SLP_S3_L_INVERT
MAKE_BASE=TRUE
MCPDDR_EN
MAKE_BASE=TRUE
=PP3V42_G3H_PWRCTL
MAKE_BASE=TRUE
CPUVTTS0_EN
=P3V3S3_EN
=PP3V3_S5_PWRCTL
P1V05_S5_PGOOD
=PP3V42_G3H_PWRCTL
SMC_PM_G2_EN
PM_SLP_S3_L
MCPCORES0_EN
MAKE_BASE=TRUE
=PP3V3_S5_PWRCTL
MAKE_BASE=TRUE
PM_G2_P3V3S5_EN_L
=PP3V3_S0_VMON
PM_SLP_S4_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
DDRREG_EN
MAKE_BASE=TRUE
P5VLTS3_EN
=USB_PWR_EN
P1V05S0_EN
PM_SLP_S3_L_BUF
MAKE_BASE=TRUE
64D3
64D8
64D8
64B3
64B3
64B3
64D3
64C4
8D1
39D8
8B5
59B3
8B7
8B7
8D1
8A3
63A6
8D1
8A3
8B5
Preliminary
IN
IN
D
SG
D
SG
IN
D
SG
D
SG
IN
D
G S
D
G S
SGD
D
SG
D
SG
IN
D
G
S
S
D
G
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
3.3V S3 FET
1.05V S0 FET
1.1A (EDP)
FDC655BN
N-TYPE
1.05V S0 FET
LOADING
MOSFET
RDS(ON)
CHANNEL
.
1.431 A (EDP)
26 MOHM @4.5V
FDC606P
P-TYPE
3.3V S0 FET
CHANNEL
MOSFET
RDS(ON)
LOADING
3.3V S0 FET
0.182 A (EDP)
48 mOhm @4.5V
P-TYPE
FDC638P
3.3V S3 FET
RDS(ON)
CHANNEL
MOSFET
LOADING
CKT FROM T18
81mW max power
90mA max load @ 0.9V
WILL EXIT SELF-REFRESH PREMATURELY.
NVIDIA RECOMMENDS UNPOWERING DURING SLEEP. IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE MUST GUARANTEE MEM_CKE SIGNALS ARE LOW
MCP79 DDRVTT FET
LOADING
CHANNEL
MOSFET
RDS(ON)
(1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU)
1.5V S0 FET
N-TYPE
6 MOHM @3.5V VGS
SI7108DNS
30 MOHM @4.0V VGS
5A (EDP)
1.5V S0 FET
MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT
BEFORE RAIL IS TURNED OFF, AND REMAINS LOW UNTIL AFTER RAIL TURNS BACK ON OR DIMMS
MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS LOW THROUGH VTT TERMINATION RESISTORS.
5
6
2
1
4
3
SM
FDC638P_G
Q7910
CRITICAL
C7911
0.033UF
1
2
16V X5R
10%
402
MF-LF
47K
R7910
1 2
5%
1/16W
402
1
2
5%
MF-LF
1/16W
402
R7912
10K
0.01UF
402
CERM
C7930
2
16V
10%
1
0.033UF
C7931
10%
402
X5R
16V
1
2
1/16W MF-LF
402
1 2
47K
R7930
5%
1
2
402
100K
MF-LF
1/16W
5%
R7932
64C6
64C1
10% 10V
1
2
0.068UF
C7903
402
CERM
0.1UF
10V
2
C7902
20%
1
402
CERM
1
SOT563
6
2
SSM6N15FEAPE
Q7971
402
1 2
MF-LF
1/16W
R7971
5%
47K
5%
R7901
10K
21
402
MF-LF
1/16W
402
1/16W MF-LF
1
2
R7903
100K
5%
3
Q7971
SSM6N15FEAPE
5
4
SOT563
64C1
Q7975
SSM6N15FEAPE
SOT563
6
2
1
NO STUFF
0.001UF
C7976
402
20% 50V
1
2
CERM
12
603
10
R7975
5% 1/10W MF-LF
100K
R7976
MF-LF
402
1/16W
5%
1
2
Q7975
SSM6N15FEAPE
4
5
3
SOT563
26C1 59C8
Q7903
SSM3K15FV
SOD-VESM-HF
1
2
3
Q7905
1
2
3
SOD-VESM-HF
SSM3K15FV
3
FDC606P_G
SOT-6
4
1 2 5 6
Q7930
CRITICAL
5%
402
2
1/16W
1
R7953
MF-LF
10K
NO STUFF
402
MF-LF
5%
220K
21
1/16W
R7952
NO STUFF
12
402
20%
C7952
10V
0.1UF
CERM
NO STUFF
SSM6N15FEAPE
SOT563
3
5
4
Q7951
NO STUFF
0.068UF
CERM
1
402
2
10% 10V
C7953
NO STUFF
6
2
1
SOT563
Q7951
SSM6N15FEAPE
NO STUFF
R7951
100K
MF-LF
1
1/16W
5%
402
2
NO STUFF
C7910
0.01UF
402
2
16V
10%
CERM
1
64C1
Q7953
1 2 5 63
4
FDC655BN_G
SOT6-HF
CRITICAL
NO STUFF
1 2
402
510
MF-LF
R7954
NO STUFF
5%
1/16W
1
2
805
R7955
0
MF-LF
5%
1/8W
Q7901
CRITICAL
SI7108DN
PWRPK-1212-8-HF
21 3
4
5
SYNC_MASTER=YUAN.MA
SYNC_DATE=04/04/2008
051-7537
79
109
A
POWER FETS
=PP3V3_S5_P3V3S3FET
=PP1V5_S0_FET
=PP1V05_S0_FET
P1V05_EN_L
P1V05_EN_L_RC
P1V05S0_SS
=PP5V_S3_P1V05S0FET
=PP5V_S3_MCPDDRFET
=PP3V3_S5_P3V3S0FET
=PP3V3_S5_P1V05FET
=P3V3S3_EN
MCPDDR_SS
MCPDDR_EN_L_RC
P1V05S0_RC
=PP1V05_S5_P1V05S0FET
=DDRVTT_EN
=PPVTT_S0_VTTCLAMP
VTTCLAMP_L
VTTCLAMP_EN
=PP5V_S3_VTTCLAMP
P1V05S0_EN
P3V3S3_EN_L
P3V3S3_SS
=PP3V3_S3_FET
=P3V3S0_EN
P3V3S0_SS
=PP3V3_S0_FET
=MCPDDR_EN
MCPDDR_EN_L
=PPCPUVTT_S0_REG
=PP1V5_S3_P1V5S0FET
P3V3S0_EN_L
62C2
8A3
8B8
8C8
8C3
8C3
8A3
8A3
8B3
8C7
8C3
8D4
8C6
8D8
8D3
Preliminary
D
G S
SYM_VER-1
SGD
NC
NC
NC
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
LVDS CONNECTOR:518S0650
LED BKLT I/F
LVDS I/F
LCD CONNECTOR
(LVDS DDC POWER)
C9012
1
2
10UF
20%
6.3V X5R 603
C9011
1
2
402
16V X5R
10%
0.1UF
R9002
1
2
402
MF-LF
1/16W
100K
5%
L9008
1 2
0402-LF
120-OHM-0.3A-EMI
CRITICAL
R9023
1 2
402
MF-LF
1/16W
10K
5%
Q9004
3
1
2
SSM3K15FV
SOD-VESM-HF
R9014
1
2
402
1K
MF-LF
5% 1/16W
2
1
402
0.001UF
50V
10% X7R
C9015
2
1
402
0.001UF
50V
10% X7R
C9010
L9080
1
23
4
CRITICAL
90-OHM-200MA
AMC2012-SM
Q9003
1
2
5
6
3
4
CRITICAL
FDC606P_G
SOT-6
C9009
1
2
402
0.001UF
CERM
50V
10%
J9000
31 32
33 34
1
10 11 12 13 14 15 16 17 18 19
2
20 21 22 23 24 25 26 27 28 29
3
30
4 5 6 7 8 9
CRITICAL
F-RT-SM
20474-030E-11
R9009
1
2
402
1/16W
100K
MF-LF
5%
R9008
1
2
402
1/16W MF-LF
100K
5%
L9004
1 2
0402-LF
FERR-120-OHM-1.5A
C9013
1 2
402
CERM
50V
0.0033UF
10%
051-7537
A
109
90
SYNC_MASTER=NMARTIN
LVDS CONNECTOR
SYNC_DATE=04/04/2008
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.30 MM
PP3V3_LCDVDD_SW_F
MIN_NECK_WIDTH=0.20 MM
LED_RETURN_5
LED_RETURN_1
LVDS_IG_A_CLK_F_P
LVDS_IG_A_CLK_F_N
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<0>
LVDS_IG_DDC_DATA
LVDS_IG_DDC_CLK
BKL_SYNC
LVDS_IG_A_DATA_P<1>
=PP3V3_S0_LCD
LVDS_IG_PANEL_PWR
LCDVDD_PWREN_L
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V MIN_LINE_WIDTH=0.30 MM
PP3V3_LCDVDD_SW
LCDVDD_PWREN_L_R
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
=PP3V3_S5_LCD
LED_RETURN_6
LED_RETURN_4
LED_RETURN_3
LED_RETURN_2
PPVOUT_S0_LCDBKLT
LVDS_IG_A_DATA_N<2> LVDS_IG_A_DATA_P<2>
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.25 MM
PP3V3_S0_LCD_F
VOLTAGE=3.3V
69C1
73B3
73B3
73B3
73B3
69B3
73B3
73B3
7C7
69B1
69C1
73B3
73B3
18B3
18B3
18B3
18A3
18A3
18B3
73B3
73B3
69B1
69B1
69B1
69B1
7C7
18B3
18B3
7C3
7B7
7B7
7C7
7C7
7C7
7C7
7C7
7C7
7C7
69C6
7C7
8C5
18B6
18B3
18B3
8A3
7B7
7B7
7B7
7B7
7C3
7C7
7C7
7C7
Preliminary
D
SG
D
GS
BI
BI
BI
BI
BI
BI
D
S G
IN
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
AUX CH has 100K pull up/down on the MLB)..
Display Port Interoperability spec says that sources
external adapter for pull ups on DDC lines (since DP
or sinks which do both DP and DVI must depend on the
1
SSM6N15FEAPE
SOT563
2
6
Q9300
R9301
1/16W
402
MF-LF
5%
33
21
MF-LF
R9300
402
33
1/16W
5%
21
402
16V
10%
21
C9300
X5R
0.1UF
SOD-VESM-HF
SSM3K15FV
2
1
3
Q9301
67D1
67D1
18B6 73B3
18B6 73B3
68B8 73B3
68C8 73B3
SSM6N15FEAPE
4
3
SOT563
5
Q9300
68B8
18B6
C9301
0.1UF
X5R
16V
10%
21
402
100K
402
MF-LF
1/16W
5%
2
1
R9302
1K
R9306
5%
MF-LF
402
1/16W
1
2
SYNC_DATE=04/18/2008
SYNC_MASTER=AMASON
051-7537
A
93
109
DISPLAYPORT SUPPORT
=PP5V_S0_DP_AUX_MUX
DP_IG_CA_DET
DP_CA_DET
DDC_CA_DET_LS5V_L
MAKE_BASE=TRUE
DP_IG_DDC_DATA
MAKE_BASE=TRUE
DP_IG_DDC_CLK
=MCP_HDMI_DDC_DATA
DP_ML_N<1>
MAKE_BASE=TRUE
DP_ML_P<0>
MAKE_BASE=TRUE
=MCP_HDMI_TXC_N
MAKE_BASE=TRUE
DP_ML_P<3> DP_ML_N<3>
MAKE_BASE=TRUE
=MCP_HDMI_TXD_N<1> =MCP_HDMI_TXD_P<2> =MCP_HDMI_TXD_N<2>
DP_ML_N<0>
MAKE_BASE=TRUE
DP_ML_P<1>
MAKE_BASE=TRUE
DP_ML_N<2>
MAKE_BASE=TRUE
DP_ML_P<2>
MAKE_BASE=TRUE
=MCP_HDMI_HPD
MAKE_BASE=TRUE
DP_HPD
=MCP_HDMI_DDC_CLK
=MCP_HDMI_TXD_P<1>
=MCP_HDMI_TXD_N<0>
=MCP_HDMI_TXD_P<0>
=MCP_HDMI_TXC_P
DP_AUX_CH_C_P
DP_IG_DDC_DATA
DP_AUX_CH_SW_P
DP_IG_AUX_CH_P
DP_AUX_CH_SW_N
DP_AUX_CH_C_N
DP_IG_DDC_CLK
DP_IG_AUX_CH_N
73B3
73C3
73C3
73B3
73B3
73C3
73B3
73C3
8D5
67C8
67C8
18A3
68C1
68C1
18B6
68C8
68C8
18B6
18B6
18B6 68C1
68C1
68B1
68C1
18B6 68A8
18A3
18B6
18B6
18B6
18B6
73B3
73B3
Preliminary
OUT
BI
IN
IN
IO NC NC
IO
GND
OUT
IO NC NC
IO
GND
GND
ML_LANE3N
HDMI_CEC GND ML_LANE3P
ML_LANE2P ML_LANE2N
RETURN
ML_LANE1N
GND
ML_LANE1P
DP_C_A_DET
DP_HPD
ML_LANE0P
AUX_CHP AUX_CHN DP_PWR
ML_LANE0N
GND
GND
SHIELD PINS
SM PINS
BOT ROW
TH PINS
TOP ROW
IO NC NC
IO
GND
IO NC NC
IO
GND
IN
IN
IN
IN
IN
IN
G
D
S
G
D
S
SYM_VER-2
SYM_VER-2
SYM_VER-2
SYM_VER-2
G
D
S
G
D
S
BI
IN
IN
OC*
OUT
EN
GND
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
Port Power Switch
514-0610
100K if DP_HPD is used.
down HPD input with
MCP79 requires pull
greater than or equal
down HPD input with
DP Source must pull
Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm
pull-up to DP_PWR.
(CA) has 100k
Cable Adapter
DP to DVI/HDMI
to 100K (DPv1.1a).
67D1
67C4 73B3
67D1 73C3
67D1 73B3
1
2
402
5%
1/16W
R9421
100K
MF-LF
SLP2510P8
RCLAMP0524P
D9411
CRITICAL
DP_ESD
9
10
12
3
40210% X5R
0.1uF
16V
21
C9415
1 2
X5R10%
0.1uF
16V 402
C9414
67A7
1 2
0.1uF
X5R 40216V10%
C9411
1 2
0.1uF
X5R 40210% 16V
C9410
5%
100K
1
2
402
MF-LF
R9420
1/16W
3
2 1
9
10
SLP2510P8
RCLAMP0524P
D9410
CRITICAL
DP_ESD
SC70-6-1
D9400
1
3
4
6
2 5
CRITICAL
RCLAMP0504F
DP_ESD
21
14
12
6
8
10
15
17
19
11
13
9
4
2
3
16
18
20
5
7
1
22
F-RT-THSM
DSPLYPRT-M97-2
J9400
CRITICAL
3
4
6 7
DP_ESD
CRITICAL
5
D9411
SLP2510P8
RCLAMP0524P
R9425
1
2
5%
MF-LF 402
1/16W
1M
D9410
3
5
6 7
RCLAMP0524P
CRITICAL
SLP2510P8
DP_ESD
4
C9417
1 2
0.1uF
X5R 40210% 16V
1 2
0.1uF
X5R 40210% 16V
C9416
1 2
0.1uF
X5R 40210% 16V
C9413
1 2
X5R 40210% 16V
0.1uF
C9412
67D1 73B3
67D1 73C3
67D1 73B3
67D1 73C3
C9400
CERM
0.01UF
16V
10%
402
1
2
L9400
1 2
0603
FERR-120-OHM-3A
5%
1
2
MF-LF
1/16W
402
R9423
100K
67D1 73B3
67D1 73C3
Q9440
3
5
4
SOT-363
2N7002DW-X-G
2N7002DW-X-G
Q9440
6
2
1
SOT-363
1
2
100K
MF-LF
402
1/16W
5%
R9443
MF-LF
1
5%
402
1/16W
100K
R9442
2
FL9401
TCM1210-4SM
1
2 3
4
12-OHM-100MA
12-OHM-100MA
FL9402
TCM1210-4SM
3
1
2
4
12-OHM-100MA
4
32
1
TCM1210-4SM
FL9400
4
3 2
1
TCM1210-4SM
12-OHM-100MA
FL9403
R9403
0
1/16W
5% 402
MF-LF
1 2
NO STUFF
R9401
NO STUFF
MF-LF
5%
1/16W
0
402
1 2
R9431
NO STUFF
1/16W
5%
0
MF-LF
402
1 2
R9432
0
1/16W
5% 402
MF-LF
NO STUFF
1 2
R9402
0
1/16W
5% 402
MF-LF
NO STUFF
1 2
1
R9413
0
5% 402
MF-LF
NO STUFF
2
1/16W
R9430
NO STUFF
MF-LF
4025%
1/16W
0
1 2
R9400
0
1/16W
5% 402
MF-LF
NO STUFF
1 2
2
10K
R9444
MF-LF
1
5%
402
1/16W
10K
1
2
MF-LF
402
1/16W
5%
R9445
Q9441
2N7002DW-X-G
SOT-363
4
5
3
402
1/16W
5%
R9422
MF-LF
1M
2
1
Q9441
2N7002DW-X-G
SOT-363
1
2
6
5%
1
2
MF-LF
1/16W
402
100K
R9446
20%
10UF
2
1
603
X5R
6.3V
C9480
2
1
402
10V
20%
0.1UF
C9481
CERM
20%
603
X5R
1
2
6.3V
10UF
C9485
NO STUFF
20% X5R-CERM
6.3V 603
1
2
C9486
CRITICAL
22UF
67D4 73B3
7C3
21C3 34B7 39C5 41A5 64D5
SOT23
4
2
1
CRITICAL
U9480
3
TPS2051B
5
94
109
A
051-7537
SYNC_DATE=06/30/2008
SYNC_MASTER=AMASON
DisplayPort Connector
TP_DPPWR_OC_L
=PP3V3_S0_DPCONN
DP_ML_P<3>
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V
PP3V3_S0_DPPWR
DP_ML_CONN_P<1>
DP_HPD_Q
DP_CA_DET
DP_HPD_L_Q
DP_CA_DET_Q
DP_ML_CONN_P<2>
DP_ML_C_N<1>
DP_ML_C_P<0>
DP_ML_C_N<0>
DP_ML_CONN_N<0>
DP_ML_C_P<1>
DP_ML_C_P<2>
DP_ML_C_N<2>
DP_ML_CONN_N<2>
DP_ML_CONN_N<1>
DP_ML_C_N<3>
DP_ML_N<3>
DP_ML_P<0>
DP_ML_N<0>
DP_ML_P<1>
DP_ML_N<1>
DP_ML_P<2>
DP_ML_N<2>
HDMI_CEC
DP_CA_DET_L_Q
=PP3V3_S0_DPCONN
DP_HPD
DP_ML_CONN_P<0>
DP_ML_C_P<3>
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.38 MM
PP3V3_S0_DPILIM
DP_AUX_CH_C_N
DP_AUX_CH_C_P
DP_ML_CONN_N<3>
DP_ML_CONN_P<3>
=PP3V3_S5_DP_PORT_PWR
PM_SLP_S3_L
68A8
68B8
8B5
73B3
73B3
73B3
73C3
73B3
73B3
73C3
73C3
73B3 73B3
73B3 73B3
8B5
73B3
73C3
73B3
73B3
8A3
Preliminary
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
S
D
G
IN
IN
G
D
S
N-CHN
G
P-CHN
S
D
RT
DRV
GNDA
ISEN1
ISEN2
ISEN6
ISET
ISWSEN
LPF
LRT
THRM_PAD
VIN
VSEN
ISEN3
ISEN5
ISEN4
SSTCMP
VSYNC
ENA
DIM
VREF
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
*R9702 AND R9715 PIN 1 SHOULD BE PLACED NEAR C9709 PIN 2
*Q9701, D9701, C9709, C9710, L9701, R9702, AND R9715 SHOULD ALL BE PLACED NEAR EACHOTHER.
*BOOST_FET_CNTL AND PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
*R9707, R9708, R9709, R9713, R9714, R9727, AND R9729 SHOULD AWAY FROM BOOST CIRCUIT
66B3
7B7
66B3
7B7
66B3
7B7
66B3
7B7
66B3
7B7
66B3
7B7
69B3
66B2
7C7 7C3
D9701
CRITICAL
PLACEMENT_NOTE=Place near Q9701
DFLS1100
POWERDI-123
21
70C3 69C7
21
XW9702
SM
PLACEMENT_NOTE=Place near C9709 and Q9701
1
R9702
402
1%
MF
1/6W
0.4
2
2
1
C9712
50V
5%
402
CERM
47PF
NOSTUFF
PLACEMENT_NOTE=Place near C9709 and Q9701
2
0.4
R9715
1%
402
1/6W
1
MF
CRITICAL
IHLP2525CZ-SM
21
L9701
22UH-2.5A
PLACEMENT_NOTE=Place near Q9701
MF-LF
21
R9731
1/16W
187K
1%
402
2
R9701
100
1/16W
1
402
1% MF-LF
2
1
C9713
X5R
25V
10%
0.1UF
402
PLACEMENT_NOTE=Place near C9709
4
3
6521
FDC5612
SSOT6
Q9701
NOSTUFF
2
1
402
1UF
10V
10%
X5R
C9714
C9702
1
0.1UF
X5R 402
10% 25V
2
1 2
3.01K
R9707
1%
402
PLACEMENT_NOTE=Away from Q9701
MF-LF
1/16W
R9713
PLACEMENT_NOTE=Away from Q9701
MF-LF
BKLT_PLL_NOT
21
1/16W
0
5%
402
66C2
BKLT_PLL
1/16W
0
5%
MF-LF
402
12
R9734
R9718
10.2
402
TF
0.1%
1/16W
1 2
10.2
402
TF
0.1%
1/16W
1 2
R9719
1/16W
10.2
402
TF
0.1%
1 2
R9720
10.2
402
TF
0.1%
1/16W
1 2
R9721
10.2
402
TF
0.1%
1/16W
1 2
R9722
21
1/16W
1%
402
MF-LF
30.1K
R9711
10K
2
R9710
MF-LF
1%
1/16W 402
1
70A7 18B6
NTUD3127CXXG
SOT-963
6
1
2
Q9702
CRITICAL
SOT-963
NTUD3127CXXG
CRITICAL
5
3
Q9702
4
MF-LF
2 1
402
5%
0
R9733
1/16W
R9700
1/16W
402
1% MF-LF
100K
NOSTUFF
MF-LF
2
402
2.0M
1/16W
5%
1
R9703
APP001A
CRITICAL
U9701
6
1
13
10
11
16
8
2
19
18
21
3
9
12
15
147
17
5
20
4
QFN
100
R9704
402
1/16W
1% MF-LF
21
PLACEMENT_NOTE=Away from Q9701
1 2
100K
MF-LF
R9708
402
1/16W
1%
PLACEMENT_NOTE=Away from Q9701
R9709
1%
21
1K
402
MF-LF
1/16W
2
1
402
10V
0.1UF
C9705
20%
CERM
NOSTUFF
0.0022UF
C9706
50V CERM
2
1
10%
402
C9707
BKLT_PLL
6.3V
20%
CERM
2.2UF
402-LF
1
2
R9714
BKLT_PLL
21
10K
PLACEMENT_NOTE=Away from Q9701
402
MF-LF
1/16W
5%
402
2
1
BKLT_PLL
25V X5R
10%
C9708
0.1UF
R9717
10.2
2
402
TF
0.1%
1/16W
1
CRITICAL
PLACEMENT_NOTE=Place near C9710
10%
C9709
50V X7R-CERM
4.7UF
1206
1
2
PLACEMENT_NOTE=Place near J9000
CRITICAL
10%
C9710
50V X7R-CERM
4.7UF
1206
1
2
21
R9723
1/10W
1%
603
MF-LF
1.2M
21
R9724
402
MF-LF
71.5K
1% 1/16W
1UF
X5R
10% 10V
C9703
1
2
402-1
R9705
100K
1/16W MF-LF
402
21
1%
21
R9706
MF-LF
10K
5%
1/16W 402
2
SM
1
XW9701
PLACEMENT_NOTE=Place near C9701
PLACEMENT_NOTE=Place near L9701
2
1
10%
805
X5R
25V
10UF
CRITICAL
C9701
R9727
15.0K
1 2
402
PLACEMENT_NOTE=Away from Q9701
1% 1/16W MF-LF
2
R9730
MF
1%
1/6W
402-HF
0.1
1
LCD BACKLIGHT DRIVER
SYNC_DATE=08/12/2008
SYNC_MASTER=YITE
97
051-7537
A
109
BKL_VREF_4V9
LVDS_IG_BKL_PWM
GND_BKL_PWRGND
PPVOUT_S0_LCDBKLT_SW
SWITCH_NODE=TRUE
VOLTAGE=30V MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.5 mm
LED_RETURN_6
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
LED_RETURN_5
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
LED_RETURN_4
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
LED_RETURN_3
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
BKL_VREF_4V9
BKL_LRT_RC
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.20MM
GND_BKL_PWRGND
PPVOUT_S0_LCDBKLT
LED_RETURN_2
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
MIN_LINE_WIDTH=0.5MM
PPVIN_S0_LCDBKLT_BUF
VOLTAGE=12.6V MIN_NECK_WIDTH=0.20MM
PPBUS_S0_LCDBKLT_PWR
PPBUS_S0_LCDBKLT_PWR
VOLTAGE=12.6V
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
BKL_VREF_IN_4V9
BKL_VREF_4V9
PPVOUT_S0_LCDBKLT
MIN_NECK_WIDTH=0.20 mm MIN_LINE_WIDTH=0.5 mm
VOLTAGE=30V
GND_BKL_PWRGND_X
MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.5MM
LED_RETURN_1
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.20MM
BOOST_SINK
BKL_SYNC
BKL_SSTCMP_RC
GND_BKL_PWRGND
BKL_VREF_4V9
BKL_DIM
BKLT_EN
BKL_VSYNC
BKL_ISEN4
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
BKL_ISEN5
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
BKL_ISEN3
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
BKL_VSEN
BKL_VIN
GND_BKL_PWRGND
BKL_LRT
BKL_ISET
BKL_ISEN6
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
BKL_ISEN2
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
BKL_ISEN1
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
PLACEMENT_NOTE=Place near PPVOUT_S0_LCDBKLT_SW
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.20MM
BOOST_FET_CNTL
BKL_RT
BKL_PWR_EN_L
BKLT_PWM_RC
BKL_LPF
BKL_SSTCMP
69C8
69C4
69C1
69C8
69C8
69C4
69D7
69B6
69D7
66B2
69C4
69D6
69B6
69D7
69B6
69D6
69A8
69C3
7C7
70C3
69A8
69C3
69A8
69D6
7C3
69B4
7C3
69B4
7C3
69D7
7C3
69B4
7C3
69C3
Preliminary
OUT
IN
IN
D
SG
D
SG
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
PPBUS S0 LCDBkLT FET
CHANNEL
MOSFET
.
RDS(ON)
FDC638APZ
P-TYPE
43 mOhm @4.5V
0.4 A (EDP)LOADING
0402-HF
2AMP-32V
21
F9800
69C7 69D7
1
2
402
1%
301K
R9808
MF-LF
1/16W
1
2
402
R9809
1/16W MF-LF
1%
147K
2
1
402
0.1UF
C9802
X5R
10% 16V
8C1
4
3
6521
FDC638APZ_SBMS001
Q9806
1
2
402
R9841
1K
1/16W MF-LF
5%
1
2
402
MF-LF
R9840
1K
1/16W
5%
26C1
SSM6N15FEAPE
Q9807
SOT563
2
1
6
3
4
5
SOT563
SSM6N15FEAPE
Q9807
18B6 70B7
051-7537
A
109
98
SYNC_DATE=06/30/2008
SYNC_MASTER=YITE
LCD Backlight Support
PPBUS_S0_LCDBKLT_EN_L
LVDS_IG_BKL_ON
PPBUS_S0_LCDBKLT_EN_DIV
PPBUS_S0_LCDBKLT_FUSED
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
LVDS_IG_BKL_PWM
LVDS_IG_BKL_ON
PPBUS_S0_LCDBKLT_PWR
VOLTAGE=12.6V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.4 mm
=PPBUS_S0_LCDBKLT
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
BKLT_PLT_RST_L
BKLT_EN_L
69A8
70C8
18B6
18B6
Preliminary
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
FSB 1X signals shown in signal table on right.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.
FSB 2X signals / groups shown in signal table on right.
Signals within each 4x group should be matched within 5 ps of strobe.
FSB 4X signals / groups shown in signal table on right.
DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.
FSB (Front-Side Bus) Constraints CPU / FSB Net Properties
(CPU_VCCSENSE) (CPU_VCCSENSE)
(FSB_CPURST_L)
(See above)
Signals
NET_TYPE
SPACING
FSB 1X Signals
ELECTRICAL_CONSTRAINT_SET
FSB 4X Signal Groups
FSB 2X
PHYSICAL
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.
All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
SR DG recommends at least 25 mils, >50 mils preferred
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
Most CPU signals with impedance requirements are 55-ohm single-ended.
FSB Clock Constraints
Some signals require 27.4-ohm single-ended impedance.
MCP FSB COMP Signal Constraints
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
Design Guide recommends each strobe/signal group is routed on the same layer.
NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.
Intel Design Guide recommends FSB signals be routed only on internal layers.
SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
CPU Signal Constraints
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.
=3x_DIELECTRIC
?
CLK_FSB
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF
=100_OHM_DIFF
*
CLK_FSB_100D
8 MIL
* ?
MCP_FSB_COMP
=50_OHM_SE
MCP_50S
=50_OHM_SE =50_OHM_SE=50_OHM_SE
*
=STANDARD =STANDARD
*
CPU_VCCSENSE
?
25 MIL
25 MIL
CPU_GTLREF
* ?
CPU_ITP
* ?
=2:1_SPACING
?
CPU_COMP
*
25 MIL
8 MIL
CPU_8MIL
?*
CPU_AGTL
?*
=STANDARD
=27P4_OHM_SE
=27P4_OHM_SE
*
=27P4_OHM_SE =27P4_OHM_SE
7 MIL7 MIL
CPU_27P4S
*
=STANDARD =STANDARD
CPU_50S
=50_OHM_SE =50_OHM_SE=50_OHM_SE =50_OHM_SE
=4x_DIELECTRICCLK_FSB
?
TOP,BOTTOM
CPU_AGTL
?
TOP,BOTTOM
=2x_DIELECTRIC
100 109
A
051-7537
CPU/FSB Constraints
SYNC_MASTER=T18_MLB
SYNC_DATE=01/04/2008
=50_OHM_SE=50_OHM_SE=50_OHM_SE
=50_OHM_SE
FSB_DSTB_50S
=1:1_DIFFPAIR=1:1_DIFFPAIR
*
TOP,BOTTOM
FSB_ADSTB
?
=4x_DIELECTRIC
=50_OHM_SE
*
=STANDARD
FSB_50S
=50_OHM_SE =50_OHM_SE
=STANDARD
=50_OHM_SE
TOP,BOTTOM
?
FSB_DATA
=4x_DIELECTRIC
TOP,BOTTOM
FSB_DSTB
?
=5x_DIELECTRIC
FSB_ADDR
TOP,BOTTOM
?
=3x_DIELECTRIC
FSB_1X
TOP,BOTTOM
?
=3x_DIELECTRIC
FSB_DATA
* ?
=2x_DIELECTRIC
?
FSB_DSTB
*
=3x_DIELECTRIC
=STANDARD
*
FSB_ADDR
?
=STANDARDFSB_1X
?*
FSB_ADSTB
?*
=2x_DIELECTRIC
FSB_DATA
FSB_DINV_L<0>
FSB_50S
FSB_DATA_GROUP0
FSB_LOCK_L
FSB_1XFSB_1X
FSB_50S
CPU_AGTL
CPU_A20M_L
CPU_ASYNC
CPU_50S
FSB_D_L<47..32>
FSB_DATA_GROUP2
FSB_DATA
FSB_50S
FSB_DSTB1
FSB_DSTB
FSB_DSTB_50S
FSB_DSTB_L_N<1>
FSB_ADSTB0
FSB_ADSTB_L<0>
FSB_50S
FSB_ADSTB
CPU_8MIL
CPU_50S
CPU_VID<6..0>
CPU_8MIL
IMVP6_VID<6..0>
CPU_50S
IMVP6_VSEN_P
CPU_VCCSENSE
CPU_27P4S
CPU_27P4S
IMVP6_VSEN_N
CPU_VCCSENSE
CPU_VCCSENSE_N
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE_P
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_50S CPU_ITP
XDP_CPURST_L
XDP_BPM_L<5>
CPU_ITPCPU_50S
XDP_BPM_L5
CPU_ITP
XDP_BPM_L<4..0>
CPU_50S
XDP_BPM_L
XDP_TRST_L
CPU_ITPCPU_50S
XDP_TRST_L
XDP_TCK
CPU_ITPCPU_50SXDP_TCK
XDP_TMS
CPU_ITPCPU_50SXDP_TMS
XDP_TDO
CPU_ITPCPU_50SXDP_TDO
XDP_TDI
CPU_ITPCPU_50SXDP_TDI
CPU_COMP<0>
CPU_27P4S
CPU_COMPCPU_COMP
CPU_COMP
CPU_50S
CPU_COMP<1>
CPU_COMP
CPU_COMP
CPU_27P4S
CPU_COMP<2>
CPU_COMP
CPU_COMP
CPU_COMP<3>
CPU_50S
CPU_COMP
CPU_GTLREF
CPU_50S
CPU_GTLREF
CPU_GTLREF
IMVP_DPRSLPVR
CPU_AGTL
CPU_50S
PM_DPRSLPVR
CPU_AGTL
PM_DPRSLPVR
CPU_50S
CPU_IERR_L
CPU_50S
CPU_IERR_L
FSB_CLK_MCP_N
CLK_FSB_100D
CLK_FSB
FSB_CLK_MCP
FSB_CLK_MCP_P
CLK_FSB_100D
CLK_FSB
FSB_CLK_MCP
FSB_CLK_ITP_N
CLK_FSB
CLK_FSB_100D
FSB_CLK_ITP
FSB_CLK_ITP_P
CLK_FSB_100D
CLK_FSB
FSB_CLK_ITP
CLK_FSB_100D
CLK_FSB
FSB_CLK_CPU_N
FSB_CLK_CPU
CLK_FSB_100D
CLK_FSB
FSB_CLK_CPU_P
FSB_CLK_CPU
MCP_50S
MCP_CPU_COMP_GND
MCP_CPU_COMP MCP_FSB_COMP
MCP_50S
MCP_CPU_COMP_VCC
MCP_CPU_COMP MCP_FSB_COMP
MCP_50S
MCP_BCLK_VML_COMP_GND
MCP_CPU_COMP MCP_FSB_COMP
MCP_50S
MCP_BCLK_VML_COMP_VDD
MCP_CPU_COMP MCP_FSB_COMP
CPU_AGTL
FSB_DPWR_L
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_DPRSTP_L
CPU_DPRSTP_L
CPU_50S
CPU_AGTL
CPU_DPSLP_L
CPU_FROM_SB
CPU_50S
CPU_AGTL
FSB_CPUSLP_L
FSB_CPUSLP_L
CPU_50S
CPU_8MIL
PM_THRMTRIP_L
PM_THRMTRIP_L
CPU_50S
CPU_AGTL
CPU_STPCLK_L
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_SMI_L
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_PWRGD
CPU_PWRGD
CPU_50S
CPU_AGTL
CPU_PROCHOT_L
CPU_PROCHOT_L
CPU_50S
CPU_AGTL
CPU_NMI
CPU_ASYNC_R
CPU_50S
CPU_AGTL
CPU_INTR
CPU_ASYNC_R
CPU_50S
CPU_AGTL
CPU_INIT_L
CPU_INIT_L
CPU_50S
CPU_AGTL
CPU_IGNNE_L
CPU_ASYNC
CPU_50S
CPU_8MIL
CPU_FERR_L
CPU_FERR_L
CPU_50S
CPU_AGTL
CPU_BSEL<2..0>
CPU_BSEL
CPU_50S
FSB_1X
FSB_TRDY_L
FSB_1X
FSB_50S
FSB_1X
FSB_RS_L<2..0>
FSB_1X
FSB_50S
FSB_1X
FSB_CPURST_L
FSB_CPURST_L
FSB_50S
FSB_HITM_L
FSB_1XFSB_1X
FSB_50S
FSB_1X
FSB_HIT_L
FSB_1X
FSB_50S
FSB_1X
FSB_DRDY_L
FSB_1X
FSB_50S
FSB_1X
FSB_DEFER_L
FSB_1X
FSB_50S
FSB_1X
FSB_DBSY_L
FSB_1X
FSB_50S
FSB_BPRI_L
FSB_1XFSB_1X
FSB_50S
FSB_BNR_L
FSB_1XFSB_1X
FSB_50S
FSB_1X
FSB_BREQ1_L
FSB_BREQ1_L
FSB_50S
FSB_1X
FSB_BREQ0_L
FSB_BREQ0_L
FSB_50S
FSB_ADS_L
FSB_1XFSB_1X
FSB_50S
FSB_50S
FSB_ADSTB
FSB_ADSTB1
FSB_ADSTB_L<1>
FSB_A_L<35..17>
FSB_ADDR
FSB_ADDR_GROUP1
FSB_50S
FSB_50S
FSB_ADDR
FSB_REQ_L<4..0>
FSB_ADDR_GROUP0
FSB_50S
FSB_A_L<16..3>
FSB_ADDR_GROUP0
FSB_ADDR
FSB_DSTB_L_N<3>
FSB_DSTB3
FSB_DSTB
FSB_DSTB_50S
FSB_DSTB3
FSB_DSTB
FSB_DSTB_L_P<3>
FSB_DSTB_50S
FSB_DATA
FSB_DINV_L<3>
FSB_DATA_GROUP3
FSB_50S
FSB_DATA
FSB_DATA_GROUP3
FSB_D_L<63..48>
FSB_50S
FSB_DSTB_L_N<2>
FSB_DSTB2
FSB_DSTB
FSB_DSTB_50S
FSB_DSTB2
FSB_DSTB
FSB_DSTB_L_P<2>
FSB_DSTB_50S
FSB_DATA
FSB_DINV_L<2>
FSB_DATA_GROUP2
FSB_50S
FSB_DSTB_L_P<1>
FSB_DSTB
FSB_DSTB1
FSB_DSTB_50S
FSB_DATA
FSB_DINV_L<1>
FSB_DATA_GROUP1
FSB_50S
FSB_DATA
FSB_D_L<31..16>
FSB_DATA_GROUP1
FSB_50S
FSB_DSTB_L_N<0>
FSB_DSTB
FSB_DSTB0
FSB_DSTB_50S
FSB_DSTB_L_P<0>
FSB_DSTB0
FSB_DSTB
FSB_DSTB_50S
FSB_DATA
FSB_D_L<15..0>
FSB_50S
FSB_DATA_GROUP0
13B3
13B6
13B3
10C6
10C6
10C6
13B3
60C7
60C8
14A3
14D3
14C3
10A6
10A6
10B6
10C6
10C6
14A3
40C4
14A3
40D4
14A3
14A3
10B4
13B2
14B6
14C6
14D6
14B3
14C3
14D6
14B6
14A3
14B3
14D6
14B6
60C7
60A5
60A5
13C6
13C6
6C7
6C7
6C7
10B6
10B6
27B1
60D8
14A3
14A3
14B3
14B3
14A3
10B2
14A3
14A3
14B7
14A3
14A3
13C7
14B6
10B8
10B8
14A3
14A3
14B7
10A4
14B6
14A6
10D6
14B6
14B6
14B6
14B3
14B6
14B3
14B6
10D6
14B6
14B6
14B6
14B6
14C6
14D6
14D6
14D6
10C2
14D6
14D6
14D6
14D6
14D6
10C4
14D6
14D6
14D3
10C4
10D6
10C8
10C2
10B4
10D8
11B6
11A5
11A5
13B4
10C5
10C6
6C6
6C6
6C6
6C4
6C6
10B3
10B3
10B3
10B3
10B4
60C7
21C7
10D6
14A4
14A4
13B3
13C3
10B6
10B6
14A6
14A6
14A6
14A6
10B2
9B2
10B2
10A2
10C6
10B8
10B8
10B2
10C5
9B2
9B2
10D6
10C8
10C8
9C2
10D6
10D6
9B2
10C6
10C6
10D6
10D6
10D6
10D6
10D6
14B6
9B2
10D6
10C8
10C8
10D8
10D8
10B2
10B2
10B2
10B2
10C2
10C2
10C2
10B4
10B4
10B4
10C4
10C4
10C4
Preliminary
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
DDR2:
DDR3:
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3
MCP MEM COMP Signal Constraints
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4
A/BA/cmd signals should be matched within 5 ps of CLK pairs.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
No DQS to clock matching requirement.
DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps
DQ signals should be matched within 5 ps of associated DQS pair.
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
Need to support MEM_*-style wildcards!
Memory Bus Spacing Group Assignments
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
Memory Bus Constraints
PHYSICAL
ELECTRICAL_CONSTRAINT_SET
SPACING
NET_TYPE
A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps.
All DQS pairs should be matched within 100 ps of clocks.
DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement.
DQ signals should be matched within 20 ps of associated DQS pair.
Memory Net Properties
051-7537
A
109101
Memory Constraints
SYNC_MASTER=T18_MLB
SYNC_DATE=01/04/2008
MEM_DQS
MEM_DQS2MEM
*
MEM_CLK
MEM_DQS
MEM_DQS2MEM
*
MEM_CTRL
*
MEM_DQS2MEM
MEM_DQS MEM_CMD
MEM_70D
=70_OHM_DIFF=70_OHM_DIFF
*
=70_OHM_DIFF=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
MEM_70D_VDD
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF =70_OHM_DIFF
*
=70_OHM_DIFF =70_OHM_DIFF
=40_OHM_SE=40_OHM_SE=40_OHM_SE=40_OHM_SE
=STANDARD
*
=STANDARD
MEM_40S
=40_OHM_SE
=STANDARD
*
=STANDARD
=40_OHM_SE =40_OHM_SE =40_OHM_SE
MEM_40S_VDD
?*
MEM_CMD2CMD
=1.5:1_SPACING
?*
=2:1_SPACING
MEM_CTRL2CTRL
=4:1_SPACING
?*
MEM_CLK2MEM
=2.5:1_SPACING
?*
MEM_CTRL2MEM
=1.5:1_SPACING
?*
MEM_DATA2DATA
=3:1_SPACING
?*
MEM_CMD2MEM
?*
=3:1_SPACINGMEM_DATA2MEM
?*
MEM_2OTHER
25 MIL
*
MEM_DQS2MEM
=3:1_SPACING
?
MEM_CLK
MEM_CMD2MEM
*
MEM_CMD
MEM_CTRL
MEM_CMD2MEM
MEM_CMD
*
MEM_CMD2CMD
MEM_CMDMEM_CMD
*
MEM_DATA
MEM_CMD2MEM
MEM_CMD
*
MEM_DQS
*
MEM_CMD
MEM_CMD2MEM
MEM_CLK
MEM_DATA
MEM_DATA2MEM
*
MEM_CTRL
MEM_DATA2MEM
*
MEM_DATA
MEM_DQS
*
MEM_DATA
MEM_DATA2MEM
*
MEM_DATA
MEM_DATA2DATA
MEM_DATA
MEM_CMD
*
MEM_DATA
MEM_DATA2MEM
* *
MEM_CLK
MEM_2OTHER
**
MEM_CTRL
MEM_2OTHER
* *
MEM_DQS
MEM_2OTHER
* *
MEM_CMD
MEM_2OTHER
**
MEM_DATA
MEM_2OTHER
*
MEM_CLK2MEM
MEM_CLKMEM_CLK
*
MEM_CLK2MEM
MEM_CTRL
MEM_CLK
*
MEM_CLK
MEM_CLK2MEM
MEM_CMD
MEM_CLK2MEM
MEM_CLK
*
MEM_DATA
*
MEM_CLK
MEM_CLK2MEM
MEM_DQS
*
MEM_CLK
MEM_CTRL2MEM
MEM_CTRL
MEM_CTRL
*
MEM_CTRL
MEM_CTRL2CTRL
MEM_CTRL
*
MEM_CTRL2MEM
MEM_DATA
MEM_CTRL2MEM
*
MEM_CTRL
MEM_DQS
MEM_CTRL
MEM_CTRL2MEM
*
MEM_CMD
MEM_DQS
MEM_DQS2MEM
*
MEM_DATA
*
MEM_DQS2MEM
MEM_DQS MEM_DQS
=STANDARD=STANDARD
*
MCP_MEM_COMP
Y
7 MIL 7 MIL
=STANDARD
?*
8 MIL
MCP_MEM_COMP
MEM_70D
MEM_A_DQS6
MEM_A_DQS_N<6>
MEM_DQS
MEM_A_DQS0
MEM_DQSMEM_70D
MEM_A_DQS_P<0>
MEM_DATA
MEM_A_DM<7>
MEM_A_DQ_BYTE7 MEM_40S
MEM_A_CMD
MEM_CMD
MEM_A_A<14..0>
MEM_40S_VDD
MEM_B_CMD
MEM_CMD
MEM_B_A<14..0>
MEM_40S_VDD
MEM_B_CMD
MEM_B_RAS_L
MEM_CMD
MEM_40S_VDD
MEM_B_CMD
MEM_B_CAS_L
MEM_CMD
MEM_40S_VDD
MEM_A_DQS7
MEM_A_DQS_P<7>
MEM_DQSMEM_70D
MEM_A_DQS5
MEM_A_DQS_P<5>
MEM_DQSMEM_70D
MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP
MCP_MEM_COMP_GND
MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP
MCP_MEM_COMP_VDD
MEM_70D_VDD
MEM_B_CLK_P<5..0>
MEM_CLK
MEM_B_CLK
MEM_70D_VDD
MEM_CLK
MEM_B_CLK_N<5..0>
MEM_B_CLK
MEM_B_CS_L<3..0>
MEM_B_CNTL
MEM_CTRL
MEM_40S_VDD
MEM_B_ODT<3..0>
MEM_B_CNTL
MEM_CTRL
MEM_40S_VDD
MEM_B_DQ_BYTE1
MEM_B_DM<1>
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE2
MEM_B_DM<2>
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE4
MEM_B_DM<4>
MEM_40S
MEM_DATA
MEM_B_DQS7
MEM_B_DQS_N<7>
MEM_70D MEM_DQS
MEM_B_DQ_BYTE3
MEM_B_DM<3>
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE5
MEM_B_DM<5>
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE6
MEM_B_DM<6>
MEM_40S
MEM_DATA
MEM_B_DQS3
MEM_B_DQS_P<3>
MEM_70D MEM_DQS
MEM_B_DQS0
MEM_B_DQS_P<0>
MEM_70D MEM_DQS
MEM_B_DQS0
MEM_B_DQS_N<0>
MEM_70D MEM_DQS
MEM_B_DQS1
MEM_B_DQS_N<1>
MEM_70D MEM_DQS
MEM_B_DQS1
MEM_B_DQS_P<1>
MEM_70D MEM_DQS
MEM_B_DQS2
MEM_B_DQS_P<2>
MEM_70D MEM_DQS
MEM_B_DQS2
MEM_B_DQS_N<2>
MEM_70D MEM_DQS
MEM_B_DQS4
MEM_B_DQS_P<4>
MEM_70D MEM_DQS
MEM_B_DQS3
MEM_B_DQS_N<3>
MEM_70D MEM_DQS
MEM_B_DQS5
MEM_B_DQS_N<5>
MEM_70D MEM_DQS
MEM_B_DQS4
MEM_70D
MEM_B_DQS_N<4>
MEM_DQS
MEM_B_DQS5
MEM_B_DQS_P<5>
MEM_70D MEM_DQS
MEM_B_DQS6
MEM_B_DQS_P<6>
MEM_70D MEM_DQS
MEM_B_DQ_BYTE7
MEM_B_DM<7>
MEM_40S
MEM_DATA
MEM_B_DQS7
MEM_B_DQS_P<7>
MEM_70D MEM_DQS
MEM_B_DQS6
MEM_B_DQS_N<6>
MEM_70D MEM_DQS
MEM_B_CMD
MEM_B_BA<2..0>
MEM_CMD
MEM_40S_VDD
MEM_B_DQ_BYTE0
MEM_B_DM<0>
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE0
MEM_B_DQ<7..0>
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE6
MEM_B_DQ<55..48>
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE7
MEM_B_DQ<63..56>
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE3
MEM_B_DQ<31..24>
MEM_40S
MEM_DATA
MEM_B_CMD
MEM_B_WE_L
MEM_CMD
MEM_40S_VDD
MEM_B_DQ_BYTE2
MEM_B_DQ<23..16>
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE1
MEM_B_DQ<15..8>
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE4 MEM_40S
MEM_B_DQ<39..32>
MEM_DATA
MEM_B_DQ_BYTE5
MEM_B_DQ<47..40>
MEM_40S
MEM_DATA
MEM_A_DQ<47..40>
MEM_DATA
MEM_A_DQ_BYTE5 MEM_40S
MEM_A_DQ<39..32>
MEM_DATA
MEM_A_DQ_BYTE4 MEM_40S
MEM_A_CMD
MEM_A_RAS_L
MEM_CMD
MEM_40S_VDD
MEM_DATA
MEM_A_DQ_BYTE1
MEM_A_DQ<15..8>
MEM_40S
MEM_A_DQ_BYTE2
MEM_A_DQ<23..16>
MEM_DATA
MEM_40S
MEM_CMD
MEM_A_CMD
MEM_A_WE_L
MEM_40S_VDD
MEM_DATA
MEM_A_DQ<31..24>
MEM_A_DQ_BYTE3 MEM_40S
MEM_A_CAS_L
MEM_CMD
MEM_A_CMD
MEM_40S_VDD
MEM_A_DQ_BYTE7
MEM_A_DQ<63..56>
MEM_DATA
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE6
MEM_A_DQ<55..48>
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE0
MEM_A_DQ<7..0>
MEM_40S
MEM_DATA
MEM_A_DM<0>
MEM_A_DQ_BYTE0 MEM_40S
MEM_A_BA<2..0>
MEM_A_CMD
MEM_CMD
MEM_40S_VDD
MEM_70D
MEM_A_DQS7
MEM_A_DQS_N<7>
MEM_DQS
MEM_70D
MEM_A_DQS6
MEM_A_DQS_P<6>
MEM_DQS
MEM_70D
MEM_A_DQS4
MEM_A_DQS_N<4>
MEM_DQS
MEM_A_DQS5
MEM_A_DQS_N<5>
MEM_DQSMEM_70D
MEM_A_DQS3
MEM_A_DQS_N<3>
MEM_DQSMEM_70D
MEM_A_DQS4
MEM_A_DQS_P<4>
MEM_DQSMEM_70D
MEM_70D
MEM_A_DQS2
MEM_A_DQS_N<2>
MEM_DQS
MEM_A_DQS2
MEM_A_DQS_P<2>
MEM_DQSMEM_70D
MEM_70D
MEM_A_DQS_P<1>
MEM_A_DQS1
MEM_DQS
MEM_A_DQS1
MEM_A_DQS_N<1>
MEM_DQSMEM_70D
MEM_A_DQS0
MEM_A_DQS_N<0>
MEM_DQSMEM_70D
MEM_DATA
MEM_A_DM<1>
MEM_A_DQ_BYTE1 MEM_40S
MEM_A_DQS3
MEM_A_DQS_P<3>
MEM_DQSMEM_70D
MEM_DATA
MEM_A_DM<6>
MEM_A_DQ_BYTE6 MEM_40S
MEM_A_DM<5>
MEM_DATA
MEM_A_DQ_BYTE5 MEM_40S
MEM_A_DM<4>
MEM_DATA
MEM_A_DQ_BYTE4 MEM_40S
MEM_DATA
MEM_A_DM<3>
MEM_A_DQ_BYTE3 MEM_40S
MEM_A_DM<2>
MEM_DATA
MEM_A_DQ_BYTE2 MEM_40S
MEM_CTRL
MEM_A_CS_L<3..0>
MEM_A_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_A_ODT<3..0>
MEM_A_CNTL
MEM_40S_VDD
MEM_70D_VDD
MEM_A_CLK_N<5..0>
MEM_A_CLK
MEM_CLK
MEM_A_CKE<3..0>
MEM_CTRL
MEM_A_CNTL
MEM_40S_VDD
MEM_70D_VDD
MEM_A_CLK_P<5..0>
MEM_A_CLK
MEM_CLK
MEM_B_CKE<3..0>
MEM_B_CNTL
MEM_CTRL
MEM_40S_VDD
28C4
29D4
29C4
28C2
28D4
28C7
29C7
29D2
29C2
29C4
28B4
28D2
28C5
29C5
29C7
29C7
29C7
29C7
29C4
29B7
29A7
29B4
29C2
29C4
29B7
29B7
28B7
28B7
28C4
28B2
28C4
28A7
28B7
28C4
28C7
28C7
28C7
28D7
28C7
29D7
28B7
28C2
28A7
15C5
15C1
29C5
29C7
28A5
28B5
29C5
29C5
29C5
29C5
29C2
29C2
29B5
29A5
29B4
29B7
29B5
29B2
29C2
29C2
29C4
29C4
29C4
29C4
29B7
29B2
29B5
29B7
29B5
29B7
29A7
29A5
29B7
29C5
29C4
29C2
29B5
29A5
29B2
29C7
15C3
29C2
29B5
29B5
28B5
28B5
28C5
28C2
15C7
28C7
28C2
28C7
28A5
28B5
28C2
28C4
28C5
28A5
28B7
28B7
28B5
28C4
28B7
28B2
28B2
28C4
28C4
28C2
28C2
28C4
28B5
28B7
28B5
28C2
28B4
28C5
28C5
28C5
28D5
28C5
29D5
15D5
15D5
15B7
15B5
15B1
15C1
15C1
15D5
15D5
16C6
16C6
15B1
15B1
15B1
15A1
15A3
15A3
15A3
15D1
15A3
15B3
15B3
15D1
15D1
15D1
15D1
15D1
15D1
15D1
15D1
15D1
15D1
15D1
15D1
15D1
15B3
15D1
15D1
15C1
15A3
15B3
15D3
15D3
15C3
15C1
15B3
15B3
15C3
15C3
15C7
15C7
15C5
15B7
15B7
15C5
15C7
15C5
15D7
15D7
15B7
15A7
15C5
15D5
15D5
15D5
15D5
15D5
15D5
15D5
15D5
15D5
15D5
15D5
15A7
15D5
15B7
15B7
15A7
15A7
15A7
15B5
15A5
15B5
15A5
15B5
15A1
Preliminary
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
ELECTRICAL_CONSTRAINT_SET
SPACING
Digital Video Signal Constraints
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.
SATA Interface Constraints
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.
PHYSICAL
NET_TYPE
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4
PCI-Express
I182
I183
109
A
SYNC_DATE=01/04/2008
102
051-7537
MCP Constraints 1
SYNC_MASTER=T18_MLB
?
=4X_DIELECTRIC
TOP,BOTTOM
PCIE
=100_OHM_DIFF
=100_OHM_DIFF=100_OHM_DIFF
=100_OHM_DIFF=100_OHM_DIFF
=100_OHM_DIFF
*
CLK_PCIE_100D
?
8 MIL
*
MCP_PEX_COMP
=90_OHM_DIFF=90_OHM_DIFF
=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF
=90_OHM_DIFF
*
PCIE_90D
?
8 MIL
*
SATA_TERMP
?*
SATA
=4x_DIELECTRIC
SATA
?
TOP,BOTTOM
=3x_DIELECTRIC
=100_OHM_DIFF=100_OHM_DIFF
=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF
=100_OHM_DIFF
*
LVDS_100D
=STANDARD=STANDARD
=STANDARD20 MIL20 MILY
*
MCP_DV_COMP
?
=3x_DIELECTRIC
*
DISPLAYPORT
=100_OHM_DIFF_HDD=100_OHM_DIFF_HDD
=100_OHM_DIFF_HDD=100_OHM_DIFF_HDD=100_OHM_DIFF_HDD
=100_OHM_DIFF_HDD
*
SATA_100D_HDD
?
=3x_DIELECTRIC
*
LVDS
?
=4x_DIELECTRIC
TOP,BOTTOM
DISPLAYPORT
?
=3X_DIELECTRIC
*
PCIE
?*
20 MIL
CLK_PCIE
=100_OHM_DIFF=100_OHM_DIFF
=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF
=100_OHM_DIFF
*
DP_100D
?
=4x_DIELECTRIC
TOP,BOTTOM
LVDS
=100_OHM_DIFF=100_OHM_DIFF
=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF
=100_OHM_DIFF
*
SATA_100D
DP_ML_CONN_N<3..0>
DP_100D
DISPLAYPORT
DISPLAYPORT
DP_100D
DP_ML_C_P<3..0>
DP_ML
DP_ML_N<3..0>
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_ML_C_N<3..0> DP_IG_AUX_CH_P
DP_100D
DISPLAYPORT
DP_AUX_CH
DP_IG_AUX_CH_N
DP_100D
DISPLAYPORT
DISPLAYPORT
DP_AUX_CH_SW_P
DP_100D
DP_AUX_CH_SW_N
DP_100D
DISPLAYPORT
DP_AUX_CH_C_P
DP_100D
DISPLAYPORT
DP_AUX_CH_C_N
DISPLAYPORT
DP_100D
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK
LVDS_100D
LVDS
LVDS_IG_A_CLK_N
LVDS_100D
LVDS
LVDS_IG_A_CLK
LVDS_IG_A_CLK_F_N
LVDS_100D
LVDS
LVDS_IG_A_DATA_P<2..0>
LVDS_100D
LVDS
LVDS_IG_A_DATA
LVDS_IG_A_DATA_N<2..0>
LVDS
LVDS_IG_A_DATA
LVDS_100D
MCP_IFPAB_RSET
MCP_IFPAB_RSET
MCP_DV_COMP
PCIE_FC_R2D_C_N
PCIE_90D
PCIE
PCIE_FC_D2R_P
PCIE_90D
PCIE
PCIE_FC_D2R
MCP_HDMI_RSET
MCP_HDMI_RSET
MCP_DV_COMP
MCP_HDMI_VPROBE
MCP_HDMI_VPROBE
MCP_DV_COMP
SATA_HDD_R2D_UF_N
SATA_100D_HDD
SATA
SATA_100D_HDD
SATA
SATA_HDD_R2D_N
SATA_100D_HDD
SATA
SATA_HDD_R2D_P
SATA_100D_HDD
SATA_HDD_R2D_C_N
SATA
SATA_100D_HDD
SATA_HDD_R2D_C_P
SATA
SATA_HDD_R2D
DP_ML
DP_ML_CONN_P<3..0>
DP_100D
DISPLAYPORT
DISPLAYPORT
DP_100D
DP_ML
DP_ML_P<3..0>
TMDS_IG_TXD_N<2..0>
DP_100D
TMDS_IG_TXD DISPLAYPORT
TMDS_IG_TXD_P<2..0>
DP_100D
TMDS_IG_TXD DISPLAYPORT
TMDS_IG_TXC_N
DP_100D
TMDS_IG_TXC DISPLAYPORT
TMDS_IG_TXC_P
DISPLAYPORT
DP_100D
TMDS_IG_TXC
PCIE_CLK100M_FC_P
CLK_PCIE_100D
CLK_PCIE
MCP_PE4_REFCLK
PCIE_CLK100M_MINI_CONN_N
CLK_PCIE_100D
CLK_PCIE
PCIE_CLK100M_MINI_P
CLK_PCIE_100D
MCP_PE1_REFCLK
CLK_PCIE
PCIE_FC_R2D
PCIE_FC_R2D_C_P
PCIE
PCIE_90D
PCIE_90D
PCIE_FC_R2D_N
PCIE
PCIE
PCIE_90D
PCIE_FC_R2D_P
PCIE_MINI_D2R_N
PCIE
PCIE_90D
PCIE_MINI_D2R
PCIE_MINI_D2R_P
PCIE
PCIE_90D
PCIE_90D
PCIE_MINI_R2D_C_N
PCIE
MCP_IFPAB_VPROBE
MCP_IFPAB_VPROBE
SATA_HDD_R2D_UF_P
SATA
SATA_100D_HDD
SATA
SATA_HDD_D2R_N
SATA_100D_HDD
SATA_HDD_D2R_C_P
SATA
SATA_100D_HDD
SATA
SATA_HDD_D2R_C_N
SATA_100D_HDD
SATA_HDD_D2R_UF_P
SATA
SATA_100D_HDD
SATA_ODD_R2D_C_P
SATA
SATA_100D
SATA_ODD_R2D
SATA_ODD_R2D_C_N
SATA_100D
SATA
SATA_ODD_R2D_P
SATA
SATA_100D
SATA_ODD_D2R
SATA_100D
SATA
SATA_ODD_D2R_P
SATA_100D
SATA
SATA_ODD_D2R_N
SATA_ODD_D2R_UF_P
SATA_100D
SATA
SATA
SATA_100D
SATA_ODD_D2R_C_N
SATA_ODD_R2D_UF_N
SATA
SATA_100D
SATA_ODD_R2D_UF_P
SATA
SATA_100D
SATA_ODD_R2D_N
SATA
SATA_100D
SATA_HDD_D2R
SATA
SATA_HDD_D2R_P
SATA_100D_HDD
LVDS_IG_A_CLK_F_P
LVDS_100D
LVDS
SATA_100D
SATA
SATA_ODD_D2R_C_P
SATA_ODD_D2R_UF_N
SATA
SATA_100D
SATA_HDD_D2R_UF_N
SATA
SATA_100D_HDD
MCP_SATA_TERMP
SATA_TERMP
MCP_SATA_TERMP
MCP_PEX_CLK_COMP
MCP_PEX_COMP
MCP_PEX_CLK_COMP
PCIE_90D
PCIE_MINI_R2D
PCIE
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_P
PCIE
PCIE_90D
PCIE_CLK100M_MINI_N
CLK_PCIE_100D
CLK_PCIE
PCIE_CLK100M_MINI_CONN_P
CLK_PCIE_100D
CLK_PCIE
PCIE_CLK100M_FC_N
CLK_PCIE
CLK_PCIE_100D
PCIE_90D
PCIE_FC_D2R_N
PCIE
PCIE
PCIE_90D
PCIE_MINI_R2D_N
68C5
68C8
68C4
68C1
68C7
66C2
66C2
68C5
68C8
31C7
31C7
36B5
68C3
68C7
68B1
68C2
67C7
67B7
68C8
68B8
66B3
66B3
66B2
18B3
18B3
25C6
32C6
32B5
25C7
25C7
36A7
36A7
36A3
36A3
68C4
68C1
32C5
31C8
31C5
32C6
17B6
17B6
31C5
25C6
36A3
36A7
36A7
36C2
36C2
36B5
36B2
36B2
36B5
7C5
36A3
66B2
36B5
31C5
31C7
31C5
31C8
32C5
32B5
31C7
68B3
68C2
67D1
68B2
18B6
18B6
67C6
67C5
67C4
67D4
18B3
18B3
7C7
7C7
7C7
18A3
9B5
9B5
18A6
18A6
36A5
7C5
7C5
20D6
20D6
68C3
67D1
9B5
7D5
17C3
9B5
32C5
32C5
7D5
7D5
17B3
18A3
36A5
20D6
7C5
7C5
36A5
20D6
20D6
7B7
20D6
20D6
36B4
7B7
36C4
36C4
7B7
20D6
7C7
7B7
36B4
36A5
20A6
17A6
17B3
7D5
17C3
7D5
9B5
9B5
7D5
Preliminary
8 7
PCI Bus Constraints
LAYER
PCI_55S
CLK_PCI_55S
SPACING_RULE_SET
PCI =STANDARD
CLK_PCI
D
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.
LAYER
LPC Bus Constraints
LAYER
LPC_55S
CLK_LPC_55S
SPACING_RULE_SET
LPC
CLK_LPC
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1.
LAYER
USB 2.0 Interface Constraints
LAYER
MCP_USB_RBIAS
USB_90D
SPACING_RULE_SET
USB
C
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1.
LAYER
SMBus Interface Constraints
LAYER
SMB_55S
SPACING_RULE_SET
SMB
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1.
LAYER
HD Audio Interface Constraints
LAYER
HDA_55S
SPACING_RULE_SET
HDA
MCP_HDA_COMP
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1.
SIO Signal Constraints
B
CLK_SLOW_55S
SPACING_RULE_SET
CLK_SLOW
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13.
LAYER
LAYER
LAYER
SPI Interface Constraints
LAYER
SPI_55S
SPACING_RULE_SET
SPI
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14.
LAYER
ALLOW ROUTE ON LAYER?
*
=55_OHM_SE =55_OHM_SE =55_OHM_SE
*
LINE-TO-LINE SPACING
* ?
* ?
ALLOW ROUTE ON LAYER?
*
=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE
=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE
*
LINE-TO-LINE SPACING
* ?
ALLOW ROUTE ON LAYER?
*
=90_OHM_DIFF
*
LINE-TO-LINE SPACING
* ?
ALLOW ROUTE ON LAYER?
=55_OHM_SE
*
LINE-TO-LINE SPACING
ALLOW ROUTE ON LAYER?
*
=55_OHM_SE =55_OHM_SE =55_OHM_SE=55_OHM_SE
LINE-TO-LINE SPACING
* ?
ALLOW ROUTE ON LAYER?
=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE
*
LINE-TO-LINE SPACING
*
ALLOW ROUTE ON LAYER?
*
=55_OHM_SE =55_OHM_SE =55_OHM_SE
LINE-TO-LINE SPACING
*
MINIMUM LINE WIDTH
8 MIL
MINIMUM LINE WIDTH
6 MIL
8 MIL
MINIMUM LINE WIDTH
=2x_DIELECTRIC
MINIMUM LINE WIDTH
=2x_DIELECTRIC
MINIMUM LINE WIDTH
=2x_DIELECTRIC
8 MIL
MINIMUM LINE WIDTH
8 MIL
MINIMUM LINE WIDTH
8 MIL
A
MINIMUM NECK WIDTH
=55_OHM_SE
=55_OHM_SE
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
?*
8 MIL 8 MIL
=90_OHM_DIFF =90_OHM_DIFF
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
=55_OHM_SE =55_OHM_SE =55_OHM_SE
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?
=55_OHM_SE
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?
=55_OHM_SE=55_OHM_SE
MINIMUM NECK WIDTH
MINIMUM NECK WIDTH
=90_OHM_DIFF
SPACING_RULE_SET
USB
MINIMUM NECK WIDTH
MINIMUM NECK WIDTH
MINIMUM NECK WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
=55_OHM_SE
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
=STANDARD=STANDARD
LAYER
TOP,BOTTOM
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
P
6
DIFFPAIR PRIMARY GAP
=STANDARD
=STANDARD
DIFFPAIR PRIMARY GAP
=STANDARD
=STANDARD =STANDARD
DIFFPAIR PRIMARY GAP
=STANDARD =STANDARD
=90_OHM_DIFF =90_OHM_DIFF
LINE-TO-LINE SPACING
=4x_DIELECTRIC
DIFFPAIR PRIMARY GAP
=STANDARD =STANDARD
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
=STANDARD =STANDARD
DIFFPAIR PRIMARY GAP
=STANDARD
=STANDARD
=STANDARD
=STANDARD=STANDARD
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
WEIGHT
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
l
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
=STANDARD=STANDARD
re
5
i
4
ELECTRICAL_CONSTRAINT_SET
MCP_DEBUG PCI_AD
PCI_AD24
PCI_AD PCI_AD
PCI_C_BE_L PCI_CNTL
PCI_CNTL
PCI_CNTL PCI_CNTL
PCI_CNTL
PCI_CNTL PCI_CNTL
PCI_REQ0_L
PCI_GNT0_L PCI_REQ1_L
PCI_GNT1_L PCI_INTW_L
PCI_INTX_L
PCI_INTY_L PCI_INTZ_L
MCP_PCI_CLK2
LPC_AD
LPC_FRAME_L LPC_RESET_L
MCP_LPC_CLK0
USB_EXTA
USB_CAMERA
USB_BT
USB_TPAD
USB_IR
USB_EXTB
m
MCP_USB_RBIAS
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
HDA_BIT_CLK
HDA_SYNC
HDA_RST_L
HDA_SDIN0
HDA_SDOUT
MCP_HDA_PULLDN_COMP
MCP_SUS_CLK
SPI_MOSI
SPI_MISO
PHYSICAL
PCI_55S PCI_55S
PCI_55S
PCI_55S PCI_55S
PCI_55S PCI_55S
PCI_55S
PCI_55S PCI_55S
PCI_55S
PCI_55S PCI_55S
PCI_55S
PCI_55S PCI_55S
PCI_55S PCI_55S
PCI_55S
PCI_55S PCI_55S
CLK_PCI_55S
CLK_PCI_55S
LPC_55S
LPC_55S LPC_55S
CLK_LPC_55S
CLK_LPC_55S CLK_LPC_55S
USB_90D
USB_90D
USB_90D USB_90D
USB_90D
USB_90D
USB_90D USB_90D
USB_90D
USB_90D USB_90D
USB_90D
USB_90D
i
USB_90D
USB_90D USB_90D
USB_90D
USB_90D USB_90D
USB_90D
USB_90D USB_90D
USB_90D
USB_90D
MCP_USB_RBIAS
SMB_55S
SMB_55S SMB_55S
SMB_55S
HDA_55S HDA_55S
HDA_55S
HDA_55S HDA_55S
HDA_55S
HDA_55S HDA_55S
HDA_55S
HDA_55S
CLK_SLOW_55S
CLK_SLOW_55S
SPI_55SSPI_CLK
SPI_55S SPI_55S
SPI_55S
SPI_55S SPI_55S
SPI_55S
SPI_55S SPI_55S
SPI_55SSPI_CS0 SPI_55S
SPI_55S SPI_55S
NET_TYPE
SPACING
PCI PCI
PCI
PCI PCI
PCI PCI
PCI
PCI PCI
PCI
PCI PCI
PCI
PCI PCI
PCI PCI
PCI
PCI PCI
CLK_PCI
CLK_PCI
LPC
LPC LPC
CLK_LPC
CLK_LPC CLK_LPC
USB
USB
USB USB
USB
USB
USB USB
USB
USB
n
USB
USB
USB USB
USB USB
USB
USB USB
USB
USB USB
USB
USB
SMB
SMB SMB
SMB
HDA HDA
HDA
HDA HDA
HDA
HDA HDA
HDA
HDA
MCP_HDA_COMP
CLK_SLOW
CLK_SLOW
SPI
SPI SPI
SPI
SPI SPI
SPI
SPI SPI
SPI SPI
SPI SPI
MCP_DEBUG<7..0> PCI_AD<23..8> PCI_AD<24> PCI_AD<31..25> PCI_PAR PCI_C_BE_L<3..0> PCI_IRDY_L PCI_DEVSEL_L PCI_PERR_L PCI_SERR_L PCI_STOP_L PCI_TRDY_L PCI_FRAME_L PCI_REQ0_L PCI_GNT0_L PCI_REQ1_L PCI_GNT1_L PCI_INTW_L PCI_INTX_L PCI_INTY_L PCI_INTZ_L
PCI_CLK33M_MCP_R PCI_CLK33M_MCP
LPC_AD<3..0> LPC_FRAME_L LPC_RESET_L
LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS
USB_EXTA_P USB_EXTA_N USB_EXTA_MUXED_P USB_EXTA_MUXED_N CONN_USB_EXTA_P CONN_USB_EXTA_N
USB_CAMERA_P USB_CAMERA_N USB_CAMERA_CONN_P USB_CAMERA_CONN_N USB_BT_P USB_BT_N CONN_USB2_BT_P CONN_USB2_BT_N USB_TPAD_P USB_TPAD_N USB_TPAD_R_P USB_TPAD_R_N USB_IR_P USB_IR_N USB_EXTB_P USB_EXTB_N CONN_USB_EXTB_P CONN_USB_EXTB_N
MCP_USB_RBIAS_GND
SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA
HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 HDA_SDIN_CODEC HDA_SDOUT HDA_SDOUT_R
MCP_HDA_PULLDN_COMP
PM_CLK32K_SUSCLK_R PM_CLK32K_SUSCLK
SPI_CLK_R SPI_CLK SPI_ALT_CLK SPI_MOSI_R SPI_MOSI SPI_ALT_MOSI SPI_MISO SPI_MISO_R SPI_ALT_MISO SPI_CS0_R_L SPI_CS0_L
SPI_CS1_R_L SPI_CS1_R_L_USE_MLB
3
13C3
19D7
19D2
19D7
19D2
19D7
19C5
19C5
19B3
39C8
19C3
39C8
19B3
26D4
19B3
26C4
26C1
39C8
26B1
41D3
ry
20D3
37A8
20D3
37A8
37C4
37C4
37C3
a
37C3
20D3
20D3
7D5
7D5
20C3
20C3
7C5
7C5
20D3
20D3
47B7
47B7
20D3
20D3
20C3
20C3
37A3
37A3
20B4
13B6
13B6
21C3
21C3
21D2
21A7
21C2
21A7
21A7
21D2
21D7
21D2
21A7
21C7
21B3
26B1
21B3
41A1
41C5
21B3
41B1
41C5
21B3
50C4
41B5
21B3
41B2
31B7
31B7
31B7
31B7
31B5
31B5
31B5
31B5
47B8
47B8
38C7
38C7
37A4
37A4
21C3
21C3
42C8
42C8
51C7
21D4
51C7
21C4
21D4
51B7
51C7
51C7
21D4
26B4
39C5
41A5
50C5
41D3
41A5
50C4
41D5
41A5
41D5
41B7
41D3
41D5
42D8
42D8
41C8
41C7
41B7
41D5
2 1
MCP Constraints 2
SYNC_MASTER=T18_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
APPLE INC.
SIZE
D
SCALE
NONE
051-7537
SHT
SYNC_DATE=12/14/2007
REV.
A
OF
109103
D
C
B
A
8
7 6
5
4
3
2
1
8 7
MCP RGMII (Ethernet) Constraints
LAYER
MCP_MII_COMP
ENET_MII_55S
SPACING_RULE_SET
MCP_BUF0_CLK
ENET_MII
D
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4
88E1116R (Ethernet PHY) Constraints
ENET_MDI_100D
SPACING_RULE_SET
ENET_MDI
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4
LAYER
LAYER
LAYER
ALLOW ROUTE ON LAYER?
=STANDARD
*
=55_OHM_SE
*
LINE-TO-LINE SPACING
* ?
ALLOW ROUTE ON LAYER?
=100_OHM_DIFF
*
LINE-TO-LINE SPACING
MINIMUM LINE WIDTH
7.5 MIL
=3:1_SPACING
12 MIL
MINIMUM LINE WIDTH
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
25 MIL
WEIGHT
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?*
MINIMUM NECK WIDTH
7.5 MIL
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
=STANDARD
=55_OHM_SE=55_OHM_SE=55_OHM_SE
MAXIMUM NECK LENGTH
6
DIFFPAIR PRIMARY GAP
=STANDARD =STANDARD
=STANDARD =STANDARD
DIFFPAIR PRIMARY GAP
5
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
=100_OHM_DIFF=100_OHM_DIFF
ELECTRICAL_CONSTRAINT_SET
MCP_MII_COMP
MCP_CLK25M_BUF0
ENET_INTR_L ENET_MDIO
ENET_MDC ENET_MII
ENET_PWRDWN_L
ENET_RXCLK
ENET_RXD ENET_RXD_STRAP
ENET_RXD
ENET_TXCLK
ENET_TXD0 ENET_TXD
ENET_TXD
ENET_MDI
4
NET_TYPE
PHYSICAL
MCP_MII_COMP MCP_MII_COMPMCP_MII_COMP
ENET_MII_55S
ENET_MII_55S ENET_MII_55S
ENET_MII_55S
ENET_MII_55S
ENET_MII_55S ENET_MII_55S
ENET_MII_55S
ENET_MII_55S ENET_MII_55S
ENET_MII_55S ENET_MII_55S
ENET_MII_55S
ENET_MII_55S
ENET_MII_55S ENET_MII_55S
ENET_MII_55S
ENET_MII_55S
ENET_MDI_100D
ENET_MDI_100D ENET_MDI_100D
ENET_MDI_100D
SPACING
MCP_BUF0_CLK
MCP_BUF0_CLKENET_MII_55S
ENET_MII ENET_MII
ENET_MII
ENET_MII ENET_MII
ENET_MII
ENET_MII ENET_MII
ENET_MII ENET_MII
ENET_MII
ENET_MII
ENET_MII ENET_MII
ENET_MII
ENET_MII
ENET_MDI
ENET_MDI ENET_MDI
ENET_MDI
MCP_MII_COMP_VDD MCP_MII_COMP_GND
MCP_CLK25M_BUF0_R RTL8211_CLK25M_CKXTAL1
ENET_INTR_L ENET_MDIO ENET_MDC ENET_PWRDWN_L
ENET_CLK125M_RXCLK_R ENET_CLK125M_RXCLK ENET_RXD_R<3..0> ENET_RXD<0> ENET_RXD<3..1> ENET_RX_CTRL ENET_RXCTL_R
ENET_CLK125M_TXCLK_R ENET_CLK125M_TXCLK ENET_TXD<0> ENET_TXD<3..1> ENET_TX_CTRL
ENET_RESET_L
ENET_MDI_P<3..0> ENET_MDI_N<3..0> ENET_MDI_TRAN_P<3..0> ENET_MDI_TRAN_N<3..0>
3
18C6
18C6
34A5
18C3
34A3
33B6
33B6
18C3
33B6
18C3
33C4
33C1
18D6
33C4
33B4
33C1
18D6
33B1
18D6
33C1
18D6
33B1
33B4
33C6
18D3
33C8
18D3
33C6
18D3
33B6
33C6
18C3
33B6
18C3
33B7
33B3
35B7
35C7
33B3
35B7
35C7
35B4
35C4
35C5
35B4
35C4
35C5
2 1
D
ry
C
C
a
n
i
m
B
i
B
l
re
P
A
8
7 6
5
4
3
SYNC_MASTER=T18_MLB
APPLE INC.
2
Ethernet Constraints
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
NONE
051-7537
SHT
104 109
1
SYNC_DATE=03/19/2008
REV.
A
OF
A
8 7
LAYER
1TO1_DIFFPAIR
D
ALLOW ROUTE ON LAYER?
*
MINIMUM LINE WIDTH
=STANDARD=STANDARD
MINIMUM NECK WIDTH
=STANDARD =STANDARD
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
6
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
0.1 MM 0.1 MM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
5
SMC SMBus Net Properties
ELECTRICAL_CONSTRAINT_SET
SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
4
NET_TYPE
SMB_55S SMB_55S
SMB_55S
SMB_55S SMB_55S
SMB_55S SMB_55S
SMB_55S
SMB_55S SMB_55S
PHYSICAL
SMB SMB
SMB
SMB SMB
SMB SMB
SMB
SMB SMB
SPACING
SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
3
42D2
7D5
7B5
42D2
7C5
7B5
42C2
42C2
42D5
42D5
42C5
7A7
42C5
42B5
42B5
2 1
D
SMBus Charger Net Properties
ELECTRICAL_CONSTRAINT_SET
CHGR_CSI
CHGR_CSO
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
PHYSICAL
NET_TYPE
SPACING
CHGR_CSI_P CHGR_CSI_N
CHGR_CSO_P CHGR_CSO_N
ry
C
C
a
n
i
m
B
i
B
l
re
P
A
SYNC_MASTER=T18_MLB
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE INC.
SMC Constraints
SYNC_DATE=01/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
DRAWING NUMBER
SIZE
D
SCALE
NONE
051-7537
SHT
A
REV.
A
OF
109106
8
7 6
5
4
3
2
1
8 7
LAYER
DIFFPAIR
D
ALLOW ROUTE ON LAYER?
*
MINIMUM LINE WIDTH
=STANDARD=STANDARD
MINIMUM NECK WIDTH
=STANDARD =STANDARD
MAXIMUM NECK LENGTH
6
DIFFPAIR PRIMARY GAP
0.1 MM 0.1 MM
5
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
M97 SENSOR NET PROPERTIES
ELECTRICAL_CONSTRAINT_SET
4
NET_TYPE
PHYSICAL
DIFFPAIR DIFFPAIR
DIFFPAIR
DIFFPAIR DIFFPAIR
DIFFPAIR DIFFPAIR
DIFFPAIR
DIFFPAIR DIFFPAIR
DIFFPAIR
DIFFPAIR DIFFPAIR
DIFFPAIR
DIFFPAIR DIFFPAIR
SPACING
CHGR_CSO_R_P CHGR_CSO_R_N CPUTHMSNS_D2_P CPUTHMSNS_D2_N CPU_THERMD_P CPU_THERMD_N ISNS_CPUVTT_P ISNS_CPUVTT_N ISNS_P1V5S0MCP_P ISNS_P1V5S0MCP_N ISNS_PVCORES0MCP_P ISNS_PVCORES0MCP_N MCPTHMSNS_D2_P MCPTHMSNS_D2_N MCP_THMDIODE_P MCP_THMDIODE_N
3
44A8
57B3
44A8
57B3
45C5
45C5
10C6
45D5
10C6
45D5
44B7
44B7
44C7
44C7
44D8
44D8
61C4
7C7
45B5
7C7
45B5
21C3
45C5
21C3
45B5
2 1
D
ry
C
C
a
n
i
m
B
i
B
l
re
P
A
APPLE INC.
8
7 6
5
4
3
2
M97 SPECIAL CONSTRAINTS
SYNC_MASTER=M97_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
NONE
051-7537
SHT
107 109
A
REV.
A
OF
1
8 7
M97 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS
BOARD LAYERS
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
D
C
B
LAYER
DEFAULT 0.100MM
LAYER
55_OHM_SE
50_OHM_SE
50_OHM_SE
40_OHM_SE
40_OHM_SE
27P4_OHM_SE
27P4_OHM_SE
70_OHM_DIFF
70_OHM_DIFF
70_OHM_DIFF
90_OHM_DIFF
90_OHM_DIFF
90_OHM_DIFF
100_OHM_DIFF
100_OHM_DIFF
100_OHM_DIFF
100_OHM_DIFF_HDD
100_OHM_DIFF_HDD
100_OHM_DIFF_HDD
110_OHM_DIFF
110_OHM_DIFF
110_OHM_DIFF
1:1_DIFFPAIR
TOP,BOTTOM
LAYER
TOP,BOTTOM
LAYER
TOP,BOTTOM
LAYER
TOP,BOTTOM
LAYER
ISL3,ISL4,ISL9,ISL10
TOP,BOTTOM
LAYER
ISL3,ISL4,ISL9,ISL10
TOP,BOTTOM
LAYER
ISL3,ISL4,ISL9,ISL10
TOP,BOTTOM
LAYER
ISL3,ISL4,ISL9,ISL10
TOP,BOTTOM
LAYER
ISL3,ISL4,ISL9,ISL10
TOP,BOTTOM
LAYER
ALLOW ROUTE ON LAYER?
*
*
ALLOW ROUTE ON LAYER?
*
ALLOW ROUTE ON LAYER?
*
ALLOW ROUTE ON LAYER?
*
ALLOW ROUTE ON LAYER?
ALLOW ROUTE ON LAYER?
ALLOW ROUTE ON LAYER?
*
ALLOW ROUTE ON LAYER?
*
ALLOW ROUTE ON LAYER?
* N
ALLOW ROUTE ON LAYER?
*
ALLOW ROUTE ON LAYER?
*
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y*
N*
Y
Y
N
Y
Y
N
Y
Y
Y
Y
N
Y
Y
Y
MINIMUM LINE WIDTH
=50_OHM_SE
=DEFAULT
MINIMUM LINE WIDTH
0.076 MM
MINIMUM LINE WIDTH
0.115 MM
0.076 MM 0.076 MM
MINIMUM LINE WIDTH
0.165 MM
0.126 MM
MINIMUM LINE WIDTH
0.310 MM
MINIMUM LINE WIDTH
=STANDARD
0.151 MM
0.185 MM
MINIMUM LINE WIDTH
=STANDARD =STANDARD
0.112 MM 0.112 MM
MINIMUM LINE WIDTH
=STANDARD
0.091 MM
MINIMUM LINE WIDTH
=STANDARD
0.095 MM 0.095 MM
MINIMUM LINE WIDTH
=STANDARD =STANDARD
0.075 MM 0.075 MM
0.077 MM 0.077 MM
MINIMUM LINE WIDTH
=STANDARD
MINIMUM NECK WIDTH
=DEFAULTSTANDARD
MINIMUM NECK WIDTH
0.090 MM0.090 MM
0.076 MM
MINIMUM NECK WIDTH
0.115 MM
MINIMUM NECK WIDTH
0.100 MM
0.100 MM
MINIMUM NECK WIDTH
0.310 MM
0.222 MM0.222 MM
MINIMUM NECK WIDTH
=STANDARD
0.100 MM
0.100 MM
MINIMUM NECK WIDTH
=STANDARD
0.095 MM0.095 MM
MINIMUM NECK WIDTH
=STANDARD
0.075 MM0.075 MM
0.091 MM
MINIMUM NECK WIDTH
=STANDARD
0.083 MM0.083 MM
MINIMUM NECK WIDTH
MINIMUM NECK WIDTH
=STANDARD =STANDARD
BOARD AREAS
NO_TYPE,BGA_P1MM
MAXIMUM NECK LENGTH
30 MM
12.7 MM
MAXIMUM NECK LENGTH
=STANDARD55_OHM_SE
MAXIMUM NECK LENGTH
=STANDARD
MAXIMUM NECK LENGTH
=STANDARD
MAXIMUM NECK LENGTH
=STANDARD
MAXIMUM NECK LENGTH
=STANDARD
=STANDARD
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
=STANDARD
MAXIMUM NECK LENGTH
=STANDARD
MAXIMUM NECK LENGTH
=STANDARD
MAXIMUM NECK LENGTH
6
BOARD UNITS (MIL or MM)
DIFFPAIR PRIMARY GAP
=DEFAULT
DIFFPAIR PRIMARY GAP
=STANDARD =STANDARD
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
=STANDARD
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
=STANDARD
0.200 MM 0.200 MM
DIFFPAIR PRIMARY GAP
=STANDARD
DIFFPAIR PRIMARY GAP
=STANDARD
0.244 MM 0.244 MM
DIFFPAIR PRIMARY GAP
0.400 MM 0.400 MM
0.400 MM
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
0.1 MM 0.1 MM
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
MM
0 MM0 MM
=DEFAULT
=STANDARD=STANDARD
=STANDARD
=STANDARD=STANDARD
=STANDARD
0.224 MM0.224 MM
=STANDARD
0.234 MM0.234 MM
0.220 MM0.220 MM
=STANDARD
0.230 MM0.230 MM
=STANDARD=STANDARD
0.400 MM
=STANDARD=STANDARD
0.330 MM0.330 MM
0.330 MM0.330 MM
ALLEGRO VERSION
15.5.1
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
5
TABLE_BOARD_INFO
SPACING_RULE_SET
DEFAULT
STANDARD
BGA_P1MM
BGA_P2MM =DEFAULT
BGA_P3MM
SPACING_RULE_SET
1.5:1_SPACING
2:1_SPACING
2.5:1_SPACING
3:1_SPACING
4:1_SPACING
SPACING_RULE_SET
2X_DIELECTRIC
3X_DIELECTRIC
4X_DIELECTRIC
5X_DIELECTRIC
2X_DIELECTRIC
3X_DIELECTRIC
4X_DIELECTRIC
5X_DIELECTRIC
LAYER
*
* ?
*
LAYER
*
*
*
* ?
LAYER
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
*
*
*
*
4
LINE-TO-LINE SPACING
0.1 MM
=DEFAULT
=DEFAULT
=DEFAULT
LINE-TO-LINE SPACING
0.15 MM
0.2 MM
0.25 MM
0.3 MM
0.4 MM
LINE-TO-LINE SPACING
0.140 MM
0.210 MM
0.280 MM
0.350 MM
0.126 MM
0.189 MM
0.252 MM
0.315 MM
WEIGHT
WEIGHT
WEIGHT
TABLE_SPACING_RULE_HEAD
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
MEM_CLK
CLK_FSB
CLK_LPC
CLK_PCI
CLK_PCIE
CLK_SLOW BGA_P1MM
3
**
*
*
*
*
*
*
FSB_DSTB BGA_P3MMFSB_DSTB BGA_P1MM
AREA_TYPE
BGA_P1MM BGA_P2MM
BGA_P1MM
BGA_P1MM
BGA_P1MM BGA_P2MM
SPACING_RULE_SET
BGA_P1MMBGA_P1MM
BGA_P2MM
BGA_P2MM
BGA_P2MMBGA_P1MM
BGA_P2MM
ry
2 1
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
NET_PHYSICAL_TYPE
MEM_40S
MEM_40S_VDD
AREA_TYPE
BGA_P1MM STANDARD
PHYSICAL_RULE_SET
TABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
STANDARDBGA_P1MM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
D
C
a
n
i
m
i
B
l
re
P
A
8
7 6
5
4
3
SYNC_MASTER=M97_MLB
APPLE INC.
2
M97 RULE DEFINITIONS
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
NONE
051-7537
SHT
1
A
REV.
A
OF
109109
Loading...