Apple macbook m75 Schematic

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

78

6

5

4

OROYA

3

ECN

ZONE

REV

? ??

DESCRIPTION OF CHANGE

12

CK APPD

DATE

ENG APPD

??

DATE

03/20/2007 - DVT

Date

01/17/2007

(MASTER)

03/19/2007

(MASTER)

03/19/2007

03/16/2007

09/09/2006

03/19/2007

01/23/2007

03/19/2007

03/12/2007

03/19/2007

03/12/2007

03/19/2007

(MASTER)

08/24/2006

01/17/2007

(MASTER)

D

C

B

45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

(.csa)

49

SMC

50

SMC Support

51

LPC+ Debug Connector

52

SMBus Connections

53

Current & Voltage Sensing

54

Current Sensing

55

Thermal Sensors

56

Fan Connectors

58

ALS Support

59

Sudden Motion Sensor (SMS)

61

SPI BootROM

69

PBus-In & Battery Connectors

70

Power FETs

71

IMVP6 CPU VCore Regulator

72

IMVP6 NB Gfx Core Regulator

73

5V / 3.3V Power Supply

74

1.25V / 1.05V Power Supply

75

1.8V DDR2 Supply

76

1.5V Power Supply

77

FW PHY Power Supplies

78

3.425V G3Hot Supply & Power Control

80

NV G84M PCI-E

81

NV G84M Core/FB Power

82

NV G84M Frame Buffer I/F

84

GDDR3 Frame Buffer A

85

GDDR3 Frame Buffer B

86

NV G84M GPIO/MIO/Misc

87

GPU Straps

88

NV G84M Video Interfaces

89

GPU (G84M) Core Supply

90

LVDS Display Connector

94

DVI Display Connector

95

LVDS Interface Mux

96

M75 Specific Connectors

100

CPU/FSB Constraints

101

NB Constraints

102

Memory Constraints

103

SB Constraints (1 of 2)

104

SB Constraints (2 of 2)

105

Clock & SMC Constraints

106

FireWire Constraints

107

GPU (G84M) Constraints

108

M75 Specific Constraints

109

M75 Rule Definitions

Contents Sync

T9_NOME

(MASTER)

M76_MLB

(MASTER)

M76_MLB

T9_NOME

(M59_SYNC)

M76_MLB

(MASTER)

(M59_SYNC)

T9_NOME

(MASTER)

Date

08/23/2006

(MASTER)

08/23/2006

03/16/2007

03/19/2007

12/12/2006

03/16/2007

01/17/2007

03/12/2007

03/16/2007

01/17/2007

08/24/2006

03/16/2007

08/23/2006

08/24/2006

11/14/2006

08/24/2006

03/16/2007

03/19/2007

(MASTER)

03/19/2007

Page

TABLE_TABLEOFCONTENTS_ITEM

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

(.csa)

1 N/A

Table of Contents

2

System Block Diagram

3

Power Block Diagram

4 N/A

Power Block Diagram

5 N/A

BOM Configuration

6 N/A

Revision History

7

Functional / ICT Test

8

Power Aliases

9

Signal Aliases

10

CPU FSB

11

CPU Power & Ground

12

CPU Decoupling & VID

13

eXtended Debug Port (XDP)

14

NB CPU Interface

15

NB PEG / Video Interfaces

16

NB Misc Interfaces

17

NB DDR2 Interfaces

18

NB Power 1

19

NB Power 2

20

NB Grounds

21

NB Standard Decoupling

22

NB Graphics Decoupling

23

SB Enet, Disk, FSB, LPC

24

SB PCI, PCIe, DMI, USB

25

SB Pwr Mgt, GPIO, Clink

26

SB Power & Ground

27

SB Decoupling

28

SB Misc

29

Clock (CK505)

30

Clock Termination

31

DDR2 SO-DIMM Connector A

32

DDR2 SO-DIMM Connector B

33

Memory Active Termination

34

Left I/O Board Connector

37

Ethernet (Yukon)

38

Yukon Power Control

39

Ethernet Connector

40

FireWire Link (TSB83AA22)

41

FireWire PHY (TSB83AA22)

42

FireWire Port Power

43

FireWire Ports

44

PATA Connector

46

External USB Connector

47

Left Clutch Barrel Interconnect

ContentsPage

Sync

N/A

(T9_MLB)

N/A

(MASTER)

(T9_MLB)

T9_NOME

M76_MLB

T9_NOME

M76_MLB

T9_NOME

(T9_MLB)

T9_NOME

(MASTER)

(M59_SYNC)

(T9_NOME)

(M59_SYNC)

T9_NOME

M76_MLB

(MASTER)

M76_MLB

D

C

B

TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

A

ALIASES RESOLVED

Schematic / PCB #’s

PART NUMBER

051-7225 CRITICAL 820-2101

DRAWING

TITLE=MLB

ABBREV=DRAWING

LAST_MODIFIED=Tue Mar 20 20:28:27 2007

QTY

1 1

8

DESCRIPTION

SCHEM,MLB,M75

PCBF,MLB,M75

REFERENCE DES

SCH PCB

CRITICAL

BOM OPTION

67

DIMENSIONS ARE IN MILLIMETERS

XX

X.XX

X.XXX

ANGLES

DO NOT SCALE DRAWING

THIRD ANGLE PROJECTION

5

4

3

DRAFTER

ENG APPD

QA APPD

RELEASE

METRIC

MATERIAL/FINISH

NOTED AS

APPLICABLE

DESIGN CK

MFG APPD

DESIGNER

SCALE

NONE

SIZE

2

TITLE

DRAWING NUMBER

D

Apple Computer Inc.

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SCHEM,OROYA,M75

051-7225

SHT

1

REV.

14.0.0

1

A

OF

88

78

6

5

4

3

12

U1000

CPU

2.? GHz

Core ~1.2V

Pg 10

Pg 9

D

J8000

Pg 77

x16 PCI-E

SDVO

800/1066? MHz

PEG Connector

J9400

DVI-I

U9120

J9000/10

Int Disp

Conn

C

Pg 78

J4510/20/30

GPIO

MUX

Pg 79,81

U9250/60

J9200

J9200 Source is the LVDS from the PEG based GPU.

GPIO

Pg 80

MUX

1.2 V / 1.5 GHz

SATA Conn

Pg 43

J4400

UATA Conn

Pg 42

JB200 JB300 JB400

PCI-E

B

Conns

Pg 93/4/5

100 MHz

UB100

PCI-E

MUX

Pg 92

3.3 V

6 - x1

2.5 GHz

64-Bit

Pg 14 Out

RGB

LVDS

Pg 14

SATA-0 SATA-1 SATA-2

Pg 22

Ln1 Ln2 Ln3 Ln4 Ln5 Ln6

TV

FSB

U1400

PCI-E

1.05 - 1.25V

x4 DMI

2.5 GHz

SATA

Pg 22

UATA

PCI-E

Pg 23

Pg 13

NB-GMCH

Core

Pg 17,18,19

DMI

Pg 15

DMI

Pg 23

U2300

Core

Pg 25

E-NET

Pg 22

T9 Diagram -- Needs to be updated to M75

U2900

CK 505

TERMS

Main Memory

Misc

Pg 15

CLnk 0

Pg 15

CLnk 0

Pg 24

SB-ICH8

Core 1.05V

CLnk 1

Pg 24

J1300/JD000

ITP/XDP CONN

Pg 12/103

DDR2 - Dual Channel

1.8V - 64 Bits

Pg 15/16

533/667/800? MHz

U6100/50

Boot ROM

SPI

Pg 23

PCI

Pg 23

AZALIA

Pg 22

SPI

Pg 58

GPIOsSMB LPC

USB

Pg 22Pg 24

Pg 23

Pg 24

Clocks

Pg 28

Pg 29

J3100 J3200

DIMM

Pg30,31

J4630

Connectors

6 7 8 951 2 3 4

UC500

Clocks

Pg 98

Parallel

Term

Pg 32

USB

Pg 44

DIMM’s

J3100 J3200

ReGen

J4600

Clk Gen

U2900 UC500

TERMS Pg 98

A

B,0 BSA BSB

U4900

J4710

Camera/IR

Pg 45

J6900/50

SMC

Pg 46

DC/Batt

Conn

Pg 66

Fan

ADC

J4720

Bluetooth

Power

Supply

Pg 68-76

J5810/20/90 ALS SENS Pg 55

Temp Sense

CPU GPU Right Side Charger

U5920 Sudden Motion Detect Pg 56

Power Sense Pg 51, 115-120

J5600/10/50/60, J5720/30/50

Fan Conn Pg 53, 54

Ser

U6000

Prt

Pg 45

TPM

Pg 57

U5572 U5500 U5550 U???

J5100

LPC Conn

J4700

Geyser

Trackpad/Keyboard

Pg 45

Pg 51 Pg 52 Pg 52 Pg ??

Pg 48

Linda Fnc

Prt 80, Comm 1, SMC, FWH

Pg 124-130

D

C

B

33 MHz 32-Bit

U4000

TSB82AA2

FW-Link

Pg 38

100 MHz

A

U3700

NINEVEH

E-NET

Pg 35

J3400

Mini PCI-E

AirPort

Pg 33

8

JB500

PCI-E

Conn

Pg 96

J4630

E-NET

Conn

Pg 37

67

8-Bit

U4100

TSB81BA3

FW-PHY

Pg 39

J4320 J4330

FireWire

Conn

Pg 41

JB000

PCI

Conn

Pg 91

5

U6300/1

Line In

Amp

Pg 60

U6400 U6500

Line Out

Amp 1

Pg 61

Audio Codec

Pg 59

J6800/1/2/3

Audio Conns

Pg 65

4

Line Out

Amp 2

Pg 62

U6600/10/20

Speaker

Amps

Pg 63

U????U6200

MDC

Pg ??

System Block Diagram

SYNC_MASTER=(T9_MLB)

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE COMPUTER INC.

3

2

D

SCALE

SYNC_DATE=08/23/2006

DRAWING NUMBER

051-7225

SHT

NONE

A

REV.

14.0.0

OF

2

88

1

78

6

5

4

3

12

D

C

D

C

B

Power Block Diagram

DRAWING NUMBER

NONE

SYNC_DATE=08/23/2006SYNC_MASTER=(T9_MLB)

051-7225

SHT

3

1

A

REV.

14.0.0

OF

88

A

APPLE COMPUTER INC.

8

67

5

4

3

2

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

D

SCALE

78

6

5

4

3

12

D

C

D

C

B

Power Block Diagram

A

APPLE COMPUTER INC.

8

67

5

4

3

SYNC_MASTER=N/A

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

2

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

SIZE

DRAWING NUMBER

NONE

051-7225

SHT

D

SCALE

SYNC_DATE=N/A

OF

4

1

A

REV.

14.0.0

88

BOM Variants

BOM NUMBER

630-7931 630-7932 630-8659 630-8662

PCBA,OROYA1,VRAM-HY,M75 PCBA,OROYA2,VRAM-HY,M75

BOM NAME PCBA,OROYA1,M75 PCBA,OROYA2,M75

78

M75_COMMON,EEE_X5D,CPU_2_2GHZ,FB_128_SAMSUNG M75_COMMON,EEE_X5E,CPU_2_4GHZ,FB_256_SAMSUNG

M75_COMMON,EEE_XXS,CPU_2_2GHZ,FB_128_HYNIX M75_COMMON,EEE_XXT,CPU_2_4GHZ,FB_256_HYNIX

6

BOM OPTIONS

5

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

4

3

12

M75 BOM Groups

D

BOM GROUP

M75_COMMON M75_COMMON1 M75_COMMON2

M75_DEBUG

M75_PROGPARTS

BOM GROUP

FB_128_SAMSUNG

FB_128_HYNIX

FB_256_SAMSUNG

FB_256_HYNIX

ALTERNATE,COMMON,M75_COMMON1,M75_COMMON2,M75_DEBUG,M75_PROGPARTS

EXTGPU_RST_HW,GPU_TMP401,ISL9504B,LVDS_SEL_RESUME,ONEWIRE_PU P1V8S3_1V825,SLG2AP101,SMS_MOT_DIS,YUKON_ULTRA,VGA_TERM_CONN

Bar Code Labels / EEE #’s

DESCRIPTION

LBL,P/N LABEL,PCB,28MM X 6 MM LBL,P/N LABEL,PCB,28MM X 6 MM LBL,P/N LABEL,PCB,28MM X 6 MM LBL,P/N LABEL,PCB,28MM X 6 MM

C

PART NUMBER

826-4393 826-4393 826-4393 CRITICAL

QTY

1 1 1 1

Module Parts

DESCRIPTION

IC,MDC,SR,E1,QS,2.2G,35W,800FSB,4M,BGA

IC,MDC,SR,E1,QS,2.4G,35W,800FSB,4M,BGA

IC,GPU,NV G84M,BGA

IC,NB,CRESTLINE,GM,C0,QS,965PM

IC,SB,ICH8M,B1,QS,BGA

IC,ISL9504,SYNC REG CTRL,2PHAS,QFN48,LF

IC,ISL9504B,2PH IMVP6 REG,PMON,QFN48

IC,68 PIN,CK505,LOW POWER CLOCK GENER

IC,SLG2AP101,LW PWR CLCK GEN,CK505,QFN68

IC,88E8058,GIGABIT ENET XCVR,64P QFN

IC,SMC,HS8/2116

IC,SMC,DEVELOPMENT,M75

IC,16MBIT 8-PIN SPI SERIAL FLASH,SOIC8

IC,EFI ROM,DEVELOPMENT,M75

IC,SGRAM,GDDR3,8Mx32,700MHZ,136 FBGA

IC,SGRAM,GDDR3,16Mx32,700MHZ,136 FBGA

REF DES

COMMENTS:

E&E alt to TDK/BI-Tech magnetics

ALL

Inductor alternate

ALL

TI alt to NationalALL

Murata alt to Samsung

ALL

B

PART NUMBER

337S3457 337S3458 338S0388 338S0426

QTY

1 1 1 1

1 353S1461 353S1651 ISL9504B 359S0127 CRITICAL 359S0130 338S0386

1

1 341S2004 CRITICAL 335S0384

1

333S0404 333S0409 333S0382 CRITICAL 333S0401 CRITICAL

PART NUMBER

157S0011

152S0476

138S0603

IS ALTERNATE FOR PART NUMBER

157S0030

152S0276

353S1294353S1681

138S0602

4

BOM OPTION

BOM OPTIONS

SMC_DEBUG_YES,XDP,XDP_CONN,LPCPLUS

BOOTROM_PROG,SMC_PROG

BOM OPTIONS

VRAM_128,VRAM_SAMSUNG,VRAM_128_SAMSUNG

VRAM_128,VRAM_HYNIX,VRAM_128_HYNIX

VRAM_256,VRAM_SAMSUNG,VRAM_256_SAMSUNG

VRAM_256,VRAM_HYNIX,VRAM_256_HYNIX

REFERENCE DES

[EEE:X5D] [EEE:X5E]

CRITICAL

CRITICAL CRITICAL

BOM OPTION

[EEE:XXS] [EEE:XXT]

REFERENCE DES

U1000 CPU_2_4GHZ U8000 U1400 U2300 U7100 U7100 U2900 U2900 U3700 U4900

CRITICAL826-4393

CRITICAL

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL338S0427 CRITICAL CRITICAL

CRITICAL CRITICAL CRITICAL338S0274

BOM OPTION

CPU_2_2GHZU1000

ISL9504A

SLG8LP537 SLG2AP101

U4900 U6100 U6100

U8400,U8450,U8500,U8550

TABLE_ALT_HEAD

TABLE_ALT_ITEM

CRITICAL CRITICAL341S2002

CRITICAL CRITICAL

BOOTROM_BLANK

BOOTROM_PROG

VRAM_128_SAMSUNG

VRAM_128_HYNIX

VRAM_256_SAMSUNG

VRAM_256_HYNIX

EEE_X5D EEE_X5E EEE_XXS EEE_XXT

SMC_BLANK

SMC_PROG

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

D

C

B

BOM Configuration

A

APPLE COMPUTER INC.

8

67

5

4

3

SYNC_MASTER=N/A

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

2

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

SIZE

DRAWING NUMBER

NONE

051-7225

SHT

D

SCALE

SYNC_DATE=N/A

OF

5

1

A

REV.

14.0.0

88

78

6

5

PROTO

See Perforce change notes for updates before Proto Release 12/22/06 -- Released for Proto (Schem Rev 08, PCB Rev 01)

EVT

8.1.0: 01/05/07 -- Clock Termination: Removed NO STUFF property from R3067 01/05/07 -- GPU FB: Corrected FB CLK termination (added cap and removed connection to VDDQ)

8.2.0: 01/08/07 -- GPU FB: Added VREF support for unterminated memory mode (added FETs and pulldown Rs)

D

9.0.0: 01/09/07 -- Temp Sensors: NO STUFFed C5520 (circuit should have only 1 cap) 01/12/07 -- Power Aliases: Moved Ethernet to PP3V3_S3 from S5 (layout improvements) 01/12/07 -- Power Supplies: Minor power supply feedback connection changes from M76

9.1.0: 01/17/07 -- Power Aliases: Moved LCD panel FET to PP3V3_S5 from S0 01/17/07 -- SMBus: Changed R5260 & R5261 from 4.7K to 3.3K 01/17/07 -- Sync with T9 noME (6.1.4) to pull in WOL_EN and Wake-on-Wireless support 01/17/07 -- Power FETs: Corrected BOM values for 5V/3.3V S3/S0 FETs 01/17/07 -- Power Sequencing: Added RC delay on PP1V8_S3 switcher enable 01/17/07 -- Testpoints: Removed FUNC_TEST from NB_RESET_L and FSB_DPWR_L per PCB request 01/17/07 -- BOM: Consolidated 3 caps on page 59 from 132S0120 to 132S0131 01/17/07 -- BOM: Added Hynix BOM configurations

9.2.0: 01/17/07 -- Power Aliases: Deleted alias that accidentally eliminated filtering on PP1V5_S0_SB_VCC1_5_B 01/18/07 -- Clock Termination: Changed series termination on all single ended clocks to 33 ohms 01/18/07 -- IMVP: Updated BOMOPTIONs and values for ISL9504B 01/18/07 -- Testpoints: Added NO_TEST property to LVDS_L_DATA_N<1>, _N<2>, _P<2> due to lack of layout space for TP 01/18/07 -- ODD Conn: Reconnected ODD power FET gate control circuitry to properly implement soft start (added one cap)

9.3.0: 01/19/07 -- SB Decoupling: Removed filtering for PP1V5_S0_SB_VCCGLANPLL to enable PP1V5_S0 corrections at SB 01/19/07 -- Ethernet Conn: Changed resistor short reference designators from R392x to RX392x 01/19/07 -- Clock Termination: Changed R3050 and R3055 to bypass discrete muxes for pending change to SLG2AP101 01/19/07 -- Power Sequencing: Added C7859 to create RC delay for 1.5 and 1.05V S0 rails 01/19/07 -- Power Sequencing: Changed power rail for U7850 to PP3V3_S5 to eliminate a leakage path

9.4.0:

C

01/19/07 -- GPU GPIOs: Added 2 TPs on GPIOs to make G-state externally visible 01/19/07 -- SB GPIOs: Changed SB_GPIO42 to WOW_EN and changed pullup to pulldown (T9_noME change 40787)

9.5.0: 01/22/07 -- LIO Conn: Removed unnecessary aliases as T9 reference design now matches M75 (T9_noME change 40998) 01/22/07 -- Clocks: Changed U2900 to SLG2AP101 as primary clock chip (T9_noME change 40975) 01/22/07 -- Clock Termination: Added R3051 for Silego 537/101 compatibility 01/22/07 -- BOM: Added BOMOPTIONs for SLG2AP101 (primary) and SLG8LP537 (backup) 01/22/07 -- BOM: Selected P1V8S3_1V825 BOMOPTION to lift voltage at FB memories

10.0.0: 01/23/07 -- BOM: Changed C3860/61 to 22pF from 27 pF based on -R characterization (T9_noME change 41248) 01/23/07 -- BOM: Changed FB memories to new Samsung and Hynix APNs (also added new BOMOPTIONs to GPU straps) 01/23/07 -- Released for EVT (Schem Rev 10, PCB Rev 02)

4

DVT (cont’d)

12.8.0: 03/08/07 -- Thermal Sensors: Added R5515/R5516 in case low pass filter is needed for EMC1033

13.0.0: 03/12/07 -- Power Control: Corrected alias connections for 5V/3V3 S5 enable signals

13.1.0: 03/13/07 -- BOM Options: Removed HDCP BOM option from stuffing list (feature removed) 03/14/07 -- Constraints: Constrained WWAN_SIM signals to 50 ohms 03/14/07 -- Thermal Sensors/Aliases: Changed mounting pads of Th2H sensor connector to left clutch chassis gnd

13.2.0: 03/16/07 -- Thermal Sensors: Replaced EMC1033 with second EMC1043 for improved noise filtering 03/16/07 -- NB GFX: LVDS_VREFL/VREFH changed to single pin nets to prevent LVDS glitches per Intel 03/16/07 -- Yukon Power Control: Crystal caps changed to 18pF (rdar://4946795 and rdar://4945362)

13.3.0: 03/16/07 -- Thermal Sensors: Moved remote sensor U5500 to SMC SMBus "A" and S3 power rail to clear I2C addr clash

13.4.0: 03/19/07 -- Thermal Sensors: Updated U5500 power alias to indicate device should be on S3 rail 03/19/07 -- Power Control: Added U7858 to level shift PM_G2_EN from 3.42V to 5V 03/19/07 -- Power Supplies: For 1.8, 3.3 and 5V, removed VBST 0-ohm series R (rdar://5070179) 03/19/07 -- Power Supplies: For 1.8, 3.3 and 5V, increased cap size to 0603/0805 on VBST caps (rdar://5070179)

13.5.0: 03/19/07 -- Power Control: Tied all 4 5V/3.3V enables (EN1, EN2, EN3, EN5) together as part of PM_G2_EN

14.0.0: 03/20/07 -- GPU Vcore: Updated setpoints for GPU Vcore based upon Nvidia Vmin (i.e. 1.05V,1.05V,1.05V,1.125V) 03/20/07 -- FB: Changed FB VREF caps to 2x0.0047uF as required in Nvidia PUN 02736-001-v07 (which requests 1x0.01uF)

3

12

D

C

EVT_SE

10.1.0: 01/24/07 -- PATA Conn: Added pass FET Q4430 to allow PCIREQ3 (ODD reset GPIO) to pullup to S0 01/24/07 -- PATA Conn: Changed =PP5V_S0_ODDPWREN to =PP3V3_S0_ODDPWREN for minor power savings 01/24/07 -- Power Aliases: Updated PP3V3_S0 aliases to support above changes

10.2.0: 01/25/07 -- PATA Conn: Replaced PCIREQ pass FET with OD buffer to correct a corner case during PLTRST 01/25/07 -- Power Aliases: Updated PP5V_S0 aliases to support above changes

11.0.0: 01/25/07 -- BOM: Updated gain of PP1V25_ENET current sense amplifier to 165 (R5432 to 165K) 01/25/07 -- BOM: Updated all Intel APNs to use QS parts 01/25/07 -- Released for EVT (Schem Rev 11, PCB Rev 03)

12.0.0:

B

02/19/07 -- GPU Reset: Changed C2885 to 0.047uF to reduce reset delay on powerup 02/19/07 -- GPU PGOOD: Changed C9595 to 330pF to reduce PGOOD delay on powerup 02/19/07 -- Power Sequencing: NO STUFFed U7885 to remove GPU PGOOD from PWROK chain 02/19/07 -- Power Sequencing Rework: Short pins 2 and 4 of U7885 to complete PWROK chain 02/19/07 -- Released post-EVT to document what was built (Schem Rev 12)

B

DVT

12.1.0: 02/20/07 -- GPU FB: Changed cal resistors per Nvidia PUN (R8290 to 45.3 ohm and R8291 to 24.9 ohm) 02/20/07 -- GPU FB: Changed unterminated-mode reference voltage to 40% (R8297 -> 1.02K, R8432/82, R8532/82 -> 2.21K) 02/21/07 -- FireWire: Changed to Rev C of TI FireWire MCM (APN: 338S0435) 02/21/07 -- Power Sequencing: Removed U7885/C7885 to take GFX_PGOOD out of PWR_OK chain (rdar://4974927) 02/26/07 -- GPU Vcore: NO STUFFed all PWRCTL related components (feature not to be supported) 02/26/07 -- GPU Vcore: Updated voltage setpoints to 1.000/1.070/1.125V (rdar://5021453) 02/26/07 -- SB GPIOs: Sync’d page25.csa to T9_MLB to get pullup updates 02/26/07 -- Thermal Sensors: Updated topology of EMC1033 filter caps (added C5515 next to IC, moved other caps to connectors - rdar://5025773)

12.2.0: 02/27/07 -- ODD Conn: Changed ODD power FET to FDC606P (from FDC638P) for reduced Rds(on) (rdar://4993378) 02/28/07 -- Power Aliases: Moving PP1V8_GPU FET source to PP1V8_S3 rather than PP1V8_S3_ISNS to improve power delivery to GPU (rdar://5021462)

12.3.0: 02/28/07 -- Left Clutch IC: Updated both I-PEX connectors to new APN (part update for shell plating) 02/28/07 -- NB GFX Core: Changed Vcore controller to ISL6263B (part consolidation effort between Apple/Intersil - rdar://5009109) 02/28/07 -- Power Supplies: Replaced APN 152S0511 with 152S0368 (duplicate APNs for same part - rdar://5009109) 03/01/07 -- Thermal Sensors: Updated topology of EMC1033 sensors (removed shorts, changed connector caps to 18pF) 03/01/07 -- NB GFX Decoupling/Power Aliases: Connected VCCD_CRT of NB to GND per CRT disable guidelines

12.4.0:

A

03/01/07 -- LVDS Connector: Changed pin 5 of connector from NC to PP3V3_SW_LCD (in case we add extra cable for power - rdar://5024882) 03/01/07 -- NB GFX Decoupling: Added R2260 (0.3 ohm, 0603) to bring ESR of regulator output cap in spec (rdar://5000272)

12.5.0: 03/02/07 -- Power/Signal Aliases: Added XW0900 to PP5V_S5 to enable layout improvements

12.6.0: 03/06/07 -- Power FETs: Changed Q7080 to RJK0301 which provides much lower Rds(on) 03/06/07 -- FireWire Ports: Changed D4260 to PDS340 for lower height

12.7.0: 03/06/07 -- FireWire Ports: Changed D4260 to PDS540 for higher current capacity 03/06/07 -- Ethernet Connector: Removed RX shorts on Ethernet MDI lines per EMC request 03/06/07 -- SB GPIOs: Changed R2514 from pulldown to pullup to correct auto power-on issue (Linda card detect GPIO) 03/06/07 -- DDR2 Regulator: Changed FB resistors to 0.1% to raise guaranteed lowest output voltage

APPLE COMPUTER INC.

SYNC_MASTER=N/A

Revision History

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

DRAWING NUMBER

NONE

051-7225

SHT

6

D

SCALE

SYNC_DATE=N/A

REV.

14.0.0

OF

88

A

8

67

5

4

3

2

1

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

GPU NO_TESTs

NO_TEST

CPU FSB NO_TESTs

NO_TEST

Left ALS Connector

Request for at least 10 GND test points

NOTE: 10 additional GND test points are called out separately in these notes.

RTC Battery Connector

Current Sense Calibration

Other Func Test Points

per

2 TPs

Left Clutch Barrel Connector

Battery Digital Connector

Left I/O Power Connector

Functional Test Points

ICT Test Points

6 TPs, 2 with each of above TP pairs

NB NO_TESTs

System Validation TPs

NO_TEST

FUNC_TEST

FUNC_TESTFUNC_TEST

FUNC_TEST FUNC_TEST

LPC+ Debug Connector

FUNC_TEST

Thermal Diode Connectors

FUNC_TEST

Fan Connectors

CPUTHMSNS can not be supported due to layout constraints

I550 I551

I552

I553

I554

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

Functional / ICT Test

051-7225

14.0.0

88

7

HSTHMSNS_D_N

TRUE

HSTHMSNS_D_P

TRUE

RSFSTHMSNS_D_P

TRUE

RSFSTHMSNS_D_N

TRUE

CPUTHMSNS_D2_N

CPUTHMSNS_D2_P

TRUE

FAN_LT_PWM

TRUE

FAN_LT_TACH FAN_RT_PWM

TRUE

CPU_DPSLP_L

TRUE

CPU_PWRGD

TRUE

PP3V3_S3

TRUE

ALS_GAIN

TRUE

LTALS_OUT

TRUE

DEBUG_RESET_L

TRUE

SMC_TRST_L

TRUE

SMC_TDO

TRUE

SMC_MD1

TRUE

LPC_AD<3>

TRUE

INT_SERIRQ

TRUE

PM_SUS_STAT_L

TRUE

SMC_RESET_L

TRUE

SMC_TCK

TRUE

SMC_TDI

TRUE

PM_SB_PWROK

TRUE

SB_RTC_RST_L

TRUE

PM_STPCPU_L

TRUE

PM_STPPCI_L

TRUE

VR_PWRGD_CLKEN

TRUE

VR_PWRGOOD_DELAY

TRUE

NB_CLK100M_PCIE_N

TRUE

NB_CLK100M_DPLLSS_N

TRUE

NC_NB_NC<1..16> TP_NB_NC<1..16>

TRUE

SMC_BS_ALRT_L

TRUE

SMBUS_SMC_BSA_SCL

TRUE

PM_CLKRUN_L

TRUE

PM_ENET_EN

TRUE

PM_S4_STATE_L

TRUE

P1V5P1V05S0_PGOOD

TRUE

CPU_DPRSTP_L

TRUE

IMVP6_VID<6..0>

TRUE

NB_CLK96M_DOT_P

TRUE

NB_CLKREQ_L

TRUE

NB_CLK100M_PCIE_P

TRUE

CPU_STPCLK_L

TRUE

SMC_LRESET_L

TRUE

GPU_RESET_L

TRUE

PLT_RST_L

TRUE

SMBUS_SMC_BSA_SDA

TRUE

GND_BATT

TRUE

LPC_AD<0>

TRUE

FWH_INIT_L

TRUE

PP5V_S0

TRUE

ISENSE_CAL_EN

TRUE

PPVCORE_S0_NB_GFX

TRUE

PP5V_S3

TRUE

PPVCORE_GPU

TRUE

USB_CAMERA_N

TRUE

PP5V_S3

TRUE

USB_CAMERA_P

TRUE

USB_WWAN_N

TRUE

PP5V_S3

TRUE

USB_WWAN_P

TRUE

SMC_ONOFF_L

TRUE

PM_SYSRST_L

TRUE

PM_DPRSLPVR

TRUE

PM_RSMRST_L

TRUE

FSB_CPURST_L

TRUE

IMVP_VR_ON

TRUE

PM_SLP_S3_L

TRUE

IMVP_DPRSLPVR

TRUE

PM_SLP_S5_L

TRUE

PPBUS_G3H

TRUE

PPVBATT_G3_RTC

TRUE

NB_SB_SYNC_L

FSB_DPWR_L

TRUE

FSB_CPUSLP_L

TRUE

PCI_RST_L

TRUE

PM_LAN_ENABLE

TRUE

CPU_DPSLP_L

TRUE

PP3V42_G3H

TRUE

PPVCORE_S0_CPU

TRUE

PCI_FW_GNT_L

TRUE

LPC_AD<1>

TRUE

LPC_AD<2>

TRUE

PCI_CLK33M_LPCPLUS

TRUE

SMC_TX_L

TRUE

LPC_FRAME_L

TRUE

LINDACARD_GPIO

TRUE

SMC_NMI

FAN_RT_TACH

TRUE

PP5V_S0

TRUE

SMC_TMS

TRUE

SMC_RX_L

TRUE

NB_CLK96M_DOT_N

TRUE

CPU_THERMTRIP_R

NB_RESET_L

TRUE

FSB_CLK_NB_P

TRUE

FSB_CLK_NB_N

TRUE

NB_CLK100M_DPLLSS_P

FSB_LOCK_L

TRUE

FSB_REQ_L<4..0>

TRUE

FSB_HITM_L

TRUE

FSB_HIT_L

TRUE

FSB_DSTB_L_P<3..0>

TRUE

FSB_DSTB_L_N<3..0>

TRUE

FSB_DRDY_L

TRUE

FSB_DINV_L<3..0>

TRUE

FSB_DBSY_L

TRUE

FSB_D_L<63..0>

TRUE

FSB_BNR_L

TRUE

FSB_BREQ0_L

TRUE

FSB_ADSTB_L<1..0>

TRUE

FSB_ADS_L

TRUE

FSB_A_L<31..3>

TRUE

LVDS_L_DATA_N<2>

TRUE

LVDS_L_DATA_N<1>

TRUE

LVDS_L_DATA_P<2>

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

78

74

78

76

63

76

78

65

62

78

65

57

59

65

61

65

59

54

58

78

62

60

48

58

53

57

59 47

57

51

65

52

53

49

58 46

52

50

84

57

79

47

49

45

57 45

58

47

84

79

48

47

58

84

30

84

45

58

84

42

59

46

74

46

79

40

56

79

43

49

83

47

42

47

84

30

23

38

78

47

46

47

28

30

28

30

29

56

47

65

43

65

23

79

30

79

77

56

47

27

22

44

67

82

44

82

44

82

78

45

58

14

36

46

49

79

23

34

12

47

84

46

47

27

47

46

30

29

79

86

87

10

13

36

53

78

47

46

47

45

46

25

28

29

28

16

29

22

46

48

45

61

34

63

16

58

29

23

45

66

28

48

45

8

49

18

8

49

44

8

44

8

44

46

28

25

45

13

58

35

79

45

40

25

14

28

45

10

28

11

38

45

47

45

47

8

46

45

28

29

22

14

77

51

52

7

10

8

45

53

28

45

23

25

45

9

23

25

9

16

45

25

36

25

61

10

12

84

16

10

28

24

45

56

23

47

7

45

8

7

8

24

7

24

7

24

45

25

16

25

10

45

25

58

25

8

28

16

10

24

25

7

8

24

23

30

43

23

25

45

52

7

45

43

84

23

16

14

16

10

73

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Chipset "VCore" Rails

"FW" (FireWire) Rails

"GPU" Rails

3.3V-2.5V Rails 1.8V-0.9V Rails

MAX I = 0.36A

MAX I = ?.??A

"ENET" Rails

Yukon EC will not be supported

"G3Hot" (Always-Present) Rails

5V Rails

Power Aliases

051-7225

14.0.0

88

8

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

MIN_LINE_WIDTH=0.3 mm

PP3V42_G3H

VOLTAGE=3.42V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP3V42_G3H

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=5V

PP5V_S5

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6 mm

PP3V3_S0

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

PP3V3_S3

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

PP3V3_S0

PP3V3_S3

VOLTAGE=12.6V

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

PPBUS_G3H

MIN_NECK_WIDTH=0.2 mm

PPBUS_G3H

PP3V3_S3

PPBUS_G3H

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.5 mm

PP1V5_S0

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

PP1V5_S0

PP1V8_S3_ISNS

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5

PP1V8_S3

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

PP1V8_S3

PP1V8_S0

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE

PP3V42_G3H

PP5V_S0

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

PP5V_S0

VOLTAGE=5V

PP5V_S0 PP5V_S0

PPBUS_G3H

PP5V_S0

PPVCORE_S0_NB_GFX

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

PP3V3_S5

VOLTAGE=3.3V

PP3V3_S5

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S3

PP3V3_S3 PP3V3_S3

PP3V3_S3

PP3V42_G3H

PP1V5_S0 PP1V5_S0

PP1V5_S0

PP5V_S5

PP5V_S3

PP1V25_ENET

PP5V_S5

PPBUS_G3H

PPDCIN_G3H

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm

PP3V42_G3H

PPBUS_G3H

GND

PP1V9_ENET

PP1V25_ENET

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

VOLTAGE=1.25V

MIN_LINE_WIDTH=0.6 mm

PP1V25_ENET PP1V25_ENET

PP0V9_S0

PP1V05_S0

PPVCORE_S0_NB_R

MAKE_BASE=TRUE

VOLTAGE=0.9V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP5V_S5

MIN_NECK_WIDTH=0.2 mm

PP1V25_GPU

MAKE_BASE=TRUE

VOLTAGE=1.25V

MIN_LINE_WIDTH=0.6 mm

PP1V25_GPU

PPVCORE_S0_NB_GFX

PPVCORE_S0_CPU

MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.25V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm

PPVCORE_S0_NB_GFX

PP1V25_ENET_ISNS

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

PP1V25_ENET_ISNS

MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.25V

PP1V9_ENET

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP1V9_ENET

VOLTAGE=1.9V

PP3V3_ENET

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP3V3_ENET

PP1V8_S0

PP0V9_S0

PP0V9_S3_MEM_VREF

PPVCORE_S0_NB_R

PP1V05_S0

PP1V25_S0

PP1V25_S0 PP1V25_S0

PP1V25_S0

PP1V5_S0

PP0V9_S0

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

VOLTAGE=0.9V

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

VOLTAGE=0.9V

MIN_LINE_WIDTH=0.4 mm

PP0V9_S3_MEM_VREF

PP5V_S5

PP1V8_S3

PP1V8_S3 PP1V8_S3

PP1V8_S3

PP1V25_GPU

PP3V3_S5

PP5V_S3

PP5V_S5

PP5V_S3

PP5V_S5

MAKE_BASE=TRUE

PPBUS_FW_FWPWRSW_F PPBUS_FW_FWPWRSW_F

PP3V3_GPU

PP1V95_FW

PP3V3_FW PP3V3_FW

PP3V3_FW

PPVP_FW_PORTB_UF

MAKE_BASE=TRUE

PPVP_FW_PORTB_UF

PPVP_FW_PORTA_UF

MAKE_BASE=TRUE

PPVP_FW_PORTA_UF

PPVP_FW

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm VOLTAGE=3.3V

MAKE_BASE=TRUE

PP3V3_FW

MIN_LINE_WIDTH=0.4 mm

PP1V95_FW

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

VOLTAGE=1.95V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=33V

PPVP_FW

PP3V3_S5

PPDCIN_G3H

PP3V3_GPU

PP3V3_S5

PP5V_S3

PP3V3_S5

PP1V25_GPU

PP3V3_GPU_TMDS

PPBUS_G3H

PP3V3_S5

PP1V25_GPU

PP1V8_GPU

PP1V8_GPU PP1V8_GPU

PP1V25_GPU

MAKE_BASE=TRUE

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP1V25_S0

PP1V25_ENET_ISNS

PP3V3_GPU_TMDS

PP1V25_GPU

PP3V3_GPU_TMDS

PP1V25_S0

PP3V3_GPU

PP3V3_GPU PP3V3_GPU PP3V3_GPU PP3V3_GPU

PP3V3_GPU

PP3V42_G3H PP3V42_G3H

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=1.05V

PP1V05_S0

PP3V3_GPU_TMDS

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP5V_S5

PP1V8_GPU

VOLTAGE=1.8V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP3V3_GPU PP3V3_GPU

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_GPU

MIN_LINE_WIDTH=0.4 mm

PP1V25_S0

PPDCIN_G3H

PP3V42_G3H

PP5V_S3

PP5V_S5

PP3V42_G3H

MIN_NECK_WIDTH=0.3 mm VOLTAGE=1.25V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

PPVCORE_S0_CPU

PPVCORE_S0_NB_GFX

PP5V_S3

VOLTAGE=5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

PP5V_S0

PPBUS_G3H

PPVCORE_GPU

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

PPVCORE_GPU

MIN_NECK_WIDTH=0.2 mm

PPVCORE_GPU

PP3V3_S0

PP3V3_S3 PP3V3_S3

16

87

77

75

74

65

59

58

57

52

51

50

21

50

48

19

47

46

25

46

42

61

42

32

50

32

31

87

31

46

87

46

31

87

31

30

74

75

74

75

30

74

30

75

74

75

30

74

30

75

30

29

63

65

78

63

78

27

65

29

63

27

65

63

65

27

78

63

29

65

29

78

74

28

78

28

78

62

78

62

60

78

76

62

76

60

28

78

74

62

78

62

26

74

26

74

60

74

60

62

60

78

26

74

78

74

78

76

62

28

78

28

60

26

28

65

27

57

27

57

61

57

61

57

65

61

65

57

27

57

65

61

65

61

23

65

23

65

57

65

77

57

77

57

61

57

77

65

23

65

77

65

61

27

57

27

57

27

48

63

26

54

26

54

60

54

60

87

55

48

59

60

59

55

26

54

48

87

63

60

48

60

21

63

21

87

63

55

63

76

55

76

55

60

55

76

48

21

63

76

48

63

48

59

60

26

54

26

55

26

47

62

25

53

25

53

59

53

59

63

48

87

47

58

59

58

48

25

53

47

63

62

78

62

59

47

59

19

62

19

63

62

87

48

78

62

78

62

74

48

74

48

78

59

48

77

74

47

19

62

77

74

47

78

62

47

78

58

59

25

53

25

48

25

46

61

24

16 21

24

51

24

51

58

51

58

34

46

62

46

57

58

57

46

24

51

46

34

61

57

61

58

46

58

18

61

77

18

65

34

61

62

77

46

57

61

57

61

73

46

73

46

57

77

58

46

77

73

77

65

77

65

73

46

18

61

73

65

46

57

61

46

57

58

24

51

24

46

24

45

60

23

50

23

50

57

50

57

27

57

28

57

45

52

57

52

28

23

50

45

27

60

53

60

57

45

57

14

50

60

74

58

14

57

27

60

57

74

28

53

60

53

60

72

28

72

28

53

74

57

28

74

70

74

57

74

57

72

45

14

60

70

72

57

45

53

60

45

58

53

52

57

23

50

23

19

28

23

43

57

21

48

21

48

56

48

56

26

50

27

50

65

43

47

56

47

59

27

21

48

43

26

57

49

57

56

43

56

13

22

57

71

59

49

59

65

62

13

27

26

62

57

50

71

27

49

57

49

57

71

64

27

71

27

49

71

56

27

71

69

71

27

71

27

71

43

13

57

69

71

27

43

49

57

43

49

59

49

47

56

74

74 74

21

48

34

43

19

38

19

38

49

38

49

22

21

26

38

57

34

42

49

42

22

26

19

38

34

22

43

46

61

43

49

34

49

61

12

21

43

68

22

12

22

57

32

12

26

22

32

43

38

68

26

46

43

46

43

65

41

64

41

64

26

65

26

46

68

76

49

26

68

26

76

68

76

26

65

34

12

76

43

68

65

26

34

46

43

34

12

22

46

42

49

67

67 67

19

38

28

27

16

36

16

36

40

36

40

12

18

25

32

22

28

27

27 27

27

40

27

18

25

16

36

28

12

27

44

50

27

40

65

28

40

36

50

62

11

18

27

66

18

11

18

57

36

22

31

11

21

12

62

31

27

32

66

25

44

27

44

27

64 64

57

64

40

41 41

40

64

40

25

65

57

25

44

66

73

40

25

66

67

66

21

73

66

73

21

57

28

11

73

27

67

57

21

65

28

44

27

28

11

18

44

27

40

49

49 49

16

36

8

9

13

8

13

8

11

16

24

31

19

8

8 8

8

24

13

8

11

9

8

35

9

8

34

8

35

33

10

16

9

57

8

50

35

19

16

10

19

11

33

16

9

31

57

24

8

9

8

9

40 40

48

39

40 40

39

24

34

48

24

8

57

72

8

24

57

19

72

57

72

19

48

8

10

72

9

57

48

19

34

8

9

8

8 8

13

8

7

8

7

8

7

8

7

7 7

7

8

7

8

7

8

7

8

7

8

7

8

7

8

7

8

8 8

8

8 8

8

7

8

7

8

7

8

7

8

7

7 7

8

7

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Board

Thermal Module Holes

Right CPU

TM Hole

Digital Ground

TM Hole

Bottom Left GPU

Top GPU Right

TM Hole

RAM Door (Torx) Holes

Add 2 buried vias to GND

Left CPU

Top CPU TM Notch

Frame Holes

Chassis GNDs

Edge

Notches

(Can’t be PTH)

Holes

Tooling

(Can’t be PTH)

TM Hole

ZT0945

1

HOLE-VIA-P5RP25

ZT0950

1

HOLE-VIA-P5RP25

R0910

1

2

OMIT

NONE

SHORT

NONE NONE

402

SH0925

1 2 3

OG-503040

SHLD-SM-LF

ZT0970

1

5P75R2P7

ZT0975

1

5P75R2P7

ZT0980

1

5P75R2P7

ZT0985

1

5P75R2P7

ZT0930

1

3P7R3P2

ZT0935

1

3P7R3P2

ZT0940

1

3P7R3P2

ZT0920

1

3P2R2P7

ZT0965

1

3P2R2P7

ZT0955

1

3P2R2P7

ZT0990

1

HOLE-VIA-P5RP25

ZT0960

1

HOLE-VIA-P5RP25

XW0900

1 2

SM

SYNC_DATE=08/23/2006

051-7225

14.0.0

88

9

SYNC_MASTER=(T9_MLB)

Signal Aliases

GND_CHASSIS_LEFTCLUTCH

MAKE_BASE=TRUE

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

GND_CHASSIS_LEFTCLUTCH

PP5V_S5

TP_USB_EXTCN

NO_TEST=TRUE

VOLTAGE=5V

MIN_NECK_WIDTH=0.1 mm

PP5V_S5_P1V25S0FET

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.1 mm

PP5V_S5_P1V25S0FET

PM_SB_PWROK

MAKE_BASE=TRUE

PM_SB_PWROK

GND

GND_CHASSIS_DVI_TOP

GND

GND_CHASSIS_RTUSB

GND_CHASSIS_ENET

GND_CHASSIS_DVI_BOT

GND_CHASSIS_DVI_TOP

GND_CHASSIS_RTUSB

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

GND_CHASSIS_ENET

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm

GND_CHASSIS_DVI_TOP

MAKE_BASE=TRUE

TP_USB_EXTCP

TP_MEM_B_A<15>

MAKE_BASE=TRUE

TP_MEM_B_A<15>

TP_MEM_A_A<15>

MAKE_BASE=TRUE

TP_MEM_A_A<15>

GFXIMVP6_VID<4..0>

MAKE_BASE=TRUE

GFX_VR_EN

MAKE_BASE=TRUE

GFX_VID<4..0>

GFX_VR_EN

VR_PWRGOOD_DELAY

MAKE_BASE=TRUE

VR_PWRGOOD_DELAY

PM_ALL_NBGFX_PGOODPM_ALL_NBGFX_PGOOD

MAKE_BASE=TRUE

SMC_SMS_INT

MAKE_BASE=TRUE

SMC_SMS_INT

TP_USB_EXTCP

MAKE_BASE=TRUE

PEG_CLK100M_GPU_P PEG_CLK100M_GPU_N

MAKE_BASE=TRUE

PEG_CLK100M_GPU_P PEG_CLK100M_GPU_N

MAKE_BASE=TRUE

TP_USB_EXTCN

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE

GND_CHASSIS_DVI_BOT

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

GND

74 65 63 62 61 60

58 58

84

57

28 28

66

51

43

82

25 25

43

41

43

82

59 59

16 16

77 77

54 54

82

30

82

44

27

24

57

9 9

76

41

37

76

41

76

24

32 32

31 31

16 16

9 9

59 59

45 45

24

29

24

76

9

8

9

7 7

9

9 9

59

9

16

9

7 7

9 9

9

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN IN IN

IN

OUT

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI

BI BI BI BI BI

BI

OUT

IN

IN IN IN IN IN

IN IN

OUT

IN IN

IN

IN IN

IN

OUT

BI BI BI BI

LOCK*

INIT*

A20M*

A6*

A3* A4*

A14*

A16*

REQ0* REQ1* REQ2* REQ3* REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD9

RSVD8

RSVD7

RSVD6

RSVD5

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20* A21* A22* A23* A24*

A26* A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

NC

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

RESERVED

ADDR GROUP0ADDR GROUP1

ICH

DINV1*

D31*

D30*

D25*

D11* D12* D13* D14*

DSTBP0* DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

DATBP1*

D0*

D32* D1* D2*

D5*

D16*

D20* D21* D22* D23* D24*

D26* D27* D28* D29*

DSTBN1*

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6

BSEL0 BSEL1 BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2* DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3* DSTBP3*

DINV3*

COMP0 COMP1 COMP2 COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PIN. MAKE SURE CPU_TEST4 IS

PLACE C1000 CLOSE TO CPU_TEST4

REFERENCED TO GND

0.5" MAX LENGTH FOR CPU_GTLREF

FSB_IERR_L WITH A GND

PLACE TESTPOINT ON

0.1" AWAY

GMCH WITHOUT T (NO STUB)

SHOULD CONNECT TO ICH AND

PM_THRMTRIP#

COMP1,3 CONNECT WITH ZO=55OHM, MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE TRACE LENGTH SHORTER THAN 0.5".

LAYOUT NOTE:

NC

R1002

1

2

402

MF-LF

54.9

1/16W

1%

R1004

1

2

MF-LF 402

1/16W

5%

68

R1005

1

2

402

1K

MF-LF

1%

1/16W

R1006

1

2

402

1/16W

2.0K

MF-LF

1%

R1019

402

54.9

1/16W MF-LF

1%

R1018

402

1%

MF-LF

1/16W

27.4

R1017

402

54.9

1/16W MF-LF

1%

R1016

402

27.4

1/16W MF-LF

1%

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

16 23 58 79

7

23 79

7

14 79

7

14 79

28 58

7

13 23 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

30 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

7

14 79

13 79

10 13 79

13 28

46 58 79

51

16 23 46 79

23 47 79

7

13 14 79

14 79

10 13 79

51 87

29 30 84

23 79

7

23 79

R1030

402

NOSTUFF

5%

MF-LF

1/16W

0

R1007

1

2

402

NOSTUFF

1K

MF-LF

5% 1/16W

R1003

1

2

402

54.9

MF-LF

1%

1/16W

R1020

402

54.9

1/16W MF-LF

1%

R1021

402

1%

MF-LF

1/16W

54.9

R1022

402

1%

MF-LF

1/16W

54.9

14 79

R1023

402

1%

MF-LF

1/16W

649

R1012

1

2

402

MF-LF

NOSTUFF

1K

5%

1/16W

C1000

1

2

402

16V

10%

0.1uF

NOSTUFF

X5R

U1000

N3 P5 P2 L2 P4 P1 R1

Y2 U5 R3 W6

A6

U4 Y5 U1 R4 T5 T3 W2 W5 Y4

J4

U2 V4

W3 AA4 AB2 AA3

L5

L4

K5

M3

N2

J1

H1

M1

V1

A22 A21

E2

AD4 AD3 AD1 AC4

G5

F1

C20

E1

H5 F21

A5

G6 E4

D20

C4

B3

C6

B4

H4

B1

AC2 AC1

D21

K3

H2

K2

J3

L1

C1 F3 F4 G3

M4

N5

T2

V3

B2

C3

D2 D22

D3

F6

A3

D5

AC5 AA6 AB3

A24 B25

C7

AB5

G2

AB6

FCBGA

MEROM

OMIT

U1000

B22 B23 C21

R26 U26 AA1 Y1

E22 F24

J24 J23 H22 F26 K22 H23

N22 K25 P26 R23

E26

L23 M24 L22 M23 P25 P23 P22 T24 R24 L25

G22

T25 N25

Y22 AB24 V24 V26 V23 T22 U25 U23

F23

Y25 W22 Y23 W24 W25 AA23 AA24 AB25

AE24 AD24

G25

AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21

E25

AC22 AD23 AF22 AC23

E23 K24 G24

M26

H25

N24

U22

AC20

E5 B5 D24

J26

L26

Y26

AE25

H26

AA26

AF24

AD26

AE6

D6 D7

C23 D25 C24

AF26

AF1 A26

FCBGA

MEROM

OMIT

R1024

402

PLACEMENT_NOTE=Place R1024 near ITP connector (if present)

54.9

1/16W MF-LF

1%

CPU FSB

10

14.0.0

051-7225

88

SYNC_MASTER=T9_NOME

SYNC_DATE=03/16/2007

TP_CPU_TEST5

FSB_DINV_L<1>

FSB_D_L<31>

FSB_D_L<30>

FSB_D_L<25>

FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14>

FSB_DSTB_L_P<0> FSB_DINV_L<0>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<6>

FSB_D_L<19>

FSB_D_L<18>

FSB_DSTB_L_P<1>

FSB_D_L<0>

FSB_D_L<32> FSB_D_L<1> FSB_D_L<2>

FSB_D_L<5>

FSB_D_L<16>

FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24>

FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29>

FSB_DSTB_L_N<1>

CPU_GTLREF CPU_TEST1

CPU_TEST2 TP_CPU_TEST3 CPU_TEST4

TP_CPU_TEST6

CPU_BSEL<0>

CPU_BSEL<1>

CPU_BSEL<2>

FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47> FSB_DSTB_L_N<2> FSB_DSTB_L_P<2> FSB_DINV_L<2>

FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63> FSB_DSTB_L_N<3> FSB_DSTB_L_P<3> FSB_DINV_L<3>

CPU_COMP<0> CPU_COMP<1> CPU_COMP<2> CPU_COMP<3>

CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD FSB_CPUSLP_L CPU_PSI_L

FSB_D_L<17>

FSB_D_L<4>

FSB_D_L<3>

FSB_DSTB_L_N<0>

FSB_D_L<15>

FSB_D_L<10>

FSB_LOCK_L

CPU_INIT_L

CPU_A20M_L

FSB_A_L<6>

FSB_A_L<3> FSB_A_L<4>

FSB_A_L<14>

FSB_A_L<16>

FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>

FSB_CLK_CPU_N

FSB_CLK_CPU_P

PM_THRMTRIP_L

CPU_THERMD_P

CPU_PROCHOT_L

XDP_DBRESET_L

XDP_TRST_L

XDP_TMS

XDP_TDO

XDP_TDI

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<1>

XDP_BPM_L<0>

FSB_HITM_L

FSB_HIT_L

FSB_TRDY_L

FSB_RS_L<2>

FSB_RS_L<1>

FSB_RS_L<0>

FSB_CPURST_L

CPU_IERR_L

FSB_BREQ0_L

FSB_DBSY_L

FSB_DRDY_L

FSB_DEFER_L

FSB_BNR_L

TP_CPU_RSVD9

TP_CPU_RSVD8

TP_CPU_RSVD7

TP_CPU_RSVD6

TP_CPU_RSVD5

TP_CPU_RSVD4

TP_CPU_RSVD3

TP_CPU_RSVD2

TP_CPU_RSVD1

TP_CPU_RSVD0

CPU_SMI_L

CPU_NMI

CPU_INTR

CPU_STPCLK_L

CPU_FERR_L

FSB_ADSTB_L<1>

FSB_A_L<35>

FSB_A_L<34>

FSB_A_L<33>

FSB_A_L<32>

FSB_A_L<31>

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<17>

FSB_ADSTB_L<0>

FSB_A_L<13>

FSB_A_L<12>

FSB_BPRI_L

FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24>

FSB_A_L<26> FSB_A_L<27>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<11>

FSB_A_L<25>

CPU_IGNNE_L

FSB_ADS_L

FSB_A_L<10>

FSB_A_L<15>

FSB_A_L<5>

XDP_TCK

XDP_TDO

XDP_TMS

XDP_TDI

XDP_TRST_L

PP1V05_S0

CPU_THERMD_N

XDP_TCK

XDP_BPM_L<5>

XDP_BPM_L<2>

61

50

46

30

27

26

23

21

19

18

14

13

12

79

11

13

10

79 79

79

10

8

OUT OUT OUT OUT OUT OUT OUT

OUT

VCC

VSSSENSE

VCCSENSE

VID6

VID5

VID4

VID3

VID2

VID1

VID0

VCCA

VCCP

VCC

3 OF 4

VSS VSS

4 OF 4

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

11.5 A (Deeper Sleep)

25.0 A (Deep Sleep HFM)

27.4 A (Sleep HFM)

17.0 A (Auto-Halt/Stop-Grant SuperLFM)

27.4 A (Auto-Halt/Stop-Grant HFM)

30.4 A (LFM)

25.5 A (SuperLFM)

9.4 A (Enhanced Deeper Sleep)

2500 mA (after VCC stable)

4500 mA (before VCC stable)

16.0 A (Deep Sleep SuperLFM)

16.8 A (Sleep SuperLFM)

41.0 A (HFM)

44.0 A (Design Target)

Standard Voltage:

(CPU CORE POWER)

130 mA

(CPU IO POWER 1.05V)

(CPU INTERNAL PLL POWER 1.5V)

Low Voltage: Ultra Low Voltage:

17.0 A (Design Target)23.0 A (Design Target)

21.0 A (HFM)

18.7 A (LFM) TBD A (SuperLFM)

TBD A (Auto-Halt/Stop-Grant HFM) TBD A (Auto-Halt/Stop-Grant SuperLFM)

TBD A (Sleep HFM) TBD A (Sleep SuperLFM)

TBD A (Deep Sleep HFM) TBD A (Deep Sleep SuperLFM)

TBD A (Deeper Sleep) TBD A (Enhanced Deeper Sleep) TBD A (Enhanced Deeper Sleep)

TBD A (Deeper Sleep)

TBD A (Deep Sleep HFM)

TBD A (Sleep HFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (HFM) TBD A (LFM)

Current numbers from Merom for Santa Rosa EMTS, doc #22221.

TBD A (Auto-Halt/Stop-Grant LFM)

TBD A (Sleep LFM)

TBD A (Deep Sleep LFM)

12 79

R1101

1

2

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

MF-LF 402

100

1% 1/16W

12 79

58 79

U1000

A7 A9

B9 B10 B12 B14 B15 B17 B18 B20

C9 C10

A10

C12 C13 C15 C17 C18

D9 D10 D12 D14 D15

A12

D17 D18

E7

E9 E10 E12 E13 E15 E17 E18

A13

E20

F7

F9 F10 F12 F14 F15 F17 F18 F20

A15

AA7 AA9

AA10 AA12 AA13 AA15 AA17 AA18 AA20

AB9

A17

AC10 AB10 AB12 AB14 AB15 AB17 AB18

AB20 AB7 AC7

A18

AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12

A20

AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17

B7

AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

B26 C26

G21 V6

R21 R6 T21 T6 V21 W21

J6 K6 M6 J21 K21 M21 N21 N6

AF7

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AE7

FCBGA

MEROM

OMIT

U1000

A4 A8

B11

W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5

B13

AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8

B16

AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11

B19

AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13

B21

AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16

B24

AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19

C5

AF21 A25 AF25

C8 C11 C14

A11

C16 C19

C2 C22 C25

D1

D4

D8 D11 D13

A14

D16 D19 D23 D26

E3

E6

E8 E11 E14 E16

A16

E19 E21 E24

F5

F8 F11 F13 F16 F19

F2

A19

F22 F25

G4

G1 G23 G26

H3

H6 H21 H24

A23

J2

J5 J22 J25

K1

K4 K23 K26

L3

L6

AF2

L21 L24

M2

M5 M22 M25

N1

N4 N23 N26

B6

P3

P6 P21 P24 R2 R5 R22 R25 T1 T4

B8 T23

T26 U3 U6 U21 U24 V2 V5 V22 V25

FCBGA

MEROM

OMIT

R1100

1

2

MF-LF 402

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

1/16W

1%

100

SYNC_DATE=03/16/2007

SYNC_MASTER=T9_NOME

CPU Power & Ground

051-7225

14.0.0

11 88

PP1V05_S0

PP1V5_S0

CPU_VID<4>

CPU_VID<6>

PPVCORE_S0_CPU

CPU_VID<1>

CPU_VID<0>

CPU_VCCSENSE_P

CPU_VCCSENSE_N

PPVCORE_S0_CPU

CPU_VID<5>

CPU_VID<3>

CPU_VID<2>

61 50 46 30

27 26 23 21

87

19

63

18

34

58

14

27

49

13

26

12

22

11

10

12

8

7

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

4x 330uF, 20x 22uF 0805

CPU VCORE VID CONNECTIONS

CPU VCORE HF AND BULK DECOUPLING

1x 470uF, 6x 0.1uF 0402

VCCP (CPU I/O) DECOUPLING

1x 10uF, 1x 0.01uF

VCCA (CPU AVdd) DECOUPLING

WF: Consider sharing bulk cap with NB Vtt?

C1206

1

2

CERM-X5R 805

6.3V

20%

22UF

C1235

1

2 3

CRITICAL

2.5V TANT

D2T

20%

470UF

C1204

1

2

CERM-X5R 805

6.3V

20%

22UF

C1216

1

2

20%

6.3V 805

CERM-X5R

22UF

C1214

1

2

20%

6.3V 805

CERM-X5R

22UF

C1208

1

2

CERM-X5R 805

6.3V

20%

22UF

C1203

1

2

CERM-X5R 805

6.3V

20%

22UF

C1207

1

2

CERM-X5R 805

6.3V

20%

22UF

C1202

1

2

CERM-X5R 805

20%

22UF

6.3V

C1201

1

2

CERM-X5R 805

6.3V

20%

22UF

C1213

1

2

20%

6.3V 805

CERM-X5R

22UF

C1212

1

2

6.3V 805

20% CERM-X5R

22UF

C1211

1

2

20%

6.3V 805

CERM-X5R

22UF

C1219

1

2

805

6.3V

20% CERM-X5R

22UF

C1200

1

2

CERM-X5R

22UF

6.3V 805

20%

C1210

1

2

805

6.3V

20% CERM-X5R

22UF

C1236

1

2

0.1UF

20% CERM

402

10V

C1205

1

2

CERM-X5R 805

6.3V

20%

22UF

C1209

1

2

CERM-X5R 805

6.3V

20%

22UF

C1215

1

2

20%

6.3V 805

CERM-X5R

22UF

C1217

1

2

20%

6.3V 805

CERM-X5R

22UF

C1237

1

2

20% CERM

402

0.1UF

10V

C1238

1

2

20% CERM

402

0.1UF

10V

C1239

1

2

20% CERM

402

0.1UF

10V

C1240

1

2

20% CERM

402

0.1UF

10V

C1241

1

2

20% CERM

402

0.1UF

10V

C1218

1

2

6.3V 805

20% CERM-X5R

22UF

C1281

1

2

PLACEMENT_NOTE=Place near CPU pin B26.

CERM 402

16V

10%

0.01UF

C1280

1

2

X5R

6.3V

20%

10uF

603

C1250

1

2 3

10%

2.0V

330UF

TANT

D2T

PLACEMENT_NOTE=Place in CPU center cavity.

CRITICAL

C1251

1

2 3

10%

2.0V

330UF

CRITICAL

TANT

D2T

PLACEMENT_NOTE=Place in CPU center cavity.

C1252

1

2 3

2.0V

330UF

CRITICAL

TANT

D2T

10%

PLACEMENT_NOTE=Place in CPU center cavity.

C1253

1

2 3

2.0V

330UF

10%

TANT

D2T

CRITICAL

PLACEMENT_NOTE=Place in CPU center cavity.

CPU Decoupling & VID

SYNC_MASTER=M76_MLB

8812

14.0.0

SYNC_DATE=03/19/2007

051-7225

PP1V05_S0

PP1V5_S0

IMVP6_VID<0..6>

CPU_VID<0..6>

MAKE_BASE=TRUE

PPVCORE_S0_CPU

61 50 46 30 27

26 23 21

87

19

63

18

34

14

27

58

13

26

49

11

22

79

11

10

11

58

79

8

7

11

7

IN

BI

OUT

OUT IN

BI IN

IN IN

OUT

IN

OUT OUT

OUT

IN

BI IN

IN IN

IN

IN IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(OBSDATA_A0) (OBSDATA_A1)

OBSDATA_D2

998-1571

OBSDATA_B0

TDI TMS XDP_PRESENT#

OBSDATA_C1

Please avoid any obstructions on even-numbered side of J1300

Direction of XDP module

ITPCLK/HOOK4

OBSDATA_A0

OBSFN_A0

OBSDATA_B2 OBSDATA_B3

OBSDATA_A2 OBSDATA_A3

OBSDATA_D0 OBSDATA_D1

HOOK1

VCC_OBS_AB

HOOK2 HOOK3

TRSTn

OBSFN_A1

OBSDATA_A1

OBSDATA_B1

SDA SCL

TCK1

SB OC[7]#

SB OC[6]#

SB OC[5]#

SB OC[2]#

SB OC[1]#

OBSDATA_C3

SB OC[0]#

DBR#/HOOK7

RESET#/HOOK6

ITPCLK#/HOOK5

TDO

OBSDATA_C2

OBSDATA_C0

OBSFN_C1

NC

(OBSDATA_A3)

TCK0

PWRGD/HOOK0

SB OC[3]#

(OBSDATA_A2)

SB OC[4]#

NB CFG[2]

NB CFG[4] NB CFG[5]

NB CFG[6] NB CFG[7]

NB CFG[3]

NB CFG[8] SB GPIO[8]

OBSDATA_D3

OBSFN_C0

(VCC_OBS_CD)

NOTE: This is not the standard XDP pinout.

Mini-XDP Connector

Use with 920-0451 adapter board to support CPU, NB & SB debugging.

NB CFG[1]

NB CFG[0]

7

10 23 79

R1399

1 2

XDP

1K

5% 1/16W MF-LF

402

15

R1315

1

2

54.9

1%

MF-LF

402

XDP

1/16W

C1300

1

2

XDP

X5R

0.1uF

10% 16V

402

R1331

1

2

402

1/16W

XDP

5%

10K

MF-LF

R1330

1

2

402

XDP

1/16W

5%

10K

MF-LF

C1301

1

2

XDP

X5R

0.1uF

10% 16V

402

10 28

10 79

7

10 14 79

10 79

29 30 79 84

24 34

24

24 77

24

24 36

24

24 43

R1303

1 2

XDP

1K

5%

MF-LF

402

1/16W

J1300

1

10

1112 1314 1516 1718 19

2

20

2122 2324 2526 2728 29

3

30

3132 3334 3536 3738 39

4

40

4142 4344 4546 4748 49

5

50

5152 5354 5556 5758 59

6

60

78 9

LTH-030-01-G-D-NOPEGS

F-ST-SM

CRITICAL XDP_CONN

16 30 79

16

25 45

16

16 30 79

16

051-7225

88

14.0.0

13

SYNC_MASTER=T9_NOME

SYNC_DATE=12/12/2006

eXtended Debug Port (XDP)

XDP_BPM_L<4>

XDP_BPM_L<1>

XDP_CLK_N

NB_CFG<8>

USB_EXTD_OC_L

NB_CFG<3>

NB_BSEL<2>

SMC_WAKE_SCI_L

CPU_PWRGD XDP_PWRGD

NB_CFG<7>

NB_CFG<6>

NB_CFG<5>

NB_CFG<4>

NB_BSEL<0>

XDP_BPM_L<0>

XDP_BPM_L<2>

XDP_BPM_L<5>

WOW_EN

TP_XDP_HOOK2

USB_EXTB_OC_L

SB_GPIO30

TP_XDP_HOOK3

XDP_BPM_L<3>

XDP_TCK

XDP_TDO

FSB_CPURST_LXDP_CPURST_L

XDP_TDI XDP_TMS

SB_GPIO40

USB_EXTA_OC_L

XDP_DBRESET_L

XDP_TRST_L

LVDS_CTRL_DATA LVDS_CTRL_CLK

XDP_OBS20

XDP_CLK_P

PP3V3_S0

EXTGPU_LVDS_EN

PM_LATRIGGER_L

NB_BSEL<1>

PP1V05_S0

87 77 75 74 65 59 58 57 52

51 50 48 47 46 42

61

32

50

31

46

30

29

27

28

26

27

23

26

21

25

19

24

18

23

14

21

12

19

11

16

10

79

8

BI

BI BI

OUT

BI

BI BI

BI

BI BI BI BI

BI BI

BI

BI BI

BI BI BI BI

BI BI

OUT

BI

OUT

BI BI BI BI BI

BI BI

H_D0*

H_D3*

H_D2*

H_D33* H_D34* H_D35*

H_D1*

H_D4*

H_D10*

H_A4* H_A5* H_A6* H_A7* H_A8*

H_A9* H_A10* H_A11* H_A12* H_A13* H_A14* H_A15* H_A16* H_A17* H_A18* H_A19* H_A20* H_A21* H_A22* H_A23* H_A24* H_A25* H_A26* H_A27* H_A28* H_A29* H_A30* H_A31* H_A32* H_A33* H_A34* H_A35*

H_ADS*

H_ADSTB0* H_ADSTB1*

H_A3*

H_D7* H_D8* H_D9*

H_D11* H_D12* H_D13* H_D14* H_D15* H_D16* H_D17* H_D18* H_D19* H_D20* H_D21* H_D22* H_D23*

H_D25* H_D26* H_D27* H_D28* H_D29* H_D30*

H_D32*

H_D36* H_D37* H_BNR* H_D38*

H_BPRI* H_D39* H_D40*

H_DEFER*

H_D41*

H_DBSY* H_D42* H_D43* H_D44*

H_DPWR* H_D45*

H_DRDY* H_D46* H_HIT* H_D47*

H_HITM* H_D48*

H_LOCK*

H_TRDY*

H_D51* H_D52* H_D53*

H_DINV0*

H_D54*

H_DINV1*

H_D55*

H_DINV2*

H_D56*

H_DINV3*

H_D57* H_D58*

H_DSTBN0*

H_D59*

H_DSTBN1*

H_D60*

H_DSTBN2*

H_D61*

H_DSTBN3*

H_D62* H_D63*

H_DSTBP0* H_DSTBP1*

H_DSTBP2* H_SWING H_RCOMP

H_REQ0* H_SCOMP H_REQ1* H_SCOMP*

H_REQ2*

H_REQ3* H_CPURST*

H_REQ4* H_CPUSLP*

H_RS0* H_RS1*

H_AVREF

H_RS2*

H_DVREF

H_D5* H_D6*

H_D31*

H_BREQ*

H_D24*

H_D49* H_D50*

H_DSTBP3*

HPLL_CLK

HPLL_CLK*

HOST

(1 OF 10)

BI BI BI BI

BI

IN

OUT OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

C1425

1

2

402

16V

10%

0.1uF

X5R

R1426

1

2

402

1/16W

1%

MF-LF

2.0K

R1425

1

2

402

1/16W

1%

MF-LF

1K

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

R1420

1

2

402

1/16W

1% MF-LF

54.9

R1415

1

2

402

1/16W

1%

MF-LF

24.9

R1410

1

2

402

1/16W

1%

MF-LF

221

R1411

1

2

402

1/16W

1%

MF-LF

100

C1410

1

2

402

16V

10%

0.1uF

X5R

7

10 79

U1400

G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17

J13

B15 E17 C18 A19 B19 N19

B11 C11 M11 C15 F16 L13

G12 H17 G20

B9

C8 E8 F12

B6 E5

E2 G2

M10 N12

N9 H5

P13

K9 M2

W10

Y8 V4

G7

M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4

M6

W3 N1

AD12

AE3 AD9 AC9

AC7 AC14 AD11 AC11

H7

AB2

AD7

AB1

Y3 AC6 AE2 AC5 AG3 AJ9 AH8

H3

AJ14

AE9

AE11 AH12

AJ5 AH5 AJ6 AE7 AJ7 AJ2

G4

AE5 AJ3 AH2

AH13

F3

N8

H2

C10

D6

K5 L2 AD13 AE13

H8 K7

M7 K3 AD2 AH11

L7 K2 AC2 AJ10

A9

E4 C6 G10

C2

M14 E13 A11 H13 B12

E12 D7 D8

W1

W2

B3

B7

AM5 AM7

FCBGA

CRESTLINE

OMIT

10 79

7

10 79

R1421

1

2

402

1/16W

1%

MF-LF

54.9

7

10 79

7

29 30 84

7

29 30 84

7

10 13 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

7

10 79

SYNC_MASTER=T9_NOME

14 88

14.0.0

051-7225

NB CPU Interface

SYNC_DATE=03/16/2007

PP1V05_S0

FSB_D_L<47>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<33> FSB_D_L<34> FSB_D_L<35>

FSB_D_L<1>

FSB_D_L<10>

FSB_D_L<7> FSB_D_L<8> FSB_D_L<9>

FSB_D_L<11>

FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23>

FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30>

FSB_D_L<32>

FSB_D_L<36> FSB_D_L<37>

FSB_D_L<39> FSB_D_L<40>

FSB_D_L<42>

FSB_D_L<44> FSB_D_L<45> FSB_D_L<46>

FSB_D_L<48>

FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58>

FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63>

NB_FSB_SCOMP NB_FSB_SCOMP_L

FSB_CPURST_L FSB_CPUSLP_L

FSB_D_L<6>

FSB_D_L<31>

FSB_D_L<24>

FSB_D_L<49> FSB_D_L<50>

FSB_D_L<12>

FSB_D_L<43>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<0>

FSB_D_L<38>

FSB_D_L<41>

FSB_D_L<59>

NB_FSB_SWING NB_FSB_RCOMP

NB_FSB_VREF

FSB_A_L<3>

FSB_A_L<6>

FSB_A_L<4> FSB_A_L<5>

FSB_A_L<7> FSB_A_L<8> FSB_A_L<9>

FSB_A_L<11>

FSB_A_L<10>

FSB_A_L<12> FSB_A_L<13> FSB_A_L<14> FSB_A_L<15> FSB_A_L<16> FSB_A_L<17> FSB_A_L<18> FSB_A_L<19> FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29>

FSB_A_L<32>

FSB_A_L<30> FSB_A_L<31>

FSB_A_L<33> FSB_A_L<34> FSB_A_L<35>

FSB_ADS_L FSB_ADSTB_L<0> FSB_ADSTB_L<1>

FSB_BPRI_L

FSB_BNR_L

FSB_BREQ0_L FSB_DEFER_L FSB_DBSY_L

FSB_DPWR_L

FSB_CLK_NB_P FSB_CLK_NB_N

FSB_DRDY_L FSB_HIT_L FSB_HITM_L

FSB_TRDY_L

FSB_LOCK_L

FSB_DINV_L<0> FSB_DINV_L<1> FSB_DINV_L<2> FSB_DINV_L<3>

FSB_DSTB_L_N<0> FSB_DSTB_L_N<1> FSB_DSTB_L_N<2> FSB_DSTB_L_N<3>

FSB_DSTB_L_P<0> FSB_DSTB_L_P<1> FSB_DSTB_L_P<2> FSB_DSTB_L_P<3>

FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>

FSB_RS_L<1>

FSB_RS_L<0>

FSB_RS_L<2>

61 50 46 30 27

26 23 21 19 18 13 12 11 10

8

IN

OUT

IN

OUT OUT OUT

OUT

IN

OUT

BI

L_BKLT_CTRL

L_VDD_EN

PEG_TX15*

PEG_TX14*

PEG_TX13*

PEG_TX12*

PEG_TX11*

PEG_TX10*

PEG_TX9*

PEG_TX8*

PEG_TX7*

PEG_TX6*

PEG_TX5*

PEG_TX4*

PEG_TX3*

PEG_TX2*

PEG_TX1*

PEG_TX0*

PEG_TX15

PEG_TX14

PEG_TX13

PEG_TX12

PEG_TX11

PEG_TX10

PEG_TX9

PEG_TX8

PEG_TX7

PEG_TX6

PEG_TX5

PEG_TX4

PEG_TX3

PEG_TX2

PEG_TX1

PEG_TX0

PEG_RX14

PEG_RX15*

PEG_RX14*

PEG_RX13*

PEG_RX12*

PEG_RX11*

PEG_RX15

PEG_RX13

PEG_RX12

PEG_RX11

PEG_RX10

PEG_RX9

PEG_RX8

PEG_RX7

PEG_RX6

PEG_RX5

PEG_RX4

PEG_RX3

PEG_RX2

PEG_RX1

PEG_RX0

PEG_RX10*

PEG_RX9*

PEG_RX8*

PEG_RX7*

PEG_RX6*

PEG_RX5*

PEG_RX4*

PEG_RX3*

PEG_RX2*

PEG_RX1*

PEG_RX0*

PEG_COMPI PEG_COMPO

CRT_DDC_DATA

L_CTRL_DATA

LVDSB_DATA1 LVDSB_DATA2

LVDSB_DATA0

LVDSB_DATA2*

LVDSB_DATA1*

LVDSB_DATA0*

LVDSA_DATA2

LVDSA_DATA0 LVDSA_DATA1

LVDSB_CLK*

LVDS_VREFL

LVDS_IBG

TVC_RTN

TVA_RTN TVB_RTN

TVC_DAC

TVB_DAC

TVA_DAC

CRT_RED*

CRT_RED

CRT_GREEN*

CRT_GREEN

CRT_BLUE*

CRT_BLUE

CRT_VSYNC

CRT_TVO_IREF

CRT_HSYNC

CRT_DDC_CLK

L_BKLT_EN

L_DDC_CLK

TV_DCONSEL0 TV_DCONSEL1

LVDSA_DATA2*

L_DDC_DATA

LVDSA_DATA1*

LVDSA_DATA0*

LVDSB_CLK

LVDSA_CLK

LVDSA_CLK*

LVDS_VREFH

L_CTRL_CLK

LVDS_VBG

VGA

TV

LVDS

(3 OF 10)

PCI-EXPRESS GRAPHICS

BI

OUT

IN

IN IN

IN

IN IN IN IN IN

IN

OUT

IN

OUT

IN

OUT

IN

OUT

OUT OUT

IN

BI BI

OUT OUT OUT OUT

OUT OUT

IN

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

IN

OUT OUT OUT

OUT

BI BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

rails must be filtered except for VCCA_CRT.

Tie DPLL_REF_CLK* and DPLL_REF_SSCLK* to VCC (VCore).

S-Video: DACB & DACC only

share filtering with VCCA_CRT_DAC.

Tie R/R#/G/G#/B/B#, HSYNC and VSYNC to GND.

Tie TVx_DAC, TVx_RTN, R/R#/G/G#/B/B#, HSYNC,

CRT & TV-Out Disable

All CRT/TVDAC rails must be powered. All

VCCA_CRT_DAC, VCCA_DAC_BG, VCCA_TVx_DAC, VCCD_CRT, VCCD_QDAC and VCC_SYNC.

NOTE: Must keep VDDC_TVDAC powered and filtered at all times!

Internal Graphics Disable

Follow instructions for LVDS and CRT & TV-Out Disable above.

TV_DCONSELx to GND.

Can also tie CRT_DDC_*, L_CTRL_*, L_DDC_*, SDVO_CTRL_* and

Tie DPLL_REF_CLK and DPLL_REF_SSCLK to GND.

Tie VCCA_DPLLA and VCCA_DPLLB to VCC (VCore). Tie VCC_AXG and VCC_AXG_NCTF to GND. Leave GFX_VID<3..0> and GFX_VR_EN as NC.

Tie TVx_DAC and TVx_RTN to GND. Must power all

TV-Out Disable / CRT Enable

CRT Disable / TV-Out Enable

VSYNC and CRT_TVO_IREF to GND. Can tie the following rails to GND:

TV-Out Signal Usage: Composite: DACA only

Component: DACA, DACB & DACC

TVDAC rails. VCCA_TVx_DAC and VCCA_DAC_BG can

LVDS Disable

SDVOC_RED SDVOC_GREEN SDVOC_BLUE SDVOC_CLKP

SDVOB_BLUE SDVOB_CLKP

SDVOB_RED# SDVOB_GREEN# SDVOB_BLUE# SDVOB_CLKN SDVOC_RED# SDVOC_GREEN# SDVOC_BLUE# SDVOC_CLKN

SDVOB_RED SDVOB_GREEN

SDVO_FLDSTALL

SDVO_INT

SDVO_TVCLKIN

SDVO_INT#

SDVO_TVCLKIN#

SDVO Alternate Function

SDVO_FLDSTALL#

Tie VCC_TX_LVDS and VCCA_LVDS to GND.

decoupling. Otherwise, tie VCCD_LVDS to GND also.

Can leave all signals NC if LVDS is not implemented.

Unused DAC outputs must remain powered, but can omit filtering components. Unused DAC outputs should connect to GND through 75-ohm resistors.

If SDVO is used, VCCD_LVDS must remain powered with proper

Note: SR DG says to tie LVDS_VREFH/L to GND. This causes a glitch during wake-up on LVDS DATA/CLK pairs. New recommendation is to float both signals, see Radar #5067636.

66 80

R1510

1

2

24.9

1% 1/16W MF-LF 402

77

66 80

22 80

U1400

H32 G32

K33 G35

K29 J29

F33

F29 E29

C32 E33

J40 H39 E39 E40 C37 D35 K40

L41 L43 N41 N40

C45

D46

G50

G51

E50

E51

F48

F49

E42

D44

E44

G44

A47

B47

A45

B45

N43 M43

J50

J51

L50

L51

AC45

AD44

AC41

AD40

AH47

AG46

AG49

AH49

AH45

AG45

AG42

AG41

M47

N47

U44

T45

T49

T50

T41

U40

W45

Y44

W41

Y40

AB50

AB51

Y48

W49

M45

N45

T38

U39

AD47

AC46

AC50

AC49

AD43

AC42

AG39

AH39

AE50

AE49

AH43

AH44

T46

U47

N50

N51

R51

R50

U43

T42

W42

Y43

Y47

W46

Y39

W38

AC38

AD39

M35 P33

E27

F27

G27

J27

K27

L27

FCBGA

CRESTLINE

OMIT

13

66 80

77

66 80

75 77

77 80

66 80

77 80

66 80

SYNC_MASTER=T9_NOME

NB PEG / Video Interfaces

051-7225

14.0.0

8815

SYNC_DATE=03/16/2007

LVDS_BKLT_CTL

LVDS_VDD_EN

PEG_R2D_C_N<15>

PEG_R2D_C_N<14>

PEG_R2D_C_N<13>

PEG_R2D_C_N<12>

PEG_R2D_C_N<11>

PEG_R2D_C_N<10>

PEG_R2D_C_N<9>

PEG_R2D_C_N<8>

PEG_R2D_C_N<7>

PEG_R2D_C_N<6>

PEG_R2D_C_N<5>

PEG_R2D_C_N<4>

PEG_R2D_C_N<3>

PEG_R2D_C_N<2>

PEG_R2D_C_N<1>

PEG_R2D_C_N<0>

PEG_R2D_C_P<15>

PEG_R2D_C_P<14>

PEG_R2D_C_P<13>

PEG_R2D_C_P<12>

PEG_R2D_C_P<11>

PEG_R2D_C_P<10>

PEG_R2D_C_P<9>

PEG_R2D_C_P<8>

PEG_R2D_C_P<7>

PEG_R2D_C_P<6>

PEG_R2D_C_P<5>

PEG_R2D_C_P<4>

PEG_R2D_C_P<3>

PEG_R2D_C_P<2>

PEG_R2D_C_P<1>

PEG_R2D_C_P<0>

PEG_D2R_P<14>

PEG_D2R_N<15>

PEG_D2R_N<14>

PEG_D2R_N<13>

PEG_D2R_N<12>

PEG_D2R_N<11>

PEG_D2R_P<15>

PEG_D2R_P<13>

PEG_D2R_P<12>

PEG_D2R_P<8>

PEG_D2R_P<7>

PEG_D2R_P<6>

PEG_D2R_P<5>

PEG_D2R_P<4>

PEG_D2R_P<3>

PEG_D2R_P<2>

PEG_D2R_P<1>

PEG_D2R_P<0>

PEG_D2R_N<10>

PEG_D2R_N<9>

PEG_D2R_N<8>

PEG_D2R_N<7>

PEG_D2R_N<5>

PEG_D2R_N<4>

PEG_D2R_N<3>

PEG_D2R_N<2>

PEG_D2R_N<0>

PEG_COMP

GND

LVDS_B_DATA_P<1> LVDS_B_DATA_P<2>

LVDS_B_DATA_P<0>

LVDS_B_DATA_N<0>

LVDS_A_DATA_P<2>

LVDS_A_DATA_P<0> LVDS_A_DATA_P<1>

LVDS_B_CLK_N

NC_LVDS_VREFL

LVDS_IBG

GND

LVDS_BKLT_EN

LVDS_CONN_DDC_CLK

GND GND

LVDS_A_DATA_N<2>

LVDS_CONN_DDC_DATA

LVDS_A_DATA_N<1>

LVDS_A_DATA_N<0>

LVDS_B_CLK_P

LVDS_A_CLK_P

LVDS_A_CLK_N

NC_LVDS_VREFH

PEG_D2R_N<6>

PEG_D2R_N<1>

PP1V05_S0_NB_VCCPEG

PEG_D2R_P<10> PEG_D2R_P<11>

PEG_D2R_P<9>

TP_LVDS_VBG

LVDS_CTRL_CLK LVDS_CTRL_DATA

LVDS_B_DATA_N<1> LVDS_B_DATA_N<2>

GND

21

22

19

IN

CLKREQ*

NC1

NC8

CL_CLK

CL_PWROK

CL_RST*

RSVD6

THERMTRIP*

PM_BM_BUSY*

RSVD4

RSVD3

RSVD7

SM_CKE1

SM_CK0*

SM_CKE0

SM_ODT0

SM_ODT2

SM_RCOMP

SM_RCOMP*

SM_VREF0 SM_VREF1

SM_RCOMP_VOL

SM_CS1*

SM_CS0*

RSVD14

RSVD11

RSVD10

RSVD9

RSVD5

RSVD8

RSVD2

DPLL_REF_CLK*

DPLL_REF_SSCLK

PEG_CLK

DMI_RXN1

DMI_RXN0

DMI_RXN3

DMI_RXN2

DMI_RXP0 DMI_RXP1 DMI_RXP2

DMI_TXN0

DMI_RXP3

DMI_TXN2

DMI_TXN1

DMI_TXP0

DMI_TXN3

DMI_TXP1 DMI_TXP2 DMI_TXP3

PEG_CLK*

RSVD12

CL_DATA

CL_VREF

SDVO_CTRL_CLK

SDVO_CTRL_DATA

ICH_SYNC*

TEST1 TEST2

GFX_VID0 GFX_VID1 GFX_VID2

GFX_VR_EN

GFX_VID3

RSVD20 RSVD21

RSVD24 RSVD25

RSVD27

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39

RSVD41 RSVD42

RSVD40

RSVD43 RSVD44 RSVD45

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13

CFG16

CFG15

CFG14

CFG17 CFG18 CFG19 CFG20

PM_DPRSTP* PM_EXT_TS0*

PWROK

PM_EXT_TS1*

RSTIN*

DPRSLPVR

NC2

NC4

NC3

NC5

NC7

NC6

NC10

NC9

NC12

NC11

NC13 NC14 NC15 NC16

DPLL_REF_CLK

SM_RCOMP_VOH

SM_ODT3

SM_ODT1

RSVD13

SM_CS2* SM_CS3*

SM_CK3 SM_CK4

SM_CK4*

SM_CKE3

RSVD1

SM_CKE4

DPLL_REF_SSCLK*

SM_CK3*

SM_CK1*

SM_CK1

SM_CK0

SA_MA14

RSVD22 RSVD23

RSVD26

SB_MA14

SM_CK2 SM_CK2* SM_CK5 SM_CK5*

(2 OF 10)

RSVD

DDR MUXING

CLK

CFG

DMI

PM

GRAPHICS VID

ME

MISC

NC

OUT OUT OUT OUT OUT

BI BI

IN

OUT

BI

BI OUT OUT

IN

OUT

OUT OUT

IN IN IN OUT

OUT OUT OUT

BI

OUT

BI

OUT

IN

OUT

OUT OUT OUT

OUT

OUT OUT OUT

OUT OUT OUT OUT

IN

IN IN

IN

IN IN IN IN

IN IN

IN

OUT

OUT OUT

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NB CFG<8:0> used for debug access

IPU IPU

NB_CFG<4> NB_CFG<5>

DMI x2 Select

NOTE: GMCH CL_PWROK input must be PWRGD signal for PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,

If ME/AMT is not used, short CL_PWROK to PWROK.

PP1V05_S0M, PP0V9_S3M and PP0V9_S0M.

NB_CFG<18>

NB_CFG<15>

FSB Dynamic ODT

NB_CFG<17>

NB_CFG<14>

NB_CFG<16>

NB_CFG<11> NB_CFG<12> NB_CFG<13>

DMI Lane Reversal

SDVO/PCIe x1

Concurrent

NB_CFG<20>

NB_CFG<19>

00 = RESERVED

or PCIe x16

11 = Normal Operation

High = Reversed

Low = Only SDVO

NB_CFG<13:12>

High = Both active

Low = Normal

01 = XOR Mode Enabled 10 = All-Z Mode Enabled

High = Enabled Low = Disabled

See Below See Below

RESERVED

Lane Reversal

PCIe Graphics

NB_CFG<9>

NB_CFG<10>

Low = Reversed

High = Normal

RESERVED

NB_CFG<7>

High = DMIx4

NB_CFG<6>

RESERVED

IPU

Clk used for PEG and DMI

IPD IPD

IPD

IPU

NB_CFG<8>

NB_CFG<3>

Low = DMIx2

RESERVED

IPU

NB CFG<13:12> require ICT access

7

28

8

16 31 32 62

C1616

1

2

10V

0.1uF

20% CERM

402

C1615

1

2

10V

0.1uF

20%

CERM

402

U1400

P27 N27

R24 L23 J23 E23 E20 K23 M20 M24 L32 N33

N24

L35

C21 C23 F23 N23 G23 J20 C20

AM49 AK50 AT43 AN49 AM50

G39

AN47 AJ38 AN42 AN46

AM47 AJ39 AN41 AN45

AJ46 AJ41 AM40 AM44

AJ47 AJ42 AM39 AM43

B42 C42 H48 H47

G36

E35 A39 C38 B39 E36

G40

BJ51

E1

A5 C51 B50 A50 A49 BK2

BK51 BK50 BL50 BL49

BL3 BL2 BK1 BJ1

K44 K45

G41 L39 L36 J36

AW49 AV20

P36

AR37 AM36 AL36 AM37

D20

P37

H10 B51

BJ20 BK22 BF19 BH20 BK18 BJ18

R35

BH39 AW20 BK20

C48 D47 B44

N35

C44 A35 B37 B36 B34 C34

AR12 AR13 AM12 AN13

J12

BJ29 BE24

H35 K36

AV29

AW30

BB23

BA23

BF23 BG23

BA25

AW25

AV23

AW23

BC23 BD24

BE29 AY32 BD39 BG37

BG20 BK16 BG16 BE13

BH18 BJ15 BJ14 BE16

BL15 BK14

BK31 BL31

AR49 AW4

A37 R32

N20

OMIT

FCBGA

CRESTLINE

9

59

25 83

7 9

16 28 58

25 83

7

29

7

25

R1691

1

2

5% 1/16W MF-LF

20K

402

R1690

1

2

5% 1/16W MF-LF

0

402

7

25 58 79

32 45

R1631

1

2

1/16W

5% MF-LF

10K

402

C1625

1

2

402

CERM

16V

10%

0.01UF

C1624

1

2

20% CERM1

6.3V

2.2UF

603

R1624

1

2

402

1/16W

1% MF-LF

1K

R1622

1

2

3.01K

MF-LF

1/16W

1%

402

C1622

1

2

20%

2.2UF

CERM1

6.3V 603

C1623

1

2

402

CERM

16V

10%

0.01UF

R1620

1

2

MF-LF

1% 1/16W

402

1K

R1641

1

2

1% 1/16W MF-LF

392

402

R1640

1

2

1%

1K

1/16W MF-LF 402

C1640

1

2

0.1uF

CERM

10V

20%

402

R1655

1

2

NBCFG_DMI_X2

1/16W MF-LF

3.9K

5%

402

R1659

1

2

NBCFG_PEG_REVERSE

3.9K

MF-LF

1/16W

5%

402

R1666

1

2

MF-LF

5% 1/16W

3.9K

NBCFG_DYN_ODT_DISABLE

402

R1669

1

2

NBCFG_DMI_REVERSE

5% 1/16W MF-LF

3.9K

402

R1670

1

2

NBCFG_SDVO_AND_PCIE

3.9K

MF-LF

1/16W

5%

402

31 33 81

32 33 81

13 30 79

13

13 16

25

13

10 23 46 79

31 45

7

10 23 58 79

7 9

16 28 58

31 81

32 81

31 81

32 81

31 81

31 33 81

32 33 81

31 33 81

32 33 81

31 33 81

32 33 81

31 33 81

32 33 81

R1610

1

2

402

20

1% 1/16W MF-LF

R1611

1

2

402

20

MF-LF

1% 1/16W

8

16 31 32 62

7

29 30 84

7

29 30 84

8

18 21 22 50

7

22 29 30 84

7

22 29 30 84

24 80

R1630

1

2

10K

5% 1/16W MF-LF

402

NB Misc Interfaces

SYNC_DATE=03/16/2007

SYNC_MASTER=T9_NOME

16 88

14.0.0

051-7225

TP_LVDS_A_DATAP3

TP_NB_RSVD<34>

MEM_B_A<14>

TP_NB_RSVD<27>

TP_NB_RSVD<26>

TP_NB_RSVD<25>

NB_CLK100M_DPLLSS_P NB_CLK100M_DPLLSS_N

NB_BSEL<0>

NB_CFG<5>

MEM_CKE<4>

TP_NB_RSVD<1>

MEM_CLK_P<0>

MEM_CLK_N<4>

MEM_CLK_N<3>

MEM_CLK_P<4>

MEM_CLK_P<3>

TP_NB_RSVD<13>

TP_NB_NC<16>

TP_NB_NC<15>

TP_NB_NC<14>

TP_NB_NC<13>

TP_NB_NC<11> TP_NB_NC<12>

TP_NB_NC<9> TP_NB_NC<10>

TP_NB_NC<6> TP_NB_NC<7>

TP_NB_NC<5>

TP_NB_NC<3>

TP_NB_NC<2>

PM_EXTTS_L<0>

NB_CFG<20>

NB_CFG<19>

TP_NB_CFG<18>

TP_NB_CFG<14> TP_NB_CFG<15> NB_CFG<16>

TP_NB_CFG<12>

TP_NB_CFG<10>

TP_NB_RSVD<41>

TP_NB_RSVD<23>

TP_NB_RSVD<22>

TP_NB_RSVD<21>

TP_NB_RSVD<20>

NB_TEST2

NB_TEST1

TP_NB_RSVD<2>

TP_NB_RSVD<8> TP_NB_RSVD<9> TP_NB_RSVD<10> TP_NB_RSVD<11>

MEM_CS_L<0> MEM_CS_L<1>

MEM_CKE<0>

MEM_CLK_N<1>

MEM_CLK_P<1>

MEM_CLK_N<0>

TP_NB_RSVD<7>

TP_NB_RSVD<3> TP_NB_RSVD<4>

TP_NB_NC<8>

TP_NB_NC<1>

GND

NB_CLK100M_PCIE_P NB_CLK100M_PCIE_N

DMI_S2N_P<0> DMI_S2N_P<1> DMI_S2N_P<2>

DMI_N2S_N<0> DMI_N2S_N<1>

DMI_N2S_N<3>

DMI_N2S_N<2>

DMI_N2S_P<0> DMI_N2S_P<1> DMI_N2S_P<2> DMI_N2S_P<3>

GFX_VID<2>

CLINK_NB_DATA VR_PWRGOOD_DELAY CLINK_NB_RESET_L

GND GND NB_CLKREQ_L NB_SB_SYNC_L

TP_MEM_CLKN2 TP_MEM_CLKP5 TP_MEM_CLKN5

PM_BMBUSY_L CPU_DPRSTP_L

VR_PWRGOOD_DELAY

PM_THRMTRIP_L

MEM_CS_L<2>

MEM_ODT<2> MEM_ODT<3>

PPVCORE_S0_NB_R

MEM_CS_L<3> MEM_ODT<0>

MEM_ODT<1>

TP_NB_RSVD<6>

TP_NB_RSVD<12>

TP_NB_NC<4>

GFX_VID<4>

DMI_S2N_P<3>

DMI_S2N_N<2>

PP0V9_S3_MEM_VREF

TP_NB_RSVD<5>

TP_NB_RSVD<24>

TP_MEM_CLKP2

TP_LVDS_A_DATAN3

TP_LVDS_B_DATAP3

MEM_A_A<14>

DMI_S2N_N<0>

TP_NB_RSVD<35> TP_NB_RSVD<36>

TP_LVDS_B_DATAN3

TP_NB_RSVD<45>

TP_NB_RSVD<42>

DMI_S2N_N<3>

DMI_S2N_N<1>

TP_NB_RSVD<14>

PM_DPRSLPVR

NB_RESET_L

PM_EXTTS_L<1>

NB_CFG<9>

NB_CFG<16>

PP3V3_S0

NB_CFG<19>

NB_CFG<20>

PP3V3_S0

TP_NB_CFG<11>

TP_NB_CFG<13>

GFX_VID<3>

GFX_VR_EN

PP3V3_S0

TP_NB_CFG<17>

GFX_VID<1>

CLINK_NB_CLK

PP1V25_S0M_NB_VCCAXD

GND

NB_CLINK_VREF

NB_BSEL<2>

NB_BSEL<1>

NB_CFG<3>

NB_CFG<6> NB_CFG<7> NB_CFG<8> NB_CFG<9>

NB_CFG<5>

MEM_RCOMP_L

TP_NB_RSVD<43> TP_NB_RSVD<44>

NB_CFG<4>

MEM_CKE<1> MEM_CKE<3>

PP0V9_S3_MEM_VREF

MEM_RCOMP_VOL

MEM_RCOMP

PP1V8_S3_ISNS

MEM_RCOMP_VOH

87

77

75

74

65

59

58

57

52

51

50

48

47

46

42

32

31

30

29

28

27

26

25

24

23

21

57

19

50

16

21

16

13

21

18

13

7

16

7

16

8

16

8

19

83

16

8

BI

BI BI BI BI BI

OUT

BI

OUT

BI BI BI

BI

BI BI BI BI

BI BI

BI BI BI BI BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI

BI

BI BI BI BI BI

BI BI

BI

OUT

BI

OUT

OUT OUT

OUT

OUT OUT

OUT

BI

OUT

BI

BI BI BI

BI

BI BI BI

BI BI

BI

BI BI

OUT

BI

OUT OUT

OUT

BI

OUT

SA_DQ0 SA_DQ1 SA_DQ2

SA_DQ4

SA_DQ6

SA_DQ14

SA_CAS*

SA_BS2

SA_DQ63

SA_DQ62

SA_DQ61

SA_DQ60

SA_DQ59

SA_DQ58

SA_DQ57

SA_DQ56

SA_DQ55

SA_DQ54

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ47

SA_DQ46

SA_DQ44

SA_DQ43

SA_DQ42

SA_DQ41

SA_DQ40

SA_DQ39

SA_DQ38

SA_DQ37

SA_DQ36

SA_DQ34 SA_DQ35

SA_DQ33

SA_DQ32

SA_DQ31

SA_DQ30

SA_DQ28 SA_DQ29

SA_DQ27

SA_DQ26

SA_DQ25

SA_DQ24

SA_DQ23

SA_DQ22

SA_DQ21

SA_DQ20

SA_DQ19

SA_DQ18

SA_DQ17

SA_DQ16

SA_DQ15

SA_DQ13

SA_DQ11 SA_DQ12

SA_DQ10

SA_DQ9

SA_DQ8

SA_DQ7

SA_DQ5

SA_DQ3

SA_BS1

SA_BS0

SA_DQ45

SA_DM0 SA_DM1

SA_DM3

SA_DM2

SA_DM5

SA_DM4

SA_DM7

SA_DM6

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_DQS1*

SA_DQS0*

SA_DQS2*

SA_DQS4*

SA_DQS3*

SA_DQS5* SA_DQS6* SA_DQS7*

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7

SA_MA9

SA_MA8

SA_MA10 SA_MA11 SA_MA12 SA_MA13

SA_RAS*

SA_RCVEN*

SA_WE*

DDR SYSTEM MEMORY A

(4 OF 10)

SB_DQ2

SB_DQ1

SB_DQ5

SB_DM0

SB_DQ0

SB_DQ4

SB_DQ6 SB_DQ7

SB_CAS*

SB_BS2

SB_BS0 SB_BS1

SB_DQ63

SB_DQ62

SB_DQ59

SB_DQ58

SB_DQ56

SB_DQ55

SB_DQ54

SB_DQ53

SB_DQ52

SB_DQ51

SB_DQ50

SB_DQ49

SB_DQ48

SB_DQ47

SB_DQ45 SB_DQ46

SB_DQ44

SB_DQ43

SB_DQ42

SB_DQ41

SB_DQ40

SB_DQ39

SB_DQ38

SB_DQ37

SB_DQ36

SB_DQ34 SB_DQ35

SB_DQ33

SB_DQ32

SB_DQ31

SB_DQ30

SB_DQ28 SB_DQ29

SB_DQ27

SB_DQ26

SB_DQ25

SB_DQ24

SB_DQ23

SB_DQ22

SB_DQ21

SB_DQ20

SB_DQ19

SB_DQ18

SB_DQ17

SB_DQ16

SB_DQ15

SB_DQ14

SB_DQ13

SB_DQ11 SB_DQ12

SB_DQ10

SB_DQ9

SB_DQ8

SB_DQ3

SB_DQ57

SB_DQ61

SB_DQ60

SB_WE*

SB_RCVEN*

SB_RAS*

SB_MA13

SB_MA12

SB_MA11

SB_MA10

SB_MA8 SB_MA9

SB_MA7

SB_MA6

SB_MA5

SB_MA4

SB_MA3

SB_MA2

SB_MA1

SB_MA0

SB_DQS7*

SB_DQS6*

SB_DQS5*

SB_DQS3* SB_DQS4*

SB_DQS2*

SB_DQS0* SB_DQS1*

SB_DQS7

SB_DQS6

SB_DQS5

SB_DQS4

SB_DQS3

SB_DQS2

SB_DQS1

SB_DQS0

SB_DM6 SB_DM7

SB_DM4 SB_DM5

SB_DM2 SB_DM3

SB_DM1

(5 OF 10)

DDR SYSTEM MEMORY B

BI

OUT OUT OUT

BI

OUT

BI

OUT

BI

BI BI BI BI BI BI BI BI BI BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

31 81

32 81

31 81 32 81

32 81

31 81

32 81

31 81

32 81

31 81

32 81

31 81

32 81

31 81

32 81

32 33 81

31 81

32 33 81

31 81

32 33 81

32 81

31 81

32 81

31 81

32 81

32 33 81

31 81

32 33 81

U1400

BB19 BK19 BF29

BL17

AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6

AR43 AW44

BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40

BA45

BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41

AY46

AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11

AR41

BE10 BD10

BD8 AY9

BG10

AW9 BD7 BB9 BB5 AY7

AR45

AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8

AN10

AT42

AT9 AN9 AM9

AN11

AW47 BB45 BF48

AT46

AT47

BE48

BD47

BB43

BC41

BC37

BA37

BB16

BA16

BH6

BH7

BB2

BC1

AP3

AP2

BJ19 BD20

BC19 BE28 BG30 BJ16

BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28

BE18 AY20

BA19

OMIT

CRESTLINE

FCBGA

U1400

AY17 BG18 BG36

BE17

AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2

AP49 AR51

BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43

AW50

BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40

AW51

BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12

AN51

BJ10

BL9 BK5 BL5 BK9

BK10

BJ8 BJ6 BF4 BH5

AN50

BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3

AV50

AY2 AY3 AU2 AT2

AV49 BA50 BB50

AT50

AU50

BD50

BC50

BK46

BL45

BK39

BK38

BJ12

BK12

BL7

BK7

BE2

BF2

AV2

AV3

BC18 BG28

BG17 BE37 BA39 BG13

BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37

AV16 AY18

BC17

OMIT

CRESTLINE

FCBGA

31 81

31 33 81

31 81

31 33 81

31 81

31 33 81

31 81

31 33 81

31 81

17 88

14.0.0

051-7225

NB DDR2 Interfaces

SYNC_MASTER=T9_NOME

SYNC_DATE=03/16/2007

MEM_A_DQ<35>

TP_MEM_A_RCVEN_L TP_MEM_B_RCVEN_L

MEM_B_DQ<39>

MEM_B_BS<0> MEM_B_BS<1> MEM_B_BS<2>

MEM_B_DM<0>

MEM_B_CAS_L

MEM_B_DM<1> MEM_B_DM<2>

MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8>

MEM_B_DM<3> MEM_B_DM<4> MEM_B_DM<5> MEM_B_DM<6> MEM_B_DM<7>

MEM_B_DQS_P<1>

MEM_B_DQS_P<0>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<2>

MEM_B_DQS_P<6>

MEM_B_DQS_P<5>

MEM_B_DQS_N<1>

MEM_B_DQS_P<7> MEM_B_DQS_N<0>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<4>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<7>

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12>

MEM_B_RAS_L

MEM_B_A<13>

MEM_B_WE_L

MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38>

MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>

MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2>

MEM_A_DQ<4>

MEM_A_DQ<6>

MEM_A_CAS_L

MEM_A_BS<2>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<5>

MEM_A_DQ<3>

MEM_A_BS<1>

MEM_A_BS<0>

MEM_A_DM<0> MEM_A_DM<1>

MEM_A_DM<3>

MEM_A_DM<2>

MEM_A_DM<5>

MEM_A_DM<4>

MEM_A_DM<7>

MEM_A_DM<6>

MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2> MEM_A_DQS_P<3> MEM_A_DQS_P<4> MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQS_N<2>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7>

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34>

MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

VCC_SM20

VCC_AXG_NCTF42

VCC_SM9

VCC_SM10

VCC_SM17

VCC_SM16

VCC3

VCC_SM5

VCC_SM8

VCC_AXG_NCTF1 VCC_AXG_NCTF2 VCC_AXG_NCTF3 VCC_AXG_NCTF4 VCC_AXG_NCTF5 VCC_AXG_NCTF6

VCC_AXG_NCTF8

VCC_AXG_NCTF7

VCC_AXG_NCTF10

VCC_AXG_NCTF9

VCC_AXG_NCTF11 VCC_AXG_NCTF12 VCC_AXG_NCTF13 VCC_AXG_NCTF14 VCC_AXG_NCTF15 VCC_AXG_NCTF16

VCC_AXG_NCTF18

VCC_AXG_NCTF17

VCC_AXG_NCTF20

VCC_AXG_NCTF19

VCC_AXG_NCTF21 VCC_AXG_NCTF22

VCC_AXG_NCTF25 VCC_AXG_NCTF26

VCC_AXG_NCTF28

VCC_AXG_NCTF27

VCC_AXG_NCTF29 VCC_AXG_NCTF20 VCC_AXG_NCTF31 VCC_AXG_NCTF32 VCC_AXG_NCTF33 VCC_AXG_NCTF34 VCC_AXG_NCTF35 VCC_AXG_NCTF36

VCC_AXG_NCTF38

VCC_AXG_NCTF37

VCC_AXG_NCTF40

VCC_AXG_NCTF39

VCC_AXG_NCTF41

VCC_AXG_NCTF43 VCC_AXG_NCTF44 VCC_AXG_NCTF45 VCC_AXG_NCTF46

VCC_AXG_NCTF48

VCC_AXG_NCTF47

VCC_AXG_NCTF49 VCC_AXG_NCTF50 VCC_AXG_NCTF51

VCC_AXG_NCTF55

VCC_AXG_NCTF58

VCC_AXG_NCTF57

VCC_AXG_NCTF59

VCC_AXG_NCTF61

VCC_AXG_NCTF60

VCC_AXG_NCTF62 VCC_AXG_NCTF63 VCC_AXG_NCTF64

VCC_AXG_NCTF66

VCC_AXG_NCTF65

VCC_AXG_NCTF67 VCC_AXG_NCTF68 VCC_AXG_NCTF69

VCC_AXG_NCTF71

VCC_AXG_NCTF70

VCC_AXG_NCTF72 VCC_AXG_NCTF73 VCC_AXG_NCTF74

VCC_AXG_NCTF76

VCC_AXG_NCTF75

VCC_AXG_NCTF77 VCC_AXG_NCTF78 VCC_AXG_NCTF79

VCC_AXG_NCTF81

VCC_AXG_NCTF80

VCC_AXG_NCTF82 VCC_AXG_NCTF83

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC_AXG_NCTF56

VCC_AXG_NCTF54

VCC_AXG_NCTF53

VCC_AXG_NCTF52

VCC_AXG1

VCC_AXG2

VCC_AXG3

VCC_AXG4

VCC_AXG5

VCC_AXG6

VCC_AXG7

VCC_AXG8

VCC_AXG9

VCC_AXG10

VCC_AXG11

VCC_AXG12

VCC_AXG13

VCC_AXG14

VCC_AXG15

VCC_AXG16

VCC_AXG17

VCC_AXG18

VCC_AXG19

VCC_AXG20

VCC_AXG21

VCC_AXG22

VCC_AXG23

VCC_AXG24

VCC_AXG25

VCC_AXG26

VCC_AXG27

VCC_AXG28

VCC_AXG29

VCC_AXG30

VCC_AXG31

VCC_AXG32

VCC_AXG33

VCC_AXG34

VCC_SM1

VCC_SM2

VCC_SM3

VCC_SM4

VCC_SM6

VCC_SM7

VCC_SM11

VCC_SM12

VCC_SM13

VCC_SM14

VCC_SM15

VCC_SM18

VCC_SM19

VCC_SM21

VCC_SM22

VCC_SM23

VCC_SM26

VCC_SM27

VCC_SM28

VCC_SM29

VCC_SM30

VCC_SM31

VCC_SM32

VCC_SM33

VCC_SM34

VCC_SM35

VCC_SM36

VCC_SM25

VCC_SM24

VCC1

VCC2

VCC7

VCC8

VCC9

VCC10

VCC11

VCC12

VCC13

VCC_AXG_NCTF24

VCC_AXG_NCTF23

VCC6

VCC5

VCC4

VCC GFX

VCC SM

VCC SM LF

(6 OF 10)

VCC CORE

POWER

VCC GFX NCTF

VCC_NCTF49

VCC_NCTF15

VCC_NCTF2

VCC_NCTF10

VCC_AXM7

VCC_AXM5

VCC_AXM4

VCC_AXM3

VCC_AXM2

VCC_AXM1

VSS_SCB6

VSS_SCB5

VSS_SCB4

VSS_SCB3

VSS_SCB2

VSS_SCB1

VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14

VSS_NCTF21

VSS_NCTF20

VSS_NCTF19

VSS_NCTF18

VSS_NCTF17

VSS_NCTF16

VSS_NCTF15

VSS_NCTF14

VSS_NCTF12

VSS_NCTF11

VSS_NCTF13

VSS_NCTF10

VSS_NCTF9

VSS_NCTF8

VSS_NCTF7

VSS_NCTF6

VSS_NCTF5

VSS_NCTF4

VSS_NCTF3

VSS_NCTF2

VSS_NCTF1

VCC_NCTF22

VCC_NCTF27

VCC_NCTF50

VCC_NCTF47 VCC_NCTF48

VCC_NCTF44

VCC_NCTF43

VCC_NCTF39 VCC_NCTF40

VCC_NCTF38

VCC_NCTF37

VCC_NCTF34 VCC_NCTF35

VCC_NCTF33

VCC_NCTF32

VCC_NCTF31

VCC_NCTF29

VCC_NCTF28

VCC_NCTF26

VCC_NCTF24 VCC_NCTF25

VCC_NCTF23

VCC_NCTF21

VCC_NCTF18 VCC_NCTF19

VCC_NCTF16 VCC_NCTF17

VCC_NCTF3 VCC_NCTF4

VCC_NCTF41 VCC_NCTF42

VCC_NCTF45 VCC_NCTF46

VCC_AXM6

VCC_AXM_NCTF1 VCC_AXM_NCTF2 VCC_AXM_NCTF3 VCC_AXM_NCTF4 VCC_AXM_NCTF5 VCC_AXM_NCTF6 VCC_AXM_NCTF7 VCC_AXM_NCTF8 VCC_AXM_NCTF9 VCC_AXM_NCTF10 VCC_AXM_NCTF11 VCC_AXM_NCTF12 VCC_AXM_NCTF13 VCC_AXM_NCTF14 VCC_AXM_NCTF15 VCC_AXM_NCTF16 VCC_AXM_NCTF17 VCC_AXM_NCTF18 VCC_AXM_NCTF19

VCC_NCTF8

VCC_NCTF20

VCC_NCTF1

VCC_NCTF5 VCC_NCTF6 VCC_NCTF7

VCC_NCTF36

VCC_NCTF30

VCC_NCTF9

VCC AXM NCTF

VCC NCTF

VSS SCBVCC AXM

VSS NCTF

(7 OF 10)

POWER

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

1395 mA (1 ch, 533MHz)

1700 mA (1 ch, 667MHz)

2700 mA (2 ch, 533MHz)

3300 mA (2 ch, 667MHz)

540 mA

1573 mA (Int Graphics)

1310 mA (Ext Graphics)

7700 mA (Int Graphics)

5 mA (standby)

impacting part performance.

These connections can break without

NCTF balls are Not Critical To Function

Current numbers from Crestline EDS, doc #21749.

U1400

AT35

AH31 AH29 AF32

R30

AT34 AH28

AC31

AC32

AK32 AJ31 AJ28 AH32

R20

AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29

T14

AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23

W13

AH24 AH26 AD31 AJ20 AN14

W14

Y12 AA20 AA23 AA26 AA28

T17

U17 U19 U20 U21 U23 U26 V16 V17 V19 V20

T18

V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23

T19

Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17

T21

AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19

T22

AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21

T23

AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17

T25

AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26

U15

V26 V28 V29 Y31

U16

AU32

BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35

AU33

BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33

AU35

BJ34 BK32 BK33 BK34 BK35 BL33 AU30

AV33 AW33 AW35 AY35 BA32 BA33

AW45 BC39 BE39 BD17 BD4 AW8 AT6

OMIT

CRESTLINE

FCBGA

U1400

AT33 AT31 AK29 AK24 AK23 AJ26 AJ23

AL24

AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33

AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33

AB33

AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36

AB36

AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35

AB37

AP36 AR35 AR36

Y32 Y33 Y35 Y36 Y37 T30 T34

AC33

T35 U29 U31 U32 U33 U35 U36 V32 V33 V36

AC35

V37

AC36 AD35 AD36 AF33

T27

AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15

T37

AR19 AR28

U24 U28 V31 V35 AA19 AB17 AB35

A3 B2 C1 BL1 BL51 A51

OMIT

CRESTLINE

FCBGA

C1806

1

2

402

0.1uF

10V

CERM

20%

C1807

1

2

402

0.1uF

10V

CERM

20%

C1804

1

2

402

X5R

0.22UF

6.3V

20%

C1805

1

2

402

X5R

0.22UF

6.3V

20%

C1802

1

2

402

10%

CERM

1uF

6.3V

C1803

1

2

402

10%

0.47UF

6.3V

CERM-X5R

C1801

1

2

402

10%

CERM

1uF

6.3V

18 88

14.0.0

051-7225

NB Power 1

SYNC_DATE=03/16/2007

SYNC_MASTER=T9_NOME

PP1V05_S0

NB_VCCSM_LF5

NB_VCCSM_LF7

PPVCORE_S0_NB_R

PP1V05_S0

NB_VCCSM_LF1 NB_VCCSM_LF2 NB_VCCSM_LF3 NB_VCCSM_LF4

NB_VCCSM_LF6

PPVCORE_S0_NB_GFX

PPVCORE_S0_NB_R

PPVCORE_S0_NB_GFX

PP1V8_S3_ISNS

61

50

46

30

27

26

23

21

19

18

14

50

14

50

13

22

13

59

22 59

57

12

21

12

22

21 22

50

11

18

11

18

18 18

21

10

16

10

8

16

8

16

8

7

8 7

8

VCCA_CRT_DAC1

VTT7 VTT8

VCC_AXD_NCTF

VCCD_CRT

VCC_RXR_DMI1 VCC_RXR_DMI2

VTT1

VCCA_SM_CK2 VCC_TX_LVDS

VCC_HV2

VCC_PEG1 VCC_PEG2 VCC_PEG3

VCC_AXF2

VCC_AXD1 VCC_AXD2

VSSA_LVDS

VCCA_SM5

VCCA_PEG_PLL

VCCA_MPLL

VCCA_HPLL VTT16

VTT17

VTT15

VCCD_LVDS2

VCCD_LVDS1

VCCD_PEG_PLL

VCCD_HPLL

VCCD_QDAC

VCCD_TVDAC

VCCA_TVC_DAC1 VCCA_TVC_DAC2

VCCA_TVB_DAC2

VCCA_TVB_DAC1

VCCA_TVA_DAC2

VCCA_TVA_DAC1

VCCA_SM_CK1

VCCA_SM2

VCCA_SM1

VCCA_SM_NCTF2

VCCA_SM_NCTF1

VCCA_SM11

VCCA_SM10

VCCA_SM9

VCCA_SM8

VCCA_SM7

VCCA_SM4

VCCA_SM3

VSSA_PEG_BG

VCCA_PEG_BG

VCCA_LVDS

VCCA_DPLLB

VCCA_DPLLA

VSSA_DAC_BG

VCCA_DAC_BG

VCC_AXF3

VCC_HV1

VCC_PEG5

VTTLF1

VTTLF3

VTTLF2

VCC_PEG4

VCC_SM_CK3

VCC_SM_CK2

VCC_SM_CK1

VCC_SM_CK4

VCC_DMI

VCC_AXF1

VTT22

VCC_AXD6

VCC_AXD5

VCC_AXD4

VCC_AXD3

VTT19

VTT2

VTT6

VTT5

VTT11

VTT10

VTT9

VTT13

VTT12

VTT14

VTT18

VTT21

VTT20

VTT3 VTT4VCCA_CRT_DAC2

VCC_SYNC

CRT

AXD

PEG

HV

AXF

VTTLF

VTT

SM CK

DMI

TV/CRT

D

LVDS

A SMA CK

CRT A LVDS

A PEG

PLL

(8 OF 10)

POWER

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

550 mA (533MHz DDR)

640 mA (667MHz DDR)

Current numbers from Crestline EDS, doc #21749.

515 mA

495 mA

850 mA @ 800MHz FSB (1.05V)

35 mA

100 mA

60 mA

30 mA

80 mA

0.4 mA

260 mA

1260 mA

770 mA @ 667MHz FSB (1.05V)

150 mA

TBD mA @ 1067MHz FSB (1.25V)

S0 or S3M is acceptable

5 mA

150 mA

250 mA

60 mA

40 mA

10 mA

100 mA

50 mA

5 mA

200 mA

100 mA

C1911

1

2

0.47UF

10% CERM-X5R

402

6.3V

C1913

1

2

0.47UF

10%

6.3V CERM-X5R 402

C1912

1

2

0.47UF

10%

6.3V CERM-X5R 402

U1400

AT23 AU28 AU24 AT29 AT25 AT30

AR29

B23 B21 A21

AJ50

C40 B40

AD51 W50 W51 V49 V50

AH50 AH51

BK24 BK23 BJ24 BJ23

J32

A43

A33 B33

A30

B49

H49

AL2

A41

AM2

K50

U51

AW18

AT18 AT17

AV19 AU19 AU18 AU17

AT22 AT21 AT19

BC29 BB29

AR17 AR16

C25 B25 C27 B27 B28 A28

M32

AN2

J41 H42

U48

N28

L29

B32

B41

K49

U13

U1 T13 T11 T10 T9 T7 T6 T5 T3 T2

U12

R3 R2 R1

U11 U9 U8 U7 U5 U3 U2

A7 F2 AH1

OMIT

FCBGA

CRESTLINE

051-7225

14.0.0

8819

NB Power 2

SYNC_DATE=03/16/2007

SYNC_MASTER=T9_NOME

NB_VTTLF_CAP2

PP1V8_S0

PP1V25_S0_NB_VCCA_DPLLA

PP1V25_S0M_NB_VCCA_HPLL

GND

GND PP1V5_S0_NB_VCCD_TVDAC

GND

PP1V25_S0

GND

PP1V25_S0M_NB_VCCA_MPLL

NB_VTTLF_CAP1

NB_VTTLF_CAP3

PP1V25_S0

GND

PP1V8_S0_NB_VCCTXLVDS

PP1V05_S0_NB_VCCPEG

PP3V3_S0

PP1V05_S0_NB_VCCPEG

PP1V25_S0_NB_VCCAXF

PP1V25_S0M_NB_VCCAXD

GND

PP1V25_S0_NB_VCCA_DPLLB

GND

PP1V05_S0

PP1V8_S0_NB_VCCTXLVDS

GND

PP1V25_S0M_NB_VCCA_SM_CK

PP1V25_S0_NB_PEGPLL

PP1V8_S3M_NB_VCCSMCK

PP1V25_S0M_NB_VCCA_SM

PP3V3_S0

87

77

75

74

65

59

58

57

52

51

50

48

47

46

42

32

61

32

31

50

31

30

46

30

29

30

29

28

27

28

27

26

27

26

23

26

25

21

25

65

24

18

24

57

23

14

23

27

21

13

21

65

26

19

12

19

57

21

16

21

11

16

22

19

22

19

13

19

21

10

22

13

8

22

21

22

8

21

8

19

15

8

15

21

16

22

8

19

21

8

VSS198VSS99

VSS197VSS98

VSS196VSS97

VSS195VSS96

VSS194VSS95

VSS193VSS94

VSS192VSS93

VSS191VSS92

VSS190VSS91

VSS189VSS90

VSS188VSS89

VSS187VSS88

VSS186VSS87

VSS185VSS86

VSS184VSS85

VSS183VSS84

VSS182VSS83

VSS181VSS82

VSS180VSS81

VSS179VSS80

VSS178VSS79

VSS177VSS78

VSS176VSS77

VSS175VSS76

VSS174VSS75

VSS173VSS74

VSS172VSS73

VSS171VSS72

VSS170VSS71

VSS169VSS70

VSS168VSS69

VSS167VSS68

VSS166VSS67

VSS165VSS66

VSS164VSS65

VSS163VSS64

VSS162VSS63

VSS161VSS62

VSS160VSS61

VSS159VSS60

VSS158VSS59

VSS157VSS58

VSS156VSS57

VSS155VSS56

VSS154VSS55

VSS153VSS54

VSS152VSS53

VSS151VSS52

VSS150VSS51

VSS149VSS50

VSS148VSS49

VSS147VSS48

VSS146VSS47

VSS145VSS46

VSS144VSS45

VSS143VSS44

VSS142VSS43

VSS141VSS42

VSS140VSS41

VSS139VSS40

VSS138VSS39

VSS137VSS38

VSS136VSS37

VSS135VSS36

VSS134VSS35

VSS133VSS34

VSS132VSS33

VSS131VSS32

VSS130VSS31

VSS129VSS30

VSS128VSS29

VSS127VSS28

VSS126VSS27

VSS125VSS26

VSS124VSS25

VSS123VSS24

VSS122VSS23

VSS121VSS22

VSS120VSS21

VSS119VSS20

VSS118VSS19

VSS117

VSS116VSS17

VSS115VSS16

VSS114VSS15

VSS113VSS14

VSS112VSS13

VSS111VSS12

VSS110VSS11

VSS109VSS10

VSS108VSS9

VSS107VSS8

VSS106VSS7

VSS105VSS6

VSS104VSS5

VSS103VSS4

VSS102

VSS101

VSS100VSS1

VSS18

VSS2 VSS3

VSS

(9 OF 10)

VSS202

VSS289 VSS290 VSS291 VSS292

VSS295

VSS199 VSS287 VSS200 VSS288 VSS201

VSS203 VSS204

VSS293 VSS294

VSS208 VSS296 VSS209 VSS297 VSS210 VSS298 VSS211 VSS299 VSS212 VSS300 VSS213 VSS301 VSS214 VSS215 VSS216 VSS302 VSS217 VSS218 VSS219 VSS303 VSS220 VSS221 VSS222 VSS304 VSS223 VSS224 VSS225 VSS305 VSS226 VSS227 VSS228 VSS229 VSS306 VSS230 VSS307 VSS231 VSS308 VSS232 VSS309 VSS233 VSS310 VSS234 VSS311 VSS235 VSS312 VSS236 VSS313 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243

VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286

VSS207

VSS206

VSS205

(10 OF 10)

VSS

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NOTE: TDE = _P

Crestline Thermal Diode Pins

TDB_SENSE

NOTE: TDB = _N

Mainly for investigation. If not used, alias these nets directly to GND.

TDB_FORCE

TDE_FORCE

TDE_SENSE

U1400

A13

AB26

AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43

AB28 AY45

AY47 AY50 B10 B20 B24 B29 B30 B35 B38

AB31

B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12

AC10

BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40

AC13

BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23

AC3

BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24

AC39

BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8

AC43

BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29

AC47

BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37

AD1

BL47 C12 C16 C19 C28 C29 C33 C36 C41

A15

AD21 AD26 AD29

AD3 AD41 AD45 AD49

AD5 AD50

AD8

A17

AE10 AE14

AE6 AF20 AF23 AF24 AF31

AG2 AG38 AG43

A24

AG47 AG50

AH3 AH40 AH41

AH7

AH9 AJ11 AJ13 AJ21

AA21

AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28

AA24

AK31 AK51

AL1 AM11 AM13

AM3

AM4 AM41 AM45

AN1

AA29

AN38 AN39 AN43

AN5

AN7

AP4 AP48 AP50 AR11

AR2

AB20

AR39 AR44 AR47

AR7 AT10 AT14 AT41 AT49

AU1 AU23

AB23

AU29

AU3 AU36 AU49 AU51 AV39 AV48

AW1 AW12 AW16

FCBGA

OMIT

CRESTLINE

U1400

C46 C50

C7 D13 D24

D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36

F4 F40 F50

G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48

G8 H24 H28

H4 H45 J11 J16

J2 J24 J28 J33 J35 J39

K12 K47

K8

L1 L17 L20 L24 L28

L3 L33 L49 M28 M42 M46 M49

M5 M50

M9 N11 N14 N17 N29 N32 N36 N39 N44 N49

N7 P19

P2 P23

P3 P50 R49 T39 T43 T47 U41 U45 U50

V2

V3

W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29

T29

T31

T33

R28

AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50

FCBGA

OMIT

CRESTLINE

051-7225

14.0.0

8820

NB Grounds

SYNC_MASTER=T9_NOME

SYNC_DATE=03/16/2007

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

GMCH Core Power

1573mA (Int Graphics) 1310mA (Ext Graphics)

WF: Matanzas has 2-pin 270uF bulk cap

540 mA

100 mA

Placeholder for 5.6nH, 0.9A, 45mOhm max

10uF caps should

Layout Note:

WF: "Place where LVDS

close to MCH

Place L and C

Layout Note:

Placeholder for 2.2nH, 1.4A, 17mOhm

10uF caps should

100 mA

250 mA

50 mA

150 mA

450 mA

be close to MCH on opposite side.

Layout Note:

be close to MCH on opposite side.

GMCH ME Core Power

200 mA200 mA

100 mA

NOTE: This follower is redundant if VCORE is always 1.05V.

Layout Note: Route to caps, then GND

5 mA (standby)

1395 mA (1ch 533MHz)

1700 mA (1ch 667MHz)

2700 mA (2ch 533MHz)

3300 mA (2ch 667MHz)

770 mA (667MHz FSB)

675 mA (667MHz DDR2) 585 mA (533MHz DDR2)

515 mA 515 mA

0.4 mA

35 mA

640 mA (667MHz DDR2) 550 mA (533MHz DDR2)

495 mA 495 mA

1260 mA1520 mA

260 mA

Current numbers from Crestline EDS, doc #21749.

850 mA (800MHz FSB)

GMCH FSB I/O Rail

GMCH Memory I/O Rail

Placeholder for 3.9nH, 1A, 32mOhm

and DDR2 taps." (C2135)

C2124

1

2

PLACEMENT_NOTE=Place close to U1400

6.3V 402

10% CERM-X5R

0.47UF

C2123

1

2

CERM1

603

2.2uF

PLACEMENT_NOTE=Place close to U1400

20%

6.3V

C2121

1

2

6.3V

20%

CERM

PLACEMENT_NOTE=Place close to U1400

603

4.7uF

C2161

1

2

20% CERM

402

0.1uF

10V

C2165

1

2

20% CERM

402

0.1uF

10V

C2100

1

2 3

2.5V TANT

470UF

20%

D2T

CRITICAL

C2113

1

2

20% CERM

402

0.1uF

PLACEMENT_NOTE=Place in GMCH cavity

10V

C2112

1

2

X5R

6.3V

20%

402

0.22uF

C2111

1

2

0.22uF

X5R

6.3V

20%

402

C2110

1

2

805-3

6.3V

20%

CERM-X5R

22UF

C2114

1

2

20%

402

0.1uF

10V

PLACEMENT_NOTE=Place in GMCH cavity

CERM

C2115

1

2

20% CERM

402

0.1uF

10V

PLACEMENT_NOTE=Place in GMCH cavity

C2122

1

2

6.3V

20%

CERM

PLACEMENT_NOTE=Place close to U1400

603

4.7uF

C2131

1

2

PLACEMENT_NOTE=Place close to U1400

CERM-X5R

20%

6.3V 805-3

22UF

C2132

1

2

PLACEMENT_NOTE=Place close to U1400

CERM-X5R

20%

6.3V 805-3

22UF

C2135

1

2

10V 402

CERM

20%

0.1uF

R2183

1

2

402

1% 1/16W MF-LF

0.51

C2191

1

2

20% CERM

402

0.1uF

10V

R2190

1

2

MF-LF

1/16W

1%

1.1

402

L2190

1 2

FERR-220-OHM

0805

C2190

1

2

603

X5R

6.3V

20%

10uF

C2192

1

2

20% CERM

402

0.1uF

10V

C2180

1

2

20% CERM

402

0.1uF

10V

PLACEMENT_NOTE=Place C2180 by U1400.AN2

C2130

1

2

330uF

20%

6.3V POLY

D3L

CRITICAL

C2120

1

2

330uF

20%

6.3V POLY

D3L

CRITICAL

C2174

1

2

X5R

6.3V

10uF

603

20%

C2173

1

2

POLY

20%

220UF

2.5V

CASE-B2

CRITICAL

L2173

1 2

1210

91NH

C2197

1

2

0.1uF

20% CERM

402

10V

R2195

1

2

1.1

1/16W

1%

MF-LF

402

L2195

1 2

1.0UH-220MA-0.12-OHM

0805

C2195

1

2

X5R

6.3V

20%

10uF

603

C2196

1

2

CERM-X5R

20%

6.3V

805-3

22UF

C2160

1

2

20% CERM

402

0.1uF

10V

C2171

1

2

1uF

402

10% 10V X5R

C2170

1

2

10uF

20%

6.3V X5R 603

R2170

1 2

0

1/10W MF-LF

5%

603

C2151

1

2

402

1uF

10% 10V X5R

R2150

1 2

603

0

MF-LF

1/10W

5%

L2150

1 2

FERR-120-OHM-0.2A

0603

NO STUFF

C2142

1

2

CERM-X5R

20%

6.3V

805-3

22UF

C2141

1

2

805-3

6.3V

20%

22uF

CERM-X5R

NO STUFF

C2143

1

2

603

CERM

20%

6.3V

4.7UF

C2140

1

2

330uF

20%

6.3V POLY

D3L

CRITICAL

C2144

1

2

10V

10%

402

1uF

X5R

R2141

1 2

603

MF-LF

1/10W

5%

0

C2145

1

2

805-3

6.3V

20%

CERM-X5R

22UF

R2145

1 2

5% 1/10W MF-LF

603

0

C2148

1

2

10V

0.1uF

402

20% CERM

R2186

1 2

402

10

MF-LF

1%

1/16W

D2186

1 3

SOT23

BAT54E3

R2185

1 2

402

1/16W

1%

MF-LF

10

D2185

1 3

SOT23

BAT54E3

C2150

1

2

CERM-X5R

20%

805-3

6.3V

NO STUFF

22UF

C2146

1

2

CERM1 603

2.2uF

20%

6.3V

NO STUFF

L2181

1 2

FERR-120-OHM-0.2A

0603

C2104

1

2

20% CERM

402

0.1uF

10V

PLACEMENT_NOTE=Place in GMCH cavity

C2177

1

2

X5R

6.3V

20%

10uF

603

C2103

1

2

X5R

6.3V

20%

402

PLACEMENT_NOTE=Place in GMCH cavity

0.22uF

C2102

1

2

X5R

6.3V

20%

402

PLACEMENT_NOTE=Place in GMCH cavity

0.22uF

C2184

1

2

20% CERM

402

0.1uF

PLACEMENT_NOTE=Place C2184 by U1400.AM2

10V

C2182

1

2

20% CERM

402

0.1uF

10V

PLACEMENT_NOTE=Place C2182 by U1400.AL2

C2181

1

2

805-3

CERM-X5R

6.3V

20%

22UF

L2183

1 2

FERR-120-OHM-0.2A

0603

C2183

1

2

805-3

CERM-X5R

6.3V

20%

22UF

C2101

1

2

CERM-X5R

PLACEMENT_NOTE=Place in GMCH cavity

20%

6.3V 805-3

22UF

SYNC_DATE=01/17/2007

21

14.0.0

051-7225

88

SYNC_MASTER=T9_NOME

NB Standard Decoupling

MIN_LINE_WIDTH=0.5 MM VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_NB_VCCPEG

MAKE_BASE=TRUE

PP1V25_S0

PP1V8_S3_ISNS

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V

MIN_LINE_WIDTH=0.4 MM

PP1V25_S0M_NB_VCCA_SM_CK

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_NB_VCCPEG

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V

MIN_LINE_WIDTH=0.25 MM

PP1V25_S0M_NB_VCCA_HPLL

GND

PP3V3_S0

PPVCORE_S0_NB_R

PP1V25_S0M_NB_VCCA_MPLL

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V

MIN_LINE_WIDTH=0.3 MM

PP1V25_S0

PP1V25_S0M_NB_MPLL_RC

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V

MIN_LINE_WIDTH=0.3 MM

PP1V25_S0

PP3V3_S0

PP3V3_S0_NB1V05_FOLLOW_R

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V

PP3V3_S0_NBCORE_FOLLOW_R

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0

PP3V3_S0

VOLTAGE=1.8V

PP1V8_S3M_NB_VCCSMCK_RC

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0

PP1V25_S0

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V

MIN_LINE_WIDTH=0.4 MM

PP1V25_S0_NB_VCCAXF

PP1V05_S0

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V25_S0M_NB_VCCAXD

VOLTAGE=1.25V

PP1V25_S0

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

PP1V25_S0_NB_PEGPLL

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V

MIN_LINE_WIDTH=0.4 MM

PP1V25_S0M_NB_VCCA_SM

VOLTAGE=1.25V

MIN_LINE_WIDTH=0.25 MM

PP1V25_S0_NB_PEGPLL_RC

MIN_NECK_WIDTH=0.2 MM

PP1V25_S0

PP1V8_S3_ISNS

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

PP1V8_S3M_NB_VCCSMCK

PP1V05_S0

87

77

75

74

65

59

58

57

52

51

50

48

47

46

42

61

42

61

32

50

32

50

31

46

31

46

30

29

27

29

27

28

26

28

26

27

23

27

23

26

21

26

21

25

19

25

19

65

24

65

24

18

24

18

65

18

65

18

57

23

57

23

14

23

14

57

14

57

14

27

50

21

50 27

27

21

13

21

13

27

13

27

50

13

26

21

19

22 26

26

19

12

19

12

26

12

26

21

12

12 21

21

18

21

16

18 21

21

16

11

16

11

21

11

21

18

11

11 19

19

16

19

13

16 19

19

13

10

13

10

19

10

19

16

10

10 15

8

19

15

19

8

19

8

16

8

19

8

19

8

IN

OUT

EN

NR/FB

IN

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NOTE: This filter is required even if using only external graphics.

100 mA

(1.7V - 5.5V)

100 mA

These 2 caps should be within 6.35 mm of NB edge

Layout Note:

60 mA

Current numbers from Crestline EDS Addendum, doc #20127.

150 mA

110 mA260 mA

Crestline LVDS Support

65 mA

Layout Note: Route to cap, then GND

Vout = 1.25V (Factory Programmed)

7700 mA

VCCD_TVDAC also powers internal thermal sensors.

GMCH Graphics Core Power

R2299

1

2

402

MF-LF

1/16W

1%

2.37K

15 80

C2265

1

2

6.3V CERM

402

10%

1UF

U2265

3

2

1

4

5

TPS731125

SOT23-5

CRITICAL

C2266

1

2

0.01UF

CERM

402

16V

10%

R2260

1

2

5% FF

603

0.300

1/10W

R2261

1 2

1/16W MF-LF

4.7

5%

402

NO STUFF

C2261

1

2

10V

0.1uF

402

CERM

20%

NO STUFF

R2262

1 2

MF-LF

402

4.7

5%

1/16W

C2262

1

2

10V 402

CERM

20%

0.1uF

C2260

1

2

603

10UF

20%

6.3V X5R

C2223

1

2

0.001UF

402

10% 50V CERM

C2221

1

2

402

10% 50V CERM

0.001UF

C2201

2

1 3

NFM18

16V

22000pF-1000mA

C2200

1

2

0.1uF

10V 402

CERM

20%

L2220

1 2

1.0UH-0.5A

1210

C2220

1

2

220UF

20%

6.3V POLY

CRITICAL

CASE-D3L

C2217

1

2

PLACEMENT_NOTE=Place in GMCH cavity

10V 402

CERM

20%

0.1uF

C2216

1

2

CERM 402

PLACEMENT_NOTE=Place in GMCH cavity

10V

0.1uF

20%

C2215

1

2

0.47UF

CERM-X5R

6.3V

PLACEMENT_NOTE=Place in GMCH cavity

10% 402

C2213

1

2

603

10uF

PLACEMENT_NOTE=Place in GMCH cavity

X5R

6.3V

20%

C2212

1

2

805-3

CERM-X5R

22UF

PLACEMENT_NOTE=Place in GMCH cavity

20%

6.3V

CRITICAL

C2211

1

2 3

CRITICAL

TANT

20%

470UF

D2T

2.5V

C2210

1

2 3

CRITICAL

470UF

TANT

D2T

2.5V

20%

C2226

1

2

6.3V CERM 402

10%

1UF

C2214

1

2

402

PLACEMENT_NOTE=Place in GMCH cavity

1UF

10% CERM

6.3V

SYNC_MASTER=M76_MLB

22 88

14.0.0

051-7225

NB Graphics Decoupling

SYNC_DATE=03/12/2007

PPVCORE_S0_NB_GFX

NB_CLK100M_DPLLSS_P

PP1V8_S0

GND

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V

MIN_LINE_WIDTH=0.2 MM

PP1V8_S0_NB_VCCTXLVDS

NB_CLK100M_DPLLSS_N

NB_CLK100M_DPLLSS_P

PPVCORE_S0_NB_R

LVDS_IBG

PP1V8_S0

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

PP1V25_S0_NB_VCCA_DPLLA

PP1V5_S0_NB_VCCD_TVDAC

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V

PP1V25_S0_NB_VCCA_DPLLB

MIN_LINE_WIDTH=0.3 MM VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

P1V25S0NBDPLL_NR

PP1V25_S0_NB_DPLL

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=0V

MIN_LINE_WIDTH=0.4 MM

GND_DPLL_ESR

MIN_NECK_WIDTH=0.2 MM

PP1V8_S0

GND

GND GND

GND

PP1V5_S0

NB_CLK100M_DPLLSS_N

NC_LVDS_VREFH

NC_LVDS_VREFL

MAKE_BASE=TRUE NO_TEST=TRUE

NC_LVDS_VREFL

NC_LVDS_VREFH

MAKE_BASE=TRUE NO_TEST=TRUE

87 63

84

50

34

84

30

65

30

22

65

27

30

59

29

57

29

21

57

26

29

18

22

18

22

12

22

8

16

19

16

19

11

16

22

22 22

22

7

8

19

7

8

19

8

7

15

15 15

15

SATA0RXP

SATA0RXN

SATALED*

RTCRST*

HDA_BIT_CLK

DDREQ

RTCX1 RTCX2

DCS1* DCS3*

IDEIRQ

DDACK*

IORDY

DIOR* DIOW*

DD11 DD12

DD4

DD2

DD14

DD0

DD15

DD1

DD13

DD5

DD10

DD8

DD3

DD9

LDRQ0*

FWH2/LAD2 FWH3/LAD3

FWH1/LAD1

LDRQ1*/GPIO23

FWH0/LAD0

FWH4/LFRAME*

HDA_SDIN0

HDA_SYNC

SATA1TXN SATA1TXP

HDA_SDIN1 HDA_SDIN2

RCIN*

SATA0TXP

SATA0TXN

CPUPWRGD/GPIO49

SMI*

A20M*

SATA1RXP

SATA1RXN

SATARBIAS

SATARBIAS*

IGNNE*

DPRSTP*

INTVRMEN

A20GATE

SATA2RXN SATA2RXP

THRMTRIP*

DPSLP*

INIT*

HDA_RST*

HDA_SDOUT

HDA_DOCK_EN*/GPIO33

SATA2TXN SATA2TXP

FERR*

NMI

HDA_SDIN3

INTR

SATA_CLKP

SATA_CLKN

DA2

DD6

STPCLK*

TP8

DA0 DA1

HDA_DOCK_RST*/GPIO34

INTRUDER*

LAN_TXD0

LAN100_SLP

LAN_RSTSYNC

LAN_RXD0 LAN_RXD1 LAN_RXD2

DD7

LAN_TXD2

LAN_TXD1

GLAN_DOCK*/GPIO13

GLAN_COMPI GLAN_COMPO

GLAN_CLK

LAN/GLANIHDA

CPU

RTC

LPC

(1 OF 6)

SATA

IDE

OUT

IN

BI

BI BI

BI

OUT

IN

OUT

IN

IN OUT OUT

IN

OUT

IN

OUT OUT

IN

OUT

OUT OUT OUT

IN IN IN

BI

OUT OUT OUT

OUT

OUT OUT

OUT

OUT OUT

IN

OUT OUT

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

INT PU

INT PD

HDA

24.000MHZ CLOCK W/INTERNAL WEAK PD

HDA_BIT_CLK HDA_RST# HDA_SDIN[0-2] HDA_SDOUT ACZ_SYNC

INTEGRATED PDs INTEGRATED PD INTEGRATED PD

INT PDINT PU

INT PD

INT PU

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

U2300

AF13 AG26

AG29

AA4 AA1 AB3

Y6 Y5

V1 U2

T4 V6 V5 U1 V2 U6

V3 T1 V4 T5 AB2 T6 T3 R2

Y2

W5

W4 W3

AF26 AE26

AD24

E5 F5 G8 F6

C4

B24

D25 C25

AH21

AJ16

AE10 AG14

AE14

AJ17 AH17 AH15 AD13

AE13

AJ15

Y3

AF27

AE24 AC20

AD22

AF25

Y1

AD21

D22

C21 B21 C22

D21 E20 C20

G9 E6

AD23

AH14

AF23

AG25 AF24

AF6 AF5 AH5 AH6

AG3 AG4 AJ4 AJ3

AF2 AF1 AE4 AE3

AB7 AC6

AF10

AG2

AG1

AG28

AA24

AE27

AA23

OMIT

BGA

ICH8M

28

7

28

7

45 47

7

45 47

7

45 47

7

45 47

28 57 65

7

45 47

10 79

R2304

1

2

402

MF-LF

1/16W

5%

2.2K

NO STUFF

R2302

1

2

402

1%

24.9

MF-LF

1/16W

R2301

1

2

1%

332K

MF-LF 402

1/16W

78 82

42 82

29 30 84

23 42 82

7

10 16 58 79

7

10 79

7

10 13 79

42 82

7

10 79

10 47 79

10 79

R2306

1

2

10K

MF-LF 402

5% 1/16W

10 16 46 79

R2308

1 2

PLACEMENT_NOTE=Place R2308 within 50mm of U2300

1%

MF-LF

1/16W

24.9

402

34 82

R2300

1

2

1/16W

1%

332K

402

MF-LF

R2303

1

2

8.2K

5% 1/16W MF-LF

402

34 82

R2310

1

2

402

MF-LF

1/16W

5%

8.2K

R2305

1

2

1% 1/16W MF-LF

402

54.9

R2309

1

2

1% 1/16W MF-LF 402

54.9

PLACEMENT_NOTE=Place R2309 within 50mm of R2308 (NO STUB)

R2313

1 2

402

33

MF-LF1/16W

5%

R2314

1 2

5%

1/16W MF-LF33402

R2315

1 2

1/16W33MF-LF

5% 402

R2316

1 2

5%

1/16W MF-LF

402

33

R2311

1

2

1/16W 402

MF-LF

10K

5%

42 82

14.0.0

23 88

051-7225

SYNC_MASTER=T9_NOME

SYNC_DATE=03/16/2007

SB Enet, Disk, FSB, LPC

TP_HDA_SDIN2 TP_HDA_SDIN3

HDA_SDIN0

TP_LAN_D2R<1>

TP_ENET_GLAN_CLK

TP_HDA_SDIN1

SATA_A_D2R_N

HDA_SDOUT

HDA_RST_L

HDA_BIT_CLK HDA_SYNC

HDA_SDOUT_R

HDA_RST_L_R

HDA_SYNC_R

HDA_BIT_CLK_R

SATA_RBIAS SATA_RBIAS

SB_CLK100M_SATA_N SB_CLK100M_SATA_P

TP_SATA_C_R2DP

TP_SATA_C_R2DN

TP_SATA_C_D2RN TP_SATA_C_D2RP

TP_SATA_B_R2DP

TP_SATA_B_R2DN

TP_LAN_R2D<1>

TP_LAN_D2R<0>

TP_LAN_RSTSYNC

TP_LAN_R2D<0>

TP_HDA_DOCK_RST_L

TP_SATA_B_D2RN TP_SATA_B_D2RP

SATA_A_R2D_C_N SATA_A_R2D_C_P

TP_SB_SATALED_L

SATA_A_D2R_P

TP_LAN_D2R<2>

TP_SB_TP8

SB_RCIN_L

TP_LPC_DRQ0_L

SB_A20GATE

CPU_FERR_L

PP3V3_S0

PP1V05_S0

IDE_PDDREQ

IDE_PDIORDY

IDE_IRQ14

IDE_PDDACK_L

IDE_PDIOR_L IDE_PDIOW_L

IDE_PDCS1_L IDE_PDCS3_L

IDE_PDA<2>

IDE_PDA<1>

IDE_PDA<0>

IDE_PDD<14> IDE_PDD<15>

IDE_PDD<13>

IDE_PDD<11> IDE_PDD<12>

IDE_PDD<9> IDE_PDD<10>

IDE_PDD<8>

IDE_PDD<6> IDE_PDD<7>

IDE_PDD<5>

IDE_PDD<4>

IDE_PDD<3>

IDE_PDD<1> IDE_PDD<2>

IDE_PDD<0>

CPU_STPCLK_L

CPU_SMI_L

CPU_NMI

CPU_INTR

CPU_INIT_L

CPU_IGNNE_L

CPU_PWRGD

CPU_DPRSTP_L CPU_DPSLP_L

CPU_A20M_L

CPU_THERMTRIP_R

PM_THRMTRIP_L

EXTGPU_PWR_EN

LPC_FRAME_L

LPC_AD<3>

LPC_AD<1>

LPC_AD<0>

LPC_AD<2>

TP_LAN_R2D<2>

SB_RTC_X1 SB_RTC_X2

SB_RTC_RST_L SB_SM_INTRUDER_L

SB_LAN100_SLP

SB_INTVRMEN

HDA_DOCK_EN_L

PP3V3_G3_SB_RTC

GLAN_COMP

PP1V5_S0_SB_VCC1_5_B

PP3V3_S0

LAN_ENERGY_DET

87

77

75

74

65

59

58

57

52

51

50

48

47

46

42

32

61

32

31

50

31

30

46

30

29

30

29

28

27

28

27

26

27

26

21

26

25

19

25

24

18

24

23

14

23

21

13

21

19

12

19

16

11

28

27

16

13

10

27

26

13

82

8

7

26

83

24

8

SPI_CS1*

PETN1

PERP1

OC4*/GPIO43 OC5*/GPIO29 OC6*/GPIO30 OC7*/GPIO31 OC8* OC9*

SPI_MOSI

OC0* OC1*/GPIO40 OC2*/GPIO41 OC3*/GPIO42

PERN5

DMI1RXN DMI1RXP DMI1TXN DMI1TXP

DMI0RXN DMI0RXP DMI0TXN DMI0TXP

DMI_CLKN DMI_CLKP

PETP1

USBP9N USBP9P

PERN2

USBP7N USBP7P USBP8N USBP8P

PETN2

USBP6N USBP6P

PERP3

USBP4N USBP4P USBP5N USBP5P

PETN3

PETP3

USBP3N USBP3P

PERN4 PERP4

USBP1N USBP1P USBP2N USBP2P

PETN4 PETP4

USBP0N USBP0P

PERP5

SPI_MISO

USBRBIAS

USBRBIAS*

PETP5

PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP

SPI_CLK SPI_CS0*

DMI3RXN DMI3RXP DMI3TXN DMI3TXP

DMI2RXN DMI2RXP DMI2TXN DMI2TXP

DMI_IRCOMP

DMI_ZCOMP

PERN1

PERP2

PETP2

PERN3

PETN5

PCI_EXPRESS

DIRECT MEDIA INTERFACE

SPI

USB

(2 OF 6)

IN

IN OUT OUT

IN

IN OUT OUT

IN

IN OUT OUT

IN

IN OUT OUT

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN

IN OUT OUT

IN

IN OUT OUT

BI BI

BI

AD4 AD5

AD9

PIRQF*/GPIO3

PIRQE*/GPIO2

AD13

PME*

PCIRST*

GNT2*/GPIO53

C/BE2*

PIRQG*/GPIO4

SERR*

PIRQA*

AD1

REQ1*/GPIO50

C/BE3*

AD11

C/BE1*

AD25 AD26

AD0

AD2

DEVSEL*

AD18

AD21

PAR

GNT0*

AD7

GNT1*/GPIO51

C/BE0*

STOP*

AD20

AD16

GNT3*/GPIO55

TRDY*

IRDY*

AD22

PIRQC*

REQ2*/GPIO52

AD19

PCICLK

PLOCK*

AD15

PIRQB*

PIRQH*/GPIO5

PLTRST*

AD3

AD6

AD8

FRAME*

AD14

AD12

AD10

REQ3*/GPIO54

PIRQD*

AD17

PERR*

REQ0*

AD31

AD27 AD28

AD30

AD29

AD24

AD23

(3 OF 6)

INTERRUPT I/F

PCI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

IN

BI

BI BI

OUT

BI BI BI

BI

OUT

IN

BI BI

IN

IN IN IN

OUT

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NOTE: GNT[0-3]# have internal 20K pull-ups enabled only when PCIRST# = 0 and PWROK = 1

If used, ensure GNT2# is not low when PWROK rises, or PCIe ports 5 & 6 will be disabled.

FireWire INT*

INT PU

Provide a pull-down on this GPIO if not used.

R2415 pull-down on GNT0# selects SPI ROM by default.

SB BOOT BIOS SELECT

I/F LPC

Nineveh-GLCI

Yukon-PCIE

PCIe Mini Card

SPI

NOTE:

0

GNT0#

1

GNT0# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H SPI_CS1# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)

high for x2)

pull HDA_SYNC

(x2-capable,

Ethernet

(AirPort)

FireWire

ExpressCard

Spares

INT PD

INT PD INT PD

EHCI1

INT PU INT PU

INT PU

INT PD

INT PD INT PD

INT PD

EHCI0

INT PD

INT PD INT PD INT PD INT PD

INT PD

External C

Camera

AirPort (PCIe Mini-Card)

ExpressCard

External B

Geyser Trackpad/Keyboard

External A

External D / WWAN

Bluetooth

IR

NOTE: USBP[0-9]P/N have internal 15K pull-downs.

R2408

1

2

1/16W

402

10K

5%

MF-LF

R2407

1

2

5%

10K

402

MF-LF

1/16W

R2400

1

2

MF-LF

1/16W

5%

402

10K

R2409

1

2

5% MF-LF

402

1/16W

10K

R2401

1

2

1/16W

10K

5%

402

MF-LF

R2402

1

2

10K

MF-LF

1/16W

5%

402

R2404

1

2

5%

MF-LF

10K

1/16W

402

R2403

1

2

5% 1/16W

402

MF-LF

10K

U2300

V27 V26 U29 U28

Y27 Y26 W29 W28

AB26 AB25 AA29 AA28

AD27 AD26 AC29 AC28

T26 T25

Y24

Y23

AJ19 AG16 AG15 AE15 AF15 AG17 AD12 AJ18 AD14 AH18

P27

M27

K27

H27

F27

D27

P26

M26

K26

H26

F26

D26

N29

L29

J29

G29

E29

C29

N28

L28

J28

G28

E28

C28

C23 B23 E22

F21

D23

G3 G2 H5 H4 H2 H1 J3 J2 K5 K4 K2 K1 L3 L2 M5 M4 M2 M1 N3 N2

F3

F2

OMIT

ICH8M

BGA

16 80

29 30 84

R2413

1 2

24.9

1/16W MF-LF

4021%

43 82

34 82

7

44 82

7

44 82

7

44 82

7

44 82

78 82

34 82

9

82

9

82

R2414

1 2

1/16W

1%

402

MF-LF

22.6

34 83

35 83

55 82

U2300

D20 E19

A12 E16 A14 G16 A15

B6

C11

A9 D11 B12

D19

C12 D10

C7 F13 E11 E13 E12

D8

A6

E8

A20

D6

A3

D17 A21 A19 C19 A18 B16 C17

E15 F16 E17

D16

A17

D7

C18

F18

C10

C8 D9

B10

G6

A7

F9

B5

C5 A10

F8 G11 F12 B3

B7

AG24

G7

A4

E18

B19

A11

F10 C16 C9

OMIT

BGA

ICH8M

38 83

24 83

24 38 83

24 83

24 38 83

24 83

38 83

24 38 83

38 83

7

28

24 38 83

24 83

24 38 83

7

28 77

30 84

24 83

R2405

1

2

10K

1/16W MF-LF 402

5%

R2406

2

1

10K

MF-LF

5%

1/16W

402

R2415

1

2

1K

MF-LF

1/16W

5%

402

R2423

1 2

8.2K

R2424

1 2

8.2K

R2425

1 2

8.2K

R2426

1 2

8.2K

R2427

1 2

8.2K

R2428

1 2

8.2K

R2430

1 2

8.2K

R2429

1 2

8.2K

R2432

1 2

8.2K

R2431

1 2

8.2K

R2433

1 2

8.2K

R2437

1 2

8.2K

R2439

1 2

8.2K

R2438

1 2

8.2K

R2436

1 2

8.2K

R2440

1 2

8.2K

24 83

R2441

1 2

8.2K

13 43

13

13 34

34 46

24 42

76

7

24 38 47 83

42 82

13

7

24 38 47 83

13 77

R2442

1 2

8.2K

13

13 36

13

SB PCI, PCIe, DMI, USB

SYNC_MASTER=T9_NOME

14.0.0

24 88

051-7225

SYNC_DATE=03/16/2007

DMI_N2S_N<0> DMI_N2S_P<0> DMI_S2N_N<0> DMI_S2N_P<0>

DMI_N2S_N<1> DMI_N2S_P<1> DMI_S2N_N<1> DMI_S2N_P<1>

DMI_N2S_N<2> DMI_N2S_P<2> DMI_S2N_N<2> DMI_S2N_P<2>

DMI_N2S_N<3> DMI_N2S_P<3> DMI_S2N_N<3> DMI_S2N_P<3>

SB_CLK100M_DMI_N SB_CLK100M_DMI_P

USB_EXTA_N USB_EXTA_P USB_MINI_N USB_MINI_P USB_WWAN_N USB_WWAN_P

USB_CAMERA_P

USB_CAMERA_N

USB_IR_N USB_IR_P USB_TPAD_N

USB_BT_N

USB_TPAD_P

USB_BT_P USB_EXTB_N USB_EXTB_P USB_EXCARD_N

TP_USB_EXTCN

USB_EXCARD_P

TP_USB_EXTCP

PCIE_MINI_R2D_C_N

PCIE_EXCARD_D2R_N

TP_PCIE_B_R2D_C_P

TP_PCIE_B_D2R_P

TP_PCIE_A_D2R_N

SPI_CE_R_L<0>

SPI_SCLK_R

PCIE_ENET_R2D_C_P

PCIE_ENET_R2D_C_N

PCIE_ENET_D2R_P

PCIE_ENET_D2R_N

PCIE_MINI_R2D_C_P

SPI_SO

PCIE_MINI_D2R_P

TP_PCIE_FW_R2D_C_P

TP_PCIE_FW_R2D_C_N

TP_PCIE_FW_D2R_P

TP_PCIE_FW_D2R_N

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_R2D_C_N

PCIE_EXCARD_D2R_P

TP_PCIE_B_R2D_C_N

TP_PCIE_B_D2R_N

PCIE_MINI_D2R_N

USB_EXTD_OC_L

SPI_SI_R

EXCARD_OC_L

USB_EXTB_OC_L

PM_LATRIGGER_L

TP_PCIE_A_D2R_P TP_PCIE_A_R2D_C_N

TP_SPI_CE_R_L<1>

DMI_IRCOMP_R

USB_RBIAS

PP1V5_S0_SB_VCC1_5_B

PP3V3_S0

PCI_PERR_L

PCI_DEVSEL_L

PCI_SERR_L

ODD_PWR_EN_L

INT_PIRQC_L

INT_PIRQF_L

PCI_LOCK_L PCI_FW_REQ_L

PCI_FRAME_L PCI_IRDY_L

PCI_STOP_L

PCI_REQ2_L INT_PIRQA_L

INT_PIRQB_L

INT_PIRQD_L INT_PIRQE_L

PCI_TRDY_L

PCI_REQ1_L

TP_PCIE_A_R2D_C_P

SB_GPIO30

USB_EXTC_OC_L

EXTGPU_LVDS_EN

USB_EXTA_OC_L SB_GPIO40

PP3V3_S5

MAKE_BASE=TRUE

PCI_FW_GNT_L PCI_FW_GNT_L

TP_PCI_PME_L

TP_SB_GPIO53

PCI_REQ1_L TP_SB_GPIO51

TP_SB_GPIO55

PCI_FW_REQ_L

PCI_REQ2_L

ODD_RST_5VTOL_L

PCI_C_BE_L<2>

PCI_C_BE_L<0> PCI_C_BE_L<1>

PCI_C_BE_L<3>

PCI_IRDY_L PCI_PAR PCI_RST_L

PCI_PERR_L

PCI_DEVSEL_L

PCI_LOCK_L PCI_SERR_L PCI_STOP_L

PCI_FRAME_L

PCI_TRDY_L

PCI_CLK33M_SB

PLT_RST_L

INT_PIRQF_L

INT_PIRQE_L

DVI_HOTPLUG_DET ODD_PWR_EN_L

PCI_AD<0>

PCI_AD<2>

PCI_AD<1>

PCI_AD<3> PCI_AD<4> PCI_AD<5> PCI_AD<6>

PCI_AD<8>

PCI_AD<7>

PCI_AD<9> PCI_AD<10> PCI_AD<11>

PCI_AD<13>

PCI_AD<12>

PCI_AD<14> PCI_AD<15> PCI_AD<16>

PCI_AD<18>

PCI_AD<17>

PCI_AD<19> PCI_AD<20> PCI_AD<21> PCI_AD<22>

PCI_AD<24>

PCI_AD<23>

PCI_AD<25> PCI_AD<26> PCI_AD<27> PCI_AD<28> PCI_AD<29> PCI_AD<30> PCI_AD<31>

INT_PIRQB_L

INT_PIRQA_L

INT_PIRQC_L INT_PIRQD_L

WOW_EN

87 77 75 74 65 59 58 57 52

51 50 48 47 46 42 32 31

87

30

75

29

65

28

60

27

57

26

55

25

48

23

46

21

28

19

27

16

83

26

83

26

13

38

42

83

38

83

38

83

38

83

25

34

82

23

8

24

8

OUT OUT

BI

IN

BI

IN IN

SMBALERT*/GPIO11

STP_PCI*/GPIO15

BMBUSY*/GPIO0

SYS_RESET*

SUS_STAT*/LPCPD*

QRT_STATE0/GPIO27

THRM*

SMLINK0

GPIO12

SPKR

SDATAOUT1/GPIO48

QRT_STATE1/GPIO28

SLP_S5*

GPIO20

GPIO8

WAKE*

CL_CLK1

BATLOW*

PWROK

SLOAD/GPIO38

SATA2GP/GPIO36

SERIRQ

RI*

CL_DATA1

SLP_S4*

EC_ME_ALERT/GPIO14

TACH0/GPIO17

CLK14

SCLOCK/GPIO22

SATA3GP/GPIO37

SATACLKREQ*/GPIO35

STP_CPU*/GPIO25

WOL_EN/GPIO9

LINKALERT*

SLP_S3*

RSMRST*

TACH3/GPIO7

CLKRUN*/GPIO32

GPIO18

LAN_RST*

CL_VREF1

S4_STATE*/GPIO26

TACH1/GPIO1 TACH2/GPIO6

SATA1GP/GPIO19

SDATAOUT0/GPIO39

SATA0GP/GPIO21

MCH_SYNC*

DPRSLPVR/GPIO16

VRMPWRGD

TP3

TP7

CL_RST*

ME_EC_ALERT/GPIO10

SLP_M*

MEM_LED/GPIO24

PWRBTN*

SUSCLK

CL_VREF0

CK_PWRGD

CLPWROK

CL_DATA0

CL_CLK0

CLK48

SMBCLK SMBDATA

SMLINK1

MISC

SYS GPIO

SMB

CLOCKS

POWER MGT

CONTROLLER LINK

GPIO

SATA

GPIO

(4 OF 6)

IN IN

OUT

IN

BI BI

OUT IN

IN

OUT

IN

BI

OUT

BI

IN

OUT OUT

OUT

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

If ME/AMT is not used, short CLPWROK to PWROK.

PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,

See note below

have been up for at least 1ms.

PM_LAN_ENABLE must remain deasseted until VccCL3_3, VccLAN3_3 and VccLAN1_05

INT PU

NOTE: ICH CLPWROK input must be PWRGD signal for

INT PD

INT PU

Test access required

AT BOOT/RESET FOR STRAPPING FUNCTION

NOTE: DPRSLPVR HAS INT 20K PD ENABLED

INT PU

for XOR chain testing.

PP1V05_S0M, PP0V9_S3M and PP0V9_S0M.

7

29 30

7

29 30

7

45 47

34 35

7

45 47

45

13 45

R2515

1

2

10K

402

MF-LF

1/16W

5%

R2516

1

2

ARB_ONLY

MF-LF

1/16W

5%

0

402

R2511

1

2

402

10K

5% 1/16W MF-LF

R2512

1

2

402

NOSTUFF

0

5% 1/16W MF-LF

R2502

1

2

402

MF-LF

10K

5%

1/16W

R2504

1

2

1/16W MF-LF

5%

10K

402

R2500

1

2

402

MF-LF

1/16W

5%

1K

R2507

1

2

MF-LF

1/16W

5%

8.2K

402

R2506

1

2

MF-LF

1/16W

10K

5%

402

R2505

1

2

MF-LF

5%

8.2K

1/16W

402

U2300

AE21

AG12

E1

F23 AE18

F22 AF19

AJ23

D24 AH23

AG9 G5

AH11

E3

AJ14

AF22

AC19

AH12 AE11

AE16

AH20

AG21

AJ13 AJ24

AJ27

C2

AE23

AH25 AD16

AF17

AG27

AH27

AJ12 AJ10 AF11 AG11

AG13

AG10

AJ11 AD10

AF12

AF9

AJ25

AG23 AF21 AD18

AG22

AJ26 AD19

AC17 AE19

AD9

AG18

AE20

F4 D3

AD15

AG8

AJ8 AJ9 AH9

AC13

AJ21

AJ22

AJ20

AE17

AG19

ICH8M

BGA

OMIT

30 84

45 46

7

35 36 40 45 49 57 62 65

R2510

1

2

MF-LF

NO_REBOOT_MODE

1K

5% 1/16W

402

7

45 46

7

16 58 79

7 9

25 28

25 45

7

45

29 31 32 34 48 82

7

45 46 47

7

28 45

16

7

28

25 38

7

16

7

34 43 45 57 65

29

7 9

25 28

16 83

R2526

1

2

MF-LF

1/16W

1%

3.24K

402

R2527

1

2

MF-LF

1/16W

1%

453

402

C2500

1

2

X5R

0.1uF

10% 16V

402

R2529

1

2

453

MF-LF

1% 1/16W

402

R2528

1

2

MF-LF

1/16W

1%

3.24K

402

C2501

1

2

0.1uF

X5R

10% 16V

402

16 83

25

R2523

1

2

5%

MF-LF

402

1/16W

100K

48 82

25

R2536

1 2

402

1%

MF-LF

10K

1/16W

R2544

1 2

402

8.2K

1/16W MF-LF

5%

R2545

1 2

402

1%

1/16W

10K

MF-LF

R2525

1

2

402

5% 1/16W MF-LF

10K

7

25 47

25

25 28

29

R2534

2

1

402

10K

5% 1/16W MF-LF

R2552

1

2

5%

10K

1/16W MF-LF

402

R2550

1

2

402

1/16W

5%

MF-LF

10K

R2553

1

2

8.2K

5% 1/16W MF-LF 402

R2551

1

2

402

MF-LF

5%

8.2K

1/16W

7

45

R2598

1 2

402

10K

1/16W MF-LF

1%

R2546

1 2

402

10K

1/16W MF-LF

1%

R2532

2

1

1/16W

5%

402

MF-LF

10K

R2533

2

1

10K

MF-LF

5%

1/16W

402

R2535

2

1

5%

402

10K

MF-LF

1/16W

77

R2547

2

1

402

10K

MF-LF

1/16W

5%

R2524

1

2

MF-LF

1/16W

5%

402

100K

R2530

1 2

402

1%

MF-LF

1/16W

10K

R2531

1 2

402

1%

MF-LF

1/16W

10K

R2514

2

1

402

100K

5% 1/16W MF-LF

R2596

1 2

402

1%

1/16W

10K

MF-LF

R2597

1 2

402

1%

MF-LF

1/16W

10K

SB Pwr Mgt, GPIO, Clink

SYNC_DATE=03/16/2007

SYNC_MASTER=T9_NOME

051-7225

8825

14.0.0

PCI_PME_FW_L

PP3V3_S5

SATA_B_PWR_EN_L

SB_SDATAOUT<0>

SB_SPKR

SB_GPIO18

SMC_WAKE_SCI_L

TP_SB_TP3

SB_SDATAOUT<1>

SB_SLOAD

SB_SATA_CLKREQ_L

FWH_MFG_MODE

SATA_B_PWR_EN_L

SB_SCLOCK

TP_SB_GPIO20

EXTGPU_RST_L

LAN_PHYPC

SMC_RUNTIME_SCI_L

SB_GPIO6

TP_SB_TP7 PCI_PME_FW_L

PM_CLKRUN_L PCIE_WAKE_L

INT_SERIRQ

PM_THRM_L

SATA_B_DET_L

TP_CLINK_WLAN_DATA

ARB_DETECT_L SB_GPIO10_CL1 SB_GPIO14_CL2 WOL_EN

PM_SLP_S3_L

SB_CLK14P3M_TIMER

SB_CLINK_VREF1

PP3V3_S5

VR_PWRGD_CLKEN

PM_SUS_STAT_L

NB_SB_SYNC_L

LINDACARD_GPIO

PM_BMBUSY_L

CLINK_NB_DATA

TP_CLINK_WLAN_CLK

PM_BATLOW_L

PM_S4_STATE_L PM_SB_PWROK

PM_SLP_S5_L

TP_PM_SLP_S4_L

PM_SYSRST_L

SMBUS_SB_ME_SDA

SMBUS_SB_SDA

PP3V3_S0

SB_GPIO14_CL2

LAN_PHYPC

SB_GPIO10_CL1

PM_BATLOW_L

PM_RI_L

PM_STPCPU_L

CLK_PWRGD

PM_DPRSLPVR

SMBUS_SB_SCL

SMBUS_SB_ME_SCL

PM_PWRBTN_L

TP_CLINK_WLAN_RESET_L

SUS_CLK_SB

SB_CLK48M_USBCTLR

PP3V3_S5

CLINK_NB_RESET_L

PM_RI_L

CLINK_NB_CLK

PM_SB_PWROK

PM_RSMRST_L

PM_LAN_ENABLE

PM_STPPCI_L

RSVD_EXTGPU_LVDS_EN

SB_CRT_TVOUT_MUX_L

PP3V3_S0

SB_GPIO36

TP_PM_SLP_M_L

SB_CLINK_VREF0

PP3V3_S5

LINDACARD_GPIO

FWH_MFG_MODE

ARB_DETECT_L

SB_GPIO6

PP3V3_S0

EXTGPU_RST_L

87

77

75

74

65

59

58

57

52

51

50

48

47

46

42

32

87

31

87

31

87

31

75

30

75

30

75

30

65

29

65

29

65

29

60

28

60

28

60

28

57

27

57

27

57

27

55

26

55

26

55

26

48

25

48

25

48

25

46

24

46

24

46

24

28

23

28

23

28

23

27

21

27

21

27

21

26

19

26

19

26

19

25

16

25

16

25

47

16

38

24

13

45

24

13

24

25

13

28

25

8

25

36

83

8

25

8

83

8

7

25

8

25

VSS

VSS_NCTF

VSS

(5 OF 6)

VCC1_5_B

V5REF_SUS

VCCDMIPLL

VCC_DMI

VCC3_3

VCC1_05

V5REF

VCCCL1_5

VCCGLANPLL

VCC3_3

VCC1_5_A

VCC3_3

VCCHDA

VCCSUS1_5

VCCSUS3_3

V_CPU_IO

VCC3_3

VCCSUSHDA

VCC1_5_A

VCC3_3

VCCSATAPLL

VCCGLAN3_3

VCCSUS3_3

VCCLAN3_3

VCCCL1_05

VCCSUS1_05

VCCSUS1_5

VCCSUS3_3

VCCA3GP

VCCGLAN1_5

VCCCL3_3

VCCLAN1_05

VCC1_5_A24

VCC1_5_A

VCCRTC

VCC1_5_A

VCCUSBPLL

VCC1_5_A

GLAN POWER

USB CORE

ATX ARX

(6 OF 6)

VCCPSUS

IDE

COREVCCP CORE

PCI

VCCPUSB

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

19 mA S0, 51 mA M1 & WOL

1 mA

80 mA

23 mA

10 mA

19 mA S0, 63 mA M1 & WOL

(VCC1_5_A total)

47 mA

1080 mA

32 mA

(VCCSUS3_3 total)

1 mA S3-S5

44 mA S3-S5

11 mA S0,

117 mA S0,

442 mA

(VCC3_3 total)

1 mA

50 mA

23 mA

1130 mA

NOTE: VccHDA and VccSusHDA can be 1.5V or 3.3V depending on VIO of HD Audio interface.

Current figures provided assume 1.5V.

Current numbers from ICH8M Max Power Estimates Rev 2.0, doc #610194.

657 mA

1 mA S0-S5

1 mA

6 uA S0-G3

C2600

1

2

402

10%

CERM

6.3V

1uF

C2601

1

2

0.1uF

20% 10V CERM 402

U2300

A23

A5

AC26

L13 L15 L26 L27 L4 L5 M12 M13 M14 M15

AC27

M16 M17 M23 M28 M29 M3 N1 N11 N12 N13

AD17

N14 N15 N16 N17 N18 N26 N27 N4 N5 N6

AD20

P12 P13 P14 P15 P16 P17 P23 P28 P29 R11

AD28

R12 R13 R14 R15 R16 R17 R18 R28 R4 T12

AD29

T13 T14 T15 T16 T17 T2 U12 U13 U14 U15

AD3

U16 U17 U23 U26 U27 U3 U5 V13 V15 V28

AD4

V29 W2 W26 W27 Y28 Y29 Y4 AB4 AB23 AB5

AD6

AB6 AD5 U4 W24

AE1

AA2

AE12

AE2

AE22

AD1

AE25

AE5 AE6

AE9 AF14 AF16

AA7

AF18

AF3

AF4

AG5

AG6 AH10 AH13 AH16 AH19

AH2

A25

AF28 AH22 AH24 AH26

AH3

AH4

AH8

AJ5

B11

B14

AB1

B17

B2 B20 B22

B8 C24 C26 C27

C6 D12

AB24

D15 D18

D2

D4 E21 E24

E4

E9 F15 E23

AC11

F28 F29

F7

G1

E2 G10 G13 G19 G23 G25

AC14

G26 G27 H25 H28 H29

H3

H6

J1 J25 J26

AC25

J27

J4

J5 K23 K28 K29

K3

K6

K7 L1

A1 A2

B1 B29

A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29

OMIT

BGA

ICH8M

U2300

A16

T7

G4

AC23 AC24

A13 B13

L14 L16 L17 L18 M11 M18 P11 P18 T11 T18

C13

U18 V17 V14 V11 U11 V18 V16 V12

C14 D14 E14 F14 G14 L11 L12

AE7 AF7

AC10

AC9

AA5 AA6

G12 G17

H7

AC7 AD7

F1

AG7

L6 L7 M6 M7

W23

AH7 AJ7

AC1 AC2 AC3 AC4 AC5

AA25 AA26

E27 F24 F25 G24 H23 H24 J23 J24 K24 K25

AA27

L23 L24 L25 M24 M25 N23 N24 N25 P24 P25

AB27

R24 R25 R26 R27 T23 T24 T27 T28 T29 U24

AB28

W25 V24 U25 Y25 V25 V23

AB29

D28 D29 E25 E26

AF29

AD2

W6 W7 Y7

A8 B15 B18 B4 B9 C15 D13

AC8

D5 E10 E7 F11

AD8 AE8 AF8

AA3 U7 V7 W1

AE28 AE29

G22

A22

F20 G21

R29

B27 A27 B28 B26 A26

B25

A24

AC12

F17 G18

F19 G20

AD25

AJ6

J6 AF20

AC16

J7

C3

AC18

P1 P2 P3 P4 P5 R1 R3 R5 R6

AC21 AC22 AG20 AH28

P6 P7 C1 N7

AD11

D1

OMIT

ICH8M

BGA

SB Power & Ground

SYNC_DATE=03/16/2007

14.0.0

26 88

051-7225

SYNC_MASTER=T9_NOME

PP1V05_S0

PP3V3_S0

PP1V5_S0_SB_VCC1_5_B

PP5V_S0_SB_V5REF

VCCCL1_5V

PP1V05_S0

PP1V25_S0

PP1V5_S0

PP3V3_S5

PP3V3_S0

PP1V5_S0

PP3V3_S0

PP1V5_S0_SB_VCC1_5_B

PP5V_S5_SB_V5REF_SUS

PP1V5_S0_SB_VCCDMIPLL

PP1V5_S0

PP3V3_S0

TP_VCCSUS1_5_INTERNAL_REG1

PP3V3_S0

PP3V3_S5

PP3V3_S0

PP1V5_S0_SB_VCCSATAPLL

PP3V3_S0

TP_VCCCL1_05_INTERNAL_REG

TP_VCCSUS1_05_INTERNAL_REG1

TP_VCCSUS1_5_INTERNAL_REG2

TP_VCCSUS1_05_INTERNAL_REG2

TP_VCCLAN1_05_INTERNAL_REG2

TP_VCCLAN1_05_INTERNAL_REG1

PP3V3_G3_SB_RTC

PP1V5_S0

PP3V3_S0

87

77

75

74

65

59

58

57

52

51

50

48

47

46

61

42

61

42

50

32

50

32

46

31

46

87

31

87

31

30

75

30

75

30

27

29

27

65

29

65

29

26

28

26

60

28

60

28

23

27

23

57

27

57

27

21

26

21

87

55

26

87

26

87

26

55

26

87

26

19

25

19

63

48

25

63

25

63

25

48

25

63

25

18

24

18

34

46

24

34

24

34

24

46

24

34

24

14

23

14

65

27

28

23

27

23

27

23

28

23

27

23

13

21

13

57

26

27

21

26

21

26

21

27

21

26

21

12

19

27

12

27

22

26

19

22

19

27

22

19

26

19

22

19

11

16

26

11

21

12

25

16

12

16

26

12

16

25

16

28

12

16

10

13

24

10

19

11

24

13

11

13

24

11

13

24

13

27

11

13

8

23

27

8

23

27

8

27

8

23

8

NCNC

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PLACE C2700 & C2705-07 < 2.54MM OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY DISTRIBUTED BETWEEN AA25..V23

PLACE C2736 NEAR PIN B27..A26

PLACE CAPS < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AJ6

38 mA S0 / 114 mA M1 & WOL

(ICH INTEL HDA SUSPEND 3.3V/1.5V PWR)

ICH VCCSUSHDA BYPASS

1 mA S3-S5

11 mA S0 /

32 mA (@ 1.5V)

(@ 1.5V)

ICH USB/VCCSUS3_3 BYPASS

0.6 uA G3

Current numbers from ICH8M Max Power Estimates Rev 2.0, doc #610194.

(ICH IO,LOGIC 1.5V PWR)

ICH VCCSUS3_3 BYPASS

117 mA S0 /

44 mA S3-S5

(ICH Reference for 5V Tolerance on Resume Well Inputs)

442 mA

(VCCSUS3_3 Total)

PLACEMENT NOTE:

P6..R6

PLACEMENT NOTE: PLACE CAPS NEAR PIN AD25 OF SB

(ICH SUSPEND 3.3V PWR)

PLACE CAPS NEAR PINS AC18..AH28

PLACE CAP NEAR PINS

PLACEMENT NOTE:

(ICH SUSPEND USB 3.3V PWR)

ICH VCCRTC BYPASS (ICH RTC 3.3V PWR)

1080 mA

(VCC1_5_A Total)

657 mA

80 mA

ICH VCC1_5_B BYPASS

47 mA

33 mA

(ICH SATA PLL PWR)

ICH VCCSATAPLL Filter

23 mA

(ICH DMI PLL PWR)

ICH VCCDMIPLL Filter

33 mA

47 mA

23 mA

PLACEMENT NOTE: PLACE CAPS < 2.54MM OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY

PLACEMENT NOTE:

OR 3.56MM ON PRIMARY NEAR PIN A24

PLACE CAPS < 2.54MM OF SB ON SECONDARY

837 mA

PLACEMENT NOTE:

1 mA

ICH V5REF Filter & Follower

1 mA

PLACE C2703 < 2.54MM OF PIN A16..T7 OF SB

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

1 mA S0-S5

(VCC3_3 Total)

3.56MM ON PRIMARY NEAR PINS AA3...Y7

PLACE < 2.54MM OF SB ON SECONDARY OR

PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AD2

PLACEMENT NOTE:

PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AD11

PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AC12

PLACEMENT NOTE:

NEAR PINS A8 ... F11

DISTRIBUTE IN PCI SECTION OF SB

OR 3.56MM ON PRIMARY NEAR PIN AF29

PLACE CAP < 2.54MM OF SB ON SECONDARY

PLACEMENT NOTE:

ICH VCCHDA BYPASS (ICH INTEL HDA CORE 3.3V/1.5V PWR)

ICH PCI/VCC3_3 BYPASS (ICH PCI I/O 3.3V PWR)

(ICH IDE I/O 3.3V PWR)

ICH IDE/VCC3_3 BYPASS

(ICH LAN I/F BUFFER 3.3V PWR)

ICH VCC_PAUX/VCCLAN3_3 BYPASS

PLACE CAP UNDER SB NEAR PINS F19 AND G20

PLACEMENT NOTE:

PLACEMENT NOTE: PLACE CAPS AT EDGE OF SB

ICH V_CPU_IO BYPASS (ICH CPU I/O 1.05V PWR)

50 mA

1 mA

1130 mA

ICH CORE/VCC1_05 BYPASS (ICH CORE 1.05V PWR)

10 mA

3.56MM ON PRIMARY NEAR PIN AC1..AC5

PLACEMENT NOTE:

PLACE NEAR PINS AC23,AC24 OF SB

OR 3.56MM ON PRIMARY NEAR PIN AE29

PLACE < 2.54MM OF SB ON SECONDARY

PLACEMENT NOTE:

(ICH USB PLL 1.5V PWR)

ICH VCCUSBPLL BYPASS

PLACE C2715 NEAR PIN D1 OF SB

3.56MM ON PRIMARY NEAR PINS F1..M7

ICH USB CORE/VCC1_5_A BYPASS

PLACE < 2.54MM OF SB ON SECONDARY OR

(ICH USB CORE 1.5V PWR)

PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR

PLACEMENT NOTE:

3.56MM ON PRIMARY NEAR PINS AE7..AJ7

PLACE < 2.54MM OF SB ON SECONDARY OR

ICH VCC1_5_A/ATX BYPASS (ICH LOGIC&IO[ATX] 1.5V PWR)

(ICH LOGIC&IO[ARX] 1.5V PWR)

ICH VCC1_5_A/ARX BYPASS

ICH V5REF_SUS Filter & Follower

ICH VCCGLANPLL Filter (ICH GLAN PLL PWR)

PLACEMENT NOTE: PLACE C2704 < 2.54MM OF PIN G4 OF SB

(ICH Reference for 5V Tolerance on Core Well Inputs)

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

PLACEMENT NOTE:

C2700

1

2

CRITICAL

CASE-B2

20%

POLY

2.5V

220UF

C2712

1

2

0.1UF

10% 16V

402

X5R

R2700

1 2

603

5%

MF-LF

1/10W

1

C2724

1

2

603

CERM

20%

6.3V

4.7UF

C2722

1

2

X5R 402

16V

10%

0.1UF

D2702

1

6

5

BAT54DW

SOT-363

D2702

4

3

2

BAT54DW

SOT-363

L2703

1 2

1.0UH-0.5A

1210

C2735

1

2

603

10UF

20%

6.3V X5R

C2703

1

2

0.1UF

10% 16V

402

X5R

C2711

1

2

6.3V CERM 402

10%

1UF

C2732

1

2

6.3V

20% CERM1

603

2.2uF

C2736

1

2

4.7uF

603

CERM

20%

6.3V

C2733

1

2

6.3V

20%

603

CERM

4.7uF

C2741

1

2

0.1UF

10% 16V

402

X5R

C2738

1

2

X5R 402

16V

10%

0.1UF

L2702

1 2

0805

10UH-100MA

C2737

1

2

X5R 402

16V

10%

0.1UF

C2739

1

2

CERM-X5R

20%

805-3

22UF

6.3V

C2702

1

2

0.1UF

10% 16V

402

X5R

R2735

1 2

0

1/16W MF-LF

5%

402

R2702

2

1

402

5% 1/16W MF-LF

100

R2701

2

1

402

5% 1/16W MF-LF

10

C2704

1

2

X5R 402

16V

10%

0.1UF

L2700

1 2

FERR-330-OHM

SM

C2705

CERM-X5R

22UF

20%

6.3V 805-3

C2706

20%

6.3V CERM-X5R 805-3

22UF

C2707

603

2.2UF

CERM1

20%

6.3V

C2701

1

2

10%

0.01UF

16V CERM 402

C2708

1

2

X5R

6.3V

20%

10UF

603

C2717

10%

1UF

402

CERM

6.3V

C2714

1

2

1UF

10% 402

CERM

6.3V

C2715

1

2

0.1UF

10% 16V

402

X5R

C2718

1

2

0.1UF

10% 16V

402

X5R

C2719

1

2

X5R 402

16V

10%

0.1UF

C2721

1

2

0.1UF

10% 16V

402

X5R

C2723

1

2

X5R 402

16V

10%

0.1UF

C2725

1

2

0.1UF

10% 16V

402

X5R

C2726

1

2

0.1UF

10% 16V

402

X5R

C2727

1

2

0.1UF

10% 16V

402

X5R

C2728

1

2

0.1UF

10% 16V

402

X5R

C2729

1

2

X5R 402

16V

10%

0.1UF

C2730

1

2

X5R 402

16V

10%

0.1UF

C2734

1

2

X5R 402

16V

10%

0.1UF

C2731

1

2

0.1UF

10% 16V

402

X5R

051-7225

14.0.0

8827

SYNC_DATE=01/17/2007

SB Decoupling

SYNC_MASTER=T9_NOME

PP1V5_S0

PP5V_S5

PP1V5_S0

PP1V25_S0

PP1V05_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S5

PP3V3_S0

PP3V3_S5

VOLTAGE=5V

MIN_NECK_WIDTH=0.25MM

PP5V_S5_SB_V5REF_SUS

MIN_LINE_WIDTH=0.3MM

PP5V_S0

PP3V3_S0

PP5V_S0_SB_V5REF

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V

PP1V5_S0_SB_VCCDMIPLL_F

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

PP1V5_S0_SB_VCCSATAPLL_F

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.5V

PP1V5_S0_SB_VCCDMIPLL

PP1V5_S0_SB_VCCSATAPLL

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.5V

PP1V5_S0_SB_VCC1_5_B

VOLTAGE=1.5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

PP3V3_S5

PP3V3_G3_SB_RTC

PP3V3_S5

87

77

75

74

65

59

58

57

52

51

50

48

47

46

61

42

50

32

46

31

87

31

87

31

87

30

75

30

75

30

75

27

29

65

29

65

29

65

26

28

60

28

60

78

28

60

74

23

27

57

27

57

76

27

57

87

65

87

21

26

55

26

55

65

26

55

63

19

25

48

25

48

59

25

48

34

62

34

18

24

46

24

46

58

24

46

27

61

27

65

14

23

28

23

28

57

23

28

26

60

26

57

13

21

27

21

27

52

21

27

22

57

22

26

12

19

26

19

26

47

19

27

26

12

43

12

21

11

16

25

16

25

42

16

26

25

28

25

11

9

11

19

10

13

24

13

24

8

13

24

26

24

8

26

7

8

26

23

8

23

8

OUT

IN

OUT

IN

NCNC

IN

OUT

IN

OUT OUT

OUT

IN

OUT

IN

A

B

Y

132

A

B

Y

132

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

threshold at approx .8 ms nominal

ON POWER UP: This delay ensures that GPU clocks run before GPU is released from reset (RC should reach schmitt trigger

NOTE: R2800 and D2805 form the double fault protection for RTC battery.

PWROK Circuit

PCI Reset Connections

ON POWER DOWN: This ensures that GPU is put into

and clocks are still running.

reset while chip is still powered

System Reset "Button"

VRMPWRGD Inverter

Muxed GFX GPU Reset Support

NC

Platform Reset Connections

to solder a reset button.

NC

Unbuffered

NC

GPU_IOENABLE_RC is used to isolate

w/ 1K pullup on PM_ALL_GPU_PGOOD)

RTC Power Sources

on the board to short or

it provides a set of pads

This part is never stuffed,

NC

SB RTC Crystal

CPU VCore ForcePSI

518S0487

Coin-Cell Connector

certain GPU signals from the rest of the system. RC prevents glitch that would otherwise be injected

reset edge and isolating FET Cgs.

into isolated signals due to sharp

R2806

1 2

402

20K

MF-LF

5%

1/16W

23

C2830

1

2

402

0.1UF

10V

20% CERM

C2806

1

2

402

10%

1UF

CERM

6.3V

10 13

R2805

1

2

5%

402

1M

1/16W MF-LF

7

25 45

R2825

1

2

1/16W 402

5% MF-LF

10K

R2800

2 1

1K

MF-LF

1/16W

402

5%

C2810

1 2

12pF

402

50V

5%

CERM

C2811

1 2

CERM

402

12pF

50V

5%

Y2810

2 4

1 3

CRITICAL

SM-2

32.768K

R2810

1 2

402

1/16W

5%

MF-LF

0

R2811

1

2

402

5%

10M

MF-LF

1/16W

7

24 28 77

R2826

1 2

402

ITP&XDP

MF-LF

5%

1/16W

1K

D2805

1

4

6

3

5

2

BAT54DW

SOT-363

R2862

1 2

5%

100

MF-LF

1/16W

402

R2863

1 2

402

MF-LF

0

5%

1/16W

R2864

1 2

100

1/16W

5%

402

MF-LF

R2860

1 2

402

1/16W

5%

MF-LF

100

C2840

1

2

402

0.1UF

CERM

20% 10V

7 9

16 58

45 46 65

7 9

25

C2880

1

2

402

0.1UF

CERM

20% 10V

R2881

1 2

0

5%

1/16W

402

MF-LF

7

16

7

47

7

45

34

7

66

U2880

3

2

1

4

5

MC74VHC1G08

SC70

U2840

3

2

1

4

5

MC74VHC1G08

SC70

U2830

3

2

1

4

5

MC74VHC1G00

SC70-5

R2820

1

2

SILK_PART=SYS RST

603

1/10W

0

5%

OMIT

MF-LF

38

R2861

1 2

MF-LF

1/16W

5%

0

402

38

R2890

1 2

100

MF-LF

5%

1/16W

402

7

24

28 76 77

7

24 28 77

10 28 58 10 28 58

58

7

25

R2840

1

2

10K

MF-LF

5% 1/16W

402

R2841

1

2

MF-LF

1/16W

402

5%

10K

J2800

3

4

1 2

M-RT-SM

BM02B-ACHKS-GAN-TF-LF-SN-M

CRITICAL

R2882

1 2

5%

MF-LF

1K

402

1/16W

C2882

1

2

50V

10% CERM

402

0.001UF

R2865

1 2

1/16W

0

MF-LF

402

5%

35

30 77

C2883

12

20% 10V

CERM

402

0.1UF

R2885

1 2

402

MF-LF

10K

1/16W

5%

C2885

1

2

402

CERM

10%

0.047UF

16V

R2886

1

2

24.3K

1%

402

MF-LF

1/16W

U2883

5

6

4

8

3

US8

74LVC2G132

CRITICAL

U2883

1

2

4

8

7

74LVC2G132

US8

CRITICAL

25

23 57 65

R2887

1 2

0

1/16W

402

MF-LF

5%

EXTGPU_RST_HW

R2880

1 2

0

402

5%

MF-LF

1/16W

EXTGPU_RST_SW

7

23

C2805

1

2

CERM

402

6.3V

1UF

10%

SB Misc

SYNC_MASTER=(T9_MLB)

88

14.0.0

051-7225

28

SYNC_DATE=08/24/2006

GPU_RESET_R_L

MAKE_BASE=TRUE

GPU_IOENABLE_RC

CPU_PSI_L

MAKE_BASE=TRUE

CPU_PSI_L

SB_RTC_X1_R

VR_PWRGD_CLKEN

ALL_SYS_PWRGD

PP3V3_S0

RST_L_AND_GPU_PGOOD_L

GPU_PGOOD_RC

VR_PWRGD_CLKEN_L

PM_ALL_GPU_PGOOD

SMC_LRESET_L

SB_SM_INTRUDER_L

SB_RTC_RST_L

PP3V3_G3_SB_RTC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

FW_PLT_RST_L

NB_RESET_L

LIO_PLT_RST_L

SB_RTC_X1

XDP_DBRESET_L

PM_SYSRST_L

MIN_NECK_WIDTH=0.2 mm

PPVBATT_G3_RTC_R

MIN_LINE_WIDTH=0.3 mm VOLTAGE=3.3V

PP3V42_G3H

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PPVBATT_G3_RTC

PP3V3_S0

VR_PWRGOOD_DELAY

SB_RTC_X2

PP3V3_S0

GPU_RESET_L

GPU_IOENABLE_RC GPU_IOENABLE_RC

PCI_FW_RST_L

PP3V3_S5

DEBUG_RESET_L

PLT_RST_L

MAKE_BASE=TRUE

PLT_RST_L

ENET_RESET_L

PM_SB_PWROK

EXTGPU_RST_L

EXTGPU_PWR_EN

RST_L_AND_GPU_PGOOD

PCI_RST_L

EXTGPU_RST_QUAL_L

PP3V3_S0

87

87 87

87

77

77 77

77

75

75 75

75

74

74 74

74

65

65 65

65

59

59 59

59

58

58 58

58

57

57 57

57

52

52 52

52

51

51 51

51

50

50 50

50

48

48 48

48

47

47 47

47

46

46 46

46

42

42 42

42

32

32 32

32

31

31 31

31

30

30 30

87

30

29

29 29

75

29

28

28 28

65

28

27

78

27 27

60

27

26

65

26 26

57

26

25

48

25 25

55

25

24

47

24 24

48

24

23

46

23 23

46

23

21

45

21 21

27

21

19

43

19 19

26

19

77

16

27

34

16 16

25

16

76

13

26

8

13 13

24

13

28

8

23

7

8

23

8

IN IN

OUT OUT

OUT

IN

OUT

OUT OUT OUT OUT

IN BI

OUT

IN

BI

OUT

IN

OUT

IN

OUT

OUT OUT

IN

VSS_PCI

CLKREQ_7*

CLKREQ_8*

GPU_STOP*

REF_0/FS_C/TEST_SEL

48M/FS_A

DOT_96/27M

DOT_96*/27M_SS

SRC_8*

SRC_8

PCI_5/FCT_SEL

PCIF_0/ITP_EN

VDD_PCI

VDD_48

THRM_PAD

SRC_4*

CLKREQ_3*

SRC_3

SRC_0/LCD_CLK

SRC_0*/LCD_CLK*

CPU_1_MCH*

CPU_1_MCH

CPU_ITP*/SRC_10*

CPU_ITP/SRC_10

VSS_SRC

VSS_REF

VSS_CPU

VSS_48

SDA

PCIF_1

PCI_4

PCI_3

PCI_2

PCI_1

VSS_A

XTAL_OUT

CLKREQ_6*

CLKREQ_5*

CLKREQ_4*

CLKREQ_1*

SCL

CPU_0

SRC_1

SRC_2*

SRC_2

SRC_4

SRC_5*

SRC_5

SRC_7*

SRC_7

SRC_6*

SRC_6

VDD_REF

CPU_0*

SRC_3*

CPU_STOP*

PCI_STOP*

XTAL_IN

VDD_A

FS_B/TEST_MODE

VDD_CPU

SRC_1*

CKPWRGD/PD*

VDD_SRC

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NOTE: Pin 53 was REF_1 on SLG8LP537.

(INT PU*)

(*) CLKREQ# internal pull-ups/downs only on SLG2AP101, not SLG8LP537.

Yukon PCIe 100MHz

on SLG8LP537 or device is set to CK410M mode.

NEED TO CHECK CAP VALUE

(266.6)

FS_AFS_BFS_C

One 10uF cap per rail.

1 1

0 1 1

1 1

1 0 0

10

0 0

00

1 0 1

166.6

(333.3)

100.0

(400.0)

RSVD

1

0

200.0

0 1

133.3

CPU MHz

CPU Host Clock (FSB/4)

One 0.1uF per power pin (place at pin).

GMCH Host Clock (FSB/4) ITP/XDP Host Clock (FSB/4)

GPU PCIe 100MHz (Ext GFX)

ICH SATA 100MHz

ICH DMI/PCIe 100MHz

From ICH

GMCH Display PLL B 100MHz (Int GFX)

SMC LPC 33MHz

ExpressCard / Spare 100MHz

Linda/LPC+ 33MHz

Spare 33MHz

Spare 33MHz Spare 33MHz

GMCH DMI/PCIe 100MHz

PCIe Mini Card (AirPort) 100MHz

(Or 27MHz Spread & Non-Spread for Ext GFX)

ICH USB/Audio 48MHz ICH SIO/LPC/REF 14.318MHz

From ICH

Spare 100MHz

(INT PU*)

ICH PCI 33MHz

NOTE: Pin 40 was PGMODE on SLG8LP537. Do not pull low

GMCH Display PLL A 96MHz (Int GFX)

(INT PU*)

TP or GPU PGOOD

(For External Graphics)

(For Internal Graphics)

LCD_CLK-

PIN 11

SRC_0-SRC_0+

LCD_CLK+

PIN 10

PIN 7

DOT_96-

27M w/SS

PIN 6

DOT_96+

27M

FCT_SEL

1

0

(INT PU*)

(INT PD*)

FW PCI 33MHz

C2910

1

2

6.3V

20% 603

X5R

10UF

L2902

1 2

0402

FERR-120-OHM-1.5A

C2912

1

2

16V

10%

402

X5R

0.1UF

C2913

1

2

16V

10%

402

X5R

0.1UF

C2915

1

2

16V

10%

402

X5R

0.1UF

C2909

1

2

16V

10% 402

X5R

0.1UF

7

25 30

7

25 30

10 30 84

7

14 30 84

7

14 30 84

13 30 79 84

7

16 22 30 84

7

16 22 30 84

9

30 66 84

9

30 66 84

23 30 84

7

16 30 84

23 30 84

30 34 84

7

16 30 84

30 34 84

30 84

25

30 84

C2990

1

2

402

CERM

50V

5%

18pF

C2989

1

2

50V

5%

CERM

18pF

402

30 84

25 31 32 34 48 82

C2907

1

2

6.3V

20%

603

X5R

10UF

C2908

1

2

16V

10%

402

X5R

0.1UF

30 84

30

30 84

C2906

1

2

16V

10%

402

X5R

0.1UF

C2905

1

2

16V

10%

402

X5R

0.1UF

C2904

1

2

16V

10%

402

X5R

0.1UF

C2903

1

2

16V

10%

402

X5R

0.1UF

C2911

1

2

6.3V

10% 402

CERM

1UF

C2901

1

2

6.3V

20%

603

X5R

10UF

C2902

1

2

16V

10%

402

X5R

0.1UF

L2901

1 2

0402

FERR-120-OHM-1.5A

C2900

1

2

6.3V

10%

402

CERM

1UF

R2901

1 2

1/16W

5%

402

MF-LF

2.2

R2902

1 2

1/16W

5%

402

MF-LF

1

C2914

1

2

6.3V

20%

603

X5R

10UF

R2900

1 2

402

MF-LF

2.2

1/16W

5%

30 35 84

30

30 34

30 35

R2903

1

2

1/16W

5%

402

MF-LF

10K

XDP

30 84

25

30 84

30 34 84

24 30 84

7

16

Y2901

1 2

5X3.2-SM

14.31818

CRITICAL

C2916

1

2

6.3V

20%

603

X5R

10UF

L2903

1 2

0402

FERR-120-OHM-1.5A

U2900

4

2

9

59

20

60

25

40

34

45

44

42

41

37

36

55

6

7

8

53

57 58 63 64 65

56

68

1

54

47 48

10

11

13

14

15

16

18

19

21

22

23

24

26

27

29

30

33

32

69

33843616749121728

35

5

39

46

62 66

52

31

51 50

OMIT

SLG2AP101

QFN

30

051-7225

29 88

14.0.0

SYNC_DATE=03/16/2007

SYNC_MASTER=T9_NOME

Clock (CK505)

NB_CLK100M_PCIE_P

SMBUS_SB_SCL

MIN_NECK_WIDTH=0.2mm VOLTAGE=3.3V

PP3V3_S0M_CK505_VDDA

MIN_LINE_WIDTH=0.5mm

CK505_XTAL_IN

CK505_FSB_TEST_MODE

PM_STPPCI_L PM_STPCPU_L

PCIE_CLK100M_EXCARD_N

FSB_CLK_CPU_N

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.5mm VOLTAGE=3.3V

PP3V3_S0M_CK505_VDD_PCI

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.5mm VOLTAGE=3.3V

PP3V3_S0M_CK505_VDD_REF

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.5mm VOLTAGE=3.3V

PP3V3_S0M_CK505_VDD_CPU_SRC

SB_CLK100M_SATA_P

SB_CLK100M_DMI_P

SB_CLK100M_DMI_N

PEG_CLK100M_GPU_N PEG_CLK100M_GPU_P

FSB_CLK_CPU_P

PEG_CLKREQ_L

SB_SATA_CLKREQ_L

NB_CLKREQ_L

CK505_PCI1_CLK TP_CK505_PCI2_CLK CK505_PCI3_CLK TP_CK505_PCI4_CLK

CK505_PCIF1_CLK

SMBUS_SB_SDA

XDP_CLK_P

XDP_CLK_N

FSB_CLK_NB_P

FSB_CLK_NB_N

NB_CLK100M_DPLLSS_N NB_CLK100M_DPLLSS_P

EXCARD_CLKREQ_L SB_CLK100M_SATA_N

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.5mm VOLTAGE=3.3V

PP3V3_S0M_CK505_VDD48

CK505_CLK27M_SS

CK505_48M_FSA CK505_REF0_FSC

PP3V3_S0

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.5mm VOLTAGE=3.3V

PP3V3_S0M_CK505_VDDA_R

NB_CLK100M_PCIE_N

CK505_XTAL_OUT

CK505_PCI5_CLK_FCTSEL

CK505_PCIF0_CLK_ITPEN

PP3V3_S0

PCIE_CLK100M_MINI_P

CLK_PWRGD

GPU_STOP_L

CK505_CLK27M

TP_CK505_CLKREQ7_L

TP_PCIE_CLK100M_SRC7P

TP_PCIE_CLK100M_SRC7N

MINI_CLKREQ_L

PCIE_CLK100M_EXCARD_P

PCIE_CLK100M_ENET_P ENET_CLKREQ_L

PCIE_CLK100M_ENET_N

PCIE_CLK100M_MINI_N

87

77

75

74

65

59

58

57

52

51

50

48

47

46

42

32

31

30

29

28

27

26

25

24

23

21

19

16

13

8

30

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

IN

OUT

BI

OUT

IN

OUT

IN

OUT

G

D

S

IN

SEL

B0

GND

B1

0

1

A

VCC

SEL

B0

GND

B1

0

1

A

VCC

IN

OUT

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

are not shown here).

NB and SATA CLKREQs are not remappable (and thus

GPU Clock Gating

Silego SLG2AP101 has internal pull-ups on all CLKREQ# pins. Support for SL8GLP537 or equiv. only.

Unused Clocks

(ITP HOST 167/200MHZ)

(FW 100MHz)

(LINDA/LPC+ LPC 33MHZ)

(Only 100-200MHz supported by

(WIRELESS PCIe MINI 100MHZ)

CLK Termination

(Spare 33MHZ)

(Reserved for TPM PCI 33MHZ)

(GMCH PEG/DMI 100MHZ)

CLKREQ Controls

(Note: HOST/SRC/GFX clock termination removed. Silego SL8GLP536 or equiv. support only)

(Int Gfx LVDS 100MHz)

(SMC PCI 33MHZ)

(FIREWIRE PCI 33MHZ)

(ICH8M PCI 33MHZ)

(Ext GFX Spread 27MHz)

(Ext GFX 27MHz)

(ENET 100MHZ)

(GPU PCIe 100MHz)

(GMCH HOST 167/200MHZ)

(CPU HOST 167/200MHZ)

(TO ICH8M USB 48MHZ)

SLG8LP536 and CY28545-5)

for manual CPU clk frequency.

NO STUFF R3082, R3086 & R3090

CPU MHz

200.0

166.6

100.0

133.3

(266.6)

(333.3)

(400.0)

FS_AFS_BFS_C

1 RSVD

1

0

1

0

0 1

0

00

0

10

1

0 1

1 1

11

(TO/FROM CK505)

(TO MCH FS_C)

(TO CK505)

(TO MCH FS_B)

(TO/FROM CK505)

(TO ICH8M 14.318MHZ)

(FROM CPU FS_C)

(FROM CPU FS_A)

(FROM CPU FS_B)

0

(ICH8M SATA 100MHZ)

(ExpressCard 100MHz)

(TO MCH FS_A)

FCT_SEL (GFX clock select)

CK505 Configuration Straps

(ICH8M DMI 100MHZ)

FS_A, FS_B, FS_C (Host clock freq select)

10 29 30 84

7

14 29 30 84

7

14 29 30 84

29 30 84

7

16 29 30 84

7

16 29 30 84

7

16 29 30 84

7

16 29 30 84

29 30 35 84

29 30 35 84 29 30 35 84

29 30 35 84

24 29 30 84

29 84

38 84

45 84

24 84

29 30 34 84

29 30 34 84 29 30 34 84

29 30 34 84

7

47 84 29 84

24 29 30 84

R3067

1

2

5% 1/16W MF-LF

10K

402

R3083

1

2

1K

MF-LF

402

5%

1/16W

R3084

1

2

1/16W

5%

402

MF-LF

1K

29

29 84

23 29 30 84

R3080

1

2

NO STUFF

1/16W

5%

402

1K

MF-LF

R3082

1 2

402

0

MF-LF

5%

1/16W

10 79

R3086

1 2

0

MF-LF

402

5%

1/16W

R3087

1

2

5%

1/16W

NO STUFF

402

1K

MF-LF

29 30 34 84

7

14 29 30 84

29 30 34 84

9

29 30 66 84

9

29 30 66 84

9

29 30 66 84

9

29 30 66 84

7

14 29 30 84

29 30 84

10 29 30 84

25 84

R3032

1 2

MF-LF

402

5%

1/16W

33

29 84

10 29 30 84

R3081

1 2

1K

402

5% 1/16W MF-LF

13 16 79

R3085

1 2

MF-LF

402

1/16W

5%

1K

13 16 79

10 79

R3090

1 2

0

MF-LF

402

5%

1/16W

R3088

1

2

NO STUFF

1K

1/16W

5%

402

MF-LF

R3091

1

2

1K

MF-LF

402

5%

1/16W

13 29 30 79 84

R3089

1 2

MF-LF

402

5% 1/16W

1K

13 16 79

25 84

R3034

1 2

MF-LF

5%

1/16W

402

33

29 84

13 29 30 79 84

R3024

1 2

402

1/16W

5%

MF-LF

33

R3025

1 2

33

1/16W

5%

402

MF-LF

7

16 22 29 30 84

7

16 22 29 30 84

7

16 22 29 30 84

7

16 22 29 30 84

R3026

1 2

MF-LF

5%

1/16W

402

33

R3027

1 2

33

5% 1/16W MF-LF

402

R3028

1 2

MF-LF

5%

1/16W

402

33

R3030

1 2

402

MF-LF

1/16W

5%

33

R3035

2

1

402

5% 1/16W MF-LF

10K

R3033

2

1

1/16W

5%

2.2K

402

MF-LF

R3046

1 2

NO STUFF

10K

1/16W MF-LF

5%

402

R3047

1 2

10K

1/16W MF-LF

5%

402

NO STUFF

29 30 34

7

25 29

7

25 29

29 30 84

29 30 34

29 30 35

29 30

71 72 86

Q3050

6

2

1

2N7002DW-X-F

SOT-363

SLG8LP537

28 30 77

U3050

43

1

2

6

5

NC7SB3157P6X

SC70

SLG8LP537

U3055

43

1

2

6

5

GPU_SS_EXT

SC70

NC7SB3157P6X

C3055

1 2

GPU_SS_EXT

CERM

20%

0.1UF

10V 402

C3050

1 2

SLG8LP537

20% 10V

CERM

402

0.1UF

28 30 77

29 30 35

R3050

1

2

SLG2AP101

0

5%

402

MF-LF

1/16W

R3055

1

2

SLG2AP101

1/16W MF-LF

402

5%

0

29 30

R3051

1

2

SLG2AP101

0

402

MF-LF

1/16W

5%

13 29 30 79 84

Clock Termination

SYNC_DATE=08/23/2006

14.0.0

8830

051-7225

SYNC_MASTER=(MASTER)

CK505_FSA

CK505_PCI5_CLK_FCTSEL

PP3V3_S0

PEG_CLK100M_GPU_N

SB_CLK100M_DMI_P

PCIE_CLK100M_EXCARD_P

MAKE_BASE=TRUE

CK505_PCIF1_CLK

CK505_CLK27M

MAKE_BASE=TRUE

PP1V05_S0

CK505_FSB_TEST_MODE

CK505_FSC

SB_CLK48M_USBCTLR

CPU_BSEL<0>

CPU_BSEL<1>

CPU_BSEL<2>

CK505_REF0_FSC

SB_CLK14P3M_TIMER

NB_BSEL<0>

CK505_48M_FSA

NB_BSEL<1>

NB_BSEL<2>

CK505_PCI1_CLK

CK505_PCIF0_CLK_ITPEN

GPU_CLK27M

CK505_PCI3_CLK

PCI_CLK33M_FW

PCI_CLK33M_SB

PCI_CLK33M_SMC

GPU_CLK27M_SS

FSB_CLK_CPU_N

MAKE_BASE=TRUE

FSB_CLK_CPU_N

FSB_CLK_CPU_P

FSB_CLK_NB_N

FSB_CLK_NB_P FSB_CLK_NB_P

MAKE_BASE=TRUE

FSB_CLK_NB_N

MAKE_BASE=TRUE

XDP_CLK_P

MAKE_BASE=TRUE

XDP_CLK_N

MAKE_BASE=TRUE

XDP_CLK_P

PEG_CLK100M_GPU_P

MAKE_BASE=TRUE

PEG_CLK100M_GPU_N

MAKE_BASE=TRUE

SB_CLK100M_DMI_N

SB_CLK100M_DMI_P

MAKE_BASE=TRUE

SB_CLK100M_DMI_N

MAKE_BASE=TRUE

PCIE_CLK100M_EXCARD_N

SB_CLK100M_SATA_P

NB_CLK100M_PCIE_N

NB_CLK100M_PCIE_P

SB_CLK100M_SATA_N

MAKE_BASE=TRUE

SB_CLK100M_SATA_P

PCIE_CLK100M_MINI_N

PCIE_CLK100M_MINI_P

TP_PCIE_CLK100M_SRC7P TP_PCIE_CLK100M_SRC7N

MAKE_BASE=TRUE

TP_PCIE_CLK100M_SRC7N

MAKE_BASE=TRUE

PCIE_CLK100M_ENET_N

MAKE_BASE=TRUE

PCIE_CLK100M_ENET_P

XDP_CLK_N

PP1V05_S0

SB_CLK100M_SATA_N

TP_PCIE_CLK100M_SRC7P

MAKE_BASE=TRUE

CK505_CLK27M_SS

MAKE_BASE=TRUE

PM_STPPCI_L

PM_STPCPU_L

MAKE_BASE=TRUE

TP_CK505_PCI2_CLK

TP_CK505_PCI4_CLK

MAKE_BASE=TRUE

TP_CK505_PCI2_CLK

TP_CK505_PCI4_CLK

PCIE_CLK100M_EXCARD_N

MAKE_BASE=TRUE

PP3V3_S0

NB_CLK100M_PCIE_P

MAKE_BASE=TRUE

PP1V05_S0

FSB_CLK_CPU_P

MAKE_BASE=TRUE

NB_CLK100M_PCIE_N

MAKE_BASE=TRUE

PCIE_CLK100M_MINI_N

MAKE_BASE=TRUE

PCIE_CLK100M_MINI_P

PEG_CLKREQ_L

PCIE_CLK100M_EXCARD_P

PEG_CLK100M_GPU_P

NB_CLK100M_DPLLSS_P

MAKE_BASE=TRUE

NB_CLK100M_DPLLSS_N

MAKE_BASE=TRUE

NB_CLK100M_DPLLSS_N

NB_CLK100M_DPLLSS_P

PCI_CLK33M_LPCPLUS

CK505_CLK27M_SS

CK505_CLK27M

PCIE_CLK100M_ENET_N

PCIE_CLK100M_ENET_P

PEG_CLKREQ_L

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

GPU_CLK27M_GATED

GPU_CLK27M_SS_GATED

GPU_CLK27M

PP3V3_S0

GPU_CLK27M_SS

ENET_CLKREQ_L

EXCARD_CLKREQ_L

MINI_CLKREQ_LMINI_CLKREQ_L

MAKE_BASE=TRUE

EXCARD_CLKREQ_L

MAKE_BASE=TRUE

TP_CK505_CLKREQ7_LTP_CK505_CLKREQ7_L

MAKE_BASE=TRUE

ENET_CLKREQ_L

MAKE_BASE=TRUE

ENET_CLKREQ_L

PM_ALL_GPU_PGOOD

MAKE_BASE=TRUE

GPU_STOP_L GPU_STOP_L

87

77

75

74

65

59

58

57

52

51

50

48

47

46

42

61

42

61

42

32

50

32

50

32

31

46

31

46

31

30

29

27

29

27

29

28

26

28

26

28

27

23

27

23

27

26

21

26

21

26

25

19

25

19

25

24

18

24

18

24

23

14

23

14

23

21

13

21

13

21

19

12

19

12

19

35

16

84

11

84

11

84

16

11

16

30

13

30

10

86

30

10

30

13

10

30

86

13

86

30

29

30

84

8

29

8

84

30

29

8

29

8

29

30

8

30

29

VSS7

VSS12

VSS9

KEY

DQ57

DQ51

DQS6

DQ43

DQ42

DQ40

DQ34

DQ1

DQ0

VSS1

DQS0* DQS0 VSS6 DQ2 DQ3

DQ8 DQ9 VSS10 DQS1* DQS1

DQ10 DQ11 VSS14

VSS16 DQ16 DQ17 VSS18 DQS2* DQS2 VSS21 DQ18 DQ19 VSS23 DQ24 DQ25 VSS25 DM3 NC1 VSS27 DQ26 DQ27 VSS29 CKE0 VDD0 NC2 BA2 VDD2 A12 A9 A8 VDD4 A5 A3 A1 VDD6 A10/AP BA0 WE* VDD8 CAS* NC/S1* VDD10 NC/ODT1 VSS31 DQ32 DQ33 VSS33 DQS4* DQS4 VSS36

DQ35 VSS38

DQ41 VSS40 DM5 VSS41

VSS43 DQ48 DQ49 VSS45 NC_TEST VSS47 DQS6*

VSS49 DQ50

VSS51 DQ56

VSS53 DM7 VSS55 DQ58 DQ59 VSS57 SDA SCL VDDSPD

DM6

DQ55

DQ61

DQ46 DQ47

DQ12

DM1

DM0

DQ7

DQ13

VSS11

CK0

CK0*

VSS13

DQ14 DQ15

VSS15

VSS17

DQ20 DQ21

VSS19

NC0 DM2

VSS22

DQ22 DQ23

VSS24

DQ28

DQ29 VSS26 DQS3*

DQS3 VSS28

DQ30

DQ31 VSS30

NC/CKE1

VDD1

NC/A15 NC/A14

VDD3

A11

A7 A6

VDD5

A4 A2 A0

VDD7

BA1

RAS*

S0* VDD9 ODT0

NC/A13

VDD11

NC3

VSS32

DQ36 DQ37

VSS34

DM4

VSS35

DQ38 DQ39

VSS37

DQ44 DQ45

VSS39 DQS5*

DQS5

VSS42

VSS44

DQ52 DQ53

VSS46

CK1 CK1*

VSS48

VSS50

DQ54

VSS52

DQ60

VSS54 DQS7*

DQS7

VSS56

DQ62 DQ63

VSS58

SA0

SA1

DQ5 VSS2

VREF

VSS4

VSS8

VSS0

DQ4

VSS5

DQ6

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Signal aliases required by this page:

NC

"Factory" (thru-hole) slot

DDR2 Bypass Caps

NC

516-0140

NC

(For return current)

ADDR=0xA0(WR)/0xA1(RD)

NC

- =PPSPD_S0M_MEM_A (2.5V - 3.3V)

- =I2C_SODIMMA_SDA BOM options provided by this page:

(NONE)

- =I2C_SODIMMA_SCL

- =PP1V8_S3M_MEM_A

- =PP0V9_S3M_MEM_DIMMVREFA

Power aliases required by this page:

Page Notes

C3113

1

2

10%

1UF

CERM

6.3V 402

C3112

1

2

10%

1UF

CERM

6.3V 402

C3109

1

2

6.3V

20% 603

X5R

10UF

C3111

1

2

10%

1UF

CERM

6.3V 402

C3108

1

2

6.3V

20% 603

X5R

10UF

C3110

1

2

10%

1UF

CERM

6.3V 402

C3119

1

2

1UF

CERM

6.3V

10% 402

C3118

1

2

1UF

CERM

6.3V

10% 402

C3117

1

2

10%

1UF

CERM

6.3V 402

C3116

1

2

10%

1UF

CERM

6.3V 402

C3121

1

2

1UF

CERM

6.3V

10% 402

C3120

1

2

1UF

CERM

6.3V

10% 402

C3115

1

2

10%

1UF

CERM

6.3V 402

C3114

1

2

10%

1UF

CERM

6.3V 402

C3100

1

2

10V

20%

402

CERM

0.1uF

C3101

1

2

6.3V

CERM1

603

20%

2.2uF

J3100

102B

105B

90B89B

101B

100B

99B

98B97B

94B

92B

93B

91B

107B

106B

85B

113B

30B 32B

164B 166B

79B

10B

26B

52B

67B

130B

147B

170B

185B

5B

35B 37B

20B 22B

36B 38B

43B 45B

55B 57B

7B

44B 46B

56B 58B

61B 63B

73B 75B

62B 64B

17B

74B 76B

123B 125B

135B 137B

124B 126B

134B 136B

19B

141B 143B

151B 153B

140B 142B

152B 154B

157B 159B

4B

173B 175B

158B 160B

174B 176B

179B 181B

189B 191B

6B

180B 182B

192B 194B

14B 16B

23B 25B

13B

11B

31B

29B

51B

49B

70B

68B

131B

129B

148B

146B

169B

167B

188B

186B

201

202

116B

86B

84B

80B

119B

115B

50B

69B

83B

120B

163B

114B

108B 110B

198B 200B

197B

195B

81B

117B 118B

82B

87B 88B

95B 96B

103B 104B

111B 112B

199B

1B 2B

27B 28B

33B 34B

39B 40B

41B 42B

47B 48B

3B

53B 54B

59B 60B

65B 66B

71B 72B

77B

8B

78B

121B 122B

127B 128B

132B

133B

138B

139B

144B

145B

149B 150B

155B 156B

161B 162B

165B

168B

171B

9B

172B

177B 178B

183B 184B

187B

190B

193B

196B

12B

15B

18B

21B

24B

109B

CRITICAL

DDR2-SODIMM-DUAL

F-RT-TH1

31 88

14.0.0

051-7225

DDR2 SO-DIMM Connector A

SYNC_MASTER=(M59_SYNC)

SYNC_DATE=08/24/2006

MEM_A_DQ<58> MEM_A_DQ<60>

MEM_A_DQ<51>

PP1V8_S3

PP0V9_S3_MEM_VREF

MEM_A_DQ<6>

MEM_A_DQ<15>

MEM_A_DQ<9>

MEM_A_A<2>

MEM_A_A<4>

MEM_A_A<7>

MEM_A_A<11>

MEM_A_DQ<29>

MEM_A_DQ<25>

MEM_A_DQS_P<3>

MEM_A_DQS_N<3>

MEM_A_DQ<24>

MEM_A_DQ<26>

MEM_A_DM<2>

PM_EXTTS_L<0>

MEM_A_DQ<20>

MEM_A_DQ<18>

MEM_A_DQ<5>

MEM_A_DQ<1>

MEM_CLK_N<0>

MEM_CLK_P<0>

MEM_A_DM<0>

MEM_A_DQ<3>

MEM_A_DQ<12>

MEM_A_DQ<8>

MEM_A_DQ<35>

MEM_A_DQ<47>

MEM_A_DQ<44>

MEM_A_DQS_P<5>

MEM_A_DQS_N<5>

MEM_A_DQ<40>

MEM_A_DQ<45>

MEM_A_DQ<52>

MEM_A_DQ<49>

MEM_A_DM<6>

MEM_CLK_N<1>

MEM_CLK_P<1>

MEM_A_DQ<50>

MEM_A_DQ<55>

MEM_A_DQ<61>

MEM_A_DQ<57>

MEM_A_DQS_P<7>

MEM_A_DQS_N<7>

MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_A_DQ<32>

MEM_A_DQ<33>

MEM_A_DM<4>

MEM_A_DQ<39>

MEM_A_A<13>

MEM_ODT<0>

MEM_CS_L<0>

MEM_A_RAS_L

PP3V3_S0

SMBUS_SB_SDA

MEM_A_DQ<41>

MEM_A_DQ<46>

MEM_A_DM<5>

MEM_A_DQ<42>

MEM_A_DQ<43>

MEM_A_DQ<53>

MEM_A_DQ<48>

MEM_A_DQS_P<6>

MEM_A_DQ<54>

MEM_A_DQ<59>

MEM_A_DQ<56>

MEM_A_DQ<34>

MEM_A_DQ<37>

MEM_A_DQS_P<4>

MEM_A_DQ<38>

MEM_A_DQ<36>

MEM_ODT<1>

MEM_CS_L<1>

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_BS<0>

MEM_A_A<10>

MEM_A_A<1>

MEM_A_A<3>

MEM_A_A<5>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<12>

MEM_A_BS<2>

PP1V8_S3

MEM_CKE<0>

MEM_A_DQ<28>

MEM_A_DQ<30>

MEM_A_DQ<27>

MEM_A_DQ<31>

MEM_A_DQ<16>

MEM_A_DQ<23>

MEM_A_DQS_P<2>

MEM_A_DQS_N<2>

MEM_A_DQ<21>

MEM_A_DQ<17>

MEM_A_DQ<4>

MEM_A_DQS_P<0>

MEM_A_DQS_N<0>

MEM_A_DQ<0>

MEM_A_DQ<7>

MEM_A_DQ<11>

MEM_A_DQ<10>

MEM_A_DQS_P<1>

MEM_A_DQS_N<1>

MEM_A_DQ<13>

MEM_A_DQ<2>

MEM_A_DM<1>

MEM_A_DQ<14>

MEM_A_BS<1>

MEM_A_A<0>

MEM_A_DQS_N<4>

SMBUS_SB_SCL

MEM_A_A<6>

MEM_A_DM<3>

MEM_CKE<1>

TP_MEM_A_A<15> MEM_A_A<14>

PP1V8_S3

MEM_A_DQ<19>

MEM_A_DQ<22>

MEM_A_DQS_N<6>

MEM_A_DM<7>

87 77 75 74 65 59 58 57 52 51 50 48 47 46 42 32 30 29 28

27 26

87

25

87 87

62

24

62 62

57

23

82

57

82

57

50

21

48

50

48

50

38

62

19

34

38

34

38

32

81

16

32

81

32

81

32

81

32

81

31

16

81

33

81

45

81

33

13

29

81

33

31

33

81

33

81

29

33

81

33

31

81

17

8

17

16

17

16

17

16

17

16

17

8

25

17

16

17

8

16

17

25

17

16

9

16

8

17

VSS2

DQS0*

DQ5

VSS0

DQ4

VSS5

DQ6

VSS29

DM0

VSS7

DM1

DQ7

VDD1

DQ30

DQ23

VSS22

NC/ODT1

RAS*

SA1

SA0

VSS58

DQ63

DQ62

VSS56

DQS7

DQS7*

VSS54

DQ60

VSS52

DQ54

VSS50

VSS48

CK1*

CK1

VSS46

DQ53

DQ52

VSS44

VSS42

DQS5

DQS5*

VSS39

DQ45

DQ44

VSS37

DQ39

DQ38

VSS35

DM4

VSS34

DQ37

DQ36

VSS32

NC3

VDD11

NC/A13

ODT0

VDD9

S0*

BA1

VDD7

A0

A2

A4

VDD5

A6

A7

A11

VDD3

NC/A14

NC/A15

NC/CKE1

VSS30

DQ31

DQS3

DQ29

DQ28

VSS24

DQ22

DM2

NC0

VSS19

DQ21

DQ20

VSS17

VSS15

DQ15

DQ14

VSS13

CK0*

CK0

VSS11

DQ13

DQ12

DQ47

DQ46

DQ61

DQ55

DM6

VDDSPD

SCL

SDA

VSS57

DQ59

DQ58

VSS55

DM7

VSS53

DQ56

VSS51

DQ50

VSS49

DQS6*

VSS47

NC_TEST

VSS45

DQ49

DQ48

VSS43

VSS41

DM5

VSS40

DQ41

VSS38

DQ35

VSS36

DQS4

DQS4*

VSS33

DQ33

DQ32

VSS31

VDD10

NC/S1*

CAS*

VDD8

WE*

BA0

A10/AP

VDD6

A1

A3

A5

VDD4

A8

A9

A12

VDD2

BA2

NC2

VDD0

CKE0

DQ27

DQ26

VSS27

NC1

DM3

DQ25

DQ24

VSS23

DQ19

DQ18

VSS21

DQS2

DQS2*

VSS18

DQ17

DQ16

VSS16

VSS14

DQ11

DQ10

VSS12

DQS1

DQS1*

DQ9

DQ8

VSS8

DQ3

DQ2

VSS6

DQS0

VREF

DQ34

DQ40

DQ42 DQ43

DQS6

DQ51

DQ57

KEY

VSS9

DQ1 VSS4

DQ0

VSS1

DQS3*

VSS26

VSS28

VSS25

VSS10

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Resistor prevents pwr-gnd short

ADDR=0xA4(WR)/0xA5(RD)

Page Notes

Power aliases required by this page:

Signal aliases required by this page:

"Expansion" (surface-mount) slot

516S0471

DDR2 Bypass Caps

(For return current)

NC

BOM options provided by this page: (NONE)

- =I2C_SODIMMB_SCL

- =I2C_SODIMMB_SDA

- =PP0V9_S3M_MEM_DIMMVREFB

- =PPSPD_S0M_MEM_B (2.5V - 3.3V)

- =PP1V8_S3M_MEM_B

C3213

1

2

6.3V

10%

1UF

CERM 402

C3212

1

2

6.3V

10%

1UF

CERM 402

C3209

1

2

10UF

X5R 603

20%

6.3V

C3211

1

2

20%

402

CERM

0.1uF

10V

C3208

1

2

10UF

X5R

6.3V

20% 603

C3210

1

2

6.3V

10%

1UF

CERM 402

C3219

1

2

20% 402

CERM

0.1uF

10V

C3218

1

2

20% 402

CERM

0.1uF

10V

C3217

1

2

10V

20% 402

CERM

0.1uF

C3216

1

2

6.3V

10%

1UF

CERM 402

C3221

1

2

20% 402

CERM

0.1uF

10V

C3220

1

2

20% 402

CERM

10V

0.1uF

C3215

1

2

6.3V

10%

1UF

CERM 402

C3214

1

2

6.3V

10%

1UF

CERM 402

R3200

1

2

10K

5% MF-LF

402

1/16W

C3200

1

2

10V

20%

402

CERM

0.1uF

C3201

1

2

6.3V

CERM1

603

20%

2.2uF

J3200

102A

105A

90A89A

101A

100A

99A

98A97A

94A

92A

93A

91A

107A

106A

85A

113A

30A 32A

164A 166A

79A

10A

26A

52A

67A

130A

147A

170A

185A

5A

35A 37A

20A 22A

36A 38A

43A 45A

55A 57A

7A

44A 46A

56A 58A

61A 63A

73A 75A

62A 64A

17A

74A 76A

123A 125A

135A 137A

124A 126A

134A 136A

19A

141A 143A

151A 153A

140A 142A

152A 154A

157A 159A

4A

173A 175A

158A 160A

174A 176A

179A 181A

189A 191A

6A

180A 182A

192A 194A

14A 16A

23A 25A

13A

11A

31A

29A

51A

49A

70A

68A

131A

129A

148A

146A

169A

167A

188A

186A

201

202

203

204

116A

86A

84A

80A

119A

115A

50A

69A

83A

120A

163A

114A

108A 110A

198A 200A

197A

195A

81A

117A 118A

82A

87A 88A

95A 96A

103A 104A

111A 112A

199A

1A 2A

27A 28A

33A 34A

39A 40A

41A 42A

47A 48A

3A

53A 54A

59A 60A

65A 66A

71A 72A

77A

8A

78A

121A 122A

127A 128A

132A

133A

138A

139A

144A

145A

149A 150A

155A 156A

161A 162A

165A

168A

171A

9A

172A

177A 178A

183A 184A

187A

190A

193A

196A

12A

15A

18A

21A

24A

109A

F-RT-SM-M9

CRITICAL

DDR2-SODIMM-DUAL

DDR2 SO-DIMM Connector B

SYNC_DATE=08/24/2006

SYNC_MASTER=(M59_SYNC)

14.0.0

051-7225

32 88

PP1V8_S3

PP0V9_S3_MEM_VREF

MEM_B_DQ<23>

PP1V8_S3

MEM_B_DQ<8>

MEM_B_DQ<3>

MEM_B_DQ<14>

MEM_B_DQ<11>

MEM_B_DQS_N<3>

MEM_B_DQ<22>

MEM_ODT<2>

MEM_B_RAS_L

MEM_B_A<0>

MEM_B_A<11>

MEM_B_DQ<30>

MEM_B_DQ<28>

MEM_B_DQ<26>

MEM_B_DQ<16>

MEM_B_DM<2>

MEM_B_DQ<18>

MEM_B_DQ<0>

MEM_B_BS<1>

MEM_CKE<4>

MEM_B_DQ<15>

MEM_B_DQ<10> MEM_B_DQ<13>

MEM_B_DQ<7> MEM_B_DQ<2>

MEM_B_DQS_N<0> MEM_B_DQS_P<0>

MEM_B_DQ<1>

MEM_B_DQ<21> MEM_B_DQ<19>

MEM_B_DQS_N<2> MEM_B_DQS_P<2>

MEM_B_DQ<20>

MEM_B_DQ<24>

MEM_B_DM<3>

MEM_B_DQ<27> MEM_B_DQ<25>

MEM_CKE<3>

MEM_B_BS<2>

MEM_B_A<12> MEM_B_A<9> MEM_B_A<8>

MEM_B_A<5> MEM_B_A<3> MEM_B_A<1>

MEM_B_BS<0> MEM_B_WE_L

MEM_B_DQ<4>

MEM_B_DQS_P<4>

MEM_B_DQ<35>

MEM_B_DQ<57> MEM_B_DQ<60>

MEM_B_DM<7>

MEM_B_DQ<61> MEM_B_DQ<62>

MEM_B_DQ<48> MEM_B_DQ<51>

MEM_B_DQS_N<6> MEM_B_DQS_P<6>

MEM_B_DQ<50> MEM_B_DQ<55>

MEM_B_DQ<40> MEM_B_DQ<47>

MEM_B_DM<5>

MEM_B_DQ<42> MEM_B_DQ<45>

SMBUS_SB_SDA SMBUS_SB_SCL

MEM_B_DQ<9>

MEM_B_DM<1>

MEM_B_DM<0>

MEM_CLK_P<4> MEM_CLK_N<4>

MEM_B_DQ<5>

MEM_B_DQ<17>

TP_MEM_B_A<15> MEM_B_A<14>

MEM_B_A<6>

MEM_B_A<2>

MEM_CS_L<2>

PP1V8_S3

MEM_B_A<13>

MEM_B_DQ<32> MEM_B_DQ<37>

MEM_B_DM<4>

MEM_B_DQ<38> MEM_B_DQ<39>

MEM_B_DQ<56> MEM_B_DQ<59>

MEM_B_DQS_N<7> MEM_B_DQS_P<7>

MEM_B_DQ<63>

MEM_B_DQ<54> MEM_B_DQ<53>

MEM_B_DQS_N<5> MEM_B_DQS_P<5>

MEM_B_DQ<41>

PM_EXTTS_L<1>

MEM_B_DQ<58>

MEM_B_DQS_P<3>

MEM_B_DQ<31>

MEM_B_DQ<29>

MEM_B_DQS_N<1>

MEM_B_DQ<6>

MEM_B_DQ<12>

MEM_B_DQS_P<1>

MEM_B_A<4>

MEM_B_A<7>

PP3V3_S0

MEM_B_DQ<43>

PP3V3_S0

SODIMM_B_SA1

MEM_B_DQ<46>

MEM_B_DQ<52>

MEM_CLK_N<3>

MEM_CLK_P<3>

MEM_B_DQ<36>

MEM_B_DQ<34>

MEM_ODT<3>

MEM_CS_L<3>

MEM_B_A<10>

MEM_B_DQ<44>

MEM_B_DQ<49>

MEM_B_DM<6>

MEM_B_DQS_N<4>

MEM_B_DQ<33>

MEM_B_CAS_L

87

77

75

74

65

59

58

57

52

51

50

48

47

46

42

32

31

30

29

28

27

26

87

87 87

25

62

62 62

24

57

82

57

23

50

48

50

21

38

62

38

34

38

19

32

31

32

81

81 81

81

31

81

32

81

16

81

31

16

81

31

81

33

81

33

81

33

81

29

81

33

31

33

81

45

81

81 81

33

13

81

13

81

33

81

33

8

17

8

17

16

17

16

17

16

17

25

17

16

17

9

16

17

16

8

17

16

17

17 17

17

8

17

8

17

16

17

16

17

IN

IN IN

IN

IN IN

IN

IN IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

One cap for each side of every RPAK, one cap for every two discrete resistors

Ensure CS_L and ODT resistors are close to SO-DIMM connector

C3352

1

2

402

0.1uF

10V

20% CERM

C3356

1

2

402

0.1uF

10V

20% CERM

C3354

1

2

402

0.1uF

10V

20% CERM

C3350

1

2

402

0.1uF

10V

20% CERM

C3360

1

2

402

0.1uF

10V

20% CERM

C3364

1

2

402

0.1uF

10V

20% CERM

C3368

1

2

402

0.1uF

10V

20% CERM

C3366

1

2

402

0.1uF

10V

20% CERM

C3362

1

2

402

0.1uF

CERM

10V

20%

C3358

1

2

402

0.1uF

10V

20% CERM

17 32 81

16 32 81

RP3358

2 7

56

5%

1/16W SM-LF

RP3300

3 6

56

5%

1/16W SM-LF

17 31 81

17 32 81

17 31 81

16 32 81

16 31 81

16 32 81

16 31 81

17 32 81

17 31 81

16 31 81

17 31 81

17 32 81

16 32 81

17 32 81

17 31 81

17 32 81

16 32 81

17 32 81

R3370

1 2

402

MF-LF1/16W

5%

56

16 31 81

RP3346

4 5

56

5%

1/16W SM-LF

RP3330

1 8

SM-LF1/16W

5%

56

RP3342

2 7

56

5%

1/16W SM-LF

RP3330

3 6

56

5%

1/16W SM-LF

RP3330

4 5

SM-LF

56

5%

1/16W

RP3330

2 7

56

5%

1/16W SM-LF

RP3342

4 5

SM-LF

56

5%

1/16W

RP3342

3 6

SM-LF1/16W

5%

56

RP3342

1 8

SM-LF

56

5%

1/16W

RP3358

4 5

56

5%

1/16W SM-LF

RP3346

3 6

1/16W

5%

56

SM-LF

RP3358

3 6

SM-LF1/16W

5%

56

RP3346

1 8

1/16W

5%

56

SM-LF

RP3346

2 7

56

5%

1/16W SM-LF

RP3358

1 8

56

5%

1/16W SM-LF

RP3366

4 5

56

5%

1/16W SM-LF

RP3366

1 8

SM-LF

56

5%

1/16W

RP3366

2 7

SM-LF1/16W

5%

56

RP3350

1 8

SM-LF1/16W

5%

56

RP3334

4 5

56

5%

1/16W SM-LF

RP3338

2 7

SM-LF1/16W

5%

56

RP3354

3 6

56

5%

1/16W SM-LF

RP3354

4 5

SM-LF1/16W

5%

56

RP3310

1 8

1/16W

5%

56

SM-LF

RP3310

4 5

SM-LF1/16W

5%

56

RP3310

2 7

1/16W

5%

56

SM-LF

RP3362

3 6

56

5%

1/16W SM-LF

RP3350

4 5

1/16W

5%

56

SM-LF

RP3350

2 7

SM-LF1/16W

5%

56

RP3354

2 7

SM-LF

56

5%

1/16W

RP3350

3 6

SM-LF1/16W

5%

56

RP3354

1 8

SM-LF

56

5%

1/16W

RP3338

4 5

SM-LF1/16W

5%

56

RP3338

3 6

1/16W

5%

56

SM-LF

RP3338

1 8

SM-LF1/16W

5%

56

RP3334

2 7

SM-LF

56

5%

1/16W

RP3334

1 8

SM-LF1/16W

5%

56

RP3334

3 6

1/16W

5%

56

SM-LF

RP3300

4 5

56

5%

1/16W SM-LF

RP3305

2 7

SM-LF

56

5%

1/16W

RP3366

3 6

56

5%

1/16W SM-LF

RP3300

2 7

SM-LF

56

5%

1/16W

RP3310

3 6

SM-LF1/16W

5%

56

RP3362

2 7

SM-LF

56

5%

1/16W

RP3305

4 5

SM-LF1/16W

5%

56

RP3305

1 8

SM-LF

56

5%

1/16W

RP3305

3 6

SM-LF1/16W

5%

56

RP3300

1 8

SM-LF

56

5%

1/16W

RP3362

1 8

56

5%

1/16W SM-LF

RP3362

4 5

1/16W

5%

56

SM-LF

R3371

1 2

402

56

5%

1/16W MF-LF

16 32 81

C3370

1

2

402

0.1uF

CERM

20% 10V

17 31 81

16 31 81

17 31 81

16 32 81

C3348

1

2

402

0.1uF

10V

20% CERM

C3346

1

2

402

0.1uF

10V

20% CERM

C3336

1

2

402

0.1uF

10V

20% CERM

C3334

1

2

402

0.1uF

10V

20% CERM

C3332

1

2

402

0.1uF

10V

20% CERM

C3330

1

2

402

0.1uF

10V

20% CERM

C3312

1

2

0.1uF

10V

20% CERM

402

C3310

1

2

402

0.1uF

CERM

20% 10V

C3307

1

2

402

0.1uF

10V

20% CERM

C3305

1

2

402

0.1uF

10V

20% CERM

C3302

1

2

402

0.1uF

10V

20% CERM

C3300

1

2

402

0.1uF

10V

20% CERM

C3344

1

2

402

0.1uF

10V

20% CERM

C3342

1

2

402

0.1uF

10V

20% CERM

C3340

1

2

402

0.1uF

10V

20% CERM

C3338

1

2

402

0.1uF

10V

20% CERM

33 88

14.0.0

051-7225

Memory Active Termination

SYNC_MASTER=(T9_NOME)

SYNC_DATE=11/14/2006

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<11>

MEM_A_BS<2>

MEM_B_A<4>

MEM_B_A<12>

MEM_B_A<1> MEM_B_A<2>

MEM_CKE<3>

MEM_ODT<1>

MEM_A_A<14>

MEM_A_A<8>

MEM_B_A<5>

MEM_A_A<1> MEM_A_A<2>

MEM_A_A<5>

MEM_A_A<12>

MEM_A_BS<0>

MEM_CS_L<0>

MEM_CS_L<3>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_A<13>

MEM_CKE<4>

MEM_B_A<7>

MEM_B_RAS_L

MEM_A_CAS_L

MEM_CS_L<1>

MEM_B_BS<0>

MEM_A_BS<1>

MEM_B_A<11>

MEM_B_BS<1>

MEM_B_A<0>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6>

MEM_CKE<0> MEM_CKE<1>

MEM_ODT<0>

MEM_A_A<0>

MEM_A_A<4>

MEM_A_A<9>

MEM_B_A<14>

MEM_B_BS<2>

MEM_CS_L<2>

MEM_ODT<2>

MEM_B_A<13>

MEM_B_CAS_L MEM_B_WE_L

MEM_ODT<3>

MEM_B_A<3>

MEM_A_A<3>

MEM_B_A<10>

PP0V9_S0

MEM_A_A<10>

62

8

IN

IN IN

IN

BI

BI IN IN

OUT OUT IN

OUT OUT OUT

IN

IN IN

IN

OUT OUT

OUT IN

IN

OUT

BI IN

BI BI

IN BI

IN IN

OUT OUT

IN IN

IN

OUT IN

IN OUT

BI BI

IN

OUT OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Pull-up on LIO, FETs to GND on MLB

Left I/O Board Connector

Place caps close to SB

(Output to LIO)

(Input from LIO)

516S0348

NC

24 34 83

77

J3400

1

10

1112 1314 1516 1718 19

2

20

2122 2324 2526 2728 29

3

30

3132 3334 3536 3738 39

4

40

4142 4344 4546 4748 49

5

50

5152 5354 5556 5758 59

6

60

6162 6364 6566 6768 69

7

70

7172 7374 7576 7778 79

8

80

81

8283

84

9

M-ST-SM

CRITICAL

QT500806-L121-9F

45 46

36

45 46

36 40 45 46

45 46

29 30

28

24 46

13 24

49

45

45 46

65

45 46

49

7

25 43 45 57 65

45

25 35

45 48 51 84

24 82

25 29 31 32 48 82

29 30 84

24 83

29 30 84

23 82

24 82

C3411

1 2

0.1uF

402

X5R

16V

10%

C3410

1 2

16V 402

X5R

10%

0.1uF

C3421

1 2

402

X5R

16V

10%

0.1uF

C3420

1 2

16V

10%

0.1uF

X5R 402

24 83

24 34 83

34 88

14.0.0

051-7225

Left I/O Board Connector

SYNC_MASTER=(M59_SYNC)

SYNC_DATE=08/24/2006

HDA_RST_L

HDA_SYNC

HDA_BIT_CLK

HDA_SDIN0

PCIE_WAKE_L SMBUS_SMC_B_S0_SDA SMBUS_SMC_B_S0_SCL

USB_EXCARD_N USB_EXCARD_P

USB_EXTB_P

SMBUS_SB_SCL SMBUS_SB_SDA

PCIE_CLK100M_MINI_N PCIE_CLK100M_MINI_P

PCIE_MINI_D2R_N PCIE_MINI_D2R_P

PCIE_MINI_R2D_P

PCIE_CLK100M_EXCARD_N PCIE_CLK100M_EXCARD_P

PCIE_EXCARD_D2R_P

MAKE_BASE=TRUE

PCIE_EXCARD_R2D_N PCIE_EXCARD_R2D_P

SYS_ONEWIRE SMC_ADAPTER_EN SMC_BATT_CHG_EN

LCDBKLT_PWM_UNBUF LCDBKLT_PWREN EXCARD_CLKREQ_L MINI_CLKREQ_L LIO_PLT_RST_L

PP3V42_G3H PPDCIN_G3H

EXCARD_OC_L USB_EXTB_OC_L LIO_BATT_ISENSE

SMC_SYS_ISET

SMC_BATT_ISET SMC_BATT_TRICKLE_EN_L SMC_EXCARD_CP SMC_BC_ACOK PM_SLP_S3_LS5V

LIO_DCIN_ISENSE

PCIE_MINI_R2D_C_N

PCIE_MINI_R2D_C_P

PCIE_EXCARD_D2R_P

PCIE_EXCARD_D2R_N

MAKE_BASE=TRUE

PCIE_EXCARD_R2D_C_N

PCIE_EXCARD_R2D_C_P

MAKE_BASE=TRUE

PCIE_EXCARD_R2D_C_N

PCIE_EXCARD_R2D_C_P

USB_MINI_P

SMC_EXCARD_PWR_EN

PM_S4_STATE_L

HDA_SDOUT

PP1V5_S0

USB_EXTB_N

PCIE_MINI_R2D_N

PCIE_EXCARD_D2R_N

MAKE_BASE=TRUE

SMC_ENRGYSTR_LDO_EN

USB_MINI_N

PM_WLAN_EN_L

78

65 48

87

47

63

46

27

45

26

43

22

83

28

83

12

83

34

8

65

34

11

34

87

24

87

7

8

24

8

87

24

BI BI

OUT

IN

OUT

IN IN

THRML_PAD

VDDO_TTL1

VMAIN_AVLBL

SWITCH_VAUX

VAUX_AVLBL

LED_DUPLEX*

RSVD_43

RSVD_29

RSVD_25

RSVD_24

NC_64

CTRL12

NC_57

NC_52

NC_51

NC_32

RSET

SWITCH_VCC

AVDDH

AVDD0

AVDD3

VDDO_TTL3

LOM_DISABLE*

VDD0

VDD1

VDD3

VDD4

TX_P

CTRL18

TESTMODE

VDD2

VDD5

VDD7

CLKREQ*

WAKE*

PERST*

MDIP0

MDIP1 MDIN1

MDIP2 MDIN2

MDIP3

XTALI

MDIN3

XTALO

REFCLKP REFCLKN

RX_N

RX_P

SPI_DO

SPI_CLK

SPI_CS

VPD_DATA

VPD_CLK

TX_N

MDIN0

AVDD1

LED_LINK1000*

VDD6

VDDO_TTL2

VDDO_TTL0

LED_ACT*

LED_LINK10/100*

AVDD2

SPI_DI

ANALOG

PCI EXPRESS

SPI

LED

TWSI

MEDIA

MAIN CLK

TEST/RSVD

IN

OUT OUT

E2

WC*

NC0

NC1

VCC

VSS

SCL

SDA

IN OUT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

No link: 60 mA 10 Mbps: 70 mA

- Alias =YUKON_EC_PP2V5_ENET to PP1V8R2V5_ENET_PHY_AVDD, add 1x 0.1uF and 1x 0.001uF caps

- Connect =ENET_CLKREQ_L to clock generator via 0-ohm resistor (BOMOPTION: YUKON_ULTRA)

- Use YUKON_EC and YUKON_ULTRA BOMOPTIONs to select stuffed part

- Use 0-ohm resistors or variable supply to provide 1.8V or 2.5V to =PP1V8R2V5_ENET_PHY

Yukon EC: Pin 42 should be NC (or TP) net.

Page Notes

Power aliases required by this page:

- =PP3V3_ENET_PHY

- =PP1V2_ENET_PHY

(EC / Ultra) (2.5V / 1.8V) (2.5V / GND)

NC

NC NC NC

NC NC NC NC

(IPD)

(IPU) (IPU) (IPU) (IPU)

(IPU)

EC:CTRL25

NC

NC NC

NC

EC:AVDD 2.5V

EC:NO CONNECT

100 Mbps: 70 mA

Yukon Ultra

10 Mbps: 179 mA

No link: 4 mA

1000 Mbps: 4 mA

NC

VPD ROM

Yukon EC

100 Mbps: 150 mA

Yukon EC No link: 171 mA

100 Mbps: 203 mA 1000 Mbps: 426 mA

Yukon Ultra

- =YUKON_EC_PP2V5_ENET

Must be high in S0 state (can use PP3V3_S0 as input)

1000 Mbps: 80 mA

100 Mbps: 4 mA

10 Mbps: 4 mA

Yukon Ultra (1.8V)

10 Mbps: 30 mA

No link: 0 mA

100 Mbps: 40 mA 1000 Mbps: 150 mA

Yukon EC (2.5V)

10 Mbps: 108 mA 100 Mbps: 126 mA 1000 Mbps: 218 mA

No link: 82 mA

Yukon EC: Alias to PP1V8R2V5_ENET_PHY_AVDD, add 1x 0.1uF & 1x 0.001uF caps Yukon Ultra: Alias to GND

(EC:2.5V)

YUKON_ULTRA - Selects Yukon Ultra RSET.

BOM options provided by this page:

- =ENET_CLKREQ_L (NC/TP for Yukon EC)

Signal aliases required by this page:

- =PP1V8R2V5_ENET_PHY

To support Yukon EC and Ultra on the same board:

YUKON_EC - Selects Yukon EC RSET value.

instructions for dual Yukon EC / Yukon Ultra schematic support.

NOTE: See bottom of page for

- =ENET_VMAIN_AVLBL (See note by pin)

and magnetics. Can also use BCP69T1 connected to CTRL18 pin 4 for internal VR.

(IPU)

1000 Mbps: 290 mA

10 Mbps: 130 mA

No link: 130 mA

R3740

1

2

SIGNAL_MODEL=EMPTY

402

1/16W

1% MF-LF

49.9

R3741

1

2

SIGNAL_MODEL=EMPTY

402

1%

MF-LF

49.9

1/16W

37 83

24 83

C3740

1

2

10% CERM

50V

0.001UF

402

C3742

1

2

10% CERM

50V

0.001UF

402

C3744

1

2

10% CERM

50V

0.001UF

402

C3746

1

2

10% CERM

50V

0.001UF

402

R3742

1

2

1/16W

SIGNAL_MODEL=EMPTY

402

1% MF-LF

49.9

R3743

1

2

SIGNAL_MODEL=EMPTY

402

1%

MF-LF

49.9

1/16W

R3747

1

2

SIGNAL_MODEL=EMPTY

402

1%

MF-LF

49.9

1/16W

R3746

1

2

SIGNAL_MODEL=EMPTY

402

1% MF-LF

49.9

1/16W

R3745

1

2

SIGNAL_MODEL=EMPTY

402

1%

MF-LF

49.9

1/16W

R3744

1

2

SIGNAL_MODEL=EMPTY

402

1/16W

1% MF-LF

49.9

C3735

1 2

0.1uF

10% X5R 40216V

C3736

1 2

0.1uF

10% 16V X5R 402

C3730

1 2

PLACEMENT_NOTE=Place C3730 close to southbridge.

16V10%

0.1uF

X5R 402

C3731

1 2

PLACEMENT_NOTE=Place C3731 close to southbridge.

402X5R16V10%

0.1uF

24 83

28

25 34

29 30

29 30 84

U3700

192223

28

8

42

3

4

59

63

62

60

10

18

21

27

31

17

20

26

30

3251525764

5

56

55

16

24 25 29 43

53

54

37 36

35

34

9

11

46

65

50

49

12

271333394448

58

14045

61

47

38 41

6

15 14

88E8058

CRITICAL

OMIT

QFN

7

25 36 40 45 49 57 62 65

R3765

1

2

YUKON_ULTRA

4.99K

402

MF-LF

1/16W

1%

C3720

1

2

CERM

6.3V

20%

4.7UF

603

C3724

1

2

50V CERM

0.001UF

402

10%

C3723

1

2

0.1UF

402

16V

10% X5R

C3722

1

2

402

0.1UF

16V

10% X5R

C3721

1

2

X5R

10% 16V

402

0.1UF

C3714

1

2

402

10%

0.001UF

50V CERM

C3713

1

2

0.1UF

402

16V

10% X5R

C3712

1

2

0.1UF

402

16V

10% X5R

C3711

1

2

X5R

10% 16V

402

0.1UF

C3710

1

2

6.3V

20%

603

4.7UF

CERM

C3715

1

2

CERM

50V

0.001UF

402

10%

C3705

1

2

0.1UF

X5R

10% 16V

402

C3704

1

2

0.1UF

X5R

10% 16V

402

C3703

1

2

X5R

10% 16V

402

0.1UF

C3702

1

2

X5R

10% 16V

402

0.1UF

C3701

1

2

0.1UF

402

16V

10% X5R

C3700

1

2

603

4.7UF

20%

6.3V CERM

C3708

1

2

10%

402

0.001UF

50V CERM

C3707

1

2

10%

402

0.001UF

50V CERM

C3706

1

2

10%

402

0.001UF

50V CERM

U3780

3

1

2

6

5

8

4

7

SO8

M24C08

OMIT

CRITICAL

C3780

1

2

X5R

10% 16V

402

0.1UF

R3780

1

2

4.7K

5%

402

MF-LF

1/16W

R3781

1

2

4.7K

5%

402

MF-LF

1/16W

R3760

1

2

5%

4.7K

402

MF-LF

1/16W

L3720

1 2

FERR-120-OHM-1.5A

0402

36

051-7225

14.0.0

88

Ethernet (Yukon)

35

SYNC_MASTER=T9_NOME

SYNC_DATE=03/16/2007

YUKON_EC1 U3700338S0270

IC,88E8053,GIGABIT ENET XCVR,64P QFN

CRITICAL

1338S0386 U3700 CRITICAL

YUKON_ULTRA

IC,88E8058,GIGABIT ENET XCVR,64P QFN

CRITICAL1 U3780

YUKON_ULTRA

341S2060

IC,FLASH,88E8058 ETHERNET VPD,IIC,SO8

CRITICAL1 YUKON_EC341S1797

IC,EEPROM,SERIAL IIC,8KBIT,SO8

U3780

114S0285 1 YUKON_EC

RES,4.87K,1%,1/16W,0402,LF

R3760

GND

PP1V9_ENET

PP1V8R2V5_ENET_PHY_AVDD

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

PP1V25_ENET

PCIE_ENET_R2D_P

YUKON_VPD_DATA

PCIE_ENET_R2D_C_N

PCIE_ENET_R2D_C_P

PCIE_ENET_D2R_N

PCIE_ENET_D2R_P

PCIE_ENET_R2D_N

PCIE_ENET_D2R_C_N

TP_YUKON_CTRL18 TP_YUKON_CTRL12

PM_SLP_S3_L

YUKON_RSET

ENET_LOM_DIS_L

ENET_MDI0 ENET_MDI1 ENET_MDI2 ENET_MDI3

YUKON_VPD_CLK

PCIE_ENET_D2R_C_P

ENET_MDI_P<2> ENET_MDI_N<2>

ENET_MDI_P<1>

PCIE_CLK100M_ENET_P

ENET_MDI_N<1>

ENET_MDI_N<0>

ENET_CLKREQ_L

PCIE_CLK100M_ENET_N

PCIE_WAKE_L

ENET_MDI_P<0>

ENET_RESET_L

PP3V3_ENET

ENET_CLK25M_XTALI ENET_CLK25M_XTALO

ENET_MDI_N<3>

ENET_MDI_P<3>

61

36

50

36

8

37

8

83

8

OUT

THRM_PAD

NC

IN1

EN

IN2

OUT1 OUT2

NR/FB

GND

IN

OUT

G

D

S

IN

G

D

S

G

D

S

IN

OUT

G

DS

G

D

S

G

D

S

G

D

S

IN

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

Yukon Crystal

(AC_EN_L)

ENET Enable Generation

1.9V for Yukon Ultra, 2.5V for Yukon EC

NC

Vout = 1.2246V * (1 + Ra / Rb)

(U3850 limit)

500 mA max output

NC

3.3V ENET FET

(PM_SLP_S3_L)

Ultra: Vout = 1.912V

NOTE: S3 term is guaranteed by FET & pull-up source, MUST BE S3 RAIL.

"WLAN" = "S0" || ("S3" && "AC" && "WOW_EN")

WLAN Enable Generation

Yukon AVDDL LDO

Yukon Ultra requires 1.9V on its magnetics to pass compliance tests

EC: Vout = 2.510V

NOTE: S3 term is guaranteed by source of R3800 & Q3810, MUST BE S3 RAIL.

"ENET" = "S0" || ("S3" && "AC" && "WOL_EN")

7

61 65

U3850

8

6

1 2

7

5

3 4

9

CRITICAL

SON

LREG_TPS79501DRB

C3850

1

2

10%

402

CERM

6.3V

1UF

C3851

1

2

1UF

6.3V CERM 402

10%

R3855

1

2

16.9K

1% 1/16W MF-LF 402

YUKON_ULTRA

R3856

1

2

MF-LF

30.1K

1% 1/16W

402

C3855

1

2

5%

50V

CERM

402

33PF

Y3860

24

13

SM-3.2X2.5MM

25.0000M

CRITICAL

C3861

1

2

CERM 402

50V

5%

18PF

C3860

1

2

CERM

5%

50V 402

18PF

35

Q3800

6

2

1

2N7002DW-X-F

SOT-363

34 40 45 46

C3800

1

2

402

10%

CERM

0.22UF

10V

Q3805

3

5

4

SOT-363

2N7002DW-X-F

Q3805

6

2

1

2N7002DW-X-F

SOT-363

13 24

34

R3810

1 2

1/16W

5%

MF-LF

100K

402

R3811

1

2

10K

MF-LF

5%

1/16W

402

C3810

12

10% 16V

402

0.01UF

CERM

Q3810

3

1

2

SOT-23

NTR4101P

C3811

1

2

10% 16V

402

X5R

0.033UF

R3800

1

2

5%

1/16W

10K

402

MF-LF

Q3801

3

5

4

SOT-363

2N7002DW-X-F

Q3800

3

5

4

SOT-363

2N7002DW-X-F

Q3801

6

2

1

2N7002DW-X-F

SOT-363

7

25 35 40 45 49 57 62 65

25

SYNC_DATE=03/16/2007

SYNC_MASTER=T9_NOME

36 88

14.0.0

051-7225

Yukon Power Control

1 R3855 YUKON_EC

RES,31.6K,1%,1/16W,402,LF

114S0363

PM_WLAN_EN_L

PP3V3_S3

PP3V3_ENET

P3V3ENET_SS

PP1V9_ENET

ENETAVDDL_FB

WOW_EN

SMC_ADAPTER_EN

PM_ENET_EN

ENET_CLK25M_XTALO

ENET_CLK25M_XTALI

PP3V3_ENET

AC_EN_L

PM_SLP_S3_L

WOL_EN

PM_ENET_EN_L

78 57 54 53 51 50 48 38 36

36

8

35

35 35

7 8

8 8

SYM_VER2

NC2

NC3

NC4

LINE

SIDE

CHIP

SIDE

NC1

SYM_VER2

NC2

NC3

NC4

LINE

SIDE

CHIP

SIDE

NC1

BI

OUT

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

sides of the board

Transformers should be mirrored on opposite

Page Notes

Power aliases required by this page:

Signal aliases required by this page:

BOM options provided by this page:

Short shielded RJ-45

514-0277

(NONE)

Place close to connector

New Series Rs required for European Telecom Compliance

- =GND_CHASSIS_ENET

Place one cap at each pin of transformer

RX3910

1 2

402

NONE

SHORT

NONE

OMIT

C3903

1

2

402

CERM

1uF

6.3V

10%

C3902

1

2

6.3V 402

CERM

10%

1uF

R3903

1

2

75

5% 1/16W

402

MF-LF

R3902

1

2

1/16W

5%

402

MF-LF

75

R3901

1

2

75

MF-LF

402

5%

1/16W

R3900

1

2

75

402

5%

MF-LF

1/16W

C3901

1

2

CERM

10%

1uF

402

6.3V

C3900

1

2

402

10%

6.3V CERM

1uF

T3900

1

10

11

14

15

16

2

3

6

7

8 9

4 5 12

13

OMIT

XFR-SM

CRITICAL

1000BT-824-00275

T3901

1

10

11

14

15

16

2

3

6

7

8 9

4 5 12

13

1000BT-824-00275

XFR-SM

CRITICAL

OMIT

35 83

9

41

J3900

9

10

11

12

1 2 3 4 5 6 7 8

CRITICAL

JM36113-P2054-7F

F-RT-TH-RJ45

RX3911

1 2

402

NONE

SHORT

NONE

OMIT

RX3991

1 2

402

NONE

SHORT

NONE

OMIT

RX3990

1 2

402

NONE

SHORT

NONE

OMIT

C3904

1 2

1206

1000PF

CERM

2KV

10%

CRITICAL

SYNC_DATE=03/19/2007

SYNC_MASTER=M76_MLB

14.0.0

37

051-7225

88

Ethernet Connector

CRITICAL

T3900,T3901

XFMR,ISO,HALF-PORT,1000T,16P,SMD,2MM

2

157S0030

PP1V8R2V5_ENET_PHY_AVDD

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

ENET_CTAP_COMMON

ENETCONN_N<3>

ENETCONN_P<2>

ENETCONN_N<2>

ENETCONN_P<3>

ENETCONN_N<1>

ENETCONN_P<0>

ENETCONN_N<0>

ENETCONN_P<1>

ENET_CTAP2

ENET_CTAP1

ENET_CTAP3

ENET_CTAP0

GND_CHASSIS_ENET

ENET_MDI_P<0>

ENET_MDI_N<0>

ENET_MDI_P<1>

ENET_MDI_N<1>

ENET_MDI_P<2>

ENET_MDI_N<2>

ENET_MDI_P<3>

ENET_MDI_N<3>

35

87

BI

BI BI BI BI

BI

BI BI

BI BI BI

OUT OUT

IN

OUT

BI

OUT

IN IN

BI

OUT

SDA

SCL

PCI_AD19

PCI_AD18

PCI_AD17

PCI_AD16

PCI_AD15

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD11

PCI_AD10

PCI_AD31

PCI_AD30

PCI_AD28 PCI_AD29

PCI_AD27

PCI_AD25 PCI_AD26

PCI_AD24

PCI_AD23

PCI_AD21

PCI_AD20

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD6

PCI_AD5

PCI_AD4

PCI_AD3

PCI_AD2

PCI_PAR

PCI_CLK PCI_IDSEL

GND

PCI_AD1

PCI_AD0

VCC

MFUNC

G_RST_L

REG18_1

REG18_0

REG_EN_L

PHY_PINT

PHY_PCLK

PHY_LREQ

PHY_LPS

PHY_LINKON

PHY_LCLK

PHY_D7

PHY_D6

PHY_D5

PHY_D4

PHY_D3

PHY_D1-D1

PHY_D2

PHY_D0-D0

PHY_CTL1-CTL1

PHY_CTL0-CTL0

PCI_ACK64_L

PCI_TRDY_L

PCI_STOP_L

PCI_SERR_L

PCI_RST_L

PCI_REQ64_L

PCI_REQ_L

PCI_PME_L

PCI_PERR_L

PCI_IRDY_L

PCI_INTA_L

PCI_GNT_L

PCI_FRAME_L

PCI_DEVSEL_L

VCCP

PCI_AD22

PCI_C_BE2_L

PCI_C_BE0_L

PCI_C_BE3_L

PCI_C_BE1_L

G

D

S

IN

G

D

S

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

when there’s no power on VCCP

G_RST* is clamped to VCCP

aliased to the same rail)

It must not be taken high

(OK if VCCP and VCC are

G_RST* assertion min 2ms

MFUNC as a GPIO

Might use

(FW_G_RST_L)

24 83

25

24 83

30 84

7

24 47 83

28

C4008

1

2

1uF

10V X5R 402

10%

C4009

1

2

10V 402

X5R

1uF

10%

C4004

1

2

10V 402

X5R

1uF

10%

C4003

1

2

10V 402

X5R

10%

1uF

C4002

1

2

10V

1uF

10% X5R

402

C4001

1

2

10%

1uF

10V X5R 402

C4000

1

2

10% X5R

10V 402

1uF

R4002

1

2

402

MF-LF

1/16W

5%

4.7K

R4001

1

2

1/16W MF-LF

402

5%

4.7K

24 83

39

R4090

1

2

220

402

MF-LF

1/16W

5%

R4080

1

2

1K

402

MF-LF

1/16W

5%

R4091

1

2

220

5% 1/16W MF-LF 402

39 85

R4010

1

2

10K

5% 1/16W MF-LF

402

U4000

E4

C7

C8

F7F8F9

F10

G6G7G8

G9

G10

H6D6H7H8H9

H10

J8

J9

J10

K10

D7E6E7E8E9

E10

F6

A1

N12

L12 N11

N6 M6 M7 K9 K8 M5 K3 N1 L4 M2

M11

M1 L1 J4 H3 H4 J3 H2 G3 H1 F1

N10

F2 G4

M10 K12

M9 N9 L8 M8

N8 M3 K5 K2

D3

N2 L3 E3

L2

B3 K4

N3

L6 F4

J13

F3

D1 L7 L5 J5

F13 F12

E13 E12

C13 B9 B10 C11 B12 A11 B7 B4 A2 D4 B6 A3

G11 G12

C2

C3 C4

D5D8D9E5F5

H11J6J7

J11

E11

F11

TSB83AA22CZAJ

CRITICAL

(2 OF 2)

BGA

Q4070

3

5

4

SOT-363

2N7002DW-X-F

39

Q4070

6

2

1

2N7002DW-X-F

SOT-363

R4070

1

2

100K

402

MF-LF

1/16W

5%

R4071

1

2

10K

5% 1/16W MF-LF 402

45

28

R4000

1

2

402

MF-LF

1/16W

5%

22

C4010

1

2

16V

10%

402

X5R

0.1uF

C4011

1

2

402

X5R

16V

10%

0.1uF

24 83

SYNC_DATE=03/19/2007

SYNC_MASTER=M76_MLB

38 88

14.0.0

051-7225

FireWire Link (TSB83AA22)

PP3V3_S3 PP3V3_S3

INT_PIRQD_L

PCI_FW_GNT_L

PCI_FRAME_L

PCI_ACK64_L

PCI_TRDY_L

PLT_GATED_RST

SMC_RSTGATE_L

FW_G_RST_L

PP3V3_S3

FW_PLT_RST_L

PP1V8_S3

FW_DATA<4>

PCI_PAR

PCI_C_BE_L<1> PCI_C_BE_L<2>

PCI_AD<22>

PCI_C_BE_L<3>

PCI_C_BE_L<0>

PCI_PME_FW_L

PCI_FW_RST_L PCI_SERR_L PCI_STOP_L

TP_FW_CTL<0> TP_FW_CTL<1>

TP_FW_DATA<0>

FW_DATA<2>

TP_FW_DATA<1>

FW_DATA<3>

FW_DATA<5> FW_DATA<6> FW_DATA<7> CLKFW_PHY_LCLK FW_LINKON FW_LPS FW_LREQ

FW_PINT

PCI_AD<0> PCI_AD<1>

PCI_CLK33M_FW

PCI_AD<2> PCI_AD<3> PCI_AD<4> PCI_AD<5> PCI_AD<6> PCI_AD<7> PCI_AD<8> PCI_AD<9>

PCI_AD<20> PCI_AD<21>

PCI_AD<23> PCI_AD<24>

PCI_AD<26>

PCI_AD<25>

PCI_AD<27>

PCI_AD<29>

PCI_AD<28>

PCI_AD<30> PCI_AD<31>

PCI_AD<10> PCI_AD<11> PCI_AD<12> PCI_AD<13> PCI_AD<14> PCI_AD<15> PCI_AD<16> PCI_AD<17> PCI_AD<18>

FW_PCI_IDSEL

PCI_AD<19>

FW_MFUNC

FW_SDA

FW_SCL

PCI_FW_REQ_L

PCI_DEVSEL_L

PCI_PERR_L

PCI_IRDY_L

PCI_REQ64_L

FW_LLC_PP1V8LDO_EN_L

CLKFW_LINK_PCLK

78

57

54

53

51

87

50

62

48

57

38

50

36

32

8

31

7

8

SE

SM

RESET

D7

D5 D6

D4

D3

D2

CPS

PD

BMODE

PC2

PC0 PC1

LREQ

LPS

DS1 LCLK

DS0

XI

R1

R0

TESTM TESTW

TPBIAS0 TPBIAS1

TPB1N

TPB1P

TPB0N

TPB0P

TPA1N

TPA1P

TPA0P TPA0N

PINT

PCLK

AVDD_3P3

DVDD_3P3

DVDD_CORE

PLLVDD_3P3

PLLVDD_CORE

PLLGND

LKON_DS2

CNA

BI BI

OUT

OUT OUT

OUT

TRI-ST/NC

VCC

GND

IN

OUT

BI BI BI BI BI BI

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

R4160 provides isolation between R4161 and unpowered LLC.

No need for DS2 pull-down on TSB83AA22A, as 3rd FireWire port is not pinned out.

Power Class:

Single-port / Desktop systems are Power Class 0 (’000’).

Strap via alias on port page.

Implement 1K pull-up or pull-down on port page.

Multi-port Portable systems are Power Class 4 (’100’).

DSx Straps:

Hi: Data-Strobe only (1394a). Lo: Beta Mode enable (1394b).

PHY power-up reset.

C4150 with internal pull-up provides

NC

(IPU)

NC

1MA (MAX) BUS HOLDERS

C4150

1

2

6.3V

20%

402

X5R

0.22uF

R4155

1

2

390K

5% 1/16W MF-LF

402

U4000

D10

D11G5H5

L9

M12

A5

D13

C9 C10 C12 B13 B11

A6

B8

D12

H12

J12K7K6C5C6

G13

L13

N13

K13

N4

M4

N5

H13

K11

M13

A10

A7

A8

A12 A13

L10

A4

B5

L11 N7

E2

E1

J1

J2

B1

C1

G1

G2

D2 K1

A9

TSB83AA22CZAJ

BGA

(1 OF 2)

CRITICAL

C4110

1

2

0.01uF

CERM 402

20% 16V

C4102

1

2

1uF

X5R 402

10% 10V

C4121

1

2

10V

10% 402

X5R

1uF

41 85

38 85

41

C4101

1

2

1uF

X5R 402

10% 10V

C4103

1

2

X5R 402

10% 10V

1uF

C4104

1

2

1uF

X5R 402

10% 10V

C4111

1

2

1uF

X5R 402

10% 10V

C4112

1

2

1uF

X5R 402

10V

10%

C4113

1

2

X5R 402

10% 10V

1uF

C4114

1

2

X5R 402

10% 10V

1uF

G4180

2

3 1

4

CRITICAL

98P3040MHZ

SM

38 85

38

R4145

12

1K

MF-LF

402

1/16W

5%

R4142

12

1K

1/16W MF-LF

5%

402

C4131

1

2

1uF

X5R 402

10% 10V

C4130

1

2

1uF

X5R 402

10% 10V

C4135

1

2

2.2uF

CERM1 603

10%

6.3V

8

39 40 41 64

R4156

1

2

10K

5% 1/16W MF-LF

402

R4186

1

2

4.7

5% 1/16W MF-LF 402

R4100

1 2

1

MF-LF

402

5%

1/16W

R4135

1 2

1

MF-LF

402

5%

1/16W

R4120

1 2

1/16W

5%

402

MF-LF

1

R4161

1

2

470

MF-LF 402

5% 1/16W

R4162

1

2

402

6.34K

MF-LF

1% 1/16W

R4160

1 2

1K

402

MF-LF

1/16W

5%

38

R4180

1 2

1/16W

5%

402

MF-LF

22

C4180

1

2

0.22uF

X5R 402

20%

6.3V

R4191

1

2

1K

MF-LF 402

5% 1/16W

R4140

1

2

1/16W

5%

402

MF-LF

1K

R4190

1

2

1K

MF-LF

402

5%

1/16W

SYNC_MASTER=M76_MLB

39 88

14.0.0

051-7225

SYNC_DATE=03/19/2007

FireWire PHY (TSB83AA22)

FWPHY_R0

VOLTAGE=1.86V

FW_0_TPBIAS

PP3V3_FW

VOLTAGE=1.86V

FW_1_TPBIAS

CLKFW_LINK_PCLK

FWPHY_TESTM

FW_PINT

FW_PORT0_TPA_P

FW_PORT1_TPA_N

FW_PORT1_TPB_N

FW_PORT1_TPB_P

FWPHY_R1

PPVP_FW

FWPHY_DS0 FWPHY_DS1

FWPHY_TESTW

FW_LINKON

FWPHY_CPS

FWPHY_BMODE

FW_PORT0_TPA_N

CLKFW_PHY_LCLK

FW_DATA<2>

FW_DATA<7>

FW_DATA<6>

FW_DATA<5>

FW_DATA<4>

FW_DATA<3>

PP3V3_FW

FW_LINKON_R

PP3V3_FW

FW_PORT0_TPB_N

FWPHY_CLK98P304

PP1V95_FW

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.20 mm

PP1V8_FW_PHYOSC_R

FWPHY_CLK98P304M_R

FW_LPS

FWPHY_RESET_L

GND

FW_LREQ

FW_PORT0_TPB_P

FW_PORT1_TPA_P

VOLTAGE=1.95V

MIN_NECK_WIDTH=0.22 mm

MIN_LINE_WIDTH=0.38 mm

PP1V95_FW_PHY_PLLVDD

PP1V95_FW

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.22 mm

PP3V3_FW_PHY_AVDD

PP3V3_FW_PHY_PLLVDD

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm VOLTAGE=3.3V

64

41

40

64

40

64

39

40

39

8

V-

V+

S

G

D

S

G

D

GND

SENSEB

OUTA

FAULTB_L

FAULTA_L

ONB

INB

ONA

ONQ1

INA

GATE1A

GATE2A

SENSEA

GATE1B

GATE2B

OUTB

G

D

S

G

D

S

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

NC

Late-VG Event Detection

NC

0.020 ohm => 2.4A

Current Limits

is running or on AC.

Enables port power when machine

FWLATEVG_3V_REF Hysteresis:

2.95V when port power is on

2.81V on late Vg event and port power is off

0.033 ohm => 1.5A

0.030 ohm => 1.66A (Ideal)

0.025 ohm => 2A

as +1 if over the limit (at any point during the period)

MAX5944 current limiter trips if integrator (counter) reaches 16. A new sample (taken every 125 us) is weighted

and -1/128 if under the limit. As a result, the device tends to trip easily on devices that produce periodic current spikes. Current limit has been set higher to compensate.

Power aliases required by this page:

- =PPBUS_S5_FWPWRSW (system supply for bus power)

- =PP3V3_FW_LATEVG_ACTIVE

- =PPVP_FW_SUMNODE (power passthru summation node) Signal aliases required by this page:

(NONE) BOM options provided by this page:

- FW_PORT_FAULT_PU

Current Limit/Active Late-VG Protection

FireWire Port Power Switch

Page Notes

R4219

1

2

2.0M

MF-LF 402

5% 1/16W

C4219

1

2

0.33UF

CERM-X5R 603

10% 10V

C4210

1

2

10V

20%

402

CERM

0.1UF

R4210

1 2

1/16W

1%

402

MF-LF

200K

U4210

4

3

1

5

2

SM-LF

LMC7211

R4211

1

2

10K

MF-LF

402

5%

1/16W

C4211

1

2

50V

5%

CERM

100pF

402

R4212

1

2

10K

402

1% 1/16W MF-LF

R4213

1

2

1/16W

1%

402

MF-LF

80.6K

D4219

12

MBR0540XXG

SOD-123

Q4220

3

1

2

CRITICAL

SI2318DS

SOT23-3

Q4225

3

1

2

CRITICAL

SOT23-3

SI2318DS

C4225

1

2

CRITICAL

X7R 805

10%

1uF

35V

C4220

1

2

35V

10%

805

X7R

1uF

CRITICAL

R4220

1 2

0.020

0.25W

1% MF

805

CRITICAL

U4220

3

11

15

7

14

6

12

1

9

2

10

4

13

5

16

8

SOIC

MAX5944

CRITICAL

R4225

1 2

CRITICAL

0.25W 805

0.020

1% MF

R4229

1

2

FW_PORT_FAULT_PU

MF-LF

1/16W

5%

402

100K

Q4260

5

6

7

8

4

1

2

3

NDS9407

CRITICAL

SOI-LF

C4260

1

2

0.01uF

CERM

402

20% 16V

R4260

1

2

MF-LF

5% 1/16W

470K

402

Q4261

6

2

1

SOT-363

2N7002DW-X-F

R4261

1

2

5%

330K

MF-LF

1/16W 402

Q4261

3

5

4

SOT-363

2N7002DW-X-F

34 36 45 46

7

25 35 36 45 49 57 62 65

F4260

1 2

1.5A-24V

CRITICAL

MINISMDC

D4260

1

2

3

OMIT

CRITICAL

PDS340XF

PWRDI5

CRITICAL

D4260

DIODE,SCHOTTKY,40V,5A,POWERDI 5,LF

1

371S0466

SYNC_DATE=03/19/2007

SYNC_MASTER=M76_MLB

FireWire Port Power

8840

051-7225

14.0.0

PP3V3_FW

PPVP_FW

PPBUS_FW_FWPWRSW_D

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm VOLTAGE=12.6V

PPVP_FW_PORTA_ISENSE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm VOLTAGE=33V

PPBUS_FW_FWPWRSW_F

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPBUS_G3H

FWPWR_EN_L_DIV

PP2V4_FW_LATEVG

LATEVG_EVENT_L

P2V4_FWLATEVG_RC

FWPWR_EN_L

SMC_ADAPTER_EN

PM_SLP_S3_L

FW_PORT_FAULT_L FW_PORTPWR_DISABLE_L

PPVP_FW

FW_PORTA_PWRCTRL

PPVP_FW_PORTB_ISENSE

VOLTAGE=33V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPVP_FW_PORTA_UF

VOLTAGE=33V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

FWLATEGV_3V_REF

FW_PORTB_PWRCTRL

VOLTAGE=33V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPVP_FW_PORTB_UF

74 63

62 61 60 59 58 57

64

56

64

41

40

49

40

39

64

8

39

41

8

7

41

8

TPO#

TPI

TPO

TPI#

VGND

VP

SYM_VER-2

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

"Snapback" & "Late VG" Protection

FireWire TPA/TPB pairs to their

(NONE)

- =GND_CHASSIS_FW_PORT0L

Power aliases required by this page:

514S0133

AREF needs to be isolated from all

When a bilingual device is connected to a

ground for speed signaling and connection

Cable Power

(PPVP_FW_PORT1)

Note: Trace PPVP_FW_PORT1 must handle up to 5A

(GND_FW_PORT1_VG)

PORT 1

OUTPUT

INPUT

(PPFW_PORT0_VP)

(GND_FW_PORT0_VG)

514-0255

PORT 0

(TPA-)

(TPA+)

(TPB+)

Note: Trace PPVP_FW_PORT0 must handle up to 5A

1394A

"Snapback" & "Late VG" Protection

beta-only device, there is no DC path

local grounds per 1394b spec

detection currents per 1394b V1.33

BREF should be hard-connected to logic

(FW_PORT1_BREF)

between them (to avoid ground offset issue)

BILINGUAL

NC

NC VG

VP

TPB+

TPA+

TPA<R>

TPA-

TPB<R>

TPB-

Cable Power

(TPB-)

the necessary aliases to map the

NOTE: This page is expected to contain

Signal aliases required by this page:

FireWire PHY Config Straps

provide the appropriate constraints

constrained on this page. It is

NOTE: FireWire TPA/TPB pairs are NOT

BOM options provided by this page:

properly terminate unused signals.

- =GND_CHASSIS_FW_PORT1

- =GND_CHASSIS_FW_PORT0U

- =PP3V3_FW_LATEVG

- =PPVP_FW_PORT1

Page Notes

Late-VG Protection Power

PP2V4_FWLATEVG needs to be biased

- Port "1" Bilingual (1394B)

Configures PHY for:

- 2-port Portable Power Class (4)

- Port "0" Data-Strobe only (1394A)

Termination

1394b implementation based on Apple FireWire Design Guide (FWDG 0.6, 5/14/03)

to apply to entire TPA/TPB XNets.

assumed that FireWire PHY page will

appropriate connectors and/or to

- =PPVP_FW_PORT0

- =GND_CHASSIS_FW_EMI_R

(NONE)

R4390 should be 390 Ohms max for a 3.3V rail

to at least 2.1V for FW signal integrity and should be biased to 2.4V for margin

(Common to all ports)

for snap-back diodes

ESD and late-VG rail

Place close to FireWire PHY

TI PHYs require 1uF even though FW spec calls out 0.33uF

C4350

1

2

1uF

CERM 402

10%

6.3V

R4351

1

2

1/16W

1%

402

MF-LF

56.2

R4350

1

2

1/16W

1%

402

MF-LF

56.2

R4353

1

2

1/16W

1%

402

MF-LF

56.2

SIGNAL_MODEL=EMPTY

R4352

1

2

1/16W

1%

402

MF-LF

56.2

SIGNAL_MODEL=EMPTY

R4354

1

2

4.99K

MF-LF

402

1%

1/16W

C4354

1

2

220pF

CERM 402

5% 25V

L4300

1 2

CRITICAL

FERR-250-OHM

SM

C4304

1

2

CERM 402

20% 50V

0.001uF

DP4300

4

5

3

BAV99DW-X-F

SOT-363

J4300

7 8 9 10

4

3

6

5

2

1

CRITICAL

1394A

F-RT-TH-LF

C4305

1

2

50V CERM 603

20%

0.01uF

DP4301

4

5

3

BAV99DW-X-F

SOT-363

C4301

1

2

402

10%

0.01uF

50V X7R

DP4300

1

2

6

BAV99DW-X-F

SOT-363

C4300

1

2

0.01uF

50V

10%

402

X7R

C4303

1

2

50V

10%

402

X7R

0.01uF

DP4301

1

2

6

BAV99DW-X-F

SOT-363

C4302

1

2

0.01uF

X7R 402

10% 50V

R4363

1

2

1/16W

1%

402

MF-LF

56.2

R4364

1

2

4.99K

MF-LF

402

1%

1/16W

R4362

1

2

1/16W

1%

402

MF-LF

56.2

C4364

1

2

220pF

CERM 402

5% 25V

R4361

1

2

1/16W

1%

402

MF-LF

56.2

C4360

1

2

1uF

CERM 402

10%

6.3V

R4360

1

2

1/16W

1% MF-LF

402

56.2

C4317

1

2

0.01uF

CERM

402

20% 16V

NO STUFF

C4319

1

2

PLACEMENT_NOTE=Place C4319 close to connector pin 5.

0.1uF

X7R

603-1

10% 50V

R4319

1

2

1M

1/16W

5%

402

MF-LF

C4314

1

2

CERM 402

20% 50V

0.001uF

L4310

1 2

FERR-250-OHM

CRITICAL

SM

C4315

1

2

CERM 603

20% 50V

0.01uF

CX4304

1

2

402

NONE

SHORT

NONE

OMIT

C4310

1

2

X7R 402

10% 50V

0.01uF

DP4310

1

2

6

SOT-363

BAV99DW-X-F

C4311

1

2

X7R 402

0.01uF

50V

10%

DP4310

4

5

3

SOT-363

BAV99DW-X-F

DP4311

1

2

6

SOT-363

BAV99DW-X-F

DP4311

4

5

3

SOT-363

BAV99DW-X-F

C4313

1

2

X7R 402

10% 50V

0.01uF

C4312

1

2

0.01uF

402

X7R

10% 50V

R4390

1 2

332

MF-LF

402

1%

1/16W

D4390

1

3

CRITICAL

MMBZ5227B

SOT23

J4310

1

10

11

2

3

4

5

6

7

8

9

1394B-UG31903

F-RT-SM1

CRITICAL

FL4300

1

2 3

4

CRITICAL

1210-4SM1

90-OHM-100MA

FL4301

1

2 3

4

90-OHM-100MA

1210-4SM1

CRITICAL

L4360

1 2

0402

CRITICAL

18NH-250MA

L4361

1 2

0402

18NH-250MA

CRITICAL

L4362

1 2

0402

CRITICAL

18NH-250MA

SIGNAL_MODEL=EMPTY

L4363

1 2

0402

SIGNAL_MODEL=EMPTY

18NH-250MA

CRITICAL

CX4305

1

2

402

NONE

SHORT

NONE

OMIT

CX4306

1

2

402

NONE

SHORT

NONE

OMIT

CX4307

1

2

402

NONE

SHORT

NONE

OMIT

CX4302

1

2

402

NONE

SHORT

NONE

OMIT

CX4303

1

2

402

NONE

SHORT

NONE

OMIT

CX4300

1

2

402

NONE

SHORT

NONE

OMIT

CX4301

1

2

402

NONE

SHORT

NONE

OMIT

FireWire Ports

SYNC_MASTER=M76_MLB

SYNC_DATE=03/19/2007

8841

14.0.0

051-7225

FW_B_TPB_L_N

FW_PORT1_TPA_P

FW_PORT1_TPB_P FW_PORT1_TPB_N

FW_PORT1_TPB_C

FW_PORT0_TPB_N

FW_PORT0_TPB_C

FW_PORT0_TPA_P

MAKE_BASE=TRUE

FW_PORT0_TPA_N

MAKE_BASE=TRUE

FW_PORT0_TPB_N

MAKE_BASE=TRUE

FW_PORT0_TPB_P

MAKE_BASE=TRUE

FW_PORT1_TPA_P

MAKE_BASE=TRUE

FW_PORT1_TPB_P

MAKE_BASE=TRUE

FW_PORT1_TPA_N

FW_PORT1_TPB_N

MAKE_BASE=TRUE

PP3V3_FW

FW_B_TPA_L_N

PP3V3_FW

FW_PORT0_TPB_P

FW_0_TPBIAS

FW_PORT1_TPA_N

FW_PORT0_TPA_N

FW_PORT0_TPA_P

FW_B_TPA_L_P

FW_1_TPBIAS

PP2V4_FW_LATEVG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm VOLTAGE=2.4V

FW_PORT0_TPB_FL_N

FW_PORT0_TPA_FL_N FW_PORT0_TPB_FL_P

PPVP_FW_PORTB_UF

FW_PORT0_TPA_N

FW_PORT0_TPA_FL_P

PPVP_FW_PORTA_UF

FW_PORT0_TPB_N

GND_CHASSIS_RTUSB

PPVP_FW_PORT0

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V

FW_PORT0_TPA_P

PP2V4_FW_LATEVG

FW_PORT0_TPB_P

GND_CHASSIS_ENET

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V

PPVP_FW_PORT1

GND_CHASSIS_ENET

PP2V4_FW_LATEVG

FW_PORT1_TPA_P

FW_PORT1_AREF

FW_PORT1_TPA_N

GND_CHASSIS_ENET

FW_PORT1_TPB_P

FW_PORT1_TPB_N

FW_B_TPB_L_P

GND

64

41

85

40

85

43

85

41

85

41

39

41

40

41

40

41

37

41

39

8

39

40

87

8

39

87

8

39

9

39

40

39

9

40

39

BI BI

IN

OUT

G

D

S

G

D

S

IN

Y

B

A

SGD

IN

BI

IN

OUT

BI BI BI BI

IN

OUT

IN

OUT

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(UATA_CS0*)

Placement note

Place within 12.7mm from ball of SB

(UATA_CS1*)

Indicates disk presence

NC

(UATA_HSTROBE)

Unused SATA Ports

(UATA_DSTROBE)

(SB has internal pulldown 5.7k-23.5k)

IDE (ODD) Connector

(UATA_STOP)

(ODD has internal

516S0335

100K pull-up to 5V)

23 42 82

Q4421

3

5

4

SOT-363

2N7002DW-X-F

Q4421

6

2

1

SOT-363

2N7002DW-X-F

R4422

1

2

100K

MF-LF

402

5%

1/16W

24

J4400

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26

27

28

29

3

30

31

32

33

34

35

36

37

38

39

4

40

41

42

43

44

45

46

47

48

49

5

50

6 7 8 9

M-ST-SM1-LF

CRITICAL

R4420

1

2

5%

MF-LF

402

1/16W

10K

R4421

12

47K

1/16W MF-LF

5%

402

C4422

1

2

402

CERM

0.068UF

10V

10%

24 82

R4430

1

2

100K

MF-LF

402

5%

1/16W

U4430

3

2

1

4

5

MC74VHC1G09

SC70

Q4420

1 2 5 6

3

4

CRITICAL

SOT-6

FDC606P

23 82

R4460

1

2

1%

24.9

1/16W MF-LF 402

23 82

R4402

1

2

1/16W

5% MF-LF

4.7K

402

R4403

1

2

1/16W

5%

402

MF-LF

6.2K

45

R4410

1

2

402

MF-LF

1/16W

5%

33K

23 82

23 82 23 82

23 82

C4421

1 2

0.01UF

CERM

16V

10%

402

23 82

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

8842

14.0.0

051-7225

PATA Connector

ODD_RST_BUF_L

PP5V_S0

ODD_RST_5VTOL_L

ODD_PWR_EN

ODD_RST_BUF_L

IDE_PDD<3>

IDE_PDD<4>

IDE_PDA<0>

IDE_PDD<15>

IDE_PDD<13>

IDE_PDD<10>

IDE_PDD<9>

IDE_PDD<8>

IDE_PDA<2>

IDE_PDCS1_L

IDE_PDA<1>

IDE_PDDACK_L

IDE_PDIOR_L

IDE_PDIOW_L

IDE_PDD<0>

IDE_PDD<1>

IDE_PDD<5>

IDE_PDD<6>

IDE_PDD<7>

IDE_PDCS3_L

PP3V3_S0

TP_SATA_C_D2RN

TP_SATA_C_D2RP

TP_SATA_B_D2RN

TP_SATA_B_D2RP

TP_SATA_C_R2DN

TP_SATA_C_R2DP

TP_SATA_B_R2DN

TP_SATA_B_R2DP

SATA_RBIAS

TP_SATA_B_R2DP

MAKE_BASE=TRUE

TP_SATA_C_R2DP

MAKE_BASE=TRUE

TP_SATA_C_R2DN

TP_SATA_C_D2RP

MAKE_BASE=TRUE

TP_SATA_B_R2DN

MAKE_BASE=TRUE

TP_SATA_B_D2RN

MAKE_BASE=TRUE

TP_SATA_B_D2RP

MAKE_BASE=TRUE

TP_SATA_C_D2RN

MAKE_BASE=TRUE

SATA_RBIAS

MAKE_BASE=TRUE

IDE_PDD<11>

IDE_PDD<12>

IDE_PDD<14>

SMC_ODD_DETECT

IDE_PDIORDY

IDE_PDDREQ

IDE_PDD<2>

IDE_IRQ14

ODD_PWR_EN_L

P5VODD_EN_L

PP5V_S0

P5VODD_SS

PP5V_S0

PP5V_ODD

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=5V

87 77 75 74 65 59 58 57 52 51 50 48 47 46 32 31 30

78

29

78

76

28

76

65

27

65

59

26

59

58

25

58

57

24

57

52

23

52

47

21

47

42

19

42

27

16

82

27

8

13

42

8

42

7

42

8

23

7

OUT

VBUS

D-

D+

GND

IN

OUT

EN

OC*

GND

THRML

PAD

VDD

THRM_PAD

GND

0I0 Y0

SEL

1I1

1I0

0I1

Y1

BI

SYM_VER-1

IN OUT

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Port Power Switch

Right USB Port

Place L4600 and L4605 across moat

514S0115

If power source is S3, can tie EN to IN.

SEL=0 Choose SMC SEL=1 Choose USB

USB/SMC Debug Mux

L4605

1 2

FERR-220-OHM-2A

0603

CRITICAL

C4696

1

2

CRITICAL

100UF

6.3V

20%

B2

POLY

C4695

1

2

CERM

10uF

20%

805-1

6.3V

C4690

1

2

6.3V

20%

805-1

CERM

10uF

C4691

1

2

10V

20% 402

CERM

0.1UF

C4605

1

2

0.01uF

CERM

402

20% 16V

CX4601

1

2

402

NONE

SHORT

NONE

OMIT

13 24

J4600

1 2 3 4

5 6

7 8

CRITICAL

F-RT-SM-USB-RGT1

UAR2X

D4600

3

12

RTUSB_ESD

RCLAMP0502B

SC-75

CRITICAL

U4690

4

1

2

3

5

8

7

6

9

CRITICAL

MSOP

TPS2051

U4650

12

10

11

9

157

6

13

2

8

3 4

SIGNAL_MODEL=USB_MUX

SMC_DEBUG_YES

CRITICAL

TDFN

PI3USB10

24 82

C4650

1

2

0.1UF

10V

20%

402

CERM

SMC_DEBUG_YES

R4650

1

2

1/16W

5%

402

MF-LF

10K

L4600

1

2 3

4

CRITICAL

90-OHM-100MA

1210-4SM1

7

45 46 47

7

45 46 47

45

7

25 34 45 57 65

R4651

1 2

402

5%

0

MF-LF

1/16W

SMC_DEBUG_NO

R4652

1 2

SMC_DEBUG_NO

0

402

5%

MF-LF

1/16W

CX4600

1

2

402

NONE

SHORT

NONE

OMIT

CX4603

1

2

402

NONE

SHORT

NONE

OMIT

CX4602

1

2

402

NONE

SHORT

NONE

OMIT

051-7225

External USB Connector

SYNC_DATE=03/19/2007

SYNC_MASTER=M76_MLB

14.0.0

8843

USB_EXTA_OC_L

PP5V_S5

PP3V42_G3H

USB_EXTA_P

USB_EXTA_N

USB2_EXTA_MUXED_N

SMC_TX_L SMC_RX_L

USB_DEBUGPRT_EN_L

VOLTAGE=5V

MIN_NECK_WIDTH=0.5 mm

PP5V_S3_RTUSB_F

MIN_LINE_WIDTH=0.5 mm

PM_S4_STATE_L

USB2_RT_P

USB2_EXTA_MUXED_P

USB2_RT_N

GND_CHASSIS_RTUSB

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm

PP5V_S3_RTUSB_ILIM

74

78

65

63

48

62

47

61

46

60

45

57

34

27

28 9 8 8 7

87

87 87

87

SYM_VER-1

BI

SYM_VER-1

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_5_ITEM

Keep close to FL4735 to keep return current loop small

SIM Interconnect

NC

WWAN Ground WWAN Ground

WWAN Ground

NC

WWAN USB D+

WWAN Power

WWAN TwinAx Shield 2

WWAN Ground

NC

WWAN_SIM_CLOCK

WWAN_SIM_VCC

WWAN_SIM_RESET

WWAN_SIM_DATA

WWAN Power

514S0171

Camera Power

WWAN USB D-

Camera USB D+

Camera Ground

WWAN Power

Camera TwinAx Shield

Connector shield

Camera Power

Camera Ground

Camera USB D-

514S0172

Keep close to FL4745 to keep return current loop small

Left Clutch Barrel Interconnect

C4730

1

2

0.01UF

10% X7R

402

50V

L4731

1 2

OMIT

CRITICAL

FERR-220-OHM-2A

0603

C4731

1

2

NO STUFF

0.001uF

50V

CERM

402

20%

L4741

1 2

0603

FERR-220-OHM-2A

CRITICAL

OMIT

L4730

1 2

0603

FERR-220-OHM-2A

CRITICAL

J4731

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25

26 27 28 29

3

30

31

32

4 5 6 7 8 9

CRITICAL

20347-125E-12

F-RT-SM

FL4745

1

2 3

4

90-OHM-100MA

CRITICAL

1210-4SM1

7

24 44 82

7

24 44 82

C4740

1

2

X7R 402

0.01UF

10% 50V

L4740

1 2

FERR-220-OHM-2A

CRITICAL

0603

C4741

1

2

NOSTUFF

0.001uF

CERM

402

20% 50V

7

24 82

J4732

1

10

11 12

13

14

2 3 4 5 6 7 8 9

CRITICAL

20347-110E-12

F-RT-SM

L4764

1 2

FERR-120-OHM-1.5A

0402

NO STUFF CRITICAL

7 24 82

FL4735

1

2 3

4

CRITICAL

90-OHM-100MA

1210-4SM1

2

113S0022

L4731,L4741

CRITICAL

RES,MF,1/10W,0OHM,5,0603,SM,LF

44 88

14.0.0

051-7225

Left Clutch Barrel Interconnect

SYNC_MASTER=M76_MLB

SYNC_DATE=03/19/2007

GND_CHASSIS_LEFTCLUTCH

USB_CAMERA_P

PP5V_S3

USB_WWAN_P

MAKE_BASE=TRUE

USB_WWAN_F_N

USB_CAMERA_N

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

PP5V_S3_WWAN_F

GND_CHASSIS_LEFTCLUTCH

USB_CAMERA_F_N

WWAN_SIM_CLOCK PPVCC_WWAN_SIM

USB_WWAN_F_P

WWAN_SIM_RESET WWAN_SIM_DATA

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

PP5V_S3_CAMERA_F

USB_CAMERA_F_P

PP5V_S3

USB_WWAN_P

USB_WWAN_N

MAKE_BASE=TRUE

USB_WWAN_N

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

PPVCC_WWAN_SIM

WWAN_SIM_RESET

WWAN_SIM_CLOCK

WWAN_SIM_DATA

78

57

53

49

46

51

44

51

44

8

44

87

8

87

9

7

87

9

87

44

87

44

87

7

44

IN

OUT

IN

OUT

IN IN IN IN IN IN IN IN

IN

OUT

IN

OUT

P16

P51

P50

P42/SDA1

P97/IRQ15*/SDA0

P95/IRQ14*

P94/IRQ13*

P93/IRQ12*

P92/IRQ0*

P91/IRQ1*

P86/IRQ5*/SCK1/SCL1

P83/LPCPD*

P82/CLKRUN*

P80/PME*

P35/LRESET*

P34/LFRAME*

P10

P12 P13 P14 P15

P17

P31/LAD1

P30/LAD0

P32/LAD2 P33/LAD3

P36/LCLK P37/SERIRQ

P44/TMO1

P77/AN7

P76/AN6

P81/GA20

P96/EXCL

P11

P47/PWX1/PWM1

P45 P46/PWX0/PWM0

P40/TMIO

P43/TMI1/EXSCK1

P27

P26

P25

P24

P23

P22

P21

P20

P41/TMO0

P52/SCL0

P60/KIN0* P61/KIN1* P62/KIN2* P63/KIN3* P64/KIN4*

P65/KIN5* P66/IRQ6*/KIN6* P67/IRQ7*/KIN7*

P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5

P84/IRQ3*/TXD1 P85/IRQ4*/RXD1

P90/IRQ2*

(1 OF 4)

PA2/KIN10*/PS2AC PA3/KIN11*/PS2AD

PA5/KIN13*/PS2BD

PA4/KIN12*/PS2BC

PB2 PB3 PB4

PE0

PG6/EXIRQ14*/EXSDAB

PG5/EXIRQ13*/EXSCLA

PH1/EXIRQ7*

PH0/EXIRQ6*

PG7/EXIRQ15*/EXSCLB

PG4/EXIRQ12*/EXSDAA

PH3/EXEXCL

PH2/FWE

PB5

PF4/PWM4

PF2/IRQ10*/TMOY

PG2/EXIRQ10*/SDA2

PG0/EXIRQ8*/TMIX

PF7/PWM7

PC3/TIOCD0/TCLKB/WUE11*

PH5

PB7

PB6

PH4

PF5/PWM5 PF6/PWM6

PG1/EXIRQ9*/TMIY

PA6/KIN14*/PS2CC PA7/KIN15*/PS2CD

PD0/AN8 PD1/AN9 PD2/AN10 PD3/AN11 PD4/AN12 PD5/AN13 PD6/AN14 PD7/AN15

PF0/IRQ8*/PWM2 PF1/IRQ9*/PWM3

PB0/LSMI* PB1/LSCI

PC0/TIOCA0/WUE8* PC1/TIOCB0/WUE9* PC2/TIOCC0/TCLKA/WUE10*

PC4/TIOCA1/WUE12* PC5/TIOCB1/TCLKC/WUE13* PC6/TIOCA2/WUE14* PC7/TIOCB2/TCLKD/WUE15*

PG3/EXIRQ11*/SCL2

PF3/IRQ11*/TMOX

PA1/KIN9*/PA2DD

PA0/KIN8*/PA2DC

PE1*/ETCK PE2*/ETDI PE3*/ETDO PE4*/ETMS

(2 OF 4)

VCL

AVREF

VCC

AVCC

XTAL EXTAL

AVCC

VCC

MD1 MD2

NMI

RES*

ETRST*

AVREF

AVSS

VSS

(3 OF 4)

NC22

NC21

NC20

NC19

NC18

NC17

NC16

NC15

NC14

NC13

NC12

NC9

NC6

NC11

NC10

NC8

NC7

NC5

NC4

NC3

NC2

NC1

NC0

(4 OF 4)

OUT OUT

BI

IN

OUT

BI

OUT

IN

OUT

IN

OUT OUT OUT OUT

IN

IN IN

IN

IN IN

IN

OUT

IN

OUT OUT OUT OUT

BI BI BI BI BI BI

OUT OUT

OUT

IN

OUT

IN

OUT OUT

BI

OUT

IN

OUT

IN

BI BI BI BI

IN IN IN

OUT

BI

IN IN IN IN

BI

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

If SMS interrupt is not used, pull up to SMC rail.

NOTE: SMS Interrupt can be active high or low, rename net accordingly.

NC

NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC NC NC

(DEBUG_SW_3)

those designated as inputs require pull-ups.

NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating,

(OC)

(DEBUG_SW_2)

(DEBUG_SW_1)

(OC)

(OC) (OC) (OC) (OC) (OC) (OC)

C4902

1

2

CERM-X5R

22UF

20%

6.3V

805-3

7

25 46 47

7

46 47

7

46 78

C4907

1

2

CERM-X5R

0.47UF

PLACEMENT_NOTE=Place C4907 close to U4900 pin F1

10% 402

6.3V

C4903

1

2

CERM

10V

0.1UF

402

20%

C4920

1

2

PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15

CERM

10V

0.1UF

402

20%

R4999

1 2

MF-LF

5%

1/16W

4.7

402

PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15

C4904

1

2

CERM

10V

0.1UF

402

20%

XW4900

1

2

SM

25

7

58

C4905

1

2

CERM

10V

0.1UF

402

20%

7

25

46 60

28 46 65

38

C4906

1

2

CERM

10V

0.1UF

402

20%

49

7

46 56

34 46

7

43 45 46 47

7

43 45 46 47

34 36 40 46

65

U4900

B12 C13 A15 B14 B15 C14 D12 C15

D13 D14 D15 E12 E14 E15 E13 F14

D9 C9 A9 B9 D8 C8 A8 D7

A5 B5 D5 C3 B1 C2 D3 C1

G1 G4 F2

L13 L14 L15 K12 K13 K14 J12 J13

N12 R13 P13 R14 P14 R15 N13 P15

C7 A7 B7 D6 C6 A6 B6

K4 J2 J1 J3 J4 H2 H1 G2

OMIT

SMC_H8S2116

BGA

U4900

R3 P3 R2 N3 R1 N2 M4 N1

B10 A10 D10 A11 B11 C11 A12 D11

G14 G15 G13 G12 H14 H15 H13 H12

M11 P11 R11 N11 P10 R10 N10 M10

M3 M2 M1 L4 L2

M7 P6 R6 N6 M6 R5 P5 N5

P9 R9 N9 P8 R8 M8 P7 R7

E1 F3 K2 C4 D4 B3

BGA

OMIT

SMC_H8S2116

U4900

N14

N15

M14

M15

P12 R12

L1

B2

E2 K1

F4

E3

P2P1J15A1F1

D1P4R4

F12

F13

B13

A13

A4B4D2

A2

OMIT

SMC_H8S2116

BGA

U4900

G3 H3

K15 J14

F15 A14 C12 C10 C5 A3 B8 E4

K3

H4 M9 N8

L3 N4 M5

N7 M12 M13 L12

OMIT

SMC_H8S2116

BGA

34 46

48 54 84

R4909

1

2

1/16W

5%

MF-LF

10K

402

7

47

7

47

R4901

1

2

1/16W

5%

10K

402

MF-LF

R4902

1

2

10K

MF-LF

5% 1/16W

402

R4903

1

2

1/16W

5% MF-LF

0

NO STUFF

402

R4998

1

2

1/16W

5% MF-LF

10K

402

43

34 46

16 32

25

7

49

42

34 46

34

25

46

52

46

52

54

49

54

53

49

7

46 47

46

7

46 47

7

46 47

7

46 47

46 78

34

46

34

46

7

48 56 84

7

48 56 84

48 51 78 84

34 48 51 84

46

7

53 78

54

49

7

43 45 46 47

7

43 45 46 47

46

9

54

46

7

25 47

16 31

7

25 28

7

47

13 25

7

25 47

7

25

46

7

23 47

7

23 47

7

23 47

7

23 47

7

23 47

7

28

30 84

53

48 51 73 84

7

25 35 36 40 49 57 62 65

7

25 34 43 57 65

7

25 46

48 51 73 84

48 54 84

46

051-7225

14.0.0

8845

SMC

SYNC_MASTER=T9_NOME

SYNC_DATE=01/17/2007

PM_LAN_ENABLE

TP_SMC_P22

SMC_PH4

SMC_PF3

PM_SYSRST_L

SMC_BATT_ISET

TP_SMC_SYS_VSET

SMC_FAN_1_TACH

SMC_FAN_0_TACH

TP_SMC_FAN_3_CTL

TP_SMC_FAN_2_CTL

TP_SMC_GFX_OVERTEMP_L

SMC_EXCARD_OC_L

ISENSE_CAL_EN

SMC_ODD_DETECT

SMC_RUNTIME_SCI_L

SMC_EXCARD_CP SMC_EXCARD_PWR_EN

SMC_PB0

SYS_ONEWIRE PM_BATLOW_L

SMS_ONOFF_L

SMC_FWE ALS_GAIN

SMC_THRMTRIP

SMBUS_SMC_B_S0_SCL SMC_PROCHOT

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_BSA_SDA

SMC_TDI

SMC_CASE_OPEN

SMBUS_SMC_0_S0_SDA

SUS_CLK_SB

PM_S4_STATE_L

SMC_BS_ALRT_L

SMC_BC_ACOK

SMC_CPU_VSENSE

SMC_CPU_ISENSE

SMC_PM_G2_EN

SMC_EXTAL

SMC_XTAL

SMC_RESET_L

GND_SMC_AVSS

PP3V3_S5_SMC_AVCC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

SMC_MD1

PP3V42_G3H

SMC_PA1

SMC_PA0

PM_EXTTS_L<0>

SMC_VCL

SMC_NMI

SMC_TRST_L

SMC_KBC_MDE

TP_SMC_P23

TP_SMC_P26 TP_SMC_P27

RSMRST_PWRGD

SMC_RSTGATE_L ALL_SYS_PWRGD

SMC_BATT_TRICKLE_EN_L SMC_BATT_CHG_EN

LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L SMC_LRESET_L PCI_CLK33M_SMC

SMBUS_SMC_MGMT_SDA

SMC_SYS_KBDLED SMC_TX_L

SMC_RX_L SMBUS_SMC_0_S0_SCL

INT_SERIRQ

TP_SMC_P44

TP_SMC_P46

USB_DEBUGPRT_EN_L

PM_EXTTS_L<1>

SMC_FAN_0_CTL

TP_SMC_FAN_3_TACH SMS_X_AXIS

SMC_NB_CORE_ISENSE SMC_NB_1V8_ISENSE ALS_LEFT ALS_RIGHT

PM_RSMRST_L

TP_SMC_P21

TP_SMC_P20

IMVP_VR_ON

SMC_FAN_1_CTL

SMC_NBGFXCORE_ISENSE

SMS_Z_AXIS

SMS_Y_AXIS

TP_SMC_FAN_2_TACH

SMBUS_SMC_A_S3_SCL

SMC_SMS_INT

SMC_PROCHOT_3_3_L

PM_PWRBTN_L

PM_SLP_S3_L

SMC_SYS_ISET

TP_SMC_BATT_VSET

SMC_TDO SMC_TMS

SMBUS_SMC_BSA_SCL

SMC_LID

TP_SMC_PF1

TP_SMC_PF0

SMC_TCK

PP3V3_S5_AVREF_SMC

SMC_GPU_VSENSE

PM_CLKRUN_L PM_SUS_STAT_L

SMC_RX_L

SMC_ONOFF_L

SMC_PG0

PM_SLP_S5_L

SMC_NB_1V25_ISENSE

SMC_BATT_ISENSE

SMC_PBUS_VSENSE

SMC_DCIN_ISENSE

SMC_TX_L

TP_SMC_P81

SMC_WAKE_SCI_L

SMBUS_SMC_MGMT_SCL

SMC_SYS_LED

TP_SMC_P43

SMC_ENRGYSTR_LDO_EN

TP_SMC_GFX_THROTTLE_L

PM_LAN_PWRGD

SMC_P67

TP_SMC_P14

SMC_GPU_ISENSE

SMC_ADAPTER_EN TP_SMC_P62 TP_SMC_P63 TP_SMC_P64

78 65 48 47 46 43 34

53

28

49

8

46

46 46

46

7

46

34

46

G

D

S

IN

OUT

GND

NC

CD

GND

OUT

VDD

OUT

IN

OUT

IN

OUT

IN

BI

OUT

IN

G

D

S

G

D

S

OUT

IN

OUT

IN

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SMC Crystal Circuit

Debug Power "Button"

System (Sleep) LED Circuit

S5 Rail PWRGD Circuit

TPS51120 PGOOD threshold 87-93% (2.87 - 3.07V)

TPS51120 PGOOD threshold 87-93% (4.35 - 4.65V)

Reports when 5V S5 and 3.3V S5 are in regulation

NC

TO SMC

TO CPU

SMC FSB to 3.3V Level Shifting

LAN PWRGD Circuit

SMC AVREF Supply

SMC Reset "Button" / Brownout Detect

C5000

1

2

10V

0.1uF

402

20%

CERM

Q5059

6

2

1

SOT-363

2N7002DW-X-F

C5020

1

2

CERM-X5R

10%

402

6.3V

0.47UF

C5026

1

2

0.01UF

10% 16V

402

CERM

C5025

1

2

20% X5R

603

10uF

6.3V

VR5020

3

1 2

CRITICAL

REF3133

SOT23-3

R5095

1 2

MF-LF

402

5%

1/16W

0

R5070

1 2

10K

1/16W5%MF-LF

402

R5071

1 2

100K

MF-LF

5%

1/16W

402

R5072

1 2

10K

5%

MF-LF1/16W

402

R5073

1 2

402

10K

1/16W5%MF-LF

R5074

1 2

402

1/16W MF-LF

5%

100K

R5075

1 2

ONEWIRE_PU

402

1/16W5%MF-LF

2.0K

R5076

1 2

402

100K

1/16W5%MF-LF

R5077

1 2

402

10K

1/16W5%MF-LF

R5078

1 2

402

MF-LF

5%

1/16W

10K

R5079

1 2

402

MF-LF1/16W

5%

10K

R5080

1 2

402

MF-LF

5%

1/16W

10K

R5083

1 2

402

MF-LF

5%

1/16W

10K

R5084

1 2

402

MF-LF

5%

1/16W

10K

R5085

1 2

10K

4025%

MF-LF1/16W

R5086

1 2

10K

402

MF-LF

5%

1/16W

R5087

1 2

1/16W MF-LF

402

470K

5%

R5088

1 2

MF-LF

4025%

1/16W

10K

Y5010

1

2

CRITICAL

5X3.2-SM

20.00MHZ

U5000

5

3

4

1

2

RN5VD30A-F

SOT23-5

CRITICAL

R5089

1 2

1/16W5%MF-LF

402

100K

R5090

1 2

1/16W MF-LF

402

100K

5%

7

45 47

R5082

1 2

402

10K

1/16W5%MF-LF

R5081

1 2

10K

1/16W5%MF-LF

402

45

10 16 23 79

78

R5001

1

2

OMIT

1/10W

0

MF-LF

5%

603

R5015

1

2

OMIT

1/10W

0

MF-LF

5%

603

R5045

1

2

1/16W

5%

402

MF-LF

10K

45 46 60 45 46 60

C5045

1

2

CERM

50V

10%

0.0022UF

402

45 46 60

Q5060

5

3

4

SOT-363-LF

MMDT3904XF

R5061

1

2

3.3K

402

5% 1/16W MF-LF

Q5060

2

6

1

SOT-363-LF

MMDT3904XF

R5062

1 2

402

MF-LF

5%

1/16W

3.3K

R5060

1

2

5% 1/16W MF-LF 402

470

10 58 79

45

Q5059

3

5

4

2N7002DW-X-F

SOT-363

R5091

1 2

402

MF-LF

5%

1/16W

100K

R5093

1 2

402

1/16W MF-LF

5%

100K

R5092

1 2

402

1/16W5%MF-LF

100K

Q5032

3

1

2

2N7002

SOT23-LF

R5096

1 2

10K

1/16W5%MF-LF

402

R5094

1 2

10K

1/16W5%MF-LF

402

R5097

1

2

MF-LF

1/16W

100K

NO STUFF

402

5%

R5098

1 2

0

402

5%

MF-LF

1/16W

45 28 45 65

34 45 46

R5000

1

2

402

1K

MF-LF

5% 1/16W

7

45 46 78

Q5030

1

3

2

SOT23-LF

2N3906

R5030

1

2

1/16W

100

MF-LF

5%

402

R5031

1

2

1/16W

5%

MF-LF

2.2K

402

45

R5032

1

2

5%

MF-LF

402

10K

1/16W

C5010

1 2

CERM

402

5%

50V

15pF

C5011

1 2

50V

CERM

402

15pF

5%

C5001

1

2

402

CERM

16V

0.01UF

10%

SMC Support

SYNC_MASTER=(MASTER)

46 88

14.0.0

051-7225

SYNC_DATE=(MASTER)

353S1278353S1381

Intersil ISL60002-33

ALL

SMC_ENRGYSTR_LDO_EN

MAKE_BASE=TRUE

SUS_CLK_SB

TP_SMC_P81 TP_SMC_PF0 TP_SMC_PF1

SMC_EXCARD_OC_L

PP3V42_G3H

SMC_PH4

SMC_BATT_TRICKLE_EN_L

SMC_ADAPTER_EN

SMC_MANUAL_RST_L

SMC_EXTAL

PP3V3_S0

SMC_P67

SMC_PG0

SMC_THRMTRIP

PM_THRMTRIP_L

SMC_PROCHOT

CPU_PROCHOT_L_R

CPU_PROCHOT_L

CPU_PROCHOT_BUF

PP1V05_S0

TP_SMC_P44

MAKE_BASE=TRUE

TP_SMC_P44

TP_SMC_P43

MAKE_BASE=TRUE

TP_SMC_P43

TP_SMC_P27 TP_SMC_P27

MAKE_BASE=TRUE

TP_SMC_P26 TP_SMC_P26

MAKE_BASE=TRUE

TP_SMC_P23 TP_SMC_P23

MAKE_BASE=TRUE

TP_SMC_P22

MAKE_BASE=TRUE

TP_SMC_P22

TP_SMC_P21 TP_SMC_P21

MAKE_BASE=TRUE

TP_SMC_GFX_THROTTLE_L TP_SMC_GFX_THROTTLE_L

MAKE_BASE=TRUE

TP_SMC_GFX_OVERTEMP_L TP_SMC_GFX_OVERTEMP_L

MAKE_BASE=TRUE

TP_SMC_FAN_3_CTL TP_SMC_FAN_3_CTL

MAKE_BASE=TRUE

TP_SMC_FAN_3_TACH TP_SMC_FAN_3_TACH

MAKE_BASE=TRUE

TP_SMC_FAN_2_TACH TP_SMC_FAN_2_TACH

MAKE_BASE=TRUE

TP_SMC_FAN_2_CTL TP_SMC_FAN_2_CTL

MAKE_BASE=TRUE

SMC_XTAL

SYS_LED_ILIM

PP5V_S3

SYS_LED_ANODE

SYS_LED_L_VDIV

SMC_RESET_L

VOLTAGE=3.3V

PP3V3_S5_AVREF_SMC

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PM_SUS_STAT_L

SMC_EXCARD_CP

SMC_BC_ACOK

PM_SLP_S5_L

RSMRST_PWRGD

MAKE_BASE=TRUE

RSMRST_PWRGD

PP3V3_S5

EXCARD_OC_L

SMC_SYS_LED

SYS_LED_L

SMC_CASE_OPEN

SMC_PA0 SMC_PA1 SMC_PB0

SMC_ONOFF_L

SMC_TX_L

SMC_FWE

SMC_LID

SMC_RX_L

SYS_ONEWIRE SMC_BS_ALRT_L

SMC_TDO

SMC_TMS

SMC_TDI SMC_TCK

SMC_PF3

MAKE_BASE=TRUE

TP_SMC_BATT_VSETTP_SMC_BATT_VSET TP_SMC_SYS_VSET

MAKE_BASE=TRUE

TP_SMC_SYS_VSET

TP_SMC_P20

MAKE_BASE=TRUE

TP_SMC_P20

TP_SMC_P14

MAKE_BASE=TRUE

TP_SMC_P14

PP3V3_S0

SMC_PROCHOT_3_3_L

MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

MIN_LINE_WIDTH=0.4 mm

GND_SMC_AVSS

PP3V42_G3H

ALL_SYS_PWRGD

SMC_ONOFF_L

SUS_CLK_SB

PM_LAN_PWRGD

TP_SMC_P62

MAKE_BASE=TRUE

TP_SMC_P62

TP_SMC_P46

MAKE_BASE=TRUE

TP_SMC_P46

TP_SMC_P64

MAKE_BASE=TRUE

TP_SMC_P64

MAKE_BASE=TRUE

TP_SMC_P63TP_SMC_P63

MAKE_BASE=TRUE

TP_SMC_P81 TP_SMC_PF0

MAKE_BASE=TRUE

TP_SMC_PF1

MAKE_BASE=TRUE

SMC_ENRGYSTR_LDO_EN

SMC_BATT_CHG_EN

87

77

75

74

65

59

58

57

52

51

50

48

47

46

42

32

61

32

31

50

31

30

87

30

29

27

75

29

78

28

26

65

28 78

78

65

27

23

60

27 65

65

48

26

21

57

26 48

48

47

25

19

55

25 47

47

46

24

18

78

48

24 46

46

45

23

14

57

28

23 45

45

43

21

13

53

27

21 43

43

34

45

19

12

49

47

26

78

47

19 34

34

46

28

40

16

11

44

45

25

46

45

56

47

16

53

28

46

45

46

8

45

36

13

10

46 46

46

46 46

46

8

25

45

25

24

34

45

43

78

43

45

46 46

13

49

8

45

46 46

46

45

34

25

45

7

45

34

45

8

45

8

45 45

45

7

45

7

34

7

8

24

45

7

45

7

34

7

45

45 45

8

45

7

25

45 45

45

34

BI

IN

OUT OUT OUT

OUT

IN

BI

OUT OUT OUT

OUT

IN

OUT

IN

OUT

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

516S0394

LPC+ Connector

FWH_INIT_L Generation

7

23 45

7

25 45

7

30 84

7

25 45 46

7

25 45

7

24 38 83

7

45 46

7

45

7

45

7

28

7

23 45

7

23 45

7

23 45

7

45 46

7

45 46

7

45

7

25

Q5190

5

3

4

MMDT3904XF

SOT-363-LF

LPCPLUS

Q5190

2

6

1

LPCPLUS

PLACEMENT_NOTE=Place Q5190 close to R5190

SOT-363-LF

MMDT3904XF

R5192

1

2

330

LPCPLUS

MF-LF

1/16W

5%

402

R5191

1

2

LPCPLUS

5% 1/16W MF-LF 402

1.3K

R5190

1 2

LPCPLUS

330

402

MF-LF

5%

1/16W

PLACEMENT_NOTE=Place R5190 to minimize CPU_INIT_L stub

10 23 79

7

43 45 46

7

43 45 46

7

45 46

7

45 46

J5100

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

CRITICAL

LPCPLUS

M-ST-SM

QT500306-L021-9F

7

23 45

SYNC_DATE=03/19/2007

LPC+ Debug Connector

051-7225

47 88

14.0.0

SYNC_MASTER=M76_MLB

CPU_INIT_R_L

PP3V3_S0

CPU_INIT_L

SMC_TX_L

SMC_MD1

SMC_TDO

SMC_TRST_L

DEBUG_RESET_L

LINDACARD_GPIO

SMC_RX_L

SMC_NMI

SMC_RESET_L

SMC_TCK

SMC_TDI

PM_SUS_STAT_L

INT_SERIRQ

LPC_AD<3>

LPC_AD<2>

PCI_CLK33M_LPCPLUS

FWH_INIT_L

CPU_INIT_LS3V3

SMC_TMS

PCI_FW_GNT_L

PM_CLKRUN_L

LPC_FRAME_L

LPC_AD<1>

LPC_AD<0>

PP5V_S0

PP3V42_G3H

87 77 75 74 65 59 58 57 52

51 50 48 46 42 32 31 30 29 28

78

27

76

78

26

65

25

59

48

24

58

46

23

57

45

21

52

43

19

42

34

16

27

28

13

8

7

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

EMC1043-5: U5500

(Write: 0x98 Read: 0x99)

EMC1043-5: U5570

SMC "B" SMBus Connections

Remote Temps

ExpressCard Slot

U2300

(MASTER?)

ICH8-M

(Address determined by ARP)

Left I/O SMBus Connections:

ICH8-M ME SMBus Connections

(See Table)

Left I/O

J3400

(MASTER)

SMS

(Write: 0x30 Read: 0x31)

SMC "Management" SMBus Connections

(Write: 0x16 Read: 0x17)

Battery

J6950

(MASTER)

U4900

SO-DIMM "A"

The bus formerly known as "Battery B"

ICH8-M

U2300

(MASTER)

Top-Case

TMP401: U5550

SMC

U4900

(MASTER)

SMC

U4900

SMC

SMC "0" SMBus Connections

(MASTER)

NOTE: SMC RMT bus remains powered and may be active in S3 state

SMC "A" SMBus Connections

J3100

J3200

SO-DIMM "B"

U4900

SMC

(MASTER)

(Write: 0xA0 Read: 0xA1)

GPU Temp (Int)

G84M: U8000

(Write: 0xA4 Read: 0xA5)

GPU Temp (Ext)

(Write: 0x98 Read: 0x99)

(Write: 0x9E Read: 0x9F)

U4900

SMC

(Write: 0xD2 Read: 0xD3)

SLG8LP537V: U2900

Clock Chip

ICH8-M SMBus Connections

KXPS5-2050: U5900

CPU Temp

(Write: 0x92 Read: 0x93)

MLB/J9600 -- Flex/TMP105

SMC "Battery A" SMBus Connections

(See Table)

Left I/O Board

J3400

(Write: 0x90 Read: 0x91)

M35B - TMP106

(Write: 0x92 Read: 0x93)

LIO - TMP106

Left I/O SMBus Connections:

R5200

1

2

1/16W

5%

MF-LF

402

4.7K

R5201

1

2

5% 1/16W MF-LF 402

4.7K

R5280

1

2

4.7K

MF-LF

402

5%

1/16W

R5281

1

2

5%

4.7K

1/16W MF-LF 402

R5291

1

2

4.7K

5% 1/16W MF-LF 402

R5290

1

2

4.7K

1/16W

5%

402

MF-LF

R5261

1

2

5% 1/16W MF-LF 402

3.3K

R5260

1

2

5%

MF-LF

1/16W

402

3.3K

R5271

1

2

5% 1/16W

402

MF-LF

4.7K

R5270

1

2

MF-LF

402

5%

1/16W

4.7K

R5251

1

2

5%

402

1/16W

4.7K

MF-LF

R5250

1

2

4.7K

MF-LF

5%

402

1/16W

R5231

1

2

10K

1/16W MF-LF

5%

402

R5230

1

2

10K

5%

402

1/16W MF-LF

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

051-7225

8848

14.0.0

SMBus Connections

SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL

MAKE_BASE=TRUE

SMBUS_SB_SCL

PP3V3_S0

SMBUS_SMC_MGMT_SCL

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SDA

SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA

SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCLSMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

SMBUS_SB_SDA

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SCL

PP3V3_S0

SMBUS_SB_SCL

SMBUS_SB_SDA

SMBUS_SB_SCL

SMBUS_SB_SDA

SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA

PP3V3_S3

SMBUS_SB_SCL

SMBUS_SB_SDA

PP3V42_G3H

SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA

SMBUS_SMC_BSA_SCL

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA

SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA

PP3V3_S3

PP3V3_GPU

MAKE_BASE=TRUE

SMBUS_SB_SCL

MAKE_BASE=TRUE

SMBUS_SB_SDA

PP3V3_S5

SMBUS_SB_SCL SMBUS_SB_SDA

MAKE_BASE=TRUE

SMBUS_SB_ME_SCL SMBUS_SB_ME_SDA

MAKE_BASE=TRUE

SMBUS_SB_ME_SDA

SMBUS_SB_ME_SCL

SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

87

77

75

74

65

59

58

57

52

51

50

48

47

46

42

32

31

30

87

29

75

28

78

65

27

57

78

57

60

26

54

65

54

77

57

25

53

47

53

76

55

82

24

82

24

82

51

82

46

51

74

82

46

82

48

23

48

23

48

50

48

45

50

73

48

28

48

84

34

21

84

34

84

21

34

84

48

34

43

84

48

72

34

27

34

84

51

32

19

84

73

32

73

51

19

32

78

38

32

34

56

78

73

84

56

38

71

32

26

32

78

48

31

16

54

51

31

51

48

16

31

51

36

31

28

48

51

54

48

36

65

31

25

31

82

51

45

29

13

48

29

48

45

13

29

48

8

29

8

45

48

45

8

57

29

24

29

48

34

25

8

45

25

45

34

8

25

45

7

25

7

45

7

8

25

8

25

45

IN

OUT

N-CHN

S

D

G

P-CHN

G

D

S

D

S

G

IN

D

S

G

ININ

IN

OUT

IN

OUT

IN

OUT

IN IN

OUT

OUTOUT

OUT

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NB GFX Current Sense Filter

Place short near U1000 center

Place short near U8000 center

Place RC close to SMC

CPU Voltage Sense / Filter

GPU Voltage Sense / Filter

NB Core Current Sense Filter

Place RC close to SMC

GPU Current Sense Filter

Place RC close to SMC

Current Sense Calibration Circuit

Switches in fixed load on power supplies to calibrate current sense circuits

Place RC close to SMC

CPU Current Sense Filter

Place RC close to SMC

DCIN Current Sense Filter

Place RC close to SMC

Battery (PBUS) Current Sense Filter

Place RC close to SMC

Rthevanin = 4573 ohms

Place RC close to SMC

PBUS Voltage Sense & Filter

NB 1.8V Current Sense Filter

Place RC close to SMC Place RC close to SMC

S0/GPU 1.25V Current Sense Filter

Enables PBUS VSense divider when high.

7

45

R5327

1

2

402

MF-LF

1/16W

5%

100K

R5315

1

2

5% 1/16W MF-LF

402

100K

45

R5385

1

2

27.4K

1% 1/16W MF-LF

402

C5385

1

2

6.3V

0.22UF

402

X5R

20%

R5386

1

2

5.49K

402

MF-LF

1/16W

1%

Q5315

6

2

1

FDG6332C_NL

SC70-6

Q5315

3

5

4

FDG6332C_NL

SC70-6

Q5320

5

4

1 2 3

MICROFET3X3

CRITICAL

FDM6296

R5331

1 2

4.53K

402

MF-LF

1%

1/16W

ISL9504B

58 65

R5322

1

2

1.00

1%

1/4W

MF-LF

1206

Q5322

5

4

1 2 3

CRITICAL

FDM6296

MICROFET3X3

50 50

R5316

1

2

5% 1/16W MF-LF

402

100K

U5327

2

3 1

5

4

SC70-5

SN74AHCT1G125DCKRE4

R5328

12

1K

402

5%

MF-LF

1/16W

C5327

1 2

402

CERM

10V

20%

0.1UF

R5365

1 2

1/16W

4.53K

402

MF-LF

1%

50

C5365

1

2

20% X5R

402

0.22UF

6.3V

45 49

45

C5359

1

2

402

X5R

6.3V

20%

0.22UF

R5359

1 2

4.53K

402

MF-LF

1%

1/16W

45

R5370

1 2

1%

MF-LF

402

4.53K

1/16W

C5370

1

2

6.3V

0.22UF

402

X5R

20%

50 45

C5375

1

2

0.22UF

6.3V X5R

20%

402

R5375

1 2

4.53K

MF-LF

1/16W

1%

402

74

45

C5380

1

2

20% X5R

0.22UF

6.3V 402

R5380

1 2

1%

MF-LF

402

4.53K

1/16W

34 34

R5390

1 2

1% 1/16W MF-LF

402

4.53K

C5390

1

2

20% X5R

402

0.22UF

6.3V

45

C5340

1

2

20% X5R

402

0.22UF

6.3V

R5340

1 2

1/16W

1% MF-LF

402

4.53K

45

C5335

1

2

X5R 402

6.3V

20%

0.22UF

R5335

1 2

4.53K

1/16W

1%

MF-LF

402

45

C5330

1

2

6.3V X5R

20%

402

0.22UF

R5330

1 2

ISL9504A

402

4.53K

MF-LF

1%

1/16W

50

XW5359

1 2

SM

45

R5309

1 2

1/16W MF-LF

4.53K

1%

402

C5309

1

2

0.22UF

20%

6.3V X5R 402

XW5309

1 2

SM

R5320

1

2

1.00

1%

1/4W

MF-LF

1206

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

Current & Voltage Sensing

051-7225

14.0.0

8849

ISENSE_CAL_EN

ISENSE_CAL_EN_LS5V_R

PP5V_S3

IMVP6_IMON

SMC_CPU_ISENSE

CPUVCORE_IOUT

PBUSVSENS_EN_L

PM_SLP_S3_L

PBUSVSENS_EN_DIV

SMC_PBUS_VSENSE

SMC_NB_1V25_ISENSE

P1V25_S0GPU_IOUT

GND_SMC_AVSS

PPBUS_G3H_VSENSE

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.20 mm

GND_SMC_AVSS

PPBUS_G3H

GPUVSENSE_IN

SMC_GPU_VSENSE

CPUVSENSE_IN

SMC_CPU_VSENSE

PPVCORE_GPU

GND_SMC_AVSS

LIO_BATT_ISENSE

GND_SMC_AVSS

SMC_BATT_ISENSE

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.50 mm

CPUVCORE_ISENSE_CAL

GND_SMC_AVSSGND_SMC_AVSS

GND_SMC_AVSS

SMC_DCIN_ISENSE

SMC_NB_1V8_ISENSE

LIO_DCIN_ISENSE

SMC_GPU_ISENSE

GND_SMC_AVSS

PPVCORE_S0_CPU

GPUVCORE_IOUT

PPVCORE_S0_CPU

P1V8_S3_IOUT

GND_SMC_AVSS

SMC_NB_CORE_ISENSE

GND_SMC_AVSS

SMC_NBGFXCORE_ISENSE

NBCORE_IOUT

NBGFXCORE_IOUT

SMC_NBGFXCORE_ISENSESMC_NBGFXCORE_ISENSE

MAKE_BASE=TRUE

PPVCORE_GPU

GPUCORE_ISENSE_CAL

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.50 mm

ISENSE_CAL_EN_LS5V

74 63

62

65

61

62

60

78

57

59

57

45

58

53

40

57

74

49

74

46

36

53

56

67

53

53 53 53

53

12

53

67

44

35

49

40

49

49 49 49

49

11

49

8

25

46

8

46

46 46 46

46

8

46

49

8

7

45

7

45

45 45 45

45

7

45

7

OUT

R1-

R1+

R2

V-

V+

+

IN

OUT

R1-

R1+

R2

V-

V+

+

OUT

IN

OUT

R1-

R1+

R2

V-

V+

+

OUT

R1-

R1+

R2

V-

V+

+

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Gain = 165:1

Gain = 100:1

R5441

1

2

402

MF-LF

1/16W

1%

2.0K

XW5425

1

2

SM

XW5426

1

2

SM

XW5445

1

2

SM

XW5446

1

2

SM

XW5435

1

2

SM

XW5436

1

2

SM

R5410

1 2

10

1/16W MF-LF

1%

402

C5410

1

2

10% 16V X5R 402

0.1UF

49

C5412

1

2

0.001UF

CERM

402

10% 50V

R5412

1

2

402

1% 1/16W MF-LF

100K

U5410

3

2

6

1

8

5

4

7

CRITICAL

INA326EA-250

MSOP

R5411

1

2

MF-LF 402

1/16W

1%

2.0K

59

R5445

1 2

CRITICAL

0.002

1206

1/4W

1%

MF-LF

C5400

1 2

470PF

50V

10%

402

CERM

R5400

1 2

1/16W

1%

402

MF-LF

1M

C5401

1

2

10V

20% 402

CERM

0.1UF

R5402

1 2

40.2K

1/16W

402

1%

MF-LF

C5403

1

2

10V

20%

CERM

402

0.1UF

NO STUFF

U5400

3

4

1

5

2

CRITICAL

SOT23-5

LMV2011MF

R5404

1 2

1/16W

1%

402

MF-LF

1M

C5405

12

470PF

50V

10%

402

CERM

R5403

1 2

1/16W

402

40.2K

1%

MF-LF

C5404

1

2

402

CERM

NO STUFF

10V

20%

0.1UF

49

R5420

1 2

402

1%

MF-LF

1/16W

10

C5420

1

2

0.1UF

402

X5R

16V

10%

C5422

1

2

50V

10% 402

CERM

0.001UF

U5420

3

2

6

1

8

5

4

7

MSOP

INA326EA-250

CRITICAL

R5422

1

2

MF-LF

1/16W

1%

100K

402

C5426

1

2

22UF

20%

6.3V CERM-X5R 805-3

C5425

1

2

22UF

20%

6.3V CERM-X5R 805-3

R5421

1

2

1/16W

1%

402

MF-LF

2.0K

R5425

1 2

MF-LF

1%

1/4W 1206

0.002

CRITICAL

49

58

R5430

1 2

402

1%

MF-LF

1/16W

10

49

C5432

1

2

50V

10%

402

CERM

0.001UF

R5435

1 2

0.002

1/4W

MF-LF

1%

1206

CRITICAL

C5430

1

2

0.1UF

402

X5R

16V

10%

R5432

1

2

402

1% 1/16W MF-LF

165K

C5436

1

2

22UF

20%

6.3V CERM-X5R 805-3

U5430

3

2

6

1

8

5

4

7

CRITICAL

MSOP

INA326EA-250

C5435

1

2

22UF

20%

6.3V CERM-X5R 805-3

R5431

1

2

1% 1/16W

402

MF-LF

2.0K

R5440

1 2

MF-LF

10

1%

402

1/16W

49

C5442

1

2

10% 402

CERM

50V

0.001UF

C5440

1

2

0.1UF

402

X5R

16V

10%

C5446

1

2

CERM-X5R

22UF

20%

6.3V 805-3

C5445

1

2

CERM-X5R

22UF

20%

6.3V 805-3

U5440

3

2

6

1

8

5

4

7

MSOP

INA326EA-250

CRITICAL

R5442

1

2

MF-LF

1/16W

1%

402

100K

051-7225

14.0.0

8850

Current Sensing

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

PP1V8_S3_ISNS

PP1V8_S3

IMVP6_VO

CPUCOREISNS_N

P1V8ISNS_P

NBCORE_IOUT

PP3V3_S3

PPVCORE_S0_NB_R

PP3V3_S0_NBCOREISNS_VCC

MIN_NECK_WIDTH=0.2mm VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25mm

P1V25ISNS_P

P1V25ISNS_R1_P

GFXIMVP6_VO

GFXIMVP6_PHASE_VSUM

NBGFXCORE_IOUT

NBGFXISNS_R1_N

NBGFXISNS_R2

PP3V3_S0_NBGFXISNS_VCC

MIN_LINE_WIDTH=0.25mm VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2mm

NBGFXISNS_R1_P

P1V8_S3_IOUT

PP3V3_S0

NBCOREISNS_R2

PP1V05_S0

NBCOREISNS_N

NBCOREISNS_P

NBCOREISNS_R1_P

NBCOREISNS_R1_N

P1V8ISNS_R2

PP3V3_S3_P1V8ISNS_VCC

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.25mm VOLTAGE=3.3V

P1V8ISNS_R1_P

PP1V25_ENET

PP1V25_ENET_ISNS

P1V25ISNS_N

PP3V3_S3

P1V25_S0GPU_IOUT

P1V25ISNS_R2

PP3V3_S3_P1V25ISNS_VCC

MIN_NECK_WIDTH=0.2mm VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25mm

P1V25ISNS_R1_N

IMVP6_DROOP

CPUCOREISNS_P

CPUVCORE_IOUT

PP3V3_S0

P1V8ISNS_N

P1V8ISNS_R1_N

PP3V3_S0

87 77 75 74 65 59 58 57 52 51

50 48 47 46 42

32 31 30 29 28 27

87

26

77

25

75

16 21

24

74

23

65

19

59

58

57

52

51

50

48

47

46

42

61

32

46

31

30

27

29

78

26

78

28

57

23

57

27

54

21

54

26

53

19

53

25

87

51

18

51

24

62

50

14

50

23

57 57

48

22 13

48

21

21 38

38

21 12

38

19

18 32

36

18 11

36

16

16 31

8

16

13

10

57

8

13

8 8

87

7

8

87

8

87

8

7

8

BI BI BI BI

GND

VDD

SDATA

SCLK

THM*

ALERT*/

D+ D-

THM2*

BI

OUT

IN

VDD

SMDATA

SMCLK

GND

DP1 DN1

DP2 DN2

VDD

SMDATA

SMCLK

GND

DP1 DN1

DP2 DN2

BI BI

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Placement note:

to IC pins as possible

Keep 2 caps as close

(TG0H)

Place near GPU

GPU/Heat Pipe & Bottom Case Skin Thermal Sensor

Placement note:

518S0487

(TC0D)

GPU Die Thermal Sensor

Placement note:

Keep 2 caps as close to connectors as possible

Place on left side of fan cutout

518S0487

(Th2H)

(TG0T)

NB Thermal Diodes Not Used

(Reserved for CPU heatpipe sensor)

CPU T-Diode Thermal Sensor

(TG0P)

(Th1H)

Place U5550 near GPU

Placement note:

(Th0H)

(TC0P)

518S0487

Placement note:

C5500

1

2

0.1uF

CERM 402

20% 10V

R5500

1 2

47

MF-LF

5%

1/16W

402

C5510

1

2

NO STUFF

402

CERM

50V

18PF

5%

C5520

1

2

NO STUFF

5%

18PF

CERM 402

50V

J5510

3

4

1 2

BM02B-ACHKS-GAN-TF-LF-SN-M

CRITICAL

M-RT-SM

J5520

3

4

1 2

M-RT-SM

CRITICAL

BM02B-ACHKS-GAN-TF-LF-SN-M

R5552

1

2

GPU_TMP401

10K

5% MF-LF

1/16W 402

R5551

1

2

MF-LF

402

5%

10K

1/16W

GPU_TMP401

C5550

1

2

GPU_TMP401

16V

10%

402

X5R

0.1UF

C5560

1

2

GPU_TMP401

0.001UF

10%

402

CERM

50V

R5560

1 2

GPU_TMP401

499

1% 1/16W MF-LF

402

R5561

1 2

GPU_TMP401

402

MF-LF

1/16W

1%

499

U5550

6

3

2

5

8 7

4

1

GPU_TMP401

MSOP

TMP401

CRITICAL

J5590

3

4

1 2

CRITICAL

BM02B-ACHKS-GAN-TF-LF-SN-M

M-RT-SM

45 48 78 84

45 48 73 84

45 48 78 84

71 72 87

71 72

C5511

1

2

10% 50V

CERM

0.0022uF

402

U5500

2

4

1

3

5

8 7

6

CRITICAL

EMC1043-5

MSOP

C5521

1

2

402

0.0022uF

CERM

50V

10%

U5570

2

4

1

3

5

8 7

6

CRITICAL

EMC1043-5

MSOP

34 45 48 84

C5570

1

2

402

CERM

20%

0.1uF

10V

R5570

1 2

402

47

1/16W

5%

MF-LF

C5590

1

2

402

CERM

50V

10%

0.0022uF

C5580

1

2

402

CERM

50V

10%

470PF

10 87

10

SYNC_MASTER=(MASTER)

051-7225

14.0.0

8851

Thermal Sensors

SYNC_DATE=(MASTER)

GND GND

GND

SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA

PP3V3_S3

SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA

CPU_THERMD_N

CPU_THERMD_P

PP3V3_S0_CPUTHMSNS_R

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

CPUTHMSNS_D2_P

GPUTHMSNS_ALERT_L GPUTHMSNS_THM_L

PP3V3_S0

GPUTHMSNS_D_P

GPU_TDIODE_N

GPUTHMSNS_D_N

GPU_TDIODE_P

PP3V3_S0

CPUTHMSNS_D2_N

GND_CHASSIS_LEFTCLUTCH

RSFSTHMSNS_D_P

RSFSTHMSNS_D_N

HSTHMSNS_D_N

HSTHMSNS_D_P

PP3V3_S3_REMTHMSNS_R

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA

87

77

75

74

65

59

58

57

52

51

50

48

47

46

42

32

31

30

29

28

78

27

57

26

54

25

53

24

50

23

48

21

38

19

36

16

8

87

13

44

87

7

8

87

8

7

9

7

G

S D

G

S D

IN

OUT OUT

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

518S0369

Right Fan

Left Fan

518S0369

R5650

1

2

1/16W

47K

402

5%

MF-LF

R5655

1 2

1/16W

5%

MF-LF

402

47K

R5660

1

2

402

MF-LF

47K

5%

1/16W

R5665

1 2

402

47K

MF-LF

1/16W

5%

R5651

1

2

402

MF-LF

5%

1/16W

100K

Q5660

3

5

4

2N7002DW-X-F

SOT-363

R5661

1

2

100K

5%

MF-LF

402

1/16W

Q5660

6

2

1

SOT-363

2N7002DW-X-F

J5650

5

6

1 2 3 4

CRITICAL

SM04B-ACH

M-RT-SM

J5660

5

6

1 2 3 4

CRITICAL

SM04B-ACH

M-RT-SM

45

45 45

45

Fan Connectors

14.0.0

051-7225

8852

SYNC_MASTER=M76_MLB

SYNC_DATE=03/19/2007

SMC_FAN_1_CTL

SMC_FAN_1_TACH

SMC_FAN_0_CTL

SMC_FAN_0_TACH

PP3V3_S0

FAN_RT_PWM

PP5V_S0

FAN_RT_TACH

PP3V3_S0

FAN_LT_PWM

FAN_LT_TACH

PP5V_S0

87 87

77

75

74 74 65 65 59 59 58 58 57 57 52 52 51 51

50 50 48 48 47 47 46 46 42 42 32 32 31 31 30 30 29

78

29

78

28

76

28

76

27

65

27

65

26

59

26

59

25

58

25

58

24

57

24

57

23

52

23

52

21

47

21

47

19

42

19

42

16

27

16

27

13

8

13

8

7

8

7

V+

V-

G

D

S

IN

OUT

IN

OUT

IN

THRML

CAP

SW

LED

VIN

CTRL

PAD

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Right ALS Circuit

RTALS_OP_IN and RTALS_OP_COMP need to be matched

Keyboard LED Driver

Left ALS circuit has 1K series-R

Left ALS Filter

WF: This circuit does not use return, can tie cathode to GND on topcase flex

U5805

3

4

1

5

6

2

CRITICAL

SOT23-6-LF

MAX4236EUTT

C5805

1

2

0.1UF

10V

20% 402

CERM

R5806

1

2

1/16W

5%

402

MF-LF

120K

C5806

1

2

6.3V

20% 402

X5R

0.22UF

R5807

1

2

1/16W

1%

402

MF-LF

15.0K

R5808

1

2

1/16W

1%

402

MF-LF

1K

R5801

1 2

1K

1/16W

1%

402

MF-LF

PD5800

1

2

CRITICAL

TH

BS520EOF

R5800

1

2

1/16W

5%

402

MF-LF

5.1M

C5800

1

2

402

16V

20% CERM

0.01UF

Q5808

3

1

2

SOT23-LF

2N7002

7

45 78

45

R5810

1 2

1/16W

1%

402

MF-LF

4.53K

C5810

1

2

402

6.3V

20% X5R

0.22UF

45

C5830

1

2

0.22UF

X5R 402

20%

6.3V

R5830

1 2

3.48K

MF-LF

402

1%

1/16W

7

78

L5850

1 2

DE2812C-SM

10UH-0.58A

CRITICAL

C5850

1

2

CERM

603

20%

1UF

10V

R5852

1

2

402

10K

1/16W

5%

MF-LF

45

R5855

1

2

MF-LF

1%

10

1/16W 402

78

C5855

1

2

603

10% 25V

1UF

X5R

U5850

4

6

2

5

3

7

1

DFN

LT3491

CRITICAL

SYNC_DATE=03/19/2007

SYNC_MASTER=M76_MLB

14.0.0

051-7225

8853

ALS Support

KBDLED_CAP

PP5V_S3

KBDLED_SW

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.25 MM SWITCH_NODE=TRUE

LTALS_OUT

ALS_GAIN

RTALS_OP_COMP

PP3V3_S3

ALS_RT_OUT

ALS_RIGHT

GND_SMC_AVSS

RTALS_OP_IN

RTALS_PHOTODIODE

RTALS_GAIN_L

GND_SMC_AVSS

ALS_LEFT

KBDLED_ANODE

SMC_SYS_KBDLED

GND

78 57 54

78

51

57

50

49

48

46

38

53

44

36

49

8

46

7

45

CS*

SCL/SCLK

ADDR/SDI

MOT_ENABLE

ENABLE

VDD

X Y Z

FF/MOT

SDA/SDO

GND

IN

OUT OUT OUT

OUT

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

placed on board bottom-side:

Top-through View

placed on board top-side:

Desired orientation when

+Y+Y

+X

1

Package Top

+Z (dn)

1

+X

Alias SCL/SDA to GND if using analog outputs only

I2C addresses:

ADDR high => 0x32, 0x33

ADDR low => 0x30, 0x31

+Z (up)

Desired orientation when

APN:338S0354

C5900

1

2

10V

20% 402

CERM

0.1uF

C5902

1

2

0.033UF

10% 16V X5R 402

C5903

1

2

0.033UF

10% 16V X5R 402

U5900

3

2

6

11

10

12

5

4

11314

7 8 9

KXPS5-2050

LGA

CRITICAL

R5900

1

2

1/16W

5%

402

MF-LF

10K

45

R5901

1

2

SMS_MOT_EN

0

MF-LF 402

5% 1/16W

R5902

1

2

SMS_MOT_DIS

402

MF-LF

1/16W

5%

0

R5903

1

2

100K

402

MF-LF

1/16W

5%

9

45

45 48 84

C5901

1

2

X5R

10% 16V

0.033UF

402

SYNC_DATE=03/19/2007

SYNC_MASTER=M76_MLB

Sudden Motion Sensor (SMS)

051-7225

14.0.0

8854

SMS_X_AXIS

SMBUS_SMC_MGMT_SDA

SMS_Y_AXIS

SMBUS_SMC_MGMT_SCL

PP3V3_S3

SMC_SMS_INT

SMS_MOT_EN

SMS_Z_AXIS

SMS_ONOFF_L

78 57 53 51 50 48 38 36

8 7

SO

VDD

CE*

SCK

VSS

HOLD*

SI

WP*

OUT

IN

IN IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

C6100

1

2

402

0.1UF

10V

20% CERM

R6101

1

2

MF-LF

3.3K

5% 1/16W

402

R6100

1

2

3.3K

MF-LF

5%

1/16W

402

R6114

1 2

402

1/16W

5%

MF-LF

15

PLACEMENT_NOTE=Place R6114 within 12.7mm of U6100

U6100

1

7

6

5

2

8

4

3

CRITICAL

16MBIT

SOI

SST25VF016B

OMIT

24 82

R6190

1 2

PLACEMENT_NOTE=Place R6190 within 12.7mm of U2300

402

15

1/16W

5%

MF-LF

R6191

1 2

PLACEMENT_NOTE=Place R6191 within 12.7mm of U2300

15

1/16W

5%

MF-LF

402

24 82

R6193

1 2

402

15

1/16W

5%

MF-LF

PLACEMENT_NOTE=Place R6193 within 12.7mm of U2300

24 82

SPI BootROM

55 88

14.0.0

051-7225

SYNC_DATE=03/16/2007

SYNC_MASTER=T9_NOME

SPI_CE_R_L<0>

SPI_SCLK_R

SPI_CE_L<0>

SPI_SCLK

SPI_A_SO_R

SPI_WP_L

SPI_A_SI_R

SPI_HOLD_L

SPI_SO

SPI_SI_R

PP3V3_S5

87 75 65

60 57 48 46 28 27 26 25 24

82

8

OUT

BI BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Battery Connector (Digital Signals)

Left I/O Power Connector

518S0458

518S0369

7

45 46

7

45 48 84

7

45 48 84

J6900

1 2 3 4 5 6

CRITICAL

M-RT-SM

87438-0663

J6950

5

6

1 2 3 4

CRITICAL

SM04B-ACH

M-RT-SM

DZ6951

1

2

NO STUFF

8V-100PF

402

DZ6950

1

2

NO STUFF

8V-100PF

402

DZ6963

1

2

NO STUFF

402

8V-100PF

DZ6962

1

2

NO STUFF

402

8V-100PF

R6950

1

2

10

402

MF-LF

1/16W

5%

SYNC_DATE=09/09/2006

SYNC_MASTER=(M59_SYNC)

051-7225

56 88

14.0.0

PBus-In & Battery Connectors

SMBUS_SMC_BSA_SCL

SMC_BS_ALRT_L

SMBUS_SMC_BSA_SDA

VOLTAGE=0V

MIN_LINE_WIDTH=0.4 mm

GND_BATT

MIN_NECK_WIDTH=0.2 mm

PPBUS_G3H

74

63 62 61 60 59 58 57 49 40

8 7 7

D

SG

D

SG

D

SG

D

SG

D

SG

D

SG

D

SG

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

D

S

G

D

S

G

D

S

G

IN

D

SG

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

5V S0 FET

1.25V GPU FET

PBUS used for lower Rds(on)

1.8V GPU FET

3.3V GPU FET

3.3V S0 FET

5V S3 FET

1.25V S0 FET

1.8V S0 FET

3.3V S3 FET

Q7091

3

5

4

SSM6N15FE

SOT563

Q7081

3

5

4

SSM6N15FE

SOT563

Q7081

6

2

1

SSM6N15FE

SOT563

Q7051

3

5

4

SSM6N15FE

SOT563

Q7051

6

2

1

SSM6N15FE

SOT563

Q7096

3

5

4

SSM6N15FE

SOT563

Q7096

6

2

1

SSM6N15FE

SOT563

Q7002

6

2

1

2N7002DW-X-F

SOT-363

Q7012

6

2

1

2N7002DW-X-F

SOT-363

Q7002

3

5

4

SOT-363

2N7002DW-X-F

Q7012

3

5

4

SOT-363

2N7002DW-X-F

Q7072

3

1

2

2N7002

SOT23-LF

Q7020

1 5 8

4

2 3 6 7

CRITICAL

IRF7707PBF

TSSOP

Q7000

1

2

5

6

3

4

FDC638P

CRITICAL

SM-LF

Q7090

1 2 5 6

3

4

CRITICAL

SOT23

FDC637AN

Q7070

1

2

5

6

3

4

CRITICAL

FDC638P

SM-LF

Q7030

1

2

5

6

3

4

CRITICAL

FDC638P

SM-LF

Q7010

1

2

5

6

3

4

CRITICAL

FDC638P

SM-LF

Q7050

1 2 5 6

3

4

CRITICAL

SOT23

FDC637AN

Q7095

1 2 5 6

3

4

CRITICAL

SOT23

FDC637AN

Q7080

5

4

1 2 3

CRITICAL

LFPAK

RJK0301DPB

C7090

1

2

CERM-X5R 402

10%

0.15UF

6.3V

23 28 57 65

R7083

1 2

1/16W MF-LF

1%

402

499

C7080

1

2

402

10% CERM-X5R

6.3V

0.15UF

R7082

1 2

1/16W

1%

402

10K

MF-LF

R7080

1 2

15.0K

1% 1/16W MF-LF

402

C7083

1 2

0.1UF

402

CERM

20% 10V

R7081

1

2

1%

MF-LF

1/16W

402

69.8K

R7093

1 2

402

1%

499

MF-LF

1/16W

65 74

C7070

1 2

16V

0.01UF

CERM

402

10%

C7071

1

2

1UF

10% 10V X5R 402

R7070

1 2

402

MF-LF

1/16W

5%

100K

R7072

1

2

10K

5% 1/16W MF-LF

402

23 28 57 65

C7050

1

2

6.3V CERM-X5R

0.15UF

10%

402

R7053

1 2

MF-LF

1/16W

499

1%

402

R7098

1 2

1/16W MF-LF

1%

402

499

C7096

1

2

6.3V CERM-X5R

10%

402

0.15UF

R7092

1 2

1/16W

10K

402

1%

MF-LF

R7052

1 2

1%

10K

402

MF-LF

1/16W

C7053

1 2

10V

0.1UF

20%

402

CERM

R7050

1 2

1% 1/16W MF-LF

402

15.0K

R7051

1

2

MF-LF

1/16W

1%

69.8K

402

R7097

1 2

MF-LF

1/16W

10K

402

1%

R7096

1 2

402

1%

15.0K

MF-LF

1/16W

C7095

1 2

402

CERM

20% 10V

0.1UF

C7093

1 2

402

CERM

20%

0.1UF

10V

R7095

1

2

402

MF-LF

1/16W

1%

69.8K

7

25 35 36 40 45 49 57 62 65

7

25 35 36 40 45 49 57 62 65

C7001

1

2

10% 10V

0.068UF

CERM

402

C7000

1 2

16V

0.01UF

CERM

402

10%

R7091

1

2

402

69.8K

1% 1/16W MF-LF

R7002

1

2

10K

5% 1/16W MF-LF

402

R7000

1 2

47K

5%

402

MF-LF

1/16W

7

25 34 43 45

57 65

C7010

1 2

16V

0.01UF

CERM

402

10%

C7011

1

2

16V X5R

0.033UF

10%

402

R7010

1 2

402

MF-LF

1/16W

5%

100K

R7012

1

2

10K

5% 1/16W MF-LF

402

7

25 34 43 45

57 65

C7020

1 2

10%

402

CERM

0.01UF

16V

C7021

1

2

CERM

0.068UF

10% 10V

402

R7020

1 2

47K

5% 1/16W MF-LF

402

R7022

1

2

402

MF-LF

1/16W

5%

10K

R7090

1 2

15.0K

402

MF-LF

1/16W

1%

7

25 35 36 40

45 49

57 62

65

C7030

1 2

10%

402

CERM

0.01UF

16V

C7031

1

2

16V

0.033UF

10% X5R

402

R7030

1 2

100K

5% 1/16W MF-LF

402

R7032

1

2

402

MF-LF

1/16W

5%

10K

7

25 35 36 40

45 49

57 62

65

Q7091

6

2

1

SSM6N15FE

SOT563

SYNC_DATE=03/19/2007

SYNC_MASTER=M76_MLB

Power FETs

14.0.0

57

051-7225

88

PP5V_S3

PP5V_S5

P1V8S0_SS_RC

P1V8S0_EN_L

PP5V_S5

P1V8S0_EN_L_RC

P1V8S0_SS

PP1V8_S0

PP1V8_S3_ISNS

PM_SLP_S3_L

PP5V_S0

PP5V_S5

PP1V25_ENET_ISNS

PM_GPUP1V8FET_EN

PP1V25_S0

P1V25S0_SS

PP1V25_ENET_ISNS

P1V25GPU_EN_L_RC

P1V25GPU_SS

PP1V25_GPU

P3V3S0_SS

P1V25GPU_SS_RC

P1V8GPU_SS_RC

PPBUS_G3H PP5V_S5

PP5V_S5_P1V25S0FET

P1V25S0_SS_RC

P1V25S0_EN_L_RC

P1V25S0_EN_L

PM_SLP_S3_L

P1V25GPU_EN_L

EXTGPU_PWR_EN

P1V8GPU_EN_L

P1V8GPU_EN_L_RC

PM_S4_STATE_L

P5VS3_EN_L

P3V3S3_EN_L

PM_S4_STATE_L

P5VS0_EN_L

P3V3S0_EN_L

PM_SLP_S3_L

P3V3GPU_EN_L

EXTGPU_PWR_EN

P5VS0_SS

PP5V_S5

P5VS3_SS

PM_SLP_S3_L

PP3V3_S0

PP3V3_S5

PP3V3_GPU

PP3V3_S5

P3V3GPU_SS

PP3V3_S3

PP3V3_S5

P3V3S3_SS

PP1V8_S3

P1V8GPU_SS

PP1V8_GPU

87 77 75 74 65 59 58 52

51 50 48 47 46 42 32 31

87

30

75

74

29

65

74

78

74

63

74

28

60

65

76

65

62

65

27

57

78

57

63

65

63

61

63

26

55

77

55

54

55

62

59

62

60

62

25

48

76

48

53

48

78

61

58

61

59

61

24

46

74

46

51

46

87

77

53

60

52

60

65

77

58

60

23

28

73

28

50

28

62

73

49

57

50

47

57

27

74

56

57

21

27

72

27

48

27

50

70

46

43

65

21

42

43

26

71

49

43

19

26

71

26

38

26

38

69

44

27

22

18

27

57

21

57

68

40

27

16

25

65

25

36

25

32

68

8

9

19

16

8

9

50

19

50

66

8

9

13

24

48

24

8

24

31

67

7

8

7

8

7

8

9

8

7

8

IN

OUT

IN

OUT

IN

OUT OUT

IN

OUT

VID0

DPRSTP*

NC

VW

COMP

FB

FB2

RBIAS

VR_TT* NTC

VR_ON PGOOD

PSI*

RTN

VSEN

DFB

DROOP

VO

OCSET

VSUM

ISEN2

VID1

VID3 VID2

VID4

VID5

VID6

PGND2

VIN VDD

PVCC

LGATE2

PHASE2

UGATE2

ISEN1

PGND1

LGATE1

UGATE1

PHASE1

BOOT1 BOOT2

3V3

VDIFF

SOFT

DPRSLPVR

TPAD

GND

CLK_EN*

IMON

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

DPRSLPVR

DPRSTP*

(IMVP6_VSUM)

(ISL9504A)

(PGD_IN)

44A MAX CURRENT

(IMVP6_PHASE1)

These caps are for Q7100

CCM

Mode

DCM DCM

CCM

1-Phase 1-Phase

2-Phase

Operation

1-Phase

PSI*

1 0

0

1

0 0

10

1

0

1

(IMVP6_PHASE2)

(IMVP6_ISEN1)

(IMVP6_ISEN2)

(IMVP6_VO)

(GND)

(IMVP6_COMP)

(IMVP6_VW)

These caps are for Q7102

spot of reg circuit.

Place R7126 in hot

LAYOUT NOTE:

(IMVP6_NTC)

(GND_IMVP6_SGND)

(IMVP6_FB)

(GND_IMVP6_SGND)

C7100

1

2

402

50V

10%

0.0022UF

NO STUFF

CERM

R7100

1 2

402

1%

MF-LF

1/16W

10K

C7103

1 2

CERM

10V

0.22UF

10%

402

XW7104

12

SM

C7115

1

2

X5R 603

25V

0.22UF

20%

7

10 16 23 79

7

16 25 79

10 28

28

7

45

7 9

16 28

XW7102

12

SM

R7105

1 2

402

1%

MF-LF

1/16W

10K

C7104

1 2

CERM

10V

0.22UF

10%

402

C7102

1

2

0.0022UF

10% 50V

402

CERM

NO STUFF

C7127

1

2

0.22UF

25V X5R 603

20%

R7120

1 2

10

402

1%

MF-LF

1/16W

R7112

1 2

1%

10

MF-LF

1/16W

402

C7126

1

2

402

10V

1UF

10% X5R

R7121

1 2

1% 1/16W MF-LF

10

402

C7130

1

2

X5R

0.1uF

10% 402

16V

R7119

1 2

MF-LF

1%

402

1/16W

499

C7107

1

2

0.001UF

10% 50V

CERM

ISL9504B

402

R7110

1

2

6.81K

1% 1/16W MF-LF 402

ISL9504B

C7135

1

2

4.7uF

603

20%

6.3V CERM

C7110

1

2

10%

0.01uF

16V 402

CERM

R7113

1

2

1K

MF-LF

1/16W

1%

402

ISL9504B

R7109

1

2

1K

1% 1/16W MF-LF 402

ISL9504B

C7113

1

2

10%

X7R-CERM

220PF

50V 402

ISL9504B

R7114

1

2

97.6K

1%

MF-LF

1/16W

402

ISL9504B

R7104

1

2

1

5% 1/16W MF-LF 402

R7107

1

2

402

1

5% 1/16W MF-LF

C7116

1

2

0.001uF

NO STUFF

10% 50V

402

CERM

R7117

1 2

3.92K

402

1/16W MF-LF

1%

C7129

1

2

180pF

5%

402

50V CERM

R7118

1

2

1K

402

1/16W

1% MF-LF

R7130

1

2

2.61K

1/16W

1%

MF-LF

402

R7115

1

2

11K

1% MF-LF

1/16W 402

C7128

1

2

CERM-X5R

6.3V 402

10%

0.22UF

C7134

1

2

16V 402

10% X7R

0.015UF

R7122

1 2

5%

MF-LF

1/16W

0

402

C7131

1

2

0.01uF

16V 402

SIGNAL_MODEL=EMPTY

10%

CERM

C7132

1

2

NO STUFF

10%

0.01uF

16V 402

CERM

R7123

1 2

0

MF-LF

402

1/16W

5%

C7133

1

2

10%

0.01uF

16V 402

CERM

C7121

1

2

X5R 402

20%

6.3V

0.22UF

XW7100

1 2

SM

R7101

1

2

1/10W

1%

603

MF-LF

3.65K

R7106

1

2

1% MF-LF

603

1/10W

3.65K

L7100

1 2

0.36UH-27A

FDUE1030D-SM

CRITICAL

L7101

1 2

0.36UH-27A

FDUE1030D-SM

CRITICAL

C7196

1

2

10% 402

X5R

25V

0.1UF

7

12 79

7

12 79

7

12 79

7

12 79

7

12 79

7

12 79

7

12 79

C7106

1

2

0.001UF

10% 50V CERM 402

ISL9504B

C7114

1

2

470PF

10% 50V

402

CERM

ISL9504B

R7111

1

2

255

1/16W

1%

MF-LF

402

ISL9504B

C7105

1

2

X7R

0.015UF

10% 16V

402

R7116

1

2

402

MF-LF

1% 1/16W

13.3K

C7109

1

2

1UF

603

X5R

10% 25V

R7131

1

2

0603-LF

10KOHM-5%

CRITICAL

R7108

1

2

147K

1% MF-LF

402

1/16W

R7127

1

2

4.02K

MF-LF

1%

402

1/16W

R7197

1

2

2.0K

5% 1/16W

402

MF-LF

XW7103

1 2

SM

XW7101

1 2

SM

50 58

11 79

R7126

1

2

470K

402

CRITICAL

R7198

1 2

1/16W

0

MF-LF

5%

402

10 46 79

R7199

1

2

1/16W

68

MF-LF

5%

402

NO STUFF

U7100

48

36 26

47

10

17

45

46

16

11

12

21

3

24

23

32

30

25

6

8

33

29

1

34

28

2

31

4

15

7

49

35

27

22

13

37

38

39

40

41

42

43

20

18

44

5

14

19

9

ISL9504BCRZ

QFN

OMIT

Q7100

5

4

1 2 3

CRITICAL

RJK0305DPB

LFPAK

Q7103

5

4

1 2 3

CRITICAL

RJK0301DPB

LFPAK

Q7102

5

4

1 2 3

CRITICAL

RJK0305DPB

LFPAK

Q7105

5

4

1 2 3

LFPAK

CRITICAL

RJK0301DPB

Q7104

5

4

1 2 3

CRITICAL

RJK0301DPB

LFPAK

Q7101

5

4

1 2 3

CRITICAL

LFPAK

RJK0301DPB

C7117

1

2

CASE-D2-LF

22UF

25V

CRITICAL

20%

POLY

C7153

1

2

22UF

25V

CRITICAL

POLY

20%

CASE-D2-LF

C7155

1

2

CASE-D2-LF

25V

POLY

CRITICAL

20%

22UF

C7154

1

2

25V

10% X5R

603

1UF

49 65

I848I849

SYNC_DATE=01/23/2007

SYNC_MASTER=M76_MLB

8858

14.0.0

051-7225

IMVP6 CPU VCore Regulator

IMVP6_VR_TT_L

IMVP6_FB2

IMVP6_VDIFF

IMVP6_PHASE2

IMVP6_SOFT IMVP6_RBIAS

IMVP6_FB

GND_IMVP6_SGND

MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V

MIN_LINE_WIDTH=0.50 MM

PP5V_S0

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

PP3V3_S0_IMVP6_3V3

PPBUS_G3H

PP3V3_S0

IMVP6_NTC

CPU_DPRSTP_L

IMVP6_VID<5>

IMVP6_COMP

VOLTAGE=18.5V

MIN_LINE_WIDTH=0.25 MM

PPVIN_S5_IMVP6_VIN

MIN_NECK_WIDTH=0.2 MM

CPU_PROCHOT_L

VR_PWRGOOD_DELAY

IMVP_VR_ON

IMVP6_VID<0>

IMVP6_VID<2>

IMVP6_IMON

IMVP6_VID<1>

IMVP6_VID<4> IMVP6_VID<3>

PM_DPRSLPVR

IMVP6_NTC_R

CPU_PSI_L

MIN_NECK_WIDTH=0.2 MM

IMVP6_PHASE2

MIN_LINE_WIDTH=1.5 MM

MIN_NECK_WIDTH=0.2 MM

IMVP6_BOOT2

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

IMVP6_UGATE2

MIN_LINE_WIDTH=0.5 MM

IMVP6_LGATE2

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.25 MM

VR_PWRGD_CLKEN_L

CPU_VCCSENSE_P

CPU_VCCSENSE_N

IMVP6_VSUM2

PPVCORE_S0_CPU

IMVP6_VSUM1

IMVP6_COMP_RC

IMVP6_VDIFF_RC

IMVP6_VO_R

IMVP6_VO2

IMVP6_VO1

IMVP6_VSUM2

MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_VO2

IMVP6_VID<6>

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 MM

PP5V_S0_IMVP6_VDD

MIN_LINE_WIDTH=0.25 MM

IMVP6_VO1

MIN_NECK_WIDTH=0.25 MM

IMVP6_LGATE1

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

IMVP6_BOOT1

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

IMVP6_PHASE1

MIN_LINE_WIDTH=1.5 MM

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_FB2

IMVP6_VDIFF

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_RBIAS

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_SOFT

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_DFB

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_VO

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_FB

IMVP6_DROOP

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_OCSET

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_DROOP

IMVP6_DFB

IMVP_DPRSLPVR

IMVP6_VSEN_N

IMVP6_VSEN_P

IMVP6_OCSET

IMVP6_ISEN2

IMVP6_LGATE2

IMVP6_UGATE2

IMVP6_ISEN1

IMVP6_PHASE1

IMVP6_UGATE1

IMVP6_BOOT2

IMVP6_BOOT1

IMVP6_LGATE1

IMVP6_VO

IMVP6_VSUM

IMVP6_VW

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_VW

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_COMP

IMVP6_VSUM1

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

IMVP6_UGATE1

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

IMVP6_ISEN1

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

IMVP6_ISEN2

IMVP6_VSEN_N

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

IMVP6_VSEN_P

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

87 77 75 74 65

59 57 52 51 50 48

47 46 42 32 31

74

30

63

29

78

62

28

76

61

27

65

60

26

59

25

57

58

24

52

57

23

47

56

21

49

42

49

19

12

27

40

16

11

8

13

8

58

79

79 79

58

7

8

58

7

58

58 58

58

50

58

50

58

7

58

58 58

58

58 58

OUT

IN IN

IN

S

D

G

OUT OUT

OCSET

VO

DFB

COMP

VSUM

DROOP

RTN

VDIFF

PGND

VSS

THRM_PAD

VSEN

FDE

AF_EN

VID4

SOFT

FB

VW

VR_ON

VID3

VID2

PGOOD VID0

LGATE

UGATE

PHASE

BOOT

RBIAS

VIN

PVCC

VID1

VDD

IMON

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

IN RENDER SUSPEND STATE, AUDIO FILTER

(Q7250 limit)

10A max output

Vout according to VID

(GFXIMVP6_FDE)

(GFXIMVP6_AF_EN)

WHEN GFXIMVP6_FDE = 1

ENABLED WHEN GFXIMVP6_AF_EN = 1

(GFXIMVP6_VO)

(NB VID3)

(NB VID2)

100K pull-down on VR_EN per Crestline Issue #306022.

NOTE: Intel recommendation to stuff 30K pull-up and

ENTER DIODE-EMULATION-MODE IN ALL STATES

(NB VID1)

(NB VID0)

(GND)

(GFXIMVP6_VO) (GFXIMVP6_PHASE_VSUM)

VO=Sense-, PHASE_VSUM=Sense+

(VO/PHASE_VSUM offpage flags for current sensing)

(GFXIMVP6_AGND)

R7202

2 1

150K

MF-LF

1%

1/16W

402

C7203

12

10%

0.01uF

16V 402

CERM

R7251

1 2

402

1/16W

5%

MF-LF

0

C7256

1

2

10%

402

CERM

10V

0.22uF

R7222

1

2

6.98K

MF-LF

1%

1/16W

402

C7222

1

2

0.001UF

10% 50V

402

CERM

C7233

1

2

NO STUFF

470pF

50V

10% 402

CERM

C7221

1

2

0.001UF

10% 50V

402

CERM

C7220

1

2

10% 50V

0.0033UF

402

CERM

C7271

1 2

CERM

402

10% 50V

330pF

C7272

1

2

X5R 402

16V

10%

0.1uF

R7277

1 2

402

MF-LF

1%

1/16W

750

XW7200

1 2

SM

R7271

1

2

MF-LF 402

1/16W

5%

1K

R7232

1 2

0

MF-LF

5%

1/16W

402

R7220

1 2

0

MF-LF

5%

1/16W

402

PLACEMENT_NOTE=Place R7220 at NB

R7221

1 2

0

MF-LF

5%

1/16W

PLACEMENT_NOTE=Place R7221 at NB

402

C7223

1

2

10% 50V

402

CERM

0.001UF

R7250

1

2

1K

MF-LF

5%

1/16W

402

R7200

1 2

10

MF-LF

1%

402

1/16W

C7200

1

2

1uF

10V

10% 402

X5R

C7201

1

2

X5R 402

10% 10V

1uF

C7202

1

2

CERM 402

16V

0.01uF

10%

C7251

1

2

CERM 402

10% 50V

680pF

R7204

1

2

10K

1/16W

5%

NO STUFF

MF-LF

402

R7203

2 1

NO STUFF

20K

5%

1/16W

402

MF-LF

R7205

1

2

10K

MF-LF

5%

1/16W

402

R7206

1

2

MF-LF

10K

5% 1/16W

402

NO STUFF

R7207

1

2

10K

MF-LF

5% 1/16W

402

XW7201

1

2

SM

XW7202

1

2

SM

R7208

1 2

1

MF-LF

402

1/16W

5%

C7266

1

2

20%

6.3V

10UF

603

X5R

C7265

1

2

10UF

603

6.3V

20% X5R

R7270

1 2

402

1/16W

1%

MF-LF

15.0K

R7272

2

1

3.01K

402

1%

MF-LF

1/16W

L7200

1 2

CRITICAL

IHLP2525CZ-SM

0.47UH-26A

C7252

25V

22UF

20%

CASE-D2-LF

POLY

CRITICAL

C7253

1

2

10% 25V X5R

1UF

603

C7254

1

2

25V X5R

10%

1UF

603

R7230

1

2

158K

MF-LF

1% 1/16W

402

C7232

1

2

120PF

5% 50V

402

CERM

R7233

1

2

2.21K

MF-LF

1% 1/16W

402

R7231

1

2

3.65K

MF-LF

1% 1/16W

402

R7201

2

1

NO STUFF

MF-LF

5% 1/16W

402

0

C7230

12

CERM

820PF

50V

10%

402

C7231

1 2

680PF

50V

10%

402

CERM

9

77

9

59

9

59

9

59

9

59

9

16 59

R7291

1

2

5%

1/16W

402

MF-LF

22K

R7292

1

2

5%

22K

MF-LF

1/16W 402

R7294

1

2

5%

1/16W

402

MF-LF

22K

R7296

1

2

MF-LF

100K

5% 1/16W

402

R7295

1

2

MF-LF

30K

5% 1/16W

402

R7293

1

2

MF-LF

22K

5%

1/16W

402

9

59

Q7250

5

4

1 2 3

CRITICAL

PWRPK-1212-8

SI7114DN

Q7251

5

4

1 2 3

PWRPK-1212-8

CRITICAL

SI7108DNS

C7260

1

23

2.0V

330UF

10%

D2T

TANT

CRITICAL

R7260

1 2

1206

0.002

1/4W

MF-LF

1%

C7273

1

2

50V

68PF

5% CERM

402-1

50

U7200

30

17

5

11

10

6

32

28

21

3

20

31

19

22

1

9

2

33

18

16

7

23 24 25 26 27

14

12

29

8

15

13

4

CRITICAL

ISL6263B

QFN

IMVP6 NB Gfx Core Regulator

59 88

SYNC_MASTER=M76_MLB

051-7225

14.0.0

SYNC_DATE=03/19/2007

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_OCSET

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VO

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_DFB

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_COMP

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VSUM

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_DROOP

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VSEN_N

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VDIFF_R

VOLTAGE=0V

GND_GFXIMVP6_AGND

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VSEN_P

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GFXIMVP6_FDE

GFXIMVP6_AF_EN

GFXIMVP6_VID<4>

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_SOFT

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_FB

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VW

MIN_LINE_WIDTH=0.3MM

GFX_VR_EN

GFXIMVP6_VID<3>

GFXIMVP6_VID<2>

PM_ALL_NBGFX_PGOOD

GFXIMVP6_LGATE

MIN_NECK_WIDTH=0.3MM

MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.3MM

MIN_LINE_WIDTH=0.6MM

GFXIMVP6_UGATE

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_PHASE

MIN_LINE_WIDTH=0.6MM SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_BOOT

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_RBIAS

GFXIMVP6_VIN

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM

PP5V_S0_GFXIMVP6_PVCC

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VID<1>

MIN_NECK_WIDTH=0.2MM VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM

PP5V_S0_GFXIMVP6_VDD

GFXIMVP6_IMON

PP3V3_S0

GFXIMVP6_PHASE_VSUM

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.3MM

GFXIMVP6_VID<3>

GFX_VR_EN

GFXIMVP6_VID<4>

GFXIMVP6_VID<2>

GFXIMVP6_VID<1>

PPBUS_G3H

PP3V3_S0

MIN_NECK_WIDTH=0.3MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_BOOT_RC

PPVCORE_S0_NB_GFX

GFXIMVP6_VDIFF

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.3MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_COMP_RC

MIN_NECK_WIDTH=0.3MM

GFXIMVP6_VDIFF_RC

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.3MM

PP5V_S0

MIN_NECK_WIDTH=0.3MM VOLTAGE=1.0V

MIN_LINE_WIDTH=0.6MM

PPVCORE_S0_NBGFXSENSE_R

PPVCORE_S0_NB_GFX

GFXIMVP6_VID<0>

87

77

75

74

65

59

58

57

52

51

50

48

47

46

42

32

31

30

29

74

29

28

63

28

78

27

62

27

76

26

61

26

65

25

60

25

58

24

58

24

57

23

57

23

52

21

56

21

59

47

59

19

49

19

22

42

22

59

16

40

16

18

27

18

59

16

59

13

8

13

8

59

87

9

8

7

8

7

9

GND

THRML_PAD

SKIPSEL TONSEL

V5FILT

VIN

VREG5

VREG3

VREF2

EN5 EN3

VBST2

DRVH2

LL2

CS2

DRVL2

VO2

PGND2

COMP2

VFB2

PGOOD2

EN2

DRVH1

LL1

DRVL1

CS1

VO1

PGND1

VFB1 COMP1

PGOOD1

EN1

VBST1

SYM (3 OF 3)

IN

OUT OUT

IN

S

D

G

S

D

G

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

100mA max load when EN5 high

50uA max load when EN5 & EN3 high

TPS51120 LDO/Buffer outputs

(Available for system use)

Vout = 3.3V

(L7360 limit)

EN3 can float or tie to VREG5 for automatic 3.3V LDO enable

NOTE: EN5 can float or tie to VIN for automatic 5V LDO enable

When both are low TPS51120 VIN current drops from 100-150uA to 10-20uA.

5.5A max output

(L7320 limit)

Vout = 5.0V

3.3V Fixed

5V Fixed

8A max output

C7300

1

2

1UF

25V 603

X5R

10%

L7360

1 2

4.7UH

IHLP

CRITICAL

C7341

1

2

1UF

603

X5R

10% 25V

C7364

1

2

50V

0.1UF

10%

603-1

X7R

C7390

1

2

20%

6.3V

10UF

603

X5R

C7324

1

2

50V

10%

603-1

X7R

0.1UF

C7352

1

2

6.3V POLY

CRITICAL

20%

330UF

D3L

C7350

1

2

20%

CERM

10V

10UF

805-2

C7351

1

2

CERM

20% 10V

10UF

805-2

XW7300

1 2

SM

C7392

1

2

20% POLY

CRITICAL

CASE-B2

150UF

6.3V

C7340

1

2

CRITICAL

CASE-D2-LF

22UF

25V

20%

POLY

C7381

1

2

25V

1UF

603

X5R

10%

C7380

1

2

CASE-D2-LF

25V

22UF

POLY

20%

CRITICAL

L7320

1 2

CRITICAL

IHLP2525CZ-SM

2.2UH-14A

U7300

2 7

23 18

27

14

25 16

29 12

10

9

5

26 15

24 17

30 11

32

33

31

20

28 13

3 6

22

1 8

4

19

21

TPS51120

LLP

CRITICAL

R7325

1

2

1% MF-LF

402

1/16W

4.22K

R7365

1

2

1%

1/16W

402

MF-LF

3.57K

C7303

1

2

603

X5R

10UF

20%

6.3V

C7305

1

2

603

X5R

6.3V

20%

10UF

R7306

1

2

MF-LF

5%

4.7

402

1/16W

C7306

1

2

1UF

X5R

10V

10%

402

60 65

45 46 60

60 65

C7302

1

2

0.001UF

20% 50V

CERM

402

Q7360

5

4

1 2 3

SI7114DN

PWRPK-1212-8

CRITICAL

Q7365

5

4

1 2 3

SI7108DNS

PWRPK-1212-8

CRITICAL

Q7320

5

4

123

SI7114DN

CRITICAL

PWRPK-1212-8

Q7325

5

4

123

PWRPK-1212-8

SI7108DNS

CRITICAL

XW7360

1

2

SM

PLACEMENT_NOTE=Place XW7360 next to C7390.

XW7320

1

2

SM

PLACEMENT_NOTE=Place XW7320 next to C7350.

XW7325

1 2

SM

XW7365

1 2

SM

60 88

14.0.0

051-7225

SYNC_MASTER=M76_MLB

SYNC_DATE=03/19/2007

5V / 3.3V Power Supply

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P5VS5_VBST

PPBUS_G3H

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

P5VS5_LL

SWITCH_NODE=TRUE

P5VS5_CS

MIN_LINE_WIDTH=0.20 mm MIN_NECK_WIDTH=0.20 mm VOLTAGE=2V

PP2V0_S5_P5VP3V3_BUF

P5VP3V3_VREG3

P3V3S5_VBST

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=5V

PP5V_S5_P5VP3V3_V5FILT

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm GATE_NODE=TRUE

P5VS5_DRVH

P5VS5_VO

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GND_P5VS5_PGND

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P5VS5_DRVL

P3V3S5_VO

PP3V3_S5

PP5V_S5

P3V3S5_CS

PPBUS_G3H

MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm

P3V3S5_DRVH

MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

P3V3S5_DRVL

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

P3V3S5_LL

PPBUS_G3H

MIN_LINE_WIDTH=0.25 mm VOLTAGE=5V

PP5V_S5_P5VP3V3_LDO

MIN_NECK_WIDTH=0.20 mm

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GND_P3V3S5_PGND

PM_G2_EN

RSMRST_PWRGD

PM_G2_EN

VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm

GND_P5VP3V3_SGND

MIN_NECK_WIDTH=0.2 mm

74

87

74

74 63

75

63

63 62

65

62

61

57 74

61

61 60

55 65

60

60 59

48 63

59

59 58

46 62

58

58 57

28 61

57

57 56

27 57

56

56 49

26 43

49

49 40

25 27

40

8

24

9

8

8 7

8 8

7

OUT

IN

THRM_PAD

VFB

TRIP

VOUT

EN_PSV

GND

PGND

V5DRV

V5FILT

DRVL

DRVH

LL

TON

VBST

PGOOD

SYM (2 OF 2)

S

D

G

OUT

IN

THRM_PAD

VFB

TRIP

VOUT

EN_PSV

GND

PGND

V5DRV

V5FILT

DRVL

DRVH

LL

TON

VBST

PGOOD

SYM (2 OF 2)

S

D

G

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

<Ra>

Vout = 0.75V * (1 + Ra / Rb)

(P1V25ENET_VFB)

Vout = 1.051V 10A max output (L7460? limit)

8A max output

<Rb>

Vout = 0.75V * (1 + Ra / Rb)

<Rb>

(L7410? limit)

(GND)

(P1V25ENET_TON)

Vout = 1.2496V

(P1V05S0_VFB)

<Ra>

(P1V05S0_TON)

R7405

1

2

6.81K

1/16W 402

MF-LF

1%

65

7

36 65

R7401

1 2

200

MF-LF

1%

1/16W

402

XW7400

1

2

SM

U7400

13

9

1

7

12

8

6

15

2

11

10

4

14

5

3

QFN

CRITICAL

TPS51117RGY_QFN14

C7401

1

2

X5R 603

10%

2.2UF

16V

R7420

1

2

MF-LF

402

1/16W

5%

0

C7400

1

2

402

X5R

10% 10V

1UF

Q7411

5

4

1 2 3

PWRPK-1212-8

CRITICAL

SI7108DNS

C7420

1

2

10V

0.1UF

CERM

402

20%

Q7410

5

4

1 2 3

CRITICAL

PWRPK-1212-8

SI7114DN

L7410

1 2

2.2UH-14A

CRITICAL

IHLP2525CZ-SM

R7421

1

2

1/16W MF-LF 402

1%

200K

C7440

1

2

CASE-D2-LF

22UF

25V

20%

POLY

CRITICAL

C7445

1

2

X5R

25V

1UF

10%

603

R7431

1

2

402

MF-LF

1/16W

1%

12.1K

R7430

1

2

402

MF-LF

1%

8.06K

1/16W

C7430

1

2

5% 402

CERM

NO STUFF

100PF

50V

XW7430

1

2

SM

PLACEMENT_NOTE=Place XW7430 close to C7415.

C7415

1

2

6.3V

20%

10UF

603

X5R

R7455

1

2

MF-LF

1%

402

1/16W

4.32K

7

63 65

R7451

1 2

200

1%

402

MF-LF

1/16W

XW7450

1

2

SM

U7450

13

9

1

7

12

8

6

15

2

11

10

4

14

5

3

TPS51117RGY_QFN14

QFN

CRITICAL

C7451

1

2

16V

2.2UF

10%

603

X5R

R7470

1

2

MF-LF

402

1/16W

5%

0

C7450

1

2

1UF

402

X5R

10V

10%

Q7461

5

4

1 2 3

PWRPK-1212-8

SI7108DNS

CRITICAL

C7470

1

2

10V

0.1UF

CERM

402

20%

Q7460

5

4

1 2 3

PWRPK-1212-8

SI7114DN

CRITICAL

L7460

1 2 IHLP2525CZ-SM

CRITICAL

1.0UH-22A

R7471

1

2

1/16W MF-LF

1%

200K

402

C7490

1

2

CASE-D2-LF

22UF

25V

20%

POLY

CRITICAL

C7495

1

2

X5R

25V

1UF

603

10%

R7481

1

2

402

MF-LF

1/16W

1%

14.0K

R7480

1

2

MF-LF

402

1%

1/16W

5.62K

C7480

1

2

100PF

NO STUFF

5% 50V

402

CERM

XW7480

1

2

SM

PLACEMENT_NOTE=Place XW7480 close to C7465.

C7465

1

2

X5R

20% 603

6.3V

10UF

C7410

POLY CASE-B2

20%

330UF

2.0V

CRITICAL

C7460

1

23

10%

CRITICAL

TANT D2T

330UF

2.0V

XW7401

1

2

SM

XW7451

1

2

SM

1.25V / 1.05V Power Supply

SYNC_MASTER=M76_MLB

051-7225

14.0.0

61

SYNC_DATE=03/12/2007

88

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

P1V05S0_BOOT_R

P1V05S0_VFB

PP1V05_S0

PP5V_S5

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_S5_P1V25ENET_V5FILT

P1V25ENET_TRIP

PP5V_S5

P1V5P1V05S0_PGOOD

MIN_NECK_WIDTH=0.2 mm

P1V05S0_VBST

MIN_LINE_WIDTH=0.25 mm

P1V05S0_TON

MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm

P1V05S0_DRVH

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

P1V25ENET_LL

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

P1V25ENET_DRVL

GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm

PPBUS_G3H

P1V05S0_TRIP

PPBUS_G3H

PM_ENET_EN TP_P1V25ENET_PGOOD

MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

P1V25ENET_PGND

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm

P1V05S0_PGND

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_S5_P1V05S0_V5FILT

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE

P1V05S0_LL

MIN_LINE_WIDTH=0.6 mm

GND_P1V05S0_SGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

PP1V05_S0_VDDQSNS

PP1V05_S0

MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm

P1V05S0_DRVL

PM_SLP_S3_DELAY_L

PP1V25_ENET_VDDQSNS

PP1V25_ENET

GND_P1V25ENET_SGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

P1V25ENET_VFB

PP1V25_ENET

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

P1V25ENET_BOOT_R

GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

P1V25ENET_DRVH

MIN_NECK_WIDTH=0.2 mm

P1V25ENET_VBST

MIN_LINE_WIDTH=0.25 mm

P1V25ENET_TON

61

50

46

30

74

30

27

63

27

26

74

62

26

23

65

61

23

21

63

60

21

19

62

59

19

18

61

58

18

14

60

57

14

13

57

56

13

12

43

49

12

61

11

27

40

11

50

10

9

8

10

35

8

7

8

MODE

VDDQSNS

COMP

NC0 NC1

VTTSNS

VTT

VTTREF

PGOOD

S3 S5

VTTGND

THRM_PAD

GND

CS_GND

PGND

CS

LL

DRVL

DRVH

VDDQSET

VBST

VLDOINV5FILT

V5IN

SYM (2 OF 2)

IN IN

OUT

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(P1V8S3_DRVH)

(P1V8S3_DRVL)

(P1V8S3_CSGND)

Vout = 0.75V * (1 + Ra / Rb)

<Ra>

<Rb>

(P1V8S3_FB)

C7545

Vout = VDDQSNS/2

10mA max load

NC

VTT Enable

Place next to

(P1V8S3_VDDQSNS)

(P1V8S3_LL)

Vout = VTTREF

VDDQ/VTTREF Enable

Place at pin 23

(L7530 limit)

18A max output

Vout = 1.80V or 1.825V

VDDQ PGOOD

C7525

50V

10%

805

X7R-CERM

0.1UF

R7520

1

2

MF-LF 402

1/16W

21.5K

0.1%

P1V8S3_1V825

R7521

1

2

402

15.0K

1/16W MF-LF

0.1%

C7540

1

2

CRITICAL

20%

POLY

2.5V

CASE-C2

330UF

C7541

1

2

CRITICAL 330UF

2.5V POLY CASE-C2

20%

C7532

1

2

10%

603

1UF

X5R

25V

C7520

1

2

NO STUFF

402

50V

CERM

5%

100PF

U7500

6

16

17

21

19

3

20

4

7

12

18

13

10 11

25

14

15

22

9

8

23

24

1

5

2

TPS51116

QFN

CRITICAL

C7505

1

2

X5R

10% 10V

1UF

402

R7505

1 2

402

MF-LF

5%

4.7

1/16W

C7561

1

2

805-3

CERM-X5R

22UF

6.3V

20%

CRITICAL

C7560

1

2

805-3

CERM-X5R

22UF

6.3V

20%

CRITICAL

XW7560

1 2

SM

XW7535

1 2

SM

C7550

1

2

0.033UF

10% 402

X5R

16V

7

25 35 36 40 45 49 57 65

C7500

1

2

10V

20%

CERM

10UF

805-2

65

R7510

1

2

6.81K

1/16W

1%

402

MF-LF

65

C7530

1

2

CRITICAL

22UF

25V

20%

CASE-D2-LF

POLY

C7531

1

2

CRITICAL

20%

22UF

POLY

CASE-D2-LF

25V

Q7530

5

4

1 2 3

CRITICAL

LFPAK

RJK0305DPB

Q7535

5

4

1 2 3

CRITICAL

LFPAK

RJK0303DPB

L7530

1 2 IHLP4040DZ11-SM

CRITICAL

1.0UH-20A

C7545

1

2

6.3V

10UF

20% 603

X5R

Q7536

5

4

1 2 3

CRITICAL

RJK0303DPB

LFPAK

XW7545

1

2

SM

C7501

1

2

6.3V X5R 603

20%

10UF

XW7500

1

2

SM

R7526

1 2

1

1/10W

603

5%

MF-LF

SYNC_DATE=03/19/2007

14.0.0

8862

051-7225

1.8V DDR2 Supply

SYNC_MASTER=M76_MLB

RES,MTL FILM,21K,0.1,0402,SM,LF

103S0192 P1V8S3_1V8CRITICAL

1

R7520

PP5V_S5

PP0V9_S3_MEM_VREF

MIN_NECK_WIDTH=0.2 mm

P1V8S3_DRVH_R

MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE

PPBUS_G3H

PM_SLP_S3_L P1V8S3_EN TP_P1V8S3_PGOOD

PP0V9_S0

P1V8S3_CS

PP1V8_S3

DDRREG_VTTSNS

PP1V8_S3

GND_P1V8DDRREG_SGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

P1V8S3_VDDQSNS

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

P1V8S3_DRVL

GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P1V8S3_DRVH

GATE_NODE=TRUE

P1V8S3_FB

P1V8S3_CSGND

PP5V_S5_P1V8DDRREG_V5FILT

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

P1V8S3_LL

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P1V8S3_VBST

74 63

74

61

65

60

63

59

87

61

58

62

60

57

56

50

43

32

49

38

27

31

40

32

9

16

8

33

31

8

7

8

IN

OUT

THRM_PAD

VFB

TRIP

VOUT

EN_PSV

GND

PGND

V5DRV

V5FILT

DRVL

DRVH

LL

TON

VBST

PGOOD

SYM (2 OF 2)

S

D

G

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Vout = 1.50V 8A max output (L7620 limit)

(GND)

(P1V5S0_TON)

Vout = 0.75V * (1 + Ra / Rb)

(P1V5S0_VFB)

<Rb>

<Ra>

C7610

1

2

CERM

5%

402

50V

100PF

NO STUFF

R7615

1

2

0

5%

402

MF-LF

1/16W

C7615

1

2

20%

402

CERM

0.1UF

10V

C7620

1

2

CRITICAL

POLY

20% 25V

22UF

CASE-D2-LF

C7632

1

2

POLY

20%

CASE-D2E-LF

330UF

2.5V

CRITICAL

61 65

7

61 65

C7600

1

2

402

X5R

1UF

10V

10%

R7601

1 2

1%

402

MF-LF

1/16W

200

C7601

1

2

X5R 603

10%

2.2UF

16V

R7619

1

2

200K

1%

402

MF-LF

1/16W

U7600

13

9

1

7

12

8

6

15

2

11

10

4

14

5

3

CRITICAL

TPS51117RGY_QFN14

QFN

C7621

1

2

603

10%

1UF

25V X5R

Q7620

5

4

1 2 3

CRITICAL

SI7114DN

PWRPK-1212-8

Q7625

5

4

1 2 3

CRITICAL

PWRPK-1212-8

SI7108DNS

XW7620

1

2

PLACEMENT_NOTE=Place XW7620 close to L7620.

SM

XW7600

1 2

SM

R7605

1

2

1/16W 402

1% MF-LF

6.04K

C7630

1

2

6.3V

20%

10UF

X5R 603

R7610

1

2

MF-LF

402

10K

1%

1/16W

R7611

1

2

1%

10K

402

MF-LF

1/16W

L7620

1 2

CRITICAL

IHLP2525CZ-SM

1.0UH-22A

1.5V Power Supply

SYNC_DATE=03/12/2007

SYNC_MASTER=M76_MLB

8863

051-7225

14.0.0

P1V5S0_DRVL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

P1V5S0_VFB

PP5V_S5

P1V5S0_TON P1V5S0_VBST

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

P1V5S0_DRVH

GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

P1V5S0_BOOT_R

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PM_SLP_S3_DELAY_L

P1V5S0_LL

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

PPBUS_G3H

P1V5P1V05S0_PGOOD

MIN_NECK_WIDTH=0.2 mm

PP5V_S5_P1V5S0_V5FILT

MIN_LINE_WIDTH=0.6 mm VOLTAGE=5V

GND_P1V5S0_SGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

PP1V5_S0

P1V5S0_TRIP

PP1V5_S0

PP1V5_S0_VDDQSNS

74 62

74

61

65

60

87

62

59

63

61

58

34

60

57

27

57

56

26

43

49

22

27

40

12

9

8

11

8

7

8

OUT

IN

NR

NC

THRML

EN

GND

PAD

FB

BIAS

SW

SHDN*

NC

VIN

BOOST

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

200mA max output

1.95V FW PHY Supply

VP short to keep PHY powered.

Backup power in case of FW bus

NC

3.3V FW PHY Supply

Vout = 1.25V * (1 + Ra / Rb)

Vout = 3.316V

<Rb>

NC

<Ra>

(Switcher limit)

C7722

1

2

4V

20% 402

X5R

2.2uF

C7721

1

2

16V

10% 402

CERM

0.01uF

C7720

1

2

6.3V

10% 402

CERM

1uF

U7720

4

3

6

5

2

1

7

SON

TPS799195

CRITICAL

R7710

1

2

402

MF-LF

1/16W

1%

324K

R7711

1

2

1/16W

1%

402

MF-LF

196K

C7710

1

2

50V

5%

402

CERM

22pF

C7705

1

2

402

20% X5R

6.3V

0.22uF

C7700

1

2

50V

X7R-CERM

10%

1206

4.7UF

U7700

7

6

8

4

2

1 5

3

CRITICAL

TSOT23-8

LT3470

D7700

1

2

3

SMD20E40C-X-F

SC-59

L7700

1 2

33uH

CDPH4D19F-SM

CRITICAL

C7701

1

2

CRITICAL

6.3V

20%

22UF

CERM-X5R 805-3

SYNC_MASTER=M76_MLB

FW PHY Power Supplies

SYNC_DATE=03/19/2007

051-7225

14.0.0

8864

PP3V3_FW

P3V3FW_FB

P3V3FW_BOOST

PPBUS_FW_FWPWRSW_F

PP3V3_FW

PPVP_FW

VOLTAGE=33V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPVIN_FW_P3V3FW

P3V3FW_SW

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

P1V95FW_NR

PP1V95_FW

64

41

40

39

40

39

8

FB

BIAS

SW

SHDN*

NC

VIN

BOOST

GND

OUT OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

IN

OUT

OUT OUT

IN

OUT

VPG

V2

V4

V3

VREF RST*

CRT

THRM_PAD

GND

PBR*

V1

OUT OUT

G

D

S

OUT

G

D

S

Y

B

A

Y

B

A

IN

G

D

S

OUT

G

D

S

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(PM_ENET_EN)

TPS51117 PGOOD does not deassert while GPU VIDs are changing

SB GPIO has ability to force all GPU rails off

(PM_SLP_S3_L)

up in the following order:

2) 3.3V

3) Vcore

4) 1.8V

(EXTGPU_PWR_EN)

R7853 acts as pull-up for open-drain GPIO.

supplies and PGOOD revalidate

GPU core voltage.

To CPU IMVP6

Reports when 1.5V S0 and 1.05V S0 are in regulation

1.5V / 1.05V PWRGD Circuit

PM_SLP_S3_LPM_SLP_S4_L

SMC_PM_G2_ENABLE

Run (S0)

Supply needs to guarantee 3.31V delivered to SMC VRef generator

State

Soft-Off (S5)

Sleep (S3)

Battery Off (G3Hot)

0

1

1 1

0 0

1

0

1

Vout = 3.425

<Rb>

NC

Vout = 1.25V * (1 + Ra / Rb)

Unused PGOOD Signals

<Ra>

3.425V "G3Hot" Supply

Does not include GFX rails

NC

Trst = 4.6ms/nF Trst = 216ms

1) 1.2V

G84M GPU requires rails to come

TPS51117 PGOOD threshold 92.5-97.5% (1.36 - 1.46V)

TPS51117 PGOOD threshold 92.5-97.5% (0.98 - 1.02V)

Fast wake glitch filter. Should

PP1V2_GPU needs to ramp

LTC2900 typical threshold is 93.5% (4.675V, 3.086V, 1.685V, 1.120V)

(Switcher limit)

200mA max output

not be necessary to stuff if GPU

before 99ms SMC timer expires.

first via RC control

Need to ensure that

(PM_S4_STATE_L)

NOTE: 0.9V/2.5V is not checked!

Other S0 Rails PWRGD Circuit

Power Control Signals

U7800

7

6

8

4

2

1 5

3

CRITICAL

TSOT23-8

LT3470

C7800

1

2

10UF

X5R

1206-1

10% 25V

C7815

1

2

6.3V

20%

22UF

CERM-X5R 805-3

R7811

1

2

200K

MF-LF 402

1% 1/16W

R7865

1

2

402

5%

MF-LF

1/16W

10K

7

25 35

36

40 45 49 57 62 65

7

25 35

36 40 45 49 57

62 65

61 63 65

7

25 35

36 40 45 49 57

62 65

7

25 35

36 40 45 49 57

62 65

7

25 35

36 40 45 49 57

62 65

61 63 65

34 65

57 65 74

7

25 34 43 45 57 65

7

25 34 43 45 57 65

62 65

U7880

3

2

1

4

5

SC70

MC74VHC1G08

7

25 34 43 45 57 65

7

25 34 43 45 57 65

60 65

7

25 35

36

40 45 49 57 62

65

7

36 61 65

C7880

1

2

10V

20% 402

CERM

0.1UF

7

36 61 65

23 28 57 65

49 58

C7853

1

2

NO STUFF

0.047UF

16V

10% 402

CERM

7

36 61 65

60 65

7

61 63 65

60 65

R7866

1

2

MF-LF 402

5% 1/16W

0

ISL9504A

C7873

1

2

0.1UF

402

CERM

20% 10V

R7871

1

2

1% 1/16W

402

MF-LF

93.1K

R7870

1

2

1% MF-LF

402

1/16W

9.53K

U7870

3

6

5

4

11

2

10

1

9

7

8

CRITICAL

DFN

LTC2900

C7875

1

2

CERM

402

10%

0.047UF

16V

R7874

1

2

402

100K

1/16W

1% MF-LF

R7873

1

2

124K

1/16W

1%

402

MF-LF

C7872

12

0.1UF

20% 10V

CERM

402

R7875

1

2

1/16W MF-LF 402

5%

10K

C7871

1

2

CERM

10V 402

20%

0.1UF

C7870

1

2

0.1uF

10V

20%

CERM

402

23 28 57 65

Q7851

3

5

4

2N7002DW-X-F

SOT-363

65 72 74

Q7851

6

2

1

SOT-363

2N7002DW-X-F

R7852

1

2

100K

402

5% 1/16W MF-LF

R7854

1

2

10K

402

5% 1/16W MF-LF

U7850

3

2

1

4

5

MC74VHC1G09

SC70

R7859

1

2

10K

MF-LF

1/16W

402

5%

R7855

1 2

402

5%

MF-LF

1/16W

10K

C7855

1

2

6.3V

0.47UF

10%

402

CERM-X5R

C7859

1

2

0.047UF

16V

10% 402

CERM

NO STUFF

U7858

3

2

1

4

5

MC74VHC1G09

SC70

R7860

12

NO STUFF

1/16W MF-LF

5%

402

0

7

61 63 65

R7851

1

2

5%

MF-LF

1/16W

402

100K

R7850

1

2

402

MF-LF

5%

1/16W

10K

Q7850

6

2

1

SOT-363

2N7002DW-X-F

28 45 46

R7810

1

2

348K

MF-LF 402

1% 1/16W

L7810

1 2

CRITICAL

33uH

CDPH4D19F-SM

Q7850

3

5

4

2N7002DW-X-F

SOT-363

57 65 74

C7810

1

2

22pF

CERM

402

5%

50V

R7856

1

2

100K

MF-LF

5%

402

1/16W

7

25 35 36 40 45 49

57 62 65

R7857

1

2

10K

MF-LF

402

5%

1/16W

7

25 34 43 45 57 65

R7858

1

2

100K

MF-LF

402

1/16W

5%

45

C7805

1

2

0.22uF

X5R 402

20%

6.3V

R7853

1

2

1/16W

5%

402

MF-LF

10K

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

14.0.0

65 88

051-7225

3.425V G3Hot Supply & Power Control

PP3V42_G3H

SMC_PM_G2_EN

MAKE_BASE=TRUE

PM_G2_EN

MAKE_BASE=TRUE

PM_SLP_S3_LS5V

PM_SLP_S3_DELAY_L

MAKE_BASE=TRUE

PP3V3_S5

PM_SLP_S3_L

PM_ENET_EN

EXTGPU_PWR_EN

PP1V8_S0

PM_SLP_S3_L

EXTGPU_PWR_EN

P1V5P1V05S0_PGOOD

MAKE_BASE=TRUE

P1V5P1V05S0_PGOOD

IMVP6_IMON

S0PGOOD_CRT

S0PGOOD_VPG

PP5V_S0

PP1V25_S0

MAKE_BASE=TRUE

TP_P1V8S3_PGOOD

TP_P1V25ENET_PGOOD

MAKE_BASE=TRUE

ALL_SYS_PWRGD

PM_ENET_EN

TP_P1V8S3_PGOOD

PM_S4_STATE_L

TP_P1V25ENET_PGOOD

P3V42G3H_FB

P3V42G3H_SW

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE

P3V42G3H5_BOOST

PPDCIN_G3H

PM_S4_STATE_L

PP3V3_S5

PP3V3_S0

S0PGOOD_VREF

S0PGOOD_P1V2_DIV

PM_GPUVCORE_EN

MAKE_BASE=TRUE

PM_GPUVCORE_EN

PM_GPUP1V8FET_ENPM_GPUP1V8FET_EN

MAKE_BASE=TRUE

PVCOREGPU_EN_L

PP3V3_GPU

PM_SLP_S3_DELAY_L PM_SLP_S3_DELAY_L

PM_SLP_S3_L

PM_GPUP1V8FET_EN

PP5V_S5

PM_SLP_S3_L

PP3V3_S0

PM_SLP_S3_LS5V

PM_SLP_S3_L

MAKE_BASE=TRUE

PM_SLP_S3_L

PM_ENET_EN

MAKE_BASE=TRUE

P1V8S3_EN

PM_S4_STATE_L PM_S4_STATE_L

MAKE_BASE=TRUE

P1V8S3_EN

MAKE_BASE=TRUE

PM_S4_STATE_L

EXTGPU_PWR_EN

MAKE_BASE=TRUE

PP3V42_G3H

S0PGOOD_PWROK

PM_G2_EN

PM_G2_EN PM_G2_EN

87

77

75

74

65

59

58

57

52

51

50

48

47

46

42

32

87

31

75

30

65

29

78

60

78

60

28

78

65

57

76

57

27

74

27

65

48

55

59

55

26

77 63

26

48

47

48

58

48

25

76 62

25

47

46

57

46

24

74 61

24

46

45

28

52

57

28

23

73 60

23

45

43

27

47

27

21

72 57

21

43

34

26

65

57

42

26

19

71 43

19

34

28

25

57

22

27

21

25

16

74

57 27

16

28

8

65

24

28

19

8

19

65

34

24

13

65

48

9

13

65

8

7

60

34

8

23

8

7

8

62

61

62

61

8

57

8 8

8

62

7

OUT

PEX_TX0

PEX_TX0_L

PEX_RX4

PEX_RX0

PEX_TX1PEX_RX1

PEX_RX2 PEX_TX2

PEX_RX3 PEX_TX3

PEX_TX4

PEX_TX5PEX_RX5

PEX_TX6PEX_RX6

PEX_RX7 PEX_TX7

PEX_TX8PEX_RX8

PEX_TX9PEX_RX9

PEX_TX10PEX_RX10

PEX_TX11PEX_RX11

PEX_TX12PEX_RX12

PEX_TX13PEX_RX13

PEX_TX14PEX_RX14

PEX_TX15PEX_RX15

PEX_TSTCLK_OUTPEX_REFCLK

PEX_TX1_L

PEX_TX2_L

PEX_TX3_L

PEX_TX4_L

PEX_TX5_L

PEX_TX6_L

PEX_TX7_L

PEX_TX8_L

PEX_TX9_L

PEX_TX10_L

PEX_TX11_L

PEX_TX12_L

PEX_TX13_L

PEX_TX14_L

PEX_TX15_L

PEX_TSTCLK_OUT_L

PEX_RST_L

PEX_REFCLK_L

PEX_RX15_L

PEX_RX14_L

PEX_RX13_L

PEX_RX12_L

PEX_RX11_L

PEX_RX10_L

PEX_RX9_L

PEX_RX8_L

PEX_RX7_L

PEX_RX6_L

PEX_RX5_L

PEX_RX4_L

PEX_RX3_L

PEX_RX2_L

PEX_RX1_L

PEX_RX0_L

PCI-EXPRESS BUS INTERFACE

NC

PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5 PEX_IOVDD_6

PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8

PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11

PEX_PLLAVDD PEX_PLLDVDD

PEX_PLLGND

IN

IN IN

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Power aliases required by this page:

- =PP1V2_GPU_PEX_IOVDDQ

BOM options provided by this page:

PEX 1.2V Current = 2A

250mA

Page Notes

(NONE)

180mA

20mA

1500mA

Signal aliases required by this page:

- =PP1V2_GPU_PEX_IOVDD

- =PP1V2_GPU_PEX_PLLXVDD

15 80

C8081

1 2

X5R 402

0.1uF

16V10%

C8082

1 2

0.1uF

X5R16V10% 402

15 80

C8079

1 2

0.1uF

40216V10% X5R

C8080

1 2

402

0.1uF

X5R16V10%

15 80

C8077

1 2

402

0.1uF

X5R16V10%

C8078

1 2

402X5R16V10%

0.1uF

15 80

C8075

1 2

402

0.1uF

X5R16V10%

C8076

1 2

402

0.1uF

X5R16V10%

15 80

C8073

1 2

402

0.1uF

X5R16V10%

C8074

1 2

402

0.1uF

X5R16V10%

15 80

C8020

1 2

40210% 16V X5R

0.1uF

15 80

C8071

1 2

402

0.1uF

X5R16V10%

C8072

1 2

402

0.1uF

X5R16V10%

15 80

C8069

1 2

402

0.1uF

X5R16V10%

C8070

1 2

402

0.1uF

X5R16V10%

15 80

C8067

1 2

402

0.1uF

X5R16V10%

C8021

1 2

10%

0.1uF

16V X5R 402

C8068

1 2

402

0.1uF

X5R16V10%

15 80

C8065

1 2

402

0.1uF

X5R16V10%

C8066

1 2

402

0.1uF

X5R16V10%

15 80

C8063

1 2

402

0.1uF

X5R16V10%

C8064

1 2

402

0.1uF

X5R16V10%

15 80

C8050

1 2

10% 16V X5R

0.1uF

402

15 80

C8061

1 2

402

0.1uF

X5R16V10%

C8062

1 2

0.1uF

402X5R16V10%

15 80

C8059

1 2

402

0.1uF

X5R16V10%

C8060

1 2

402

0.1uF

X5R16V10%

15 80

C8057

1 2

402

0.1uF

X5R16V10%

C8051

1 2

10% 16V X5R 402

0.1uF

C8058

1 2

0.1uF

402X5R16V10%

C8048

1 2

10% 16V X5R

0.1uF

402

C8049

1 2

10% 16V X5R

0.1uF

402

C8046

1 2

16V X5R10%

0.1uF

402

U8000

AH14 AJ14

AH15

AK13 AK14

AM14 AM15

AL23 AL24

AM24 AM25

AK25 AK26

AL26 AL27

AM27 AM28

AL28 AL29

AL15 AL16

AK16 AK17

AL17 AL18

AM18 AM19

AK19 AK20

AL20 AL21

AM21 AM22

AK22 AK23

AM12 AM11

AJ15 AK15

AH16 AG16

AG23 AH23

AK24 AJ24

AJ25 AH25

AH26 AG26

AK27 AJ27

AJ28 AH27

AG17 AH17

AG18 AH18

AK18 AJ18

AJ19 AH19

AG20 AH20

AG21 AH21

AK21 AJ21

AJ22 AH22

NB8P-GS-W-A2

BGA

(1 OF 8)

OMIT

U8000

A26

M5 U6 V1 V3 V4 V5 V6 W1 W3 W4

A28

W5 Y5

Y6 AC26 AD26 AE26 AG12 AH13 AH31 AH32

B32

AM8 AM9

D1

D31 D32

F1

F6

G8

AD23 AF23 AF24 AF25 AG24 AG25

AC16

AF21 AF22

AC17 AC21 AC22 AE18 AE21 AE22 AF12 AF18

AF15 AE15 AE16

NB8P-GS-W-A2

BGA

(2 OF 8)

OMIT

C8001

1

2

6.3V

20%

603

4.7UF

CERM

C8003

1

2

6.3V

10%

1UF

402

CERM

C8004

1

2

10V

0.1UF

20% CERM

402

C8047

1 2

40210% 16V X5R

0.1uF

C8005

1

2

10V

0.1UF

402

CERM

20%

C8016

1

2

603

6.3V

20%

4.7UF

CERM

C8015

1

2

CERM

4.7UF

20%

6.3V 603

C8000

1

2

CERM-X5R

22UF

6.3V 805

20%

C8044

1 2

10% 16V X5R 402

0.1uF

C8002

1

2

CERM 402

10%

6.3V

1UF

C8006

1

2

CERM-X5R

20%

805

6.3V

22UF

C8007

1

2

4.7UF

603

20%

6.3V CERM

C8008

1

2

402

1UF

6.3V

10% CERM

C8009

1

2

CERM 402

1UF

10%

6.3V

C8010

1

2

402

CERM

20%

0.1UF

10V

C8011

1

2

402

0.1UF

10V

20% CERM

C8017

1

2

CERM 402

10V

20%

0.1UF

C8045

1 2

10% X5R

0.1uF

40216V

C8013

1

2

CERM

4.7UF

20%

6.3V 603

C8014

1

2

0.1UF

20% 10V

402

CERM

C8012

1

2

CERM

4.7UF

20%

6.3V 603

L8015

1 2

0603

10NH-600MA

L8012

1 2

0603

10NH-600MA

C8042

1 2

10% 16V X5R

0.1uF

402

C8043

1 2

10% 16V X5R

0.1uF

402

C8040

1 2

10% 16V X5R

0.1uF

402

C8041

1 2

10% 16V X5R

0.1uF

402

C8038

1 2

10% 16V X5R

0.1uF

402

C8039

1 2

10% 16V X5R 402

0.1uF

C8036

1 2

10% 16V X5R

0.1uF

402

C8037

1 2

10% 16V X5R

0.1uF

402

C8034

1 2

10% 16V X5R

0.1uF

402

C8035

1 2

10% 16V X5R

0.1uF

402

C8032

1 2

10% 16V X5R

0.1uF

402

C8033

1 2

10% X5R

0.1uF

40216V

C8030

1 2

10% 16V X5R

0.1uF

402

C8031

1 2

10% 16V X5R 402

0.1uF

C8028

1 2

10% 16V X5R

0.1uF

402

C8029

1 2

10% 16V X5R

0.1uF

402

C8026

1 2

10% 16V X5R

0.1uF

402

C8027

1 2

10% 16V X5R

0.1uF

402

C8024

1 2

16V X5R

0.1uF

40210%

C8025

1 2

10% 16V X5R

0.1uF

402

C8022

1 2

0.1uF

10% X5R 40216V

C8023

1 2

10% 16V X5R

0.1uF

402

15 80

9

29 30 84

9

29 30 84

7

28

C8055

1 2

10% 16V X5R

0.1uF

402

C8056

1 2

10% 16V X5R

0.1uF

402

15 80

C8085

1 2

402

0.1uF

X5R16V10%

C8086

1 2

402X5R16V10%

0.1uF

15 80

C8083

1 2

402

0.1uF

X5R16V10%

C8084

1 2

402

0.1uF

X5R16V10%

15 80

051-7225

14.0.0

8866

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NV G84M PCI-E

TP_GPU_PEXTSTCLK_N

PP1V25_GPU

PEG_R2D_C_N<15>

PEG_R2D_C_P<7>

PEG_R2D_N<6>

PEG_D2R_C_N<8>

PEG_D2R_C_N<11>

PEG_D2R_N<5>

PEG_D2R_C_P<14>

PEG_D2R_N<8>

PEG_D2R_P<9>

PEG_D2R_P<10>

PEG_D2R_P<13>

PEG_D2R_N<6>

PEG_D2R_C_P<7>

PEG_D2R_N<1>

PEG_D2R_N<12>

PEG_D2R_P<0>

PEG_D2R_N<0>

PEG_D2R_P<1>

PEG_D2R_N<2>

PEG_D2R_P<2>

PEG_D2R_N<3>

PEG_D2R_P<3>

PEG_D2R_N<4>

PEG_D2R_P<4>

PEG_D2R_P<5>

PEG_D2R_P<6>

PEG_D2R_P<7>

PEG_D2R_N<7>

PEG_D2R_P<8>

PEG_D2R_N<9>

PEG_D2R_N<10>

PEG_D2R_N<11>

PEG_D2R_P<11>

PEG_D2R_P<12>

PEG_D2R_P<14>

PEG_D2R_P<15>

PEG_D2R_N<14>

PEG_D2R_N<15>

PEG_D2R_N<13>

PEG_D2R_C_P<0> PEG_D2R_C_N<0>

PEG_D2R_C_P<1>

PEG_D2R_C_P<2>

PEG_D2R_C_P<3>

PEG_D2R_C_P<4>

PEG_D2R_C_P<5>

PEG_D2R_C_P<6>

PEG_D2R_C_P<8>

PEG_D2R_C_P<9>

PEG_D2R_C_P<10>

PEG_D2R_C_P<11>

PEG_D2R_C_P<12>

PEG_D2R_C_N<1>

PEG_D2R_C_N<2>

PEG_D2R_C_N<3>

PEG_D2R_C_N<4>

PEG_D2R_C_N<5>

PEG_D2R_C_N<6>

PEG_D2R_C_N<7>

PEG_D2R_C_N<9>

PEG_D2R_C_N<10>

PEG_D2R_C_N<12>

PEG_D2R_C_N<14>

PEG_R2D_N<0>

PEG_R2D_N<3>

PEG_R2D_N<2>

PEG_R2D_N<1>

PEG_R2D_N<4>

PEG_R2D_N<7>

PEG_R2D_N<8>

PEG_R2D_N<9>

PEG_R2D_N<5>

PEG_R2D_N<12>

PEG_R2D_N<15>

PEG_R2D_N<14>

PEG_R2D_P<0>

PEG_R2D_P<1>

PEG_R2D_P<2>

PEG_R2D_P<3>

PEG_R2D_P<4>

PEG_R2D_P<5>

PEG_R2D_C_N<0>

PEG_R2D_C_P<0>

PEG_R2D_C_N<1>

PEG_R2D_C_P<1>

PEG_R2D_C_N<2>

PEG_R2D_C_P<2>

PEG_R2D_C_P<3>

PEG_R2D_C_P<4>

PEG_R2D_C_N<3>

PEG_R2D_C_P<5>

PEG_R2D_C_N<4>

PEG_R2D_P<6>

PEG_R2D_P<7>

PEG_R2D_P<8>

PEG_R2D_P<9>

PEG_R2D_P<10>

PEG_R2D_P<12>

PEG_R2D_P<13>

PEG_R2D_P<14>

PEG_R2D_C_P<6>

PEG_R2D_C_N<5>

PEG_R2D_C_N<6>

PEG_R2D_C_N<7>

PEG_R2D_C_N<8>

PEG_R2D_C_P<8>

PEG_R2D_C_N<9>

PEG_R2D_C_P<9>

PEG_R2D_C_N<10>

PEG_R2D_C_P<10>

PEG_R2D_C_P<11>

PEG_R2D_C_P<13>

PEG_R2D_C_P<14>

PEG_R2D_C_N<13>

PEG_R2D_P<15>

PEG_R2D_C_P<15>

PEG_R2D_C_N<14>

PEG_CLK100M_GPU_P

GPU_RESET_L

PEG_D2R_C_P<15> PEG_D2R_C_N<15>

TP_GPU_PEXTSTCLK_P

PEG_CLK100M_GPU_N

PEG_R2D_C_N<12>

PEG_R2D_C_P<12>

PEG_D2R_C_N<13>

PEG_R2D_N<13>

PEG_R2D_C_N<11>

PEG_D2R_C_P<13>

PEG_R2D_N<11>

PEG_R2D_P<11>

PEG_R2D_N<10>

PP1V2_GPU_PEX_PLLDVDD_F

MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.2V

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP1V2_GPU_PEX_PLLAVDD_F

PP1V25_GPU PP1V25_GPU

77

74

71

68

66

57

8

80

80 80

80

80 80

80

8

FBVTT

FBVDDQ

GND_SENSE

VDD_SENSE

VDD_LP

VDD

FBVDD

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

NC NC NC NC NC NC

NC

NC NC NC NC

NC NC

???A @ ???MHz 1.8V GDDR3

Page Notes

Power aliases required by this page:

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

(NONE)

- =PP1V8_GPU_FBVDDQ

- =PPVCORE_GPU

???A @ ???/???MHz Core/Mem Clk for VDD

C8101

1

2

402

10%

1UF

6.3V CERM

C8100

1

2

402

10%

1UF

6.3V CERM

U8000

A12

A9 AA32 AD32 AG32 AK32 C32 F32 J32 M32 R32

A18 A21 A24 A27 A3 A30 A6

AA25

G22 H11 H12 H15 H18 H21 H22 L25 L26 M25

AA26

M26 R25 R26 V25 V26

AB25 AB26 G11 G12 G15 G18 G21

AA23

K12 K21 K22 K24 K9 L23 M23 T25 U25

AB23 H16 H17 J10 J23 J24 J9 K11

M21

K16

P16 P17 P19 R16 R17 T13 T14 T15 T18 T19

K17

U13 U14 U15 U18 U19 V16 V17 W13 W14 W16

N13

W17 W19 Y13 Y14 Y16 Y17 Y19 Y20

N14 N16 N17 N19 P13 P14

P20 T20 T23 U20 U23 W20

N20

NB8P-GS-W-A2

BGA

(7 OF 8)

OMIT

U8000

AE17

AG11

J16 J17 J2 J31 K10 K23 K29 K4 L27 L6

AB27

M12 M2 M31 N15 N18 N29 N4 P15 P18 P27

AB6

P6 R13 R14 R15 R18 R19 R2 R20 R31 T16

AC10

T17 T24 T29 T4 U16 U17 U24 U29 U8 V13

AC23

V14 V15 V18 V19 V2 V20 V31 W15 W18 W27

AC29

W6 Y15 Y18 Y29 Y4

AC4 AD16 AD17

AD2

AE27

AD31 AA12

AA2 AA21 AA31 AG13 AG14 AG15 AG19

AG2

AE6

AG22 AG31

AG8 AH24 AJ10 AJ13 AJ16 AJ17 AJ20 AJ23

AF11

AJ26 AJ29

AJ4

AJ7

AK2 AK28 AK31 AL10 AL11 AL14

AF26

AL19 AL22 AL25

AL3

AL6

AL9 AM10 AM13 AM16 AM17

AF29

AM20 AM23 AM26 AM29

B12

B15

B18

B21

B24

B27

AF4

B3

B30

B6 B9

C2 C31 D10 D13

D16 D17

AF7

D20 D23 D26 D29 D4 D7 F11 F14 F19 F2

AG10

F22 F25 F31 F8 G26 G29 G4 G7 H27 H6

NB8P-GS-W-A2

(8 OF 8)

BGA

OMIT

C8102

1

2

402

10%

1UF

6.3V CERM

C8107

1

2

CERM 402

10V

20%

0.1UF

C8112

1

2

10V

0.1UF

402

CERM

20%

C8117

1

2

0.1UF

CERM 402

10V

20%

C8106

1

2

402

CERM

20%

0.1UF

10V

C8105

1

2

CERM 402

20%

0.1UF

10V

C8110

1

2

402

0.1UF

CERM

10V

20%

C8111

1

2

10V

0.1UF

CERM 402

20%

C8116

1

2

0.1UF

402

CERM

10V

20%

C8115

1

2

0.1UF

CERM 402

10V

20%

C8104

1

2

20%

402

CERM

0.1UF

10V

C8109

1

2

0.1UF

402

CERM

10V

20%

C8114

1

2

0.1UF

CERM 402

10V

20%

C8113

1

2

0.1UF

402

CERM

10V

20%

C8108

1

2

0.1UF

CERM 402

10V

20%

C8103

1

2

402

20%

0.1UF

CERM

10V

C8160

1

2

0.47UF

6.3V

10%

CERM-X5R

402

C8166

1

2

CERM-X5R

10%

6.3V

0.47UF

402

C8159

1

2

0.1UF

20% 10V

402

CERM

C8151

1

2

CERM

6.3V

20%

603

4.7UF

C8158

1

2

0.1UF

20% 10V

402

CERM

C8165

1

2

10V

20%

0.1UF

402

CERM

C8164

1

2

10V

20%

0.1UF

402

CERM

C8150

1

2

CERM

6.3V

20%

603

4.7UF

C8157

1

2

0.1UF

20% 10V

402

CERM

C8163

1

2

10V

20%

0.1UF

CERM

402

C8162

1

2

10V

20%

0.1UF

402

CERM

C8156

1

2

0.1UF

20% 10V

402

CERM

C8122

1

2

10V

20% CERM

402

0.1UF

C8121

1

2

0.1UF

10V

20%

402

CERM

C8120

1

2

0.1UF

10V

20% CERM

402

C8119

1

2

20%

0.1UF

10V CERM 402

C8118

1

2

0.1UF

10V

20%

402

CERM

C8161

1

2

0.47UF

6.3V

10%

CERM-X5R

402

C8167

1

2

CERM-X5R

10%

6.3V

0.47UF

402

C8169

1

2

402

0.47UF

6.3V

10%

CERM-X5R

C8168

1

2

402

0.47UF

6.3V

10%

CERM-X5R

C8171

1

2

402

0.47UF

6.3V

10%

CERM-X5R

C8170

1

2

402

0.47UF

6.3V

10%

CERM-X5R

SYNC_MASTER=(MASTER)

NV G84M Core/FB Power

67 88

051-7225

14.0.0

SYNC_DATE=(MASTER)

PP1V8_GPU

PPVCORE_GPU

TP_GPU_VDD_SENSE TP_GPU_GND_SENSE

77 73 70 69

74

68

49

57 8 8

7

BI

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

OUT

FBAD20

FBAD22

FBAD1 FBAD2

FBAD18

FBAD0

FBAD3

FBAD5 FBAD6 FBAD7 FBAD8 FBAD9 FBAD10 FBAD11 FBAD12 FBAD13 FBAD14 FBAD15 FBAD16 FBAD17

FBAD19

FBAD21

FBAD23 FBAD24 FBAD25 FBAD26 FBAD27

FBAD29 FBAD30

FBAD32 FBAD33 FBAD34 FBAD35 FBAD36 FBAD37 FBAD38 FBAD39 FBAD40 FBAD41 FBAD42 FBAD43 FBAD44 FBAD45 FBAD46 FBAD47 FBAD48 FBAD49 FBAD50 FBAD51 FBAD52 FBAD53 FBAD54 FBAD55 FBAD56 FBAD57 FBAD58 FBAD59 FBAD60 FBAD61 FBAD62 FBAD63

FBA_PLLAVDD FBA_PLLGND

FBAD31

FBCAL_PD_VDDQ

FBCAL_PU_GND

FBAD28

FBAD4

FBADQS_WP0 FBADQS_WP1

FBADQS_WP3

FBADQS_WP2

FBADQS_WP6

FBADQS_WP5

FBADQS_WP4

FBADQS_WP7

FBA_DEBUG

FBADQS_RN2

FBADQS_RN1

FBADQS_RN0

FBADQS_RN4

FBADQS_RN3

FBADQS_RN5

FBADQS_RN7

FBADQS_RN6

FBA_CLK0

FBA_CLK0_L

FBA_CLK1_L

FBA_CLK1

FBADQM1

FBADQM0

FBADQM3

FBADQM2

FBADQM6

FBADQM5

FBADQM4

FBADQM7

FBA_CMD0

FBA_CMD2

FBA_CMD1

FBA_CMD5

FBA_CMD3 FBA_CMD4

FBA_CMD7

FBA_CMD6

FBA_CMD8

FBA_CMD10

FBA_CMD9

FBA_CMD13

FBA_CMD12

FBA_CMD11

FBA_CMD15

FBA_CMD14

FBA_CMD18

FBA_CMD17

FBA_CMD16

FBA_CMD20

FBA_CMD19

FBA_CMD23

FBA_CMD22

FBA_CMD21

FBA_CMD25

FBA_CMD24

FBA_CMD28

FBA_CMD26 FBA_CMD27

READ STROBE

WRITE STROBE

MEMORY INTERFACE A

OUT

OUT OUT

OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT

FB_VREF

FBCAL_TERM_GND

FBC_PLLGND

FBC_PLLAVDD

FBCD63

FBCD62

FBCD61

FBCD60

FBCD59

FBCD58

FBCD57

FBCD56

FBCD55

FBCD53

FBCD51

FBCD50

FBCD49

FBCD48

FBCD47

FBCD46

FBCD45

FBCD44

FBCD43

FBCD41

FBCD40

FBCD39

FBCD38

FBCD37

FBCD36

FBCD35

FBCD34

FBCD33

FBCD32

FBCD31

FBCD30

FBCD29

FBCD28

FBCD27

FBCD26

FBCD25

FBCD24

FBCD23

FBCD22

FBCD21

FBCD20

FBCD19

FBCD18

FBCD17

FBCD16

FBCD15

FBCD11

FBCD9

FBCD8

FBCD7

FBCD6

FBCD5

FBCD4

FBCD3

FBCD2

FBCD1

FBCD10

FBCD42

FBCD0

FBCD54

FBCD52

FBCD13

FBCD12

FBCD14

FBCDQS_RN0 FBCDQS_RN1 FBCDQS_RN2 FBCDQS_RN3 FBCDQS_RN4 FBCDQS_RN5 FBCDQS_RN6 FBCDQS_RN7

FBCDQS_WP1 FBCDQS_WP2

FBCDQS_WP0

FBCDQS_WP4

FBCDQS_WP3

FBCDQS_WP6 FBCDQS_WP7

FBCDQS_WP5

FBC_DEBUG

FBCDQM7

FBC_CLK1

FBC_CLK0

FBC_CLK0_L

FBC_CLK1_L

FBCDQM0 FBCDQM1 FBCDQM2 FBCDQM3 FBCDQM4 FBCDQM5 FBCDQM6

FBC_CMD4

FBC_CMD3

FBC_CMD6

FBC_CMD5

FBC_CMD9

FBC_CMD8

FBC_CMD7

FBC_CMD11

FBC_CMD10

FBC_CMD14

FBC_CMD13

FBC_CMD12

FBC_CMD16

FBC_CMD15

FBC_CMD19

FBC_CMD18

FBC_CMD17

FBC_CMD21

FBC_CMD20

FBC_CMD22

FBC_CMD24

FBC_CMD23

FBC_CMD27

FBC_CMD26

FBC_CMD25

FBC_CMD28

FBC_CMD1

FBC_CMD0

FBC_CMD2

MEMORY INTERFACE B

WRITE STROBE

READ STROBE

OUT

BI BI BI BI BI BI BI BI

IN IN IN IN IN IN

IN

OUT

OUT OUT OUT OUT

OUT

BI

IN IN IN IN IN IN IN IN

OUT OUT OUT

OUT

OUT OUT OUT

G

D

S

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

BOM options provided by this page:

Signal aliases required by this page:

Power aliases required by this page:

- =PP1V8_GPU_FBIO

(NONE)

- =PP1V2_GPU_FBPLLAVDD

Page Notes

NC NC

69 86

72

69 86

70 86

69 86

U8000

P28 R28 Y27 AA27

P32 U27

T31 U32 W29 W30 T27 V28 V30 U31 R27 V29

P31

T30 W28 R29 R30 P29 U28 Y32 Y30 V32

U30 Y31 W32 W31 T32 V27 T28

AC27

G25 G24

N27 M27

N30 N32 L31 L30 J30 L32 H30 K30 H31 F30

N28

H32 E31 D30 E30 H28 H29 E29 J27 F27 E27

L29

E28

F28 AD29 AE29 AD28 AC28 AB29 AA30

Y28 AB30

K27

AM30 AF30 AJ31 AJ30 AJ32 AK29 AM31 AL30 AE32 AE30

K28

AE31 AD30 AC31 AC32 AB32 AB31 AG27 AF28 AH28 AG28

J29

AG29 AD27 AF27 AE28

J28

P30

N31

M29 M30 G30 F29 AA29 AK30 AC30 AG30

M28 K32 G31 G27 AA28 AL31 AF31 AH29

L28 K31 G32 G28 AB28 AL32 AF32 AH30

K26 H26

NB8P-GS-W-A2

BGA

OMIT

(3 OF 8)

C8201

1

2

402

CERM

10V

0.1UF

20%

69 86

72

69 86

70 86

72

70 86

72

R8200

1

2

10K

402

MF-LF

1/16W

5%

70 86

R8250

1

2

10K

402

MF-LF

1/16W

5%

R8292

12

1/16W MF-LF

1%

402

40.2

R8291

1

2

24.9

1/16W

402

MF-LF

1%

U8000

E32

E13 F13 F18 E17

C13 A16

C15 B16 F17 C19 D15 C17 A17 C16 D14 F16

A13

C14 C18 E14 B13 E15 F15 A20 C20 A15

B17 B20 A19 B19 B14 E16 A14

F12

G10

G9

J26

B7 A7

D12

D9 E12 D11

E8

D8

E7

F7

D6

D5

C7

D3

E4

C3

B4 C10 B10

C8 A10 C11 C12

A2

A11 B11 B28 C27 C26 B26 C30 B31 C29 A31

B2

D28 D27 F26 D24 E23 E26 E24 F23 B23 A23

C4

C25 C23 A22 C22 C21 B22 E22 D22 D21 E21

A5

E18 D19 D18 E19

B5

F9 F10

A4 E11 F5 C9 C28 F24 C24 E20

C6 E9 E6 A8 B29 E25 A25 F21

C5 E10 E5 B8 A29 D25 B25 F20

NB8P-GS-W-A2

BGA

(4 OF 8)

OMIT

C8296

1

2

402

X5R

10%

0.1uF

16V

R8295

1

2

1%

1/16W

402

MF-LF

1.07K

L8200

1 2

FERR-220-OHM

0402

R8290

12

45.3

1/16W MF-LF

1%

402

C8200

1

2

6.3V CERM

603

20%

4.7UF

R8201

1

2

10K

MF-LF

1/16W

5%

402

R8251

1

2

10K

402

MF-LF

1/16W

5%

69 86

70 86

Q8295

3

5

4

SOT-363

2N7002DW-X-F

R8296

1

2

2.49K

1% 1/16W MF-LF

402

R8297

1

2

1.02K

1% 1/16W MF-LF

402

69 70 71 72

14.0.0

051-7225

8868

SYNC_DATE=(MASTER)

NV G84M Frame Buffer I/F

SYNC_MASTER=(MASTER)

PP1V25_GPU

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP1V2_GPU_FBA_PLL_F

VOLTAGE=1.2V

FB_A_DQ<3>

FB_A_DQ<6>

FB_A_DQ<9>

FB_A_DQ<23>

FB_A_DQ<27>

FB_A_DQ<24>

FB_A_DQ<22>

FB_B_DRAM_RST

FB_B_CKE FB_B_MA<0> FB_B_MA<9>

FB_B_DQ<48>

FB_B_DQ<47>

FB_A_MA<6>

FB_A_MA<1>

FB_A_MA<8> FB_A_LMA<3>

FB_B_DQ<53>

FBCAL_TERM_GND

NC_FB_A_MA12

FB_A_BA<0>

FB_A_CAS_L

FB_A_DRAM_RST

FB_A_WE_L

FB_A_UMA<5>

FB_A_MA<7> FB_A_MA<10>

FB_A_LMA<4>

FB_B_DQ<55>

FB_B_DQ<51>

FB_B_DQ<43>

FB_A_UMA<2>

FB_B_CS0_L

FB_B_UMA<3>

FB_B_BA<0>

FB_A_UMA<4>

FB_B_DQ<21>

FB_B_DQ<20>

FB_B_DQ<18>

FB_B_DQ<17>

FB_A_BA<1>

FB_A_LMA<5>

FB_A_RAS_L

FB_A_UMA<3>

FB_A_MA<11>

FB_A_MA<0>

NC_FB_A_MA13

FB_A_LMA<2>

FB_A_MA<9>

NC_FB_B_MA13

FB_B_MA<1>

FB_B_LMA<3>

FB_B_MA<8>

FB_B_LMA<2>

FB_B_MA<6>

FB_B_MA<10>

FB_B_MA<7>

NC_FB_B_MA12

FB_B_UMA<5>

FB_B_WE_L

FB_B_CAS_L

FB_B_MA<11>

FB_B_LMA<5>

FB_B_RAS_L

FB_B_DQ<61>

FB_B_DQ<59>

FB_B_DQ<58>

FB_B_DQ<57>

FB_B_DQ<50>

FB_B_DQ<49>

FB_B_DQ<46>

FB_B_DQ<45>

FB_B_DQ<44>

FB_B_DQ<41>

FB_B_DQ<40>

FB_B_DQ<39>

FB_B_DQ<38>

FB_B_DQ<37>

FB_B_DQ<36>

FB_B_DQ<35>

FB_B_DQ<34>

FB_B_DQ<33>

FB_B_DQ<30>

FB_B_DQ<29>

FB_B_DQ<28>

FB_B_DQ<27>

FB_B_DQ<26>

FB_B_DQ<25>

FB_B_DQ<24>

FB_B_DQ<23>

FB_B_DQ<22>

FB_B_DQ<19>

FB_B_DQ<16>

FB_B_DQ<15>

FB_B_DQ<11>

FB_B_DQ<9>

FB_B_DQ<8>

FB_B_DQ<7>

FB_B_DQ<6>

FB_B_DQ<5>

FB_B_DQ<4>

FB_B_DQ<3>

FB_B_DQ<2>

FB_B_DQ<1>

FB_B_DQ<10>

FB_B_LMA<4>

FB_B_DQ<42>

FB_B_BA<1>

FB_B_DQ<0>

FB_B_BA<2>

FB_B_UMA<4>

FB_B_UMA<2>

FB_B_DQ<54>

FB_B_DQ<13>

FB_B_DQ<12>

FB_B_DQ<14>

FB_B_DQ<60>

FB_B_DQ<52>

FB_B_DQ<56>

FB_B_DQ<62>

FB_A_DQ<0>

FB_A_DQ<12>

FB_A_DQ<11>

FB_A_DQ<10>

FB_A_DQ<8>

FB_A_DQ<7>

FB_A_DQ<4>

FB_A_DQ<21>

FB_A_DQ<20>

FB_A_DQ<19>

FB_A_DQ<18>

FB_A_DQ<17>

FB_A_DQ<16>

FB_A_DQ<15>

FB_A_DQ<14>

FB_A_DQ<13>

FB_A_DQ<32>

FB_A_DQ<31>

FB_A_DQ<30>

FB_A_DQ<29>

FB_A_DQ<28>

FB_A_DQ<26>

FB_A_DQ<25>

FB_A_DQ<33>

FB_A_DQ<43>

FB_A_DQ<42>

FB_A_DQ<41>

FB_A_DQ<40>

FB_A_DQ<39>

FB_A_DQ<38>

FB_A_DQ<37>

FB_A_DQ<36>

FB_A_DQ<34>

FB_A_DQ<53>

FB_A_DQ<52>

FB_A_DQ<51>

FB_A_DQ<50>

FB_A_DQ<49>

FB_A_DQ<48>

FB_A_DQ<47>

FB_A_DQ<46>

FB_A_DQ<45>

FB_A_DQ<44>

FB_A_DQ<62>

FB_A_DQ<61>

FB_A_DQ<60>

FB_A_DQ<59>

FB_A_DQ<58>

FB_A_DQ<57>

FB_A_DQ<56>

FB_A_DQ<55>

FB_A_DQ<54>

FB_A_DQ<63> FB_B_DQ<63>

FB_A_DQ<1> FB_A_DQ<2>

FB_A_CS0_L

FB_A_BA<2>

FB_A_DQ<5>

FB_A_CKE

FBCAL_PD_VDDQ

TP_FBA_DEBUG

FBCAL_PU_GND

FB_A_DQM_L<0> FB_A_DQM_L<1> FB_A_DQM_L<2> FB_A_DQM_L<3> FB_A_DQM_L<4> FB_A_DQM_L<5> FB_A_DQM_L<6> FB_A_DQM_L<7>

FB_A_RDQS<0> FB_A_RDQS<1> FB_A_RDQS<2> FB_A_RDQS<3> FB_A_RDQS<4> FB_A_RDQS<5> FB_A_RDQS<6> FB_A_RDQS<7>

FB_A_WDQS<0> FB_A_WDQS<1> FB_A_WDQS<2> FB_A_WDQS<3> FB_A_WDQS<4> FB_A_WDQS<5> FB_A_WDQS<6> FB_A_WDQS<7>

FB_A_CLK_P<0> FB_A_CLK_N<0>

NC_FBA_CMD27 NC_FBA_CMD28

FB_A_CLK_P<1> FB_A_CLK_N<1>

FB_A_DQ<35>

PP1V8_GPU

TP_FBC_DEBUG

FB_B_CLK_P<1>

FB_B_CLK_P<0> FB_B_CLK_N<0>

FB_B_DQM_L<0> FB_B_DQM_L<1> FB_B_DQM_L<2>

FB_B_CLK_N<1>

FB_B_DQM_L<3>

FB_B_DQM_L<5> FB_B_DQM_L<6> FB_B_DQM_L<7>

FB_B_DQM_L<4>

FB_B_RDQS<4>

FB_B_RDQS<3>

FB_B_RDQS<2>

FB_B_RDQS<1>

FB_B_RDQS<0>

FB_B_WDQS<0>

FB_B_RDQS<7>

FB_B_RDQS<6>

FB_B_RDQS<5>

FB_B_WDQS<5>

FB_B_WDQS<3> FB_B_WDQS<4>

FB_B_WDQS<2>

FB_B_WDQS<1>

FB_B_WDQS<6>

NC_FBC_CMD27 NC_FBC_CMD28

FB_B_DQ<31> FB_B_DQ<32>

FB_B_WDQS<7>

PP1V8_GPU

GPU_FB_VREF

GPU_FB_VREF_UNTERM_L

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

FB_VREF_UNTERM

77

73

77

70

74

69

71

68

66

67

57

8

72

8

72

8

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ8

DQ7

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21

DQ24

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6 A7

A3 A4

A2

A0 A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1 RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

(1 OF 2)

VSS0 VSS1 VSS2

VSS5

VSS3 VSS4

VSS7

VSS6

VSSA0 VSSA1

VSSQ0 VSSQ1 VSSQ2 VSSQ3

VSSQ5 VSSQ6

VSSQ4

VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14

VSSQ16

VSSQ15

VSSQ17 VSSQ18 VSSQ19VDDQ19

VDDQ20 VDDQ21

VREF1

VREF0

VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VDDQ18

VDDQ16 VDDQ17

VDDQ9

VDDA1

VDDQ0 VDDQ1 VDDQ2

VDDQ5

VDDQ3 VDDQ4

VDDQ6 VDDQ7 VDDQ8

VDD0 VDD1 VDD2

VDD5

VDD3 VDD4

VDD6 VDD7

VDDA0

(2 OF 2)

IN

BI

IN

OUT OUT OUT OUT

IN

IN IN

IN

OUT

OUT OUT

OUT

IN

IN IN

IN

IN IN

IN

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ8

DQ7

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21

DQ24

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6 A7

A3 A4

A2

A0 A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1 RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

(1 OF 2)

VSS0 VSS1 VSS2

VSS5

VSS3 VSS4

VSS7

VSS6

VSSA0 VSSA1

VSSQ0 VSSQ1 VSSQ2 VSSQ3

VSSQ5 VSSQ6

VSSQ4

VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14

VSSQ16

VSSQ15

VSSQ17 VSSQ18 VSSQ19VDDQ19

VDDQ20 VDDQ21

VREF1

VREF0

VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VDDQ18

VDDQ16 VDDQ17

VDDQ9

VDDA1

VDDQ0 VDDQ1 VDDQ2

VDDQ5

VDDQ3 VDDQ4

VDDQ6 VDDQ7 VDDQ8

VDD0 VDD1 VDD2

VDD5

VDD3 VDD4

VDD6 VDD7

VDDA0

(2 OF 2)

BI BI BI BI

BI BI BI BI BI

BI

BI BI BI BI

BI

IN IN

BI

IN IN

G

D

S

G

D

S

IN IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Connect to designated pin, then GND

BOM options provided by this page:

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

Connect to designated pin, then GND

NC NC

- =PP1V8_S0_FB_VDDQ

- =PP1V8_S0_FB_VDD

(NONE)

U8400.J1

U8400.J12

U8400.J1

U8400.J12

NC

R8430

1

2

1/16W

1%

402

MF-LF

2.37K

R8431

1

2

402

1/16W

1%

MF-LF

5.49K

C8403

1

2

0.1uF

X5R 402

10% 16V

C8402

1

2

X5R 402

10% 16V

0.1uF

C8404

1

2

0.1uF

X5R 402

10% 16V

C8401

1

2

0.1uF

X5R 402

10% 16V

C8422

1

2

402

16V

10% X5R

0.1uF

C8423

1

2

X5R

16V

10% 402

0.1uF

C8424

1

2

0.1uF

16V

10% 402

X5R

C8425

1

2

0.1uF

X5R 402

10% 16V

C8426

1

2

X5R 402

10% 16V

0.1uF

U8400

K9

H11

K11

L9

K10

M9 K4 H2 K3 L4 K2 M4

G9 G4 H3

F9

J11 J10

H9

F4

E3 E10 N10 N3

B2 B3

C11 C10 E11 F10 F11 G10 M11 L10 N11 M10

C2

R11 R10 T11 T10 M2 L3 N2 M3 R2 R3

C3

T2 T3

E2 F3 F2 G3 B11 B10

A9

H10

D3 D10 P10

P3

V9

J2

J3

V4

D2 D11 P11

P2

H4

A4

CRITICAL

OMIT

FBGA

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

U8400

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4 J9 N1 N4 N9

N12

R1 R4 R9

R12

C1

V1

V12

C4 C9

C12

E1 E4 E9

E12

H1

H12

A3 A10 G1 G12 L1 L12 V3 V10

J1 J12

B1 B4

L2 L11 P1 P4 P9 P12 T1 T4 T9 T12

B9 B12 D1 D4 D9 D12 G2 G11

OMIT

CRITICAL

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

FBGA

R8449

1

2

MF-LF 402

5% 1/16W

100

R8448

1

2

243

MF-LF

402

1%

1/16W

R8445

1

2

MF-LF 402

1% 1/16W

121

R8446

1

2

60.4

MF-LF

402

1%

1/16W

C8433

1

2

CERM

25V

0.0047uF

10% 402

C8421

1

2

0.1uF

16V

10% X5R

402

C8415

1

2

0.1uF

X5R 402

10% 16V

C8410

1

2

0.1uF

X5R 402

16V

10%

R8440

1

2

1/16W

402

MF-LF

1K

5%

R8447

1

2

60.4

1% MF-LF

402

1/16W

R8444

1

2

1/16W

402

MF-LF

121

1%

R8443

1

2

MF-LF

1%

121

402

1/16W

R8442

1

2

1/16W

402

MF-LF

121

1%

68 86

68 69 86

68 86

68 69 86

68 86

68 69 86

68 86

68 69 86

68 86

68 69 86

68 86

68 69 86

68 86

68 69 86

68 86

68 69 86

R8490

1

2

5%

1K

1/16W

402

MF-LF

R8492

1

2

1/16W

402

MF-LF

121

1%

C8471

1

2

16V 402

X5R

0.1uF

10%

C8472

1

2

16V

10% 402

X5R

0.1uF

R8498

1

2

1/16W

1%

402

MF-LF

243

R8499

1

2

1/16W

5%

402

MF-LF

100

U8450

K9

H11

K11

L9

K10

M9 K4 H2 K3 L4 K2 M4

G9 G4 H3

F9

J11 J10

H9

F4

E3 E10 N10 N3

B2 B3

C11 C10 E11 F10 F11 G10 M11 L10 N11 M10

C2

R11 R10 T11 T10 M2 L3 N2 M3 R2 R3

C3

T2 T3

E2 F3 F2 G3 B11 B10

A9

H10

D3 D10 P10

P3

V9

J2

J3

V4

D2 D11 P11

P2

H4

A4

CRITICAL

FBGA

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

OMIT

R8493

1

2

1%

121

MF-LF 402

1/16W

R8495

1

2

121

1/16W

1%

402

MF-LF

R8494

1

2

1/16W

402

MF-LF

121

1%

R8497

1

2

60.4

1/16W 402

MF-LF

1%

R8496

1

2

1/16W

1%

402

MF-LF

60.4

C8473

1

2

16V

10% 402

X5R

0.1uF

C8474

1

2

16V

10% 402

X5R

0.1uF

C8475

1

2

16V

10% 402

X5R

0.1uF

U8450

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4 J9 N1 N4 N9

N12

R1 R4 R9

R12

C1

V1

V12

C4 C9

C12

E1 E4 E9

E12

H1

H12

A3 A10 G1 G12 L1 L12 V3 V10

J1 J12

B1 B4

L2 L11 P1 P4 P9 P12 T1 T4 T9 T12

B9 B12 D1 D4 D9 D12 G2 G11

CRITICAL

OMIT

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

FBGA

C8476

1

2

16V

10% 402

X5R

0.1uF

C8451

1

2

16V

10%

402

0.1uF

X5R

C8452

1

2

16V

10% X5R

0.1uF

402

C8460

1

2

16V

10%

402

X5R

0.1uF

C8453

1

2

16V

10%

402

X5R

0.1uF

C8465

1

2

16V

10%

402

X5R

0.1uF

C8454

1

2

16V

10%

402

X5R

0.1uF

68 86

C8400

1

2

805

22UF

20%

6.3V

CERM-X5R

C8420

1

2

CERM-X5R

20%

6.3V 805

22UF

C8450

1

2

20%

6.3V 805

22UF

CERM-X5R

C8470

1

2

805

20%

6.3V

22UF

CERM-X5R

C8446

1

2

16V

10%

402

0.01UF

CERM

C8496

1

2

16V

10%

402

0.01UF

CERM

R8432

1

2

2.21K

1/16W

1%

MF-LF

402

Q8400

3

5

4

SOT-363

2N7002DW-X-F

C8483

1

2

CERM

25V

0.0047uF

402

10%

Q8400

6

2

1

2N7002DW-X-F

SOT-363

C8481

1

2

402

10%

0.0047uF

25V CERM

R8482

1

2

2.21K

1/16W

1%

MF-LF

402

R8480

1

2

2.37K

MF-LF

402

1%

1/16W

R8481

1

2

5.49K

MF-LF

1%

1/16W

402

68 69 70 71 72

C8431

1

2

10% 402

0.0047uF

25V CERM

88

051-7225

14.0.0

69

GDDR3 Frame Buffer A

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

FB_A_RDQS<6> FB_A_RDQS<4>

PP1V8_GPU

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

FB_A1_VREF_UNTERM_L

FB_A_UMA<4>

FB_A_UMA<2>

FB_A_CLK_P<1>

FB_A1_MF

FB_A_LMA<4>

FB_A_CLK_P<0>

FB_A_LMA<2>

FB_A_MA<6>

FB_A_BA<2>

FB_A_DQ<28>

FB_A_DQ<0>

FB_A_MA<11>

FB_A_CS0_L

FB_A_CAS_L FB_A_RAS_L

FB_A1_ZQ

FB_A_MA<8>

FB_A_MA<11>

FB_A_RDQS<2>

FB_A_MA<10>

FB_A_MA<8>

FB_A_DQM_L<7> FB_A_DQM_L<5> FB_A_DQM_L<6> FB_A_DQM_L<4>

FB_A_BA<1>

FB_A_BA<0>

FB_A_WDQS<4>

FB_A_WDQS<7> FB_A_WDQS<5> FB_A_WDQS<6>

FB_A_MA<1>

FB_A_MA<7>

FB_A_MA<6>

FB_A_MA<9>

FB_A_DRAM_RST

FB_A1_SEN

FB_A_RDQS<7> FB_A_RDQS<5>

FB_A_DQ<38>

FB_A_DQ<39>

FB_A_DQ<37>

FB_A_DQ<35>

FB_A_DQ<33>

FB_A_DQ<54>

FB_A_DQ<34>

FB_A_DQ<48>

FB_A_DQ<50>

FB_A_DQ<43>

FB_A_DQ<41>

FB_A_DQ<44>

FB_A_DQ<61>

FB_A_DQ<59>

FB_A_DQ<62>

FB_A_MA<10>

FB_A_DQM_L<0>

FB_A_DQM_L<2> FB_A_DQM_L<3>

FB_A_BA<1>

FB_A_DQ<30>

FB_A_DQ<29>

FB_A_DQ<31> FB_A_DQ<26>

FB_A_DQ<24>

FB_A_DQ<27>

FB_A_DQ<22> FB_A_DQ<23> FB_A_DQ<25>

FB_A_DQ<19>

FB_A_DQ<21>

FB_A_DQ<20>

FB_A_DQ<16>

FB_A_DQ<18>

FB_A_DQ<17>

FB_A_DQ<13>

FB_A_DQ<14>

FB_A_DQ<15>

FB_A_DQ<12>

FB_A_DQ<11>

FB_A_DQ<10>

FB_A_DQ<9>

FB_A_DQ<6> FB_A_DQ<8>

FB_A_DQ<5>

FB_A_DQ<3>

FB_A_DQ<7>

FB_A_DQ<2>

FB_A_DQ<1> FB_A_DQ<4>

FB_A_BA<2>

FB_A_DQM_L<1>

FB_A_RDQS<3>

FB_A_RDQS<1>

FB_A_RDQS<0>

FB_A_DQ<56> FB_A_DQ<58>

FB_A_DQ<57> FB_A_DQ<63> FB_A_DQ<60>

FB_A_DQ<40> FB_A_DQ<47> FB_A_DQ<46> FB_A_DQ<45> FB_A_DQ<42>

FB_A_RAS_L

FB_A_CKE

FB_A0_MF

FB_A_WE_L

FB_A_CKE

FB_A_CLK_N<1>

FB_A_UMA<5>

PP1V8_GPU

FB_A0_SEN

FB_A_BA<0>

FB_A_WDQS<3>

FB_A_WDQS<2>

FB_A_WDQS<1>

FB_A_WDQS<0>

FB_A_CAS_L

FB_A_WE_L

FB_A_CS0_L

FB_A_DQ<52> FB_A_DQ<51> FB_A_DQ<55> FB_A_DQ<49>

FB_A_DQ<53>

FB_A_DQ<36>

FB_A_DQ<32>

FB_A_DRAM_RST

FB_A0_ZQ

FB_A_CLK_N<0>

FB_A_MA<9>

FB_A_MA<7>

FB_A_LMA<5>

FB_A_LMA<3>

FB_A_MA<1>

FB_A_MA<0>

PP1V8_GPU

FB_A_CLK0_TERM

FB_A0_VREF_UNTERM_L

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_VREF_UNTERM

FB_A_CLK1_TERM

FB_VREF_UNTERM

FB_A_UMA<3>

FB_A_MA<0>

PP1V8_GPU

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_A0_VREF FB_A1_VREF

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

77

73

70

69

68

67

57

8

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ8

DQ7

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21

DQ24

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6 A7

A3 A4

A2

A0 A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1 RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

(1 OF 2)

VSS0 VSS1 VSS2

VSS5

VSS3 VSS4

VSS7

VSS6

VSSA0 VSSA1

VSSQ0 VSSQ1 VSSQ2 VSSQ3

VSSQ5 VSSQ6

VSSQ4

VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14

VSSQ16

VSSQ15

VSSQ17 VSSQ18 VSSQ19VDDQ19

VDDQ20 VDDQ21

VREF1

VREF0

VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VDDQ18

VDDQ16 VDDQ17

VDDQ9

VDDA1

VDDQ0 VDDQ1 VDDQ2

VDDQ5

VDDQ3 VDDQ4

VDDQ6 VDDQ7 VDDQ8

VDD0 VDD1 VDD2

VDD5

VDD3 VDD4

VDD6 VDD7

VDDA0

(2 OF 2)

IN

BI

IN

OUT OUT OUT OUT

IN

IN IN

IN

OUT

OUT OUT

OUT

IN

IN IN

IN

IN IN

IN

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ8

DQ7

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21

DQ24

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6 A7

A3 A4

A2

A0 A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1 RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

(1 OF 2)

VSS0 VSS1 VSS2

VSS5

VSS3 VSS4

VSS7

VSS6

VSSA0 VSSA1

VSSQ0 VSSQ1 VSSQ2 VSSQ3

VSSQ5 VSSQ6

VSSQ4

VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14

VSSQ16

VSSQ15

VSSQ17 VSSQ18 VSSQ19VDDQ19

VDDQ20 VDDQ21

VREF1

VREF0

VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VDDQ18

VDDQ16 VDDQ17

VDDQ9

VDDA1

VDDQ0 VDDQ1 VDDQ2

VDDQ5

VDDQ3 VDDQ4

VDDQ6 VDDQ7 VDDQ8

VDD0 VDD1 VDD2

VDD5

VDD3 VDD4

VDD6 VDD7

VDDA0

(2 OF 2)

BI BI BI BI

BI BI BI BI BI

BI

BI BI BI BI

BI

IN IN

BI

IN IN

G

D

S

G

D

S

IN IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

U8500.J12

U8500.J1

U8500.J12

U8500.J1

Connect to designated pin, then GND

NC NCNC

NC

- =PP1V8_S0_FB_VDDQ

- =PP1V8_S0_FB_VDD

(NONE)

Signal aliases required by this page:

BOM options provided by this page:

Power aliases required by this page:

Page Notes

Connect to designated pin, then GND

C8503

1

2

16V

10% X5R

0.1uF

402

C8502

1

2

16V

10%

402

X5R

0.1uF

C8504

1

2

16V

10%

402

X5R

0.1uF

C8501

1

2

402

16V

10% X5R

0.1uF

C8522

1

2

16V

10% 402

X5R

0.1uF

C8523

1

2

16V

10% 402

X5R

0.1uF

C8524

1

2

16V

10% 402

X5R

0.1uF

C8525

1

2

16V

10% 402

X5R

0.1uF

C8526

1

2

10% X5R

0.1uF

402

16V

U8500

K9

H11

K11

L9

K10

M9 K4 H2 K3 L4 K2 M4

G9 G4 H3

F9

J11 J10

H9

F4

E3 E10 N10 N3

B2 B3

C11 C10 E11 F10 F11 G10 M11 L10 N11 M10

C2

R11 R10 T11 T10 M2 L3 N2 M3 R2 R3

C3

T2 T3

E2 F3 F2 G3 B11 B10

A9

H10

D3 D10 P10

P3

V9

J2

J3

V4

D2 D11 P11

P2

H4

A4

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

FBGA

OMIT

CRITICAL

U8500

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4 J9 N1 N4 N9

N12

R1 R4 R9

R12

C1

V1

V12

C4 C9

C12

E1 E4 E9

E12

H1

H12

A3 A10 G1 G12 L1 L12 V3 V10

J1 J12

B1 B4

L2 L11 P1 P4 P9 P12 T1 T4 T9 T12

B9 B12 D1 D4 D9 D12 G2 G11

CRITICAL

OMIT

FBGA

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

R8549

1

2

1/16W

5%

402

MF-LF

100

R8548

1

2

1/16W

1%

402

MF-LF

243

C8521

1

2

16V

10% X5R

0.1uF

402

C8515

1

2

16V

10%

402

X5R

0.1uF

C8510

1

2

16V

10%

402

X5R

0.1uF

68 86

68 70 86

68 86

68 70 86

68 86

68 70 86

68 86

68 70 86

68 86

68 70 86

68 86

68 70 86

68 86

68 70 86

68 86

68 70 86

C8571

1

2

X5R 402

10% 16V

0.1uF

C8572

1

2

X5R 402

10% 16V

0.1uF

R8598

1

2

1/16W

402

MF-LF

243

1%

R8599

1

2

1/16W 402

MF-LF

5%

100

U8550

K9

H11

K11

L9

K10

M9 K4 H2 K3 L4 K2 M4

G9 G4 H3

F9

J11 J10

H9

F4

E3 E10 N10 N3

B2 B3

C11 C10 E11 F10 F11 G10 M11 L10 N11 M10

C2

R11 R10 T11 T10 M2 L3 N2 M3 R2 R3

C3

T2 T3

E2 F3 F2 G3 B11 B10

A9

H10

D3 D10 P10

P3

V9

J2

J3

V4

D2 D11 P11

P2

H4

A4

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

OMIT

CRITICAL

FBGA

C8573

1

2

10% 402

X5R

16V

0.1uF

C8574

1

2

16V

10% 402

X5R

0.1uF

C8575

1

2

X5R 402

10% 16V

0.1uF

U8550

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4 J9 N1 N4 N9

N12

R1 R4 R9

R12

C1

V1

V12

C4 C9

C12

E1 E4 E9

E12

H1

H12

A3 A10 G1 G12 L1 L12 V3 V10

J1 J12

B1 B4

L2 L11 P1 P4 P9 P12 T1 T4 T9 T12

B9 B12 D1 D4 D9 D12 G2 G11

K4J52324QC-BC20

OMIT

CRITICAL

FBGA

16MX32-GDDR3-500MHZ

C8576

1

2

X5R 402

10% 16V

0.1uF

C8551

1

2

0.1uF

X5R 402

10% 16V

C8552

1

2

0.1uF

X5R 402

10% 16V

C8560

1

2

16V

10%

402

X5R

0.1uF

C8553

1

2

16V

10%

402

X5R

0.1uF

C8565

1

2

16V

10%

402

X5R

0.1uF

C8554

1

2

0.1uF

X5R 402

10% 16V

68 86

C8500

1

2

20%

6.3V 805

22UF

CERM-X5R

C8520

1

2

CERM-X5R

20%

6.3V 805

22UF

C8550

1

2

CERM-X5R

20%

6.3V 805

22UF

C8570

1

2

CERM-X5R

22UF

20%

6.3V 805

R8546

1

2

60.4

402

1% 1/16W MF-LF

R8547

1

2

60.4

1% MF-LF

402

1/16W

R8544

1

2

1/16W

121

1%

MF-LF

402

R8545

1

2

MF-LF 402

1% 1/16W

121

R8542

1

2

402

MF-LF

121

1%

1/16W

R8540

1

2

5%

MF-LF

402

1/16W

1K

R8543

1

2

MF-LF

1%

121

402

1/16W

R8596

1

2

60.4

MF-LF

402

1%

1/16W

R8597

1

2

1% MF-LF

402

1/16W

60.4

R8595

1

2

MF-LF 402

121

1% 1/16W

R8594

1

2

1%

121

MF-LF

402

1/16W

R8592

1

2

1%

121

MF-LF

402

1/16W

R8593

1

2

1/16W 402

MF-LF

1%

121

R8590

1

2

MF-LF

402

1/16W

1K

5%

C8596

1

2

16V

10%

402

0.01UF

CERM

C8546

1

2

CERM

0.01UF

402

10% 16V

R8531

1

2

5.49K

MF-LF

1%

1/16W

402

R8532

1

2

2.21K

1/16W

1%

MF-LF

402

C8531

1

2

402

10%

0.0047uF

25V CERM

C8533

1

2

CERM

25V

0.0047uF

402

10%

Q8500

3

5

4

2N7002DW-X-F

SOT-363

R8530

1

2

2.37K

MF-LF

402

1%

1/16W

R8581

1

2

402

1/16W

1%

MF-LF

5.49K

R8582

1

2

2.21K

402

MF-LF

1%

1/16W

R8580

1

2

1/16W

1%

402

MF-LF

2.37K

C8581

1

2

10% 402

0.0047uF

25V CERM

C8583

1

2

CERM

25V

0.0047uF

10% 402

Q8500

6

2

1

SOT-363

2N7002DW-X-F

68 69 70 71 72

GDDR3 Frame Buffer B

70 88

14.0.0

051-7225

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

FB_VREF_UNTERMFB_VREF_UNTERM

FB_B0_VREF_UNTERM_L

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

FB_B_CLK0_TERM

PP1V8_GPU

FB_B1_MFFB_B0_MF

FB_B_RAS_L

FB_B_DRAM_RST FB_B_RDQS<2>

FB_B_UMA<2>

FB_B_LMA<3>

FB_B_LMA<2>

FB_B_LMA<4> FB_B_LMA<5>

FB_B_RAS_L

FB_B_CAS_L

FB_B_WE_L

FB_B_CS0_L

FB_B_CKE

FB_B_CAS_L

FB_B1_SEN

FB_B_DQ<35>

FB_B_RDQS<5>

FB_B_BA<2>FB_B_BA<2>

FB_B_DQM_L<6>

FB_B_DQM_L<7>

FB_B_BA<1>

FB_B_BA<0>

FB_B_WDQS<7>

FB_B_WDQS<6> FB_B_WDQS<5>

FB_B_DRAM_RST FB_B_RDQS<6>

FB_B_RDQS<7>

FB_B_DQ<57>

FB_B_DQ<62>

FB_B_DQ<59>

FB_B_DQ<61>

FB_B_DQ<33> FB_B_DQ<63>

FB_B_DQ<32>

FB_B_DQ<34>

FB_B_DQ<38>

FB_B_DQ<37>

FB_B_DQ<47>

FB_B_DQ<46>

FB_B_DQ<43>

FB_B_DQ<41>

FB_B_DQ<42>

FB_B_DQ<52>

FB_B_DQ<54>

FB_B_DQ<55>

FB_B_DQ<51>

FB_B_DQ<48>

FB_B_DQ<49> FB_B_DQ<50>

FB_B_MA<8>

FB_B_DQM_L<2> FB_B_DQM_L<1>

FB_B_WDQS<0>

FB_B_WDQS<1> FB_B_WDQS<3>

FB_B_MA<0>

FB_B_MA<6>

FB_B_DQ<3>

FB_B_DQ<7>

FB_B_DQ<0>

FB_B_DQ<6>

FB_B_DQ<1>

FB_B_DQ<26> FB_B_DQ<27> FB_B_DQ<2>

FB_B_DQ<30>

FB_B_DQ<31>

FB_B_DQ<29>

FB_B_DQ<28>

FB_B_DQ<24>

FB_B_DQ<11>

FB_B_DQ<14>

FB_B_DQ<13>

FB_B_DQ<10>

FB_B_DQ<9>

FB_B_DQ<12>

FB_B_DQ<22> FB_B_DQ<8>

FB_B_DQ<21>

FB_B_DQ<20>

FB_B_DQ<23>

FB_B_BA<1>

FB_B_BA<0>

FB_B_DQ<56> FB_B_DQ<60>

FB_B_MA<1>

FB_B_DQ<45>

FB_B_DQ<58>

FB_B1_ZQ

FB_B_DQ<15>

FB_B0_SEN

FB_B0_ZQ

FB_B_RDQS<1> FB_B_RDQS<3> FB_B_RDQS<0>

FB_B_DQM_L<3>

FB_B_DQ<18>

FB_B_DQ<19> FB_B_DQ<16>

FB_B_DQ<25>

FB_B_DQ<4> FB_B_DQ<5>

FB_B_RDQS<4>

FB_B_DQ<17>

FB_B_MA<11>

FB_B_WDQS<2>

FB_B_WE_L

FB_B_CS0_L

FB_B_CLK_N<0>

FB_B_CKE

FB_B_MA<10>

FB_B_MA<9>

FB_B_MA<7>

FB_B_MA<1>

FB_B_DQ<39>

FB_B_DQ<36>

FB_B_DQ<44>

FB_B_DQ<40>

FB_B_CLK_N<1>

FB_B_CLK_P<1>

FB_B_MA<6>

FB_B_UMA<3> FB_B_UMA<4> FB_B_UMA<5>

FB_B_MA<7> FB_B_MA<8> FB_B_MA<9> FB_B_MA<10> FB_B_MA<11>

FB_B_DQ<53>

FB_B_DQM_L<5> FB_B_DQM_L<4>

FB_B_MA<0>

FB_B_CLK_P<0>

FB_B_CLK1_TERM

FB_B_WDQS<4>

FB_B_DQM_L<0>

FB_B1_VREF_UNTERM_L

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP1V8_GPU

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_B0_VREF

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

FB_B1_VREF

77

73

70

69

68

67

57

8

VDD33_1 VDD33_2 VDD33_3 VDD33_4 VDD33_5 VDD33_6 VDD33_7 VDD33_8 VDD33_9 VDD33_10 VDD33_11 VDD33_12 VDD33_13

ROM_SCLK ROM_SI ROM_SO

TESTMODE SWAPRDY_A

MIOA_VDDQ_1 MIOA_VDDQ_2 MIOA_VDDQ_3 MIOA_VDDQ_4 MIOA_VDDQ_5 MIOB_VDDQ_1 MIOB_VDDQ_2 MIOB_VDDQ_3 MIOB_VDDQ_4 MIOB_VDDQ_5

MIOA_VREF MIOB_VREF

MIOACAL_PD_VDDQ MIOACAL_PU_GND

MIOBCAL_PD_VDDQ MIOBCAL_PU_GND

PLLVDD PLLGND

H_PLLVDD

VID_PLLVDD

XTALIN XTALOUT

XTALOUTBUFF

XTALSSIN

GPIO0 GPIO1 GPIO2 GPIO3

GPIO9

GPIO11

SPDIF

STEREO

JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS

MIOA_CLKOUT

MIOA_CTL3

MIOA_DE

MIOAD0 MIOAD1 MIOAD2 MIOAD3 MIOAD4 MIOAD5 MIOAD6 MIOAD7 MIOAD8

MIOAD9 MIOAD10 MIOAD11

MIOA_HSYNC MIOA_VSYNC

MIOB_CLKIN

MIOB_CLKOUT

MIOB_CTL3

MIOB_DE

MIOBD0

MIOBD1

MIOBD2

MIOBD3

MIOBD4

MIOBD5

MIOBD6

MIOBD7

MIOBD8

MIOBD9 MIOBD10 MIOBD11

MIOB_HSYNC MIOB_VSYNC

THERMDP THERMDN

GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO10

GPIO12

GPIO13

GPIO14

BUFRST_L

JTAG_TRST_L

MIOA_CLKOUT_L

MIOB_CLKOUT_L

ROMCS_L

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Page Notes

BOM options provided by this page:

(NONE)

Signal aliases required by this page:

40mA

(IPD)

(NONE)

- =PP1V2_GPU_VID_PLLVDD

- =PP1V2_GPU_H_PLLVDD

- =PP1V2_GPU_PLLVDD

- =PP3V3_GPI_MIO

- =PP3V3_GPU_VDD33

Power aliases required by this page:

40mA

Typically <??mA

U8000

F3

K3 H1

H5 F4 E3 U3 U4

K5 G5 E2 J5 G6 K6 E1 D2

G23

AJ11 AK12 AL12 AK11 AL13

R4 P4 P3 P1

R3

M7 M8 R8 T8 U9

L2

R1

L1 L3

P2 N2

L4 L5

N1 N3 M1 M3 P5 N6 N5 M4

AE4 AD4 AD5 AD3 AD1

AF3

AA8 AB7 AB8 AC6 AC7

Y2

AE3

Y1 Y3

AC3 AC1

AB4 AA5

AC2 AB2 AB1 AA1 AB3 AA3 AC5 AB5

U10

T9

AA7

W2

AA6

AA4

J6 T3

M6

H2

J1

K1

AC11

L10

L7 L8

M10

AC12 AC24 AD24 AE11 AE12

H7 J7 K7

T10

U1 U2

T2

T1

NB8P-GS-W-A2

OMIT

(6 OF 8)

BGA

R8696

1 2

402

5%

MF-LF

1/16W

10K

R8695

1

2

MF-LF

5%

1/16W

402

100K

C8601

1

2

CERM-X5R

6.3V

10%

0.47UF

402

C8602

1

2

CERM-X5R

6.3V

10%

0.47UF

402

C8636

1

2

10%

402

16V X5R

0.1uF

C8635

1

2

20%

6.3V CERM

603

4.7UF

L8635

1 2

0402

FERR-220-OHM

L8640

1 2

FERR-220-OHM

0402

C8617

1

2

402

X5R

16V

10%

0.1uF

R8616

1

2

10K

402

1/16W

5%

MF-LF

R8617

1

2

10K

1/16W

402

MF-LF

5%

R8620

1

2

402

MF-LF

1/16W

1%

49.9

R8622

1

2

402

1%

49.9

MF-LF

1/16W

R8621

1

2

402

MF-LF

1/16W

1%

49.9

C8619

1

2

0.1uF

10% 16V X5R 402

R8618

1

2

10K

5% 1/16W MF-LF 402

R8619

1

2

10K

5%

402

MF-LF

1/16W

C8611

1

2

402

CERM

1UF

10%

6.3V

C8610

1

2

CERM

1UF

10%

402

6.3V

R8623

1

2

1% 1/16W MF-LF 402

49.9

C8631

1

2

0.1uF

X5R

16V 402

10%

C8630

1

2

4.7UF

603

CERM

6.3V

20%

L8630

1 2

0402

FERR-220-OHM

C8633

1

2

4.7UF

603

CERM

6.3V

20%

C8641

1

2

10%

402

16V X5R

0.1uF

C8640

1

2

20%

6.3V CERM

603

4.7UF

C8643

1

2

4.7UF

603

CERM

6.3V

20%

C8637

1

2

20%

6.3V CERM

603

4.7UF

C8600

1

2

CERM-X5R

6.3V

10%

0.47UF

402

NV G84M GPIO/MIO/Misc

SYNC_DATE=(MASTER)

71 88

14.0.0

051-7225

SYNC_MASTER=(MASTER)

PP3V3_GPU

GPU_SWAPRDY_A

PP3V3_GPU

PP1V25_GPU

PP1V2_GPU_VID_PLLVDD_F

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.2V

PP1V25_GPU

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

PP1V2_GPU_PLLVDD_F

PP3V3_GPU

GPU_MIOA_VREF GPU_MIOB_VREF

TP_GPU_MIOA_VSYNC

GPU_MIOA_D<6>

GPU_XTALOUTBUFF

NC_GPU_XTALOUT

GPU_CLK27M_GATED

TP_GPU_MIOA_D<7> GPU_MIOA_D<8>

GPU_MIOA_PU_GND GPU_MIOB_PU_GND

GPU_MIOB_PD_VDDQ

GPU_MIOA_PD_VDDQ

GPU_MIOB_PU_GND

GPU_MIOB_PD_VDDQ

GPU_MIOA_PU_GND

GPU_MIOA_PD_VDDQ

NC_GPU_ROM_SI

GPU_CLK27M_SS_GATED

GPU_MIOB_D<10>

TP_GPU_MIOB_CLKOUT_P TP_GPU_MIOB_CLKOUT_N TP_GPU_MIOB_CTL3 TP_GPU_MIOB_DE

TP_GPU_MIOB_D<2> TP_GPU_MIOB_D<3> TP_GPU_MIOB_D<4> TP_GPU_MIOB_D<5> TP_GPU_MIOB_D<6> TP_GPU_MIOB_D<7> GPU_MIOB_D<8> GPU_MIOB_D<9>

GPU_MIOB_D<11>

TP_GPU_MIOB_VSYNC

TP_GPU_MIOA_HSYNC

GPU_MIOA_D<11>

GPU_MIOA_D<10>

GPU_MIOA_D<9>

GPU_MIOA_D<5>

GPU_MIOA_D<4>

GPU_MIOA_D<3>

GPU_MIOA_D<2>

GPU_MIOA_D<1>

GPU_MIOA_D<0>

TP_GPU_MIOA_DE

TP_GPU_MIOA_CTL3

TP_GPU_MIOA_CLKOUT_N

TP_GPU_MIOA_CLKOUT_P

GPU_VCORE_VID1 GPU_VGA_EN_L

NC_GPU_GPIO_1

GPU_VCORE_VID2

GPU_VCORE_PWRCTL1

NC_GPU_ROM_SCLK

NC_GPU_ROM_SO

GPU_TESTMODE_PD

TP_GPU_BUFRST_L

NC_GPU_STEREO

GPU_HPD

GPU_BL_PWM GPU_PANEL_EN

TP_GPU_GSTATE<0>

NC_GPU_SPDIF

TP_GPU_JTAG_TCK TP_GPU_JTAG_TDI TP_GPU_JTAG_TDO TP_GPU_JTAG_TMS

GPU_TDIODE_N

GPU_BKLT_EN GPU_VCORE_VID0

NC_GPU_GPIO_8

FB_VREF_UNTERM

GPU_GPIO_12

TP_GPU_JTAG_TRST_L

GPU_MIOB_HSYNC

GPU_TDIODE_P

TP_GPU_MIOB_CLKIN

GPU_MIOB_D<0> GPU_MIOB_D<1>

GPU_VCORE_PWRCTL0

NC_GPU_ROM_CS_L

VOLTAGE=1.2V

PP1V2_GPU_H_PLLVDD_F

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

PP1V25_GPU

77

76

74

73

77

73

77

72

74

72

74

71

65

68

65

72

68

57

66

57

86

70

87

66

48

57

48

72

74

76

77

72

77

74

69

72

74

57

8

72

30

72

71

72

30

72

51

72

68

72

51

72

8

IN

DB

DC

DD

EN_L

IN

S2D

S1D

S2C

S1C

S2B

S1B

S2A

S1A

DA

VCC

GND

THRML

PAD

OUT

IN

G

D S

G

D

S

OUT

BI

GND

VCC

NC

SDA

SCL

NC

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_5_ITEM

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

RAMCFG1 RAMCFG2 RAMCFG3

3GIO_PADCFG2

PEX_PLL_EN_TERM

MIOB_D<2>

MIOB_VSYNC, MIOB_D<10>

VID1

NC

SUBVENDOR

Supported straps: RAMCFG0

Unused Clocks

MEM_VID

MEM_VREF SLI_SYNC

AC_DET

PWR_CTL0

GPIOs

HPD1

VID0

FAN_PWM

THERM

Native Func

near GPU

Place Rs

Place Rs near GPU

MIOB_DE

BAR2_SIZE

PCI_IOBAR

SLOT_CLOCK_CFG

USER<3..0> ROMTYPE<1..0>

TVMODE<2..0>

CRYSTAL

3GIO_PADCFG3

3GIO_PADCFG0 3GIO_PADCFG1

PCI_DEVID<4..0>

(BIOS ROM PRESENT)

MIOB_CTL3, MIOB_D<11,3,5,4>

MIOB_D<6,10,7>

MIOB_D<7>

Renamed signals

Unused signals

Unused I2C Buses

Config Straps

LCD0_BL_PWM

I2CS ties into SMBus connection page

(I2CS requires pullups even if not used)

HPD0

HDCP Support

NC

IS

Analog Video Mux

MIOA_HSYNC

MIOA_D<5..2>

Straps not supported:

TMDS Backdrive Protection

LCD0_BL_EN

LCD0_VDD

PWR_CTL1

71 72 76

R8728

1

2

5%

MF-LF

402

1K

NO STUFF

1/16W

R8726

1

2

NO STUFF

402

5% 1/16W MF-LF

10K

R8724

1

2

VRAM_128

5% 1/16W MF-LF

402

10K

R8722

1

2

MF-LF

402

5%

1/16W

10K

R8720

1

2

VRAM_SAMSUNG

10K

5% 1/16W MF-LF

402

R8727

1

2

1/16W

10K

MF-LF

5%

402

R8725

1

2

VRAM_256

5% 1/16W MF-LF

402

10K

R8723

1

2

NO STUFF

10K

402

5% 1/16W MF-LF

R8721

1

2

VRAM_HYNIX

1/16W

10K

5%

MF-LF

402

R8729

1

2

NO STUFF

1K

402

MF-LF

1/16W

5%

R8730

1

2

1K

5% 1/16W MF-LF

402

NO STUFF

R8731

1

2

1K

5%

NO STUFF

1/16W MF-LF

402

R8732

1

2

1K

402

MF-LF

5%

1/16W

NO STUFF

R8733

1

2

MF-LF

1/16W

1K

5%

402

R8781

1

2

402

5% 1/16W MF-LF

10K

GPU_SS_INT

R8780

1

2

10K

402

5% 1/16W MF-LF

R8745

1

2

1%

150

402

MF-LF

1/16W

R8744

1

2

1%

150

MF-LF

1/16W

402

R8743

1

2

402

MF-LF

1/16W

1%

150

73 86

R8742

1

2

1%

150

402

MF-LF

1/16W

R8741

1

2

1%

150

MF-LF

1/16W

402

R8740

1

2

1/16W

1%

150

402

MF-LF

U8700

4

7

9

12

15

8

1

2

5

11

14

3

6

10

13

17

16

CRITICAL

TS3V330

QFN

OMIT

76 86

C8700

1 2

10V

0.1UF

20%

402

CERM

R8700

1

2

5% 1/16W MF-LF 402

10K

71 72 74

65 74

R8791

1

2

5%

MF-LF

402

1/16W

100K

Q8790

3

1

2

CRITICAL

SOT-23

SI2305DS

Q8925

3

5

4

SOT-363

2N7002DW-X-F

R8790

1

2

MF-LF 402

5% 1/16W

10K

71 72 74

C8770

1 2

HDCP

10V

0.1UF

20%

402

CERM

R8770

1

2

HDCP

1/16W

5%

MF-LF

402

10K

R8771

1

2

10K

402

MF-LF

5%

1/16W

HDCP

73

U8770

4

12

3

76

5

8

CRITICAL

SOI

AT88SC080C

HDCP

68 69 70 71 72

71 72 77

353S1579 353S1718

ALL (U8700)

TS3V330 alt to TS3V340

353S1718

1

U8700

CRITICAL

IC,TS3V340,QUAD VIDEO SW,QFN16

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

051-7225

14.0.0

8872

GPU Straps

GPU_VCORE_VID2

TP_GPU_GSTATE<0>

GPU_VGA_EN_L

GPU_VCORE_VID1

GPU_VCORE_VID0

GPU_BKLT_EN

GPU_GPIO_12

GPU_MIOA_D<0>

NC_GPU_GPIO_1

GPU_PANEL_EN

TP_GPU_GSTATE<0>

MAKE_BASE=TRUE

GPU_VGA_R

GPU_BL_PWM

PP3V3_GPU

GPU_MIOB_D<9>

PP3V3_GPU

GPU_CLK27M_SS_GATED

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_I2CA_SDA NC_GPU_I2CA_SDA

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_I2CA_SCL NC_GPU_I2CA_SCL

NC_FB_A_MA13

NC_FB_B_MA12

NC_FB_B_MA13

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FB_A_MA13

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FB_B_MA12

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FB_B_MA13GPU_PANEL_DDC_DATA

GPU_PANEL_DDC_CLK

GPU_DVI_DDC_DATA

NC_GPU_XTALOUT

NC_GPU_SPDIF

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_SPDIF

NC_GPU_STEREO

GPU_CLK27M_SS_GATED

MAKE_BASE=TRUE

GPU_CLK27M_SS_GATED

GPU_TDIODE_P

MAKE_BASE=TRUE

GPU_TDIODE_P

GPU_CLK27M_GATED

MAKE_BASE=TRUE

GPU_CLK27M_GATED

MAKE_BASE=TRUE

GPU_PANEL_DDC_CLK

MAKE_BASE=TRUE

GPU_DVI_DDC_CLK

MAKE_BASE=TRUE

GPU_DVI_DDC_DATA

MAKE_BASE=TRUE

GPU_PANEL_DDC_DATA

GPU_XTALOUTBUFF

GPU_MIOA_D<6>

GPU_MIOB_D<0>

GPU_VGA_EN_L

GPU_VGA_B

GPU_TV_Y_VGA_G

GPU_TV_COMP_VGA_B

GPU_TV_C_VGA_R

MAKE_BASE=TRUE

GPU_HPD

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_GPIO_1

MAKE_BASE=TRUE

GPU_BL_PWM

MAKE_BASE=TRUE

GPU_BKLT_EN

GPU_PANEL_EN

MAKE_BASE=TRUE

GPU_VGA_EN_L

NO_TEST=TRUE

NC_GPU_GPIO_8

MAKE_BASE=TRUE

TP_GPU_GSTATE<1>

MAKE_BASE=TRUE

GPU_VCORE_VID0

MAKE_BASE=TRUE

GPU_VCORE_PWRCTL1

FB_VREF_UNTERM

MAKE_BASE=TRUE

GPU_VCORE_VID2

PM_GPUVCORE_EN

PP3V3_GPU_TMDS

GPU_TMDS_PWREN_L

MAKE_BASE=TRUE

GPU_VCORE_PWRCTL0 GPU_VCORE_PWRCTL1

MAKE_BASE=TRUE

NC_FB_A_MA12

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FB_A_MA12

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_STEREO

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_XTALOUT

GPU_DVI_DDC_CLK

GPU_TDIODE_N

MAKE_BASE=TRUE

GPU_TDIODE_N

NC_LVDS_U_DATAN<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_U_DATAN<3>

NC_LVDS_L_DATAP<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_L_DATAP<3>

NC_GPU_CSYNC

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_CSYNC

NC_LVDS_L_DATAN<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_L_DATAN<3>

NC_GPU_IFPD_CLK_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_IFPD_CLK_P

NC_GPU_IFPD_CLK_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_IFPD_CLK_N

TP_GPU_MIOA_CLKOUT_P

MAKE_BASE=TRUE

TP_GPU_MIOA_CLKOUT_P

TP_GPU_MIOA_D<7>

MAKE_BASE=TRUE

TP_GPU_MIOA_D<7>

GPU_MIOA_D<5..2>

MAKE_BASE=TRUE

TP_GPU_MIOA_D<5..2>

GPU_MIOA_D<11..10>

MAKE_BASE=TRUE

TP_GPU_MIOA_D<11..10>

GPU_MIOB_D<7..2>

MAKE_BASE=TRUE

TP_GPU_MIOB_D<7..2>

GPU_MIOB_D<11..10>

MAKE_BASE=TRUE

TP_GPU_MIOB_D<11..10>

NC_GPU_G2

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_G2

NC_GPU_B2

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_B2

NC_GPU_R2

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_R2

NC_GPU_H2SYNC

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_H2SYNC

TP_GPU_MIOA_CLKOUT_N

MAKE_BASE=TRUE

TP_GPU_MIOA_CLKOUT_N

TP_GPU_MIOA_CTL3

MAKE_BASE=TRUE

TP_GPU_MIOA_CTL3

TP_GPU_MIOA_DE

MAKE_BASE=TRUE

TP_GPU_MIOA_DE

TP_GPU_MIOA_HSYNC

MAKE_BASE=TRUE

TP_GPU_MIOA_HSYNC

NC_GPU_V2SYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_V2SYNC

TP_GPU_MIOA_VSYNC

MAKE_BASE=TRUE

TP_GPU_MIOA_VSYNC

TP_GPU_MIOB_CLKOUT_P

MAKE_BASE=TRUE

TP_GPU_MIOB_CLKOUT_P

TP_GPU_MIOB_CLKOUT_N

MAKE_BASE=TRUE

TP_GPU_MIOB_CLKOUT_N

TP_GPU_MIOB_DE

MAKE_BASE=TRUE

TP_GPU_MIOB_DE

TP_GPU_MIOB_CTL3

MAKE_BASE=TRUE

TP_GPU_MIOB_CTL3

TP_GPU_MIOB_VSYNC

MAKE_BASE=TRUE

TP_GPU_MIOB_VSYNC

TP_GPU_MIOB_CLKIN

MAKE_BASE=TRUE

TP_GPU_MIOB_CLKIN

NC_LVDS_U_DATAP<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_U_DATAP<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FBA_CMD27

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FBC_CMD27 NC_FBC_CMD27

NC_FBA_CMD27

NC_FBA_CMD28

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FBA_CMD28

NC_FBC_CMD28

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FBC_CMD28

NC_GPU_ROM_SO

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_ROM_SO

NC_GPU_ROM_SI

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_ROM_SI

NC_GPU_ROM_SCLK

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_ROM_SCLK

NC_GPU_ROM_CS_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_ROM_CS_L

GPU_MIOB_D<1>

PP3V3_GPU

GPU_VCORE_PWRCTL0

GPU_MIOB_HSYNC

GPU_I2CH_SDA

PP3V3_GPU

GPU_I2CH_SCL

GPU_HPD

MAKE_BASE=TRUE

GPU_VCORE_VID1

MAKE_BASE=TRUE

FB_VREF_UNTERM

GPU_MIOB_D<8>

GPU_MIOA_D<8>

GPU_TV_COMP

GPU_TV_Y

GPU_TV_C

GPU_VGA_G

GPU_MIOA_D<1>

GPU_MIOA_D<9>

NC_GPU_GPIO_8

77

76

74

73

72

71

72

71

65

86

87 87

86 86

71

65

74

77

57

72

77

76

72

72 72

77

76

77

74

70

76

72

57

74

57

76

72

48

71

73 73

72

72 73

73

72

72 72

72

71

71 71

73

72

69

73

72 72

72

73

71

73 73

73

72 72

73 73

72 72

73 73

72 72

73 73

72

72 72

72

72 72

48

72

48

72

71

8

71

8

30

72 72

68

68 72

72

71

71 71

71

30

51 51

30 30

72

71

68

8

68 68

71

72

51

72 72

72

71 71

71

72 72

71 71

72 72

71 71

72 72

68

68 68

68

68 68

71 71

71

8

71

8

71

OUT OUT OUT

OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT

OUT OUT OUT OUT OUT OUT

BI BI

OUT

IFPA_TXD0

I2CB_SDA

I2CB_SCL

I2CA_SDA

I2CA_SCL

DACC_VSYNC

DACC_HSYNC

DACC_BLUE

DACC_GREEN

DACC_RED

DACB_CSYNC

DACB_BLUE

DACB_GREEN

DACB_RED

DACA_VSYNC

DACA_HSYNC

DACA_BLUE

DACA_GREEN

DACA_RED

IFPD_TXD6

IFPD_TXD5

IFPD_TXD4

IFPD_TXC

IFPC_TXD2

IFPC_TXD1

IFPC_TXD0

IFPC_TXC

IFPB_TXD7

IFPB_TXD6

IFPB_TXD5

IFPB_TXD4

IFPB_TXC

IFPA_TXD3

IFPA_TXD2

IFPA_TXD1

IFPA_TXC

I2CS_SDA

I2CS_SCL

I2CH_SDA

I2CH_SCL

I2CC_SDA

I2CC_SCL

DACC_RSET

DACC_VREF

DACC_IDUMP

DACC_VDD

DACB_RSET

DACB_VREF

DACB_IDUMP

DACB_VDD

DACA_RSET

DACA_VREF

DACA_IDUMP

DACA_VDD

IFPCD_RSET

IFPCD_VPROBE

IFPCD_PLLGND

IFPCD_PLLVDD

IFPD_IOVDD

IFPC_IOVDD

IFPAB_RSET

IFPAB_VPROBE

IFPAB_PLLGND

IFPB_IOVDD

IFPA_IOVDD

IFPAB_PLLVDD

IFPA_TXC_L

IFPA_TXD0_L

IFPA_TXD1_L

IFPA_TXD2_L

IFPA_TXD3_L

IFPB_TXC_L

IFPB_TXD4_L

IFPB_TXD5_L

IFPB_TXD6_L

IFPB_TXD7_L

IFPC_TXC_L

IFPC_TXD0_L

IFPC_TXD1_L

IFPC_TXD2_L

IFPD_TXC_L

IFPD_TXD4_L

IFPD_TXD5_L

IFPD_TXD6_L

OUT OUT

OUT

BI BI BI BI BI BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

I2CS addr fixed at 0x9E,0x9F

I2CS must be pulled up if not used

- =PP3V3_GPU_DAC

- =PP1V8_GPU_IFPX

(NONE)

C R Pr Y G Y Comp B Pb

Composite/S-Video VGA Component

Place at AF8Place at AF9

40mA peak

Place at AE7

40mA peak

120mA peak

150mA peak

120mA peak

Sum of peak currents: 390mA

- =PP3V3_GPU_IFPCD_IOVDD

BOM options provided by this page:

Place at AD6

20mA peak per diff pair 200mA peak for all pairs

160mA peak for all pairs

20mA peak per diff pair

Sum of peak currents: 240mA

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

R8850

1

2

MF-LF 402

1% 1/16W

1K

NO STUFF

L8805

1 2

0402

FERR-220-OHM

C8806

1

2

20%

0.1UF

10V 402

CERM

L8815

1 2

FERR-220-OHM

0402

L8830

1 2

FERR-220-OHM

0402

L8820

1 2

FERR-220-OHM

0402

L8840

1 2

FERR-220-OHM

0402

NO STUFF

72 86

77 86

72

77 86

7

77 86

7

77 86

7

77 86

72

76 86

72

72 76

C8805

1

2

4.7UF

20%

CERM

6.3V 603

C8820

1

2

4.7UF

603

CERM

6.3V

20%

72

72 86

U8000

AH12

AJ12

AF10

AG9

AH11

AH9

AD10

AH10

AK10

T6

U5

T5V7

R6

R7

V8

R5

AE5

AG6

AG7

AG4

AF6

AF5

AD7

AH4

AG5

K2 J3

H4 J4

G2 G1 G3 H3 C1 B1

AF9 AK9

AJ9

AH6 AJ6 AH8 AH7 AJ8 AK8 AJ5 AH5

AD9

AC9

AL5

AM4

AF8

AK4 AL4

AM6 AM5 AM7 AL7 AK6 AK5 AK7 AL8

AD6 AM2

AM3

AE2 AE1 AF1 AF2 AG1 AH1

AB10

AA10

AH3

AK3

AE7

AG3 AH2

AK1 AJ1 AL2 AL1 AJ2 AJ3

NB8P-GS-W-A2

BGA

(5 OF 8)

OMIT

72

R8852

1

2

1/16W 402

MF-LF

124

1%

R8853

1

2

1/16W 402

MF-LF

124

1%

R8854

1

2

1/16W MF-LF 402

124

1%

72

C8852

1

2

0.1UF

CERM 402

20% 10V

C8853

1

2

0.1UF

10V

20% CERM

402

C8854

1

2

0.1UF

10V

20% CERM

402

72 77

72

45 48 51 84

C8821

1

2

20%

0.1UF

10V 402

CERM

C8831

1

2

20%

0.1UF

10V CERM 402

C8830

1

2

20%

6.3V CERM 603

4.7UF

C8841

1

2

20% 10V CERM 402

0.1UF

C8840

1

2

4.7UF

603

CERM

6.3V

20%

NO STUFF

C8845

1

2

20%

6.3V CERM

603

4.7UF

C8815

1

2

4.7UF

CERM

603

6.3V

20%

C8801

1

2

20%

0.1UF

10V 402

CERM

C8800

1

2

4.7UF

20%

CERM

6.3V 603

L8800

1 2

0402

FERR-220-OHM

C8803

1

2

402

CERM

10V

0.1UF

20%

C8856

1

2

CERM 402

0.01UF

16V

20%

NO STUFF

C8855

1

2

CERM 402

0.01UF

16V

20%

NO STUFF

C8813

1

2

402

CERM

10V

0.1UF

20%

C8811

1

2

20%

0.1UF

10V 402

CERM

C8810

1

2

20%

6.3V 603

CERM

4.7UF

L8810

1 2

0402

FERR-220-OHM

C8816

1

2

20%

0.1UF

10V 402

CERM

R8851

1

2

MF-LF 402

1% 1/16W

1K

NO STUFF

051-7225

14.0.0

8873

NV G84M Video Interfaces

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

GPU_I2CH_SCL GPU_I2CH_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA

MIN_NECK_WIDTH=0.2 mm

PP1V8_GPU_IFPCD_PLLVDD_F

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.3 mm

TMDS_DATA_N<5>

TMDS_DATA_N<4>

TMDS_DATA_N<3>

NC_GPU_IFPD_CLK_N

TMDS_DATA_N<2>

TMDS_DATA_N<1>

TMDS_DATA_N<0>

TMDS_CLK_N

NC_LVDS_U_DATAN<3>

LVDS_U_DATA_N<2>

LVDS_U_DATA_N<1>

LVDS_U_DATA_N<0>

LVDS_U_CLK_N

NC_LVDS_L_DATAN<3>

LVDS_L_DATA_N<2>

LVDS_L_DATA_N<1>

LVDS_L_DATA_N<0>

LVDS_L_CLK_N

GPU_IFPAB_VPROBE GPU_IFPAB_RSET

GPU_IFPCD_VPROBE GPU_IFPCD_RSET

GPU_DACA_VREF GPU_DACA_RSET

GPU_DACB_VREF GPU_DACB_RSET

LVDS_L_CLK_P

LVDS_L_DATA_P<1>

LVDS_L_DATA_P<2>

NC_LVDS_L_DATAP<3>

LVDS_U_CLK_P

LVDS_U_DATA_P<0>

LVDS_U_DATA_P<1>

LVDS_U_DATA_P<2>

NC_LVDS_U_DATAP<3>

TMDS_CLK_P

TMDS_DATA_P<0>

TMDS_DATA_P<1>

TMDS_DATA_P<2>

NC_GPU_IFPD_CLK_P

TMDS_DATA_P<3>

TMDS_DATA_P<4>

TMDS_DATA_P<5>

GPU_VGA_R

GPU_VGA_B

GPU_VGA_HSYNC GPU_VGA_VSYNC

GPU_TV_C GPU_TV_Y GPU_TV_COMP

NC_GPU_CSYNC

NC_GPU_R2

NC_GPU_H2SYNC NC_GPU_V2SYNC

NC_GPU_I2CA_SCL NC_GPU_I2CA_SDA

GPU_DVI_DDC_CLK GPU_DVI_DDC_DATA

LVDS_L_DATA_P<0>

PP3V3_GPU

PP3V3_GPU_DACC_VDD_F

MIN_LINE_WIDTH=0.35 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

PP3V3_GPU_DACB_VDD_F

MIN_LINE_WIDTH=0.35 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

PP3V3_GPU_DACA_VDD_F

MIN_LINE_WIDTH=0.35 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm

PP3V3_GPU_IFPCD_IOVDD_F

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP1V8_GPU_IFPAB_PLLVDD_F

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.4 mm

PP1V8_GPU_IFPAB_IOVDD_F

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

PP3V3_GPU_TMDS

GPU_DACB_RSET GPU_DACC_RSET

GPU_IFPCD_RSET

GPU_IFPAB_RSET

GPU_DACA_VREFGPU_DACA_RSET

GPU_DACC_VREF

GPU_DACB_VREF

GPU_IFPCD_VPROBE

GPU_IFPAB_VPROBE

PP1V8_GPU

GPU_DACC_VREF GPU_DACC_RSET

GPU_PANEL_DDC_CLK GPU_PANEL_DDC_DATA

NC_GPU_B2

NC_GPU_G2

GPU_VGA_G

77 76 74

77

72

70

71

69

65

68

57

76

67

48

72

57

73

8

73

73 73

73

8

73

OUT

V-

V+

+

-

THRM_PAD

VFB

TRIP

VOUT

EN_PSV

GND

PGND

V5DRV

V5FILT

DRVL

DRVH

LL

TON

VBST

PGOOD

SYM (2 OF 2)

IN

OUT

G

D

S

G

D

S

G

D

S

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

<Rb>

GPU VCore Regulator

<Ra>

(GPUVCORE_VFB)

GPU VCore Setpoints

VID1 VID0

- - -

1.050V (max batt)

1.050V (rsvd state)

1.050V (balanced)

1.125V (max perf)

All other states not defined

Y Y -

Y - -

C D E State

VID2

0

1

0

0 1

0

1

1 1

0 0

1

Y Y Y

Place near C8940

Vout = 0.75V * (1 + Ra / Req)

Vout = 1.25V - 0.96V

(=PPVCORE_GPU_REG)

Vout(min) = 0.75V * (1 + Ra / Rb)

(GPUVCORE_VFB)

(L8920 limit)

18A max output

(GND)

(GPUVCORE_TON)

(=PPVCORE_GPU_REG)

Req = Rb || Rc || Rd || Re

GPU VCore Current Sense

R8921

1

2

2.87K

1/16W MF-LF

1%

402

R8922

1

2

7.15K

402

1%

MF-LF

1/16W

C8940

1

2

603

X5R

10UF

20%

6.3V

C8921

1

2

NO STUFF

402

25V X7R

1000pF

10%

R8923

1

2

NO STUFF

1% 1/16W MF-LF 402

61.9K

C8998

12

10%

470pF

CERM

402

50V

49

C8992

12

10%

CERM

470pF

50V 402

R8998

1 2

1/16W

1%

1M

MF-LF

402

R8992

1 2

1/16W MF-LF

1%

1M

402

C8995

1

2

6.3V

10%

402

CERM

1uF

R8993

1 2

20.0K

MF-LF

402

1/16W

1%

R8991

1 2

MF-LF

402

20.0K

1%

1/16W

R8990

1

2

PLACEMENT_NOTE=Place R8990 close to L8920

1/16W MF-LF

402

1%

649

R8994

1 2

PLACEMENT_NOTE=Place R8994 close to L8920

NO STUFF

1%

1K

402

MF-LF

1/16W

C8990

12

PLACEMENT_NOTE=Place C8990 close to L8920

402

6.3V

0.47UF

CERM-X5R

10%

R8997

1

2

PLACEMENT_NOTE=Place R8997 close to L8920

CRITICAL

10KOHM-5%

0603-LF

R8996

1

2

MF-LF

1/16W

1K

1%

402

C8920

1

2

5%

100PF

402

50V CERM

NO STUFF

C8930

1

2

CASE-D2-LF

22UF

25V

20%

POLY

CRITICAL

Q8920

5

4

1 2 3

CRITICAL

RJK0305DPB

LFPAK

Q8922

5

4

1 2 3

LFPAK

RJK0301DPB

CRITICAL

Q8921

5

4

1 2 3

CRITICAL

LFPAK

RJK0301DPB

L8920

1 2

CRITICAL

IHLP4040DZ11-SM

1.0UH-20A

C8991

12

PLACEMENT_NOTE=Place C8991 close to L8920

10%

402

6.3V

0.22UF

CERM-X5R

U8995

1

3

4

2

5

HPA00141AIDCKR

SC70-5

CRITICAL

R8919

1

2

402

MF-LF

1/16W

1%

200K

C8915

1

2

10V

0.1UF

CERM

402

20%

R8915

1

2

MF-LF

402

1/16W

5%

0

C8900

1

2

10% 603

X5R

16V

1uF

U8900

13

9

1

7

12

8

6

15

2

11

10

4

14

5

3

CRITICAL

TPS51117RGY_QFN14

QFN

C8901

1

2

2.2UF

603

X5R

10% 16V

XW8900

1 2

SM

65 72

57 65

R8905

1

2

MF-LF

10.5K

1%

402

1/16W

R8901

1

2

200

402

MF-LF

1/16W

1%

R8973

1 2

1/16W

5%

402

7.5K

MF-LF

Q8923

3

5

4

2N7002DW-X-F

SOT-363

Q8923

6

2

1

SOT-363

2N7002DW-X-F

R8974

1 2

402

MF-LF

5%

1/16W

7.5K

Q8925

6

2

1

2N7002DW-X-F

SOT-363

R8975

1 2

7.5K

402

MF-LF

5%

1/16W

71 72

R8970

1

2

100K

5%

MF-LF

1/16W

402

R8971

1

2

100K

1/16W MF-LF

402

5%

71 72

R8924

1

2

NO STUFF

402

MF-LF

1/16W

1%

30.1K

R8925

1

2

28K

402

MF-LF

1/16W

1%

C8973

1

2

20% 10V CERM 402

0.1UF

C8974

1

2

20% 10V CERM 402

0.1UF

C8975

1

2

20% 10V CERM 402

0.1UF

R8972

1

2

5%

402

MF-LF

1/16W

100K

71 72

C8932

1

2

X5R

25V

1UF

10%

603

C8931

1

2

CRITICAL

POLY

20% 25V

CASE-D2-LF

22UF

C8942

1

2 3

TANT

D2T

10%

330UF

2.0V

CRITICAL

C8943

1

23

CRITICAL

2.0V

330UF

10%

D2T

TANT

XW8920

1

2

SM

71 72

R8967

1

2

NO STUFF

1.5K

1/16W MF-LF 402

5%

R8962

1

2

NO STUFF

1K

5% MF-LF

1/16W 402

R8960

1 2

NO STUFF

1%

1/16W

4.99K

MF-LF

402

R8965

1 2

NO STUFF

1%

4.99K

402

MF-LF

1/16W

C8961

1 2

NO STUFF

402

CERM

0.01UF

10% 16V

C8966

1 2

NO STUFF

16V

CERM

10%

0.01UF

402

R8966

1

2

NO STUFF

402

MF-LF

1/16W

5%

1K

R8961

1

2

NO STUFF

1K

5%

MF-LF

1/16W

402

R8963

1

2

NO STUFF

402

1/16W MF-LF

5%

1.5K

R8968

1

2

NO STUFF

1/16W 402

5% MF-LF

1K

R8964

1 2

NO STUFF

402

MF-LF

5%

1/16W

10K

R8969

1 2

NO STUFF

10K

1/16W

5%

MF-LF

402

Q8927

5

3

4

NO STUFF

SOT-363-LF

MMDT3904XF

Q8927

2

6

1

NO STUFF

MMDT3904XF

SOT-363-LF

R8927

1

2

53.6K

402

MF-LF

1/16W

1%

NO STUFF

R8926

1

2

53.6K

402

MF-LF

1/16W

1%

NO STUFF

XW8901

1

2

SM

GPU (G84M) Core Supply

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

74 88

051-7225

14.0.0

GPU_VCORE_PWRCTL0

PVCORE_GPU_NTC

GPUVCORE_TON

PP3V3_GPU

GPU_VCORE_VID2_RC

GPU_VCORE_VID1_RC

GND_GPUVCORE_SGND

GPUISENS_NTC

PP3V3_S0

GPUVCORE_IOUT

GPUISENS_NEG

GPUISENS_POS

GPUISENS_RC

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

GPUVCORE_BOOT_R

PM_GPUVCORE_EN

GND_GPUVCORE_SGND

PM_GPUP1V8FET_EN

GPUVCORE_VFB_E

MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

GPUVCORE_DRVH

MIN_LINE_WIDTH=0.6 mm

PPBUS_G3H

GPUVCORE_TRIP

GPU_VCORE_VID0

GPUVCORE_VFB_PC0

GPUVCORE_VFB_PC1

GND_GPUVCORE_SGND

GPU_VCORE_VID1

GND_GPUVCORE_SGND

GPUVCORE_VBST

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

PP5V_S5

PC0_BIAS_B

PC1_BIAS_B

GPU_VCORE_PWRCTL1

PP1V25_GPU

PC0_BIAS

PC0_DIV

PC1_BIAS

PC1_DIV

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm VOLTAGE=5V

PP5V_S5_GPUVCORE_V5FILT

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

GPUVCORE_LL

MIN_NECK_WIDTH=0.2 mm

GPUVCORE_VFB_PC1

GND_GPUVCORE_SGND

GPUVCORE_VFB_PC0

GPU_VCORE_VID2

GPU_VCORE_VID0_RC

GND_GPUVCORE_SGND

MIN_LINE_WIDTH=0.6 mm VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

PPVCORE_GPU_XW

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.25 mm VOLTAGE=1.25V

GPUVCORE_DRVL

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GPUVCORE_VFB_C

PPVCORE_GPU

GPUVCORE_VFB_D

GPUVCORE_VFB

87 77 75 65 59 58 57 52 51 50 48 47 46 42 32 31 30 29

63

28

62

27

61

65

77

26

60

63

76

25

59

62

73

24

58

61

72

23

57

60

77

71

21

56

57

71

65

19

49

43

68

67

57

16

40

27

66

49

48

13

8

9

57

8

74

8

74

7

74

8

74

7

D

S

G

D

S

IN

SYM_VER-1

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

LCD (LVDS) INTERFACE

100K pull-ups are for no-panel case (development). Panel has 2K pull-ups

518S0289

C9010

1

2

50V

20%

402

CERM

0.001uF

C9001

1

2

402

CERM

50V

0.001uF

20%

L9000

FERR-250-OHM

SM

CRITICAL

C9000

1 2

50V

10%

402

CERM

0.0022uF

R9001

1/16W

5%

402

MF-LF

100K

R9000

1

2

1/16W

5%

402

MF-LF

100K

Q9000

1

2

5

63

4

TSOP-LF

SI3443DV

Q9001

3

1

2

SOT23-LF

2N7002

R9094

1

2

1/16W

5%

402

100K

MF-LF

R9011

1

2

1/16W

5%

402

MF-LF

100K

R9010

1

2

1/16W

5%

MF-LF

100K

402

77

J9000

33

34

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26 27 28 29

3

30

4 5 6 7 8 9

CRITICAL

F-RT-SM

MSC-RB30-5-FA

L9010

1

2 3

4

CRITICAL

1210-4SM1

90-OHM-100MA

PLACEMENT_NOTE=Place close to connector.

L9011

1

2 3

4

PLACEMENT_NOTE=Place close to connector.

90-OHM-100MA

1210-4SM1

CRITICAL

75 88

14.0.0

051-7225

LVDS Display Connector

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

PP3V3_S5

LVDS_U_CLK_CONN_P

LVDS_U_CLK_CONN_N

LVDS_PANEL_EN

LVDS_L_CLK_CONN_P

LVDS_L_CLK_CONN_N

LVDS_U_DATA_CONN_P<2>

LVDS_U_DATA_CONN_N<2>

LVDS_U_DATA_CONN_P<1>

LVDS_U_DATA_CONN_N<1>

LVDS_U_DATA_CONN_P<0>

LVDS_L_DATA_CONN_N<1> LVDS_L_DATA_CONN_P<1>

LVDS_L_DATA_CONN_N<2> LVDS_L_DATA_CONN_P<2>

LVDS_U_DATA_CONN_N<0>

LVDS_L_DATA_CONN_N<0> LVDS_L_DATA_CONN_P<0>

LCD_PWREN_L

LCD_PWREN_L_RC

PP3V3_SW_LCD_UF

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm VOLTAGE=3.3V

LVDS_CONN_DDC_DATA

LVDS_CONN_DDC_CLK

PP3V3_S0

LVDS_U_CLK_CONN_F_P

LVDS_U_CLK_CONN_F_N

LVDS_L_CLK_CONN_F_P

LVDS_L_CLK_CONN_F_N

VOLTAGE=3.3V

PP3V3_SW_LCD

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

87 77 74 65 59 58 57 52 51 50 48 47 46 42 32 31

87

30

65

29

60

28

57

27

55

26

48

25

46

24

28

23

27

21

26

19

25

16

24

87

77

13

8

77

15

8

87

G

SD

G

SD

SYM_VER-1

G

SD

SYM_VER-1

OUT

IN

OUT

G

S

D

G

S

D

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

514-0278

(55mA requirement per DVI spec)

DVI INTERFACE

DVI DDC Current Limit

Isolation required for DVI->ADC Adapter

GPU Isolation / Level-Shift

(PP5V_S0_DDC)

VGA SYNC Buffers

PLACE CLOSE TO CONNECTOR

ANALOG FILTERING

(Place close to connector)

(DACB TV C)

(DACB TV COMP)

(DACB TV Y)

TMDS Filtering

(Place close to GPU)

R9421

1

2

1/16W

5%

402

MF-LF

10K

R9420

1

2

1/16W

5%

402

MF-LF

10K

Q9411

6

2

1

SOT-363

2N7002DW-X-F

Q9411

3

5

4

SOT-363

2N7002DW-X-F

R9422

1

2

1/16W

5%

402

MF-LF

270K

C9413

1

2

100pF

CERM 402

5% 50V

R9412

1

2

4.7K

MF-LF 402

5% 1/16W

R9410

1

2

4.7K

MF-LF

402

5%

1/16W

C9411

1

2

50V

5%

402

CERM

100pF

C9410

1

2

0.01uF

CERM

603

20% 50V

L9410

1 2

CRITICAL

SM-1

400-OHM-EMI

F9410

1 2

SM-LF

0.5AMP-13.2V

CRITICAL

D9410

1 2

B0530WXF

SOD-123

C9414

1

2

100pF

CERM 402

5% 50V

R9411

1 2

100

MF-LF

402

5%

1/16W

R9413

1 2

100

MF-LF

402

5%

1/16W

R9414

1 2

1/16W

5%

402

MF-LF

100

C9441

1

2

3.3pF

CERM 402

0.25% 50V

R9442

1

2

1%

1/16W

150

MF-LF

402

VGA_TERM_FILTER

R9440

1

2

150

MF-LF

402

1%

1/16W

VGA_TERM_FILTER

R9441

1

2

150

1/16W

1%

402

MF-LF

VGA_TERM_FILTER

C9442

1

2

3.3pF

CERM 402

0.25% 50V

C9440

1

2

50V

0.25% 402

CERM

3.3pF

R9450

1 2

1/16W

5%

402

MF-LF

33

R9451

1 2

1/16W

5%

402

MF-LF

33

J9400

C1

C2

C3

C4

C5AC5B

31

32

33

34

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

3

4

5

6

7

8

9

CRITICAL

QH11121-RIG02-4F

F-RT-TH-DVI

R9415

1

2

1/16W

5%

402

MF-LF

20K

R9486

1

2

NO STUFF

MF-LF

402

SIGNAL_MODEL=EMPTY

49.9

1%

1/16W

R9482

1

2

49.9

NO STUFF

1/16W

1%

402

MF-LF

SIGNAL_MODEL=EMPTY

R9478

1

2

49.9

NO STUFF

1/16W

1%

402

MF-LF

SIGNAL_MODEL=EMPTY

R9473

1 2

0

MF-LF

402

5%

1/16W

R9472

1 2

1/16W

5%

402

MF-LF

0

R9470

1

2

49.9

NO STUFF

MF-LF

402

1%

1/16W

SIGNAL_MODEL=EMPTY

R9466

1

2

NO STUFF

MF-LF

402

1%

SIGNAL_MODEL=EMPTY

1/16W

49.9

L9472

1

2 3

4

370-OHM

CRITICAL

PLACEMENT_NOTE=Place close to connector.

SM

C9451

1

2

10V

20% 402

CERM

0.1uF

C9450

1

2

10V

20% 402

CERM

0.1uF

U9450

3

2

1

4

5

SC70

MC74VHC1G08

PLACEMENT_NOTE=Place close to connector.

U9451

3

2

1

4

5

PLACEMENT_NOTE=Place close to connector.

SC70

MC74VHC1G08

R9462

1

2

1%

1/16W

402

MF-LF

49.9

NO STUFF

SIGNAL_MODEL=EMPTY

Q9415

6

2

1

SOT-363

2N7002DW-X-F

R9423

1

2

1/16W

5%

402

MF-LF

270K

L9460

1

2 3

4

PLACEMENT_NOTE=Place close to connector.

CRITICAL

1210-4SM1

90-OHM-100MA

L9464

1

2 3

4

90-OHM-100MA

1210-4SM1

CRITICAL

PLACEMENT_NOTE=Place close to connector.

L9468

1

2 3

4

1210-4SM1

90-OHM-100MA

CRITICAL

PLACEMENT_NOTE=Place close to connector.

L9480

1

2 3

4

CRITICAL

PLACEMENT_NOTE=Place close to connector.

1210-4SM1

90-OHM-100MA

L9476

1

2 3

4

CRITICAL

1210-4SM1

90-OHM-100MA

PLACEMENT_NOTE=Place close to connector.

L9484

1

2 3

4

1210-4SM1

PLACEMENT_NOTE=Place close to connector.

90-OHM-100MA

CRITICAL

24

73 86

72 86

72 73

Q9414

6

2

1

SOT-363

2N7002DW-X-F

Q9414

3

5

4

SOT-363

2N7002DW-X-F

28 77

71 72

C9462

1

2

NO STUFF

0.01UF

10%

402

CERM

16V

C9466

1

2

CERM

402

10%

0.01UF

16V

NO STUFF

C9470

1

2

16V

0.01UF

NO STUFF

CERM

402

10%

C9478

1

2

NO STUFF

CERM

402

10%

0.01UF

16V

C9482

1

2

NO STUFF

CERM

402

10%

0.01UF

16V

C9486

1

2

16V

0.01UF

10%

402

CERM

NO STUFF

C9474

1

2

16V

0.01UF

10%

402

CERM

NO STUFF

R9474

1

2

49.9

NO STUFF

MF-LF

402

1%

1/16W

SIGNAL_MODEL=EMPTY

FL9440

27

36

45

18

MEA2010P-SM

210MHZ

CRITICAL

CX9491

1

2

NONE

SHORT

NONE 402

OMIT

CX9490

1

2

NONE

SHORT

NONE 402

NONE

OMIT

CX9492

1

2

402

NONE

SHORT

NONE NONE

OMIT

CX9493

1

2

OMIT

402

NONE

SHORT

NONE NONE

CX9403

1

2

OMIT

NONE

SHORT

NONE NONE

402

CX9402

1

2

402

NONE

SHORT

NONE

OMIT

CX9401

1

2

402

NONE

NONE NONE

SHORT

OMIT

CX9400

1

2

402

NONE

SHORT

NONE

OMIT

R9463

12

402

MF-LF

1%

49.9

NO STUFF

1/16W

R9467

12

NO STUFF

49.9

1%

1/16W MF-LF

402

R9471

12

NO STUFF

49.9

1%

1/16W MF-LF

402

R9475

12

NO STUFF

402

MF-LF1/16W

1%

49.9

R9479

12

NO STUFF

49.9

1%

1/16W MF-LF

402

R9483

12

NO STUFF

49.9

1%

1/16W MF-LF

402

R9487

12

1/16W

NO STUFF

49.9

1%

MF-LF

402

R9443

1

2

1%

1/16W

150

MF-LF

402

VGA_TERM_CONN

R9445

1

2

402

150

1%

MF-LF

1/16W

VGA_TERM_CONN

R9444

1

2

402

MF-LF

150

1/16W

1%

VGA_TERM_CONN

051-7225

14.0.0

8876

DVI Display Connector

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

TMDS_CLK_R_P

TMDS_DATA_P<4>

TMDS_DATA_P<5>

TMDS_CLK_N

PP3V3_GPU_TMDS

TMDS_DATA_P<3>

TMDS_DATA_P<1>

TMDS_DATA_P<2>

PP3V3_GPU_TMDS

TMDS_CLK_P

TMDS_DATA_P<0>

PP3V3_GPU_TMDS

TMDS_CLK_R_N

GND_CHASSIS_DVI_BOT

TMDS_DATA_F_N<3>

TMDS_DATA_F_P<3> DVI_DDC_CLK_R

PP5V_S0_DDC

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

DVI_HPD

VGA_HSYNC

PP3V3_GPU_TMDS

GPU_VGA_VSYNC

GPU_VGA_HSYNC

TMDS_DATA_F_P<0>

PP3V3_GPU

VGA_G

GPU_TV_COMP_VGA_B

VGA_R

VGA_B

TMDS_CLK_F_P

TMDS_DATA_F_N<2>

TMDS_DATA_F_N<1>

TMDS_DATA_F_P<1>

TMDS_DATA_F_N<3>

TMDS_DATA_F_P<3>

TMDS_DATA_N<3>

TMDS_DATA_F_N<4>

TMDS_DATA_F_P<4>

VGA_HSYNC_R

VGA_HSYNC

VGA_VSYNC_R

VGA_VSYNC

PP3V3_GPU

TMDS_DATA_F_P<5>

TMDS_DATA_F_N<5>

TMDS_DATA_F_P<4>

TMDS_DATA_F_N<4>

TMDS_DATA_F_P<1>

TMDS_DATA_F_P<0> TMDS_DATA_F_P<2>

TMDS_DATA_F_N<0>

TMDS_DATA_F_N<1>

TMDS_DATA_F_N<2>

TMDS_CLK_F_N

TMDS_CLK_F_P

VGA_VSYNC DVI_HPD_R

PP5V_S0

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP5V_S0_DDC_PULLUPS

DVI_DDC_CLK

DVI_DDC_DATA

VOLTAGE=5V

PP5V_S0_DDC_F

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

DVI_DDC_DATA_R

GPU_DVI_DDC_CLK

PP5V_S0

DVI_HOTPLUG_DET

PP3V3_GPU

GPU_HPD_BILAT

GPU_DVI_DDC_DATA

GPU_HPD

GPU_IOENABLE_RC

TMDS_DATA_F_N<0>

TMDS_DATA_F_P<5>

TMDS_DATA_F_N<5>

GPU_TV_Y_VGA_G

TMDS_CLK_F_N

TMDS_DATA_N<5>

TMDS_DATA_N<4>

GPU_TV_C_VGA_R

TMDS_DATA_F_P<2>

PP3V3_GPU_TMDS

GND_CHASSIS_DVI_TOP

GND_CHASSIS_DVI_BOT

VGA_R

VGA_G

VGA_B

TMDS_DATA_N<2>

PP3V3_GPU_TMDS

TMDS_DATA_N<1>

PP3V3_GPU_TMDS

TMDS_DATA_N<0>

78

76

77

65

77

76

59

76

74

58

74

73

57

73

72

52

72

71

47

71

76

65

42

65

73

57

27

57

72

76

87

72

87

48

87

48

87

87 87

87

8

48

87

76

87

8

87

9

76

8

76

8

76

87

76

87

76

8

76

76 76

76

7

8

76

9

76

SYM_VER-3

GND

SEL

DB19*

DB18*

DB17*

DB16*

DB15*

DB14*

DB13*

DB12*

DB11*

DB10*

DB9* DH19

DH14

DH13

DH12

DH11

DH10

DH9

DH15 DH16 DH17 DH18

DB4* DB5* DB6* DB7* DB8*

DB0* DB1* DB2* DB3*

DH4

DH3

DH2

DH1

DH0

DH8

DH7

DH6

DH5

DA15 DA16 DA17 DA18 DA19

DA13 DA14

DA12

DA11

DA10

DA5 DA6 DA7 DA8 DA9

DA0 DA1 DA2 DA3 DA4

VDD

G

S D

G

S D

IN

OUT

BIBI

BI

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT OUT

OUT

OUT OUT OUT

IN IN IN IN IN IN IN IN

IN IN IN

IN IN

IN IN IN IN IN IN

IN IN

IN IN IN IN IN IN

IN IN

IN IN IN

IN

OUT

VPG

V2

V4

V3

VREF RST*

CRT

THRM_PAD

GND

PBR*

V1

OUT

G

D

S

G

D

S

IN

V+

V-

1B1

4B2

2B1 2B2 3B1 3B2 4B1

1B2

1A

2A

3A

4A

OE*

S

THRML

PAD

GND

VCC

SYM_VER-2

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PGOOD Monitor for GPU Rails

LTC2900 provides programmable reset delay which is required to play nice with ICHx PGOOD circuit

LVDS Data Mux Power Supply

GPU LVDS I/F

NC

NB LVDS I/F

LVDS I/F Mux

NC

NOTE: SEL = LOW selects port B

Fast wake condition is worst case. ICHx can create an S3 duration of 1 RTC clock (32 us). If mux select is on core well and AND-gate is implemented, glitch filter or <99ms PGOOD assertion time is required for PGOODs to be valid at end of 99 ms SMC timer. If mux select on resume well, then observed PGOOD will not change during S3 transitions and ICHx will honor whatever

be necessary before going to sleep to keep PGOODs valid.

core well, this could mean powering up IG supply will

a switch can occur. If mux select GPIO is still on a

to guarantee that the "other" device is ready before

be powered off if using external GPU. S/W will have

NOTE: New H/W and S/W challenge since NB gfx might

Panel/Backlight Control Mux

Alias to 3.3V if not used->

NOTE: NAND-gate required if EXTGPU_LVDS_EN GPIO is on SB core well. Keeps PGOOD looking at non-GPU rails until GPIO switches back to default state and GPU power rails have come up and are valid (which should be before platform reset deasserts). Could be eliminated if GPIO moved to resume well.

HI=xB2 LO=xB1

Trst = 4.6ms/nF

(Int. GFX)

NC

(Int. GFX)

(Ext. GFX)

PGOOD delays are provided.

GPU DDC Pass FETs

Mux Select Conditioning

LTC2900 typical threshold is 93.5% (3.055V, 2.325V, 1.685V, 1.120V)

Trst = 1.5ms

R9596

1

2

402

MF-LF

5% 1/16W

470K

U9550

F1 H1 K1 K3 K4 K6 J7

K9 J10 G10 E10 C10 A10

A8

A7

A5

B4

A2

B1

D1

G1

J1

K2

J4

K5

K7

K8 K10 H10 F10 D10 B10

A9

B7

A6

A4

A3

A1

C1

E1

F2 H2 J2 J3 J5 J6 J8 J9 H9 F9 E9 C9 B9 B8 B6 B5 B3 B2 C2 E2

C5C6D2

D9G2G9H5H6

E3

E8F3F8

BGA-LF

CRITICAL

CBTV4020

Q9570

6

2

1

SOT-363

2N7002DW-X-F

Q9570

3

5

4

2N7002DW-X-F

SOT-363

C9593

1

2

20% 10V

0.1UF

CERM

402

C9591

1

2

402

20% 10V

0.1UF

CERM

R9595

1

2

1K

1/16W MF-LF 402

5%

72 73

15 75 77

15 75 77 72 73

15 75 77

75 87

71 72

15

71 72

15

71 72

15

28 30 77

9

59

15 80

73 86

7

73 86

7

73 86

7

73 86

15 80

73 86

34

75

U9590

3

6

5

4

11

2

10

1

9

7

8

CRITICAL

DFN

LTC2900

R9593

1

2

1/16W MF-LF 402

124K

1%

R9594

1

2

100K

402

1/16W

1% MF-LF

C9595

1

2

330PF

10% 50V

402

CERM

C9592

12

0.1UF

20% 10V

CERM

402

28 30 77

R9562

1

2

10K

MF-LF

402

5%

1/16W

R9545

1

2

MF-LF

402

1/16W

10K

5%

R9544

1

2

5%

10K

MF-LF

402

1/16W

Q9540

6

2

1

SOT-363

2N7002DW-X-F

Q9540

3

5

4

SOT-363

2N7002DW-X-F

R9541

1 2

402

LVDS_SEL_RESUME

MF-LF

0

1/16W

5%

R9542

1 2

402

5%

1/16W

0

MF-LF

LVDS_SEL_CORE

C9561

12

0.1UF

LVDS_SEL_CORE

402

CERM

10V

20%

7

24 28

25

13 24

R9543

1 2

LVDS_SEL_RESUME

MF-LF

1/16W

5%

402

0

R9563

1 2

MF-LF

0

1/16W

5%

402

LVDS_SEL_CORE

U9561

3

2

1

4

5

MC74VHC1G00

LVDS_SEL_CORE

SC70-5

R9555

1

2

10K

1% 1/16W MF-LF

402

U9555

3

4

1

5

6

2

CRITICAL

MAX4236EUTT

SOT23-6-LF

C9555

12

CERM

20%

0.1UF

10V 402

R9556

1

2

31.6K

402

MF-LF

1/16W

1%

C9556

1

2

0.1UF

402

CERM

10V

20%

C9550

1

2

10V

20% 402

CERM

0.1UF

C9560

1

2

0.1UF

CERM

402

20% 10V

R9570

1

2

15.8K

MF-LF

402

1%

1/16W

R9571

1

2

15.8K

1%

MF-LF

402

1/16W

U9560

42

3

75

6

911

10

1214

13

15

8117

16

CRITICAL

QFN

74CBTLV3257

R9560

1

2

1/16W

5%

402

MF-LF

10K

R9561

1

2

100K

MF-LF

402

5%

1/16W

C9590

1

2

10V

20%

CERM

402

0.1uF

R9590

1

2

1% MF-LF

402

1/16W

28K

R9591

1

2

1% 1/16W

402

71.5K

MF-LF

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

14.0.0

051-7225

77 88

LVDS Interface Mux

RSVD_EXTGPU_LVDS_EN

PP3V3_S0

PP3V3_GPU

LVDS_CONN_DDC_CLK

GPU_PANEL_DDC_DATA

EXTGPU_LVDS_EN33_L

PP2V5_S0_LVDS_MUX

PP1V25_GPU

PP3V3_GPU

MAKE_BASE=TRUE

LVDS_CONN_DDC_CLK

MAKE_BASE=TRUE

LVDS_CONN_DDC_DATA

GPU_PANEL_DDC_CLK

GPU_IOENABLE_RC

LVDS_CONN_DDC_DATA

PP3V3_S0

PLT_RST_L

PP3V3_S0

PM_ALL_NBGFX_PGOOD LVDSCTRLMUX_SEL_GPU_L

LVDS_PANEL_EN

LCDBKLT_PWM_UNBUF

GPU_PANEL_EN

LCDBKLT_PWREN

TP_PM_ALL_GFX_PGOOD

LVDS_VDD_EN

LVDS_BKLT_CTL PM_ALL_GPU_PGOOD

GPU_PGOOD_CRT

PM_ALL_GPU_PGOOD

GPU_PGOOD_VPG

GPU_PGOOD_VREF

EXTGPU_LVDS_EN

EXTGPU_LVDS_EN_QUAL

EXTGPU_LVDS_SEL

GPU_PGOOD_P1V2_DIV

LVDSCTRLMUX_SEL_GPU_L

LVDSDATAMUX_SEL_GPU_L

PP2V5_S0_LVDS_MUX

LVDSDATAMUX_SEL_GPU_L

LVDS_U_DATA_CONN_P<2>

LVDS_U_CLK_CONN_P

LVDS_U_CLK_CONN_N

LVDS_U_DATA_CONN_N<1>

LVDS_U_DATA_CONN_P<1>

LVDS_L_DATA_CONN_P<2> LVDS_L_DATA_CONN_N<2> LVDS_L_DATA_CONN_N<1> LVDS_L_DATA_CONN_P<1>

LVDS_L_CLK_CONN_P LVDS_L_CLK_CONN_N

LVDS_L_DATA_CONN_N<0> LVDS_L_DATA_CONN_P<0>

LVDS_U_DATA_CONN_N<0>

LVDS_U_DATA_CONN_N<2>

LVDS_U_DATA_CONN_P<0>

LVDS_L_DATA_N<2> LVDS_L_DATA_N<1> LVDS_L_DATA_P<1>

LVDS_L_DATA_P<2>

LVDS_L_DATA_P<0>

LVDS_L_DATA_N<0>

LVDS_L_CLK_N

LVDS_L_CLK_P

LVDS_U_DATA_N<2> LVDS_U_DATA_N<0> LVDS_U_DATA_P<0>

LVDS_B_DATA_N<1>

LVDS_B_CLK_N LVDS_B_CLK_P LVDS_B_DATA_P<2>

LVDS_B_DATA_P<1>

LVDS_A_DATA_N<2> LVDS_A_DATA_N<1> LVDS_A_DATA_P<1>

LVDS_A_CLK_N

LVDS_A_DATA_N<0> LVDS_A_DATA_P<0> LVDS_A_DATA_P<2>

LVDS_B_DATA_N<0>

LVDS_B_DATA_N<2>

LVDS_B_DATA_P<0>

LVDS_A_CLK_P

LVDS_U_DATA_P<1> LVDS_U_DATA_N<1>

LVDS_U_CLK_N LVDS_U_CLK_P LVDS_U_DATA_P<2>

VOLTAGE=2.5V

PP2V5_S0_LVDS_MUX

MIN_NECK_WIDTH=0.10 mm

MIN_LINE_WIDTH=0.25 mm

P2V5_S0_VREF

PP3V3_S0

PP1V8_GPU

PP3V3_GPU

GPU_BL_PWM

LVDS_BKLT_EN

GPU_BKLT_EN

87

77

75

74

65

59

58

57

52

51

50

48

47

46

42

32

31

30

29

28

27

77

27

77

26

76

26

76

25

74

25

74

24

73

24

73

23

72

74

72

23

70

72

21

71

21

69

71

19

65

68

65

19

68

65

16

57

66

57

16

67

57

13

48

57

48

76

13

57

48

8

77

8

28

8

77

8

IN

OUT

IN

OUT

SYM_VER-1

OUT

BI BI

OUT

BI

OUT

BI BI

BI

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

516S0412

NC NC

SATA HDD & IR & SIL Flex Connector

Left ALS Connector

are to remove this noise from SATA signals.

NOTE: SATA _UF_ nets cross DDR2 signals and pick up significant noise. Common-mode chokes

White colored version of 518S0369

518S0469

Top-Case Connector

7

45 53

7

53

23 82

C9660

1 2

PLACEMENT_NOTE=Place C9660 close to southbridge

0.0047uF

CERM

402

10% 25V

C9661

1 2

PLACEMENT_NOTE=Place C9661 next to C9660

0.0047uF

CERM

402

10% 25V

23 82

C9665

2 1

PLACEMENT_NOTE=Place C9665 close to J9660

0.0047uF

CERM

402

10% 25V

C9666

2 1

PLACEMENT_NOTE=Place C9666 next to C9665

0.0047uF

CERM

402

10% 25V

FL9660

1

2 3

4

PLACEMENT_NOTE=Place FL9660 close to J9660 CRITICAL

90-OHM-100MA

1210-4SM1

FL9665

1

2 3

4

PLACEMENT_NOTE=Place FL9665 close to southbridge CRITICAL

1210-4SM1

90-OHM-100MA

7

45 46

24 82

45 48 51 84

45 46

24 82

53

24 82

J9600

1

10 11 12 13 14 15 16 17 18 19

2

20

3 4 5 6 7 8 9

M-ST-SM

QT500206-L020

CRITICAL

D9600

3

1

2

CRITICAL

RCLAMP0502B

SC-75

24 82

J9630

5

6

1 2 3 4

CRITICAL

BM04B-ACH

M-RT-SM

24 82

46

J9660

1

10 11 12 13 14 15 16 17 18 19

2

20

3 4 5 6 7 8 9

M-ST-SM

QT500206-L020

CRITICAL

051-7225

14.0.0

8878

SYNC_MASTER=(M59_SYNC)

SYNC_DATE=08/24/2006

M75 Specific Connectors

LTALS_OUT

ALS_GAIN

PP3V3_S3

SATA_A_R2D_C_P

SATA_A_R2D_UF_P

SATA_A_R2D_UF_N

SATA_A_D2R_UF_N

SATA_A_D2R_UF_P

SATA_A_D2R_N

SATA_A_D2R_P

SATA_A_R2D_C_N

USB_TPAD_N

SMBUS_SMC_A_S3_SCL

USB_TPAD_P

SMBUS_SMC_A_S3_SDA

PP3V3_S3

PP5V_S3

SMC_ONOFF_L

USB_BT_N USB_BT_P

KBDLED_ANODE

GND

SMC_LID

PP3V42_G3H

PP5V_S3

SYS_LED_ANODE

USB_IR_P

SATA_A_D2R_C_N

USB_IR_N

SATA_A_D2R_C_P

SATA_A_R2D_N SATA_A_R2D_P

PP5V_S0

78

76

57

65

54

48

59

53

78

47

78

58

51

57

46

57

50

53

45

53

52

48

49

43

49

47

38

46

34

46

42

36

44

28

44

27

8

7

87

7

82

7

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

FSB (Front-Side Bus) Constraints

Design Guide recommends each strobe/signal group is routed on the same layer.

CPU Signal Constraints

Most CPU signals with impedance requirements are 55-ohm single-ended. Some signals require 27.4-ohm single-ended impedance.

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

NOTE: Design Guide does not indicate FSB spacing to other signals, assumed 3:1.

DSTB complementary pairs are spaced 1:1 and routed as differential pairs.

Worst-case spacing is 2:1 within Addr bus, with 3:1 spacing to the ADSTBs.

(See above)

CPU / FSB Net Properties

PHYSICAL

NET_TYPE

SPACING

DG recommends at least 25 mils, >50 mils preferred

Worst-case spacing is 2:1 within Data bus, with 3:1 spacing to the DSTBs.

Design Guide recommends FSB signals be routed only on internal layers.

NOTE: Design Guide allows closer spacing if signal lengths can be shortened.

All FSB signals with impedance requirements are 55-ohm single-ended.

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.2 & 4.3

ELECTRICAL_CONSTRAINT_SET

(See above)

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target differential impedance.

(See above)

(FSB_CPURST_L)

=2:1_SPACING

?

CPU_2TO1

*

=3:1_SPACING

FSB_DATA

*

?

=2:1_SPACING

?

*

CPU_ITP

CPU_55S

=55_OHM_SE=55_OHM_SE

*

=55_OHM_SE

Y =STANDARD =STANDARD

FSB_DSTBFSB_DATA

*

FSB_DATA2DSTB

FSB_ADDR2ADDR

*

FSB_ADDR FSB_ADDR

FSB_DATA2DATA

FSB_DATA

*

FSB_DATA

FSB_ADDR2ADSTB

FSB_ADDR

FSB_ADSTB

*

?

=2:1_SPACING

*

FSB_COMMON

?

FSB_ADDR

=3:1_SPACING

*

=3:1_SPACING

*

FSB_DSTB

?

*

FSB_DATA2DSTB

?

=3:1_SPACING

SYNC_DATE=01/17/2007

CPU/FSB Constraints

SYNC_MASTER=T9_NOME

79 88

14.0.0

051-7225

=55_OHM_SE

FSB_55S

=STANDARD

=55_OHM_SE

*

=55_OHM_SE =55_OHM_SE

=STANDARD

?

=2:1_SPACING

FSB_ADDR2ADDR

*

?

=3:1_SPACING

FSB_ADSTB

*

?

=3:1_SPACING

*

FSB_ADDR2ADSTB

?

CPU_VCCSENSE

*

25 MIL

?

CPU_COMP

*

?

*

CPU_GTLREF

25 MIL

=1:1_DIFFPAIR

FSB_DSTB_55S

=1:1_DIFFPAIR=1:1_DIFFPAIR

=55_OHM_SE

*

=55_OHM_SE =55_OHM_SE

* Y

=27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE

CPU_27P4S

7 MIL 7 MIL

*

FSB_DATA2DATA

?

=2:1_SPACING

CPU_2TO1

CPU_VID<6..0>

CPU_55S

CPU_55S CPU_ITP

XDP_TDI

CPU_55S CPU_ITP

XDP_TDO

CPU_55S CPU_ITP

XDP_TMS

CPU_55S CPU_ITP

XDP_TCK

CPU_55S CPU_ITP

XDP_TRST_L

XDP_BPM_L<4..0>

XDP_BPM_L

CPU_ITPCPU_55S

IMVP6_VSEN_P

CPU_VCCSENSE

CPU_27P4S CPU_27P4S

IMVP6_VSEN_N

CPU_VCCSENSE

CPU_VCCSENSE_P

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE_N

CPU_VCCSENSE

CPU_27P4S

IMVP6_VID<6..0>

CPU_2TO1

CPU_55S

CPU_ITPCPU_55S

XDP_CPURST_L

XDP_CLK_P

CLK_FSB_100D

CLK_FSB CLK_FSB

CLK_FSB_100D

XDP_CLK_N

CPU_55S CPU_ITP

XDP_BPM_L5

XDP_BPM_L<5>

CPU_55S

NB_BSEL<2>

CPU_2TO1

CPU_COMP<3>

CPU_COMP

CPU_55S

CPU_COMP

NB_BSEL<0>

CPU_2TO1

CPU_55S

CPU_GTLREF

CPU_2TO1

CPU_55S

IMVP_DPRSLPVR

PM_DPRSLPVR

CPU_2TO1

PM_DPRSLPVR

CPU_55S

FSB_CPUSLP_L

CPU_55S

FSB_CPUSLP_L

PM_THRMTRIP_L

CPU_2TO1

CPU_55S

PM_THRMTRIP_L

CPU_FROM_SB

CPU_IGNNE_L

CPU_55S

CPU_IERR_L

CPU_55S

CPU_IERR_L

CPU_55S

CPU_BSEL2

CPU_2TO1

CPU_BSEL<2>

CPU_2TO1

CPU_BSEL<1>

CPU_BSEL1

CPU_55S

FSB_DATA

FSB_DATA_GROUP2

FSB_D_L<47..32>

FSB_55S

FSB_DATA_GROUP1

FSB_DATA

FSB_D_L<31..16>

FSB_55S

FSB_COMMON

FSB_TRDY_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_55S

FSB_BPRI_L

FSB_COMMON

FSB_ADS_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_55S

FSB_DBSY_L

FSB_COMMON

FSB_55S

FSB_BREQ0_L

FSB_COMMON

FSB_DATA_GROUP0

FSB_55S

FSB_DATA

FSB_DINV_L<0>

FSB_COMMON

FSB_RS_L<2..0>

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_LOCK_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_DRDY_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_DPWR_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_HITM_L

FSB_COMMON

FSB_55S

FSB_CPURST_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_DEFER_L

FSB_COMMON

FSB_55S

FSB_ADDR

FSB_ADDR_GROUP0

FSB_55S

FSB_REQ_L<4..0>

FSB_DSTB_L_P<3>

FSB_DSTB

FSB_DSTB3

FSB_DSTB_55S

FSB_D_L<63..48>

FSB_DATA_GROUP3

FSB_55S

FSB_DATA

FSB_DSTB

FSB_DSTB_L_N<0>

FSB_DSTB_55S

FSB_DSTB0

FSB_DSTB

FSB_DSTB_L_P<0>

FSB_DSTB_55S

FSB_COMMON

FSB_BNR_L

FSB_COMMON

FSB_55S

FSB_DINV_L<3>

FSB_DATA_GROUP3

FSB_55S

FSB_DATA

FSB_DSTB_L_N<1>

FSB_DSTBFSB_DSTB_55S

FSB_55S

FSB_DATA_GROUP0

FSB_DATA

FSB_D_L<15..0>

FSB_DSTB1

FSB_DSTB

FSB_DSTB_L_P<1>

FSB_DSTB_55S

FSB_DATA_GROUP1

FSB_DATA

FSB_55S

FSB_DINV_L<1>

FSB_COMMON

FSB_HIT_L

FSB_55S

FSB_COMMON

FSB_DINV_L<2>

FSB_DATA_GROUP2

FSB_DATA

FSB_55S

FSB_DSTB_L_P<2>

FSB_DSTB

FSB_DSTB2

FSB_DSTB_55S

FSB_DSTB_L_N<2>

FSB_DSTB_55S FSB_DSTB

FSB_DSTB_L_N<3>

FSB_DSTBFSB_DSTB_55S

FSB_ADDR_GROUP0

FSB_55S

FSB_A_L<16..3>

FSB_ADDR

FSB_ADSTB

FSB_ADSTB1

FSB_ADSTB_L<1>

FSB_55S

FSB_A_L<35..17>

FSB_ADDR_GROUP1

FSB_55S

FSB_ADDR

FSB_55S

FSB_ADSTB

FSB_ADSTB_L<0>

FSB_ADSTB0

CPU_FERR_L

CPU_55S

CPU_PROCHOT_L

CPU_2TO1

CPU_55S

CPU_PWRGD

CPU_55S

CPU_PWRGD

CPU_55S

CPU_INTR

CPU_FROM_SB

CPU_NMI

CPU_55S

CPU_FROM_SB CPU_FROM_SB

CPU_A20M_L

CPU_55S

CPU_INIT_L

CPU_INIT_L CPU_FROM_SB

CPU_SMI_L

CPU_55S

CPU_COMP

CPU_27P4S

CPU_COMP<0>

CPU_COMP

CPU_55S

CPU_STPCLK_L

CPU_FROM_SB

CPU_BSEL0

CPU_BSEL<0>

CPU_2TO1

CPU_55S

CPU_FROM_SB

CPU_DPSLP_L

CPU_55S

CPU_COMPCPU_COMP

CPU_COMP<1>

CPU_55S

CPU_COMP<2>

CPU_COMP CPU_COMP

CPU_27P4S

CPU_DPRSTP_L

CPU_55S

CPU_2TO1

CPU_DPRSTP_L

NB_BSEL<1>

CPU_55S

CPU_2TO1

58

84

58

46

14

23

58

30

25

14

23

14

13

14

58

13

47

23

16

30

12

13

58

12

29

13

16

58

16

10

16

23

30

10

14

10

14

10

14

10

23

46

10

23

10

30

10

16

11

10

58

11

7

13

10

13

10

13

10

7

10

7

10

7

10

7

10

7

10

7

10

7

10

7

10

7

13

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LVDS signals are 100-ohm +/- 20% differential impedence.

- 37.5-ohm +/- 15% from GMCH to first termination resistor.

- 50-ohm +/- 15% from first to second termination resistor.

- 55-ohm +/- 15% from second termination resistor to connector. CRT_HSYNC/CRT_VSYNC signals are 55-ohm +/- 15% single-ended impedence.

CRT & TVDAC signal single-ended impedence varies by location:

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 8.1 - 8.3.

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 7.2, 9.2 & 10.5

DG Says 40 mil spacing minimum

NET_TYPE

SPACING

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

PCI-Express / DMI Bus Constraints

Video Signal Constraints

DG Says 40 mil spacing minimum

DG Says 30 mil spacing minimum

?

*

25 MIL

CRT_SYNC

TVDAC_2TVDAC

TVDACTVDAC

*

CRT_SYNC CRT_SYNC

CRT_SYNC2SYNC

=50_OHM_SE =50_OHM_SE=50_OHM_SE

=STANDARD* =STANDARD

=50_OHM_SE

CRT_50S

=100_OHM_DIFF

*

=100_OHM_DIFF

DMI_100D

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

PCIE_100D

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

*

=100_OHM_DIFF

NB Constraints

SYNC_DATE=01/17/2007

80 88

14.0.0

051-7225

SYNC_MASTER=T9_NOME

=55_OHM_SE =55_OHM_SE=55_OHM_SE

CRT_55S

=55_OHM_SE

=STANDARD* =STANDARD

20 MIL

PCIE

*

?

TVDAC_2TVDAC

*

?

20 MIL

*

?

CRT_SYNC2SYNC

20 MIL

CRT 25 MIL

*

?

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

*

LVDS_100D

=100_OHM_DIFF

TVDAC

25 MIL

*

?

CRT_2CRT

*

?

20 MIL

LVDS

*

?

DMI 20 MIL

?

*

CRT_2CRT

CRTCRT

*

TVDAC

CRT_50S

TV_A_DAC

CRT_SYNC

CRT_55S

CRT_SYNC

CRT_VSYNC_R

CRT_50S

TV_C_DAC

TVDAC

TV_C_DAC

CRT_50S

TV_B_DAC

TVDAC

TV_B_DAC

CRT_RED

CRT

CRT_50S

CRT_RED

CRT_GREEN

CRT

CRT_50S

CRT_GREEN

CRT_BLUE

CRT

CRT_50S

CRT_BLUE

CRT

CRT_TVO_IREF

DMI_100D

DMI

DMI_N2S_N<3..0>

DMI

DMI_100D

DMI_S2N_P<3..0>

DMI_S2N

DMI

DMI_100D

DMI_S2N_N<3..0>

LVDS_IBG

LVDS

LVDS_B_DATA3 LVDS

LVDS_100D

LVDS_B_DATA_N<3>

PCIE

PCIE_100D

PEG_D2R_N<15..0>

PCIE_100D

PEG_D2R_C_N<15..0>

PCIE

PCIE_100D

PEG_R2D_C_N<15..0>

PCIE

PCIE_100D

PEG_R2D_C_P<15..0>

LVDS

LVDS_A_CLK

LVDS_A_CLK_N

LVDS_100D

LVDS_A_DATA

LVDS_A_DATA_P<2..0>

LVDS_100D

LVDS

LVDS_A_DATA

LVDS_A_DATA_N<2..0>

LVDS_100D

LVDS

LVDS_A_CLK

LVDS_A_CLK_P

LVDS

LVDS_100D

PCIE

PCIE_100D

PEG_D2R

PEG_D2R_P<15..0>

PCIE

PCIE_100D

PEG_R2D_N<15..0>

PCIE

PCIE_100D

PEG_R2D

PEG_R2D_P<15..0>

LVDS_A_DATA3

LVDS_A_DATA_N<3>

LVDS

LVDS_100D

LVDS_A_DATA3

LVDS_A_DATA_P<3>

LVDS

LVDS_100D

LVDS_B_CLK

LVDS_B_CLK_P

LVDS

LVDS_B_DATA3

LVDS_B_DATA_P<3>

LVDS_100D

LVDS

DMI_100D

DMI_N2S

DMI

DMI_N2S_P<3..0>

PCIE

PCIE_100D

PEG_D2R_C_P<15..0>

CRT_SYNC

CRT_55S

CRT_SYNC

CRT_HSYNC_R

LVDS_B_CLK

LVDS_B_CLK_N

LVDS

LVDS_100D LVDS_100D

LVDS_B_DATA

LVDS_B_DATA_P<2..0>

LVDS

LVDS_B_DATA

LVDS_B_DATA_N<2..0>

LVDS

LVDS_100D

24

22

66

77

66

77

24

77

16

15

66

15

66

15

16

66

15

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

Memory Net Properties

NET_TYPE

SPACING

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

Need to support MEM_*-style wildcards!

DDR2 Memory Bus Constraints

*

MEM_DATA2MEM

MEM_DATA

MEM_CLK

=1.5:1_SPACING

MEM_DATA2DATA

*

?

MEM_DQS2MEM

*

=3:1_SPACING

?

MEM_CTRL

MEM_CTRL2MEM

MEM_CLK

*

MEM_CMD2MEM

MEM_CMD

*

MEM_DQS

*

MEM_CMD MEM_CMD

MEM_CMD2CMD

MEM_CMD2MEM

*

=3:1_SPACING

?

MEM_CTRL2CTRL

=2:1_SPACING

*

?

MEM_DATA2MEM =3:1_SPACING

*

?

*

MEM_CMD

MEM_CMD2MEM

MEM_DATA

81 88

14.0.0

051-7225

Memory Constraints

SYNC_MASTER=T9_NOME

SYNC_DATE=01/17/2007

=45_OHM_SE =45_OHM_SE =45_OHM_SE

MEM_45S

=STANDARD

=45_OHM_SE

=STANDARD*

=55_OHM_SE =55_OHM_SE =55_OHM_SE

*

MEM_55S

=STANDARD =STANDARD

=55_OHM_SE

=70_OHM_DIFF

=70_OHM_DIFF=70_OHM_DIFF =70_OHM_DIFF

* =70_OHM_DIFF =70_OHM_DIFF

MEM_70D

MEM_CMD

*

MEM_CMD2MEM

MEM_CLK

MEM_CTRL2CTRL

MEM_CTRL

*

MEM_CTRL

MEM_DATA

MEM_CTRL2MEM

*

MEM_CTRL

MEM_DQS

MEM_CTRL

*

MEM_CTRL2MEM

*

=3:1_SPACING

?

*

MEM_DATA

MEM_DATA2MEM

MEM_CTRL

MEM_CMD

*

MEM_CTRL2MEM

MEM_CTRL

MEM_DATA2DATA

MEM_DATAMEM_DATA

*

MEM_DATA2MEM

MEM_DATA

*

MEM_DQS

MEM_DATA2MEM

MEM_DATA

*

MEM_CMD

*

=4:1_SPACING

MEM_CLK2MEM

?

*

MEM_CLK2MEM

MEM_CLKMEM_CLK

MEM_CLK2MEM

MEM_CLK

*

MEM_DATA

=85_OHM_DIFF

MEM_85D

=85_OHM_DIFF

=85_OHM_DIFF*

=85_OHM_DIFF

25 MIL

MEM_2OTHER

*

?

MEM_2OTHER

MEM_CLK

**

*

MEM_CLK2MEM

MEM_CTRL

MEM_CLK

MEM_CMD2CMD

*

=1.5:1_SPACING

?

*

MEM_CLK

MEM_CLK2MEM

MEM_DQS

*

MEM_CLK

MEM_CLK2MEM

MEM_CMD

*

MEM_CMD

MEM_CMD2MEM

MEM_CTRL

MEM_DQS

MEM_DQS2MEM

*

MEM_CLK

MEM_DQS

MEM_DQS2MEM

*

MEM_CTRL

*

MEM_DQS2MEM

MEM_DQS MEM_CMD MEM_DQS

MEM_DQS2MEM

*

MEM_DATA

*

MEM_DQS2MEM

MEM_DQS MEM_DQS

MEM_2OTHER

MEM_DQS

**

MEM_2OTHER

MEM_DATA

* *

MEM_2OTHER

MEM_CMD

**

MEM_2OTHER

MEM_CTRL

* *

MEM_A_CNTL

MEM_45S

MEM_CTRL

MEM_CKE<1..0>

MEM_A_CMD

MEM_A_CAS_L

MEM_55S MEM_CMD

MEM_CMD

MEM_A_CMD

MEM_A_WE_L

MEM_55S

MEM_DATA

MEM_55SMEM_A_DQ_BYTE0

MEM_A_DQ<7..0>

MEM_55S

MEM_DATA

MEM_A_DQ_BYTE2

MEM_A_DQ<23..16>

MEM_DATA

MEM_55SMEM_A_DQ_BYTE1

MEM_A_DQ<15..8>

MEM_55S

MEM_DATA

MEM_A_DQ_BYTE6

MEM_A_DQ<55..48>

MEM_A_DQ_BYTE7

MEM_A_DQ<63..56>

MEM_55S

MEM_DATA

MEM_55S

MEM_A_DM1

MEM_DATA

MEM_A_DM<1>

MEM_DATA

MEM_55S

MEM_A_DM0

MEM_A_DM<0>

MEM_55S

MEM_DATA

MEM_A_DM2

MEM_A_DM<2>

MEM_A_DM<4>

MEM_55S

MEM_DATA

MEM_A_DM4

MEM_55S

MEM_DATA

MEM_A_DM3

MEM_A_DM<3>

MEM_A_DM<6>

MEM_55S

MEM_DATA

MEM_A_DM6

MEM_A_DQS_P<0>

MEM_A_DQS0

MEM_DQSMEM_85D

MEM_A_DQS_N<0>

MEM_DQSMEM_85D

MEM_A_DQS_N<1>

MEM_DQSMEM_85D

MEM_A_DQS_P<1>

MEM_A_DQS1

MEM_DQSMEM_85D

MEM_A_DQS3

MEM_A_DQS_P<3>

MEM_DQSMEM_85D

MEM_A_DQS2

MEM_A_DQS_P<2>

MEM_DQSMEM_85D

MEM_A_DQS_N<2>

MEM_DQSMEM_85D

MEM_A_DQS4

MEM_A_DQS_P<4>

MEM_DQSMEM_85D

MEM_A_DQS_N<3>

MEM_DQSMEM_85D

MEM_A_DQS_N<5>

MEM_DQSMEM_85D

MEM_A_DQS_N<4>

MEM_DQSMEM_85D

MEM_A_DQS5

MEM_A_DQS_P<5>

MEM_DQSMEM_85D

MEM_A_DQS6

MEM_A_DQS_P<6>

MEM_DQSMEM_85D

MEM_70D MEM_CLK

MEM_CLK_N<5..3> MEM_CKE<4..3>

MEM_CTRL

MEM_45S

MEM_B_CNTL

MEM_CTRL

MEM_45S

MEM_CS_L<3..2>

MEM_B_CNTL

MEM_CMDMEM_55S

MEM_B_A<14..0>

MEM_B_CMD

MEM_CMDMEM_55S

MEM_B_WE_L

MEM_B_CMD

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE1

MEM_B_DQ<15..8>

MEM_DATA

MEM_55SMEM_B_DQ_BYTE0

MEM_B_DQ<7..0>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE3

MEM_B_DQ<31..24>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE2

MEM_B_DQ<23..16>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE4

MEM_B_DQ<39..32>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE6

MEM_B_DQ<55..48>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE5

MEM_B_DQ<47..40>

MEM_DATA

MEM_55S

MEM_B_DM0

MEM_B_DM<0>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE7

MEM_B_DQ<63..56>

MEM_55S

MEM_DATA

MEM_B_DM2

MEM_B_DM<2>

MEM_55S

MEM_DATA

MEM_B_DM1

MEM_B_DM<1>

MEM_55S

MEM_DATA

MEM_B_DM3

MEM_B_DM<3>

MEM_55S

MEM_DATA

MEM_B_DM5

MEM_B_DM<5>

MEM_55S

MEM_DATA

MEM_B_DM4

MEM_B_DM<4>

MEM_55S

MEM_DATA

MEM_B_DM6

MEM_B_DM<6>

MEM_55S

MEM_DATA

MEM_B_DM7

MEM_B_DM<7>

MEM_DQSMEM_85D

MEM_B_DQS0

MEM_B_DQS_P<0>

MEM_DQSMEM_85D

MEM_B_DQS1

MEM_B_DQS_P<1>

MEM_DQSMEM_85D

MEM_B_DQS_N<0>

MEM_DQSMEM_85D

MEM_B_DQS2

MEM_B_DQS_P<2>

MEM_DQSMEM_85D

MEM_B_DQS_N<1>

MEM_DQSMEM_85D

MEM_B_DQS_N<2>

MEM_DQSMEM_85D

MEM_B_DQS_N<3>

MEM_DQSMEM_85D

MEM_B_DQS3

MEM_B_DQS_P<3>

MEM_DQSMEM_85D

MEM_B_DQS_N<4>

MEM_DQSMEM_85D

MEM_B_DQS4

MEM_B_DQS_P<4>

MEM_DQSMEM_85D

MEM_B_DQS5

MEM_B_DQS_P<5>

MEM_DQSMEM_85D

MEM_B_DQS6

MEM_B_DQS_P<6>

MEM_DQSMEM_85D

MEM_B_DQS_N<5>

MEM_DQSMEM_85D

MEM_B_DQS7

MEM_B_DQS_P<7>

MEM_DQSMEM_85D

MEM_B_DQS_N<6>

MEM_DQSMEM_85D

MEM_B_DQS_N<7>

MEM_CLK_N<2..0>

MEM_CLKMEM_70D

MEM_A_CNTL

MEM_CS_L<1..0>

MEM_45S

MEM_CTRL

MEM_A_CNTL

MEM_ODT<1..0>

MEM_CTRL

MEM_45S

MEM_55S

MEM_A_CMD

MEM_A_A<14..0>

MEM_CMD

MEM_55S

MEM_A_CMD

MEM_A_BS<2..0>

MEM_CMD

MEM_A_CMD

MEM_A_RAS_L

MEM_55S MEM_CMD

MEM_55S

MEM_DATA

MEM_A_DQ_BYTE3

MEM_A_DQ<31..24> MEM_A_DQ<39..32>

MEM_55S

MEM_DATA

MEM_A_DQ_BYTE4

MEM_A_DQ<47..40>

MEM_55S

MEM_DATA

MEM_A_DQ_BYTE5

MEM_A_DM<7>

MEM_A_DM7

MEM_55S

MEM_DATA

MEM_A_DM<5>

MEM_55S

MEM_DATA

MEM_A_DM5

MEM_CLK_P<2..0>

MEM_A_CLK

MEM_70D MEM_CLK

MEM_A_DQS_N<7>

MEM_85D MEM_DQS

MEM_70D MEM_CLK

MEM_B_CLK

MEM_CLK_P<5..3>

MEM_A_DQS7

MEM_A_DQS_P<7>

MEM_DQSMEM_85D

MEM_A_DQS_N<6>

MEM_DQSMEM_85D

MEM_CMDMEM_55S

MEM_B_CAS_L

MEM_B_CMD

MEM_CMDMEM_55S

MEM_B_RAS_L

MEM_B_CMD

MEM_CMDMEM_55S

MEM_B_CMD

MEM_B_BS<2..0>

MEM_CTRL

MEM_45S

MEM_ODT<3..2>

MEM_B_CNTL

33

32

33

31

33

31

32

17

32

31

17

31

32

31

32

16

17

16

17

16

17

16

17

16

17

16

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SOURCE: Santa Platform DG, Rev 1.0 (#21112), Section 10.17

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.9.1

Internal Interface Constraints

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 10.13.2

PHYSICAL

SPACING

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

DG says minimum spacing 50 mils to clocks

USB 2.0 Interface Constraints

Disk Interface Constraints

HD Audio Interface Constraints

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.7 & 10.9

=55_OHM_SE

HDA_55S

=55_OHM_SE

*

=55_OHM_SE =55_OHM_SE

=STANDARD =STANDARD

=55_OHM_SE =55_OHM_SE

SMB_55S

*

=55_OHM_SE=55_OHM_SE

=STANDARD =STANDARD

=55_OHM_SE

SATA_55S

=55_OHM_SE

=STANDARD

=55_OHM_SE =55_OHM_SE

=STANDARD*

=55_OHM_SE =55_OHM_SE=55_OHM_SE =55_OHM_SE

SPI_55S

* =STANDARD =STANDARD

=55_OHM_SE =55_OHM_SE

*

IDE_55S

=STANDARD=STANDARD

=55_OHM_SE=55_OHM_SE

SB Constraints (1 of 2)

051-7225

14.0.0

8882

SYNC_DATE=01/17/2007

SYNC_MASTER=T9_NOME

USB_2CLK

25 MIL

*

?

SATA

*

20 MIL

?

=90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

*

USB_90D

=55_OHM_SE

USB_60S

=55_OHM_SE=55_OHM_SE=55_OHM_SE

=STANDARD=STANDARD*

=3:1_SPACING

SMB

*

?

*

SPI

=1.8:1_SPACING

?

*

?

USB 20 MIL

HDA

=1.8:1_SPACING

?

*

=1.8:1_SPACING

?

IDE

*

=100_OHM_DIFF

*

=100_OHM_DIFF

SATA_100D

=100_OHM_DIFF

USB_EXTA_MUXED_P

USB

USB_90D

USB_EXTA_MUXED_N

USB

USB_90D

USB

USB_EXTA_P

USB_EXTA

USB_90D

USB

USB_EXTA_N

SPI_55S

SPI

SPI_CE_L<1>

SPI_CE_R_L<1>

SPI_CE_L1

SPI

SPI_55S

SPI

SPI_CE_L<0>

SPI_55S

SPI

SPI_CE_L0

SPI_CE_R_L<0>

SPI_B_SO_R

SPI_55S

SPI

SPI_B_SO

SPI_55S

SPI

SPI_A_SO_R

SPI

SPI_55S

SPI

SPI_55S

SPI_SO

SPI

SPI_55S

SPI_B_SI_R

SPI_55S

SPI

SPI_A_SI_R

SPI

SPI_55S

SPI_SI

SPI

SPI_55S

SPI_SI

SPI_SI_R

SPI_55S

SPI

SPI_B_SCLK_R

SPI

SPI_55S

SPI_A_SCLK_R

SPI_55S

SPI

SPI_SCLK

SMB_55S

SMB

SMBUS_SB_ME_SDA

SMB_SB_ME_SDA

SPI_SCLK

SPI_55S

SPI

SPI_SCLK_R

SMB

SMB_55S

SMBUS_SB_ME_SCL

SMB_SB_ME_SCL

SMB_SB_SDA

SMB

SMB_55S

SMBUS_SB_SDA

SMB_55S

SMB

SMB_SB_SCL

SMBUS_SB_SCL

USB_RBIAS

USB_60S

USB_90D

TP_USB_EXTCN

USB

TP_USB_EXTCP

USB_EXTC

USB

USB_90D

USB_EXCARD_N

USB

USB_90D

USB_EXCARD_P

USB_EXCARD

USB

USB_90D

USB_EXTB_N

USB

USB_90D

USB_EXTB_P

USB_EXTB

USB

USB_90D

USB_IR_N

USB_90D

USB

USB_IR_P

USB_IR

USB_90D

USB

USB_TPAD_N

USB_90D

USB

USB_TPAD_P

USB_TPAD

USB_90D

USB

USB_BT_N

USB_90D

USB

USB_BT_P

USB_BT

USB_90D

USB

USB_CAMERA_N

USB_90D

USB

USB_CAMERA_P

USB_CAMERA

USB_90D

USB

USB_WWAN_N

USB_90D

USB

USB_WWAN_P

USB_90D

USB

USB_EXTD

USB_MINI_N

USB

USB_90D

USB_MINI_P

USB_MINI

USB_90D

USB

HDA_55S

HDA_RST_L

HDA

HDA_RST_L

HDA_55S

HDA

HDA_RST_L_R

HDA_SDIN0

HDA

HDA_55S

HDA_SDIN0

HDA

HDA_SDIN_CODEC

HDA_55S

SATA_RBIAS

SATA_55S

SATA_RBIAS

SATA_100D

SATA

SATA_C_D2R_C_P

SATA

TP_SATA_C_D2RP

SATA_100D

SATA_C_D2R

TP_SATA_C_R2DN

SATA

SATA_100D

IDE_CNTL

IDE_55S

IDE

IDE_PDDACK_L

IDE_55S

IDE

IDE_PDIOR_L

HDA_BIT_CLK_R

HDA_55S

HDA

SATA_B_R2D_N

SATA_100D

SATA

TP_SATA_B_D2RP

SATA

SATA_100D

SATA_B_D2R

SATA_A_R2D_C_N

SATA

SATA_100D

SATA_A_R2D_C_P

SATA_A_R2D

SATA_100D

SATA

SATA_B_R2D_P

SATA_100D

TP_SATA_B_D2RN

SATA

IDE_PDIORDY

IDE_55S

IDE

SATA

SATA_A_D2R_C_P

SATA_100D

SATA

SATA_A_D2R_C_N

SATA_100D

ODD_RST_5VTOL_L

IDE_RST_L

IDE_55S

IDE

SATA_A_D2R_N

SATA

SATA_100D

IDE_PDD<15..0>

IDE_55S

IDE

IDE_PDD

TP_SATA_B_R2DN

SATA

SATA_100D

SATA_A_R2D_N

SATA

SATA_100D

SATA_A_R2D_P

SATA_100D

SATA

IDE_PDA<2..0>

IDE_55SIDE_PDA

IDE

SATA_A_D2R

SATA_A_D2R_P

SATA_100D

SATA

IDE_IRQ14

IDE_55S

IDE

IDE_PDDREQ

IDE_CNTL

IDE

IDE_55S

IDE_PDCS3_L

IDE_55S

IDE

IDE_PDCS

IDE_PDCS1_L

IDE_55S

IDE

IDE_PDCS

IDE_PDIOW_L

IDE

IDE_55S

IDE_CNTL

SATA

TP_SATA_B_R2DP

SATA_B_R2D

SATA_100D

HDA_SYNC

HDA_55S

HDA

HDA_SYNC

HDA_55S

HDA

HDA_SYNC_R

HDA_SDOUT_R

HDA_55S

HDA

HDA_SDOUT

HDA

HDA_55S

HDA_BIT_CLK

HDA_55S

HDA

HDA_BIT_CLK

SATA

SATA_C_R2D_P

SATA_100D

TP_SATA_C_R2DP

SATA_C_R2D

SATA

SATA_100D

SATA

SATA_100D

SATA_B_D2R_C_N

SATA_100D

SATA_B_D2R_C_P

SATA

SATA_100D

SATA

SATA_C_D2R_C_N

TP_SATA_C_D2RN

SATA_100D

SATA

SATA_C_R2D_N

SATA_100D

48

34

32

31

44

43

55

48

55

48

29

24

34

78

24

34

42

78

42

78

42

78

42

34

42

24

55

24

55

24

55

24

55

25

24

25

24

9

24

7

24

23

78

24

23

78

23

78

PCI Bus Constraints

LAYER

PCI_55S

SPACING_RULE_SET

LAYER

PCI

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.18.1 & 10.19

Controller Link (AMT) Constraints

D

LAYER

CLINK_55S

CLINK_12MIL

SPACING_RULE_SET

LAYER

CLINK

CLINK_VREF

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30

Ethernet (Yukon) Constraints

LAYER

ENET_100D

SPACING_RULE_SET

ENET_MDI

SOURCE: Based on Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30

LAYER

ALLOW ROUTE ON LAYER?

=55_OHM_SE =55_OHM_SE

*

LINE-TO-LINE SPACING

*

=2:1_SPACING

ALLOW ROUTE ON LAYER?

=55_OHM_SE =55_OHM_SE

=STANDARD

LINE-TO-LINE SPACING

*

=1.8:1_SPACING

*

ALLOW ROUTE ON LAYER?

*

=100_OHM_DIFF

LINE-TO-LINE SPACING

*

12 MILS

25 MILS

MINIMUM LINE WIDTH

=55_OHM_SE

WEIGHT

?

MINIMUM LINE WIDTH

12 MILS

WEIGHT

? ?

MINIMUM LINE WIDTH

WEIGHT

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

=55_OHM_SE

5 MILS

MINIMUM NECK WIDTH

=100_OHM_DIFF

MAXIMUM NECK LENGTH

=55_OHM_SE

MAXIMUM NECK LENGTH

=55_OHM_SE

300 MILS

MAXIMUM NECK LENGTH

=100_OHM_DIFF=100_OHM_DIFF

DIFFPAIR PRIMARY GAP

C

B

6

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

=STANDARD =STANDARD* =STANDARD

=100_OHM_DIFF =100_OHM_DIFF

=STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

5

ELECTRICAL_CONSTRAINT_SET

PCI_AD PCI_AD19 PCI_AD20 PCI_AD PCI_AD PCI_C_BE_L PCI_CNTL PCI_CNTL PCI_CNTL PCI_LOCK_L PCI_CNTL PCI_CNTL PCI_CNTL PCI_CNTL PCI_FW_REQ_L PCI_FW_GNT_L PCI_REQ1_L PCI_GNT1_L PCI_REQ2_L PCI_GNT2_L INT_PIRQA_L INT_PIRQB_L INT_PIRQC_L INT_PIRQD_L INT_PIRQE_L INT_PIRQF_L

PCIE_A_R2D

PCIE_A_D2R

PCIE_B_R2D

PCIE_B_D2R

PCIE_EXCARD_R2D

PCIE_EXCARD_D2R

PCIE_FW_R2D

PCIE_FW_D2R

PCIE_MINI_R2D

PCIE_MINI_D2R

GLAN_COMP

CLINK_NB CLINK_NB CLINK_NB_RESET_L CLINK_WLAN CLINK_WLAN CLINK_WLAN_RESET_L NB_CLINK_VREF SB_CLINK_VREF0 SB_CLINK_VREF1

PCIE_ENET_R2D

PCIE_ENET_D2R

ENET_MDI

4

PHYSICAL

PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S

PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D

CLINK_55S CLINK_55S CLINK_55S CLINK_55S CLINK_55S CLINK_55S CLINK_12MIL CLINK_12MIL CLINK_12MIL

PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D

ENET_100D ENET_100D ENET_100D ENET_100D ENET_100D ENET_100D ENET_100D ENET_100D

NET_TYPE

SPACING

PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI

PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE

CLINK CLINK CLINK CLINK CLINK CLINK CLINK_VREF CLINK_VREF CLINK_VREF

PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE

ENET_MDI ENET_MDI ENET_MDIENET_MDI ENET_MDI ENET_MDI ENET_MDI ENET_MDI ENET_MDI

PCI_AD<18..0> PCI_AD<19> PCI_AD<20> PCI_AD<31..21> PCI_PAR PCI_C_BE_L<3..0> PCI_IRDY_L PCI_DEVSEL_L PCI_PERR_L PCI_LOCK_L PCI_SERR_L PCI_STOP_L PCI_TRDY_L PCI_FRAME_L PCI_FW_REQ_L PCI_FW_GNT_L PCI_REQ1_L PCI_GNT1_L PCI_REQ2_L PCI_GNT2_L INT_PIRQA_L INT_PIRQB_L INT_PIRQC_L INT_PIRQD_L INT_PIRQE_L INT_PIRQF_L

PCIE_A_R2D_C_P PCIE_A_R2D_C_N PCIE_A_D2R_P PCIE_A_D2R_N PCIE_B_R2D_C_P PCIE_B_R2D_C_N PCIE_B_D2R_P PCIE_B_D2R_N PCIE_EXCARD_R2D_C_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N PCIE_MINI_D2R_P PCIE_MINI_D2R_N

GLAN_COMP CLINK_NB_CLK

CLINK_NB_DATA CLINK_NB_RESET_L CLINK_WLAN_CLK CLINK_WLAN_DATA CLINK_WLAN_RESET_L NB_CLINK_VREF SB_CLINK_VREF0 SB_CLINK_VREF1

PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_N PCIE_ENET_R2D_P PCIE_ENET_R2D_N PCIE_ENET_D2R_P PCIE_ENET_D2R_N PCIE_ENET_D2R_C_P PCIE_ENET_D2R_C_N

ENET_MDI_P<0> ENET_MDI_N<0> ENET_MDI_P<1> ENET_MDI_N<1> ENET_MDI_P<2> ENET_MDI_N<2> ENET_MDI_P<3> ENET_MDI_N<3>

3

38

24

38

24

38

24

38

24

38

24

38

24

38

24

38

24

38

24

38

24

38

47 38

7

24

38

24

34

24

34

24

34

24

34

24

34

24

34

24

34

24

34

23

16

25

16

25

16

25

16

25

24

35

24

35

24

35

24

35

37

35

37

35

37

35

37

35

37

35

37

35

37

35

37

12

D

C

B

SB Constraints (2 of 2)

A

APPLE COMPUTER INC.

8

67

5

4

3

SYNC_MASTER=T9_NOME

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

2

NOTICE OF PROPRIETARY PROPERTY

SIZE

D

SCALE

SYNC_DATE=01/17/2007

DRAWING NUMBER

051-7225

SHT

NONE

A

REV.

14.0.0

OF

8883

1

78

Clock Signal Constraints

LAYER

CLK_FSB_100D

CLK_PCIE_100D =100_OHM_DIFF=100_OHM_DIFF

CLK_MED_55S

CLK_SLOW_55S

SPACING_RULE_SET

CLK_FSB

D

CLK_PCIE

CLK_MED

CLK_SLOW

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 14.1 - 14.6

LAYER

ALLOW ROUTE ON LAYER?

=100_OHM_DIFF

*

=100_OHM_DIFF

*

=55_OHM_SE =55_OHM_SE =55_OHM_SE

*

LINE-TO-LINE SPACING

* * * *

25 MIL 20 MIL 20 MIL 10 MIL

MINIMUM LINE WIDTH

=100_OHM_DIFF

=55_OHM_SE

WEIGHT

? ? ? ?

MINIMUM NECK WIDTH

=55_OHM_SE

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

C

B

MAXIMUM NECK LENGTH

=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF

=55_OHM_SE=55_OHM_SE =55_OHM_SE

6

DIFFPAIR PRIMARY GAP

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=STANDARD* =STANDARD =STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=100_OHM_DIFF

=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

5

Clock Net Properties

ELECTRICAL_CONSTRAINT_SET

CK505_CPU CK505_CPU

CK505_NB CK505_ITP CK505_ITP

CK505_PCIF1 CK505_PCI1 CK505_PCI2 CK505_PCI3 CK505_PCI4 CK505_PCI5

(CPU_BSEL0) (CPU_BSEL2)

CK505_DOT96

CK505_LVDS

CK505_SRC1

CK505_SRC2

CK505_SRC3

CK505_SRC4

CK505_SRC5

CK505_SRC6

CK505_SRC7

CK505_SRC8

(CK505_CPU) (CK505_CPU) (CK505_NB) (CK505_NB) (CK505_ITP) (CK505_ITP)

(CK505_PCIF0) (CK505_PCIF1) (CK505_PCI1) (CK505_PCI2) (CK505_PCI3)

(CPU_BSEL0) (CPU_BSEL2)

(CK505_DOT96) (CK505_DOT96) (CK505_LVDS) (CK505_LVDS) (CK505_SRC1) (CK505_SRC1) (CK505_SRC2) (CK505_SRC2) (CK505_SRC3) (CK505_SRC3) (CK505_SRC4) (CK505_SRC4) (CK505_SRC5) (CK505_SRC5) (CK505_SRC6) (CK505_SRC6)

4

PHYSICAL

CLK_FSB_100D CLK_FSB_100D CLK_FSB_100DCK505_NB CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D

CLK_MED_55SCK505_PCIF0 CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S

CLK_MED_55S CLK_MED_55S

CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D

CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D

CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S

CLK_MED_55S CLK_MED_55S

CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D

NET_TYPE

SPACING

CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB

CLK_MED CLK_MED CLK_MED CLK_MED CLK_MED CLK_MED CLK_MED

CLK_MED CLK_MED

CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE

CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB

CLK_MED CLK_MED CLK_MED CLK_MED CLK_MED

CLK_MED CLK_MED

CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE

FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_NB_P FSB_CLK_NB_N XDP_CLK_P XDP_CLK_N

CK505_PCIF0_CLK_ITPEN CK505_PCIF1_CLK CK505_PCI1_CLK TP_CK505_PCI2_CLK CK505_PCI3_CLK TP_CK505_PCI4_CLK CK505_PCI5_CLK_FCTSEL

CK505_48M_FSA CK505_REF0_FSC

CK505_CLK27M CK505_CLK27M_SS NB_CLK100M_DPLLSS_P NB_CLK100M_DPLLSS_N PEG_CLK100M_GPU_P PEG_CLK100M_GPU_N SB_CLK100M_DMI_P SB_CLK100M_DMI_N PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N SB_CLK100M_SATA_P SB_CLK100M_SATA_N NB_CLK100M_PCIE_P NB_CLK100M_PCIE_N PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N TP_PCIE_CLK100M_SRC7P TP_PCIE_CLK100M_SRC7N PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N

FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_NB_P FSB_CLK_NB_N XDP_CLK_P XDP_CLK_N

PCI_CLK33M_LPCPLUS PCI_CLK33M_SB PCI_CLK33M_FW PCI_CLK33M_TPM PCI_CLK33M_SMC CK505 PCI4 is project-specific CK505 PCI5 is project-specific

SB_CLK48M_USBCTLR SB_CLK14P3M_TIMER

CK505_FSA CK505_FSC

NB_CLK96M_DOT_P NB_CLK96M_DOT_N NB_CLK100M_DPLLSS_P NB_CLK100M_DPLLSS_N PEG_CLK100M_GPU_P PEG_CLK100M_GPU_N SB_CLK100M_DMI_P SB_CLK100M_DMI_N PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N SB_CLK100M_SATA_P SB_CLK100M_SATA_N NB_CLK100M_PCIE_P NB_CLK100M_PCIE_N PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N

3

84

29

10

30

29

10

30

84

14

7

84

30

29

14

7

84

29

30

29

84

30

13

79

29

13

84

30

79

29

30

29

30

29

30

29

30

29

30

29

30

29

30

29

30

29

30

29

30

22

7

16

84

29

16

84

7

30

22

29

84

30

9

29

66

84

30

29

9

66

29

24

30

84

29

24

84

30

84

29

34

29

30

84

30

23

29

84

29

30

23

84

29

7

16

30

84

29

7

16

30

34

29

84

34

29

30

84

30

29

30

35

29

84

30

35

29

84

29

10

30

10

29

84

29

7

14

30

84

29

7

14

30

84

30

13

29

79

29

79

13

84

30

47

7

30

24

30

38

30

45

25

30

25

30

7

29

16

84

7

30

22

30

22

7

16

84

29

84

30

9

29

66

84

30

9

29

66

30

24

29

84

30

24

29

84

34

29

30

84

30

29

34

84

29

23

30

84

29

23

30

16

7

84

29

30

16

7

84

29

84

30

29

34

84

30

29

34

12

D

C

B

CK505 SRC7 is project-specific

(CK505_SRC8) (CK505_SRC8)

CLK_PCIE_100D CLK_PCIE_100D

CLK_PCIE CLK_PCIE

PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N

84

30

29

35

84

30

29

35

SMC SMBus Net Properties

ELECTRICAL_CONSTRAINT_SET

SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL

A

8

67

5

SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA

SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S

4

PHYSICAL

NET_TYPE

SPACING

SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB

SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA

3

78

48

45

51

78

48

45

51

45

34

51

48

45

34

51

48

73

48

45

51

73

48

45

51

56

45

7

48

56

45

7

48

45

54

48

45

54

APPLE COMPUTER INC.

Clock & SMC Constraints

SYNC_MASTER=T9_NOME

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

D

SCALE

SYNC_DATE=01/17/2007

DRAWING NUMBER

051-7225

SHT

NONE

2

A

REV.

14.0.0

OF

8884

1

FireWire Interface Constraints

FW_55S

FW_110D

SPACING_RULE_SET

FW_TP

LAYER

ALLOW ROUTE ON LAYER?

=55_OHM_SE =55_OHM_SE

*

=110_OHM_DIFF

*

LINE-TO-LINE SPACING

*FW *

=2:1_SPACING =3:1_SPACING

MINIMUM LINE WIDTH

=110_OHM_DIFF =110_OHM_DIFF

WEIGHT

? ?

D

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

78

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=55_OHM_SE=55_OHM_SE

=110_OHM_DIFF

6

DIFFPAIR PRIMARY GAP

=110_OHM_DIFF =110_OHM_DIFF

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

5

FireWire Net Properties

ELECTRICAL_CONSTRAINT_SET

FW_D_CTL FW_D_CTL FW_LCLK CLK_MED

FW_PCLK CLK_MED

FW_LKON

FW_LPS FW_LREQ FW_PINT

FWPHY_CLK98P304M_XI

FW_0_TPA FW_0_TPA FW_0_TPB FW_0_TPB FW_1_TPA FW_1_TPA FW_1_TPB FW_1_TPB

4

PHYSICAL

FW_55S FW_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S FW_55S FW_55S FW_55S FW_55S FW_55S

CLK_MED_55S CLK_MED_55S

FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D

NET_TYPE

SPACING

FW FW

CLK_MED

CLK_MED FW FW FW FW FW

CLK_MED CLK_MED

FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP

FW_LINK<7..0> FW_CTL<1..0> CLKFW_LINK_LCLK CLKFW_PHY_LCLK CLKFW_LINK_PCLK CLKFW_PHY_PCLK FW_LKON FW_LKON_R FW_LPS FW_LREQ FW_PINT

CLK98P304M_FW_XI_R CLK98P304M_FW_XI

FW_PORT0_TPA_P FW_PORT0_TPA_N FW_PORT0_TPB_P FW_PORT0_TPB_N FW_PORT1_TPA_P FW_PORT1_TPA_N FW_PORT1_TPB_P FW_PORT1_TPB_N

3

39

38

39

38

39

38

39

38

39

38

41

39

41

39

41

39

41

39

41

39

41

39

41

39

41

39

12

D

Port 2 Not Used

C

B

C

B

FireWire Constraints

A

APPLE COMPUTER INC.

8

67

5

4

3

SYNC_MASTER=T9_NOME

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

2

NOTICE OF PROPRIETARY PROPERTY

SIZE

D

SCALE

SYNC_DATE=01/17/2007

DRAWING NUMBER

051-7225

SHT

NONE

A

REV.

14.0.0

OF

8885

1

78

GDDR3 Frame Buffer Signal Constraints

LAYER

GDDR3_40R50SE

GDDR3_50SE

GDDR3_80D

SPACING_RULE_SET

LAYER

GDDR3_CLK GDDR3_CMD

D

GDDR3_DATA

GDDR3_DQS

Video Signal Constraints

LAYER

TMDS_100D

VGA_50S VGA_55S

SPACING_RULE_SET

TMDS

VGA 20 MIL

VGA_SYNC

LAYER

ALLOW ROUTE ON LAYER?

=50_OHM_SE

*

=50_OHM_SE

*

=80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFF

*

LINE-TO-LINE SPACING

*

=2.5:1_SPACING =2.5:1_SPACING

* *

=2.5:1_SPACING

*

=2.5:1_SPACING

ALLOW ROUTE ON LAYER?

=100_OHM_DIFF

=50_OHM_SE =50_OHM_SE

* =STANDARD

MINIMUM LINE WIDTH

=40_OHM_SE =50_OHM_SE =50_OHM_SE

MINIMUM NECK WIDTH

=50_OHM_SE =50_OHM_SE

=80_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=100_OHM_DIFF

=50_OHM_SE

=55_OHM_SE =55_OHM_SE=55_OHM_SE =55_OHM_SE

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

* * *

LINE-TO-LINE SPACING

20 MIL

C

MAXIMUM NECK LENGTH

12.7 MM

=80_OHM_DIFF=80_OHM_DIFF

MAXIMUM NECK LENGTH

=100_OHM_DIFF=100_OHM_DIFF

=50_OHM_SE

6

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD =STANDARD =STANDARD

DIFFPAIR PRIMARY GAP

=100_OHM_DIFF*=100_OHM_DIFF

=STANDARD =STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD*

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

5

4

GDDR3 FB A/B Net Properties GDDR3 FB C/D Net Properties

ELECTRICAL_CONSTRAINT_SET

FB_A_CLK_P

FB_B_CLK_P

FB_AB_CMD GDDR3_CMD

FB_AB_CMD FB_AB_CMD GDDR3_CMD FB_AB_CMD_PD FB_AB_CMD FB_AB_CMD_PD

FB_A_CMD FB_B_CMD

FB_A_WDQS0 FB_A_WDQS1 FB_A_WDQS2 FB_A_WDQS3

FB_A_RDQS0 FB_A_RDQS1 FB_A_RDQS2 FB_A_RDQS3

FB_A_DQ_BYTE0 FB_A_DQ_BYTE1 FB_A_DQ_BYTE2 FB_A_DQ_BYTE3

FB_A_DQM0 FB_A_DQM1 FB_A_DQM2 FB_A_DQM3

FB_B_WDQS0 FB_B_WDQS1 FB_B_WDQS2 FB_B_WDQS3

FB_B_RDQS0 FB_B_RDQS1 FB_B_RDQS2 FB_B_RDQS3

FB_B_DQ_BYTE0 FB_B_DQ_BYTE1 FB_B_DQ_BYTE2 FB_B_DQ_BYTE3

FB_B_DQM0 FB_B_DQM1 FB_B_DQM2 FB_B_DQM3

PHYSICAL

GDDR3_80D GDDR3_80D GDDR3_80D GDDR3_CLK GDDR3_80D

GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE

GDDR3_50SE GDDR3_50SE

GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE

GDDR3_CLK GDDR3_CLK

GDDR3_CLK

GDDR3_CMDFB_AB_CMD

GDDR3_CMDFB_AB_CMD GDDR3_CMDFB_AB_CMD GDDR3_CMD

GDDR3_CMD GDDR3_CMD GDDR3_CMD

GDDR3_CMD GDDR3_CMD

GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS

GDDR3_DATAGDDR3_50SE GDDR3_DATAGDDR3_50SE GDDR3_DATAGDDR3_50SE GDDR3_DATAGDDR3_50SE

GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS

GDDR3_DATAGDDR3_50SE GDDR3_DATAGDDR3_50SE GDDR3_DATAGDDR3_50SE GDDR3_DATAGDDR3_50SE

FB_A_CLK_P<0> FB_A_CLK_N<0> FB_A_CLK_P<1> FB_A_CLK_N<1>

FB_A_MA<1..0> FB_A_MA<11..6> FB_A_BA<2..0> FB_A_RAS_L FB_A_CAS_L FB_A_WE_L FB_A_CKE FB_A_CS0_L FB_A_DRAM_RST

FB_A_LMA<5..2> FB_A_UMA<5..2>

FB_A_WDQS<0> FB_A_WDQS<1> FB_A_WDQS<2> FB_A_WDQS<3>

FB_A_RDQS<0> FB_A_RDQS<1> FB_A_RDQS<2> FB_A_RDQS<3>

FB_A_DQ<7..0> FB_A_DQ<15..8> FB_A_DQ<23..16> FB_A_DQ<31..24>

FB_A_DQM_L<0> FB_A_DQM_L<1> FB_A_DQM_L<2> FB_A_DQM_L<3>

FB_A_WDQS<4> FB_A_WDQS<5> FB_A_WDQS<6> FB_A_WDQS<7>

FB_A_RDQS<4> FB_A_RDQS<5> FB_A_RDQS<6> FB_A_RDQS<7>

FB_A_DQ<39..32> FB_A_DQ<47..40> FB_A_DQ<55..48> FB_A_DQ<63..56>

FB_A_DQM_L<4> FB_A_DQM_L<5> FB_A_DQM_L<6> FB_A_DQM_L<7>

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

68

69

3

ELECTRICAL_CONSTRAINT_SET

FB_C_CLK_P

FB_D_CLK_P

FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD_PD FB_CD_CMD FB_CD_CMD_PD

FB_C_CMD FB_D_CMD

FB_C_WDQS0 FB_C_WDQS1 FB_C_WDQS2 FB_C_WDQS3

FB_C_RDQS0 FB_C_RDQS1 FB_C_RDQS2 FB_C_RDQS3

FB_C_DQ_BYTE0 FB_C_DQ_BYTE1 FB_C_DQ_BYTE2 FB_C_DQ_BYTE3

FB_C_DQM0 FB_C_DQM1 FB_C_DQM2 FB_C_DQM3

FB_D_WDQS0 FB_D_WDQS1 FB_D_WDQS2 FB_D_WDQS3

FB_D_RDQS0 FB_D_RDQS1 FB_D_RDQS2 FB_D_RDQS3

FB_D_DQ_BYTE0 FB_D_DQ_BYTE1 FB_D_DQ_BYTE2 FB_D_DQ_BYTE3

FB_D_DQM0 FB_D_DQM1 FB_D_DQM2 FB_D_DQM3

PHYSICAL

GDDR3_80D GDDR3_80D GDDR3_80D GDDR3_80D

GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE

GDDR3_50SE GDDR3_50SE

GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE

NET_TYPENET_TYPE

SPACINGSPACING

GDDR3_CLK GDDR3_CLK GDDR3_CLK GDDR3_CLK

GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD

GDDR3_CMD GDDR3_CMD

GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS

GDDR3_DATAGDDR3_50SE GDDR3_DATAGDDR3_50SE GDDR3_DATAGDDR3_50SE GDDR3_DATAGDDR3_50SE

GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS

GDDR3_DATAGDDR3_50SE GDDR3_DATAGDDR3_50SE GDDR3_DATAGDDR3_50SE GDDR3_DATAGDDR3_50SE

FB_B_CLK_P<0> FB_B_CLK_N<0> FB_B_CLK_P<1> FB_B_CLK_N<1>

FB_B_MA<1..0> FB_B_MA<11..6> FB_B_BA<2..0> FB_B_RAS_L FB_B_CAS_L FB_B_WE_L FB_B_CKE FB_B_CS0_L FB_B_DRAM_RST

FB_B_LMA<5..2> FB_B_UMA<5..2>

FB_B_WDQS<0> FB_B_WDQS<1> FB_B_WDQS<2> FB_B_WDQS<3>

FB_B_RDQS<0> FB_B_RDQS<1> FB_B_RDQS<2> FB_B_RDQS<3>

FB_B_DQ<7..0> FB_B_DQ<15..8> FB_B_DQ<23..16> FB_B_DQ<31..24>

FB_B_DQM_L<0> FB_B_DQM_L<1> FB_B_DQM_L<2> FB_B_DQM_L<3>

FB_B_WDQS<4> FB_B_WDQS<5> FB_B_WDQS<6> FB_B_WDQS<7>

FB_B_RDQS<4> FB_B_RDQS<5> FB_B_RDQS<6> FB_B_RDQS<7>

FB_B_DQ<39..32> FB_B_DQ<47..40> FB_B_DQ<55..48> FB_B_DQ<63..56>

FB_B_DQM_L<4> FB_B_DQM_L<5> FB_B_DQM_L<6> FB_B_DQM_L<7>

12

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

70

68

D

C

G84M Net Properties

ELECTRICAL_CONSTRAINT_SET

(CK505_DOT96)

B

A

CK505_CLK27MSS

TMDS_CLK TMDS_CLK TMDS_DATA TMDS_DATA

VGA_R_TV_C VGA_G_TV_Y VGA_B_TV_COMP

VGA_SYNC VGA_SYNC VGA_SYNC

CLK_SLOW_55S CLK_SLOW_55S CLK_SLOW

CLK_SLOW_55S CLK_SLOW CLK_SLOW_55S CLK_SLOW

LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D

TMDS_100D TMDS_100D TMDS_100D TMDS_100D

VGA_50S VGA_50S VGA_50S

VGA_55S VGA_55S

PHYSICAL

NET_TYPE

SPACING

CLK_SLOW

LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS

TMDS TMDS TMDS TMDS

VGA VGA VGA

VGA_SYNC

GPU_CLK27M GPU_CLK27M_GATED

GPU_CLK27M_SS GPU_CLK27M_SS_GATED

LVDS_L_CLK_P LVDS_L_CLK_N LVDS_L_DATA_P<3..0> LVDS_L_DATA_N<3..0> LVDS_U_CLK_P LVDS_U_CLK_N LVDS_U_DATA_P<3..0> LVDS_U_DATA_N<3..0>

TMDS_CLK_P TMDS_CLK_N TMDS_DATA_P<5..0> TMDS_DATA_N<5..0>

GPU_TV_C_VGA_R GPU_TV_Y_VGA_G GPU_TV_COMP_VGA_B

GPU_VGA_R GPU_VGA_G GPU_VGA_B

GPU_TV_C GPU_TV_Y GPU_TV_COMP

GPU_VGA_HSYNC GPU_VGA_VSYNC

30

72

71

30

72

71

73

77

73

77

7

73

77

7

73

77

73

77

73

77

76

73

76

73

76

73

76

72

76

72

76

72

76

72

73

72

73

72

73

72

73

72

73

72

73

76

73

76

APPLE COMPUTER INC.

GPU (G84M) Constraints

SYNC_MASTER=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

DRAWING NUMBER

D

SCALE

NONE

SYNC_DATE=(MASTER)

051-7225

SHT

OF

REV.

14.0.0

8886

B

A

8

67

5

4

3

2

1

78

SENSE_1TO1_55S THERM_1TO1_55S

SPACING_RULE_SET

SENSE THERM

D

SPACING_RULE_SET

ENETCONN

SPACING_RULE_SET

GND

PP1V8_MEM

SPACING_RULE_SET

GND_P2MM PWR_P2MM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CLK MEM_CMD

MEM_CTRL GND_P2MM

MEM_DQS MEM_CLK

C

MEM_CMD

MEM_DATA

MEM_DQS

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CLINK_VREF

CLK_MED

CLK_PCIE

DMI PCIE SATA

DMI SATA

USB

NET_SPACING_TYPE1 NET_SPACING_TYPE2

B

LVDS

* *

ALLOW ROUTE ON LAYER?

=1:1_DIFFPAIR

LINE-TO-LINE SPACING

=2:1_SPACING =2:1_SPACING

LINE-TO-LINE SPACING

LAYER

*

LAYER

LINE-TO-LINE SPACING

* *

LAYER

LINE-TO-LINE SPACING

* *

GND GND GND GND

GND PP1V8_MEM PP1V8_MEM PP1V8_MEM PP1V8_MEM PP1V8_MEM

GND

GNDUSB

SB_POWERCLK_PCIE PWR_P2MM SB_POWER SB_POWER

GND

25 MILS

=STANDARD =STANDARD

0.20 MM

AREA_TYPE

* * * * * * * * * *

AREA_TYPE

* * * * * * * * * * *

AREA_TYPE

*

MINIMUM LINE WIDTH

=55_OHM_SE =55_OHM_SE =55_OHM_SE

WEIGHT

SPACING_RULE_SET

GND_P2MM GND_P2MM

GND_P2MMMEM_DATA GND_P2MM PWR_P2MM PWR_P2MM PWR_P2MMMEM_CTRL PWR_P2MM PWR_P2MM

SPACING_RULE_SET

GND_P2MM GND_P2MM GND_P2MM GND_P2MM GND_P2MM GND_P2MM GND_P2MM

PWR_P2MM PWR_P2MM PWR_P2MMSB_POWER

SPACING_RULE_SET

GND_P2MM

? ?

?

? ?

1000 1000

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

=55_OHM_SE

MAXIMUM NECK LENGTH

=55_OHM_SE

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CLK_FSB

CPU_COMP

CPU_GTLREF

CPU_VCCSENSE

FSB_DSTB

NET_SPACING_TYPE1 NET_SPACING_TYPE2

ENET_MDI ENET_MDI

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CLK_MED

DIFFPAIR PRIMARY GAP

GND GND GND GND GND

GND

ENET_POWER

FW_POWER

Memory Constraint Relaxations

Allow 0.127 mm necks for >0.127 mm lines for GMCH fanout.

LAYER

MEM_70D 6.35 MM

BOTTOM

Allow 0.1 mm necks for >0.1 mm lines between thru-hole SO-DIMM pins.

LAYER

MEM_45S

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_70D MEM_85D 2.54 MM

ISL10

ISL4,ISL10

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

0.127 MM

ALLOW ROUTE ON LAYER?

*

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.100 MM

MAXIMUM NECK LENGTH

2.54 MM

DIFFPAIR PRIMARY GAP

0.100 MM

6

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR

GND_P2MM GND_P2MM GND_P2MM GND_P2MM GND_P2MM

GND_P2MM PWR_P2MM

GND_P2MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

* * * * *

AREA_TYPE

* *

AREA_TYPE

*

SPACING_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

5

M75 Specific Net Properties

ELECTRICAL_CONSTRAINT_SET

(PCIE_EXCARD) (PCIE_EXCARD)

(PCIE_MINI) (PCIE_MINI)

(SATA_A_R2D) (SATA_A_R2D)

(SATA_A_D2R) (SATA_A_D2R)

(USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_EXTD) (USB_EXTD) (USB_CAMERA) (USB_CAMERA)

SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_DIFFPAIR

THERM_DIFFPAIR THERM_DIFFPAIR THERM_DIFFPAIR THERM_DIFFPAIR THERM_DIFFPAIR THERM_DIFFPAIR THERM_DIFFPAIR

(VGA_R_TV_Y) (VGA_G_TV_C) (VGA_B_TV_COMP)

(VGA_SYNC) (VGA_SYNC) (VGA_SYNC) (VGA_SYNC)

I119

I118

4

NET_TYPE

PHYSICAL

PCIE_100D PCIE_100D

ENET_100D ENET_100D ENET_100D ENET_100D

FW_110D FW_110D FW_110D FW_110D

SATA_100D SATA_100D

USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D

SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S

THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S

LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D

TMDS_100D TMDS_100D TMDS_100D TMDS_100D TMDS_100D TMDS_100D

VGA_50S VGA_50S VGA_50S

VGA_55S VGA_55S VGA_55S VGA_55S

SPACING

PCIE PCIE

ENET_MDI ENET_MDI ENETCONN ENETCONN

FW_TP FW_TP FW_TP FW_TP

SATA SATA

USB USB USB USB USB USB USB USB

SENSE SENSE SENSE SENSE

THERM THERM THERM THERM THERM THERM THERM

LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS

TMDS TMDS TMDS TMDS TMDS TMDS

VGA VGA VGA

VGA_SYNC VGA_SYNC VGA_SYNC VGA_SYNC

PP1V8_MEM PP1V8_MEM GND

SB_POWER SB_POWER SB_POWER

WWAN_SIMWWAN_SIM WWAN_SIMWWAN_SIM

PCIE_EXCARD_R2D_P PCIE_EXCARD_R2D_N

PCIE_MINI_R2D_P PCIE_MINI_R2D_N

ENET_MDI_R_P<3..0> ENET_MDI_R_N<3..0> ENETCONN_P<3..0> ENETCONN_N<3..0>

FW_PORT0_TPA_FL_P FW_PORT0_TPA_FL_N FW_PORT0_TPB_FL_P FW_PORT0_TPB_FL_N

SATA_A_R2D_UF_P SATA_A_R2D_UF_N

SATA_A_D2R_UF_P SATA_A_D2R_UF_N

USB2_EXTA_MUXED_P USB2_EXTA_MUXED_N USB2_RT_P USB2_RT_N USB_WWAN_F_P USB_WWAN_F_N USB_CAMERA_F_P USB_CAMERA_F_N

GFXIMVP6_VSEN_P NBCOREISNS_P P1V8ISNS_P P1V25ISNS_P

CPUTHMSNS_D2_P CPU_THERMD_P GPUTHMSNS_D_P GPU_TDIODE_P HSTHMSNS_D_P REMTHMSNS_DX_P RSFSTHMSNS_D_P

LVDS_L_CLK_CONN_F_P LVDS_L_CLK_CONN_F_N LVDS_L_CLK_CONN_P LVDS_L_CLK_CONN_N LVDS_L_DATA_CONN_P<3..0> LVDS_L_DATA_CONN_N<3..0> LVDS_U_CLK_CONN_P LVDS_U_CLK_CONN_N LVDS_U_DATA_CONN_P<3..0> LVDS_U_DATA_CONN_N<3..0>

TMDS_CLK_R_P TMDS_CLK_R_N TMDS_CLK_F_P TMDS_CLK_F_N TMDS_DATA_F_P<5..0> TMDS_DATA_F_N<5..0>

VGA_R VGA_G VGA_B

VGA_HSYNC_R VGA_VSYNC_R VGA_HSYNC VGA_VSYNC

PP1V8_S3 PP1V8_S3 GND

PP3V3_S5 PP3V3_S0 PP1V5_S0

WWAN_SIM_CLOCK WWAN_SIM_DATA

3

34

37

41

78

43

44

59

50

7

51

10

51

72

71

51

7

51

7

75

77

75

77

75

77

75

77

75

77

75

77

75

77

75

77

75

76

87

62

57

50

38

32

31

8

32

31

8

25

24

8

75

65

16

8

13

30

29

12

11

8

44

87

62

57

50

38

48

46

28

27

26

23

21

19

27

26

22

60

57

55

77 75 74 65 59 58 57 52

28

27

26

25

24

51 50 48 47 46 42 32 31

63

34

12

D

C

B

Graphics Constraint Relaxations

Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

PHYSICAL_RULE_SET

BGA BGA

A

NET_PHYSICAL_TYPE

LVDS_100D TMDS_100D

AREA_TYPE

100_DIFF_BGA 100_DIFF_BGA

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

SIM Card Constraints

WWAN_SIM

SPACING_RULE_SET

WWAN_SIM

*

ALLOW ROUTE ON LAYER?

=50_OHM_SE

LINE-TO-LINE SPACING

=2:1_SPACING

LAYER

8

MINIMUM LINE WIDTH

=50_OHM_SE =50_OHM_SE =50_OHM_SE

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

=50_OHM_SE

67

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=50_OHM_SE

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

M75 Specific Constraints

SYNC_MASTER=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

DRAWING NUMBER

APPLE COMPUTER INC.

5

4

3

2

D

SCALE

NONE

SYNC_DATE=(MASTER)

051-7225

SHT

OF

87 88

1

A

REV.

14.0.0

78

M75 Board-Specific Spacing & Physical Constraints

BOARD LAYERS

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

LAYER

DEFAULT

ALLOW ROUTE ON LAYER?

*

STANDARD

D

55_OHM_SE 55_OHM_SE

LAYER

TOP,BOTTOM ISL2,ISL11

55_OHM_SE

LAYER

50_OHM_SE

TOP,BOTTOM

50_OHM_SE

LAYER

45_OHM_SE

TOP,BOTTOM

45_OHM_SE

LAYER

40_OHM_SE

TOP,BOTTOM

ALLOW ROUTE ON LAYER?

* =STANDARDY

ALLOW ROUTE ON LAYER?

* Y =STANDARD =STANDARD

ALLOW ROUTE ON LAYER?

* Y =STANDARD =STANDARD

ALLOW ROUTE ON LAYER?

40_OHM_SE =STANDARD

ALLOW ROUTE ON LAYER?

* Y

C

27P4_OHM_SE 27P4_OHM_SE

LAYER

TOP,BOTTOM

Y Y*

Y Y

Y

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=55_OHM_SE

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.100 MM 0.100 MM

0.250 MM

0.076 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.125 MM 0.125 MM

0.090 MM 0.090 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.150 MM 0.150 MM

0.105 MM 0.105 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.335 MM 0.335 MM

0.240 MM 0.240 MM

=55_OHM_SE

=DEFAULT=DEFAULT

0.076 MM

0.185 MM0.185 MM

0.131 MM0.131 MM

BOARD AREAS

NO_TYPE,BGA

MAXIMUM NECK LENGTH

30 MM

12.7 MM

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

6

DIFFPAIR PRIMARY GAP

=STANDARD

BOARD UNITS (MIL or MM)

MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=DEFAULT=DEFAULT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARDY*

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

12

ALLEGRO VERSION

5

TABLE_BOARD_INFO

4

3

15.5.1

BGA_P1MM BGA_P2MM BGA_P2MM BGA_P2MM BGA_P2MM BGA_P2MM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

D

TABLE_PHYSICAL_RULE_HEAD

SPACING_RULE_SET

TABLE_PHYSICAL_RULE_ITEM

0 MM0 MM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

DEFAULT STANDARD BGA_P1MM BGA_P2MM =DEFAULT BGA_P3MM

SPACING_RULE_SET

1.5:1_SPACING

1.8:1_SPACING 2:1_SPACING

LAYER

2.5:1_SPACING

TABLE_PHYSICAL_RULE_HEAD

3:1_SPACING

TABLE_PHYSICAL_RULE_ITEM

4:1_SPACING

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

* * * * *

* * * * * *

LINE-TO-LINE SPACING

0.1 MM =DEFAULT =DEFAULT

=DEFAULT

LINE-TO-LINE SPACING

0.15 MM

0.18 MM

0.2 MM

0.25 MM

0.3 MM

0.4 MM

WEIGHT

? ? ? ? ?

WEIGHT

? ? ? ? ? ?

TABLE_SPACING_RULE_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MEM_CLK CLK_FSB

CLK_PCIE

CLK_MED CLK_SLOW FSB_DSTB BGA_P3MMFSB_DSTB

AREA_TYPE

** * * * * *

SPACING_RULE_SET

BGA BGA BGA BGA BGA BGA BGA

C

B

A

70_OHM_DIFF 70_OHM_DIFF 70_OHM_DIFF 70_OHM_DIFF 70_OHM_DIFF

80_OHM_DIFF 80_OHM_DIFF 80_OHM_DIFF 80_OHM_DIFF 80_OHM_DIFF

85_OHM_DIFF 85_OHM_DIFF 85_OHM_DIFF 85_OHM_DIFF 85_OHM_DIFF

90_OHM_DIFF 90_OHM_DIFF 90_OHM_DIFF 90_OHM_DIFF 90_OHM_DIFF

100_OHM_DIFF 100_OHM_DIFF 100_OHM_DIFF 100_OHM_DIFF 100_OHM_DIFF

110_OHM_DIFF 110_OHM_DIFF 110_OHM_DIFF 110_OHM_DIFF 110_OHM_DIFF

LAYER

*

ISL3,ISL4

ISL9,ISL10

ISL2,ISL11 TOP,BOTTOM

LAYER

*

ISL9,ISL10

ISL2,ISL11 TOP,BOTTOM

LAYER

*

ISL3,ISL4

ISL9,ISL10

ISL2,ISL11 TOP,BOTTOM

LAYER

*

ISL3,ISL4

ISL9,ISL10

ISL2,ISL11 TOP,BOTTOM

LAYER

*

ISL3,ISL4

ISL9,ISL10

ISL2,ISL11 TOP,BOTTOM

LAYER

*

ISL3,ISL4 ISL9,ISL10 ISL2,ISL11 TOP,BOTTOM

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

=STANDARD Y Y Y Y

N

0.149 MM 0.149 MM

0.149 MM

0.185 MM 0.185 MM

MINIMUM LINE WIDTH

=STANDARD =STANDARD YISL3,ISL4 Y Y Y

0.115 MM 0.115 MM

0.140 MM 0.140 MM

MINIMUM LINE WIDTH

=STANDARD =STANDARD Y Y Y Y

N =STANDARD =STANDARD

0.101 MM 0.101 MM

0.125 MM 0.125 MM

MINIMUM LINE WIDTH

=STANDARD Y Y Y

0.130 MM 0.130 MM

Y

MINIMUM LINE WIDTH

=STANDARD Y Y Y

0.080 MM

0.099 MM

Y

MINIMUM LINE WIDTH

N =STANDARD =STANDARD Y Y

0.077 MM 0.077 MM

0.077 MM 0.077 MM Y Y

MINIMUM NECK WIDTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

0.149 MM

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=STANDARD

0.115 MM0.115 MM

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=STANDARD

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=STANDARD=STANDARD

0.102 MM0.102 MM

0.130 MM0.130 MM

MINIMUM NECK WIDTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

0.080 MM

0.099 MM

0.099 MM0.099 MM

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=STANDARD=STANDARD =STANDARD

0.089 MM0.089 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0.125 MM 0.125 MM

0.125 MM

0.125 MM 0.125 MM

0.125 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0.125 MM 0.125 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD =STANDARDN

0.125 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0.220 MM 0.220 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0.200 MM 0.200 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0.330 MM 0.330 MM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARDN

0.125 MM

=STANDARD=STANDARD

0.125 MM0.125 MM

0.125 MM

0.125 MM0.125 MM

0.220 MM0.220 MM

=STANDARD=STANDARDN

0.200 MM0.200 MM

0.330 MM0.330 MM

1:1_DIFFPAIR

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

100_DIFF_BGA

TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM

100_DIFF_BGA

TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM

100_DIFF_BGA

TABLE_PHYSICAL_RULE_ITEM

NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LAYER

ISL3,ISL4 Y

ISL9,ISL10

*

ALLOW ROUTE ON LAYER?

Y*

ALLOW ROUTE ON LAYER?

=100_OHM_DIFF

Y

MINIMUM LINE WIDTH

=STANDARD

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=STANDARD =STANDARD

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

0.075 MM 0.075 MM

DIFFPAIR PRIMARY GAP

0.1 MM 0.1 MM

DIFFPAIR PRIMARY GAP

=100_OHM_DIFF =100_OHM_DIFF

0.125 MM 0.125 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

B

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

M75 Rule Definitions

SYNC_MASTER=(MASTER)

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE COMPUTER INC.

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

SIZE

DRAWING NUMBER

NONE

051-7225

SHT

D

SCALE

A

REV.

14.0.0

OF

8888

8

67

5

4

3

2

1

Apple macbook m75 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual