Apple iPhone7 Plus Schematic

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

D11 MLB - PVT

6 5 4 3

LAST_MODIFICATION=Wed Jul 6 08:55:26 2016

2 1

ECNREV DESCRIPTION OF REVISION

CK
APPD

DATE

2016-07-0600065328798 ENGINEERING RELEASED

D

C

B

<CSA>

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TABLE OF CONTENTS

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TABLE OF CONTENTS
SYSTEM:BOM TABLES
SYSTEM:EEEE CALLOUTS
SYSTEM:MECHANICAL COMPONENTS
SYSTEM: BOARDID
spare
SOC:JTAG,USB,XTAL
SOC:PCIE
SOC:MIPI AND ISP
SOC:LPDP
SOC:SERIAL
SOC:GPIO & UART
SOC:AOP
SOC:POWER (1/3)
SOC:POWER (2/3)
SOC:POWER (3/3)
NAND
SYSTEM POWER:PMU (1/3)
SYSTEM POWER:PMU (2/3)
SYSTEM POWER:PMU (3/3)
SYSTEM POWER:CHARGER
SYSTEM POWER:BATTERY CONN
SYSTEM POWER:BOOST
SENSORS
B2B FILTERS: UTAH
CAMERA:STROBE DRIVER
Accessory: Buck Circuit
TRINITY:FF SPECIFIC
B2B:FOREHEAD
B2B:NEVADA
AUDIO:CALTRA CODEC (1/2)
AUDIO:CALTRA CODEC (2/2)
AUDIO:SPEAKER AMP 2
AUDIO:SPEAKER AMP 1
ARC:DRIVER
ARC:MAGGIE
DISPLAY & MESA:POWER
B2B:ORB & MESA
B2B FILTERS: DISPLAY & TOUCH
TRISTAR 2
B2B:DOCK FLEX
spare
spare
B2B FILTERS: RIGHT BUTTON FLEX
B2B FF SPECIFIC

SYNC

<SYNC_MASTER1>
<SYNC_MASTER2>
<SYNC_MASTER3>
<SYNC_MASTER4>
<SYNC_MASTER5>

<SYNC_DATE1>

<SYNC_DATE2>

<SYNC_DATE3>

<SYNC_DATE4>

<SYNC_DATE5>

<SYNC_DATE27>

<SYNC_DATE30>

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<CSA>

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<CSA_PAGE78>

<CSA_PAGE79>

<CSA_PAGE80>

<CSA_PAGE81>

<CSA_PAGE82>

<CSA_PAGE83>

<CSA_PAGE84>

<CSA_PAGE85>

<CSA_PAGE86>

<CSA_PAGE87>

<CSA_PAGE88>

<CSA_PAGE89>

<CSA_PAGE90>

CONTENTSPAGEDATE

LARGE FORM FACTOR SPECIFIC
I2C MAP: AP, TOUCH, HOMER, I2C5
I2C MAP AOP
I2C TABLE
spare
spare
MLB UNIQUE
CELL,WIFI,NFC
page1
NFC
page1
METROCIRC [2]
UAT MATCH AND TUNER [3]
WIFI_MLB SCHEMATIC
PERENNIAL
WIFI FRONT-END [77]
page1
BOM_OMIT_TABLE
PMU: CONTROL AND CLOCKS
PMU: SWITCHERS AND LDOS
BASEBAND: POWER2
BASEBAND: CONTROL
BASEBAND GPIOS
TRANSCEIVER0/1: POWER
TRANSCEIVER0/1: TX PORTS
TRANSCEIVER0/1: PRX PORTS
RECEIVE MATCHING
LOWER ANTENNA & COUPLERS
DIVERSITY RECEIVE ASM'S
DIVERSITY RECEIVE LNA'S
UPPER ANTENNA FEEDS
PMU: ET MODULATOR
TEST POINTS & BOOT CONFIG
TDD TRANSMIT
FDD TRANSMIT
ICEFALL, SIM, DEBUG_CONN

<SYNC_MASTER48>
<SYNC_MASTER49>
<SYNC_MASTER50>
<SYNC_MASTER51>
<SYNC_MASTER52>
<SYNC_MASTER53>

<SYNC_MASTER71>
<SYNC_MASTER72>
<SYNC_MASTER73>
<SYNC_MASTER74>
d

<SYNC_MASTER78>
<SYNC_MASTER79>
<SYNC_MASTER80>
<SYNC_MASTER81>
<SYNC_MASTER82>
<SYNC_MASTER83>
<SYNC_MASTER84>
<SYNC_MASTER85>
<SYNC_MASTER86>
<SYNC_MASTER87>
<SYNC_MASTER88>
<SYNC_MASTER89>
<SYNC_MASTER90>

DATESYNC

<SYNC_DATE46>

<SYNC_DATE48>

<SYNC_DATE49>

<SYNC_DATE50>

<SYNC_DATE51>

<SYNC_DATE52>

<SYNC_DATE53>

<SYNC_DATE71>

<SYNC_DATE72>

<SYNC_DATE73>

<SYNC_DATE74>

<SYNC_DATE78>

<SYNC_DATE79>

<SYNC_DATE80>

<SYNC_DATE81>

<SYNC_DATE82>

<SYNC_DATE83>

<SYNC_DATE84>

<SYNC_DATE85>

<SYNC_DATE86>

<SYNC_DATE87>

<SYNC_DATE88>

<SYNC_DATE89>

<SYNC_DATE90>

C

B

A

Schematic & PCB Callouts

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

051-00482 SCH CRITICAL

820-00229 1 CRITICAL

SCH,MLB,D11-121

PCBPCBF,MLB,D11-12

BOM OPTIONCRITICAL

?

?

TABLE_5_HEAD

TABLE_5_ITEM

SCH 051-00482
BRD 820-00229
MCO 056-01585

System Block Diagram:

<rdar://problem/16684269>

3

TABLE OF CONTENTS

DRAWING TITLE

SCH,MLB,D11

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=03/01/2016SYNC_MASTER=david-copy

051-00482

REVISION

8.0.0

BRANCH

PAGE

1 OF 53

SHEET

1 OF 81

1245678

A

SIZEDRAWING NUMBER

D

34567 8

2 1

D

NAND BOM Options

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

NAND,H,32GB,16nm,MLC

335S00182

335S00183 CRITICAL

138S0867

138S00003

138S00003 5 CRITICAL

1 U1701 CRITICAL

NAND,H,128GB,16nm,TLC

NAND,T,256GB,3Dv3,TLC

1 U1701

CAP,X5R,10UF,20%,6.3V,0.65MM,HRZTL,0402 C1748,C1713,C1716,C1721,C1733

5 CRITICAL

5

CAP,X5R,15UF,20%,,6.3V,0.65MM,HRZTL,0402 C1748,C1713,C1716,C1721,C1733

CAP,X5R,15UF,20%,,6.3V,0.65MM,HRZTL,0402

PART NUMBER

C1748,C1713,C1716,C1721,C1733

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

335S00201 ALTERNATE T,15nm,MLC,32GBU1701335S00169

U1701ALTERNATE335S00169 S,16nm,MLC,32GB335S00209

335S00182 SS,1Ynm,TLC,128GB335S00195 ALTERNATE U1701

335S00180 U1701 T,15nm,TLC,128GBALTERNATE335S00182

335S00182 SD,15nm,TLC,128GBALTERNATE335S00179 U1701

335S00148 335S00183 SD,3Dv2,TLC,256GBU1701ALTERNATE

U1701335S00183 SS,3Dv3,TLC,256GB335S00190 ALTERNATE

#22686038:See Radar

CRITICAL1 U1701335S00169

CRITICAL

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

BOM OPTIONCRITICAL

NAND_32G

NAND_128G

NAND_256G

NAND_32G

NAND_128G

NAND_256G

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

Active Diode Alternate

PART NUMBER

376S00047 ALTERNATE376S00106 Q2101 DIODES INC. ACT DIODE

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

DDR PLL Alternate

PART NUMBER

155S00068155S00095

ALTERNATE FL1501

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

FERR BD,100OHM,25%,100MA,2OHM,01005

Power Inductor Alternates

PART NUMBER

152S00075152S00118

ALTERNATE ALL

ALTERNATE152S00077

ALL152S00397

152S00121 152S00081 ALTERNATE ALL

ALTERNATE152S1936152S00123 ALL

152S00366152S00402 ALLALTERNATE

152S00297 ALL152S1843 ALTERNATE

ALTERNATE152S00365 152S00297 ALL

ALTERNATE152S00398 152S00204 ALL

152S00120 ALTERNATE

152S00074152S00117

ALTERNATE

ALL152S00077

L1806,L1810,L1814,L1816,L1817

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

IND,PWR,SHLD,1.2 UH,3.0A,0.080 OHM,2016

IND,PWR,SHLD,1.0 UH,2.25A,0.150 OHM,2016

IND,PWR,SHLD,0.47 UH,3.8A,0.048 OHM,2012

IND,PWR,SHLD,15 UH,0.72A,0.900 OHM,3225

IND,MULT,1UH,1.2A,0.320 OHM,0603

CYNTEC 2012 1UH

CYNTEC 2012 1UH

IND,PWR,0.22UH,20%,6.7a,23MOHM,2012

For Chestnut inductor only

IND,PWR,SHLD,1.0 UH,3.0A,0.060 OHM,2016

Acc Buck Alternates

TABLE_ALT_HEAD

TABLE_ALT_ITEM

152S00558 ALTERNATE L2700152S00557

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Load Switch OMIT TABLE

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

updated 11/12

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

updated 11/12

TABLE_ALT_ITEM

reverted 11/13

TABLE_ALT_ITEM

TABLE_ALT_ITEM

For Chestnut inductor; so it doesn't interfere with PMU inducotr Buck 7 alts

TABLE_ALT_ITEM

Except BUCK5 LX (BUCK5 LX is Taiyo only)

TABLE_ALT_ITEM

353S01007 CRITICAL1

PART NUMBER

ALTERNATE371S00064371S00087 D2700

376S00164 ALTERNATE376S00166

ONSEMI,IC,LOAD,SWITCH,WLCSP4

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

DIODE,SHOTTKY,30V,200MA,0201

IND,MLD,0.47UH,2.5A,80Mohm,1608

Q2700,Q2701 PFET,12V,CSP4

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

U2710,NFCSW_RF

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

D

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

C

Magnesium Alternates

PART NUMBER

338S00203 ALTERNATE U2402338S00173

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

Larger Wafer (-29 flow) Magnesium

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Global R/C Alternates

PART NUMBER

118S0764 118S0717

138S0657 ALTERNATE ALL138S0702

138S0648 ALTERNATE

138S0986 ALTERNATE ALL138S00024

138S0706 138S0739 ALLALTERNATE

138S0739 ALTERNATE138S0945 ALL

132S0436

132S0400

ALTERNATE ALL

ALLALTERNATE138S0835138S00006

ALL138S0652

ALTERNATE ALL132S0400 132S0436

ALTERNATE

ALL

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

RES, 3.92K, 0.1%, 0201

CAP, X5R, 4.3UF, 4V, 0610

CAP, 3-TERM, 4.3UF, 4V, 0402

CAP,X5R,4.7UF,6.3V,0.65MM,0402,TAIYO

CAP,X5R,0.22UF,6.3V,01005,TDK

CAP,CER,3-TERM,7.5UF,20%,4V,0402,TAIYO/TDK

CAP,CER,1UF,20%,10V,X5R,0201,MURATA

CAP,CER,1UF,20%,10V,X5R,0201,KYOCERA

CAP,CER,X5R,0.22UF,20%,6.3V,20%

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

MUR+KYO 15UF

N&V 15uF Cap Alternates

PART NUMBER

138S00005 138S00003 ALTERNATE

138S00005 138S00003

ALTERNATE

138S00005 ALTERNATE138S00003

138S00005 ALTERNATE138S00003

138S00005 138S00003

138S00005

138S00005 138S00003

ALTERNATE

ALTERNATE138S00003

ALTERNATE

138S00005 138S00003 ALTERNATE

138S00005 138S00003 ALTERNATE

138S00005 ALTERNATE138S00003

138S00003 ALTERNATE138S00048

(C1818, C1825, C1831)

(C1837, C1842, C1844)

(C1819, C1826, C1832)

(C1838, C1843, C1845)

(C1401, C1408, C1434)

(C1813, C1820, C1827)

(C1833, C1839, C1865)

(C1814, C1821, C1828)

(C1834, C1866, C1414)

(C1806, C1810)

ALL

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

CAP,X5R,15UF,6.3V,0.65MM,0402,TY

CAP,X5R,15UF,6.3V,0.65MM,0402,TY

CAP,X5R,15UF,6.3V,0.65MM,0402,TY

CAP,X5R,15UF,6.3V,0.65MM,0402,TY

CAP,X5R,15UF,6.3V,0.65MM,0402,TY

CAP,X5R,15UF,6.3V,0.65MM,0402,TY

CAP,X5R,15UF,6.3V,0.65MM,0402,TY

CAP,X5R,15UF,6.3V,0.65MM,0402,TY

CAP,X5R,15UF,6.3V,0.65MM,0402,TY

CAP,X5R,15UF,6.3V,0.65MM,0402,TY

CAP,X5R,15UF,6.3V,0.65MM,0402,KYOCERA

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

C

CPU

GPU + GPU_SRAM

B

UT LDO Alternates

PART NUMBER

353S00889 353S00015 U2501ALTERNATE

Mamba LDO Alternates

PART NUMBER

353S00576353S00932 U3801

ALTERNATE

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

ST, LDO REG, 2.925V, CSP 0.65x0.65

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

ST, LDO REG, 2.75V

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Global Ferrite Alternates

PART NUMBER

155S0581 ALTERNATE ALL155S00067

155S00012 ALLALTERNATE155S00168

152S00489 ALL152S00456

ALTERNATE155S0581 ALL155S00067

ALLALTERNATE155S00194 155S0610

ALLALTERNATE155S00200 155S0610

ALTERNATE

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

FERR, 240OHM, 0.38OHM DCR, 0201

FERR, 240OHM, 0.38OHM DCR, 0201

FLTR, 65 OHMS, 0605

FERR BD, 150OHM, TDK

FERR BD, 150OHM, TY

FERR BD, 0.47UH, TY

Global Varistor Alternates

PART NUMBER

377S0140 ALL377S0168 ALTERNATE

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

VARISTOR, 6.8V, 100PF, 01005

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_HEAD

TABLE_ALT_ITEM

B

A

I2C5 Alternate

PART NUMBER

ALTERNATE335S00234 335S00233 U1101

8 7 5 4 2 1

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

I2C5 ALTERNATE

TABLE_ALT_HEAD

TABLE_ALT_ITEM

SYNC_MASTER=Sync

PAGE TITLE

SYNC_DATE=06/29/2016

A

SYSTEM:BOM TABLES

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

051-00482

REVISION

8.0.0

BRANCH

PAGE

2 OF 53

SHEET

2 OF 81

D

36

D

D11 EEEE CALLOUTS

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

EEEE CODE FOR 639-01812

EEEE CODE FOR 639-01813

EEEE CODE FOR 639-01814

1 CRITICAL825-6838

825-6838 1 CRITICALEEEE_H3RN

825-6838

825-6838

EEEE CODE FOR 639-02138

EEEE CODE FOR 639-02139

EEEE CODE FOR 639-02140

1

EEEE CODE FOR 639-02460

1

EEEE CODE FOR 639-02465

EEEE CODE FOR 639-02462

EEEE_GY2T1825-6838 CRITICAL

EEEE_GY2V1825-6838

EEEE_GY2W

EEEE_H3RP1 CRITICAL825-6838

EEEE_H3RQ825-6838

EEEE_H8C31 CRITICAL

CRITICAL

CRITICAL

CRITICAL825-6838 1 EEEE_H8C1

CRITICALEEEE_H8CK

BOM OPTIONCRITICAL

EEEE_D11_BEST_JP

EEEE_D11_SUPREME_JP

EEEE_D11_EXTREME_JP

EEEE_D11_BEST_ROW

EEEE_D11_SUPREME_ROW

EEEE_D11_EXTREME_ROW

EEEE_D11_BEST_CH

EEEE_D11_SUPREME_CH

EEEE_D11_EXTREME_CH

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

34567 8

2 1

D

C

CAYMAN DDR Alternates

TABLE_ALT_ITEM

ALTERNATE

ALL339S00258 DDR-S, 3G, B1339S00257

CAYMAN OMIT TABLE

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

339S00257 U07001 CRITICAL

CAYMAN, DDR-H, 3G, B1

2.2uF CAP Alts

TABLE_ALT_HEAD

PART NUMBER

138S00032

ALLALTERNATE138S00049 138S00032

ALL138S0831 ALTERNATE

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

CAP,CER,X5R,2,2UF,20%6.3V,20%, KYOCERA

TABLE_ALT_ITEM

CAP,CER,X5R,2,2UF,20%,6.3V,20%,MURATA

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

C

B

SIP Alternates

PART NUMBER

ALTERNATE ALL339M00009 339M00003 TRINITY BLUE,STATS

ALTERNATE ALL339M00008 339M00002 NEO,STATS

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

TABLE_ALT_ITEM

B

A

SYNC_MASTER=david-copy SYNC_DATE=03/01/2016

PAGE TITLE

SYSTEM:EEEE CALLOUTS

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00482

8.0.0

3 OF 53
3 OF 81

A

D

D

Current as of D11 MCO 056-01585 rev. 63

O

O

BS0415

2.70R1.80-NSP

1

UP_RFFE

BS0401

2.70R1.80-NSP

1

PTH per Rev63 for 1.8mm Drill

Contained in radio_mlb pages

BS0402

STDOFF-2.9OD0.888H-SM

NORTH_SCREW_EXPOSED

O

NEO Stiffener

BS0403

STDOFF-2.9OD0.81H-SM

1

CHASSIS_GND_BS402 CHASSIS_GND_BS403CHASSIS_GND_BS401

4 4 44 4

1

#25046211

1

C0413

220PF

5%
10V

2

C0G-CERM
01005

1

C0414

56PF

5%
25V

2

NP0-C0G-CERM
01005

1

C0415

18PF

2%
16V

2

CERM
01005

1

C0416

4PF

+/-0.1PF
16V

2

NP0-C0G
01005

TESTPOINTS

POWER

41 40 21

22 21

PP5V0_USB

PP_BATT_VCC

TP0420

1

TP-P55

ROOM=TEST

TP0421

1

TP-P55

ROOM=TEST

TP0415

1

TP-P55

ROOM=TEST

TP0422

1

TP-P55

ROOM=TEST

A

A

A

A

345678

POWER GROUND

VBUS

VBATT

PP_LCM_BL_CAT1_CONN

45 39

PP_LCM_BL_CAT2_CONN

45 39

PP_LCM_BL_ANODE_CONN

45 39

46 45

PP_LCM_BL34_CAT1_CONN

2 1

LCM

TP0409

1

TP-P55

ROOM=TEST

TP0410

1

TP-P55

ROOM=TEST

TP0411

1

TP-P55

ROOM=TEST

TP0417

1

TP-P55

ROOM=TEST

A

A

A

A

LCM BACKLIGHT SINK1

LCM BACKLIGHT SINK2

LCM BACKLIGHT SOURCE

LCM BACKLIGHT SINK3

D

C

B

CHASSIS_GND_BS401

44 4

1

C0401

220PF

5%
10V

2

C0G-CERM
01005

CHASSIS_GND_BS402

4

1

C0407

220PF

5%
10V

2

C0G-CERM
01005

CHASSIS_GND_BS403

4

1

C0417

220PF

5%
10V

2

C0G-CERM

1

2

1

2

1

2

C0402

220PF

5%
10V
C0G-CERM
01005

C0408

220PF

5%
10V
C0G-CERM
01005

C0418

220PF

5%
10V
C0G-CERM
0100501005

1

C0403

100PF

5%
16V

2

NP0-C0G
01005

1

C0409

100PF

5%
16V

2

NP0-C0G
01005

1

C0419

100PF

5%
16V

2

NP0-C0G
01005

1

C0404

56PF

5%
25V

2

NP0-C0G-CERM
01005

1

C0410

56PF

5%
25V

2

NP0-C0G-CERM
01005

1

C0420

56PF

5%
25V

2

NP0-C0G-CERM
01005

1

C0405

18PF

2%
16V

2

CERM
01005

1

C0411

18PF

2%
16V

2

CERM
01005

1

C0421

18PF

2%
16V

2

CERM

Back Shields

1

SH0400

SM

SHLD-SOFT-UP-BK-D11

1

SH0402

SM

SHLD-SOFT-LOWER-BK-D11

1

C0406

4PF

+/-0.1PF
16V

2

NP0-C0G
01005

1

C0412

4PF

+/-0.1PF
16V

2

NP0-C0G
01005

1

C0422

4PF

+/-0.1PF
16V

2

NP0-C0G
0100501005

BS0404

2.70R1.80-NSP

1

BS0405

STDOFF-2.9OD0.888H-SM

1

Front Shields

1

SH0401

SM

SHLD-UP-FRT-D11

1

SH0403

SM

SHLD-LOWER-FRT-D11

28 27 26 25 23 21 19 18 10 9
46 41 40 39 37 35 34 33 31 30

DFU

20 12

PMU_TO_AP_FORCE_DFU

E75

41 40

41 40

41 40

41 40

41 40

41 40

TRISTAR_CON_DETECT_L

41 40

90_TRISTAR_DP1_CONN_P

90_TRISTAR_DP1_CONN_N

90_TRISTAR_DP2_CONN_P

90_TRISTAR_DP2_CONN_N

PP_TRISTAR_ACC1

PP_TRISTAR_ACC2

AMUX

PMU_AMUX_AY

20

PMU_AMUX_BY

20

MOJAVE

53

PP_VDD_MAIN

#25244799

100k to 200k

TP0423

1

TP-P55

ROOM=TEST

TP0419

TP0408

1

TP-P55

ROOM=TEST

A

FD0408

FID

0P5SM1P0SQ-NSP

1

ROOM=TEST

VDD_MAIN

Note: Fiducial used as test point

PP_LCM_BL34_CAT2_CONN

46 45

PP_LCM_BL34_ANODE_CONN

46 45

1

ROOM=TEST

TP0418

1

ROOM=TEST

A

TP-P55

A

TP-P55

LCM BACKLIGHT SINK4

LCM BACKLIGHT SOURCE (3/4)

FIDUCIALS

FD0410

FID

TP0414

1

TP-P55

ROOM=TEST

TP0402

1

TP-P55

ROOM=TEST

TP0403

1

TP-P55

ROOM=TEST

TP0404

1

TP-P55

ROOM=TEST

TP0405

1

TP-P55

ROOM=TEST

TP0406

1

TP-P55

ROOM=TEST

TP0407

1

TP-P55

ROOM=TEST

TP0416

1

TP-P55

ROOM=TEST

TP0412

1

TP-P55

ROOM=TEST

TP0413

ROOM=TEST

1

R0413

200K

1%
1/32W
MF
01005

2

A

ROOM=SOC

1

TP-P55

A

FORCE DFU

A

A

A

A

A

ACCESSORY ID AND POWER

A

A

TP IS TO HELP WITH USB SI
IN THE FACTORY FIXTURE.

A

FOR DIAGS

A

ANALOG MUX A OUTPUT

ANALOG MUX B OUTPUT

Note: Fiducial used as test point

0P5SM1P0SQ-NSP

1

ROOM=ASSEMBLY

FD0409

FID

0P5SM1P0SQ-NSP

1

ROOM=ASSEMBLY

FD0405

FID

0P5SM1P0SQ-NSP

1

ROOM=ASSEMBLY

FD0406

0P5SQ-SMP3SQ-NSP

FID

1

ROOM=ASSEMBLY

FD0404

0P5SQ-SMP3SQ-NSP

FID

1

ROOM=ASSEMBLY

FD0403

0P5SQ-SMP3SQ-NSP

FID

1

ROOM=ASSEMBLY

FD0402

0P5SQ-SMP3SQ-NSP

FID

1

ROOM=ASSEMBLY

FD0401

0P5SQ-SMP3SQ-NSP

FID

1

ROOM=ASSEMBLY

FD0400

0P5SQ-SMP3SQ-NSP

FID

1

ROOM=ASSEMBLY

FD0407

FID

0P5SM1P0SQ-NSP

1

ROOM=TEST

FD0411

0P5SQ-SMP3SQ-NSP

FID

1

C

B

A

BS0406

CLIP-COAX-RETENTION-D11

CL0401

SM

1

STDOFF-2.9OD1.9ID-0.85H-SM

1

38 37

38 37

MESA_TO_BOOST_EN

PP16V0_MESA

TOP SIDE

8 7 5 4 2 1

TP0400

1

TP-P55

ROOM=TEST

TP0401

1

TP-P55

ROOM=TEST

A

A

SYNC_MASTER=sync SYNC_DATE=05/17/2016

PAGE TITLE

SYSTEM:MECHANICAL COMPONENTS

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

BRANCH

PAGE

SHEET

36

051-00482

8.0.0

4 OF 53
4 OF 81

A

D

345678

2 1

D

C

BOOTSTRAPPING:BOARD REV

12

BOARD_REV3

12

BOARD_REV2

BOARD_REV1

12

12

BOARD_REV0

BOARD_ID4=No connect

NOSTUFF

R0509

01005

NOSTUFF

R0505

01005

R0508

01005 MF

NOSTUFF

R0504

01005

ROOM=SOC

MF

5%

ROOM=SOC

MF

5%

ROOM=SOC

5%

ROOM=SOC

MF 5%

21

1/32W

21

1/32W

21

1/32W

21

1/32W

1.00K

1.00K

1.00K

1.00K

MAKE_BASE=TRUE

BOARD ID
BOOT CONFIG

PP1V8

SELECTED -->

52 48 47 46 39 30

BOARD_REV[3:0]

FLOAT=LOW, PULLUP=HIGH

1111 Pre-Proto w/D520 (non enclosure)
1110 PROTO1
1101 PROTO2
1100 PROTO2.5
1011 EVT
xxxx SPARE
1000 CARRIER
xxxx SPARE
0010 DVT
xxxx SPARE
0000 PVT

29 25 18 17 16 13 12 11 9 8 7

D

C

BOARD_ID3

11

11

BOARD_ID2

0=EUREKA, 1=KAROO

BOARD_ID1

11

0=FORM FACTOR A, 1=FORM FACTOR B

BOARD_ID0=No connect

PP1V8

12

BOOT_CONFIG1=No connect

R0502

NOSTUFF

R0503

R0501

ROOM=SOC

MF01005 1/32W

ROOM=SOC

ROOM=SOC

21

1.00K

5%

21

1.00K

5%MF01005 1/32W

21

1.00K

1/32W

5%MF01005

MAKE_BASE=TRUE

SELECTED -->

BOARD_ID[4:0]

FLOAT=LOW, PULLUP=HIGH
01000 D10 MLB
01001 D10 DEV
01010 D11 MLB
01011 D11 DEV
01100 D101 MLB
01101 D101 DEV
01110 D111 MLB
01111 D111 DEV

0=MLB, 1=DEV
0=FORM FACTOR A, 1=FORM FACTOR B
0=EUREKA, 1=KAROO

B

BOOT_CONFIG0=No connect

SELECTED -->

BOOT_CONFIG[2:0]

FLOAT=LOW, PULLUP=HIGH
000 SPI0
001 SPI0 TEST MODE
010 NVME0_X2
011 NVME0 X2 TEST
100 NVME0 X1
101 NVME0 X1 TEST
110 SLOW SPI0 TEST
111 FAST SPI0 TEST

B

A

PAGE TITLE

SYSTEM: BOARDID

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=03/01/2016SYNC_MASTER=david-copy

051-00482

8.0.0

5 OF 53

5 OF 81

A

D

34567 8

2 1

D

D

C

C

B

B

A

SYNC_MASTER=Sync

PAGE TITLE

spare

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00482

8.0.0

6 OF 53
6 OF 81

D

SYNC_DATE=06/06/2016

A

345678

2 1

D

SOC - USB, JTAG, XTAL

VDD18_AMUX: 1.62-1.98V @1mA MAX

PP1V1_XTAL

C0700

1

0.1UF

20%

2

6.3V
X5R-CERM
01005

ROOM=SOC

C0704

1

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

PP3V3_USB

FL0700

240-OHM-25%-0.20A-0.9DCR

21

01005

ROOM=SOC

30 19

VDD18_USB: 1.71-1.89V @20mA MAX

PP1V8

VDD11_XTAL:1.06-1.17V @TBD mA MAX

PP1V1

C0705

1

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

52 48 47 46 39 30

29 25 18 17 16 13 12 11 9 8 7 5

D

18 15

C

25 18 17 16 13 12 11 9 8 7 5

52 48 47 46 39 30 29

PP1V8

CKPLUS_WAIVE=PWRTERM2GND

CL20

VDD12_UH1_HSIC0

AJ60

VDD18_AMUX

CE25

VDD18_USB

U0700

CAYMAN-2GB-20NM-DDR-M

CSP

CG50

VDD11_XTAL

CG26

C0701

1

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

CC25

VDD33_USB

VDD_FIXED_USB

PP0V9_SOC_FIXED

3.14-3.46V @20mA MAX

18 15 10 9 8

tbd - tbd V @5mA MAX

C

B

Dev ONLY

40 37 20 13

PP0701

P2MM-NSM

SM

1

PP

40

SWD_DOCK_BI_AP_SWDIO
SWD_DOCK_TO_AP_SWCLK

40

20 13

PMU_TO_SYSTEM_COLD_RESET_L
PMU_TO_AOP_TRISTAR_ACTIVE_READY

20

AP_TO_PMU_TEST_CLKOUT

17

AP_TO_NAND_RESET_L

NC
NC

NC
NC
NC

CM22
CM20

CL31

CL29

CG37

CJ35
CK33
CH37

CM14

BJ3
BJ2

BL65

UH1_HSIC0_DATA
UH1_HSIC0_STB

JTAG_SEL

JTAG_TRST*
JTAG_TDO
JTAG_TDI
JTAG_TMS
JTAG_TCK

COLD_RESET*
CFSB
TST_CLKOUT

S3E_RESET*

SYM 1 OF 16

OMIT_TABLE

ANALOGMUX_OUT

USB_DP

USB_DM

USB_VBUS

USB_ID

USB_REXT

N64

CM26
CL26

CH26

CJ26

CK26

AP_TO_PMU_AMUX_OUT

90_USB_AP_DATA_P
90_USB_AP_DATA_N

USB_VBUS_DETECT

NC

AP_USB_REXT

20

40

40

21

1

R0700

200

1%
1/32W
MF

2

01005

ROOM=SOC

B

BJ4

HOLD_RESET

BL3

TESTMODE

WDOG

XI0

XO0

CK35

CM42
CL42

AP_TO_PMU_WDOG_RESET

XTAL_AP_24M_IN
XTAL_AP_24M_OUT

20

1

R0701

511K

1%
1/32W
MF

2

01005

ROOM=SOC

R0702

0.00

0%

1/32W

MF

01005

ROOM=SOC

CRITICAL
ROOM=SOC

Y0700

1.60X1.20MM-SM

24.000MHZ-30PPM-9.5PF-60OHM

21

SOC_24M_O

1

C0702

12PF

5%
16V

2

CERM
01005

ROOM=SOC

31

42

1

C0703

12PF

5%
16V

2

CERM
01005

ROOM=SOC

A

SYNC_MASTER=Sync

PAGE TITLE

SOC:JTAG,USB,XTAL

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00482

8.0.0

7 OF 53
7 OF 81

D

SYNC_DATE=06/06/2016

A

SOC - PCIE INTERFACES

345678

2 1

D

19 16 10

PP1V2_SOC

1

C0805

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

R0804

0.00

0%

1/32W

MF

01005

ROOM=SOC

21

VDD12_PCIE_REFBUF:1.08-1.26V @40mA MAX

PP1V2_SOC_PCIE_REFBUF

C0802

1

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

VDD12_PCIE: 1.14-1.26V @10mA MAX

1

C0801

0.1UF

20%

6.3V
X5R-CERM

2

01005

ROOM=SOC

CE58

VDD_FIXED_PCIE_xxx:0.855-0.990V @225mA MAX

PP0V9_SOC_FIXED

18 15 10 9 7

D

R0803

PP0V9_SOC_FIXED_PCIE_REFBUF

1

C0804

0.1UF

CC47

CA60

CE49

CC49

VDD12_PCIE

CA55

CC53

CC62

CE55

CE60

BW55

20%

2

6.3V
X5R-CERM
01005

ROOM=SOC

0.00

1/32W
01005

ROOM=SOC

21

0%
MF

C0803

1

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

C0800

1

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=SOC

1

C0806

2.2UF

20%

2

6.3V
X5R-CERM
0201-1

ROOM=SOC

C

17

17

17

17

17

17

PCIE LINK 0

17

17

29 25 18 17 16 13 12 11 9 7 5

PCIE_NAND_BI_AP_CLKREQ_L

PP1V8

1

R0805

100K

5%
1/32W
MF

2

01005

ROOM=SOC

52 48 47 46 39 30

90_PCIE_AP_TO_NAND_REFCLK_P
90_PCIE_AP_TO_NAND_REFCLK_N

#24557655:replace with 20% caps. SI no negative impact

GND_VOID=TRUE

21

C0807

ROOM=SOC

90_PCIE_NAND_TO_AP_RXD_P
90_PCIE_NAND_TO_AP_RXD_N 90_PCIE_NAND_TO_AP_RXD_C_N

D10 NAND is now Gen3 (was Gen2). Caps intentionally 0.22uF

90_PCIE_AP_TO_NAND_TXD_P
90_PCIE_AP_TO_NAND_TXD_N

PCIE_AP_TO_NAND_RESET_L

C0808

ROOM=SOC

C0809

ROOM=SOC

C0810

ROOM=SOC

20%
X5R 01005

20%
X5R

20%
X5R

20%
X5R

6.3V

GND_VOID=TRUE

21

6.3V
01005

GND_VOID=TRUE

21

6.3V
01005

GND_VOID=TRUE

21

6.3V
01005

0.22UF

0.22UF

0.22UF

0.22UF

90_PCIE_NAND_TO_AP_RXD_C_P

90_PCIE_AP_TO_NAND_TXD_C_P
90_PCIE_AP_TO_NAND_TXD_C_N

BC64

CJ48

CK48

CM46

CL46

CK44

CJ44

BJ65

PCIE_CLKREQ0*
PCIE_REF_CLK0_P

PCIE_REF_CLK0_N

PCIE_RX0_P
PCIE_RX0_N

PCIE_TX0_P
PCIE_TX0_N

PCIE_PERST0*

VDD12_PCIE_REFBUF

VDD_FIXED_PCIE_CLK

U0700

CAYMAN-2GB-20NM-DDR-M

CSP

SYM 2 OF 16

VDD_FIXED_PCIE_ANA

PCIE_CLKREQ3*

PCIE_REF_CLK3_P
PCIE_REF_CLK3_N

PCIE_PERST3*

VDD_FIXED_PCIE_REFBUF

PCIE_RX3_P
PCIE_RX3_N

PCIE_TX3_P
PCIE_TX3_N

BE66
CL64

CM64

CM61
CL61

CK63
CJ63

BJ66

PCIE_WLAN_BI_AP_CLKREQ_L
90_PCIE_AP_TO_WLAN_REFCLK_P

90_PCIE_AP_TO_WLAN_REFCLK_N

90_AP_PCIE3_RXD_C_P
90_AP_PCIE3_RXD_C_N

90_AP_PCIE3_TXD_C_P
90_AP_PCIE3_TXD_C_N

52

52

52

52

52

52

52

PCIE_AP_TO_WLAN_RESET_L

52

C

B

PCIE LINK 1

1

R0802

100K

5%
1/32W
MF

2

01005

ROOM=SOC

LINK 1 USED ON AP_DEV ONLY

NC
NC

NC

NC
NC

NC
NC

NC

CL54

CM54

CK52

CJ52

CM50

CL50

CH57

CG57

PCIE_CLKREQ1*
PCIE_REF_CLK1_P

PCIE_REF_CLK1_N

PCIE_RX1_P
PCIE_RX1_N

PCIE_TX1_P
PCIE_TX1_N

PCIE_PERST1*

PCIE_EXT_REF_CLK_P
PCIE_EXT_REF_CLK_N

LINK0

LINK1

LINK3

LINK2

PCIE_CLKREQ2*

PCIE_REF_CLK2_P
PCIE_REF_CLK2_N

PCIE_RX2_P
PCIE_RX2_N

PCIE_TX2_P
PCIE_TX2_N

PCIE_PERST2*

BE65BG66
CK59

CJ59

CK56
CJ56

CM57
CL57

BE64BG64

PCIE_BB_BI_AP_CLKREQ_L
90_PCIE_AP_TO_BB_REFCLK_P

90_PCIE_AP_TO_BB_REFCLK_N

WLAN RX PP's are now managed on Page 52

90_AP_PCIE2_RXD_C_P
90_AP_PCIE2_RXD_C_N

90_AP_PCIE2_TXD_C_P
90_AP_PCIE2_TXD_C_N

52

52

52

52

52

52

52

1

R0806

100K

5%
1/32W
MF
01005

2

ROOM=SOC

PCIE_AP_TO_BB_RESET_L

1

R0801

100K

5%
1/32W
MF
01005

ROOM=SOC

2

B

PCIE LINK 2 PCIE LINK 3

52

A

PCIE_REXT

CG63

AP_PCIE_RCAL

1

R0800

3.01K

1%
1/32W
MF
01005

2

ROOM=SOC

SYNC_MASTER=Sync

PAGE TITLE

SOC:PCIE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00482

REVISION

D

8.0.0

BRANCH

PAGE

8 OF 53

SHEET

8 OF 81

SYNC_DATE=06/06/2016

A

8 7 5 4 2 1

36

SOC - MIPI & ISP INTERFACES

345678

2 1

D

0.825-0.94V @25mA MAX

18 15 10 8 7

90_MIPI_NH_TO_AP_DATA0_P

45

90_MIPI_NH_TO_AP_DATA0_N

45

PP0V9_SOC_FIXED

1

C0902

2

ROOM=SOC

0.1UF

20%

6.3V
X5R-CERM
01005

1

C0900

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

A18

MIPI0C_DPDATA0

B18

MIPI0C_DNDATA0

G6

G17

G13

VDD_FIXED_MIPI

G10

G15

U0700

CAYMAN-2GB-20NM-DDR-M

CSP

SYM 3 OF 16

G21

G19

VDD18_MIPI

ISP_I2C0_SCL

ISP_I2C0_SDA

1.62-1.98V @7mA MAX

1

C0901

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

N65
N66

I2C_ISP_UT_SCL
I2C_ISP_UT_SDA

1

C0903

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

PP1V8

48

48

D

52 48 47 46 39 30

29 25 18 17 16 13 12 11 8 7 5

C

R0900

4.02K

1/32W
01005

ROOM=SOC

D11/111 ONLY

1%
MF

U64
R65

U65
U66

W64
W66

AA64

B50
A48
C48

A50
E50
AA65
AE64
AC65

I2C_ISP_NV_SCL
I2C_ISP_NV_SDA

I2C_ISP_NH_SCL
I2C_ISP_NH_SDA

NC
NC

NC

Dev ONLY

Spare

AP_TO_UT_CLK_R
AP_TO_NV_CLK_R

AP_TO_NH_CLK_R

AP_TO_UT_SHUTDOWN_L
AP_TO_NV_SHUTDOWN_L
AP_TO_NH_SHUTDOWN_L

TP_SENSOR3_RST

NC

48

48

46 30

46 30

C

R0906

30

25

30

29

D11/111 ONLY

D11/111 ONLY

1

PP

PP0902

SM

P2MM-NSM

ROOM=SOC

33.2

1/32W
01005

ROOM=SOC

R0907

33.2

1/32W
01005

ROOM=SOC

Radar 20511449

<--- Needed for Cayman debug; this pin cannot be input

1%
MF

1%
MF

21

NOSTUFF

1

C0906

100PF

5%
35V

2

NP0-C0G
01005

21

NOSTUFF

1

C0907

100PF

5%
35V

2

NP0-C0G
01005

AP_TO_UT_CLK

AP_TO_NH_CLK

25

29

NC
NC

NC
NC

B20

MIPI0C_DPDATA1

C20

MIPI0C_DNDATA1

C24

MIPI0C_DPDATA2

B24

MIPI0C_DNDATA2

A26

MIPI0C_DPDATA3

B26

MIPI0C_DNDATA3

B22

MIPI0C_DPCLK

A22

MIPI0C_DNCLK

E24

MIPI0C_REXT

B4

MIPID_DPDATA0

A4

MIPID_DNDATA0

B5

MIPID_DPDATA1

C5

MIPID_DNDATA1

C9

MIPID_DPDATA2

B9

MIPID_DNDATA2

A11

MIPID_DPDATA3

B11

MIPID_DNDATA3

ISP_I2C1_SCL

ISP_I2C1_SDA

ISP_I2C2_SCL

ISP_I2C2_SDA

ISP_I2C3_SCL

ISP_I2C3_SDA

SENSOR_INT

SENSOR0_CLK
SENSOR1_CLK
SENSOR2_CLK

SENSOR0_RST
SENSOR1_RST
SENSOR2_RST
SENSOR3_RST
SENSOR4_RST

90_MIPI_NH_TO_AP_DATA1_P

45

90_MIPI_NH_TO_AP_DATA1_N

45

45

90_MIPI_NH_TO_AP_CLK_P
90_MIPI_NH_TO_AP_CLK_N

45

MIPI0C_REXT

1

90_MIPI_AP_TO_LCM_DATA0_P

39

90_MIPI_AP_TO_LCM_DATA0_N

2

39

90_MIPI_AP_TO_LCM_DATA1_P

39

90_MIPI_AP_TO_LCM_DATA1_N

39

46

90_MIPI_AP_TO_LCM_DATA2_P

46

90_MIPI_AP_TO_LCM_DATA2_N

46

90_MIPI_AP_TO_LCM_DATA3_P

46

90_MIPI_AP_TO_LCM_DATA3_N

B

39

90_MIPI_AP_TO_LCM_CLK_P
90_MIPI_AP_TO_LCM_CLK_N

39

AP_TO_STROBE_DRIVER_HWEN

26

SPI_AP_TO_MAGGIE_CS_L

36

MIPID_REXT

1%

1/32W

MF

01005

1

2

R0901

4.02K

ROOM=SOC

NC

B7

MIPID_DPCLK

A7

MIPID_DNCLK

BN4

DISP_TOUCH_BSYNC0

BR2

DISP_TOUCH_BSYNC1

BR4

DISP_TOUCH_EB

E11

MIPID_REXT

SENSOR0_ISTRB
SENSOR1_ISTRB

SENSOR0_XSHUTDOWN
SENSOR1_XSHUTDOWN

MIPI1C_REXT

MIPI1C_DPDATA0
MIPI1C_DNDATA0

MIPI1C_DPDATA1
MIPI1C_DNDATA1

MIPI1C_DPCLK
MIPI1C_DNCLK

E52
D50

C50
B48

E16

B12
C12

B16
C16

B14
A14

NC_SENSOR0_ISTRB

NC

NC

AP_TO_MUON_BL_STROBE_EN

Per Radar 21221938

46 37

B

Dev only

A

28 27 26 25 23 21 19 18 10 4
46 41 40 39 37 35 34 33 31 30

53

8 7 5 4 2 1

PP_VDD_MAIN

1

C0904

220PF

5%
10V

2

C0G-CERM
01005

ROOM=SOC

AC return path for LCM MIPI which is referenced to GND and VDD_MAIN
Radar 21203307

1

C0905

220PF

5%
10V

2

C0G-CERM
01005

ROOM=SOC

1

C0908

220PF

5%
10V

2

C0G-CERM
01005

ROOM=SOC

1

C0909

220PF

5%
10V

2

C0G-CERM
01005

ROOM=SOC

1

C0910

220PF

5%
10V

2

C0G-CERM
01005

ROOM=SOC

SYNC_MASTER=Sync

PAGE TITLE

SYNC_DATE=06/06/2016

A

SOC:MIPI AND ISP

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

051-00482

REVISION

8.0.0

BRANCH

PAGE

9 OF 53

SHEET

9 OF 81

36

D

345678

2 1

D

19 16 8

PP1V2_SOC

1

C1013

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

VDD12_PLL_LPDP:1.14-1.26V @3mA MAX
VDD12_LPDP:1.14-1.26V @60mA MAX

1

C1001

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

1

C1004

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

1

C1005

0.01UF

10%

6.3V

2

X5R
01005

ROOM=SOC

90_LPDP_NV_TO_AP_D0_P

30

90_LPDP_NV_TO_AP_D0_N

30

1

C1002

15PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=SOC

Desense for Wifi frequencies

CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND

A54

LPDPRX_RX_D0_P

B54

LPDPRX_RX_D0_N

G25

G28

VDD12_LPDP_TX

G30

G55

G58

G60

VDD12_LPDP_RX

G62

G23

VDD12_PLL_LPDP

U0700

CAYMAN-2GB-20NM-DDR-M

CSP

SYM 4 OF 16

LPDP_TX0P
LPDP_TX0N

B27
C27

NC
NC

D

Dev ONLY

C

LPDP Lanes swapped between D10 and D11

D11/111 ONLY

D11/111 ONLY

90_LPDP_NV_TO_AP_D1_P

30

90_LPDP_NV_TO_AP_D1_N

30

90_LPDP_UT_TO_AP_D2_P

25

90_LPDP_UT_TO_AP_D2_N

25

90_LPDP_UT_TO_AP_D3_P

25

90_LPDP_UT_TO_AP_D3_N

25

GND ON MLB; other on Dev

30

LPDP_NV_BI_AP_AUX

LPDP_UT_BI_AP_AUX

25

NC

NC
NC

B56

LPDPRX_RX_D1_P

C56

LPDPRX_RX_D1_N

A61

LPDPRX_RX_D2_P

B61

LPDPRX_RX_D2_N

B63

LPDPRX_RX_D3_P

C63

LPDPRX_RX_D3_N

A64

LPDPRX_RX_D4_P

B64

LPDPRX_RX_D4_N

D54

LPDPRX_AUX_D0_P

E56

LPDPRX_AUX_D1_P

D61

LPDPRX_AUX_D2_P

E63

LPDPRX_AUX_D3_P

D64

LPDPRX_AUX_D4_P

LPDP_TX1P
LPDP_TX1N

LPDP_TX2P
LPDP_TX2N

LPDP_TX3P
LPDP_TX3N

LPDP_AUX_P
LPDP_AUX_N

LPDP_CAL_DRV_OUT

LPDP_CAL_VSS_EXT

A29
B29

B31
C31

A33
B33

D33
E33

E35
E31

NC
NC

C

NC
NC

NC

NC
NC

NC
NC

B

18 15 9 8 7

R1001

300

1%

1/32W

MF

01005-1

ROOM=SOC

C1006

100PF

5%

16V

NP0-C0G

01005

ROOM=SOC

GND ON MLB; other on Dev

PP0V9_SOC_FIXED

1

2

AP_LPDPRX_RCAL_NEG

1

2

#24401637:Unconnect LPDPRX_EXT_C

NC

B59

LPDPRX_BYP_CLK_P

C59

LPDPRX_BYP_CLK_N

A57

LPDPRX_RCAL_P

B57

LPDPRX_RCAL_N

D57

LPDPRX_EXT_C

EDP_HPD

DP_WAKEUP

BN3
AP2

NC
NC

Reserved for PanelID[1:0] on ap_dev board
Reserved for PanelID[1:0] on ap_dev board

B

A

53

28 27 26 25 23 21 19 18 9 4

46 41 40 39 37 35 34 33 31 30

8 7 5 4 2 1

PP_VDD_MAIN

1

C1010

33PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=SOC

AC return path for LCM LPDP which is referenced to GND and VDD_MAIN

1

C1011

33PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=SOC

SYNC_MASTER=Sync

PAGE TITLE

SOC:LPDP

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

36

REVISION

BRANCH

PAGE

SHEET

051-00482

8.0.0

10 OF 53
10 OF 81

D

SYNC_DATE=06/06/2016

A

SOC - SERIAL INTERFACES

345678

2 1

D

I2S_AP_TO_CODEC_MCLK

32

R1103

33.2

1%

1/32W

MF

01005

ROOM=SOC

D

CK7
CG12

AG64
AG66

U3
U4

AE66
AE65

I2C0_AP_SCL
I2C0_AP_SDA

I2C1_AP_SCL
I2C1_AP_SDA

I2C2_AP_SCL
I2C2_AP_SDA

I2C3_AP_SCL
I2C3_AP_SDA

47

47

47

47

47

47

47

47

NC

NC

BV65

BY66
BU64
BR64
BU65

D48
E48
A46
C46
E46

BU66
BR66
BN64
BN65

BJ64

I2S0_MCK
I2S0_BCLK
I2S0_LRCK
I2S0_DIN
I2S0_DOUT

I2S1_MCK
I2S1_BCLK
I2S1_LRCK
I2S1_DIN
I2S1_DOUT

I2S2_MCK
I2S2_BCLK
I2S2_LRCK
I2S2_DIN
I2S2_DOUT

U0700

CAYMAN-2GB-20NM-DDR-M

CSP

SYM 6 OF 16

21

I2S_AP_TO_CODEC_MCLK_R

32

I2S_AP_TO_CODEC_MSP_BCLK

32

I2S_AP_TO_CODEC_MSP_LRCLK

32

I2S_CODEC_TO_AP_MSP_DIN
I2S_AP_TO_CODEC_MSP_DOUT

32

I2S1/2/3 MCLK NC #24559456

53

I2S_AP_TO_BT_BCLK

53

I2S_AP_TO_BT_LRCLK

53

I2S_BT_TO_AP_DIN

53

I2S_AP_TO_BT_DOUT

36 35 34 33 32

36 35 34 33 32

I2S_MAGGIE_TO_AP_L26_CODEC_BCLK
I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK

36

I2S_MAGGIE_TO_AP_DIN

36

I2S_AP_TO_MAGGIE_DOUT

I2C0_SCL
I2C0_SDA

I2C1_SCL
I2C1_SDA

I2C2_SCL
I2C2_SDA

I2C3_SCL
I2C3_SDA

C

B

36 32

SPI_AP_TO_CODEC_MAGGIE_SCLK

Route as daisy-chain. No T's allowed.

SPI_AP_TO_TOUCH_SCLK

39

R1116

0.00

0%

1/32W

MF

01005

ROOM=SOC

R1101

0.00

0%

1/32W

MF

01005

ROOM=SOC

CH11

NC

53

I2S_BB_TO_AP_BCLK

53

I2S_BB_TO_AP_LRCLK

53

I2S_BB_TO_AP_DIN

53

I2S_AP_TO_BB_DOUT

5

BOARD_ID2

5

BOARD_ID1

BOARD_ID0

5

BOARD_ID3

36 32

SPI_CODEC_MAGGIE_TO_AP_MISO
SPI_AP_TO_CODEC_MAGGIE_MOSI

36 32

21

21

SPI_AP_TO_CODEC_MAGGIE_SCLK_R

32

SPI_AP_TO_CODEC_CS_L

39

SPI_TOUCH_TO_AP_MISO

39

SPI_AP_TO_TOUCH_MOSI
SPI_AP_TO_TOUCH_SCLK_R

39

SPI_AP_TO_TOUCH_CS_L

38

SPI_MESA_TO_AP_MISO

38

SPI_AP_TO_MESA_MOSI

38

SPI_AP_TO_MESA_SCLK

38

MESA_TO_AP_INT

CG18

NC

CM7

CK9

CJ9

CB2
BY4
BY3
CB4

N2
N3
N4
R3

C44
B44
A44
D44

B42
A42
E44
C42

I2S3_MCK
I2S3_BCLK
I2S3_LRCK
I2S3_DIN
I2S3_DOUT

SPI0_MISO
SPI0_MOSI
SPI0_SCLK
SPI0_SSIN

SPI1_MISO
SPI1_MOSI
SPI1_SCLK
SPI1_SSIN

SPI2_MISO
SPI2_MOSI
SPI2_SCLK
SPI2_SSIN

SPI3_MISO
SPI3_MOSI
SPI3_SCLK
SPI3_SSIN

SPI4_SCLK

SPI4_MISO
SPI4_MOSI

I2C5_SCL
I2C5_SDA

GPIO_42
GPIO_43

PMU_SCLK
PMU_MISO
PMU_MOSI

DWI_CLK

DWI_DO

DROOP

GPU_TRIGGER

SOCHOT

CLK32K_OUT

NAND_SYS_CLK

CJ12

NC

CG22

NC

CM9

NC

CH16
CJ14

CH20

NC

CH22

NC

AH65

SPI_PMGR_TO_PMU_SCLK

AH66

SPI_PMU_TO_PMGR_MISO

AK64

SPI_PMGR_TO_PMU_MOSI

AK65

DWI_PMGR_TO_BACKLIGHT_CLK

AM64

DWI_PMGR_TO_BACKLIGHT_DATA

AE3
BY2

AG4

AM66

AP_TO_CUMULUS_CLK32K

BN66

AP_TO_NAND_SYS_CLK_R

I2C5_SCL
I2C5_SDA

R1118

0.00

0%

1/32W

MF

01005

ROOM=SOC

20

20

20

39

C

47 11

47 11

PP1V8

1

R1113

10K

5%
1/32W
MF
01005

2

ROOM=SOC

46 37

46 37

1

R1114

10K

5%
1/32W
MF
01005

2

ROOM=SOC

52 48 47 46 39 30

PMU_TO_AP_PRE_UVLO_L
PMU_TO_AP_THROTTLE_GPU_L

AP_TO_PMU_SOCHOT_L

29 25 18 17 16 13 12 11 9 8 7 5

20

20

20

B

21

AP_TO_NAND_SYS_CLK

17

A

25 18 17 16 13 12 11 9 8 7 5

52 48 47 46 39 30 29

PP1V8

I2C5

See Radar#25316444 for Details

1

C1101

1.0UF

2

20%

6.3V
X5R
0201-1

ROOM=SOC

SCL

VCC

U1101

WLCSP

VSS

ROOM=SOC

CRITICAL

B2 A1

SDA

A2B1

I2C5_SDA
I2C5_SCL

47 11

47 11

To Cayman

SYNC_MASTER=Sync

PAGE TITLE

SOC:SERIAL

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00482

REVISION

D

8.0.0

BRANCH

PAGE

11 OF 53

SHEET

11 OF 81

SYNC_DATE=06/06/2016

A

8 7 5 4 2 1

36

.

345678

2 1

D

C

B

36

29 25 18 17 16 13 11 9 8 7 5

52 48 47 46 39 30

20

#24557547:Delete R1204

MAGGIE_TO_AP_CDONE

PP1V8

Nostuff per #24511702

PMU_TO_AP_THROTTLE_CPU_L

D101/D111 ONLY
D101/D111 ONLY

D101/D111 ONLY

NOSTUFF

1

R1210

10K

5%
1/32W
MF
01005

ROOM=SOC

2

D10/D11 ONLY

Dev only

SOC - GPIO INTERFACES

AP_TO_ACC_BUCK_VSEL

27

AP_TO_MAGGIE_CRESETB_L

36

44 20

BUTTON_VOL_UP_L

DEV ONLY

AP_TO_BB_RESET_L

53

RESERVERD FOR SSHB ID ON DEV BOARD

NC_AP_TO_BB_IPC_GPIO2
NC_AP_TO_GNSS_WAKE
AP_TO_BB_TIME_MARK

53

NC_AP_TO_GNSS_TIME_MARK

BB_TO_AP_RESET_DETECT_L

53

33

AP_TO_SPKAMP2_RESET_L
ALS_TO_AP_INT_L

29

53

AP_TO_NFC_FW_DWLD_REQ

AP_TO_NAND_FW_STRAP

17

39

TOUCH_TO_AP_INT_L

AP_TO_BBPMU_RADIO_ON_L

53

AP_TO_ICEFALL_FW_DWLD_REQ

53

AP_TO_LCM_RESET_L

39

AP_BI_HOMER_BOOTLOADER_ALIVE

36

20 4

PMU_TO_AP_FORCE_DFU
NC_DFU_STATUS

5

PP1V8

AP_TO_NFC_DEV_WAKE

53

20

PMU_TO_AP_BUF_RINGER_A

53

AP_TO_BT_WAKE

53

AP_TO_WLAN_DEVICE_WAKE

5

BOARD_REV3

5

BOARD_REV2
BOARD_REV1

5

BOARD_REV0

5

AP_TO_TOUCH_MAMBA_RESET_L

39

53

AP_TO_BB_MESA_ON
AP_TO_BB_COREDUMP

53

AP_TO_BB_IPC_GPIO1

53

BOOT_CONFIG0

#24608280

BOOT_CONFIG1

BOARD_ID4

NC

NC

NC

NC

NC

NC

BB64
BC65
BB66
AY65
AY66
AV65
AV67

AT67
AT66

AT64
AP66
AP65
AH64

AE4
AC3
AE2
BB2
BB4
BC3
BC4
BE2
BE4
BE3
BG2

CJ11

CL9

CH14

CK11

CG20

AA2
AA3

D42
E42
A41
C41
E41
A39
AT4

AT2
AV3
AY2
AY3

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25
GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPIO_32
GPIO_33
GPIO_34
GPIO_35
GPIO_36
GPIO_37
GPIO_38
GPIO_39
GPIO_40
GPIO_41

U0700

CAYMAN-2GB-20NM-DDR-M

CSP

SYM 5 OF 16

TMR32_PWM0
TMR32_PWM1
TMR32_PWM2

UART5_RTXD

UART0_RXD

UART0_TXD

UART1_CTS*
UART1_RTS*

UART1_RXD

UART1_TXD

UART2_CTS*
UART2_RTS*

UART2_RXD

UART2_TXD

UART3_CTS*
UART3_RTS*

UART3_RXD

UART3_TXD

UART4_CTS*
UART4_RTS*

UART4_RXD

UART4_TXD

UART6_RXD

UART6_TXD

UART7_RXD

UART7_TXD

AG2
AH4
AH3

CL5
CJ7

E39
D39
C39
B39

AM4
AK3
AK4
AH2

AA4
W2
W4
U2

D37
C37
B37
A37

BG4

CG16
CG14

AP3
AM2

NC

PROX_BI_AP_AOP_INT_PWM_L
NC_BB_TO_AP_RESET_ACT_L

UART_AP_DEBUG_RXD
UART_AP_DEBUG_TXD

UART_BT_TO_AP_CTS_L
UART_AP_TO_BT_RTS_L
UART_BT_TO_AP_RXD
UART_AP_TO_BT_TXD

NC_AP_UART2_CTS_L
NC_AP_UART2_RTS_L
NC_AP_UART2_RXD
NC_AP_UART2_TXD

UART_NFC_TO_AP_CTS_L
UART_AP_TO_NFC_RTS_L
UART_NFC_TO_AP_RXD
UART_AP_TO_NFC_TXD

UART_WLAN_TO_AP_CTS_L
UART_AP_TO_WLAN_RTS_L
UART_WLAN_TO_AP_RXD
UART_AP_TO_WLAN_TXD

SWI_AP_BI_TIGRIS

UART_ACCESSORY_TO_AP_RXD
UART_AP_TO_ACCESSORY_TXD

UART_HOMER_TO_AP_RXD
UART_AP_TO_HOMER_TXD

40

40

53

53

53

53

53

53

53

53

53

53

53

53

21

40

40

36

36

D

29 13

D101/D111 ONLY

C

D101/D111 ONLY; for GNSS

B

A

20

PMU_TO_AP_BUF_POWER_KEY_L
PMU_TO_AP_BUF_VOL_DOWN_L

20

#25120460:REQUEST_DFU Assignment

BU2
BU3

REQUEST_DFU1
REQUEST_DFU2

SYNC_MASTER=Sync

PAGE TITLE

SYNC_DATE=06/06/2016

A

SOC:GPIO & UART

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00482

8.0.0

12 OF 53
12 OF 81

D

SOC - AOP

345678

2 1

D

C

#24512059: Remove R1300 PU

Use internal pullup in SOC (AOP side).

Plan to use internal pullup in AOP. Radar 21210869

20

20 15

24

24

29 12

24

24

24

24

53 39 23 20

40

36

24

24

24

35 34 33 32

48

20

AOP_TO_PMU_SLEEP1_REQUEST
PMU_TO_AOP_SLEEP1_READY

SPI_AOP_TO_COMPASS_CS_L
COMPASS_TO_AOP_INT
PROX_BI_AP_AOP_INT_PWM_L
ACCEL_GYRO_TO_AOP_DATARDY
SPI_AOP_TO_ACCEL_GYRO_CS_L
ACCEL_GYRO_TO_AOP_INT
SPI_AOP_TO_PHOSPHORUS_CS_L
LCM_TO_MANY_BSYNC
TRISTAR_TO_AOP_INT
AOP_TO_MAGGIE_EN

PHOSPHORUS_TO_AOP_INT_L
SPI_AOP_TO_BOT_ACCEL_GYRO_CS_L

BOT_ACCEL_GYRO_TO_AOP_DATARDY

AUDIO_TO_AOP_INT_L

AOP_TO_MESA_I2C_ISO_EN

PMU_TO_AOP_IRQ_L

CM16
CM29

CK12
CK16
CK18

CJ29
CG31
CH31

CK20

CJ31

CK27
CK24
CK29
CK22

CM12

CK31

CG33

CJ33

CAYMAN-2GB-20NM-DDR-M

AOP_DDR_REQ
AOP_DDR_RESET*

AOP_FUNC_0
AOP_FUNC_1
AOP_FUNC_2
AOP_FUNC_3
AOP_FUNC_4
AOP_FUNC_5
AOP_FUNC_6
AOP_FUNC_7
AOP_FUNC_8
AOP_FUNC_9
AOP_FUNC_10
AOP_FUNC_11
AOP_FUNC_12
AOP_FUNC_13
AOP_FUNC_14
AOP_FUNC_15

U0700

CSP

SYM 7 OF 16

CFSB_AOP

AWAKE_REQ

AWAKE_RESET*

AOP_PDM_CLK0
AOP_PDM_DATA0
AOP_PDM_DATA1

RT_CLK32768

AOP_SWD_TCK_OUT

AOP_SWD_TMS0
AOP_SWD_TMS1

SWD_TMS2
SWD_TMS3

CH35
CM31

CJ37
CM37

CH41
CK39

CM33
CL14

CL16
CG35
BU4
BV3

PP1V8

NOSTUFF

1

R1304

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

PMU_TO_SYSTEM_COLD_RESET_L
AOP_TO_PMU_ACTIVE_REQUEST

PMU_TO_AOP_TRISTAR_ACTIVE_READY

AOP_TO_MESA_BLANKING_EN

AOP_TO_WLAN_CONTEXT_B
AOP_TO_WLAN_CONTEXT_A

PMU_TO_AOP_CLK32K
SWD_AP_TO_MANY_SWCLK

HOMER_TO_AOP_WAKE_INT
SWD_AOP_BI_BB_SWDIO
SWD_AP_BI_NAND_SWDIO
SWD_AP_BI_HOMER_SWDIO

D

52 48 47 46 39

30 29 25 18 17 16 12 11 9 8 7 5

20 7

20

40 37 20 7

38

53

53

20

C

36

53

17

36

53 36 17

BB_SWDIO has pullup in Radio_MLB pages

B

#25756894:North Carbon R1

#25756894:South Carbon R2

24

24

SPI_AOP_TO_IMU_SCLK_R2

36 35 34 33

I2S_AOP_TO_MAGGIE_L26_MCLK

R1305

49.9

ROOM=SOC

1%

1/32W

MF

01005

21

R1306

49.9

ROOM=SOC

1%

1/32W

MF

01005

21

SPI_AOP_TO_IMU_SCLKSPI_AOP_TO_IMU_SCLK_R1

R1303

33.2

1%

1/32W

MF

01005

ROOM=SOC

I2C_AOP_SCL

48

48

I2C_AOP_SDA

24

SPI_IMU_TO_AOP_MISO
SPI_AOP_TO_IMU_MOSI

24

UART_BB_TO_AOP_RXD

53

53

UART_AOP_TO_BB_TXD

36

MAGGIE_TO_AOP_INT

36

UART_AOP_TO_MAGGIE_TXD
UART_TOUCH_TO_AOP_RXD

39

39

UART_AOP_TO_TOUCH_TXD

32

I2S_CODEC_XSP_TO_AOP_BCLK
I2S_CODEC_XSP_TO_AOP_DIN

32

21

I2S_AOP_TO_MAGGIE_L26_MCLK_R
I2S_CODEC_XSP_TO_AOP_LRCLK

32

32

I2S_AOP_TO_CODEC_XSP_DOUT

CM11

CJ24

CJ18
CJ27
CJ16

CK14

CJ20
CJ22

CL11

CG29

CH29

CL35
CJ39

CM35

CK37

CG39

AOP_I2C0_SCL
AOP_I2C0_SDA

AOP_SPI_MISO
AOP_SPI_MOSI
AOP_SPI_SCLK

AOP_UART0_RXD
AOP_UART0_TXD

AOP_UART1_RXD
AOP_UART1_TXD

AOP_UART2_RXD
AOP_UART2_TXD

AOP_I2S_BCLK
AOP_I2S_DIN
AOP_I2S_MCK
AOP_I2S_LRCK

AOP_I2S_DOUT

DOCK_ATTENTION

DOCK_CONNECT

CG41
CL37

AOP_TO_SPKAMP1_ARC_RESET_L

MESA_TO_AOP_FDINT

B

35 34

38

DOCK_CONNECT can be GPIO, but input only. Radar 21680759

A

SYNC_MASTER=Sync

PAGE TITLE

SOC:AOP

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00482

8.0.0

13 OF 53
13 OF 81

D

SYNC_DATE=06/06/2016

A

SOC - CPU, GPU & SOC RAILS

345678

2 1

D

C

B

PP_CPU_VAR

1.06V @17.4A MAX

0.9V @tbd A MAX

0.625V @tbd A MAX

1

C1401

15UF

20%

6.3V

2

X5R
0402-1

ROOM=SOC

C1404

7.5UF

20%

4V

CERM CERM

1

432

ROOM=SOC

C1405

4.3UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1406

0.47UF

20%

6.3V
CERM
0402

1

432

1

2

ROOM=SOC

C1411

7.5UF

1

ROOM=SOC

C1412

4.3UF

1

ROOM=SOC

C1413

0.47UF

1

1.06V @1.0A MAX

0.80V @TBDA MAX

18

PP_CPU_SRAM_VAR

ROOM=SOC

C1407

7.5UF

20%

4V
CERM
0402

1

1.03V @1.44A MAX

0.92V @1.50A MAX

0.80V @TBD A MAX

18

PP_GPU_SRAM_VAR

3

4

2

18 14

C1408

15UF

20%

6.3V
X5R
0402-1

20%

4V

0402

432

20%

4V
CERM
0402

432

20%

6.3V
CERM
0402

432

ROOM=SOC

C1435

7.5UF

20%

4V

CER

0402

1

4

2

ROOM=SOC

C1439

7.5UF

20%

4V

CER

0402

1

1

2

ROOM=SOC

C1417

7.5UF

1

ROOM=SOC

C1418

1UF

20%

CERM
0402

1

ROOM=SOC

C1419

0.47UF

20%

6.3V
CERM
0402

1

3

C1434

15UF

20%

6.3V
X5R
0402-1

20%

4V
CERM
0402

432

4V

432

432

18

ROOM=SOC

C1433

7.5UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1437

7.5UF

20%

4V
CERM
0402

1

1

2

ROOM=SOC

C1422

4.3UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1423

1UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1424

0.47UF

20%

6.3V
CERM
0402

1

432

ROOM=SOC

C1427

4.3UF

20%

4V
CERM
0402

1

ROOM=SOC

C1428

1UF 1UF

20%

4V
CERM
0402

1

ROOM=SOC

C1460

7.5UF

20%

4V
CERM
0402

1

BUCK0_PP_CPU_FB

C1458

1

10UF

20%

2

6.3V
CERM-X5R
0402-9

ROOM=SOC

1

C1459

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=SOC

C1449

2.2UF

20%

6.3V
X5R-CERM
0201-1

ROOM=SOC

ROOM=SOC

C1430

4.3UF

20%

CERM
04020402

1

432

ROOM=SOC

C1431

20%

CERM
0402

1

432

ROOM=SOC

C1461

7.5UF

20%

CERM
0402

1

432

OMIT

XW1402

SHORT-20L-0

NO_XNET_CONNECTION

2 1

ROOM=SOC

4V

432

4V

432

4V

432

.05MM-SM

AD10
AD15
AD19
AD23

AF13
AF17
AJ23
AL21

AL8
AN10
AN19
AN23
AR13
AR17
AR21
AU10
AU15

AW13
AW17
AW21

BA10
BA23
BD21

BD8
BF10
BF23

BH13
BH17
BH21
BK10
BK15

AJ10

AF8

AN15

AR8

AU19

AW8
BA15
BA19

BH8

AF43
AF47
AF51

P17
P21
P25
P30
P34
P38
P43
P47
P51
Y15
Y19
Y23
Y40
Y45
Y49
Y53

CAYMAN-2GB-20NM-DDR-M

VDD_CPU

VDD_CPU_SRAM

VDD_GPU_SRAM

U0700

CSP

SYM 8 OF 16

VDD_GPU

VDD_CPU_SENSE

VSS_CPU_SENSE

VDD_GPU_SENSE

VDD_SOC_SENSE

VSS_SENSE

AB13
AB17
AB21
AB25
AB43
AB47
AB51
AB55
AD40
AD45
AD49
AD53
AF55
AJ40
AJ49
AJ53
J25
J30
J38
J43
J47
J51
L15
L19
L23
L28
L32
L36
L40
L45
L49
L53
P13
T15
T36
T40
T53
V13
V25
V34
V38
V51
V55
Y28

BK23

BK21

TP_AP_VSS_CPU_SENSE

AJ45

AL47

TP_VDD_SOC_SENSE

AJ47

TP_VSS_SENSE

1

2

ROOM=SOC

C1402

4.3UF

20%

4V
CERM
0402

1

432

OMIT

NO_XNET_CONNECTION

C1414

15UF

20%

6.3V
X5R
0402-1

ROOM=SOC

PP1401

P2MM-NSM

ROOM=SOC

PP1402

P2MM-NSM

ROOM=SOC

XW1401

SHORT-20L-0.05MM-SM

ROOM=SOC

1

C1466

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

ROOM=SOC

SM

PP

SM

PP

21

C1409

4.3UF

20%

4V
CERM
0402

1

432

1

1

1

1

1

1

2

ROOM=SOC

C1452

4.3UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1410

1UF

20%

4V
CERM
0402

1

432

SM

PP

SM

PP

SM

PP

PP_GPU_VAR

PP_CPU_VAR

BUCK1_PP_GPU_FB

C1448

2.2UF

20%

6.3V
X5R-CERM
0201-1

ROOM=SOC

ROOM=SOC

C1454

4.3UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1415

1UF

20%

4V
CERM
0402

1

432

PP1403

P2MM-NSM

ROOM=SOC

PP1410

P2MM-NSM

ROOM=SOC

PP1411

P2MM-NSM

ROOM=SOC

ROOM=SOC

C1416

7.5UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1420

1UF

20%

4V
CERM
0402

1

432

1

1

18 14

18 14

18

ROOM=SOC

C1421

7.5UF

20%

4V
CERM
0402

1

432

ROOM=SOC ROOM=SOC

ROOM=SOC

C1426

1

C1425

0.47UF

20%

6.3V
CERM
0402

1

432

AP_VDD_CPU_SENSE

SM

PP1408

PP

P2MM-NSM

ROOM=SOC

AP_VDD_GPU_SENSE

SM

PP1409

PP

P2MM-NSM

ROOM=SOC

7.5UF

20%

4V
CERM
0402

432

C1429

0.47UF

20%

6.3V
CERM
0402

1

20

20

432

ROOM=SOC

C1432

7.5UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1456

0.47UF

6.3V
CERM
0402

1

1.03V @12.9A MAX

0.92V @10.7A MAX

0.80V @TBD A MAX

0.67V @TBD A MAX

PP_GPU_VAR

ROOM=SOC

C1457

0.47UF

1

20%

6.3V
CERM
0402

432

20%

432

PP_SOC_VAR

18

0.80V @4.1A MAX

1

C1436

10UF

20%

2

6.3V
CERM-X5R
0402-9

ROOM=SOC

1

C1444

10UF

20%

2

6.3V
CERM-X5R
0402-9

ROOM=SOC

1

C1403

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=SOC

ROOM=SOC

OMIT

XW1403

SHORT-20L-0

NO_XNET_CONNECTION

ROOM=SOC

C1465

4.3UF

20%

1

4V
CERM
0402

432

BK45
BK49
BK53
BM55
BP15
BP19
BP23
BP28
BP32
BP36
BP40
BP45
BP49
BP53
BP58
BT13
BT17
BT21
BT25
BT30
BT34
BT38
BT43
BT47
BT51
BT55
BW10
CA13
CA17
CA21
CA25
CA30
CA34
CA38
CA43
CA47
CE13
CE17
CE45
J13
J21
J34
P55
T10
T60
V30
Y10
Y36
Y60
BF40
J60

AW25

18 14

AD28
AD32
AF60

AJ28
AJ32
AJ36

AL6
AN28
AN32
AN36
AN40
AN45
AN49
AN53
AN58
AR25
AR30
AR34
AR38
AR43
AR47
AR51
AR55

AW30
AW34
AW38
AW43
AW47
AW51
AW55
AW60

BD25
BD30
BD34
BD38
BD43
BD47
BD51
BD55

BD6
BD60
BF28
BF32
BF36
BF45
BF49
BF53
BF58
BK28
BK32
BK36
BK40

CAYMAN-2GB-20NM-DDR-M

VDD_SOC

U0700

CSP

SYM 9 OF 16

VDD_SOC

0.67V @TBDA MAX

.05MM-SM

21

ROOM=SOC

BUCK2_PP_SOC_FB

C1438

1UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1440

7.5UF

20%

4V
CERM
0402

1

432

18

ROOM=SOC

C1442

0.47UF

20%

6.3V
CERM
0402

1

432

D

C

B

A

432

432

SYNC_MASTER=Sync

PAGE TITLE

SOC:POWER (1/3)

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00482

8.0.0

14 OF 53
14 OF 81

D

SYNC_DATE=06/06/2016

A

SOC - POWER SUPPLIES

345678

2 1

DDR IMPEDANCE CONTROL

D

C

B

18 10 9 8 7

TBD-TBDV @1.9A MAX

PP0V9_SOC_FIXED

ROOM=SOC

C1502

4.3UF

20%

4V
CERM
0402

1

432

C1501

1

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=SOC

ROOM=SOC

C1527

1UF

20%

4V
CERM
0402

1

432

ROOM=SOC

C1503

7.5UF

20%

4V
CERM
0402

1

0.797-0.945V @9 mA MAX

0.765-0.840V @60mA MAX

19

PP0V8_AOP

1

C1504

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

1.06-1.17V @0.85A MAX

18 15 7

AB30
AB34
AB38
AD58

AF25

432

AF30
AF34
AF38
AF62
AJ58
AL25
AL30
AL34
AL38
AL43
AL51
AL55

AL60
AR60
AU28
AU32
AU36
AU40
AU45
AU49
AU53
AU58

AU6
BA28
BA32
BA36
BA40
BA45
BA49
BA53
BA58
BH25
BH30
BH34
BH38
BH43
BH47
BH51
BH55
BK58

AW23

CC36
CE30
CE40

VDD_FIXED

VDD_FIXED_CPU

VDD_LOW

PP1V1

1

C1506

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=SOC

1

2

U0700

CAYMAN-2GB-20NM-DDR-M

CSP

SYM 10 OF 16

VDD_FIXED

C1528

10UF

20%

6.3V
CERM-X5R
0402-9

ROOM=SOC

BK6
BM13
BM17
BM21
BM25
BM30
BM34
BM38
BM43
BM47
BM51
BP10
BP60
BW15
BW19
BW23
BW28
BW32
BW36
BW40
BW45
BW49
BW53
BW58
BW8
CC10
CC15
CC19
CC23
CC28
CC32
CC45
G32
G36
J17
J23
J55
J62
L10
L58
L60
T32
T58
T8
Y58
Y8

1

C1518

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

1

C1519

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

1

C1514

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

1

C1522

2.2UF

20%

6.3V
X5R-CERM

2

0201-1

ROOM=SOC

BE1

BJ1
BL1

BM8

BP6

BT8

BW6

CA8
CC6
CD1
CH1

BE67
BH60

BJ67

BK62

BL67

BM60

BP62

BT60

BW62

CD67
CH67

AB8
AC1
AE1
AH1

E1
K1

L6
P8
T6
V8
Y6

AB60
AC67
AD62
AE67
AH67

E67
K67
P60
T62
V60
Y62

VDDIO11_DDR0

VDDIO11_DDR1

VDDIO11_DDR2

VDDIO11_DDR3

U0700

CAYMAN-2GB-20NM-DDR-M

CSP

SYM 11 OF 16

VDDIO11_RET_DDR0
VDDIO11_RET_DDR1
VDDIO11_RET_DDR2
VDDIO11_RET_DDR3

DDR0_RREF
DDR1_RREF
DDR2_RREF
DDR3_RREF

DDR0_ZQ
DDR3_ZQ

DDR0_RET*
DDR1_RET*
DDR2_RET*
DDR3_RET*

VDDIO11_PLL_DDR0
VDDIO11_PLL_DDR1
VDDIO11_PLL_DDR2
VDDIO11_PLL_DDR3

DDR0_SYS_ALIVE
DDR1_SYS_ALIVE
DDR2_SYS_ALIVE
DDR3_SYS_ALIVE

VDD2

18 15 7

CD3
BY64
K3
K65

BN2
AA66

CF3
CB65
K4
K64

CE8
BW60
J8
P58

CG3
CD65
H4
H64

CF4
CB64
H3
H65

AM3
AM65
BB3
BB65
BR1
BR67
BV1
BV67
BY1
BY67
C2
C66
CJ2
CJ66
CK2
CK66
D2
D66
N1
N67
R1
R67
W1
W67

PP1V1

1

R1501

240

1%
1/32W
MF
01005

2

ROOM=SOC

DDR0_RREF
DDR1_RREF
DDR2_RREF
DDR3_RREF

DDR0_ZQ
DDR3_ZQ

PMU_TO_AOP_SLEEP1_READY

1.06 - 1.17V @4mA MAX

PP1V1_DDR_PLL

C1508

1

0.22UF

20%

2

6.3V
X5R
01005-1

ROOM=SOC

(CURRENT INCLUDED IN VDD2)

C1509

1

0.22UF

20%

2

6.3V
X5R
01005-1

ROOM=SOC

PP1V1_SDRAM

SYSTEM_ALIVE

1.06 - 1.17V @1.74A MAX

C1512

1

10UF

20%

2

6.3V
CERM-X5R
0402-9

ROOM=SOC

C1513

1

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=SOC

21 20 17

1

R1502

240

1%
1/32W
MF
01005

2

ROOM=SOC

C1523

1

0.22UF

20%

6.3V

2

X5R
01005-1

ROOM=SOC

C1507

1

2.2UF

20%

2

6.3V
X5R-CERM
0201-1

ROOM=SOC

19 18 15

1

R1503

240

1%
1/32W
MF
01005

2

ROOM=SOC

20 13

1

2

1

R1504

240

1%
1/32W
MF
01005

2

ROOM=SOC

FL1501

100OHM-25%-0.12A

01005

C1510

0.22UF

20%

6.3V
X5R
01005-1

ROOM=SOC

C1529

1

2.2UF

20%

2

6.3V
X5R-CERM
0201-1

ROOM=SOC

ROOM=SOC

R1505

1

240

1%
1/32W
MF
01005

ROOM=SOC

2

21

PP1V1

PP1V1_SDRAM

C1511

1

2.2UF

20%

2

6.3V
X5R-CERM
0201-1

ROOM=SOC

R1506

1

240

1%
1/32W
MF
01005

ROOM=SOC

2

C1515

1

2.2UF

20%

2

6.3V
X5R-CERM
0201-1

ROOM=SOC

D

18 15 7

C

19 18 15

B

A

SYNC_MASTER=Sync

PAGE TITLE

SOC:POWER (2/3)

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00482

8.0.0

15 OF 53
15 OF 81

D

SYNC_DATE=06/06/2016

A

D

C

B

SOC - POWER SUPPLIES

A12
A16

A2
A20
A24
A27
A31
A35

A5
A52
A56
A59
A63
A66

A9

AA1
AA67
AB10
AB15
AB19
AB23
AB28
AB32
AB36
AB40
AB45
AB49
AB53
AB58

AB6
AB62

AC2

AC4
AC64
AC66
AD13
AD17
AD21
AD25
AD30
AD34
AD43
AD47
AD51
AD55
AD60

AD8

AF10
AF15
AF19
AF23
AF28
AF32
AF36
AF40
AF45
AF49
AF53
AF58

AF6
AG1
AG3

AG65
AG67

AJ21
AJ25
AJ30
AJ34
AJ38
AJ43

AL10

AJ51
AJ55

AJ8
AK1
AK2

AK66
AK67

U0700

CAYMAN-2GB-20NM-DDR-M

CSP

SYM 13 OF 16

VSS VSS

AL23
AL28
AL32
AL36
AL40
AL45
AL53
AL58
AL62
AN13
AN17
AN21
AN25
AN30
AN34
AN38
AN43
AN47
AN51
AN55
AN60
AN8
AP1
AP4
AP64
AP67
AR10
AR15
AR19
AR28
AR32
AR36
AR40
AR45
AR49
AR53
AR58
AR6
AR62
AT1
AT3
AT65
AU13
AU17
AU21
AU25
AU30
AU34
AU38
AU43
AU47
AU51
AU55
AU60
AU8
AV1
AV2
AV4
AV64
AV66
AW10
AW15
AW19
CH50
AW28
AW32
AW36

AW40

AW45
AW49
AW53
AW58
AW6
AW62
AY1
AY4
AY64
AY67

B1

B3
B35
B41
B46
B52
B65
B67

BA13
BA17
BA21
BA30
BA34
BA38
BA43
BA47
BA51
BA55
BA60

BA8
BC1
BC2

BC66
BC67
BD10
BD23
BD28
BD32
BD36
BD40
BD45
BD49
BD53
BD58
BD62

BF21
BF25
BF30
BF34
BF43
BF47
BF51
BF55

BF8
BG1
BG3

BG65
BG67

BH10
BH15
BH19
BH23
BH28
BH32
BH36
BH40
BH45
BH49
BH53
BH58

BH6

BH62
BK13
BK17

AL49
BK25
BK30
BK34
BK38
BK43
BK47
BK51
BK55
BK60

BK8

BL2
BL4

BL64

U0700

CSP

SYM 14 OF 16

VSS VSS

BL66
BM10
BM15
BM19
BM23
BM28
BM32
BM36
BM40
BM45
BM49
BM53
BM58
BM6
BM62
BN1
BN67
BP13
BP17
BP21
BP25
BP30
BP34
BP38
BP43
BP47
BP51
BP55
BP8
BR3
BR65
BT10
BT15
BT19
BT23
BT28
BT32
BT36
BT40
BT45
BT49
BT53
BT58
BT6
BT62
BU1
BU67
BV2
BV4
BV64
BV66
BW13
BW17
BW21
BW25
BW30
BW34
BW38
BW43
BW47
BW51
CE51
BY65
C11
C14
C18
C22
C26
C29
C33
C35
C4
C52
C54
C57
C61
C64
C7
CA10

CA15
CA19
CA23
CA28
CA32
CA36
CA40
CA45
CA49
CA53
CA58

CA6

CA62

CB1

CB3
CB66
CB67

CC13
CC17
CC21
CC30
CC34
CC38
CC43

CL22

T30
CC8
CD2
CD4

CD64
CD66

CE10
CE15
CE47
CE53

CE6

CE62

CF1

CF2
CF64
CF65
CF66
CF67

CG1

CG11

CG2
CG24
CG27

CG4
CG42
CG44
CG46
CG48

CG5
CG52
CG54
CG56
CG59
CG61
CG64
CG65
CG66
CG67
CH12
CH18

CH2
CH24
CH27

CH3
CH33
CH39

CH4
CH42
CH44
CH46
CH48

345678

2 1

1.70-1.95V @134mA MAX

CH5

U0700

CAYMAN-2GB-20NM-DDR-MCAYMAN-2GB-20NM-DDR-M

SYM 15 OF 16

VSSVSS

CH52
CH54
CH56
CH59
CH61
CH63
CH64
CH65
CH66
CH7
CH9
CJ1
CJ3
CJ4
CJ41
CJ42
CJ46
CJ5
CJ50
CJ54
CJ57
CJ61
CJ64
CJ65
CJ67
CK4
CK41
CK42
CK46
CK5
CK50
CK54
CK57
CK61
CK64
CL1
CL12
CL18
CL24
CL27
CL3
CL33
CL39
CL4
CL41
CL44
CL48
CL52
CL56
CL59
CL63
CL65
CL67
CL7
CM18
CM2
CM24
CM27
CM39
CM4
CM41
CM44
CM48
CM5
CM52
CM56
CM59
CM63
CM66
D1
D11
D12
D14
D16
D18

D20
D22
D24
D26
D27
D29

D3
D31
D35

D4
D41
D46

D5
D52
D56
D59
D63
D65
D67

D7

D9

E12
E14
E18

E2

E20
E22
E26
E27
E29

E3

E37

E4

E5

E54
E57
E59
E61
E64
E65
E66

E7

E9

F1
F2
F3

F4
F64
F65
F66
F67

G38
G43
G47
G51

G8
H1

H2
H66
H67

J10
J15
J19
J28
J32
J40
J45
J49
J53

J6

K2

K66

L13
L17
L21
L25
L30
L34

U0700

CAYMAN-2GB-20NM-DDR-M

CSPCSP

SYM 16 OF 16

L38
L43
L47
L51
L55
L62
L8
M1
M2
M3
M4
M64
M65
M66
M67
P10
P15
P19
P23
P28
P32
P36
P40
P45
P49
P53
P6
P62
R2
R4
R64
R66
T13
T25
T34

VSSVSS

T38
T51
T55
U1
U67
V10
V15
V28
V32
V36
V40
V53
V58
V6
V62
W3
W65
Y13
Y17
Y21
Y25
Y30
Y43
Y47
Y51
Y55
BF38
J58

46 41 40 37 36 32 21 20 18 16

29 25 18 17 13 12 11 9 8 7 5

46 41 40 37 36 32 21 20 18 16

19 10 8

PP1V2_SOC

53 52 48 47

52 48 47 46 39 30

53 52 48 47

19

C1604

2.2UF

X5R-CERM

ROOM=SOC

PP1V8_SDRAM

1.62-1.98V @43mA MAX

PP1V8

PP1V8_SDRAM

1

C1603

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

PP1V2_REF

R1602

0.00

1/32W
01005

ROOM=SOC

R1601

0.00

1/32W
01005

ROOM=SOC

20%

6.3V

0201-1

1

2

0%
MF

0%
MF

1

C1601

0.1UF

20%

6.3V
X5R-CERM

2

01005

ROOM=SOCROOM=SOC

1

C1615

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

1

C1602

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=SOC

1

2

1

2

C1611

1

2.2UF

20%

2

6.3V
X5R-CERM
0201-1

ROOM=SOC

VDD12_PLL_CPU:1.14-1.26V @13mA MAX

21

PP1V2_PLL_CPU

C1606

1

0.1UF

20%

2

6.3V
X5R-CERM
01005

ROOM=SOC

VDD12_PLL_SOC:1.14-1.26V @31mA MAX

PP1V2_PLL_SOC

21

C1605

2.2UF

20%

6.3V
X5R-CERM
0201-1

ROOM=SOC

C1607

2.2UF

20%

6.3V
X5R-CERM
0201-1

ROOM=SOC

1

C1608

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

1

C1610

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

1.62-1.98V @10mA MAX

1.62-1.98V @2mA MAX

1.62-1.98V @1mA MAX

1.62-1.98V @1mA MAX

TBD-TBDV @30mA MAX

1

C1609

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

1

C1612

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

1

C1614

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=SOC

C1613

1

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

AM1

AM67

BB1

BB67

C3

C65

CK3

CK65

AJ62
AN62
AU62
BA62

BF62

G40
G45
G49
G53

AD6

AJ6
AN6
BA6

BF6

CE19
CE23

CE28
CE32
CE34
CE36
CE43
CE38

AR23
BK19

AF21

J36

CE21

BF60

CG9

CC40

AU23

T28

Y38

BA25

Y32

AD36
AD38

Y34

CAYMAN-2GB-20NM-DDR-M

VDD1

VDDIO18_GRP1

VDDIO18_GRP2

VDDIO18_GRP3

VDDIO18_GRP4

VDDIO18_GRP10

VDD18_TSADC0
VDD18_TSADC1
VDD18_TSADC2
VDD18_TSADC3
VDD18_TSADC4
VDD18_TSADC5

VDD18_FMON

VDD18_LPOSC

VDD12_CPU_UVD
VDD12_GPU_UVD
VDD12_SOC_UVD

VDD12_PLL_CPU

VDD12_PLL_SOC

U0700

CSP

SYM 12 OF 16

VDD18_EFUSE1
VDD18_EFUSE2

D

CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND

CG7
G34

C

B

A

SYNC_MASTER=Sync

PAGE TITLE

SOC:POWER (3/3)

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00482

8.0.0

16 OF 53
16 OF 81

D

SYNC_DATE=06/06/2016

A

345678

2 1

D

25 18 17 16 13 12 11 9 8 7 5

52 48 47 46 39 30 29

315mA MAX

PP1V8

1

C1701

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

1

C1739

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

R1703

24.9

1%

1/32W

MF

01005

ROOM=NAND

PP1V8_NAND_AVDD

21

17

1

C1741

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=NAND

NAND_AGND

1

C1707

15UF

20%

6.3V
X5R

2

0402-1

ROOM=NAND

1

C1743

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

1

C1726

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=NAND

1

C1729

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

1

C1745

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

1

C1710

0.1UF

20%

6.3V
X5R-CERM

2

01005

ROOM=NAND

1

C1730

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

1

C1747

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

PROBE POINTS

17 8

90_PCIE_AP_TO_NAND_REFCLK_P

90_PCIE_AP_TO_NAND_REFCLK_N

17 8

D

SM

1

1

PP1701

PP

P2MM-NSM

ROOM=NAND

SM

PP1702

PP

P2MM-NSM

ROOM=NAND

C

PP0V9_NAND

19

1007mA MAX

C1737

1

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=NAND

1

C1708

220PF

5%
10V

2

C0G-CERM
01005

ROOM=NAND

1

C1704

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

C1738

1

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

1

C1711

22PF

5%
16V

2

CERM
01005

ROOM=NAND

1

C1702

15UF

20%

6.3V
X5R

2

0402-1

ROOM=NAND

C1740

1

1.0UF

20%

2

6.3V
X5R
0201-1

ROOM=NAND

1

C1717

68PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

1

C1705

15UF

20%

6.3V
X5R

2

0402-1

ROOM=NAND

C1742

1

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=NAND

1

C1723

39PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

C1722

1

15UF

20%

6.3V

2

0402-1

ROOM=NAND

C1744

1

1.0UF

20%

2

6.3V
X5R
0201-1 0201-1

ROOM=NAND

1

C1712

2

C1727

1

15UF

20%

6.3V

2

X5RX5R
0402-1

ROOM=NAND

C1746

1

2

100PF

5%
16V
NP0-C0G
01005

ROOM=NAND

1.0UF

20%

6.3V
X5R

ROOM=NAND

#24543147:10uF for 32GB
#26326159:10uF for C1719

OMIT

1

C1748

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

OMIT

1

C1713

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

OMIT

1

C1716

15UF

20%

6.3V

2

X5R
0402-1

1

C1719

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=NANDROOM=NAND

1230mA MAX (1us peak power)

PP3V0_NAND

OMIT

1

C1721

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

OMIT

1

C1733

15UF

20%

6.3V

2

X5R
0402-1

ROOM=NAND

C

B

C1703

1

220PF

5%
10V

2

C0G-CERM
01005

ROOM=NAND

C1706

1

22PF

5%
16V

2

CERM
01005

ROOM=NAND

25 18 17 16 13 12 11 9 8 7 5

52 48 47 46 39 30 29

1

R1704

3.01K

1%
1/32W
MF
01005

ROOM=NAND

2

C1709

1

100PF

5%

2

16V
NP0-C0G
01005

ROOM=NAND

PP1V8

C1714

1

220PF

5%
10V

2

C0G-CERM
01005

ROOM=NAND

1

C1724

0.01UF

10%

6.3V

2

X5R
01005

ROOM=NAND

1

C1725

0.01UF

10%

2

6.3V
X5R
01005

ROOM=NAND

C1720

1

100PF

5%

2

16V
NP0-C0G
01005

ROOM=NAND

11

AP_TO_NAND_SYS_CLK

17 8

90_PCIE_AP_TO_NAND_REFCLK_P

17 8

90_PCIE_AP_TO_NAND_REFCLK_N

8

PCIE_NAND_BI_AP_CLKREQ_L

C1728

1

68PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

PCIE_NAND_RESREF

8

90_PCIE_AP_TO_NAND_TXD_P

8

90_PCIE_AP_TO_NAND_TXD_N

8

90_PCIE_NAND_TO_AP_RXD_P
90_PCIE_NAND_TO_AP_RXD_N

8

NAND_VREF

NC
NC

NC
NC

M4

PCI_AVDD_CLK1

D2

CLK_IN

H8

PCIE_REFCLK_P

H6

PCIE_REFCLK_M

G9

PCIE_CLKREQ*

M6

PCI_RESREF

M8

PCIE_RX0_P

K8

PCIE_RX0_M

N5

PCIE_RX1_P

N3

PCIE_RX1_M

P8

PCIE_TX0_P

N7

PCIE_TX0_M

M2

PCIE_TX1_P

K2

PCIE_TX1_M

K6

K4

J7

J5

PCI_VDD2

PCI_VDD1

PCI_AVDD_H

PCI_AVDD_CLK2

C3

E5

AVDD1

A3

VREF

OB0

A5

R7

R3

J9

J1

F2

A7

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDDIO

U1701

THGBX6T1T82LFXF

VLGA

VER-1

ROOM=NAND

BOMOPTION=OMIT_TABLE

CRITICAL

OB10

VDDIO

VDDIO

OF10

OF0

VDDIO

VDDIO

R5

VDDIO

OA0

VCC

OD0

OA10

VCC

OD10

VCC

VCC

OG10

OG0

VCC

VCC

EXT_D0
EXT_D1
EXT_D2
EXT_D3
EXT_D4
EXT_D5
EXT_D6

EXT_D7
EXT_NCE
EXT_NRE

EXT_NWE

EXT_RNB

EXT_CLE
EXT_ALE

G3
J3
H2
E3
E7
F6
C7
B8

G1
F4
C5
G5
H4
D4

1

C1749

1.0UF 1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=NAND

1

C1715

220PF

5%
10V

2

C0G-CERM
01005

ROOM=NAND

1

C1750

20%

6.3V

2

X5R
0201-1

ROOM=NAND

1

C1718

22PF

5%
16V

2

CERM
01005

ROOM=NAND

PMU_TO_NAND_LOW_BATT_BOOT_L
AP_TO_NAND_FW_STRAP

NC
NC
NC
NC
NC

SYSTEM_ALIVE
PCIE_AP_TO_NAND_RESET_L
SWD_AP_BI_NAND_SWDIO_R
SWD_AP_NAND_SWCLK_R

NC
NC

1

C1751

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=NAND

1

C1731

68PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

ROOM=NAND

ROOM=NAND

1/32W 0%

1

C1752

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=NAND

1

C1732

39PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

20

12

8

0.00

0%

0.00

1

C1753

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=NAND

1

C1734

100PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

1

C1754

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=NAND

1

C1735

220PF

5%
10V

2

C0G-CERM
01005

ROOM=NAND

1

C1736

100PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

B

21 20 15

R1702

21

01005 MF1/32W

R1707

21

01005 MF

SWD_AP_BI_NAND_SWDIO
SWD_AP_TO_MANY_SWCLK

13

53 36 13

A

F8
D8
D6

RESET*
TRST*
ZQ

SYNC_MASTER=Sync

PAGE TITLE

7

AP_TO_NAND_RESET_L

NC

NAND_ZQ

NAND

1

R1701

34.8

0.5%
1/32W
MF
01005

2

ROOM=NAND

NAND_AGND

17

VSSA

B2

VSS

B4

VSS

B6

VSS

VSS

G7

OE10

VSS

L3

VSS

L5

VSS

L7

P2

VSS

P4

VSS

P6

VSS

OC0

8 7 5 4 2 1

VSS

OC10

VSS

OE0

VSS

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

BRANCH

PAGE

SHEET

36

051-00482

8.0.0

17 OF 53
17 OF 81

D

SYNC_DATE=06/06/2016

A

345678

2 1

D

C

B

A

BUCK5

3.2A MAX

BUCK6

1.5A MAX

BUCK7

1.5A MAX

BUCK8

1.5A MAX

BUCK9

0.75A MAX

15 10 9 8 7

30 25

28 27 26 25 23 21 19 10 9 4

46 41 40 39 37 35 34 33 31 30

1

C1867

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

PP1V25_BUCK

19

PP_CPU_SRAM_VAR

14

0.80V - 1.06V

PP_GPU_SRAM_VAR

14

0.80V - 0.92V

PP2V8_UT_AF_VAR

53

1

C1840

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1811

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

1

C1868

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

1

C1869

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

1

C1870

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

PP_VDD_MAIN

1

C1875

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1876

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1801

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1846

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=PMU

1

C1847

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1848

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1803

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1804

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1805

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1806

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1862

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1850

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=PMU

1

C1851

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1852

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1877

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1807

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1808

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1809

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1810

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1863

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

VDD_MAIN_SNS

19

1

C1853

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=PMU

1

C1854

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1855

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1849

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

D10/D101:#24681501,TY ONLY, D11/D11: Both Vendor

CRITICAL

1

C1857

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=PMU

1

C1858

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1859

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1856

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

L1803

1.0UH-3.6A-0.06OHM

CRITICAL

2 1

MEKK2016T-SM

NO_XNET_CONNECTION=1

ROOM=PMU

OMIT

XW1802

SHORT-20L-0.05MM-SM

2 1

L1804

BUCK5_LX0PP0V9_SOC_FIXED

BUCK5_FB

NO_XNET_CONNECTION=1ROOM=SOC

1UH-20%-2.1A-0.12OHM

CRITICAL

2 1

PIQA20121T-SM

ROOM=PMU

OMIT

XW1807

SHORT-20L-0.05MM-SM

2 1

ROOM=SOC

L1805

BUCK6_LX0

BUCK6_FB

NO_XNET_CONNECTION=1

1.0UH-20%-2.25A-0.086OHM

2 1

SHORT-20L-0.05MM-SM

CRITICAL

MCFE2016T-SM

ROOM=PMU

OMIT

XW1803

2 1

ROOM=SOC NO_XNET_CONNECTION=1

L1801

BUCK7_LX0

BUCK7_FB

1UH-20%-2.1A-0.12OHM

CRITICAL

2 1

PIQA20121T-SM

ROOM=PMU

OMIT

XW1801

SHORT-20L-0.05MM-SM

2 1

ROOM=SOC

NO_XNET_CONNECTION=1

L1802

BUCK8_LX0

BUCK8_FB

1.0UH-20%-1.5A-0.161OHM

21

0603

OMIT

XW1806

SHORT-20L-0.05MM-SM

2 1

ROOM=SOC NO_XNET_CONNECTION=1

BUCK9_LX0

BUCK9_FB

M8

VDD_MAIN_SNS

N7

VDD_MAIN

H6

VDD_MAIN_E

F11

VDD_MAIN_N

R13

VDD_MAIN_SW

H14

VDD_MAIN_W

H13

VDD_MAIN_W

A5
B5
C5
D5

A9
B9
C9
D9

A17
B17
C17
D17

A13
B13
C13
D13

H1
H2
H3

T2
T3

M1
M2
M3

B1
C1
D1

K18
K19

U6
V6

F18
F19

L18
L19

B2
C2
D2
A2

F5

BUCK5_FB

J18
J19

H16

BUCK6_FB

U7
V7

R8

BUCK7_FB

G18
G19

H15

BUCK8_FB

M18
M19

P16

BUCK9_FB

VDD_BUCK0_01

VDD_BUCK0_23

VDD_BUCK1_01

VDD_BUCK1_23

VDD_BUCK2

VDD_BUCK3

VDD_BUCK4

VDD_BUCK5

VDD_BUCK6

VDD_BUCK7

VDD_BUCK8

VDD_BUCK9

BUCK5_LX0

BUCK6_LX0

BUCK7_LX0

BUCK8_LX0

BUCK9_LX0

U1801

D2333A1

WLCSP

SYM 2 OF 4

ROOM=PMU

BAT/USBBUCK INPUT

BUCK0_LX0

BUCK0_LX1

BUCK0_LX2

BUCK0_LX3

BUCK0_FB

BUCK1_LX0

BUCK1_LX1

BUCK1_LX2

BUCK1_LX3

BUCK1_FB

BUCK2_LX0

BUCK2_LX1

BUCK2_FB

BUCK3_LX0

BUCK3_FB

VBUCK3_SW

BUCK4_LX0

BUCK4_LX1

BUCK4_FB

VBUCK4_SW

BUCK3_SW1

BUCK3_SW2
BUCK3_SW3

SWITCH OUTPUTS

BUCK4_SW1

BUCK0_LX0

B4
C4
D4
A4

A6
B6
C6
D6

A8
B8
C8
D8

A10
B10
C10
D10

F10

BUCK0_PP_CPU_FB

B18
C18
D18
A18

A16
B16
C16
D16

A14
B14
C14
D14

A12
B12
C12
D12

F12

BUCK1_PP_GPU_FB

G1
G2
G3

J1
J2
J3

J5

BUCK2_PP_SOC_FB

R2
R3
R1
R7

U2
V2

N1
N2
N3

L1
L2
L3

K5

U5
V5

T1
U1

U3
V3

U4
V4

NO_XNET_CONNECTION=1

BUCK0_LX1

NO_XNET_CONNECTION=1

BUCK0_LX2

NO_XNET_CONNECTION=1

BUCK0_LX3

NO_XNET_CONNECTION=1

BUCK1_LX0

NO_XNET_CONNECTION=1

BUCK1_LX1

NO_XNET_CONNECTION=1

BUCK1_LX2

BUCK1_LX3

NO_XNET_CONNECTION=1

BUCK2_LX0

BUCK2_LX1

NO_XNET_CONNECTION=1

BUCK3_LX0

NO_XNET_CONNECTION=1

BUCK3_FB

NO_XNET_CONNECTION=1

BUCK4_LX0

NO_XNET_CONNECTION=1

BUCK4_LX1

NO_XNET_CONNECTION=1

BUCK4_FB

NO_XNET_CONNECTION=1 ROOM=SOC

L1806

1.0UH-20%-3.6A-0.060OHM

21

PIQA20161T-SM

ROOM=PMU

CRITICAL

L1807

0.22UH-20%-6.7A-0.023OHM

21

PINA20121T-SM

ROOM=PMU

CRITICAL

L1808

0.22UH-20%-6.7A-0.023OHM

2 1

PINA20121T-SM

ROOM=PMU

CRITICAL

L1809

0.22UH-20%-6.7A-0.023OHM

21

PINA20121T-SM

ROOM=PMU

14

CRITICAL

L1810

1.0UH-20%-3.6A-0.060OHM

21

PIQA20161T-SM

ROOM=PMU

CRITICAL

L1811

0.22UH-20%-6.7A-0.023OHM

21

PINA20121T-SM

ROOM=PMU

CRITICAL

L1812

0.22UH-20%-6.7A-0.023OHM

2 1

PINA20121T-SM

ROOM=PMUNO_XNET_CONNECTION=1

CRITICAL

L1813

0.22UH-20%-6.7A-0.023OHM

21

PINA20121T-SM

ROOM=PMU

14

CRITICAL

L1814

1.0UH-20%-3.6A-0.060OHM

21

PIQA20161T-SM

ROOM=PMU

CRITICAL

L1815

0.47UH-20%-3.8A-0.048OHM

2 1

PIQA20121T-SM

ROOM=PMU

14

L1816

CRITICAL

ROOM=PMU

1.0UH-20%-3.6A-0.060OHM

21

PIQA20161T-SM

OMIT

XW1804

SHORT-20L-0.05MM-SM

ROOM=SOC

CRITICAL

21

L1817

1.0UH-20%-3.6A-0.060OHM

21

PIQA20161T-SM

ROOM=PMU

CRITICAL

L1818

0.47UH-20%-3.8A-0.048OHM

2 1

PIQA20121T-SM

OMIT

ROOM=PMU

XW1805

SHORT-20L-0.05MM-SM

21

PP1V8

PP1V8_TOUCH
PP1V8_MAGGIE_IMU

PP1V1

CRITICAL

Voltages per Cayman Power Spec, Sec. 2.2, rev 0.9.2, #24557869

PP_CPU_VAR

1

C1818

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1819

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1825

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1826

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1831

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1832

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1837

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1838

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1842

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1843

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1844

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1845

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

2

0.625V - 1.06V

C1872

220PF

5%
10V
C0G-CERM
01005

ROOM=PMU

PP_GPU_VAR

1

C1813

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1814

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1820

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1821

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1827

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1828

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1833

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1834

15UF

20% 20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1839

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1866

15UF

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1865

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1873

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

0.67V - 0.92V

1.03V for overdrive only

PP_SOC_VAR

0.67V/0.80V

1

C1822

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1829

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1835

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1841

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1864

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1871

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

PP1V8_SDRAM

1

C1816

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1823

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1860

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

PP1V1_SDRAM

1

C1830

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

52 48 47 46 39

30 29 25 17 16 13 12 11 9 8 7 5

1

C1836

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1802

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1874

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

SYNC_MASTER=Sync

PAGE TITLE

1

C1861

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

14

14

14

13.4A MAX 4.7A MAX

BUCK0 BUCK2

D

13.4A MAX

BUCK1

C

(pending vendor qual)

53 52 48 47 46

19 15

41 40 37 36 32 21 20 16

1.7A MAX

4.7A MAX

B

BUCK4BUCK3

A

SYNC_DATE=06/06/2016

SYSTEM POWER:PMU (1/3)

DRAWING NUMBER SIZE

47 46 39 38

36 24

NOTICE OF PROPRIETARY PROPERTY:

15 7

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Apple Inc.

R

051-00482

REVISION

8.0.0

BRANCH

PAGE

18 OF 53

SHEET

18 OF 81

D

8 7 5 4 2 1

36

345678

2 1

D

27 26 25 23 21 19 18 10 9 4

41 40 39 37 35 34 33 31 30 28

18

VDD_MAIN_SNS

20

PMU_PRE_UVLO_DET

53 46

PP_VDD_MAIN

OMIT

XW1901

SHORT-20L-0

2 1

ROOM=PMU

NO_XNET_CONNECTION

OMIT

XW1902

SHORT-20L-0.05MM-SM

2 1

ROOM=PMU

1

.05MM-SM

27 26 25 23 21 19 18 10 9 4

41 40 39 37 35 34 33 31 30 28

2

53 46

C1901

15UF

20%

6.3V
X5R
0402-1

ROOM=PMU

1

C1910

10UF

20%

6.3V

2

0402-9

ROOM=PMU

PP_VDD_MAIN

1

C1914

10UF

20%

6.3V
CERM-X5R

2

0402-9

ROOM=PMU

1

C1911

10UF

20%

6.3V

2

CERM-X5RCERM-X5R
0402-9

1

C1907

10UF

20%

6.3V
CERM-X5R

2

0402-9

ROOM=PMUROOM=PMU

LDO#

LDO1 (Ca)

LDO2 (Ca)
LDO3 (Ca)

LDO4 (D)
LDO5 (F)

LDO6 (Cb)

LDO8 (Cb)
LDO9 (Cb)

ADJ.RANGE, LOW

1.2-2.475V

1.2-2.475V

1.2-2.475V

0.7-1.2V

2.5-3.6V(tbc)

1.2-2.475V

1.2-2.475V

1.2-2.475V

ADJ.RANGE, HI

2.4-3.675V

2.4-3.675V

2.4-3.675V

2.4-3.675V

2.4-3.675V

2.4-3.675V

ACCURACY

+/-1.4%

+/-2.5%
+/-2.5%

MAX.CURRENT

50mA

50mA
50mA

+/-2.5% 60mA
+/-75mV

+/-2.5%

1000mA

250mA

(500/100mA in bypass)

250mA+/-30mV2.4-3.675V1.2-2.475VLDO7 (Cb)

+/-30mV
+/-25mV

250mA
250mA

ADELYN LDO SPECS

LDO#

LDO11 (Cb)
LDO12 (E)

LDO13 (Cb)
LDO14 (Gb)

LDO15 (Ca)

LDO16 (Cb)
LDO17 (Ca)

LDO18 (Gb)
LDO19 (Gb)

ADJ.RANGE, LOW

1.2-2.475V

1.8V

1.2-2.475V

0.7-1.4V

1.2-2.475V

1.2-2.475V

1.2-2.475V

0.7-1.4V

0.7-1.4V

ADJ.RANGE, HI

2.4-3.675V

2.4-3.675V

2.4-3.675V

2.4-3.675V

2.4-3.675V

ACCURACY

+/-30mV
+/-5%

+/-30mV
+/-3.0%

+/-2.5%

+/-30mV
+/-2.5%

+/-3.0%
+/-3.0%

MAX.CURRENT

250mA
10mA

250mA
400mA

50mA

250mA
50mA

400mA
400mA

D

C

B

A

U1801

D2333A1

WLCSP

SYM 4 OF 4

A1
A11
A15

H8
A19
P13

A3
P14

A7
B11
B15
B19

B3

B7
C11
C15
C19

C3

C7
D11
D15
D19

D3

D7

VSS VSS

E1

E10
E11
E12
E13
E14
E15
E16
E17
E18
E19

E2

E3

E4

E5

E6

E7

E8

E9

F1

F17

F2

F3

F4

18 15

PP1V1_SDRAM

53 38 37 32 30 25 23

G17
G4
H17
H18
H19
H4
J17
J4
J8
K1
K17
K2
K3
K4
K8
L17
L4
L8
M17
M4
N17
N18
N19
N4
P1
P2
P3
P4
P15
R17
R4
T5
T15
T4
T6
T7
T8
U15
T13
U8
V1
V12
V19
V8

U15 = PMU XTAL GND

PP_VDD_BOOST

1

C1915

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1908

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

18

PP1V25_BUCK

27 26 25 23 21 19 18 10 9 4

41 40 39 37 35 34 33 31 30 28

PMU_VSS_RTC

1

C1912

15UF

20%

6.3V

2

X5R
0402-1

ROOM=PMU

1

C1913

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

20

53 46

PP_VDD_MAIN

NC

R12

VDD_LDO1

V11

VDD_LDO2_15

R10

VDD_LDO3_17

R16

VDD_LDO4

V9

VDD_LDO5

V10

R14

VDD_LDO6_BYP

P19

VDD_LDO7_8

R19

VDD_LDO9

R9

VDD_LDO10

V13

VDD_LDO11_13

V16

VDD_LDO14

T19

VDD_LDO16

V17

VDD_LDO18

V18

VDD_LDO19

U19

VDD_LDO19

VPP_OTP

G15

TP_DET

VPUMP: 10nF min. @4.6V

1

C1905

33PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=PMU

U1801

D2333A1

WLCSP

SYM 1 OF 4

LDO INPUT

LDO

1

2

1

C1909

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

PMU_VPUMP

C1902

47NF

20%

6.3V
X5R-CERM
01005

ROOM=PMU

VLDO1
VLDO2
VLDO3

VLDO4
VLDO5_0
VLDO5_1

VLDO6

VBYPASS

VLDO7

VLDO8

VLDO9

VLDO9_FB

VLDO10
VLDO11
VLDO12
VLDO13
VLDO14
VLDO15
VLDO16
VLDO17
VLDO18
VLDO19

VBUF_1V2

VPUMP

T12
U11
T10
T16
U9
U10
T14

R15
T17

P18
R18

P17
T9

U13
P7
U14
U16
U12
T18
T11
U17
U18

P8J6

R5

NC

NC

1

C1916

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

LDO10 (Ga)

1

C1918

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1921

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

0.7-1.2V 1150mA

1

C1933

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=PMU

1

C1922

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1923

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1925

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=PMU

1

C1926

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

+/-4.5%

1

C1927

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

1

C1935

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=PMU

1

C1930

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

LDO_RTC
BUF_1V2

1

2

1

C1904

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

C1932

0.22UF

20%

6.3V
X5R
01005-1

ROOM=PMU

2.5V

1.2V

PP3V3_USB
PP1V8_VA
PP3V0_ALS_APS_CONVOY
PP0V8_AOP
PP3V0_NAND

+/-2.0%
+/-5.0%

30 7

35 34 33 32

30 29 25

15

17

PP_ACC_VAR

PP3V0_TRISTAR_ANT_PROX
PP2V9_NH_AVDD
PP1V8_HAWKING

PP0V9_NAND

29

44

17

PP1V8_ALWAYS
PP3V0_MESA

38

PP1V2_SOC
PP1V8_MESA

#24989262

PP_LDO17
PP1V2_UT_DVDD

1/20W

1%

R1901

0.00

2 1

MF

NOSTUFF

0201

25

PP1V2_NH_NV_DVDD

PP1V2_REF

#24989262:OTP-AO LDO17 default off,50mA Iout_max

SYNC_MASTER=Sync

PAGE TITLE

16

53 41 40 29

21 20

16 10 8

48 38

30 29

1

C1919

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PMU

SYSTEM POWER:PMU (2/3)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

10mA
10mA

LDO1
LDO2
LDO3
LDO4
LDO5

40 27

LDO6

LDO7
LDO8
LDO9

LDO10
LDO11
LDO12
LDO13
LDO14
LDO15
LDO16
LDO17
LDO18
LDO19

VBUF_1V2

DRAWING NUMBER SIZE

051-00482

REVISION

D

8.0.0

BRANCH

PAGE

19 OF 53

SHEET

19 OF 81

C

New for ADELYN

B

A

SYNC_DATE=06/06/2016

8 7 5 4 2 1

36

46 41 40 37 36 32 21 20 18 16

53 52 48 47

PP1V8_SDRAM

PP1V8_ALWAYS

345678

2 1

BUTTON PULL-UP RESISTORS

1

SM

PP

1

PP

1

PP

21 20 19

PP2001

P2MM-NSM

ROOM=SOC

PP2002

SM

P2MM-NSM

ROOM=SOC

SM

PP2003

P2MM-NSM

ROOM=PMU

PP1V8_SDRAM

NOSTUFF

1

R2008

100K

5%
1/32W
MF
01005

2

ROOM=PMU

53 52 48 47

46 41 40 37 36 32 21 20 18 16

D

1

R2006

100K

5%
1/32W
MF
01005

2

ROOM=PMU

1

R2005

100K

5%
1/32W
MF
01005

2

ROOM=PMU

D101/D111 ONLY: TCXO_RF Supplies 32K

1

R2012

10K

5%
1/32W
MF
01005

2

ROOM=PMU
NO_XNET_CONNECTION

1

C2001

1000PF

10%
10V

2

X5R
01005

ROOM=PMU

40

13 7

13

15 13

13

40 37 13 7

13

21 17 15

53 39 23 13

13

7

AP_TO_PMU_WDOG_RESET
TRISTAR_TO_PMU_HOST_RESET

AP_TO_PMU_SOCHOT_L

11

PMU_TO_SYSTEM_COLD_RESET_L

Active high with int 200k PD

AOP_TO_PMU_SLEEP1_REQUEST
PMU_TO_AOP_SLEEP1_READY
AOP_TO_PMU_ACTIVE_REQUEST
PMU_TO_AOP_TRISTAR_ACTIVE_READY

PMU_TO_AOP_CLK32K

SYSTEM_ALIVE
LCM_TO_MANY_BSYNC

PMU_TO_AOP_IRQ_L

HIGH=FORCE PWM MODE

NC

NC

NC

P9
P10
P11

M5

P12

R11

L11
L12

J12

M9

M10

H5
L13
L10

G5

RESET_IN1
RESET_IN2
RESET_IN3
RESET*
SHDN

SLEEP1_REQ
SLEEP1_RDY
ACTIVE_REQ
ACTIVE_RDY

SLEEP_32K
OUT_32K

SYS_ALIVE
FORCE_SYNC
CRASH*
IRQ*

U1801

D2333A1

WLCSP

SYM 3 OF 4

REFS

RESETS

COMPARATORADC

IREF

VREF

PRE_UVLO*

VDROOP0*
VDROOP1*

VDROOP0_DET
VDROOP1_DET

K6

PMU_IREF

J7

PMU_VREF

1

C2006

0.22UF

20%

6.3V

2

X5R
0201

ROOM=PMU

N10

PMU_TO_AP_PRE_UVLO_L

G6

PMU_TO_AP_THROTTLE_CPU_L

G7

PMU_TO_AP_THROTTLE_GPU_L

F6

AP_VDD_CPU_SENSE

F7

AP_VDD_GPU_SENSE

1

R2011

200K

1%
1/20W
MF
201

ROOM=PMU

2

11

12

11

14

14

44 20

44 20

BUTTON_RINGER_A

BUTTON_POWER_KEY_L

BUTTON_VOL_DOWN_L

NOTE:VDROOP_DET filtering is now inside Adelyn

PP1V8_ALWAYS

NOSTUFF

1

R2007

220K

5%
1/32W
MF
01005

2

ROOM=PMU

PP1V8_SDRAM

NOSTUFF

1

R2015

220K

5%
1/32W
MF
01005

2

ROOM=PMU

21 20 19

D

53 52 48 47

46 41 40 37 36 32 21 20 18 16

44 20

C

B

C2007

100PF

NP0-C0G

ROOM=PMU

ROOM=PMU

ROOM=PMU

01005

C2008

100PF

NP0-C0G

01005

C2009

100PF

NP0-C0G

01005

5%

16V

5%

16V

5%

16V

FOREHEAD NTC

1

1

2

R2001

10KOHM-1%

01005

2

ROOM=PMU

REAR CAMERA NTC

1

1

R2002

10KOHM-1%

2

2

01005
ROOM=PMU

RADIO PA NTC

1

1

2

R2003

10KOHM-1%

01005
ROOM=PMU

2

FOREHEAD_NTC_RETURN

RCAM_NTC_RETURN

PA_NTC_RETURN

I2C1_AP_SDA

47

#24825674: Add R2020 to meet timing spec
#26169957: R2020 to 100ohm

OMIT

XW2002

SHORT-20L-0

ROOM=SOC

SHORT-20L-0

ROOM=SOC

SHORT-20L-0.05MM-SM

ROOM=SOC

SHORT-20L-0.05MM-SM

ROOM=SOC

.05MM-SM

21

OMIT

XW2003

.05MM-SM

21

OMIT

XW2004

21

OMIT

XW2005

21

R2020

100

5%

1/32W

MF

01005

1

C2013

1000PF

10%
10V

2

X5R
01005

ROOM=PMU
PLACE_NEAR=U1801:2mm

N13

M13

N6

N5

P5

J14
J15

J16
K16
K15
K14

J13
K13
K12

L14
L15
L16

M16
M15
M14

N16
N15
N14

R6

M6

P6

L5
L6

G16

V14
V15

N9

SCL
SDA

SCLK
MOSI
MISO

AMUX_A0
AMUX_A1
AMUX_A2
AMUX_A3
AMUX_A4
AMUX_A5
AMUX_A6
AMUX_A7
AMUX_AY

AMUX_B0
AMUX_B1
AMUX_B2
AMUX_B3
AMUX_B4
AMUX_B5
AMUX_B6
AMUX_B7
AMUX_BY

TDEV1
TDEV2
TDEV3
TDEV4
TDEV5
TCAL

XTAL1
XTAL2

VDD_RTC

IBAT

N8

PMU_PRE_UVLO_DET

L7

NC

M7

NC

H7

TRISTAR_TO_PMU_USB_BRICK_ID

PMU_ADC_IN

K7

M12

BUTTON_VOL_DOWN_L

N12

BUTTON_POWER_KEY_L

M11

BUTTON_RINGER_A

N11
H11

J11
K11

F16
F15
G14
F14
F13
G13
G12
H12
G11
G10
F9
G9
F8
G8
H9
H10
J9
J10
K9
K10
L9

Reserved for MENU key on dev board

NC

PMU_TO_AP_BUF_VOL_DOWN_L
PMU_TO_AP_BUF_POWER_KEY_L
PMU_TO_AP_BUF_RINGER_A

TIGRIS_TO_PMU_INT_L
BB_TO_PMU_PCIE_HOST_WAKE_L
PMU_TO_BBPMU_RESET_R_L
WLAN_TO_PMU_HOST_WAKE
NFC_TO_PMU_HOST_WAKE
PMU_TO_NAND_LOW_BATT_BOOT_L

NC_PMU_TO_GNSS_EN

PMUGPIO_TO_WLAN_CLK32K
PMU_TO_BT_REG_ON

NC_GNSS_TO_PMU_HOST_WAKE

PMU_TO_WLAN_REG_ON
BT_TO_PMU_HOST_WAKE
PMU_TO_CODEC_DIGLDO_PULLDN
PMU_TO_ACC_BUCK_SW_EN
PMU_TO_BB_USB_VBUS_DETECT
PMU_TO_NFC_EN

PMU_TO_BOOST_EN

PMU_TO_LCM_PANICB

PMU_TO_HOMER_RESET_L

I2C0_AP_SCL

19

20

12

12

12

40 20

44 20

44 20

44 20

21

53

53

53

17

53

53

53

32

27

53

53

23

39

36

37 47

Button for two-finger reset: 20711463 and 21196187

ROOM=PMU

53 20

#24511807: Stuff for Carrier

R2009

RS
RS

RS

Sequencer controllable

PRE_UVLO_DET

PMGR

VBAT

BRICK_ID

ADC_IN

BUTTON1
BUTTON2
BUTTON3
BUTTON4

AMUX

BUTTONS

NTCXTAL

GPIO

GPIO21 = I2C SCL is for Chestnut dark current mitigation RS = requires sequencer

BUTTONO1
BUTTONO2
BUTTONO3

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21

R2000

1.00K

5%

1/32W

MF

01005

0.00

1/32W
01005

21

0%
MF

C

21

PMU_TO_BBPMU_RESET_L

53

B

PMU_TO_AP_FORCE_DFUPMU_TO_AP_FORCE_DFU_R

12 4

I2C1_AP_SCL

47

21

44 12

39 37

40 20

TBD

53 20

I2C_PMU_SDA_R

11

SPI_PMGR_TO_PMU_SCLK
SPI_PMGR_TO_PMU_MOSI

11

SPI_PMU_TO_PMGR_MISO

11

AP_TO_PMU_AMUX_OUT

7

PMU_ADC_IN

20

BUTTON_VOL_UP_L

LCM_TO_CHESTNUT_PWR_EN
TRISTAR_TO_PMU_USB_BRICK_ID
PP1V2_MAGGIE

36

PMU_AMUX_AY

4

53

BBPMU_TO_PMU_AMUX1
BBPMU_TO_PMU_AMUX2

53

ACC_BUCK_TO_PMU_AMUX

27

PMUGPIO_TO_WLAN_CLK32K

CHESTNUT_TO_PMU_ADCMUX

37

7

AP_TO_PMU_TEST_CLKOUT

BBPMU_TO_PMU_AMUX3

53

PMU_AMUX_BY

4

NC

NC

NC

FOREHEAD_NTC
REAR_CAMERA_NTC
RADIO_PA_NTC
AP_NTC

PMU_TCAL

NC

PMU_XTAL1

PMU_XTAL2

PMU_VDD_RTC

1

C2002

0.22UF

20%

6.3V

2

X5R
0201

ROOM=PMU

A

AP NTC

1

C2010

100PF

NP0-C0G

ROOM=PMU

01005

5%

16V

1

2

R2004

10KOHM-1%

01005

2

ROOM=PMU

AP_NTC_RETURN

NOTE:100PF CAPS ARE THE SAMPLING CAPS FOR PMU ADC

1

C2011

100PF

5%
16V

2

NP0-C0G MF
01005

ROOM=PMU

1

R2010

3.92K

0.1%
1/20W

0201

2

ROOM=PMU

C2003

22PF

5%

16V

CERM

01005

ROOM=PMU

1

2

19

CRITICAL

32.768KHZ-20PPM-12.5PF

Y2001

21

1.60X1.00-SM

ROOM=PMU

PMU_VSS_RTC

1

C2004

22PF

5%
16V

2

CERM
01005

ROOM=PMU

XW2001

SHORT-20L-0

ROOM=PMU

OMIT

.05MM-SM

21

SYNC_MASTER=Sync

PAGE TITLE

SYSTEM POWER:PMU (3/3)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00482

REVISION

D

8.0.0

BRANCH

PAGE

20 OF 53

SHEET

20 OF 81

SYNC_DATE=06/06/2016

A

8 7 5 4 2 1

36

TIGRIS CHARGER

345678

2 1

D

1

C2113

10UF

20%

6.3V

2

CERM-X5R
0402-9 0402-9

ROOM=CHARGER

1

2

C2114

10UF

20%

6.3V
CERM-X5R

ROOM=CHARGER

PP_VDD_MAIN

D

30 28 27 26 25 23 19 18 10 9 4

53 46 41 40 39 37 35 34 33 31

C

B

41 40 4

20 19

20

PP5V0_USB

PP1V8_ALWAYS

TIGRIS_TO_PMU_INT_L

7

USB_VBUS_DETECT

1

R2101

100K

5%
1/32W
MF
01005

2

ROOM=CHARGER

#24558610: Change to 100ohm

1

C2101

4.2UF

10%
16V

2

X5R-CERM
0402-1

ROOM=CHARGER

R2103

100

5%

1/32W

MF

01005

R2104

30.1K

1%

1/32W

MF

01005

TIGRIS_PMID

1

C2103

100PF

5%
35V

2

NP0-C0G
01005

ROOM=CHARGER

1

C2110

330PF

10%
16V

2

CER-X7R
01005

F4: 100 kOhm pullup to VLDO (regulated output voltage)

21

ROOM=CHARGER

21

ROOM=CHARGER

1

2

ROOM=CHARGER

20 17 15

1

C2109

4.2UF

10%
16V
X5R-CERM
0402-1

ROOM=CHARGER

47

I2C1_AP_SDA

47

I2C1_AP_SCL

C2111

4.2UF

10%
16V

2

X5R-CERM
0402-1

ROOM=CHARGER

SYSTEM_ALIVE

40

TRISTAR_TO_TIGRIS_VBUS_OFF

TIGRIS_TO_PMU_INT_R_L

TIGRIS_VBUS_DETECT

1

C2112

100PF

5%
35V

2

NP0-C0G
01005

ROOM=CHARGER

F5

PMID

A5

VBUS

B5

VBUS

D5

VBUS

C5

VBUS

E5

VBUS

G3

SDA

E4

SCL

E3

SYS_ALIVE

F4

VBUS_OVP_OFF

G2

INT

F1

VBUS_DET

F3

TEST

C2

D2

B2

A2

VDD_MAIN

VDD_MAIN

VDD_MAIN

VDD_MAIN

U2101

SN2400AB0

WCSP

ROOM=CHARGER

CRITICAL

PGND

PGND

PGND

PGND

B3

A3

D3

C3

LDO

BOOT

BUCK_SW
BUCK_SW
BUCK_SW
BUCK_SW

BAT
BAT
BAT
BAT

BAT_SNS

ACT_DIODE

HDQ_HOST

HDQ_GAUGE

G4
G5
A4

B4
D4
C4

A1
B1
D1
C1

E1
E2
G1

F2

TIGRIS_LDO

1

C2104

220PF

5%
10V

2

C0G-CERM
01005

ROOM=CHARGER

NO_XNET_CONNECTION

C2105

0.047UF

TIGRIS_BOOT

ROOM=CHARGER

TIGRIS_BUCK_LX

VBATT_SENSE
TIGRIS_ACTIVE_DIODE
SWI_AP_BI_TIGRIS

TIGRIS_TO_BATTERY_SWI_1V8

10%
16V
X5R

0201

1

C2115

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=CHARGER

28

TO TRINITY

A1

A3

A2

G

#25112685,Remove Snub

10%
16V

1

2

C2106

21

22

12

330PF

CER-X7R

ROOM=CHARGER

01005

C2102

220PF

C0G-CERM

ROOM=CHARGER

NOSTUFF

01005

R2102

47 46 41 40 37 36 32 20 18 16

53 52 48

PP1V8_SDRAM

ROOM=CHARGER

5%

10V

100K

5%

1/32W

MF

01005

1

2

1

2

C1

1

C2108

330PF

10%
16V

2

CER-X7R
01005

B3

B2

B1

C2

S

D

C3

ROOM=CHARGER

CRITICAL

Q2101

CSD68827W

BGA

ROOM=CHARGER

PP_BATT_VCC

1

C2117

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=CHARGER

1

C2118

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=CHARGER

22 4

C

B

1

R2105

40.2K

1%
1/32W
MF
01005

2

2

RV3C002UN

1

G

S

SYM_VER_1

Q2102

DFN

D

3

TIGRIS_TO_BATTERY_SWI

22

A

SYNC_MASTER=Sync

PAGE TITLE

SYSTEM POWER:CHARGER

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00482

8.0.0

21 OF 53
21 OF 81

D

SYNC_DATE=06/06/2016

A

345678

2 1

D

D

BATTERY CONNECTOR

THIS ONE ON MLB ---> 516S00172 (matches d10 mlb MCO rev 27)

C

TIGRIS_TO_BATTERY_SWI

21

R2201

100

1/32W
01005

ROOM=BATTERY_B2B

21

5%
MF

TIGRIS_BATTERY_SWI_CONN

1

C2201

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=BATTERY_B2B

RCPT-BATT-SHORT

J2201

F-ST-SM

1
3 2
4

ROOM=BATTERY_B2B

CRITICAL

ALLOW_APPLE_PREFIX

11
87

5

6

109
12

XW2201

SHORT-20L-0

PLACE_NEAR=J2201:2mm

ROOM=BATTERY_B2B

NO_XNET_CONNECTION=1

.05MM-SM

21

VBATT_SENSE

1

C2202

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=BATTERY_B2B

21

1

C2203

100PF

5%
16V

2

NP0-C0G
01005

ROOM=BATTERY_B2B

1

C2204

220PF

5%
10V

2

C0G-CERM
01005

ROOM=BATTERY_B2B

PP_BATT_VCC

C

21 4

B

B

A

SYNC_MASTER=Sync

PAGE TITLE

SYSTEM POWER:BATTERY CONN

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00482

8.0.0

22 OF 53
22 OF 81

D

SYNC_DATE=06/06/2016

A

34567 8

2 1

D

D

C

28 27 26 25 21 19 18 10 9 4

46 41 40 39 37 35 34 33 31 30

53

PP_VDD_MAIN

1

C2309

10UF

20%

6.3V

2

CERM-X5R
0402-9

ROOM=BOOST

1

C2301

4.7UF

20%

6.3V

2

X5R-CERM1
402

ROOM=BOOST

20

PMU_TO_BOOST_EN

1

R2301

511K

1%
1/32W
MF
01005

2

L2301

ROOM=BOOST

0.47UH-20%-4.2A-0.048OHM

21

SYS_BOOST_LX

PIUA20121T-SM

I2C0_AP_SCL

47

I2C0_AP_SDA

47

BOOST

A3

VIN

A4
C3

C4
A1
B2
C2
B1
C1

VIN

SW
SW

EN
SCL
SDA
VSEL
BYP*

U2301

SN61280D

DSBGA

ROOM=BOOST

VOUT
VOUT

B3
B4

1

C2302

15UF

20%

6.3V

2

X5R
0402-1

ROOM=BOOST

1

C2303

15UF

20%

6.3V

2

X5R
0402-1

ROOM=BOOST

1

C2304

15UF

20%

6.3V

2

X5R
0402-1

ROOM=BOOST

1

C2307

15UF

20%

6.3V

2

X5R
0402-1

ROOM=BOOST

1

C2308

15UF

20%

6.3V

2

X5R
0402-1

ROOM=BOOST

1

C2306

220PF

5%
10V

2

C0G-CERM
01005

ROOM=BOOST

When VDD_MAIN < 3.4, boosts to 3.4
Otherwise tracks VDD_MAIN

PP_VDD_BOOST

53 38 37 32 30 25 19

C

B

53 39 20 13

LCM_TO_MANY_BSYNC

HIGH=FORCE PWM MODE

Control details from Radar 19634006

A2

GPIO

PGND

D3

D2

D4

AGND

D1

B

A

SYNC_MASTER=Sync

PAGE TITLE

SYSTEM POWER:BOOST

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00482

8.0.0

23 OF 53
23 OF 81

D

SYNC_DATE=06/06/2016

A

345678

2 1

D

C

36 24 18

36 24 18

PP1V8_MAGGIE_IMU

13

PP1V8_MAGGIE_IMU

1

2

BOMOPTION=CARBON_1

1

R2401

100K

5%
1/32W
MF
01005

2

ROOM=SOC

SPI_AOP_TO_ACCEL_GYRO_CS_L

GYRO_CHARGE_PUMP

13

ACCEL_GYRO_TO_AOP_INT

BOMOPTION=CARBON_1

1

C2403

0.1UF

10%

6.3V

2

X6S
0201

ROOM=CARBON

CARBON - ACCEL & GYRO

C2418

2.2UF

20%

6.3V
X5R-CERM
0201-1

ROOM=CARBON

INVENSENSE, MPU-6800: C2403=0.1UF

BOMOPTION=CARBON_1

1

C2402

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=CARBON

BOMOPTION=CARBON_1

1

C2415

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=CARBON

16

VDD

1

BOMOPTION=CARBON_1

VDDIO

U2401

MPU-6900-21

LGA

5
8

14

7

CS
FSYNC
REGOUT

INT

GND

9

ROOM=CARBON

CRITICAL

GND

GND

12

11

10

GND

GND

13

SPC

SDI

SDO

DRDY

GND

15

BOMOPTION: CARBON_1
#25765850:Update Carbon APN

2

SPI_AOP_TO_IMU_SCLK_R1

3

SPI_AOP_TO_IMU_MOSI

4

SPI_IMU_TO_AOP_MISO

6

ACCEL_GYRO_TO_AOP_DATARDY

13

MAGNESIUM - COMPASS

D

PP1V8_MAGGIE_IMU_FILT

24

1

C2401

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=MAGNESIUM

24 13

24 13

24 13

BOMOPTION=CARBON_1

1

C2419

5PF

+/-0.1PF
16V

2

NP0-C0G
01005

ROOM=CARBON

PP1V8_MAGGIE_IMU_FILT

24

1

C2408

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=MAGNESIUM

NC
NC

NC
NC
NC

C2

B1

B3
D1
D2

D4

C4

VDD

U2402

HSCDTD601A-19A

VPP
RSV

RSV
RSV
RSV

RST*

ROOM=MAGNESIUM

LGA

CRITICAL

VSS

C1

SDO

SDA/SDI

SCL/SCK

114K INT PU

114K INT PD1.09M INT PU

CSB

TRG/SE

DRDY

B4
A4
A3
A2
C3
A1

NC

SPI_IMU_TO_AOP_MISO
SPI_AOP_TO_IMU_MOSI
SPI_AOP_TO_IMU_SCLK_R1
SPI_AOP_TO_COMPASS_CS_L

COMPASS_TO_AOP_INT

PP2404

1

SM

PP

P2MM-NSM

ROOM=MAGNESIUM

PP2401

1

PP

ROOM=MAGNESIUM

SM

P2MM-NSM

24 13

24 13

24 13

13

13

C

B

36 24 18

#25782019:Add 0ohm

R2404

PP1V8_MAGGIE_IMU PP1V8_MAGGIE_IMU_R

ROOM=BOT_CARBON

PP1V8_MAGGIE_IMU_R

24

13

0.00

0%

1/32W

MF

01005

1

R2441

100K

5%
1/32W
MF
01005

2

ROOM=SOC

BOT_GYRO_CHARGE_PUMP

1

C2443

0.1UF

10%

6.3V

2

X6S
0201

ROOM=BOT_CARBON

24

21

1

C2448

2.2UF

20%

6.3V

2

X5R-CERM X5R-CERM
0201-1

ROOM=BOT_CARBON

1

C2442

0.1UF

2

SPI_AOP_TO_BOT_ACCEL_GYRO_CS_L

OMIT

XW2404

SHORT-20L-0.05MM-SM

21

NC

ROOM=BOT_CARBON
NO_XNET_CONNECTION=1

XW2404 to balance Via/Cu at INT pin

BOT_ACCEL_GYRO_TO_XW_INT

20%

6.3V
X5R-CERM
01005

ROOM=BOT_CARBON

1

C2445

0.1UF

20%

6.3V

2

01005

ROOM=BOT_CARBON

14

5
8

7

VDD

CS
FSYNC
REGOUT

INT

GND

9

16

1

VDDIO

U2404

MPU-6900-21

LGA

ROOM=BOT_CARBON

CRITICAL

GND

GND

GND

13

12

11

10

GND

SPC

SDI

SDO

DRDY

GND

15

#25740540:PP for South Carbon MOSI

2

SPI_AOP_TO_IMU_SCLK_R2

3

SPI_AOP_TO_IMU_MOSI

4

SPI_IMU_TO_AOP_MISO

6

BOT_ACCEL_GYRO_TO_AOP_DATARDY

PP2402

SM

1

PP

P2MM-NSM

ROOM=MAGNESIUM

PP2403

1

PP

24 13

24 13

PP2440

SM

P2MM-NSM

ROOM=HOMER

13

NOSTUFF

1

C2449

5PF

+/-0.1PF
16V

2

NP0-C0G
01005

ROOM=BOT_CARBON

13

1

PP

ROOM=MAGNESIUM

SM

P2MM-NSM

B

A

PP1V8_MAGGIE_IMU_FILT

24

BOSCH: Internal PU

13

NOSTUFF

1

R2403

100K

5%
1/32W
MF
01005

ROOM=SOC

2

SPI_AOP_TO_IMU_SCLK_R1

24 13

SPI_AOP_TO_PHOSPHORUS_CS_L

PP1V8_MAGGIE_IMU_FILT

24

VDD

U2403

BMP284AA

SDI SDO

4

SCK

2

CS*

8

GND

LGA

1

6

VDDIO

IRQ

1

C2413

20%

6.3V

2

X5R-CERM
01005

ROOM=PHOSPHORUS

53

7

PHOSPHORUS

#24593845

BOSCH (APN:338S00188): nostuff C2420/C2421/C2422/C2423 and R2403 PU

ST (APN:338S00230): stuff C2420-C2423, C2420R2422 with 155S00017, stuff R2403 PU
C2420=4pF(131S0253),C2405=3pF(131S0251) per #25691124

R2422

1

C2405

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=PHOSPHORUS

SPI_IMU_TO_AOP_MISOSPI_AOP_TO_IMU_MOSI

PHOSPHORUS_TO_AOP_INT_L

13

NOSTUFF

1

C2420

4PF

+/-0.1PF
16V

2

NP0-C0G
01005

ROOM=PHOSPHORUS

24 13 24 13

NOSTUFF

1

C2421

20PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=PHOSPHORUS

0.00

1/32W
01005

ROOM=PHOSPHORUS

0%
MF

21

NOSTUFF

1

C2422

20PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=PHOSPHORUS

NOSTUFF

1

C2423

5.6PF

+/-0.1PF
16V

2

NP0-C0G-CERM
01005

ROOM=PHOSPHORUS

1

C2414

2.2UF0.1UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=PHOSPHORUS

PP1V8_MAGGIE_IMU

SYNC_MASTER=Sync

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

36 24 18

Apple Inc.

R

SENSORS

DRAWING NUMBER SIZE

051-00482

REVISION

D

8.0.0

BRANCH

PAGE

24 OF 53

SHEET

24 OF 81

SYNC_DATE=06/06/2016

A

8 7 5 4 2 1

36

345678

2 1

D

Scrub voltage selection

NOTE: OUTPUT IMPDEANCE MUST BE >0.005-OHM

IN ORDER TO MEET CAP ESR REQUIREMENT PER LDO SPEC.
VENDOR ALSO RECOMMENDS CIN = COUT FOR STABILITY

U2501

LP5907UVX2.925-S

53 38 37 32 30 23 19 46 45

PP_VDD_BOOST

1

C2527

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=RCAM_B2B

B1

VIN

VEN

DSBGA

ROOM=RCAM_B2B

GND

B2

VOUT

A2A1

1

See Page46: D11x C2507 is 4UF

C2502

0.22UF

10%

6.3V

2

CER-X5R
01005

ROOM=RCAM_B2B

PP2V9_UT_AVDD_CONN

1

C2504

220PF

5%
10V

2

C0G-CERM
01005

ROOM=RCAM_B2B

L2501

33-OHM-25%-1500MA

30 18

PP2V8_UT_AF_VAR

0201

ROOM=RCAM_B2B

21

1

C2505

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=RCAM_B2B

PP2V8_UT_AF_VAR_CONN

1

C2501

220PF

5%
10V

2

C0G-CERM
01005

ROOM=RCAM_B2B

IO FILTERSUTAH POWER

FL2504

150OHM-25%-200MA-0.7DCR

AP_TO_UT_CLK

9

1

C2512

100PF

5%
16V

2

NP0-C0G
01005

ROOM=RCAM_B2B

NOSTUFF

01005

ROOM=RCAM_B2B

21

1

C2513

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=RCAM_B2B

FL2501

150OHM-25%-200MA-0.7DCR

45 45

9

AP_TO_UT_SHUTDOWN_L

01005

ROOM=RCAM_B2B

21

1

C2514

220PF

5%
10V

2

C0G-CERM
01005

ROOM=RCAM_B2B

AP_TO_UT_CLK_CONN

AP_TO_UT_SHUTDOWN_CONN_L

45

D

C

30 29 19

19

29 18 17 16 13 12 11 9 8 7 5

52 48 47 46 39 30

PP3V0_ALS_APS_CONVOY

PP1V2_UT_DVDD

PP1V8

L2502

33-OHM-25%-1500MA

21

0201

ROOM=RCAM_B2B

L2503

33-OHM-25%-1500MA

21

0201

ROOM=RCAM_B2B

L2504

33-OHM-25%-1500MA

21

0201

ROOM=RCAM_B2B

1

C2506

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=RCAM_B2B

1

C2519

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=RCAM_B2B

1

C2508

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

ROOM=RCAM_B2B

1

2

1

C2510

2.2UF

20%

6.3V

2

X5R-CERM
0201-1

C2509

1.0UF

20%

6.3V
X5R
0201-1

ROOM=RCAM_B2B

ROOM=RCAM_B2B

PP3V0_UT_SVDD_CONN

1

C2518

220PF

5%
10V

2

C0G-CERM
01005

ROOM=RCAM_B2B

PP1V2_UT_VDD_CONN

1

C2503

220PF

5%
10V

2

C0G-CERM
01005

ROOM=RCAM_B2B

1

2

PP1V8_UT_CONN

1

C2511

220PF

5%
10V

2

C0G-CERM
01005

ROOM=RCAM_B2B

45

45

C2521

15PF

5%
16V
NP0-C0G-CERM
01005

ROOM=RCAM_B2B

Desense for Wifi frequencies

45

26

28 27 26 23 21 19 18 10 9 4

46 41 40 39 37 35 34 33 31 30

53

UT_AND_NV_TO_STROBE_DRIVER_STROBE

LPDP FILTERS

AC return path for LPDP which is referenced to GND and VDD_MAIN

PP_VDD_MAIN

FL2503

150OHM-25%-200MA-0.7DCR

21

01005

ROOM=RCAM_B2B

1

C2515

220PF

5%
10V

2

C0G-CERM
01005

ROOM=RCAM_B2B

UT_AND_NV_TO_LED_DRIVER_STROBE_EN_CONN

45 30

C

B

10

90_LPDP_UT_TO_AP_D2_P

10

90_LPDP_UT_TO_AP_D2_N

90_LPDP_UT_TO_AP_D3_P

10

10

90_LPDP_UT_TO_AP_D3_N

1

C2522

33PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=RCAM_B2B

90_LPDP_UT_TO_AP_D2_P

MAKE_BASE=TRUE

90_LPDP_UT_TO_AP_D2_N

MAKE_BASE=TRUE

90_LPDP_UT_TO_AP_D3_P

MAKE_BASE=TRUE

90_LPDP_UT_TO_AP_D3_N

MAKE_BASE=TRUE

1

C2528

33PF

5%
16V

2

NP0-C0G-CERM
01005

C2523

ROOM=RCAM_B2B

C2524

ROOM=RCAM_B2B

C2525

ROOM=RCAM_B2B

C2526

ROOM=RCAM_B2B

ROOM=RCAM_B2B

21

6.3V20%

X5R-CERM

X5R-CERM

X5R-CERM

X5R-CERM 01005

01005

21

6.3V20%
01005

21

6.3V20%
01005

21

6.3V20%

1

C2529

33PF

5%
16V

2

NP0-C0G-CERM
01005

0.1UF

0.1UF

0.1UF

0.1UF

ROOM=RCAM_B2B

90_LPDP_UT_TO_AP_D2_CONN_P

90_LPDP_UT_TO_AP_D2_CONN_N

90_LPDP_UT_TO_AP_D3_CONN_P

90_LPDP_UT_TO_AP_D3_CONN_N

B

45

45

45

45

A

10

LPDP_UT_BI_AP_AUX

LPDP_UT_BI_AP_AUX

MAKE_BASE=TRUE

C2530

0.1UF

21

20%

6.3V

X5R-CERM

01005

ROOM=RCAM_B2B

LPDP_UT_BI_AP_AUX_CONN

1

C2520

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=RCAM_B2B

45

SYNC_MASTER=sync

PAGE TITLE

B2B FILTERS: UTAH

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=05/17/2016

DRAWING NUMBER SIZE

051-00482

REVISION

D

8.0.0

BRANCH

PAGE

25 OF 53

SHEET

25 OF 81

A

8 7 5 4 2 1

36