Apple iPad 2 Wi-Fi Schematics

Second Generation

http://mobilegsm.in.ua/

editor "schemu"

8

7

3456

12

D

D

820-3069-A -Left MLB

J3700

C1023

C1032

C1131

R0765

R8218

R1209

R1208

R1207

C1029

C0908 C0903

C0902

C0907 C0654

C1018

R1005

C1002

C1027

C0930

C0661

FL0610

C0920

R1001
C1007

R1006

C1145
C1144

C1005

C1017

C1148

C1147

C1149

C1146

C

R5613

J5600

R3608

R3622

R3621

C5623

C5616

C5614

C5615

MT1

J6100

R5512

R5513

C3851

C3614

C3613

R3851

C3618

C3617

C3606

C3605

C4310

C3602

U3600

R4312

C3600

L4303

C3853C3852

C3601

L4301

L4304

L4306
C5510

L5510

C5512

C5511

R5510

R5511

C5521

L5520

L5501

C5522

L5500

C5520

J5501

C5601

C563

C5602

R3620

L5612

C3850

C3615

C3604

R3850

R3603

R3602

R3601

C3854

L4302

C5500

U5501

C5501

L5610

R0705

R0704

R1400

C3608

C3616

C3603

C3609

C3607

C3611

C4217

C1403

R4213

R4212

C4213

C4211

R4202

R4203

C4200

C4201

R4201

U4200

C4216

C4212

R3605

R3604

R0813
R0811
R0812

U5500

L5540

R0932

R0933

C5542

R5501

C5541

C5540

C5530

C5620

C5600

R5600

R0703

R0931

R0930

R0702

R5612

R5611

R5610

C5621

C5617

C5612

C5613

C5618

L5613

L5611

U1400

R7541

C7522

FL7500

LED9000

L5601

L5600

C7523

C7525

C7524

R9002

C1414

C1402

C1404

R1401

R0801
R0803
R0810

R0800

C1411

C1400

R0825
R0833

R0864
R0832
R0831
R0802

R0860
R0834

C1401

R0865

R0867
R0827

R0828
R0861

R0836

C3803

C3800

R3800

U1410

C3801
C3802

TP7502

C0655

C1412

C1413

R0866

R0862
R0863

C1410

R0770

R0738

R0737

R0739

R0735

R9000

C1042

C1046

R0736

R1201

R1202

R1200

R1203

C1150

C1151

C1152

C1013

U0652

C1019

R1205

C1052

C1160

R1204

R1052

R1206

C1161

R1000

C1180

C1011

R1051

C1014

C1008

R1055

C1020

C1043

C1125

C1129

C1127

R0771

C1128

C1141

R1056

C1135

C1137

C1056

C1138

C1030

C1012

R0900

R0957

R0955

R0956

C1006

R0940

C1041

C0955

C1143

C0954

C0952

C1045

C0951

C1044

R0720

FL0910

C1182

DZ5720

R1731

R1210

R0662

R5710

C5780

R0910

R1750

U1701

C0923

C1750

R1751

C1034

C1130

C1132

C1126

C1024
C1136
C1140

C1036

C1133

C1037

C1134

C1038

C1139

C1026

C1035

C1021

C0651

C0641

R1253
R1252

R0950

C1706

C1707

R1251

R1250

C0924

R0920

C1250

R1723

C1703

C1702

C0950

R1720

R5730

C0956

R0645

R5795

R0646

R0617

R0689

C0618

R0632

R0688

C2011

C2013

C1040

FL2002

R2010

C1101

U2000

C2016

C1010

R2052

C1001

C1100

C1104

C1105

C1111

C1119

C1120

C1112

C1116

C1118

C1022

C1121

C2001

C1102

C1000

C1113

C1115

C1108

C1107

C1110

C1109

C1114

C1117

C1106

C1103

Q8351

R0620

C1039

R0621
R0624

C0608

C0660

C0648

C0644

C0646

C1004

R1054

C1054

C0642

C0627

C0909
C0643

C1251

C1031

C0926

R5731

R5796

U5730

C5730

R8352

C0607

C0613

R0640

R0655

R0623

Y0602

R0622

R0642

C0652

R1260

C1009

R0625

C1142

C1181

DZ0600

R1053

C0640

R0651

C0630

C1705
C1704

C1016C1015

C0925

C0927

C1301
C1300

R1315

C1370

R1372

U1300

R1320

R1362

R1360

R1361

R0647

R1212

R1211

R1214

R1213

R2050
R2051

C2014

C2003

C2002

FL2001

U2001

C2004

C2010

R2006

C2000

R2001

C2017

R0878

R2002

R2008

R2003

FL2000

Q8350

C2015

C2012

C8119

C8120

R8350

R8353
R8351

R8354

L8128

R1370
R1371

C8108

C8107

C8352

C8353

C8351

L8110

C8166

L8105

L8107

C8102

C8103

R8202

C8157

C8164

R9001

C8159

C8161

C8135

U8100

C8209

C8160

C8169

C8149C8167

C8204

C8147

C8142

C8143

C8144

C8168

C8130

R8203

C8153

Y8138

C8136

C8150

C8148

C8146

C8226

R6100

C6100
R6101

L6001

L5757

C5721

C5722

R5790

C6001

C8122

C8121

L8121

L8101

C8158

C8131

C8212

C8152

C8145

C8162

C8151

C8163

C8214

R5752

L8225

Q8123

C8117

L8119

C8118

L8115

L8100

C8138

C8140

C8238

DZ8120

R8130

R8116

C8124

C8141

C8139

C8137

R0700
R0701

C8210

C8206

C8125

C8207
C8217
C8223
C8215

C8220

C8221

C8155

C8201

C8236

R8222

R8219

L8229

C8156

C8154

C8237

D8230

C8234

C8235

C2233

C8233

C2220

D8228

C8232

C8101

C8100

Q8104

L8112

L2200

R8100

D8100

C6000

L6000

J6000

C8165

C3030

R2205

R2211

R3180

R3173

Q2201

R3171

R2204

U3101

C3112

C2241

R2210

C2240

C3110

C2204

R2250

R2203

C2203

C2230

C2202

Q2200

L2201

L2202L2232

R8235

R8239

R8227

R8231

R8232

R8240

L2222L2212

C3106

C3108

C3109

C3111

R3107

R2200

R2201

C2200

C2232

C2231

C3031

R3031

R3032

R3120

C3041

R3030

U3009

U3007

C3107

R3161

U3010

R3160

R3025

C3050

C3105

R3181

R3190

C3101

R3155

C3102

C3191

C2206

C3714

C3713

R3713

R3700

U3710

C3711

C3712

R5750

R3711

R3712

R3033

R5751

C3104

R3101

C3103

C3704

C3703

R3703

U3700

C3701

C3702

R3701

R3702

L5762

L5760

L5763

L5761

FL5711
FL5707
FL5708

D5703D5701

L5716

L5700L5701

U3100

J2201

C3053

C3007

U3003

C3750

C3751

C3752

C3753

C5783

DZ5760

DZ5752

R5753

C5755

R5721

DZ5751

D5700

D5702

R5720

C5782

C5754

C5751

L5702

DZ5790

R8216

C5750

DZ5711

DZ5710
DZ5712

R5740

J5900

U5700

C5753
C5760

L5714

DZ5753

C5752

DZ5750

C

J3010

C3009

C3000

R3066

B

820-3069-A -Right MLB

R3012
C3002

U3000

C3005

C3001

C3008

R3009

D3000

C3006

L3000

A

J3011

B

A

8 7 6 5 4 2 1

3

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

K94 CHOPIN MLB

3456

A

ECNREV

0001052699

DESCRIPTION OF REVISION

PRODUCTION RELEASED

12

CK
APPD

DATE

2011-01-10

PVT

D

REV. A

D

LAST_MODIFIED=Mon Jan 10 13:11:06 2011

PDF

CSAPDF

TABLE_TABLEOFCONTENTS_HEAD

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B

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TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

DRAWING

TITLE=BACH
ABBREV=DRAWING

CONTENTS

1

TABLE OF CONTENTS

2

BLOCK DIAGRAM: SYSTEM

5

BOM TABLE

6

AP: MAIN
AP: I/Os

8

AP: NAND
AP: TV,DP,MIPI

9
10

AP: PWR
AP: PWR

11

AP: MISC & ALIASES

12

AP: VIDEO BUFFER,BB USB MUXES

13

14

VIDEO: DISPLAY PORT

17

VIDEO: MLC

20

VIDEO: MLC ALIASES

21

22

VIDEO: LVDS CONNECTOR
GRAPE: GROUNDHOG,CONN,BOOST

31

GRAPE: Z1, Z2

36

AUDIO: L63 CODEC
AUDIO: SPEAKER AMP

37

38

AUDIO: HEADPHONE OUT

39

AUDIO: BLANK

42

AUDIO: DETECT/MIC BIAS

43

AUDIO: HP/MIC FILTERS

54

CONNECTOR: CANADA FLEX CONN,SENSOR PANEL ALIASES

55

CONNECTOR: CANADA FLEX FILTERS
CONNECTOR: SENSOR PANEL CONNECTOR

56

IO FLEX: DOCK COMPONENTS

57

59

IO FELX: B2B Connector

60

CONNECTOR: X23 WIFI/BT
CONNECTOR: X24 CELLULAR/GPS

61

SYNC MASTER

MIKE

MIKE2N/A

MIKE

JAMES

JAMES7N/A

JAMES

JAMES

JAMES8N/A

JAMES

JAMES

JAMES

JONATHAN

JAMES

MIKE

MIKE

ALEX

RAMSIN30N/A

RAMSIN N/A

LENG

LENG

LENG

LENG

LENG

LENG

MARK B.

MARK B.

MARK B.27N/A

JAMES

JAMES

MIKE

MIKE

DATE

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

TABLE_TABLEOFCONTENTS_HEAD

32

TABLE_TABLEOFCONTENTS_ITEM

33

TABLE_TABLEOFCONTENTS_ITEM

34

TABLE_TABLEOFCONTENTS_ITEM

35

TABLE_TABLEOFCONTENTS_ITEM

36

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38

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39

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40

TABLE_TABLEOFCONTENTS_ITEM

41

TABLE_TABLEOFCONTENTS_ITEM

42

CSA

CONTENTS
POWER: ALIASES

73

75

POWER: BATTERY CONNECTOR
POWER: PMU

81

POWER: PMU

82
83

POWER: 3.3V VR
DEBUG AND MISC

90

93

FCT/ICT TEST/BRACKETS

100

CONSTRAINTS: ASSIGNMENTS
CONSTRAINTS: ASSIGNMENTS

101

CONSTRAINTS: MLB RULES

102

CONSTRAINTS: RF RULES

106

8 7 6 5 4 2 1

SYNC MASTER

YOSH

YOSH

YOSH

YOSH

YOSH

MIKE

MIKE

MIKE

MIKE

MIKE

MIKE

DATE

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

C

B

SIZE

A

D

DRAWING TITLE

CHOPIN MLB

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

1 OF 106

SHEET

1 OF 42

3

345678

2 1

ISP_I2C1

Z2

CSA 31

SPI1

H4P

MIPI1C

ISP_I2C0

MIPI0C

D

GROUNDHOG

CSA 30 CSA 31

Z1

DUAL-CORE ARM

CORTEX-A9 W/ SMP

850 MHZ

SDIO

UART3

LPDDR2

FF CAMERA

CANADA FLEX

REAR CAMERA

SENSOR PANEL

X23

WIFI/BT

BT_I2S

CSA 60

D

WIFI/BT ANT

2X32-BIT

400MHZ/800MB/S

DISPLAY/

TOUCH PANEL

C

BACKLIGHT

LVDS

MLC

CSA 20

MIPI0D

GPU

DUAL-CORE IMG

SGX543-MP

AUDIO

AE2

USB1.1

UART1
UART2
UART4

SPI2 IPC

USB1.1
USART
UMTS
GPS

X24

ICE3.0/GPS

CSA 61

CELLULAR ANT

GPS ANT

C

ARM A5 CPU

UART5

USB2.0

PMU

ALISON

BATTERY

UART0

30-PIN

DOCK

DISPLAYPORT

CSA 75

DWI

VIDEO DAC

AMP

I2C0

CSA 81

B

B

AUDIO CODEC

I2C1

VSP

ASP

XSP

PROX SENSOR

SENSOR PANEL SENSOR PANEL

COMPASS

I2C2

I2S2

I2S0

I2S3

FMI3FMI2FMI1FMI0 HSIC0

A

GYRO

SENSOR PANEL SENSOR PANEL

ACCELEROMETER

8 7 5 4 2 1

ALS

CANADA FLEX

NAND FLASHNAND FLASH

SD CARD READER

CSA 14 CSA 14

36

L63

LINEOUT

CSA 36

CSA 58

CSA 57

AMP

SPEAKER

AMP

MIC

HP

SYNC_MASTER=MIKE

PAGE TITLE

BLOCK DIAGRAM: SYSTEM

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

2 OF 106

SHEET

2 OF 42

SIZE

A

D

Page Notes

Power aliases required by this page:
(NONE)

Signal aliases required by this page:
(NONE)

BOM options provided by this page:

ALL AVAIL BOM OPTIONS

COMMON
ALTERNATE

D

16GB_PROD
32GB_PROD
64GB_PROD

BKLT_PLL
DEVELOPMENT_JTAG

DEVELOPMENT_JTAG_TAP
JTAG_DAP
JTAG_TAP_NOT

SPEAKER
INTERNAL_MIC

PORTRAIT_DOCK
MLC_DEV

MLC_PROD

K93
K94

345678

2 1

BOM OPTIONS

PROGRAMMABLE PARTS

SCH AND BOARD P/N

PART#

051-8962

820-3069

QTY

DESCRIPTION

SCH,CHOPIN_AUDIO,MLB,K94

1

PCBF,CHOPIN_AUDIO,MLB,K94

1

REFERENCE DESIGNATOR(S)

SCH1

PCB1

BOM OPTION

D

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

BOM GROUP

BASIC

BOM OPTIONS

COMMON,ALTERNATE

ADD DEVELOPMENT AND OTHER BOMS ONCE YOU GET BOM NUMBERS

C

B

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

PD PARTS

QTY

PART#

806-1397

806-1398 FENCE2

806-1399

806-1400 FENCE3

806-1401

TOP BARCODE LABEL/EEE CODES
(ONLY ONE IS USED PER BOM)

PART#

QTY

1

825-7651

825-7651

825-7651

825-7651

825-7651

825-7651

825-7651

825-7651

1

1

1

1

1

1

1

1

DESCRIPTION

1

FENCE,GRAPE,MLB,K93/K94

CAN,GRAPE,MLB,K93/K94

1

FENCE,CPU,MLB,K93/K94

1

CAN,CPU,MLB,K93/K94

1

FENCE,NAND,MLB,K93/K94

1

1

CAN,NAND,MLB,K93/K94

DESCRIPTION

EEEE FOR 639-1180 (K93 16G)

EEEE FOR 639-1426 (K93 32G)

EEEE FOR 639-1428 (K93 64G)

EEEE FOR 639-1112 (K94 16G)

EEEE FOR 639-1181 (K94 32G)

EEEE FOR 639-1182 (K94 64G)

EEEE FOR 639-1430 (K95 16G)

EEEE FOR 639-1427 (K95 32G)

EEEE FOR 639-1429 (K95 64G)

REFERENCE DESIGNATOR(S)

FENCE1806-1396

REFERENCE DESIGNATOR(S)

DH36825-7651

DH37

DG99

DFC4

DFC5

DFC6

DH3C

DH3D

DG9C

CAN1

CAN2

CAN3

CRITICAL BOM OPTION

CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL

BOM OPTION

NOSTUFF

NOSTUFF

NOSTUFF

EEEE_K93_16G

EEEE_K93_32G

EEEE_K93_64G

EEEE_K94_16G

EEEE_K94_32G

EEEE_K94_64G

EEEE_K95_16G

EEEE_K95_32G

EEEE_K95_64G

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

C

B

BOTTOM LABEL TYPE 1

PART#

825-7639 LBL1

825-7639 LBL2

QTY

1

1

DESCRIPTION

631- B/C LABEL

639- B/C LABEL

REFERENCE DESIGNATOR(S)

CRITICAL BOM OPTION

CRITICAL
CRITICAL

BOTTOM LABEL TYPE 2

PART#

825-7640

825-7640

DESCRIPTION

QTY

MATRIX LABEL

1

631- MATRIX LABEL

1

REFERENCE DESIGNATOR(S)

LBL3

LBL4

A

CRITICAL BOM OPTION

CRITICAL
CRITICAL

SYNC_MASTER=MIKE

PAGE TITLE

BOM TABLE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

SIZE

A

D

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

5 OF 106

SHEET

3 OF 42

345678

PART NUMBER

D

C

B

A

ALTERNATE FOR
PART NUMBER

AU14
AU15
AU16
AU17

AV1
AV2
AV3
AV4
AV5
AV6
AV7
AV8

AV9
AV10
AV11
AV12
AV13
AV14
AV15
AV16
AV17
AV29
AV33
AV34

AW1

AW2

AW4
AW23
AW33
AW34

AY1

AY2

AY3

AY4
AY20
AY22
AY24
AY30
AY31
AY32
AY33
AY34

B1
B2
B7

B9
B10
B12
B13
B15
B17
B18
B20
B22
B23
B28
B29
B30
B32
B33
B34

C1

C2

C3

C4

C5

C6

C7

C8

C9
C10
C11
C12
C13
C14
C15
C16
C23
C27
C29
C32
C33

D1

D3

D5

D7

D9
D11
D13
D15
D16
D23

BOM OPTION

U0652

H4P-512MB

BGA

SYM 11 OF 12

SC58940X01-A030

VSS VSS

REF DES

COMMENTS:

D27
D32
E1
E2
E3
E4
E6
E8
E10
E12
E14
E16
E17
E18
E19
E20
E21
E22
E23
E25
E26
E27
E28
E30
E31
E32
E34
F1
F2
F3
F5
F19
F20
F21
F22
F23
F25
F26
F29
F30
F31
F32
G1
G3
G4
G7
G8
G9
G10
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G25
G28
G29
G30
H1
H2
H3
H5
H7
H8
H10
H12
H14
H16
H18
H20
H22
H24
H25
H29
H30
J1
J2
J3
J4
J7
J9
J11
J13
J15
J17
J19

8 7 5 4 2 1

TABLE_ALT_HEAD

NEED TO ADD BOM TABLE FOR ALT P/N OF HYNIX (?)

=PP1V8_H4

4 5 7

10 13 32

R0645

100K

1 2

R0646

100K

1 2

R0647

100K

1 2

=PP3V3_USB_H4

4

32

28 31 35

IN

JTAG_AP_TCK

JTAG_AP_TMS

JTAG_AP_TDI

RST_AP_L

4

28 39

4

28 39

4

10 39

1

R0617

10K

1%
1/32W
MF
01005

2

=PP1V1_PLL_H4

32

JTAGSEL
0 - PARALLEL
1 - DAISY-CHAIN (FOR USE WITH 5-WIRE JTAG)

PER RADAR #6755237

10 13 32

R0632

100K

1 2

1%

1/32W

MF

01005

1

1

R0688

42.2K

1/32W
01005

C0618

1000PF

10%

1%

16V

2

X7R

MF

201

2

=PP1V8_H4

4 5 7

R0620

1 2

R0621

1 2

R0622

1 2

R0623

1 2

AP_DDR1_CKEIN_1V2

1

R0689

82.5K

1%

1/32W

MF

01005

2

0.00

0%

1/32W

MF

01005

0.00

0%

1/32W

MF

01005

0.00

0%

1/32W

MF

01005

0.00

0%

1/32W

MF

01005

R0624

0.00

1 2

0%

1/32W
01005

DEVELOPMENT_JTAG_TAP

1

2

=PP1V1_USB_H4

4

32

32

R0662

100K

1 2

10 39

10 39

4

10 39

4

28 39

4

28 39

NOSTUFF

XW0604

C0608

0.01UF

10%

6.3V
X5R
01005

=PP1V2_HSIC_H4

OUT
OUT
IN
OUT
OUT

MF

1

C0651

0.01UF

10%

6.3V

2

X5R
01005

1

C0648

0.01UF

10%

6.3V

2

X5R
01005

1

C0646

0.01UF

10%

6.3V

2

X5R
01005

1

C0644

0.01UF

10%

6.3V

2

X5R
01005

1

C0660

56PF

5%

6.3V

2

NP0-C0G
01005

AP_JTAG_SEL

10

JTAG_AP_TRST_L
JTAG_AP_TDO
JTAG_AP_TDI
JTAG_AP_TMS
JTAG_AP_TCK

10

10

10

10

SHORT-01005

1 2

NOSTUFF

XW0605

SHORT-01005

1 2

1

C0642

0.01UF

10%

6.3V

2

X5R
01005

TP_HSIC1_AP_DATA
TP_HSIC1_AP_STB

NC_HSIC2_AP_DATA
NC_HSIC2_AP_STB

NC_JTAG_AP_RTCK

AP_TESTMODE

AP_TST_STPCLK

TP_AP_TST_CLKOUT

AP_FAST_SCAN_CLK

AP_HOLD_RESET

RST_AP_1V8_L

AP_CFSB

AP_DDR1_CKEIN

PP1V1_PLL4_F

VOLTAGE=1.1V

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

PP1V1_PLL3_F

VOLTAGE=1.1V

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

PP1V1_PLL2_F

VOLTAGE=1.1V

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

PP1V1_PLL1_F

VOLTAGE=1.1V

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

PP1V1_PLL0_F

VOLTAGE=1.1V

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

1

C0643

0.22UF

20%

6.3V

2

X5R
0201

1

C0641

0.01UF

10%

6.3V

2

X5R
01005

A26
A27

C26
D26

N31
M30
N29
M31
M32
N32
N30

P29

M28

P33
P34

T32

P31

P32

W30

G11

R7

D25

HSIC_VDD121

17MA

HSIC1_DATA
HSIC1_STB

HSIC2_DATA
HSIC2_STB

JTAG_SEL
JTAG_TRTCK
JTAG_TRST*
JTAG_TDO
JTAG_TDI
JTAG_TMS
JTAG_TCK

TESTMODE

FUSE1_FSRC

TST_STPCLK
TST_CLKOUT

FAST_SCAN_CLK

HOLD_RESET

RESET*

CFSB

DDR0_CKEIN
DDR1_CKEIN

HSIC_VSS121

C25

F24

D24

HSIC_DVDD

7MA

HSIC_VDD122

17MA

HSIC_DVSS

HSIC_VSS122

E24

C24

C19

C20

C21

C18

PLL2_AVDD11

PLL1_AVDD11

PLL0_AVDD11

2.5MA EACH

SYM 1 OF 12

U0652

H4P-512MB

(FOR IC TESTER)

(0=NORMAL)

PLL2_AVSS11

PLL1_AVSS11

PLL0_AVSS11

D19

D20

D21

D18

PP1V1_PLL_USB_F

C17

C22

AR10

PLL3_AVDD11

PLL4_AVDD11

PLL_USB_AVDD11

2.5MA

MIPI0D_VDD11_PLL

6.5MA

BGA

USB_ANALOGTEST

PLL_USB_AVSS11

PLL4_AVSS11

PLL3_AVSS11

MIPI_VSS_0

D17

D22

AN10

PART#

VOLTAGE=1.1V

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

1

C0652

0.01UF

10%

6.3V

2

X5R
01005

PP1V1_MIPID_PLL_F

1

C0661

56PF

5%

6.3V

2

NP0-C0G
01005

C28

H27

H28

AT14

USB_DVDD

5MA

USB_VDD330

28MA

MIPI1D_VDD11_PLL

WDOG

XI0

XO0

USB11_DP
USB11_DM

USB_DP
USB_DM

USB_VBUS

USB_ID

USB_BRICKID

USB_REXT

USB_VSSAC

USB_VSSA0

USB_DVSS

MIPI_VSS_1

D28

H26

J26

AN11

36

DESCRIPTION

QTY

VOLTAGE=1.1V

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

1

C0654

0.1UF

10%

6.3V

2

X5R
201

1

C0627

0.01UF

10%

6.3V

2

X5R
01005

P30

A18

A19

A22
A23

A29
A28

G26

XTAL_24M_I

39

XTAL_24M_O

39

NC_USB_ANALOGTEST

F27

F28

NC_USB_ID

G27

A21

USB_REXT

NOTE:
PAGE 4608
H4P UM V0.83

R0625

0.00

1 2

0%

1/32W

MF

01005

USB_FS_D_P
USB_FS_D_N

USB_D_P
USB_D_N

1

R0642

44.2

1%
1/20W
MF
201

2

FL0610

80-OHM-0.2A-0.4-OHM

1 2

C0655

1UF

10%

6.3V
CERM
402

C0640

1UF

10%

6.3V
CERM
402

0201-1

1

2

1

2

1

2

RST_PMU_IN

11 39

BI

11 39

BI

28 39

BI

28 39

BI

2 1

REFERENCE DESIGNATOR(S)

=PP3V3_USB_H4

C0630

0.01UF

10%

6.3V
X5R
01005

OUT

R0655

1.00M

1% MF

01005

1 2

USB_AP_VBUS

2

DZ0600

GDZT2R5.1B

GDZ-0201

1

SYNC_MASTER=JAMES

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

CRITICAL BOM OPTION

=PP1V1_USB_H4

=PP1V1_MIPI_PLL_H4

=PP1V1_USB_H4

4

32

35

1/32W

R0640

22

1 2

5%

1/32W

MF

01005

R

4

32

4

32

24M_O

39

1

2

R0651

100K

1 2

5%

1/32W

MF

01005

USB_BRICKID

AP: MAIN

Apple Inc.

32

CRITICAL

Y0602

SM-2

24.000MHZ-16PF-60PPM

1 3

C0613

22PF

5%
16V
CERM
01005

2 4

PPVBUS_USB

OUT

TABLE_5_HEAD

34

35

DRAWING NUMBER

051-8962

REVISION

BRANCH

PAGE

SHEET

1

C0607

22PF

5%
16V

2

CERM
01005

SYNC_DATE=N/A

A.0.0

6 OF 106

4 OF 42

SIZE

D

C

B

A

D

345678

2 1

=PP3V0_OPTICAL

=PP1V8_H4

4 7

10 13 32

I2C0_SDA_1V8

5

10 19 35 39

I2C0_SCL_1V8

5

10 19 35 39

I2C1_SDA_1V8

5

25 39

I2C1_SCL_1V8

5

D

25 39

I2C2_SDA_3V0

5

25 26 39

I2C2_SCL_3V0

5

25 26 39

1

R0700

4.7K

5%
1/32W
MF
01005

2

1

R0701

4.7K

5%
1/32W
MF
01005 01005

2

1

R0702

4.7K

5%
1/32W
MF

2

26 27 32

1

R0703

4.7K

5%
1/32W
MF
01005

2

1

R0704

1.8K

5%
1/32W
MF
01005

2

1

R0705

1.8K

5%
1/32W
MF
01005

2

=PP1V8_S2R_MISC

5

28 32

=PP1V8_ALWAYS

32

=PP1V8_S2R_MISC

5

28 32

(SCREEN ROTATION LOCK)

5

29 35

5

25 35

5

25 35

C

HOME_L

ONOFF_L

SRL_L

R0771

220K

1 2

5%

1/20W

MF

201

R0770

220K

1 2

5%

1/20W

MF

201

R0765

220K

1 2

5%

1/20W

MF

201

HOME_L

5

29 35

IN

ONOFF_L

5

25 35

IN

PM_BT_WAKE

30

OUT

PM_RADIO_ON

5

31

OUT

RST_DET_L

31

IN

SPI_IPC_SRDY

31

IN

IRQ_PMU_L

35

IN

IRQ_CODEC_L

19

IN

IRQ_GYRO_INT2

5

25

OUT

BOOT_CONFIG_0

10

IN

PM_KEEPACT

5

35

OUT

IRQ_GRAPE_HOST_INT_L

18

OUT

GPS_SYNC

31

OUT

GSM_TXBURST_IND

31

IN

BOOT_CONFIG_1

10

IN

FORCE_DFU

5

37

IN

DFU_STATUS

5

OUT

BOOT_CONFIG_2

10

IN

BOOT_CONFIG_3

10

IN

RST_GPS_L

31

OUT

PM_GPS_STANDBY_L

31

OUT

IRQ_PROX_INT_L

25

OUT

IRQ_GYRO_INT1

25

IN

IRQ_GPS_INT_L

31

IN

TP_IRQ_COMPASS_INT_L
IRQ_ACCEL_INT1_L

25

IN

IRQ_ALS_INT_L

26

IN

IRQ_ACCEL_INT2_L

25

IN

AUD_SPKRAMP_MUTE_L

20

OUT

PORT_DOCK_VIDEO_AMP_EN

11

OUT

NC_AP_GPIO2
NC_AP_GPIO3
NC_AP_GPIO4
NC_AP_GPIO5
NC_AP_GPIO6

NC_AP_GPIO8

NC_AP_GPIO10

NC_AP_GPIO14

NC_BOARD_ID_3

NC_AP_GPIO20

NC_AP_GPIO22

NC_GPIO_218

AA3
AA4
AA5
AA6
AA7
AB3
AB4
AB5
AC7
AC4
AD7
AC3
AD6
AD5
AD4
AD3
AE7
AD1
AE1
AE4
AE3
AE2
AF4
AF3
AF7
AF2
AG7
AG6
AG5
AG4
AG3
AG1
AH1
AH2
AH7
AH3
AH4
AJ5
AJ4
AJ3

U30
V30

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39

GPIO_3V0
GPIO_3V1

U0652

H4P-512MB

BGA

SC58940X01-A030

SYM 2 OF 12

1.8V

1.8V/3.0V
GROUP 0

GROUP 1

VSS

A1A2A3A6A7A8A9

EHCI_PORT_PWR0
EHCI_PORT_PWR1
EHCI_PORT_PWR2

TMR32_PWM0
TMR32_PWM1
TMR32_PWM2

3.0V

UART1_CTSN
UART1_RTSN

UART2_CTSN
UART2_RTSN

UART3_CTSN
UART3_RTSN

UART4_CTSN
UART4_RTSN

UART5_RTXD

UART6_CTSN
UART6_RTSN

A10

A11

A12

UART0_RXD
UART0_TXD

UART1_RXD
UART1_TXD

UART2_RXD
UART2_TXD

UART3_RXD
UART3_TXD

UART4_RXD
UART4_TXD

UART6_RXD
UART6_TXD

AL7
AL6
AM6

AC30
AA27
AB30

R31
R30

AN4
AM5
AM3
AM1

AP4
AM2
AM4
AN5

AP1
AR2
AR4
AP2

AU1
AT3
AT4
AT1

AR3

AU2
AN3
AU3
AP3

AP_GPIO40_BRD_REV0
AP_GPIO41_BRD_REV1
AP_GPIO42_BRD_REV2

NC_AP_GPIO185
NC_AP_GPIO186
NC_AP_GPIO187

UART_0_RXD
UART_0_TXD

UART_1_CTS_L
UART_1_RTS_L

UART_1_RXD
UART_1_TXD

SRL_L

RST_BB_L
UART_2_RXD
UART_2_TXD

UART_3_CTS_L
UART_3_RTS_L

UART_3_RXD
UART_3_TXD

UART_4_CTS_L
UART_4_RTS_L

UART_4_RXD
UART_4_TXD

BATTERY_SWI

AUD_VOL_DOWN_L

IPC_GPIO

AUD_VOL_UP_L
TP_PROX_GPIO

10

IN

10

IN

10

IN

D

10

IN

10

OUT

10

IN

10

OUT

10

IN

10

OUT

5

25 35

IN

31

OUT

10

IN

10

OUT

10

IN

10

OUT

10

IN

10

OUT

10

IN

10

OUT

10

IN

10

OUT

33 35

OUT

25

IN

31

IN

25

IN

TO DOCK MUX

TO BB USART

TO BB UMTS

TO BT UART

TO GPS UART

C

PM_KEEPACT

R0720

33.2

1%

1/32W

MF

01005

1 2

I2S_AP_0_MCK_R

19 39

OUT

CODEC ASP

B

BB (NOT USED)

CODEC VSP & BT

CODEC XSP

19 39

OUT

19 39

OUT

19 39

IN

19 39

OUT

19 30

OUT

39
19 30

OUT

39
19 30

IN

39
19 30

OUT

39

19 39

OUT

19 39

OUT

19 39

IN

19 39

OUT

I2S_AP_0_BCLK
I2S_AP_0_LRCK
I2S_AP_0_DIN
I2S_AP_0_DOUT

NC_I2S_AP_1_MCK
NC_I2S_AP_1_BCLK
NC_I2S_AP_1_LRCK
NC_I2S_AP_1_DIN
NC_I2S_AP_1_DOUT

NC_I2S_AP_2_MCK
I2S_AP_2_BCLK
I2S_AP_2_LRCK
I2S_AP_2_DIN
I2S_AP_2_DOUT

NC_I2S_AP_3_MCK
I2S_AP_3_BCLK
I2S_AP_3_LRCK
I2S_AP_3_DIN
I2S_AP_3_DOUT

I2S_AP_0_MCK

NC_AP_GPIO216

BOARD_ID_2_SPI_FLASH_DOUT

10

IN

BOARD_ID_1_SPI_FLASH_DIN

10

IN

BOARD_ID_0_SPI_FLASH_CLK

10

IN

TO GRAPE

A

TO BB

NC_SPI_FLASH_CS_L

17 40

IN

17 40

OUT

17 40

OUT

17 40

OUT

31 40

IN

31 40

OUT

31 40

IN

31 40

OUT

SPI_GRAPE_MISO
SPI_GRAPE_MOSI
SPI_GRAPE_SCLK
SPI_GRAPE_CS_L

SPI_IPC_MISO
SPI_IPC_MOSI
SPI_IPC_SCLK
SPI_IPC_MRDY

8 7 5 4 2 1

AB33

AC34
AA32

AC33
AD32

AC32

AE29
AG34
AE31
AE32

AH32
AF28
AG32
AF31

AF34
AG33
AE27
AE28

Y32

Y31

Y34
W34

V33
V32
U34
U32
V31

T31
W32
U31
T30
W29

W31

I2S0_MCK
I2S0_BCLK
I2S0_LRCK
I2S0_DIN
I2S0_DOUT

I2S1_MCK
I2S1_BCLK
I2S1_LRCK
I2S1_DIN
I2S1_DOUT

I2S2_MCK
I2S2_BCLK
I2S2_LRCK
I2S2_DIN
I2S2_DOUT

I2S3_MCK
I2S3_BCLK
I2S3_LRCK
I2S3_DIN
I2S3_DOUT

SPDIF

SPI0_MISO
SPI0_MOSI
SPI0_SCLK
SPI0_SSIN

SPI1_MISO
SPI1_MOSI
SPI1_SCLK
SPI1_SSIN

SPI2_MISO
SPI2_MOSI
SPI2_SCLK
SPI2_SSIN

U0652

H4P-512MB

BGA

SC58940X01-A030

SYM 3 OF 12

DUAL-WIRE INTF

GROUP 6

1.8V/3.0V
GROUP 5

VSS

A13

A14

A15

A16

A17

A20

GROUP 7

FOR PMU

A30

A33

SDIO0_CLK

SDIO0_CMD
SDIO0_DATA0
SDIO0_DATA1
SDIO0_DATA2
SDIO0_DATA3

SPI3_MISO

SPI3_MOSI

SPI3_SCLK

SPI3_SSIN

A34

AA9

I2C0_SCL
I2C0_SDA

I2C1_SCL
I2C1_SDA

I2C2_SCL
I2C2_SDA

SWI_DATA

DWI_CLK

DWI_DI
DWI_DO

AD26
AD29

AD31
AE30

AF30
AF29

AA30

AB34
AA31
Y27

AB27
AC26
AB31
AD30
AB26
AB32

AH31
AH29
AH30
AG30

I2C0_SCL_1V8
I2C0_SDA_1V8

I2C1_SCL_1V8
I2C1_SDA_1V8

I2C2_SCL_3V0
I2C2_SDA_3V0

NC_SWI_AP

DWI_AP_CLK
DWI_AP_DI
DWI_AP_DO

SDIO_WL_CLK

SDIO_WL_CMD
SDIO_WL_DATA<0>
SDIO_WL_DATA<1>
SDIO_WL_DATA<2>
SDIO_WL_DATA<3>

NC_SPI_AP_3_MISO
NC_SPI_AP_3_MOSI
NC_SPI_AP_3_SCLK
NC_SPI_AP_3_CS_L

1

R0735

5

10 19 35 39

BI

5

10 19 35 39

OUT

5

25 39

BI

5

25 39

OUT

5

25 26 39

BI

5

25 26 39

OUT

35 39

OUT

35 39

IN

35 39

OUT

30 40

OUT

30 40

OUT

30 40

BI

30 40

BI

30 40

BI

30 40

BI

TO WIFI

100K

2

1

R0736

100K

5%
1/20W
MF
201

5%
1/32W

01005

2

SYNC_MASTER=JAMES

PAGE TITLE

1

R0737

100K

5%
1/20W
MFMF
201

2

1

R0738

100K

5%
1/20W
MF
201

2

AP: I/Os

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

36

IRQ_GYRO_INT2

FORCE_DFU

DFU_STATUS

PM_RADIO_ON

1

R0739

100K

5%
1/20W
MF
201

2

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

5

35

5

25

5

37

5

5

31

SYNC_DATE=N/A

051-8962

A.0.0

7 OF 106

5 OF 42

SIZE

B

A

D

345678

=PPIO_NAND_H4

6 9

10

J21
J23
J25
J27
J28
J29
J30

K1

D

C

B

A

K3

K5
K7

K8
K10
K12
K14
K16
K18
K20
K22
K24
K26
K30
K31
K32

L1

L2

L3

L4

L7

L9
L11
L13
L15
L17
L19
L21
L23
L25
L28
L29
L30
L31
L32
L33

M1

M3

VSS VSS

M5

M7

M8
M10
M12
M14
M16
M18
M20
M22
M24
M26
M29
M33

N1

N2

N3

N4

N7

N9
N11
N13
N15
N17
N19
N21
N23
N25
N27
N28

P1

P2

P3

P5

P7

P8
P10
P12
P14
P16
P18
P20
P22
P24
P26

R1

U0652

H4P-512MB

BGA

SYM 12 OF 12

SC58940X01-A030

R3
R4
R9
R11
R13
R15
R17
R19
R21
R23
R25
R27
R29
R34
T1
T2
T3
T5
T7
T8
T10
T12
T14
T16
T18
T20
T22
T24
T26
T29
T33
U1
U3
U4
U7
U9
U11
U13
U15
U17
U19
U21
U23
U25
U27
U28
V1
V2
V3
V5
V7
V8
V10
V12
V14
V16
V18
V20
V22
V24
V26
V28
V34
W1
W2
W3
W4
W7
W9
W11
W13
W15
W17
W19
W21
W23
W25
W27
Y3
Y5
Y7
Y8
Y10
Y12
Y14
Y16
Y18
Y20
Y22
Y24
Y29
Y30

F1CE0_L

6

12 39

F1CE1_L

6

12 39

F1CE2_L

6

12 39

F1CE3_L

6

12 39

F0CE0_L

6

12 39

F0CE1_L

6

12 39

F0CE2_L

6

12 39

F0CE3_L

6

12 39

=PPIO_NAND_H4

6 9

10

F1CE4_L

6

12 39

F1CE5_L

6

12 39

F1CE6_L

6

12 39

F1CE7_L

6

12 39

F0CE4_L

6

12 39

F0CE5_L

6

12 39

F0CE6_L

6

12 39

F0CE7_L

6

12 39

H4P-512MB

F0CE0_L

6

12 39

OUT

F0CE1_L

6

12 39

OUT

F0CE2_L

6

12 39

OUT

F0CE3_L

6

12 39

OUT

F0CE4_L

6

12 39

OUT

F0CE5_L

6

12 39

OUT

F0CE6_L

6

12 39

OUT

F0CE7_L

6

12 39

OUT

F0AD<0>

12 39

BI

F0AD<1>

12 39

BI

F0AD<2>

12 39

BI

F0AD<3>

12 39

BI

F0AD<4>

12 39

BI

F0AD<5>

12 39

BI

F0AD<6>

12 39

BI

F0AD<7>

12 39

BI

F0ALE

6

12 39

OUT

F0CLE

6

12 39

OUT

F0WE_L

6

12 39

OUT

F0RE_L

6

12 39

OUT

F1CE0_L

6

12 39

OUT

F1CE1_L

6

12 39

OUT

F1CE2_L

6

12 39

OUT

F1CE3_L

6

12 39

OUT

F1CE4_L

6

12 39

OUT

F1CE5_L

6

12 39

OUT

F1CE6_L

6

12 39

OUT

F1CE7_L

6

12 39

OUT

F1AD<0>

12 39

BI

F1AD<1>

12 39

BI

F1AD<2>

12 39

BI

F1AD<3>

12 39

BI

F1AD<4>

12 39

BI

F1AD<5>

12 39

BI

F1AD<6>

12 39

BI

F1AD<7>

12 39

BI

F1ALE

6

12 39

OUT

F1CLE

6

12 39

OUT

F1WE_L

6

12 39

OUT

F1RE_L

6

12 39

OUT

NC_AP_GPIO76

NC_AP_GPIO93

AV20
AW21
AU19
AU20
AV31
AT31
AV32
AU30

AV18
AU18
AT22
AW19
AV21
AU22
AY21
AR20

AT20
AU21
AT19
AV22
AT21

AN22
AY19
AP20
AT18
AN30
AU34
AU33
AP30

AV25
AU23
AW25
AU25
AU24
AV24
AT23
AV23

AP23
AV19
AN23
AN21
AY25

FMI0_CEN0
FMI0_CEN1
FMI0_CEN2
FMI0_CEN3
FMI0_CEN4
FMI0_CEN5
FMI0_CEN6
FMI0_CEN7

FMI0_IO0
FMI0_IO1
FMI0_IO2
FMI0_IO3
FMI0_IO4
FMI0_IO5
FMI0_IO6
FMI0_IO7

FMI0_ALE
FMI0_CLE
FMI0_WEN
FMI0_REN
FMI0_DQS

FMI1_CEN0
FMI1_CEN1
FMI1_CEN2
FMI1_CEN3
FMI1_CEN4
FMI1_CEN5
FMI1_CEN6
FMI1_CEN7

FMI1_IO0
FMI1_IO1
FMI1_IO2
FMI1_IO3
FMI1_IO4
FMI1_IO5
FMI1_IO6
FMI1_IO7

FMI1_ALE
FMI1_CLE
FMI1_WEN
FMI1_REN
FMI1_DQS

AA11

AA13

U0652

SYM 4 OF 12

GROUP 3

3.3V

GROUP 2

GROUP 3

3.3V

GROUP 2

AA15

AA17

AA19

VSS

AA21

R0832

1

100K

5%
1/32W
MF
01005

2

R0860

1

100K

5%
1/32W
MF
01005

2

GROUP 2GROUP 2

GROUP 5

GROUP 4

GROUP 5

AA23

AA25

GROUP 2GROUP 2

GROUP 4

AA29

R0836

1

100K

5%
1/32W
MF
01005

2

R0861

1

100K

5%
1/32W
MF
01005

2

BGA

AB1

AB6

FMI2_CEN0
FMI2_CEN1
FMI2_CEN2
FMI2_CEN3
FMI2_CEN4
FMI2_CEN5
FMI2_CEN6
FMI2_CEN7

FMI2_IO0
FMI2_IO1
FMI2_IO2
FMI2_IO3
FMI2_IO4
FMI2_IO5
FMI2_IO6
FMI2_IO7

FMI2_ALE
FMI2_CLE
FMI2_WEN
FMI2_REN
FMI2_DQS

FMI3_CEN0
FMI3_CEN1
FMI3_CEN2
FMI3_CEN3
FMI3_CEN4
FMI3_CEN5
FMI3_CEN6
FMI3_CEN7

FMI3_IO0
FMI3_IO1
FMI3_IO2
FMI3_IO3
FMI3_IO4
FMI3_IO5
FMI3_IO6
FMI3_IO7

FMI3_ALE
FMI3_CLE
FMI3_WEN
FMI3_REN
FMI3_DQS

AB8

R0833

1

100K

5%
1/32W
MF
01005

2

R0862

1

100K

5%
1/32W
MF
01005

2

AY26
AU26
AW26
AV26
AP34
AL32
AK31
AM32

AY29
AR30
AU29
AV28
AY28
AW30
AW28
AU28

AW27
AU27
AV27
AY27
AV30

AT30
AP31
AU31
AU32
AN34
AM33
AM34
AN33

AP33
AL31
AR34
AN32
AM31
AN31
AR32
AP32

AT32
AT34
AT33
AR31
AR33

R0828

1

100K

5%
1/32W
MF
01005

2

R0863

1

100K

5%
1/32W
MF
01005

2

R0831

1

100K

5%
1/32W
MF
01005

2

R0864

1

100K

5%
1/32W
MF
01005

2

NC_F2CE0_L
NC_F2CE1_L
NC_F2CE2_L
NC_F2CE3_L

GRAPE_FW_DNLD_EN_L

NC_F2AD<0>
NC_F2AD<1>
NC_F2AD<2>
NC_F2AD<3>
NC_F2AD<4>
NC_F2AD<5>
NC_F2AD<6>
NC_F2AD<7>

NC_F2ALE
NC_F2CLE
NC_F2WE_L
NC_F2RE_L

NC_AP_GPIO_110

NC_F3CE0_L
NC_F3CE1_L
NC_F3CE2_L
NC_F3CE3_L

NC_AP_GPIO_147

NC_F3AD<0>
NC_F3AD<1>
NC_F3AD<2>
NC_F3AD<3>
NC_F3AD<4>
NC_F3AD<5>
NC_F3AD<6>
NC_F3AD<7>

NC_F3ALE
NC_F3CLE
NC_F3WE_L
NC_F3RE_L

NC_AP_GPIO_135

8 7 5 4 2 1

R0825

R0834

1

1

100K

100K

5%

5%

1/32W

1/32W

MF

MF

01005

01005

2

2

R0866

R0865

1

1

100K

100K

5%

5%

1/32W

1/32W
MF

MF
01005

01005

2

2

TP_GPIO_SD_CTRL

RST_GRAPE_L

R0827

1

100K

5%
1/32W
MF
01005

2

R0867

1

100K

5%
1/32W
MF
01005

2

17

OUT

17

OUT

TP_RST_SD_CTRL_L

TP_CD_SD_CTRL_L

36

10

RST_MLC_L

1

R0878

100K

5%
1/32W
MF
01005

2

PM_MLC_PWR_EN

=PPIO_NAND_H4

6 9

F0WE_L

6

12 39

F0RE_L

6

12 39

F1WE_L

6

12 39

F1RE_L

6

12 39

F0ALE

6

12 39

F0CLE

6

12 39

F1ALE

6

12 39

F1CLE

6

12 39

OUT

OUT

2 1

R0800

R0801

1

1

100K

100K

5%

5%

1/32W

1/32W

MF

MF

01005

2

14

36

SYNC_MASTER=JAMES

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

01005

2

R0810

1

100K

5%
1/32W
MF

2

AP: NAND

Apple Inc.

R

R0811

1

100K

5%
1/32W
MF
0100501005

2

R0802

1

100K

5%
1/32W
MF
01005

2

R0812

1

100K

5%
1/32W
MF
01005

2

R0803

1

100K

5%
1/32W
MF
01005

2

R0813

1

100K

5%
1/32W
MF
01005

2

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

8 OF 106

SHEET

6 OF 42

SIZE

D

C

B

A

D

345678

MIN_NECK_MIDTH SHOULD BE 0.2MM

=PP3V0_IO_H4

9

32

D

=PP3V0_VIDEO_H4

7

32

1

2

240-OHM-0.2A-0.8-OHM

=PP3V0_VIDEO_H4

7

32

C

0.1UF

6.3V

1

10%

2

X5R
201

C0956

DAC_AP_VREF

R0950

6.34K

1/20W

1 2

201

C0951

1UF

10%

6.3V
CERM
402

FL0910

0201

DAC_AP_IREF

1

1%
MF

2

1

C0952

0.01UF

10%

6.3V

2

X5R
01005

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

DAC_AP_COMP_FTR

TP_DP_AP_ANALOG_TEST

NOTE: 0.6V ANALOG REF

AP_DP_R_BIAS

0.01UF

6.3V

01005

1

10%

2

X5R

C0950

NOSTUFF

1

C0955

0.1UF

10%

6.3V

2

X5R
201

DAC_AP_COMP

1

R0920

4.99K

1%
1/32W
MF
01005

2

1

2

J34

K34

H33

H34

C0954

0.01UF

10%

6.3V
X5R
01005

L27

DAC_AVDD30A

6MA

21MA

DAC_VREF

DAC_IREF

DAC_COMP

DP_PAD_DC_TP

DP_PAD_R_BIAS

DAC_AVSS30A

DAC_AVSS30A

M27

K27

K29

DAC_AVDD30D

<= 5MA

SC58940X01-A030

DAC_AVSS30D

K28

B

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

PP_AP_DP_AVDD_AUX

10

PP_DP_PAD_AVDD0

PP_DP_PAD_AVDD1

E29

D30

H31

DP_PAD_AVDD0

DP_PAD_AVDD1

63MA 63MA

DP_PAD_AVDD_AUX

SYM 6 OF 12

U0652

H4P-512MB

BGA

DP_PAD_AVSS_AUX

DP_PAD_AVSS1

DP_PAD_AVSS0

D29

C30

G31

1

C0927

0.22UF

20%

6.3V

2

X5R
402

D31

DP_PAD_AVDDP0

5MA

2MA

DP_PAD_AUXP
DP_PAD_AUXN

DP_PAD_TX0P
DP_PAD_TX0N

DP_PAD_TX1P
DP_PAD_TX1N

DP_PAD_AVSSP0

C31

H32

1

2

10

10

G32

J31

DP_PAD_DVDD

DP_PAD_AVDDX

1.2MA

DAC_OUT3
DAC_OUT2
DAC_OUT1

DP_HPD

DP_PAD_AVSSX

DP_PAD_DVSS

J32

L34J33
M34
N34

1

2

C0926

0.22UF

20%

6.3V
X5R X5R
402

R32

G34
F34

D34
C34

A32
A31

1

R0955

200

1%
1/20W
MF
201

2

C0925

0.22UF

20%

6.3V
402

1

2

1

R0956

200

2

1

C0924

56PF

5%

6.3V

2

NP0-C0G
01005

=PP1V1_DPORT_H4

C0909

0.1UF

10%

6.3V
X5R
201

1

R0957

200

1%
1/20W
MF
201

2

R0910

0

1 2

5%

1/20W

MF

201

32

DAC_AP_OUT3
DAC_AP_OUT2
DAC_AP_OUT1

DP_AP_HPD

DP_AP_AUX_P
DP_AP_AUX_N

DP_AP_TX_P<0>
DP_AP_TX_N<0>

DP_AP_TX_P<1>
DP_AP_TX_N<1>

1%
1/20W

NOTE: PLACE R0955-57 NEAR U0652

MF
201

1

C0923

56PF

5%

6.3V

2

NP0-C0G
01005

OUT
OUT
OUT

OUT
OUT

OUT
OUT

IN

BI
BI

=PP1V8_DPORT_H4

11

YIN

40
11

CVBSIN

40
11

CIN

40

13

13 40

13 40

10 13 40

10 13 40

10 13 40

10 13 40

32

REAR CAMERA

=PP1V1_MIPI_H4

32

1

2

27 40

IN

27 40

IN

27 40

OUT

27 40

OUT

14 40

OUT

14 40

OUT

14 40

OUT

14 40

OUT

14 40

OUT

14 40

OUT

14 40

OUT

14 40

OUT

14 40

OUT

14 40

OUT

1

C0930

1UF

10%

6.3V
CERM
402

MIPI0C_AP_DATA_P<0>
MIPI0C_AP_DATA_N<0>

MIPI0C_AP_CLK_P
MIPI0C_AP_CLK_N

MIPID_AP_DATA_P<0>
MIPID_AP_DATA_N<0>

MIPID_AP_DATA_P<1>
MIPID_AP_DATA_N<1>

MIPID_AP_DATA_P<2>
MIPID_AP_DATA_N<2>

MIPID_AP_DATA_P<3>
MIPID_AP_DATA_N<3>

MIPID_AP_CLK_P
MIPID_AP_CLK_N

C0908

0.1UF

10%

6.3V

2

X5R

201

NC_AP_GPIO184

NC_MIPI0C_AP_DATA_P<1>
NC_MIPI0C_AP_DATA_N<1>

NC_MIPI0C_AP_DATA_P<2>
NC_MIPI0C_AP_DATA_N<2>

NC_MIPI0C_AP_DATA_P<3>
NC_MIPI0C_AP_DATA_N<3>

1

C0903

0.1UF

10%

6.3V

2

X5R
201

AA26

AW10
AY10

AW11
AY11

AW13
AY13

AW14
AY14

AW12
AY12

AW5
AY5

AW6
AY6

AW8
AY8

AW9
AY9

AW7
AY7

32

=PP1V8_MIPI_H4

AP10

MIPI_VSYNC

MIPI0C_DPDATA0
MIPI0C_DNDATA0

MIPI0C_DPDATA1
MIPI0C_DNDATA1

MIPI0C_DPDATA2
MIPI0C_DNDATA2

MIPI0C_DPDATA3
MIPI0C_DNDATA3

MIPI0C_DPCLK
MIPI0C_DNCLK

MIPI0D_DPDATA0
MIPI0D_DNDATA0

MIPI0D_DPDATA1
MIPI0D_DNDATA1

MIPI0D_DPDATA2
MIPI0D_DNDATA2

MIPI0D_DPDATA3
MIPI0D_DNDATA3

MIPI0D_DPCLK
MIPI0D_DNCLK

1

C0907

0.1UF

10%

6.3V

2

X5R
201

AP11

AP13

AP14

AP15

MIPI_VDD11

28MA

SC58940X01-A030

AP16

AP17

AP18

AR12

2MA ???

SYM 5 OF 12

GROUP 5

U0652

H4P-512MB

BGA

MIPI_VSS

AN13

AN15

MIPI0D_VDD18

MIPI1D_VDD18

VOLTAGE=0.4V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

VOLTAGE=0.4V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

PP_AP_MIPI1D_0P4V

AR11

AR15

MIPI0D_VREG_0P4V

MIPI1D_VREG_0P4V

ISP0_FLASH

ISP0_PRE_FLASH

ISP0_SCL
ISP0_SDA

ISP1_FLASH

ISP1_PRE_FLASH

ISP1_SCL
ISP1_SDA

SENSOR0_CLK
SENSOR0_RST

SENSOR1_CLK
SENSOR1_RST

MIPI1C_DPDATA0
MIPI1C_DNDATA0

MIPI1C_DPDATA1
MIPI1C_DNDATA1

MIPI1C_DPCLK
MIPI1C_DNCLK

PP_AP_MIPI0D_0P4V

2 1

=PP1V8_H4

4 5

AG31
AG29
AE26
AC29

AJ32
AG28
AC31
AF27

AA33
Y26

AA34
Y33

AW15
AY15

AW17

NC_MIPI1C_AP_DATA_P<1>

AY17

NC_MIPI1C_AP_DATA_N<1>

AW16
AY16

10 13 32

ISP_AP_0_SCL

7

25 39

ISP_AP_0_SDA

7

25 39

ISP_AP_1_SCL

7

26 39

ISP_AP_1_SDA

7

26 39

1

C0902

2.2NF

10%
10V

2

X5R
201

1

C0920

2.2NF

10%
10V

2

X5R
201

NC_AP_GPIO153
NC_AP_GPIO152

ISP_AP_0_SCL
ISP_AP_0_SDA

NC_AP_GPIO155
NC_AP_GPIO154

ISP_AP_1_SCL
ISP_AP_1_SDA

CLK_CAM_RF_R

CLK_CAM_FF_R

MIPI1C_AP_DATA_P<0>
MIPI1C_AP_DATA_N<0>

MIPI1C_AP_CLK_P
MIPI1C_AP_CLK_N

OUT

OUT

22

22

1

R0930

4.7K

5%
1/32W
MF
01005

2

7

BI

7

BI

1 2

1 2

7

7

R0900

R0940

25 39

25 39

26 39

26 39

PM_REAR_CAM_SHUTDOWN

PM_FRONT_CAM_SHUTDOWN

26 40

IN

26 40

IN

26 40

OUT

26 40

OUT

1

R0931

4.7K

5%
1/32W
MF
01005

2

REAR CAMERA

FRONT CAMERA

CLK_CAM_RF

CLK_CAM_FF

FRONT CAMERA

1

R0932

1.00K

5%
1/32W
MF
01005

2

OUT
OUT

OUT
OUT

27 39

25

26 39

26

1

R0933

1.00K

5%
1/32W
MF
01005

2

D

C

B

AN12

AP12

AR14

AR16

AR17

AR18

A

SYNC_MASTER=JAMES

PAGE TITLE

AP: TV,DP,MIPI

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

9 OF 106

SHEET

7 OF 42

SIZE

A

D

345678

2 1

=PP1V2_S2R_H4

1

R1005

2.21K

1%
1/32W
MF
01005

2

1

R1006

2.21K

1%

=PP1V2_VDDQ_H4

8

32

1/32W
MF
01005

2

1

R1053

1.00K

1%
1/32W
MF
01005

2

1

R1054

1.00K

1%
1/32W
MF
01005

2

D

8

32

PPVREF_DDR0_CA

NOSTUFF

1

C1002

0.01UF

10%

6.3V

2

X5R

01005

PPVREF_DDR0_DQ

NOSTUFF

1

C1054

0.01UF

10%

6.3V

2

X5R

01005

8

39

VOLTAGE=0.6V

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=VREF
MAX_NECK_LENGTH=3 MM

8

39

VOLTAGE=0.6V

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=VREF
MAX_NECK_LENGTH=3 MM

C

C1008

10UF

=PP1V8_S2R_H4

32

B

=PP1V2_VDDQ_H4

8

32

A

C1027

56PF

6.3V

NP0-C0G

01005

NOSTUFF

1

5%

2

8 7 5 4 2 1

20%

6.3V
X5R
603

C1014

C1023

10UF

8

32

8

32

=PP1V2_S2R_H4

8

32

1

2

10UF

20%

6.3V
X5R
603

20%

6.3V
X5R
603

=PP1V2_S2R_H4

1

R1051

2.21K

1%
1/32W
MF
01005

2

1

R1052

2.21K

1%
1/32W
MF
01005

2

=PP1V2_VDDQ_H4

1

R1055

1.00K

1%
1/32W
MF
01005

2

1

R1056

1.00K

1%
1/32W
MF
01005

2

(DDR IMPEDANCE CONTROL)

1

C1009

4.3UF

20%

4V

2

X5R-CERM

0610

1

C1015

1UF

2

1

2

6.3V
CERM

C1019

0.22UF

6.3V
0201

C1024

4.3UF

X5R-CERM

C1029

0.22UF

6.3V
0201

C1004

0.22UF

C1010

1

10%

2

402

1

20%

2

X5R

20%

4V

0610

20%
X5R

PPVREF_DDR1_CA

NOSTUFF

1

C1052

0.01UF

10%

6.3V

2

X5R

01005

PPVREF_DDR1_DQ

NOSTUFF

1

C1056

0.01UF

10%

6.3V

2

X5R

01005

1

20%

6.3V
2

X5R

0201

1

1UF

10%

6.3V
2

CERM

402

C1016

0.22UF

1

2

C1030

1

0.22UF

2

8

VOLTAGE=0.6V

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=VREF
MAX_NECK_LENGTH=3 MM

8

VOLTAGE=0.6V

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=VREF
MAX_NECK_LENGTH=3 MM

1

C1005

0.22UF

20%

6.3V
2

X5R

0201

1

C1011

1UF

10%

6.3V
2

CERM

402

1

1UF

10%

6.3V
2

CERM

402

C1020

1

20%

6.3V

2

X5R

0201

C1031

1

0.22UF

20%

6.3V

2

X5R

0201

39

39

R1001

1 2

1 2

R1000

C1006

0.22UF

C1012

0.01UF

C1017

0.01UF

C1021

0.22UF

20%

6.3V
X5R

0201

240

240

6.3V

01005

0201

6.3V
0201

10%
X5R

20%
X5R

20%
X5R

10%
10V
X5R
201

1

2

8

32

1%

1/20WMF201

1/20W1%201

1

0.22UF

2

1

2

1

0.01UF

2

1

2

C1026

0.01UF

=PP1V2_S2R_H4

C1000

0.22UF

20%

6.3V
X5R

0201

PPVREF_DDR0_CA

8

39

PPVREF_DDR1_CA

8

39

PPVREF_DDR1_DQ

8

39

PPVREF_DDR0_DQ

8

39

MF

C1007

1

20%

6.3V

2

X5R

0201

1

C1013

56PF

5%

6.3V
2

NP0-C0G

01005

NOSTUFF

1

C1018

10%

6.3V
2

X5R

01005

1

C1022

56PF

5%

6.3V6.3V

2

NP0-C0G

01005

NOSTUFF

1

10%

6.3V
2

X5R

01005

1

2

C1001

0.22UF

6.3V
0201

DDR0_ZQ
DDR1_ZQ

=PP1V2_VDDIOD_H4

32

1

C1032

10UF

20%

6.3V
2

X5R
603

1

20%

2

X5R

H11

DDR0_VDDQ_CKE

R8

DDR1_VDDQ_CKE

AY23

DDR0_VREF_CA

AE34

DDR1_VREF_CA

AA1

DDR1_VREF_DQ

A25

DDR0_VREF_DQ

AY18

DDR0_ZQ

AK34

DDR1_ZQ

AD33
AH33
AW20
AW24

VDDCA

80MA

AW29

W33

A24

AA2
AF33
AK33

AL1
AW22
AW31

VDD2

B4

320MA

B5
B25
F33
T34

Y1

A4

A5
AB2
AL2

AL33
AW18

VDD1

AW32

40MA

B26
E33
U33

AC2
AG2
AK2
AN2
AT2
AW3

B3

B6

B8
B11
B14
B16
B19
B21
B24
B27

VDDQ

B31

500MA

(VDDQ = VDDIOD: DON’T DOUBLE COUNT)

D2
D33

G2
G33

K2
K33

M2
N33

R2
R33

U2

Y2

U0652

BGA

H4P-512MB

<1MA
<1MA

SYM 7 OF 12

SC58940X01-A030

VSS_32
VSS_33

VSS_34
VSS_35

VSS_36
VSS_37

VSS_38
VSS_39

VSS

VSS

VSS

VSS

AB10
AB12

AB14
AB16

AB18
AB20

AB22
AB24

AB29
AC1
AC5
AC9
AC11
AC13

AC15
AC17
AC19
AC21
AC23
AC25
AC27
AD2
AD8
AD10
AD12
AD14
AD16

AD18
AD20
AD22
AD24
AD27
AD34
AE5
AE9
AE11
AE13

AE15
AE17
AE19
AE21
AE23
AE25
AE33
AF1
AF5
AF8
AF10
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF32
AG9
AG11
AG13
AG15
AG17
AG19
AG21
AG23
AG25

C1036

0.22UF

6.3V
0201

1

20%

2

X5R

C1037

0.22UF

20%

6.3V
X5R

0201

=PP1V8_VDDIO18_H4

9

32

C1041

56PF

NP0-C0G

01005

NOSTUFF

C1044

0.22UF

6.3V
0201

6.3V

20%
X5R

1

2

5%

C1038

0.22UF

1

2

1

2

20%

6.3V
X5R

0201

C1042

0.22UF

C1045

0.22UF

6.3V
0201

1

2

0201

20%
X5R

C1034

4.3UF

X5R-CERM

0.22UF

20%
X5R

1

2

20%

4V

0610

C1039

6.3V
0201

1

2

1

2

20%
X5R

C1043

C1046

1

2

1UF

6.3V6.3V
CERM

1UF

6.3V
CERM

C1035

0.22UF

C1040

56PF

NP0-C0G

01005

NOSTUFF

1

10%

2

402

1

10%

2

402

6.3V
0201

6.3V

1

20%

2

X5R

1

5%

2

SYNC_MASTER=JAMES

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D4
D6

D8
D10
D12
D14

E5

E7

E9
E11
E13
E15

F4

F6

F7

F8

F9
F10
F11
F12
F13
F14
F15
F16
F17
F18

G5

G6

VDDIOD

H4

500MA

H6

(VDDQ = VDDIOD: DON’T DOUBLE COUNT)

J5

J6

K4

K6

L5

L6

M4

M6

N5

N6

P4

P6

R5

R6

T4

T6

U5

U6

V4

V6

W5

W6

Y4

Y6

AA28

AB7

AB28

AC6

AC28
AD28

AE6
AF6
AH6
AN6

VDDIO18

AN7
AN8
H23
P28
R28
T28
W28
Y28

Apple Inc.

R

U0652

H4P-512MB

BGA

SYM 9 OF 12

SC58940X01-A030

44MA

AP: PWR

AM16
AM18
AM20
AM22
AM24
AM26
AM28
AM29
AM30
AN1
AN14
AN16
AN17
AN18
AN19
AN20
AN24
AN25
AN26
AN27
AN28
AN29
AP5
AP6
AP7
AP8
AP9
AP19

VSS

AP21
AP22
AR1
AR5
AR6
AR7
AR8
AR9
AR13
AR19
AR24
AR25
AR26
AR27
AR28
AR29
AT5
AT6
AT7
AT8
AT9
AT10
AT11
AT12
AT13
AT15

AT16
AT17
AT24
AT25
AT26
AT27
AT28
AT29
AU4
AU5

VSS

AU6
AU7
AU8
AU9
AU10
AU11
AU12
AU13

DRAWING NUMBER

051-8962

REVISION

BRANCH

PAGE

10 OF 106

SHEET

SYNC_DATE=N/A

A.0.0

8 OF 42

SIZE

D

C

B

A

D

36

345678

=PPVDD_SOC_H4

32

1

C1100

4.3UF

20%

4V

2

X5R-CERM

0610

NOSTUFF

D

C1108

1

0.22UF

20%

6.3V
2

X5R

0201

C1112

0.22UF

20%

6.3V
X5R

0201

C1117

C

0.22UF

6.3V
0201

C1121

4.3UF

X5R-CERM

1

20%

2

X5R

1

20%

4V

2

0610

C1104

56PF

NP0-C0G

1

2

0.22UF

5%

6.3V

01005

C1109

0.22UF

C1113

0.22UF

C1118

6.3V
0201

6.3V
0201

20%
X5R

1

2

6.3V
0201

20%
X5R

20%
X5R

C1101

10UF

NOSTUFF

C1105

56PF

NP0-C0G

1

2

1

2

1

2

20%

6.3V
X5R
603

5%

6.3V

01005

C1110

0.22UF

0.22UF

1

2

1

2

20%

6.3V
X5R

0201

C1114

20%

6.3V
X5R

0201

C1119

0.22UF

6.3V
0201

20%
X5R

C1102

4.3UF

X5R-CERM

0610

NOSTUFF

C1106

56PF

6.3V

NP0-C0G

01005

1

2

1

2

1

2

1

20%

4V

2

1

5%

2

0.22UF

C1115

0.22UF

C1120

0.22UF

C1111

20%

6.3V
X5R

0201

20%

6.3V
X5R

0201

B

A

8 7 5 4 2 1

C1103

4.3UF

X5R-CERM

NOSTUFF

C1107

NP0-C0G

20%

6.3V
X5R

0201

1

2

0610

56PF

6.3V

01005

1

2

1

2

1

20%

4V

2

1

5%

2

C1116

0.22UF

6.3V
0201

1

2

6

10

=PPVDD_CPU_H4

32

C1125

10UF

20%

6.3V
X5R
603

C1129

56PF

5%

6.3V

NP0-C0G

01005

C1133

0.22UF

20%

6.3V
X5R

0201

C1138

0.22UF

20%

6.3V
X5R

0201

=PPIO_NAND_H4

C1144

0.22UF

20%

6.3V
X5R

0201

=PP3V0_IO_H4

7 9

32

C1126

4.3UF

X5R-CERM

0610

C1130

56PF

6.3V

NP0-C0G

01005

C1134

0.22UF

6.3V
0201

C1139

0.22UF

6.3V
0201

C1145

0.22UF

6.3V
0201

1UF

10%

6.3V
CERM

402

1

20%

4V

2

1

5%

2

1

20%

2

X5R

1

20%

2

X5R

32

1

C1146

20%

2

X5R

NP0-C0G

NOSTUFF

1

C1181

1UF

10%

6.3V

2

CERM

402

1

C1127

4.3UF

20%

4V

2

X5R-CERM

0610

1

C1131

56PF

5%

6.3V

2

NP0-C0G

01005

1

C1135

0.22UF

20%

6.3V

2

X5R

0201

C1140

1

0.22UF

20%

6.3V

2

X5R

0201

32

=PP1V8_VDDIO18_H4

8

C1150

0.22UF

6.3V
0201

1

6.3V

1

2

5%

C1182

2

C1147

1UF

10%

6.3V
CERM

402

56PF

01005

C1136

=PP3V0_IO_H4

7 9

1

20%

2

X5R

1UF

10%

6.3V
CERM

402

1

2

1

2

1

2

1

2

1

2

1

2

C1180

C1128

4.3UF

X5R-CERM

0610

C1132

56PF

6.3V

NP0-C0G

01005

0.22UF

6.3V
0201

C1141

0.22UF

6.3V
0201

C1142

0.22UF

6.3V
0201

C1151

0.22UF

1

2

C1160

0.22UF

20%

4V

5%

20%
X5R

20%
X5R

20%
X5R

20%

6.3V
X5R

0201

C1148

1UF

6.3V
CERM

20%

6.3V
X5R

0201

1

2

1

2

1

2

1

2

C1143

1

2

1

2

1

10%

2

402

1

2

0.22UF

6.3V
0201

NOSTUFF

C1152

56PF

NP0-C0G

01005

C1149

10UF

C1161

0.22UF

20%
X5R

6.3V

6.3V

6.3V
0201

1

2

1

5%

2

1

20%

2

X5R
603

1

20%

2

X5R

AA20
AA22
AA24

AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB25

AC8
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AC24

1

20%

2

X5R

AD11
AD13
AD15
AD17
AD19
AD21
AD23
AD25

AE10
AE12
AE14
AE16
AE18
AE20
AE22
AE24

AF11
AF13
AF15
AF17
AF19
AF21
AF23
AF25

AG10
AG12
AG14
AG16
AG18
AG20
AG22
AG24
AG26

AH11
AH13
AH15
AH17
AH19
AH21
AH23
AH25

AJ10
AJ12
AJ14
AJ16
AJ18
AJ20
AJ22
AJ24
AJ26

AK11
AK13
AK15
AK17
AK19
AK21
AK23
AK25

AL10
AL12
AL14
AL16
AL18

AD9

AE8

AF9

AG8

AH9

AJ8

AK9

AL8

U0652

H4P-512MB

BGA

SYM 10 OF 12

SC58940X01-A030

2100MA

AL20
AL22
AL24
AL26
AM9
AM11
AM13
AM15
AM17
AM19
AM21
AM23
AM25
H9
H13
H15
H17
H19
H21
J8
J10
J12
J14
J16
J18
J20
J22
J24
K9
K11
K13
K15
K17
K19
K21
K23
K25
L8
L10
L12
L14
L16
L18
L20
L22
L24
L26
M9
M11

VDDVDD

M13
M15
M17
M19
M21
M23
M25
N20
N22
N24
N26
P19
P21
P23
P25
P27
R20
R22
R24
R26
T19
T21
T23
T25
T27
U20
U22
U24
U26
V19
V21
V23
V25
V27
W20
W22
W24
W26
Y19
Y21
Y23
Y25

C1137

0.22UF

6.3V
0201

20%
X5R

36

2 1

AA8
AA10
AA12
AA14
AA16
AA18

N8
N10
N12
N14
N16
N18

P9
P11
P13
P15
P17
R10
R12
R14
R16
R18

T9
T11
T13
T15

VDD_CPU

T17

1900MA

U8
U10
U12
U14
U16
U18

V9
V11
V13
V15
V17

W8
W10
W12
W14
W16
W18

Y9
Y11
Y13
Y15
Y17

G23
G24
U29

VDDIO30

V29

AJ7
AK7

VDDIOD0

AN9

VDDIOD1

10MA

AP24
AP25
AP26
AP27
AP28

VDDIOD2

AR21

24MA

AR22
AR23

AP29

VDDIOD3
AL27
AM27

VDDIOD4
AJ27

AK27

VDDIOD5
AH27

VDDIOD6
AG27

VDDIOD7

SYNC_MASTER=JAMES

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

U0652

H4P-512MB

BGA

SYM 8 OF 12

SC58940X01-A030

100MA

GPIO[30-39]

9MA

24MA

24MA

24MA

1.8V

UART4

1.8V

FMI[0-2]

3.3V

FMI[0-1]_CEN[4-7]

3.3V

FMI[3]

3.3V

FMI[2-3]_CEN[4-7]
SPI3,ISP FLASH
NOT USED

SPI1

1MA
1MA

I2C2

AP: PWR

Apple Inc.

R

VSS

VSS

VSS

VSS

VSS

3.0V

AH5
AH8
AH10
AH12
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH34
AJ1
AJ2
AJ6
AJ9
AJ11
AJ13
AJ15
AJ17
AJ19
AJ21
AJ23
AJ25
AJ28
AJ29
AJ30
AJ31
AJ33
AJ34
AK1
AK3
AK4
AK5
AK6
AK8
AK10
AK12
AK14
AK16
AK18
AK20
AK22
AK24
AK26
AK28
AK29
AK30

AK32
AL3
AL4
AL5

AL9
AL11

AL13

AL15
AL17
AL19
AL21
AL23
AL25
AL28
AL29

AL30

AL34
AM7

AM8
AM10

AM12
AM14

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

11 OF 106

SHEET

9 OF 42

SIZE

D

C

B

A

D

345678

2 1

D

C

BOOT CONFIG ID

BOOT_CONFIG[3] (GPIO29)

BOOT_CONFIG[2] (GPIO28)

BOOT_CONFIG[1] (GPIO25)

BOOT_CONFIG[0] (GPIO18)

BOARD ID

BOARD_ID[3]

BOARD_ID[2]

BOARD_ID[1]

BOARD_ID[0]

BOARD REVISION

AP_GPIO42_BRD_REV2

5

AP_GPIO41_BRD_REV1

5

AP_GPIO40_BRD_REV0

5

=PP1V8_H4

4 5 7

10 13 32

BOOT_CONFIG_3

5

BOOT_CONFIG_2

5

BOOT_CONFIG_1

5

BOOT_CONFIG_0

5

BOOT_CONFIG[3-0]

FMI0/1 4/4 CS

1101
1110

FMI0/1 4/4 CS WITH TEST

=PP1V8_H4

4 5 7

10 13 32

BOARD_ID_3

BOARD_ID_2_SPI_FLASH_DOUT

5

BOARD_ID_1_SPI_FLASH_DIN

5

BOARD_ID_0_SPI_FLASH_CLK

5

BOARD_ID[3-0]

K93 AP

0100
0101

K93 DEV

0110

K94 AP

0111

K94 DEV
K95 AP

0010
0011

K95 DEV

1

R1207

10K

5%
1/20W
MF
201

2

1

R1208

10K

5%
1/20W
MF
201

2

1

R1200

10K

5%
1/20W
MF
201

2

1. SET GPIO AS INPUT

2. DISABLE PU AND ENABLE PD

3. READ

K93-K94

1

R1204

10K

5%
1/32W
MF
01005

2

S/W READ FLOW

1. SET GPIO AS INPUT

2. DISABLE PU AND ENABLE PD

3. READ

NOSTUFF

1

R1209

10K

5%
1/20W
MF
201

2

K94-K95

1

R1205

10K

5%
1/32W
MF
01005

2

1

R1201

10K

5%
1/20W
MF
201

2

S/W READ FLOW

K9X_DEV

1

R1206

10K

5%
1/32W
MF
01005

2

FMI_TEST

1

R1202

10K

5%
1/20W
MF
201

2

FMI_NOTEST

1

R1203

10K

5%
1/32W
MF
01005

2

SIGNAL_MODEL=EMPTY
NOSTUFF

1

R1250

150

5%
1/20W
MF
201

2

DP_TERM_C1250

1

2

PLACEMENT NOTE: NEAR U0652

SIGNAL_MODEL=EMPTY
NOSTUFF

1

R1251

150

5%
1/20W
MF
201

2

SIGNAL_MODEL=EMPTY
NOSTUFF

C1250

100PF

5%

25V
CERM

201

DP_AP_TX_P<1>

SIGNAL_MODEL=EMPTY
NOSTUFF

1

R1252

150

5%
1/20W
MF
201

2

DP_TERM_C1251

1

2

DP_AP_TX_P<0>
DP_AP_TX_N<0>

DP_AP_TX_N<1>

SIGNAL_MODEL=EMPTY
NOSTUFF

1

R1253

150

5%
1/20W
MF
201

2

SIGNAL_MODEL=EMPTY
NOSTUFF

C1251

100PF

5%
25V
CERM
201

JTAG

DEVELOPMENT_JTAG_TAP

R1212

0.00

JTAG_DAP

R1210

100

1 2

AP_JTAG_SEL

JTAG_DAP

R1211

100

1 2

7

13 40

OUT

7

13 40

OUT

7

13 40

OUT

7

13 40

OUT

JTAG_AP_TRST_L

2-WIRE DAP

DEVELOPMENT_JTAG
JTAG_DAP

39

IN

4

OUT

JTAG_AP_TDI

4

39

OUT

4

10 39

OUT

JTAG_AP_TRST_L

4

10 39

OUT

SCAN DUMP

DEVELOPMENT_JTAG
DEVELOPMENT_JTAG_TAP

PP_AP_DP_AVDD_AUX

7

MAKE_BASE=TRUE

=PPIO_NAND_H4

6 9

R1260

100

1 2

5%

1/32W

MF

01005

SHORT-01005

NOSTUFF

XW0601

NOSTUFF

XW0602

NOSTUFF

XW0603

1 2

SHORT-01005

1 2

SHORT-01005

1 2

JTAG_AP_TDO

4

1 2

0%

1/32W

MF

01005

DEVELOPMENT_JTAG_TAP

R1213

0.00

1 2

0%

1/32W

MF

01005

DEVELOPMENT_JTAG_TAP

R1214

0.00

1 2

0%

1/32W

MF

01005

PRODUCTION

JTAG_DAP

PP_DP_PAD_AVDD0

PP_DP_PAD_AVDD1

=PP3V3_NAND_H4

AP_TESTMODE

AP_TST_STPCLK

AP_FAST_SCAN_CLK

AP_HOLD_RESET

VIDEO_EMI_C_Y

VIDEO_EMI_Y_PR

VIDEO_EMI_CVBS_PB

7

7

32

4

4

4

4

11 28 40

OUT

11 28 40

IN

11 28 40

IN

D

C

BRD_REV[2-0]

PROTO 1

B

000
001

011

PROTO 2
EVT010
EVT2
DVT100

FOR REFERENCE

BOOT_CONFIG[3:0]

0000 SPI0
0001 SPI3
0010 SPI0 W/TEST
0011 SPI3 W/TEST
0100 FMI0 2CS
0101 FMI0 4CS
0110 FMI0 4CS W/TEST
0111 RESERVED
1000 FMI1 2 CS
1001 FMI1 4 CS
1010 FMI1 4CS W/TEST

1011 RESERVED
1100 FMI0/1 2/2 CS

CURRENT SETTING ->

1101 FMI0/1 4/4 CS
1110 FMI0/1 4/4 CS W/TEST
1111 RESERVED

A

8 7 5 4 2 1

S/W READ FLOW

1. SET GPIO AS INPUT

2. ENABLE PU AND DISABLE PD

3. READ

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

23

23

UART_0_RXD
UART_0_TXD

UART_1_CTS_L
UART_1_RTS_L

UART_1_RXD
UART_1_TXD

UART_2_RXD
UART_2_TXD

UART_3_CTS_L
UART_3_RTS_L

UART_3_RXD
UART_3_TXD

UART_4_CTS_L
UART_4_RTS_L

UART_4_RXD
UART_4_TXD

CHS_SCL
CHS_SDA

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

UART_AP_0_RXD
UART_AP_0_TXD

UART_AP_1_CTS_L
UART_AP_1_RTS_L

UART_AP_1_RXD
UART_AP_1_TXD

UART_AP_2_RXD
UART_AP_2_TXD

UART_AP_3_CTS_L
UART_AP_3_RTS_L

UART_AP_3_RXD
UART_AP_3_TXD

UART_AP_4_CTS_L
UART_AP_4_RTS_L

UART_AP_4_RXD
UART_AP_4_TXD

I2C0_SCL_1V8
I2C0_SDA_1V8

SYNC_MASTER=JAMES

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

11

IN

11

OUT

31

IN

31

OUT

31

IN

31

OUT

31

IN

31

OUT

30

IN

30

OUT

30

IN

30

OUT

31

IN

31

OUT

31

IN

31

OUT

5

19 35 39

IN

5

19 35 39

OUT

TO DOCK MUX

TO BB USART

TO BB UMTS

TO BT UART

TO GPS UART

AP: MISC & ALIASES

Apple Inc.

R

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

12 OF 106

SHEET

10 OF 42

SIZE

B

A

D

36

345678

2 1

D

NOTE:

LDO3 PROVIDES 50MA TO BOTH H4P AND U1300
IF THAT’S NOT ENOUGH, STUFF R1371 AND NOSTUFF R1370

=PP3V0_VIDEO_BUF

32

=PP3V0_VIDEO_BUFFER

32

C

YIN

CVBSIN

CIN

R1371

0.00

1 2

0%

1/32W

MF

01005

NOSTUFF

R1370

0.00

1 2

0%

1/32W

MF

01005

7

40

IN

7

40

IN

7

40

IN

UART_AP_0_TXD

10

IN

UART_AP_0_RXD

OUT

USB_BB_D_P

31 39

BI

USB_BB_D_N USB_FS_D_N

31 39

BI

DAC_AP_OUT3
DAC_AP_OUT2
DAC_AP_OUT1

VOLTAGE=3.0V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

~15MA

PP3V0_U0900_FILTR

1

C1370

0.1UF

10%

6.3V

2

X5R
201

C1301

C1

C4E2D2

VDH

VDL

VA_1

VA_0

U1300

THS7380IZSYR

UCSP

A3 A2

CH.1_IN

A4 A1

CH.2_IN

B4 B1

CH.3_IN

D4

TX_VLOW

E4

RX_VLOW

F3

USB_D+

F4

USB_D-

RX_VHIGH/USB_2D+
TX_VHIGH/USB_2D-

B2

B3

DGNDAGND

D3

CH.1_OUT
CH.2_OUT
CH.3_OUT

E3

VID_EN

USB_1D+
USB_1D-

SEL

1

56PF

5%

6.3V

2

NP0-C0G

01005

PORT_DOCK_VIDEO_AMP_EN

C3

E1
D1

F2
F1

C2

40

40

40

C1300

0.1UF

10%

6.3V
X5R
201

BUF_Y_PR
BUF_CVBS_PB
BUF_C_Y

=PP3V2_S2R_USBMUX

1

2

1

R1372

100K

5%

1/32W

MF

01005

2

USB_FS_P_ACC_RX
USB_FS_N_ACC_TX

USB_FS_D_P

DOCK_BB_EN

1

R1320

100K

5%
1/32W
MF
01005

2

NOTE:
DOCK_BB_EN = 1:
DOCK_BB_EN = 0:

32

5

IN

4

BI

4

BI

35

IN

BB USB <-> DOCK SERIAL
BB USB <-> H4P FS USB
H4P UART0 <-> DOCK SERIAL

NOTE: PLACE R0960-62 NEAR U0900

JTAG_DAP

R1360

75

1 2

1%

1/20W

MF

201

JTAG_DAP

R1361

75

1 2

1%

1/20W

MF

28 39

OUT

28 39 10

39

39

IN

1

R1315

1.00M

5%
1/32W
MF
01005

2

201

JTAG_DAP

R1362

75

1 2

1%

1/20W

MF

201

VIDEO_EMI_Y_PR

VIDEO_EMI_CVBS_PB

VIDEO_EMI_C_Y

10 28 40

OUT

10 28 40

OUT

10 28 40

OUT

B

D

C

B

A

SYNC_MASTER=JAMES

PAGE TITLE

AP: VIDEO BUFFER,BB USB MUXES

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

13 OF 106

SHEET

11 OF 42

SIZE

A

D

345678

2 1

QTY

PART#

335S0701

PART NUMBER

335S0682 335S0701

335S0790

D

335S0781 335S0701

DESCRIPTION

TOSHIBA 32NM 16GB RAW

1

ALTERNATE FOR
PART NUMBER

335S0701

BOM OPTION

16GB_PROD

16GB_PROD

16GB_PROD

REFERENCE DESIGNATOR(S)

U1400

REF DES

COMMENTS:

SAMSUNG 35NM 16GB RAW

U1400

SAMSUNG 27NM 16GB RAW

U1400

HYNIX 26NM 16GB PPN

U1400

BOM OPTION

16GB_PROD

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

32GB FLASH CONFIGURATIONS

1

C1403

82PF

5%

25V

2

CERM

0201

1

C1400

0.1UF

10%

2

X5R
201

1

C1401

0.1UF

10%

6.3V6.3V

2

X5R
201

=PP3V3_NAND

1

C1402

2.2UF

20%

6.3V

2

CERM
402-LF

PART#

335S0701

PART NUMBER

335S0790

12 32

QTY

DESCRIPTION

TOSHIBA 32NM 16GB RAW

2

ALTERNATE FOR
PART NUMBER

335S0701335S0682

335S0701

335S0701335S0781

BOM OPTION

32GB_PROD

32GB_PROD

32GB_PROD

REFERENCE DESIGNATOR(S)

U1400,U1410

REF DES

COMMENTS:

SAMSUNG 35NM 16GB RAW

U1400,U1410

SAMSUNG 27NM 16GB RAW

U1400,U1410

HYNIX 26NM 16GB PPN

U1400,U1410

BOM OPTION

32GB_PROD

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

C

B6M6N1

OA8
OB8

OC0
OC8
OD0
OD8
OF0
OF8

G3
G1
H2
J1
J3
L1
K2
N3
L5
N5

K6
L7
J5
J7
H6
G7

A7

IO0_0

IO0_1

IO1_0

IO1_1

IO2_0

IO2_1

IO3_0

IO3_1

IO4_0

IO4_1

IO5_0

IO5_1

IO6_0

IO6_1

IO7_0

IO7_1

INC

INC_VDDI

R

U1400

F0AD<0>

6

12 39

BI

F1AD<0>

6

12 39

BI

F0AD<1>

6

12 39

BI

F1AD<1>

6

12 39

BI

F0AD<2>

6

12 39

BI

F1AD<2>

6

12 39

BI

F0AD<3>

6

12 39

BI

F1AD<3>

6

12 39

BI

F0AD<4>

6

12 39

BI

F1AD<4>

6

12 39

BI

F0AD<5>

6

12 39

BI

F1AD<5>

6

12 39

BI

F0AD<6>

6

12 39

BI

F1AD<6>

6

12 39

BI

F0AD<7>

6

12 39

BI

F1AD<7>

6

12 39

BI

R1400

100K

B

1 2

1/20W

201

12

NAND0_RB

1%
MF

NAND0_VDDL

1

C1404

1UF

10%

6.3V

2

X5R
402

VSS

B2F6L3

OMIT

N7

VCC

VCCQ

C1

ALE0

D2

ALE1

A5

CE0*

LGA

VLGA5-N90

NAND-XXNM-64GX8

CE1*

CE2*
CE3*
CE4*

CE5*

CE6*
CE7*

CLE0
CLE1

RE0*
RE1*

R/B0*
R/B1*

WE0*

WE1*

C5
A1
OA0
G5
F2
OB0
OE0

A3
C3

C7
D6

E5
E7

E3
E1

VSSQ

M2

OE8

F0ALE
F1ALE

F0CE0_L
F1CE0_L
F0CE1_L
F1CE1_L
F0CE4_L
F1CE4_L
F0CE5_L
F1CE5_L

F0CLE
F1CLE

F0RE_L
F1RE_L

NAND0_RB

F0WE_L

F1WE_L

B6M6N1

OA8
OB8

OC0
OC8
OD0
OD8
OF0
OF8

G3
G1
H2
J1
J3
L1
K2
N3
L5
N5
K6
L7
J5
J7
H6
G7

A7

IO0_0

IO0_1

IO1_0

IO1_1

IO2_0

IO2_1

IO3_0

IO3_1

IO4_0

IO4_1

IO5_0

IO5_1

IO6_0

IO6_1

IO7_0

IO7_1

INC

INC_VDDI

R

U1410

6

12 39

IN

6

12 39

IN

6

39

IN

6

39

IN

6

39

IN

6

39

IN

6

39

IN

6

39

IN

6

39

IN

6

39

IN

6

12 39

IN

6

12 39

IN

6

12 39

IN

6

12 39

IN

12

6

12 39

IN

6

12 39

IN

12 39

12 39

12 39

12 39

12 39

12 39

12 39

12 39

12 39

12 39

12 39

12 39

12 39

12 39

12 39

12 39

F0AD<0>

6

BI

F1AD<0>

6

BI

F0AD<1>

6

BI

F1AD<1>

6

BI

F0AD<2>

6

BI

F1AD<2>

6

BI

F0AD<3>

6

BI

F1AD<3>

6

BI

F0AD<4>

6

BI

F1AD<4>

6

BI

F0AD<5>

6

BI

F1AD<5>

6

BI

F0AD<6>

6

BI

F1AD<6>

6

BI

F0AD<7>

6

BI

F1AD<7>

6

BI

R1401

100K

1 2

1%

1/20W

MF

201

12

NAND1_RB
NAND1_VDDL

1

C1414

1UF

10%

6.3V

2

X5R
402

VSS

B2F6L3

64GB FLASH CONFIGURATIONS16GB FLASH CONFIGURATIONS

QTY

PART#

335S0702

PART NUMBER

335S0665 335S0702

335S0791

335S0722

335S0782 335S0702

1

C1413

82PF

5%
25V

2

CERM
0201

OMIT

N7

VCC

VCCQ

C1

ALE0

D2

ALE1

A5

CE0*

LGA

VLGA5-N90

NAND-XXNM-64GX8

M2

VSSQ

OE8

CE1*

CE2*
CE3*
CE4*

CE5*

CE6*
CE7*

CLE0
CLE1

RE0*
RE1*

R/B0*
R/B1*

WE0*

WE1*

C5
A1
OA0
G5
F2
OB0
OE0

A3
C3

C7
D6

E5
E7

E3
E1

DESCRIPTION

2

TOSHIBA 32NM 32GB RAW

ALTERNATE FOR
PART NUMBER

335S0702

335S0702

1

C1410

0.1UF

10%

6.3V

2

X5R
201

F0ALE
F1ALE

F0CE2_L
F1CE2_L
F0CE3_L
F1CE3_L
F0CE6_L
F1CE6_L
F0CE7_L
F1CE7_L

F0CLE
F1CLE

F0RE_L
F1RE_L

NAND1_RB

F0WE_L
F1WE_L

BOM OPTION

64GB_PROD

64GB_PROD

64GB_PROD

64GB_PROD

1

2

12

C1411

0.1UF

10%

6.3V
X5R
201

IN
IN

IN
IN
IN
IN
IN
IN
IN
IN

IN
IN

IN
IN

IN
IN

REFERENCE DESIGNATOR(S)

REF DES

U1400,U1410

U1400,U1410

U1400,U1410

U1400,U1410

1

2

6

12 39

6

12 39

6

39

6

39

6

39

6

39

6

39

6

39

6

39

6

39

6

12 39

6

12 39

6

12 39

6

12 39

6

12 39

6

12 39

U1400,U1410

COMMENTS:

SAMSUNG 35NM 32GB RAW

SAMSUNG 27NM 32GB RAW

SANDISK 32NM 32GB RAW

HYNIX 26NM 32GB PPN

=PP3V3_NAND

C1412

2.2UF

20%

6.3V
CERM
402-LF

BOM OPTION

64GB_PROD

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

12 32

TABLE_5_HEAD

TABLE_5_ITEM

D

C

B

A

SYNC_MASTER=JONATHAN

PAGE TITLE

NAND

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

14 OF 106

SHEET

12 OF 42

SIZE

A

D

345678

2 1

D

D

DISPLAYPORT AC COUPLING

10 40

10 40

10 40

10 40

40

40

7

IN

7

IN

7

IN

7

IN

7

BI

7

BI

DP_AP_TX_P<0>

DP_AP_TX_N<0>

DP_AP_TX_P<1>

DP_AP_TX_N<1>

DP_AP_AUX_P

DP_AP_AUX_N

C1702
C1703
C1704
C1705

C1706
C1707

C

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

1 2

10% X5R

1 2

10% X5R

1 2

10% X5R

1 2

10% X5R

1 2

10% X5R

1 2

10% X5R

6.3V

6.3V

6.3V

6.3V

6.3V

6.3V

DP_EMI_TX_P<0>

201

DP_EMI_TX_N<0>

201

DP_EMI_TX_P<1>

201

DP_EMI_TX_N<1>

201

DP_EMI_AUX_P

201

DP_EMI_AUX_N

201

28 40

OUT

28 40

OUT

28 40

OUT

28 40

OUT

13 28 40

BI

13 28 40

BI

=PP3V0_IO_MISC

13 32

DP_EMI_AUX_N

13 28 40

DP_EMI_AUX_P

13 28 40

1

R1720

100K

1%
1/32W
MF
01005

2

1

R1723

100K

1%
1/32W
MF
01005

2

C

DISPLAYPORT HOT PLUG DETECT

=PP3V0_IO_MISC

13 32

1

=PP1V8_H4

4 5 7

10 32

B

R1750

0.00

0%

1/32W

MF

01005

28 35

IN

FW_ZENER_PWR

1 2

DP_BUF_HPD

NOSTUFF

1

R1751

10K

5%
1/32W
MF
01005

2

PART NUMBER

1

C1750

0.1UF

10%

6.3V

2

X5R
201

ALTERNATE FOR
PART NUMBER

311S0341311S0536

2

1

6

VCC

U1701

74LVC1G07

SOT886

GND

3

BOM OPTION

CRITICAL

YA

NCNC

4

5

REF DES

U1701

A

8 7 5 4 2 1

R1731

220K

5%
1/32W
MF
01005

2

COMMENTS:

RADAR:8481319

DP_AP_HPD

TABLE_ALT_HEAD

TABLE_ALT_ITEM

36

B

7

OUT

SIZE

A

D

SYNC_MASTER=JAMES

PAGE TITLE

VIDEO: DISPLAY PORT

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

17 OF 106

SHEET

13 OF 42

345678

2 1

MLC EEPROM:RAW APN 335S0661

WHEN WC_L IS LOW, CAN WRITE TO EEPROM
WHEN WC_L IS HIGH, CANNOT WRITE TO EEPROM

D

=PP3V3_MLC

14 16 32

1

1

C2016

82PF

5%
25V

2

CERM
0201

MIPID_AP_CLK_P

C

NOSTUFF

PP2000

P4MM

SM
PP

=PP3V3_MLC

14 16 32

MLC_2WC_L

FL2000

80-OHM-0.2A-0.4-OHM

1 2

0201-1

FL2001

80-OHM-0.2A-0.4-OHM

1 2

0201-1

FL2002

80-OHM-0.2A-0.4-OHM

1 2

0201-1

7

14 40

R2006

10K

1/20W

1%
MF

201

C2010

4.7UF

X5R-CERM

REF DES

TABLE_5_HEAD

TABLE_5_ITEM

COMMENTS:

RADAR:8377307

D

TABLE_ALT_HEAD

TABLE_ALT_ITEM

C

PART#

341S2799

1

C2017

0.1UF

20%
10V

2

CERM
402

1

3

2

2
1
7

6 5

PP3V3_MLC_LVDS

PP3V3_MLC_18LDO_12LDO

PP3V3_MLC_DIG_12LDO

1

1

C2013

6.3V

20%

402

0.1UF

20%
10V

2

2

CERM
402 402

OMIT

VCC

U2001

M24C64

EEPROM

MLP

E2
E1
E0
WC*

SDASCL

VSS

THM_P

984

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR

C2011

4.7UF

20%

6.3V

X5R-CERM

402

1

R2050

4.7K

5%

1/20W

MF

201

2

1

1

C2014

0.1UF

20% 20%
10V

2

2

CERM

R2051

4.7K

1/20W

1

5%
MF

201

2

C2012

4.7UF

6.3V

X5R-CERM

1

20%

2

402

MLC_MUX_SDA_3V3
MLC_MUX_SCL_3V3

1

C2015

0.1UF

10V

2

CERM
402

15

BI

15

IN

F3H8B4A2C6H4E5

D5

DESCRIPTION

QTY

MLC EEPROM 100MHZ LVDS,2MHZ SWI

1

REFERENCE DESIGNATOR(S)

U2001

PART NUMBER

138S0652 138S0618

CRITICAL BOM OPTION

CRITICAL

ALTERNATE FOR
PART NUMBER

100MHZ_PANEL

BOM OPTION

C2000,C2001,C2002,C2003,C2010,C2011,C2012,C3609,C3611,C3616

VOLTAGE=0.4V
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.1 MM
MAX_NECK_LENGTH=3 MM

NOSTUFF

PP2009

P4MM

SM

1

MIPID_AP_DATA_N<3>

PP

B

NOSTUFF

PP2011

P4MM

SM
PP

1

MIPID_AP_DATA_P<0>

A

7

14 40

7

14 40

=PP3V3_MLC

14 16 32

NOSTUFF

R2052

100K

1/20W

1

1%
MF

201

2

R2008

100K

1/20W

R2002

100K

1/20W

1

1%
MF

201

2

1

1%
MF

201

2

1

R2003

100K

1%
1/20W
MF
201

2

1

C2004

2.2NF

10%
10V

2

X5R
201

7

14 40

7

40

7

14 40

7

40

40

7

7

40

7

40

7

40

7

40

7

14 40

6

R2010

100K

NET_SPACING_TYPE=PWR

MLC_VREG_0V4

NC_MIPI_MLC_MASTER_CLK_P
NC_MIPI_MLC_MASTER_CLK_N

NC_MIPI_MLC_MASTER_DATA_P
NC_MIPI_MLC_MASTER_DATA_N

MIPID_AP_CLK_P

IN

MIPID_AP_CLK_N

IN

MIPID_AP_DATA_P<0>

IN

MIPID_AP_DATA_N<0>

IN

MIPID_AP_DATA_P<1>

IN

MIPID_AP_DATA_N<1>

IN

MIPID_AP_DATA_P<2>

IN

MIPID_AP_DATA_N<2>

IN

MIPID_AP_DATA_P<3>

IN

MIPID_AP_DATA_N<3>

IN

MLC_BIST
MLC_TEST

RST_MLC_L

IN

SWI_MLC

MLC_MONITOR0_PD

1

1%

1/20W

MF

201

2

NC_MLC_MONITOR1
NC_MLC_MONITOR2
NC_MLC_MONITOR3

B3

C1
C2

B1
B2

F1
F2

D1
D2

E1
E2

G1
G2

H1
H2

B7
B8

B5

H6

H5
G3
G4
G5

8 7 5 4 2 1

VDD33A_OSC

M_VREG_0P4V

M_DPCLK
M_DNCLK

M_DPDATA0
M_DNDATA0

S_DPCLK
S_DNCLK

S_DPDATA0
S_DNDATA0

S_DPDATA1
S_DNDATA1

S_DPDATA2
S_DNDATA2

S_DPDATA3
S_DNDATA3

BIST
TEST

RESET*

SWI

MONITOR0
MONITOR1
MONITOR2
MONITOR3

VSS12D_PLL

A3

VDD33A_18LDO

VDD33A_12LDO_1

VDD33A_12LDO_0

VDD33A_12LDO_2

U2000

FBGA1

S6T2MLC

VSS33A_18LDO

VSS33A_12LDO_0

VSS33A_12LDO_1

H3C4A1

VDD33P_LVDS

VDD33A_LVDS

VDD33D_LVDS

CAP_18LDO
CAP_12LDO_0
CAP_12LDO_1
CAP_12LDO_3
CAP_12LDO_5

MLC_SCL
MLC_SDA

EDID_SCL
EDID_SDA

TCLKP
TCLKN

ROUT_LVDS

VSYNC

MONITOR4
MONITOR5
MONITOR6

VSS33A_LVDS

VSS33D_LVDS

VSS33P_LVDS

D6F6E6

TAP
TAN

TBP
TBN

TCP
TCN

TDP
TDN

PWM
PPC

C3
E3
H7
A7
A4

A6
A5

A8
B6

C8
C7

G8
G7

F8
F7

E8
E7

D8
D7

C5

F5
D4
G6

F4
E4
D3

MLC_SCL_3V3
MLC_SDA_3V3

LVDS_DDC_CLK
LVDS_DDC_DATA

LVDS_CLK_P
LVDS_CLK_N

LVDS_DATA_P<0>
LVDS_DATA_N<0>

LVDS_DATA_P<1>
LVDS_DATA_N<1>

LVDS_DATA_P<2>
LVDS_DATA_N<2>

NC_LVDS_DATA_P<3>
NC_LVDS_DATA_N<3>

ROUT_LVDS

TP_MLC_VSYNC

TP_PM_LCD_BKLT_PWM

NC_MLC_MONITOR4
NC_MLC_MONITOR5
NC_MLC_MONITOR6

MLC_CAP_1V8LDO
MLC_CAP_1V2LDO_0
MLC_CAP_1V2LDO_1_3

15

OUT

15

BI

16

OUT

16

OUT

16 40

OUT

16 40

OUT

16 40

OUT

16 40

OUT

16 40

OUT

16 40

OUT

16 40

OUT

16 40

OUT

PM_MLC_PPC_OUT

MLC_CAP_1V2_LDO_5

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR

C2000

4.7UF

X5R-CERM

1

16

OUT

2

20%

6.3V
402

R2001

8.45K

1%
1/20W
MF
201

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR

1

2

C2001

4.7UF

6.3V

X5R-CERM

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.4 MM
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR

MIN_NECK_WIDTH=0.2 MM

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=PWR

B

1

20%

2

402

C2002

4.7UF

6.3V

X5R-CERM

1

20%

2

402

SYNC_MASTER=MIKE

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

1

C2003

4.7UF

20%

6.3V

2

X5R-CERM

402

VIDEO: MLC

Apple Inc.

R

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

20 OF 106

SHEET

14 OF 42

SIZE

A

D

36

345678

2 1

D

C

14

MLC_SDA_3V3
MLC_SCL_3V3

MLC_MUX_SDA_3V3
MLC_MUX_SCL_3V3

14 14

14

D

C

SIZE

B

A

D

B

A

8 7 5 4 2 1

36

SYNC_MASTER=MIKE

PAGE TITLE

VIDEO: MLC ALIASES

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

21 OF 106

SHEET

15 OF 42

LVDS CONNECTOR

345678

2 1

CRITICAL

D

=PP3V3_LCD

32

NOSTUFF

1

14

IN

=PP3V3_MLC

14 16 32

NOSTUFF

R2211

1/20W

PM_MLC_PPC_OUT

10K

201

1

G

R2210

10K

1%
1/20W
MF
201

2

D

3

Q2201

2N7002TXG

2

S

R2204

21.5K

1 2

1/20W

SOT-523-3

1%
MF

201

1

C2240

82PF

25V

2

CERM

1

1%
MF

2

0201

1

R2205

100K

1%
1/20W
MF
201

2

1

C2241

82PF

5%5%
25V

2

CERM
0201

LCDVDD_PWREN_L

1

R2203

39K

1%
1/20W
MF
201

2

R2250_1

R2250

0

1 2

5%

1/20W

MF

201

Q2200

SIA413DJ

SC70-6L

S

4 7

3

LCDVDD_PWREN_L_R

G

D

1

C2204

0.015UF

1 2

10%

6.3V
X5R

0201

C

SIA413DJ

MOSFET
CHANNEL
RDS(ON)
IMAX
VGS MAX

PART NUMBER

376S0961

B

376S0903 376S0796

155S0583 155S0460

ALTERNATE FOR
PART NUMBER

376S0796

BOM OPTION

REF DES

Q2200

Q2200

L2202,L2212,L2222,L2232,L5500,L5501,L5600,L5601,L5702,L5716

COMMENTS:

RADAR:8403895

RADAR:8403865

RADAR:8376383

SIA413DJ
P-TYPE
100MOHM @-1.5V
3 A
+/- 8V

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.30 MM

MIN_NECK_WIDTH=0.20 MM

PP3V3_S0_LCD_FERR

1

C2203

0.1UF

10%

6.3V

2

X5R
201

1

C2202

2

10UF

20%

6.3V
X5R
603

14 40

14 40

14 40

14 40

14 40

14

IN

14

IN

IN

14 40

IN

IN

IN

14 40

IN

IN

14 40

IN

IN

1

C2230

82PF

5%
25V

2

CERM
0201

14 16 32

LVDS_DDC_CLK

LVDS_DDC_DATA

LVDS_DATA_N<0>

LVDS_DATA_P<0>

LVDS_DATA_N<1>

LVDS_DATA_P<1>

LVDS_DATA_N<2>

LVDS_DATA_P<2>

LVDS_CLK_N

LVDS_CLK_P

=PP3V3_MLC

1

R2201

10K

5%
1/20W
MF
201

2

2 3

1

90-OHM-50MA

L2212

2 3

1

90-OHM-50MA

L2222

2 3

1

90-OHM-50MA

L2232

2 3

1

90-OHM-50MA

L2202

L2201

FERR-120-OHM-1.5A

1 2

0402

1

R2200

10K

5%
1/20W
MF
201

2

4

SYM_VER-2

TCM0605

4

SYM_VER-2

TCM0605

4

SYM_VER-2

TCM0605

4

SYM_VER-2

TCM0605

C2231

82PF

1 2

5%

25V
CERM
0201

C2200

1000PF

1 2

10%
16V
X7R
201

1

C2232

82PF

5%
25V

2

CERM
0201

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.30 MM

MIN_NECK_WIDTH=0.20 MM

C2206

1000PF

1 2

10%
16V
X7R
201

PP3V3_LCDVDD_SW_F

35

OUT

=PPLED_REG

32

35

35

35

35

35

35

CABLINE-CA CONNECTOR: 518S0787

NOTE: CONNECTOR ON PANEL IS FLIPPED

(LVDS DDC POWER)

BOARD_TEMP4

LVDS_DATA_CONN_N<0>

40

LVDS_DATA_CONN_P<0>

40

40

LVDS_DATA_CONN_N<1>

40

LVDS_DATA_CONN_P<1>

40

LVDS_DATA_CONN_N<2>

40

LVDS_DATA_CONN_P<2>

40

40

FERR-240-OHM-25%-300MA

IN
IN
IN
IN
IN
IN

35

L2200

1 2

LED_IO_6
LED_IO_5
LED_IO_4
LED_IO_3
LED_IO_2
LED_IO_1
BOARD_TEMP4_N

VOLTAGE=20.4V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

0402

1

C2233

100PF

5%
50V

2

CERM
402

LVDS_CLK_CONN_N
LVDS_CLK_CONN_P

NC_LCD_PGAMMA

PPLED_BACK_REG

1

C2220

820PF

10%
50V

2

CERM

402

CRITICAL

J2201

CABLINE-CA

F-RT-SM

32

41
40
39
38
37
36
35
34
33

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8

NC

7
6
5
4
3
2
1

31

D

C

B

NOSTUFF RESISTORS ARE THERE TO
INVESTIGATE POSSIBILITY OF REMOVING
THE CHOKE

A

SYNC_MASTER=ALEX

PAGE TITLE

VIDEO: LVDS CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

22 OF 106

SHEET

16 OF 42

SIZE

A

D

345678

2 1

PART#

DESCRIPTION

QTY

1

IC,ASIC,GROUNDHOG B0,120B BGA

D

CONNECTORS TO GRAPE FLEX

P/N 518S0817

41
39

MT_PANEL_OUT<36>

17

MT_PANEL_OUT<38>

17

MT_PANEL_IN<29>

18

MT_PANEL_IN<27>

18

MT_PANEL_IN<25>

18

MT_PANEL_IN<23>

C

18

MT_PANEL_IN<21>

18

MT_PANEL_IN<19>

18

MT_PANEL_IN<17>

18

MT_PANEL_IN<15>

18

MT_PANEL_IN<13>

18

MT_PANEL_IN<11>

18

MT_PANEL_IN<9>

18

MT_PANEL_IN<7>

18

MT_PANEL_IN<5>

18

MT_PANEL_IN<3>

18

MT_PANEL_IN<1>

18

MATES WITH LEFTMOST GRAPE FLEX TAIL

37
35
33
31
29
27
25
23
21
19
17
15
13
11

9
7
5
3
1

38
40

F-RT-SM

502250-8237

J3010

B

41
39

MT_PANEL_OUT<1>

17

MT_PANEL_OUT<3>

17

MT_PANEL_OUT<5>

17

MT_PANEL_OUT<7>

17

MT_PANEL_OUT<9>

17

MT_PANEL_OUT<11>

17

MT_PANEL_OUT<13>

17

MT_PANEL_OUT<15>

17

MT_PANEL_OUT<17>

17

MT_PANEL_OUT<19>

17

MT_PANEL_OUT<21>

17

MT_PANEL_OUT<23>

17

MT_PANEL_OUT<25>

17

MT_PANEL_OUT<27>

17

MT_PANEL_OUT<29>

17

MT_PANEL_OUT<31>

17

MT_PANEL_OUT<33>

17

MT_PANEL_OUT<35>

17

A

37
35
33
31
29
27
25
23
21
19
17
15
13
11

9
7
5
3
1

38
40

F-RT-SM

502250-8237

J3011

MATES WITH RIGHTMOST GRAPE FLEX TAIL

8 7 5 4 2 1

REFERENCE DESIGNATOR(S)

U3003

MT_PANEL_OUT<37>

36

MT_PANEL_OUT<39>

34
32

MT_PANEL_IN<28>

30

MT_PANEL_IN<26>

28

MT_PANEL_IN<24>

26

MT_PANEL_IN<22>

24

MT_PANEL_IN<20>

22

MT_PANEL_IN<18>

20

MT_PANEL_IN<16>

18

MT_PANEL_IN<14>

16

MT_PANEL_IN<12>

14

MT_PANEL_IN<10>

12

MT_PANEL_IN<8>

10

MT_PANEL_IN<6>

8

MT_PANEL_IN<4>

6

MT_PANEL_IN<2>

4

MT_PANEL_IN<0>

2

MT_PANEL_OUT<0>

36

MT_PANEL_OUT<2>

34

MT_PANEL_OUT<4>

32

MT_PANEL_OUT<6>

30

MT_PANEL_OUT<8>

28

MT_PANEL_OUT<10>

26

MT_PANEL_OUT<12>

24

MT_PANEL_OUT<14>

22

MT_PANEL_OUT<16>

20

MT_PANEL_OUT<18>

18

MT_PANEL_OUT<20>

16

MT_PANEL_OUT<22>

14

MT_PANEL_OUT<24>

12

MT_PANEL_OUT<26>

10

MT_PANEL_OUT<28>

8

MT_PANEL_OUT<30>

6

MT_PANEL_OUT<32>

4

MT_PANEL_OUT<34>

2

CRITICAL BOM OPTION

CRITICAL343S0525

17

17

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

BOOST CONVERTOR

MIN_LINE_WIDTH=0.2MM

PP18V_GRAPE

17

C3005

0.1UF

TABLE_5_HEAD

TABLE_5_ITEM

MUX_IN<0>
MUX_IN<1>

18

MUX_IN<2>

18

MUX_IN<3>

18

MUX_IN<4>

18

MUX_IN<5>

18

MUX_IN<6>

18

MUX_IN<7>

18

MUX_IN<8>

18

MUX_IN<9>

18

MUX_IN<10>

18

MUX_IN<11>

18

MUX_IN<12>

18

MUX_IN<13>

18

MUX_IN<14>

18

MUX_IN<15>

18

MUX_IN<16>

18

MUX_IN<17>

18

MUX_IN<18>

18

MUX_IN<19>

18

L3000

4.7UH-700MA-280MOHM

VR_BOOST_L

1 2

=PP3V0_GRAPE

17 18 32

CRITICAL

1

U3000

L

TPS61045

QFN-1

3

DO

NC

1

C3001

2.2UF

THRML

10%

6.3V

2

PAD

X5R
603

9

VIN

7

VLF

2

PGND

10%
25V
X5R
402

Z1_BON_L<0>

18

Z1_BON_L<1>

18

Z1_BON_L<2>

18

Z1_BON_L<3>

18

Z1_BON_L<4>

18

Z1_BON_L<5>

18

FB

CTRL

SW

GND

6

AGND_U3000

MIN_LINE_WIDTH=0.2MM

2

XW3000

SM

1

1

C3007

2

8

0.1UF

10%
25V
X5R
402

NC
NC
NC
NC

MIN_LINE_WIDTH=0.2MM

VR_BOOST_SW

C3009

1 2

0.1UF

VR_BOOST_FBK

4

5

PM_BOOST_EN

1

C3053

2

B1

MUX0

C1

MUX1

E1

MUX2

F2

MUX3

H1

MUX4

J1

MUX5

J2

MUX6

J3

MUX7

K4

MUX8

H5

MUX9

I5

MUX10

J8

MUX11

J9

MUX12

K8

MUX13

J10

MUX14

I10

MUX15

H10

MUX16

F11

MUX17

C11

MUX18

E10

MUX19

A11

MUX20

B4

MUX21

A5

MUX22

A2

MUX23

C7

BON_L0

A7

BON_L1

B7

BON_L2

B8

BON_L3

A8

BON_L4

C8

BON_L5

C6

NC

D3

NC

D4

NC

D5

NC

D6

NC

D8

NC

D9

NC

E4

NC

E8

NC

F4

NC

F5

NC

NC

F8

NC

F9

NC

G3

NC

G4

NC

G9

NC

H3

NC

H4

NC

H7

NC

H8

NC

H9

NC

J6

NC

K7

NC

10%
16V
X5R
402

0.1UF

1

10%
25V

2

X5R
402

GROUNDHOG

E9

F3

VDDH

U3003

BGA

CRITICAL

OMIT

B6

A6

VCC_DIG

GND

G7

G8

G6

MIN_NECK_MIDTH SHOULD BE 0.4MM

D3000

SOD-323

1 2

B0520WSXG

C3008

33PF

NP0-C0G
201

18

5%

25V

1

2

F6F7G5

NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=18V

PP18V_R_GRAPE

R3009

1

2

C3002

470PF

10%
16V
X5R-X7R
201

E5E6E7

1/16W
MF-LF

1M

E3

402

A_AD_R0
A_AD_R1
A_AD_R2

D7

1%

VSTM0
VSTM1
VSTM2
VSTM3
VSTM4
VSTM5
VSTM6
VSTM7
VSTM8

VSTM9
VSTM10
VSTM11
VSTM12
VSTM13
VSTM14
VSTM15
VSTM16
VSTM17
VSTM18
VSTM19
VSTM20
VSTM21
VSTM22
VSTM23
VSTM24
VSTM25
VSTM26
VSTM27
VSTM28
VSTM29
VSTM30
VSTM31
VSTM32
VSTM33
VSTM34
VSTM35
VSTM36
VSTM37
VSTM38
VSTM39
VSTM40
VSTM41
VSTM42
VSTM43
VSTM44
VSTM46
VSTM45
VSTM47

C9

1

2

1

R3012

71.5K

1%

1/20W

MF

201

2

=PP3V0_GRAPE_MARIO1

1

C3006

0.1UF

10%

6.3V

2

X5R
201

A1

MT_PANEL_OUT<0>

B2

MT_PANEL_OUT<1>

C2

MT_PANEL_OUT<2>

D1

MT_PANEL_OUT<3>
MT_PANEL_OUT<4>

D2
E2

MT_PANEL_OUT<5>

F1

MT_PANEL_OUT<6>

G1

MT_PANEL_OUT<7>

G2

MT_PANEL_OUT<8>

I1

MT_PANEL_OUT<9>

H2

MT_PANEL_OUT<10>

I2

MT_PANEL_OUT<11>
MT_PANEL_OUT<12>

K1
K2

MT_PANEL_OUT<13>

I3

MT_PANEL_OUT<14>

K3

MT_PANEL_OUT<15>

J4

MT_PANEL_OUT<16>

I4

MT_PANEL_OUT<17>

K6

MT_PANEL_OUT<18>

H6

MT_PANEL_OUT<19>
MT_PANEL_OUT<20>

K5
J5

MT_PANEL_OUT<21>

I7

MT_PANEL_OUT<22>

K9

MT_PANEL_OUT<23>

I8

MT_PANEL_OUT<24>

K10

MT_PANEL_OUT<25>

I6

MT_PANEL_OUT<26>

J7

MT_PANEL_OUT<27>
MT_PANEL_OUT<28>

K11
I9

MT_PANEL_OUT<29>

J11

MT_PANEL_OUT<30>

I11

MT_PANEL_OUT<31>

H11

MT_PANEL_OUT<32>

G11

MT_PANEL_OUT<33>

G10

MT_PANEL_OUT<34>

F10

MT_PANEL_OUT<35>
MT_PANEL_OUT<36>

C10
D10

MT_PANEL_OUT<37>

E11

MT_PANEL_OUT<38>

D11

MT_PANEL_OUT<39>

B11

NC

B10

NC

C4

NC

A4

NC

B5

NC

A3

NC

C5

NC

B3

NC

A10

Z1_B_ADR<0>

B9

Z1_B_ADR<1>

A9

Z1_B_ADR<2>

LOAD CURRENT ~ 153UA

R3066

0.1

1 2

1%

1/20W

C3000

1UF

10%
25V
X5R
603-1

MF

201

1

2

32

17 18

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

18

18

18

PP18V_GRAPE

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=18V
NET_SPACING_TYPE=PWR

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

RST_GRAPE_Z2_L

GRAPE_FW_DNLD_EN_L

6

IN

OUT

1

R3030

5%
1/20W
MF
201

2

DIR_U3007

18

1

R3031

10K10K

5%
1/20W
MF
201

2

1

C3030

0.1UF

10%

6.3V

2

X5R
201

16

1

CRITICAL

1B1
2B1

1B2
2B2

2

15
13

14
12

3

2

VCCA

VCCB

U3007

PQFP1

6

1A1

8

2A1

4

1DIR

1

1OE*

7

1A2

9

2A2

5

2DIR
2OE*

SN74AVCH4T245RSV

SPI_GRAPE_SCLK

5

17 40

IN

SPI_GRAPE_CS_L

5

17 40

IN

SPI_GRAPE_MOSI

5

17 40

IN

RST_GRAPE_L

6

IN

MAKE_BASE=TRUE

5

17 40 18

5

17 40

IN

5

17 40

IN

5

17 40

IN

SPI_GRAPE_MISO

OUT

SPI_GRAPE_SCLK
SPI_GRAPE_CS_L

SPI_GRAPE_MOSI

(A -> B)

GND

10

11

=PP3V0_GRAPE

6

CRITICAL

VCC

U3010

SN74LVC1G126DRYR-M

Z1_CS_OE

17 18

IN

17

Z2_H_CS_L

17 18

IN

1

2

PART NUMBER

311S0523 311S0485

311S0524 311S0533

311S0525 311S0532

LLP

OE

A

GND

3

ALTERNATE FOR
PART NUMBER

4

Y

NC

5

BOM OPTION

1

C3050

0.1UF

10%

6.3V

2

X5R
201

Z1_CS_L

17 18 32

OUT

REF DES

U3007

U3009

U3010

CRITICAL

SN74LVC1G125DRYR-M

SPI_GRAPE_MISO

5

17 40

OUT

18

COMMENTS:

Z1_CS_OE

17 18

IN

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

U3009

6

LLP
4

SYNC_MASTER=RAMSIN

PAGE TITLE

2

NC

5

OE*

3

1

GRAPE: GROUNDHOG,CONN,BOOST

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

=PP3V0_GRAPE

1

2

RST_GRAPE_Z1_L

GRAPE_MISO

1

C3031

0.1UF

10%

6.3V
X5R
201

2

APN:311S0485

=PP3V0_GRAPE

1

C3041

0.1UF

10%

6.3V

2

X5R
201

R3025

10K

5%
1/20W
MF
201

GRAPE_SCLK
GRAPE_CS_L

GRAPE_MOSI

R3032

3.3K

5%
1/20W
MF
201

17 18 32

=PP3V0_GRAPE

1

R3033

10K

5%
1/20W
MF
201

2

Z1_SCLK

Z2_H_CS_L

Z1_MISO

Z1_CS_OE

17 18 32

Z1_MOSI

18

OUT

18

OUT

18

OUT

18

OUT

IN

17 18 32

OUT
OUT

OUT
OUT

18

IN

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

30 OF 106

SHEET

17 OF 42

18

17 18

18

17 18

TO Z2

TO Z1/Z2

SIZE

D

C

B

A

D

36

345678

2 1

ARM9 MCU (Z2 BASED)

Z2_VDDCORE

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.1MM

NET_SPACING_TYPE=PWR

VDDANA AND VDDCORE
ARE EACH GENERATED WITHIN
Z2 AND BYPASSED OUTSIDE

Z2_VDDANA

D

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.1MM

NET_SPACING_TYPE=PWR

1

2

1

C3112

2

C

CFG1 CFG0 MODE

DEPENDENT 1

00

0

1

DEPENDENT 2

1

0

AUTONOMOUS

1

1

SLAVE

K48 USES DEPENDENT 2 MODE

BOOT_CFG0_R

BOOT_CFG1_R

1

R3173

0

5%
1/20W
MF
201

2

B

17 18 32

=PP3V0_GRAPE

A

R3171

0

1 2

PART NUMBER

138S0618 138S0648

C3111

10UF

20%

6.3V
X5R
603

2.2UF

20%
4V
X5R
402

ALTERNATE FOR
PART NUMBER

138S0648138S0652

1

C3109

0.1UF

10%

6.3V

2

X5R
201

1

C3110

0.1UF

10%

6.3V

2

X5R
201

D2

E1G8H2J5E2

VDDANA

A9

IN0_0

NC

B9

IN0_1

NC

A7

IN1_0

NC

A8

IN1_1

NC

B8

IN2_0

NC

C8

IN2_1

NC

B7

IN3_0

NC

C7

IN3_1

NC

A6

IN4_0

NC

B6

IN4_1

NC

C6

IN5_0

NC

C5

IN5_1

NC

B5

IN6_0

NC

A5

IN6_1

NC

A4

IN7_0

NC

B4

IN7_1

NC

A3

IN8_0

NC

B3

IN8_1

NC

C2

IN9_0

NC

A2

IN9_1

NC

B2

IN10_0

NC

C1

IN10_1

NC

B1

IN11_0

NC

A1

IN11_1

NC

E6

ARMTAPMD*

NC

F6

BOOT_CFG0

D3

BOOT_CFG1

G5

FLOO

NC

F5

LFOO

NC

G7

EXTFLLIN

NC

VDDCORE

U3101

BCM5974CKFBGH

FBGA

VDDIO

CRITICAL

INTERNAL PU

VDDLDO

GND

C3H8C4D6D7D8C9D9G2

BOM OPTION

REF DES

C3107

C3107

COMMENTS:

RADAR:8392120

BOM CONSOLIDATION

VOLTAGE=1.8V
NET_SPACING_TYPE=PWR

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

1

2

E3

B_ADR0
B_ADR1
B_ADR2

BON_L0
BON_L1
BON_L2
BON_L3
BON_L4
BON_L5

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS

H_CS*

H_SCLK

H_SDI
H_SDO

A_CS*

A_SCLK

A_SDI
A_SDO

TM0
TM1

CLKIN

CLKOUT

RESET*

D1

1

C3105

0.1UF

10%

6.3V

2

X5R
201

C3108

0.1UF

10%

6.3V
X5R
201

F9
F8
G9

J8
H9
J9
H7
J7
H5

J2
J3
H4
J6
G3
F3
F4
H6

G6
E8
E9
F7

H1
J1
H3
J4

F1
G1
F2
G4

E7
D4

E5
E4

D5

1

2

Z2_3V3_1V8_IN

1

C3106

0.1UF

10%

6.3V

2

X5R
201

Z1_PCLK

Z1_CS_OE_R
NC_BON_L1
NC_BON_L2
NC_BON_L3
NC_BON_L4
Z2_BON_L4

Z1_GO

Z1_DONE

TP_U3101_TCK
TP_U3101_TDI
TP_U3101_TDO
TP_U3101_TMS

Z2_H_CS_L

Z1_SCLK
Z1_MISO

Z1_MOSI

Z2_A_CS_L

TP_Z2_A_SCLK

TP_Z2_A_SDI
TP_Z2_A_SDO

TP_U3101_TM0

U3101_TM1

HOST_REFCLK

NC

RST_GRAPE_Z2_L

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

C3107

4.7UF

20%

6.3V
X5R
402

1

C3191

22UF

20%

6.3V

2

X5R-CERM
603

18

18

18

GRAPE_CS_L
GRAPE_MOSI
GRAPE_MISO
GRAPE_SCLK

17

IN

17 18

IN

17 18

IN

17 18

OUT

=PP3V0_GRAPE_Z2

R3190

1.00

1 2

1%

1/20W

MF

201

R3120

0

5%

1/20W

MF

201

1 2

=PP3V0_GRAPE_Z2
NOSTUFF

1

R3161

100K

5%
1/20W
MF
201

2

IRQ_GRAPE_HOST_INT_L

PM_BOOST_EN

17

IN

17

IN

17

OUT

17

IN

=PP3V0_GRAPE

1

R3107

100K

5%
1/20W
MF
201

2

CLK_32K_PMU

MAKE_BASE=TRUE

17

IN

18 32

Z1_1V8_OUT

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM

VOLTAGE=1.8V
NET_SPACING_TYPE=PWR

MIN_NECK_MIDTH SHOULD BE 0.4MM

Z1_CS_OE

NOTE: PLATEFORM DETECTION PIN "H5"
PULL DOWN = K48
FLOATING = K93/K94
PULL UP = RESERVED FOR FUTURE

1

2

R3180

1 2

1/32W
01005

IN

18 32

R3160

100K

5%
1/20W
MF
201

100

5%
MF

IN

17

OUT

17 18 32

35 39

18

5

OUT

17

8 7 5 4 2 1

ZEPHYR 1+ ASIC

=PP3V0_GRAPE_Z1

32

VOLTAGE=3.0V

4.7

1/20W

201

5%
MF

MIN_LINE_WIDTH=0.2MM

NET_SPACING_TYPE=PWR

MT_3V3_INT

1

C3104

20%
4V

2

X5R
402

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

R3101

1 2

MT_PANEL_IN<0>

17

MT_PANEL_IN<1>

17

MT_PANEL_IN<2>

17

MT_PANEL_IN<3>

17

MT_PANEL_IN<4>

17

MT_PANEL_IN<5>

17

MT_PANEL_IN<6>

17

MT_PANEL_IN<7>

17

MT_PANEL_IN<8>

17

MT_PANEL_IN<9>

17

MT_PANEL_IN<10>

17

MT_PANEL_IN<11>

17

MT_PANEL_IN<12>

17

MT_PANEL_IN<13>

17

MT_PANEL_IN<14>

17

MT_PANEL_IN<15>

17

MT_PANEL_IN<16>

17

MT_PANEL_IN<17>

17

MT_PANEL_IN<18>

17

MT_PANEL_IN<19>

17

MT_PANEL_IN<20>

17

MT_PANEL_IN<21>

17

MT_PANEL_IN<22>

17

MT_PANEL_IN<23>

17

MT_PANEL_IN<24>

17

MT_PANEL_IN<25>

17

MT_PANEL_IN<26>

17

MT_PANEL_IN<27>

17

MT_PANEL_IN<28>

17

MT_PANEL_IN<29>

17

MUX_IN<0>

17

MUX_IN<1>

17

MUX_IN<2>

17

MUX_IN<3>

17

MUX_IN<4>

17

MUX_IN<5>

17

MUX_IN<6>

17

MUX_IN<7>

17

MUX_IN<8>

17

MUX_IN<9>

17

MUX_IN<10>

17

MUX_IN<11>

17

MUX_IN<12>

17

MUX_IN<13>

17

MUX_IN<14>

17

MUX_IN<15>

17

MUX_IN<16>

17

MUX_IN<17>

17

MUX_IN<18>

17

MUX_IN<19>

17

1

C3102

2

1

C3103

0.1UF2.2UF

10%

6.3V

2

X5R
201

C1

C10

VDDANA

D1

IN0

D2

IN1

D3

IN2

D4

IN3

E1

IN4

E2

IN5

E3

IN6

E4

IN7

F1

IN8

F2

IN9

F3

IN10

F4

IN11

G1

IN12

G2

IN13

G3

IN14

G4

IN15

G5

IN16

H1

IN17

H2

IN18

H3

IN19

H4

IN20

H5

IN21

J1

IN22

K1

IN23

J2

IN24

K2

IN25

J3

IN26

K3

IN27

J4

IN28

K4

IN29

J5

IN30

K5

IN31

K6

IN32

J6

IN33

J7

IN34

K7

IN35

J8

IN36

K8

IN37

J9

IN38

K9

IN39

J10

IN40

K10

IN41

H6

IN42

H7

IN43

H8

IN44

H9

IN45

H10

IN46

G6

IN47

G7

IN48

G8

IN49

G9

IN50

G10

IN51

F7

IN52

F8

IN53

F9

IN54

F10

IN55

E7

IN56

E8

IN57

E9

IN58

E10

IN59

D7

IN60

D8

IN61

D9

IN62

D10

IN63

GNDANA

C2C9D6E6F6B7C8

0.1UF

10%

6.3V
X5R
201

D5E5F5C7C4

CRITICAL

U3100

BGA-HF

INTERNAL PU

VDDIO

VDDDIG

BCM5973

GNDDIG

Z1_1V8_OUT

18

C6

V18

SCLK

CS*
MISO
MOSI

GO

DONE

PCLK

STMOUT

STMIN

B_ADR0
B_ADR1
B_ADR2

BON_L0
BON_L1
BON_L2
BON_L3
BON_L4
BON_L5

TM

RESET*

GNDIO

C3

36

A9

A7
A6

B5
B6

A10

B9
B10

B2
B3
B4

A1
A2
A3
A4
A5
B1

B8

1

2

A8

C5

C3101

2.2UF

20%
4V
X5R
402

=PP3V0_GRAPE

1

R3155

100K

5%
1/20W
MF
201

2

Z1_DONE

Z1_PCLK

Z1_STMIN

Z1_B_ADR<0>
Z1_B_ADR<1>
Z1_B_ADR<2>

Z1_BON_L<0>
Z1_BON_L<1>
Z1_BON_L<2>
Z1_BON_L<3>
Z1_BON_L<4>
Z1_BON_L<5>

U3100_TM

Z1_SCLK
Z1_CS_L
Z1_MISO
Z1_MOSI

Z1_GO

RST_GRAPE_Z1_L

R3181

100

1 2

5%

1/32W

MF

01005

17 18 32

18

18

18

17

17

17

17

17

17

17

17

17

D

17 18

IN

17

IN

17 18

IN

17 18

OUT

C

17

B

SIZE

A

D

SYNC_MASTER=RAMSIN

PAGE TITLE

GRAPE: Z1, Z2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

31 OF 106

SHEET

18 OF 42

L63 AUDIO CODEC

APN:338S0940

345678

2 1

=PPVCC_MAIN_AUDIO

D

5

10 35 39

5

10 35 39

5

35

35

5

25

OUT

25

OUT

25

IN

25

IN

39

5

39

5

39

5

39

5

39

5

30 39

5

30 39

5

30 39

5

30 39

5

39

5

39

5

39

5

39

DMIC_SCLK_SENSOR

DMIC_SCLK_CANADA

DMIC_SD_SENSOR

DMIC_SD_CANADA

C

B

23

23

23 40

23 40

23

A

8 7 5 4 2 1

20 32

32

I2C0_SCL_1V8

IN

I2C0_SDA_1V8

BI

IRQ_CODEC_L

OUT

RST_L63_L

IN

AUD_MIK_HS1_INT_L

OUT

I2S_AP_0_MCK_R

IN

I2S_AP_0_LRCK

IN

I2S_AP_0_BCLK

IN

I2S_AP_0_DOUT

IN

I2S_AP_0_DIN

OUT

I2S_AP_2_LRCK

IN

I2S_AP_2_BCLK

IN

I2S_AP_2_DOUT

IN

I2S_AP_2_DIN

OUT

I2S_AP_3_LRCK

IN

I2S_AP_3_BCLK

IN

I2S_AP_3_DOUT

IN

I2S_AP_3_DIN

OUT

EXT_MIC_BIAS

OUT

HSMIC_C_P

IN

EXT_MIC_P

IN

EXT_MIC_REF

IN

HSMIC_C_N

IN

GND_AUDIO_CODEC

19 21

=PP1V8_AUDIO

NOSTUFF

NOSTUFF

R3608

1 2

5%

1/32W

R3620

1 2

5% MF

1/32W

R3621

1 2

5% MF

1/32W

R3622

1 2

5%

C3600

1000PF

R3601

R3602

R3603

22

MF

01005

22

01005

22

01005

22

MF

010051/32W

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

MAX_NECK_LENGTH=75 MM

1

C3601

0.1UF

10%

6.3V

2

X5R

01005

1 2

MF5%

1/32W 01005

1 2

1 2

MF

MF5%

01005

1/32W5%01005

1/32W

R3605

01005

22

22

22

1

C3605

27PF

5%
16V

2

NP0-C0G

VHP_FLYP

VHP_FLYC

VHP_FLYN

SPKR_VQ

FILT_P

VHPPFILT
VHPNFILT

01005

1

2

C3602

1

20%

4V

2

X5R

1

0.1UF

20%

4V

2

X5R

01005

DMIC_SCLK_CODEC
DMIC_SD_CODEC

39

L63_ASP_SDOUT

39

L63_VSP_SDOUT

L63_XSP_SDOUT

39

NC_LINE_IN1_CODEC
NC_LINE_IN1_REF_CODEC

NC_LINE_IN2_CODEC

NC_LINE_IN2_REF_CODEC

NC_MIC1_BIAS_CODEC

NC_MIC1P_CODEC

NC_MIC1N_CODEC

NC_MIC1_FILT_CODEC

1.00K

1 2

1%

1/32W

MF

01005

1

C3609

4.7UF

20%

6.3V

2

X5R-CERM

402

C3603

10UF

6.3V

R3604

1

20%

2

X5R
603

1 2

1% MF

1/32W

1.00K

C3611

4.7UF

6.3V

X5R-CERM

1

C3604

0.1UF

10%

6.3V

2

X5R
201

01005

MIC2_DET_REF

MIC2_BIAS_FILT

1

20%

2

402

MIC2_DET

C6

SCL

C7

SDA

E4

INT*

E5

RESET*

E3

WAKE*

B9

MCLK

C8

ASP_LRCLK

B7

ASP_SCLK

B8

ASP_SDIN

A9

ASP_SDOUT

C9

VSP_LRCLK

C10

VSP_SLCLK

A11

VSP_SDIN

A10

VSP_SDOUT

B6

XSP_LRCLK

A6

XSP_SCLK

A8

XSP_SDIN/DAC2B_MUTE

A7

XSP_SDOUT

B5

DMIC_SCLK

A5

DMIC_SD

C5

LINEINA

C4

LINEINA_REF

D6

LINEINB

D5

LINEINB_REF

D4

MIC1_BIAS

A3

MIC1

B3

MIC1_REF

E2

MIC1_BIAS_FILT

C2

MIC2_BIAS

D3

MIC2_DETECT

B1

MIC2

B2

MIC2_REF

C3

MIC2_DETECT_REF

C1

MIC2_BIAS_FILT

D2

MIC3A_BIAS

A1

MIC3A

A2

MIC3A_REF

D1

MIC3A_BIAS_FILT

F1

MIC3B_BIAS

A4

MIC3B

B4

MIC3B_REF

E1

MIC3B_BIAS_FILT

GNDD

B10

C11

B11

VL

VD

CS42L63B

I2C ADDRESS: 1001010X??

GNDA

GNDCP

F2

G5

E10

U3600

WLCSP

GNDP

G2

F5

VP

LINEOUT2A_REF

LINEOUT2B_REF

GND

D8

D9

VA

LINEOUT1_REF

SPEAKEROUTA+
SPEAKEROUTA-

SPEAKEROUTB+
SPEAKEROUTB-

D11

VCP

HP_DETECT

HPOUTB

HPOUTA

HPOUT_REF

LINEOUT1B
LINEOUT1A

LINEOUT2A

LINEOUT2B

EAROUT+
EAROUT-

FLYP

FLYC

FLYN

SPEAKER_VQ

FILT+

+VCP_FILT

-VCP_FILT

E9

G9

G10

F9

G8
F8
E8

D7
E7

F7
G7

G3
F3

F6
G6

F4
G4

E11

F11

G11

E6

G1

D10
F10

C3614

10UF

6.3V

C3613

10UF

20%

6.3V
X5R
603

1

C3606

10UF

20%
4V

2

X5R
402

C3617

2.2UF

X5R-CERM

1 2

20%
10V

402

1

C3607

0.1UF

20%
4V

2

X5R
01005

NC_EAROUT_AN

NC_SPEAKEROUT_AP
NC_SPEAKEROUT_AN

NC_SPEAKEROUT_BP

NC_SPEAKEROUT_BN

C3618

2.2UF

1 2

20%
10V

X5R-CERM

402

1

C3608

4.7UF

20%
4V

2

TANT
402-3

XW3600

1 2

XW3601

1 2

XW3602

1 2

NC_EAROUT_AP

SM

SM

SM

MIN_LINE_WIDTH=1.0MM
MIN_NECK_WIDTH=0.2MM

NOT USING SPEAKER AMPLIFIER, THIS CAN BE A NO STUFF

2.2UF

RECOMMENDED

1

20%

2

X5R
603

CRITICAL

1

C3615

1UF

10%

6.3V

2

TANT
402-1

CRITICAL

1

C3616

4.7UF

20%

6.3V

2

X5R-CERM
402

36

=PP1V7_VA_VCP

GND_AUDIO_CODEC

GND_AUDIO_HP_AMP

CODEC_LINE_OUT_R

CODEC_LINE_OUT_L

CODEC_LINE_OUT_REF

LEFT_CH_OUT_P

LEFT_CH_OUT_REF

RIGHT_CH_OUT_P

RIGHT_CH_OUT_REF

32

19 21

21 23

HP_DET

HP_REF

SYNC_MASTER=LENG

PAGE TITLE

HP_R

HP_L

24

IN

21

OUT

21

OUT

21 23

IN

21

OUT

21

OUT

21

IN

20 40

OUT

20 40

IN

20 40

OUT

20 40

IN

AUDIO: L63 CODEC

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

36 OF 106

SHEET

19 OF 42

SIZE

D

C

B

A

D

345678

2 1

D

SPEAKER AMPLIFIER

APN:353S2958

12DB
9DB
6DB
3DB
0DB

GAIN

VDD
47K

NC
SHORT

NC

GND
NC

47K
NC
NCNC
SHORT

D

TURN ON TIME: 7.5MS

80HZ +/- XXX%

=PPVCC_MAIN_AUDIO

19 20 32

SM

1 2

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM

AUD_SPKR_AMP1_PBUS

XW3701

LEFT CHANNEL IS INVERTED TO FIX CODEC BUG ON LINEOUT2

CRITICAL

C3702

0.047UF

1 2

40

LEFT_CH_OUT_REF

19 40

OUT

R3701

100

LEFT_CH_OUT_P

19 40

IN

AUD_SPKRAMP_MUTE_L

5

20

C

L63 LINEOUT2A IS CONNECTED TO U3700
L63 LINEOUT2B IS CONNECTED TO U3710

IN

=PPVCC_MAIN_AUDIO

19 20 32

1%

1/32W

MF

01005

12

R3702

0.00

1/32W
01005

LEFT_CH_P

40

1

0%
MF

2

10%

6.3V
X5R
201

XW3711

SM

1 2

0.047UF

SSM2375_L_IN_N

201

C3701

12

10%

6.3V
X5R

CRITICAL

AUD_SPKR_AMP2_PBUS

40

SSM2375_L_IN_P

1

R3700

100K

5%

1/32W

MF

01005

2

XW3700

SM

1 2

B

CRITICAL

C3711

0.047UF

10%

6.3V
X5R
201

12

CRITICAL

0.047UF

C3712

10%

6.3V
X5R
201

SSM2375_R_IN_P

40

12

SSM2375_R_IN_N

40

RIGHT_CH_OUT_P

19 40

IN

RIGHT_CH_OUT_REF

19 40

OUT

AUD_SPKRAMP_MUTE_L

5

20

R3711

100

1%

1/32W

MF

01005

12

40

RIGHT_CH_P

TURN ON DELAY: 20MS

1

C3703

0.1UF

10%

6.3V

2

X5R
201

B1
A1

A2

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM

1

C3713

0.1UF

10%

6.3V

2

X5R
201

C2

VDD

U3700

SSM2375

WLCSP
IN+
IN-

SD*

GND

C1

GND_SPKR_AMP1

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM

U3710

SSM2375

WLCSP

B1

IN+

A1

IN-

A2

SD*

GND

C1

OUT+
OUT-

GAIN

EDGE

GAIN:6DB

C2

VDD

OUT+
OUT-

GAIN

EDGE

GAIN:6DB

1

R3703

0.00

0%

1/32W

MF

01005

2

C3
B3

A3

SSM2375_L_GAIN

B2

1

R3713

0.00

0%

1/32W

MF

01005

2

C3
B3

A3

SSM2375_R_GAIN

B2

1

C3704

10UF

20%

10V

2

X5R
603

SPKRAMP_L_OUT_P
SPKRAMP_L_OUT_N

1

C3714

10UF

20%

10V

2

X5R
603

SPKRAMP_R_OUT_P
SPKRAMP_R_OUT_N

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

SPKRAMP_L_OUT_P

20

SPKRAMP_L_OUT_N

20

SPKRAMP_R_OUT_P

20

SPKRAMP_R_OUT_N

20

20

OUT

20

OUT

20

OUT

20

OUT

SPEAKER CONNECTOR

APN 518S0521

NOSTUFF

CRITICAL

1

C3750

100PF

5%

16V

2

NP0-C0G
01005

NOSTUFF

CRITICAL

C3751

100PF

NP0-C0G

01005

1

5%

16V

2

NOSTUFF

CRITICAL

1

C3752

100PF

5%

16V

2

NP0-C0G
01005

NOSTUFF

CRITICAL

C3753

100PF

NP0-C0G

01005

5%

16V

1

2

J3700

78171-0004

M-RT-SM
5

1
2
3
4

6

C

B

1

R3712

0.00

0%

1/32W

MF

01005

2

A

8 7 5 4 2 1

XW3710

SM

1 2

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM

GND_SPKR_AMP2

SIZE

A

D

SYNC_MASTER=LENG

PAGE TITLE

AUDIO: SPEAKER AMP

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

37 OF 106

SHEET

20 OF 42

36

345678

2 1

HEADPHONE OUTPUT ZOBEL NETWORK

XW3851

D

19

IN

19

IN

19 23

19 23

HP_L

HP_R

GND_AUDIO_HP_AMP

19 23

HP_REF

OUT

R3850

1/32W
01005

C3850

33000PF

6.3V

100

10%
X5R

XW3850

1 2

1

1

R3851

2

1

2

HP_ZR

100

1%
1/32W
MF
01005

2

HP_ZL

1

C3851

33000PF

10%

6.3V

2

X5R
201201

1%
MF

SM

1 2

SM

1

C3853

27PF

5%
16V

2

NP0-C0G
01005

1

C3852

27PF

5%
16V

2

NP0-C0G
01005

AUD_HP1_MLBCON_L

AUD_HP1_MLBCON_R

24

OUT

24

OUT

IN

D

C

1

C3854

27PF

5%
16V

2

NP0-C0G
01005

C

DOCK LINE OUTPUT

XW3800

CODEC_LINE_OUT_REF

19

OUT

B

19

IN

19

IN

CODEC_LINE_OUT_L

CODEC_LINE_OUT_R

MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.07MM

MIN_LINE_WIDTH=0.1MM

MIN_NECK_WIDTH=0.07MM

MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.07MM

SM

1 2

XW3801

SM

1 2

XW3802

SM

1 2

CODEC

XW3803

SM

GND_AUDIO_CODEC

19

1 2

MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.07MM

MIN_LINE_WIDTH=0.1MM

MIN_NECK_WIDTH=0.07MM

MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.07MM

1

C3801

15PF

5%
16V

2

NP0-C0G-CERM
01005

C3802

15PF

5%

16V

NP0-C0G-CERM

01005

AUD_LO_REF_FILT

NOSTUFF

1

C3800

1

0.01UF

10%
10V

2

2

X7R
201

R3800

MIN_LINE_WIDTH=0.1MM

1.00

1 2

MIN_NECK_WIDTH=0.07MM

1%

1/20W

MF

201

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

MAX_NECK_LENGTH=75 MM

C3803

15PF

NP0-C0G-CERM

01005

AV_EMI_DIFF_SENSE

AUDIO_EMI_LO_L

AUDIO_EMI_LO_R

1

5%

16V

2

GND_AUDIO_PT_DK

IN

OUT

OUT

DOCK

28

IN

28

28

28

B

A

SYNC_MASTER=LENG

PAGE TITLE

AUDIO: HEADPHONE OUT

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

38 OF 106

SHEET

21 OF 42

SIZE

A

D

345678

2 1

D

D

EXTERNAL (HEADSET) MIC INPUT CIRCUITRY

=PP3V0_S2R_HALL_CHSW

32

1

C4200

0.1UF

10%

6.3V

2

X5R
201

C

AUD_HS_MIC1_HI

24

IN

FROM HEADSET

24

IN

19 21

OUT

AUD_HS_MIC1_LO

AUD_HS_RET1

24

AUD_HS_RET2

24

GND_AUDIO_HP_AMP

19 21

HP_REF

C4216

33PF

NP0-C0G

01005

1

5%

16V

2

NP0-C0G-CERM

C4212

15PF

01005

1

5%

16V

2

XW4200

1 2

C1

SM

A1

VDD

U4200

TS3A8235YFP

WCSP

RAMPI

RAMPO

CLAMPI

CLAMPO

MIC1
MIC2

ADDR

GND

GND2

B2

B3

C3

MIC
REF

SCL
SDA

C2

GND1

D4

D3
C4

B4

CHS_CLAMPO

HSMIC_C_P

D2B1

HSMIC_C_N

D1

A3
A4
A2

B

R4203

2.2K

1 2

1%

1/20W

MF

201

CHS_CLAMPI

R4202

2.2K

1 2

1%

1/20W

MF

201

1 2

1

C4201

10UF

20%

6.3V

2

CERM-X5R
0402-1

R4201

1K

5%

1/20W

MF

201

EXT_MIC_BIAS

C4211

0.1UF

1 2

10%

6.3V
X5R
201

C4213

0.1UF

1 2

10%

6.3V
X5R
201

HSMIC_R_P

HSMIC_R_N

HSMIC_C_P

R4212

470

1 2

1%

1/20W

MF

201

R4213

470

1 2

1%

1/20W

MF

201

1

C4217

1000PF

10%
16V

2

X7R
201

EXT_MIC_P

EXT_MIC_REF

HSMIC_C_N

CHS_SCL

CHS_SDA

TO CODEC

10

EXT MIC LPF FC = 677KHZ

19

IN

19 23 19 23

OUT

19 40

OUT

19 40

OUT

19 23 19 23

OUT

10

C

B

A

8 7 5 4 2 1

36

SYNC_MASTER=LENG

PAGE TITLE

AUDIO: DETECT/MIC BIAS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

42 OF 106

SHEET

23 OF 42

SIZE

A

D

345678

2 1

D

D

HEADPHONE JACK CONNECTION IS ON FRONT PANEL FLEX, CSA 55/PDF 29

PLACE ALL COMPONENTS NEAR J5501

L4301

30-OHM-1.7A

CONN_AUD_HS_MIC1_HI

25

IN

MIN_LINE_WIDTH=1.0MM
MIN_NECK_WIDTH=0.1MM

CONN_AUD_HS_MIC1_LO

25

IN

MIN_LINE_WIDTH=1.0MM
MIN_NECK_WIDTH=0.1MM

CONN_AUD_HS_RET1

25 23

C

IN

CONN_AUD_HS_RET2

IN

CONN_AUD_HP1_DET_H

25

IN

CONN_AUD_HP1_MLBCON_R

25

OUT

CONN_AUD_HP1_MLBCON_L

25

OUT

1 2

0402

L4302

30-OHM-1.7A

1 2

0402

MAKE_BASE=TRUE
MIN_LINE_WIDTH=1.0MM
MIN_NECK_WIDTH=0.1MM

MAKE_BASE=TRUE
MIN_LINE_WIDTH=1.0MM
MIN_NECK_WIDTH=0.1MM

MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=1.0MM

MIN_LINE_WIDTH=1.0MM
MIN_NECK_WIDTH=0.1MM

240-OHM-0.2A-0.8-OHM

L4303

1 2

0201

L4304

30-OHM-1.7A

1 2

0402

L4306

30-OHM-1.7A

1 2

0402

AUD_HS_RET1

AUD_HS_RET2

AUD_HS_MIC1_HI

AUD_HS_MIC1_LO

OUT

23 25

OUT

AUD_HP1_DET_H

AUD_HP1_MLBCON_R

AUD_HP1_MLBCON_L

23

OUT

23

OUT

C

24

OUT

21

IN

21

IN

HEADSET JACK INSERTION DETECT

R4312

3.3K

B

AUD_HP1_DET_H

24 19

IN

1 2

5%

1/32W

MF

01005

A

8 7 5 4 2 1

NOSTUFF

1

C4310

4700PF

10%
10V

2

X7R
201

HP_DET

OUT

SYNC_MASTER=LENG

PAGE TITLE

AUDIO: HP/MIC FILTERS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

43 OF 106

SHEET

24 OF 42

36

SIZE

B

A

D

345678

2 1

D

CANADA FLEXES CONN.

SENSOR BOARD CONN ALIASES

D

APN: 518S0817

CLK_CAM_RF_FILT

J5501

CRITICAL

41
39

PPVSIM

26 31

SIM_CLK_FILT

26

IN

SIM_DET

31

OUT

CONN_AUD_HS_MIC1_HI

24

OUT

CONN_AUD_HS_MIC1_LO

24

OUT

CONN_AUD_HP1_MLBCON_R

24

C

IN

CONN_AUD_HP1_DET_H

24

OUT

IRQ_ALS_INT_CONN_L

26

OUT

I2C2_SDA_3V0_ALS

26 39

BI

ISP_CAM_1_SDA

26 39

BI

PM_FRONT_CAM_SHUTDOWN_FILT

26

IN

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

38
40

F-RT-SM

502250-8237

SIM_RST
SIM_IO
CONN_AUD_HS_RET1
CONN_AUD_HS_RET2
CONN_AUD_HP1_MLBCON_L
DMIC_SCLK_CANADA

I2C2_SCL_3V0_ALS

DMIC_SD_CANADA

ISP_CAM_1_SCL

PP3V0_ALS

CLK_CAM_FF_CONN
PP1V8_CAM_FF
PP2V85_CAM_FF
MIPI1C_CAM_CLK_P
MIPI1C_CAM_CLK_N
MIPI1C_CAM_DATA_P<0>
MIPI1C_CAM_DATA_N<0>

31

IN

31

BI

24

OUT

24

OUT

24

IN

26 39

IN

26 39

IN

26

26 39

IN

26

26

26 40

IN

26 40

IN

26 40

BI

26 40

BI

19

IN

19

OUT

27 39 27

MIPI0C_CAM_DATA_N<0>

27 40 27

MIPI0C_CAM_DATA_P<0>

27 40

MIPI0C_CAM_CLK_N

27 40 27

MIPI0C_CAM_CLK_P

27 40

PM_REAR_CAM_SHUTDOWN

7

PP1V8_SENSOR_FILT

27

PP2V85_CAM_REAR

27

DMIC_SD_SENSOR

19 27

19

DMIC_SCLK_SENSOR

ISP_AP_0_SCL

7

39

ISP_AP_0_SDA

7

39

I2C2_SCL_3V0

5

26 39

I2C2_SDA_3V0

5

26 39

IRQ_ACCEL_INT1_L

5

IRQ_ACCEL_INT2_L

5

IRQ_GYRO_INT1

5

IRQ_GYRO_INT2

5

I2C1_SCL_1V8

5

39

I2C1_SDA_1V8

5

39

IRQ_HALL

35

IRQ_PROX_INT_L

5

PP3V0_S2R_HALL_FILT

27

ONOFF_L

5

35

SRL_L

5

35

AUD_VOL_UP_L

5

AUD_VOL_DOWN_L

5

PP3V0_OPTICAL_SENS

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

CONN_CLK_CAM_RF_FILT
CONN_MIPI0C_CAM_DATA_N<0>
CONN_MIPI0C_CAM_DATA_P<0>

CONN_MIPI0C_CAM_CLK_N
CONN_MIPI0C_CAM_CLK_P

CONN_PM_REAR_CAM_SHUTDOWN

CONN_PP1V8_SENSOR_FILT
CONN_PP2V85_CAM_REAR

CONN_DMIC_SD_SENSOR

CONN_DMIC_SCLK_SENSOR
CONN_ISP_AP_0_SCL
CONN_ISP_AP_0_SDA
CONN_I2C2_SCL_3V0
CONN_I2C2_SDA_3V0
CONN_IRQ_ACCEL_INT1_L
CONN_IRQ_ACCEL_INT2_L
CONN_IRQ_GYRO_INT1
CONN_IRQ_GYRO_INT2
CONN_I2C1_SCL_1V8
CONN_I2C1_SDA_1V8
CONN_IRQ_HALL
CONN_IRQ_PROX_INT_L
CONN_PP3V0_S2R_HALL
CONN_ONOFF_FTR_L
CONN_SRL_FTR_L
CONN_AUD_VOL_UP_FTR_L
CONN_AUD_VOL_DOWN_FTR_L

CONN_PP3V0_OPTICAL_SENS

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27 27

C

SIZE

B

A

D

B

A

8 7 5 4 2 1

36

SYNC_MASTER=MARK B.

PAGE TITLE

CONNECTOR: CANADA FLEX CONN,SENSOR PANEL ALIASES

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

54 OF 106

SHEET

25 OF 42

345678

2 1

VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

25

PP3V0_ALS

MAX_NECK_LENGTH=3 MM

D

1

PPVSIM

25 31

1

C5530

0.1UF

10%

6.3V

2

X5R
201

C5542

1000PF

10%
16V

2

X7R
201 402

1

C5540

1UF

10%
10V

2

X5R

L5540

240-OHM-0.2A-0.8-OHM

1 2

0201

1

C5541

82PF

2

FILTER PLACEHOLDER

5%
25V
CERM
0201

=PP3V0_OPTICAL

5

27 32

D

CANADA FLEX CONN ON PG 54

26 32

=PP1V8_CAM

240-OHM-0.2A-0.8-OHM

L5520

1 2

0201

FILTER PLACEHOLDER

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

C5521

82PF

5%
CERM

0201

1

C5520

1UF

10%
10V25V

2

X5R
402

1

2

1

C5522

1000PF

10%
16V

2

X7R
201

PP1V8_CAM_FF

25

25

PP2V85_CAM_FF

VOLTAGE=2.85V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

1

C5512

1000PF

10%
16V

2

X7R
201

1

C5510

1UF

10%
10V

2

X5R
402

C

L5510

240-OHM-0.2A-0.8-OHM

1 2

0201

1

C5511

82PF

5%
25V

2

CERM
0201

FILTER PLACEHOLDER

=PP2V85_CAM

27 32

C

CANADA FLEX SIGNAL FILTERS

R5510

B

CLK_CAM_FF

7

39

IN

=PP1V8_CAM

26 32

1

R5501

2

5

25 39

A

IN

7

39

BI

PM_FRONT_CAM_SHUTDOWN

7

IN

39

7

IN

31 25

5

5

25 39

100K

5%
1/20W
MF
201

I2C2_SCL_3V0
ISP_AP_1_SDA

ISP_AP_1_SCL

8 7 5 4 2 1

IN

OUT

BI

SIM_CLK

IRQ_ALS_INT_L

I2C2_SDA_3V0

NOSTUFF

1

C5501

1000PF

10%
16V

2

X7R
201

800MHZ-100MA-27PF

1

IN1

2

IN2

3

IN3

4

IN4

U5501

800MHZ-100MA-27PF

1

IN1

2

IN2

3

IN3

4

IN4

NOSTUFF

1

C5500

100PF

5%
25V

2

CERM
201

U5500

0603

GND

9

10

0603

GND

9

OUT1
OUT2
OUT3
OUT4

10

SIM_CLK_FILT

5

OUT1

6

OUT2

7

OUT3

8

OUT4

I2C2_SCL_3V0_ALS

5

ISP_CAM_1_SDA

6

PM_FRONT_CAM_SHUTDOWN_FILT

7

ISP_CAM_1_SCL

8

IRQ_ALS_INT_CONN_L

I2C2_SDA_3V0_ALS
CLK_CAM_FF_CONN

OUT

25

IN

25 39

BI

25 39

OUT

40

7

IN

7

40

IN

7

40

BI

7

40

BI

MIPI1C_AP_CLK_P
MIPI1C_AP_CLK_N
MIPI1C_AP_DATA_P<0>
MIPI1C_AP_DATA_N<0>

R5511

R5512

R5513

25 39

OUT

25 39

BI

OUT

25 39

25

OUT

36

0

1 2

MF

5%

L5500

90-OHM-50MA

TCM0605

SYM_VER-1

1 2

5%

1 2

L5501

90-OHM-50MA

TCM0605

SYM_VER-1

1 2

5%

1/20W

201

0

MF

201

0

MF5%

201

0

MF

201

1/20W

1

2 3

1/20W

1/20W

1

2 3

NOSTUFF

4

MIPI1C_CAM_CLK_P

MIPI1C_CAM_CLK_N

NOSTUFF

NOSTUFF

4

MIPI1C_CAM_DATA_P<0>

MIPI1C_CAM_DATA_N<0>

NOSTUFF

25 40

OUT

25 40

OUT

25 40

BI

25 40

BI

SYNC_MASTER=MARK B.

PAGE TITLE

CONNECTOR: CANADA FLEX FILTERS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

55 OF 106

SHEET

26 OF 42

SIZE

B

A

D

345678

R5600

0

7

39

D

MIPI0C_AP_DATA_N<0>

7

40

IN

MIPI0C_AP_DATA_P<0>

7

40

BI

MIPI0C_AP_CLK_N

7

40

IN

MIPI0C_AP_CLK_P

7

40

BI

IN

C

L5610

240-OHM-0.2A-0.8-OHM

=PP3V0_S2R_HALL

32

=PP1V8_SENSOR

32

B

26 32

=PP3V0_OPTICAL

5

26 32

1 2

0201

L5611

240-OHM-0.2A-0.8-OHM

1 2

0201

=PP2V85_CAM

L5612

240-OHM-0.2A-0.8-OHM

1 2

0201

A

PP3V0_S2R_HALL_FILT

1

C5601

82PF

5%
25V

2

CERM
0201

PP1V8_SENSOR_FILT

1

C5612

82PF

5%
25V

2

CERM
0201

L5613

240-OHM-0.2A-0.8-OHM

1 2

0201

PP3V0_OPTICAL_SENS

1

C5614

82PF

5%
25V

2

CERM
0201

1

C5602

1UF

10%
10V

2

X5R
402

1

C5613

1UF

10%
10V

2

X5R
402

PP2V85_CAM_REAR

1

C5617

82PF

5%
25V

2

CERM
0201

1

C5615

1UF

2

10%
10V
X5R
402

1

C563

1000PF

10%
16V

2

X7R
201

1

C5620

1000PF

10%
16V

2

X7R
201

1

C5618

1UF

10%
10V

2

X5R
402

1

2

CLK_CAM_RF

R5610

1 2

1/20W

L5600

90-OHM-50MA

TCM0605

SYM_VER-1

1

2 3

R5611

1 2
5% MF

1/20W

R5612

1 2

5%

1/20W

L5601

90-OHM-50MA

TCM0605

SYM_VER-1

1

2 3

R5613

1 2

5%

1/20W

VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

1

C5621

1000PF

10%
16V

2

X7R
201

C5616

0.1UF

10%

6.3V
X5R
201

1

2

0

MF5%

201

4

0

201

0

MF

201

0

MF

201

C5623

1000PF

10%
16V
X7R
201

1 2

1/20W

201

NOSTUFF

NOSTUFF

NOSTUFF

4

NOSTUFF

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

8 7 5 4 2 1

5%
MF

VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

CLK_CAM_RF_FILT

NOSTUFF

1

C5600

1000PF

10%
16V

2

X7R
201

MIPI0C_CAM_DATA_N<0>
MIPI0C_CAM_DATA_P<0>

MIPI0C_CAM_CLK_N
MIPI0C_CAM_CLK_P

25 39

25 40

25 40

25 40

25 40

25

25

25

25

CONNECTED BY
PG 54 ALIASES

SENSOR PANEL CONNECTOR

CABLINE-CA CONNECTOR: 518S0787

CONN_PP2V85_CAM_REAR

25

CONN_PP1V8_SENSOR_FILT

25

CONN_CLK_CAM_RF_FILT

25

CONN_ISP_AP_0_SCL

25

CONN_ISP_AP_0_SDA

25

CONN_PM_REAR_CAM_SHUTDOWN

25

CONN_MIPI0C_CAM_DATA_N<0>

25

CONN_MIPI0C_CAM_DATA_P<0>

25

CONN_MIPI0C_CAM_CLK_N

25

CONN_MIPI0C_CAM_CLK_P

25

CONN_IRQ_HALL

25

CONN_I2C1_SDA_1V8

25

CONN_I2C1_SCL_1V8

25

CONN_IRQ_PROX_INT_L

25

CONN_PP3V0_S2R_HALL

25

CONN_IRQ_GYRO_INT2

25

CONN_IRQ_GYRO_INT1

25

CONN_IRQ_ACCEL_INT1_L

25

CONN_IRQ_ACCEL_INT2_L

25

CONN_I2C2_SCL_3V0

25

CONN_I2C2_SDA_3V0

25

CONN_AUD_VOL_DOWN_FTR_L

25

CONN_AUD_VOL_UP_FTR_L

25

CONN_SRL_FTR_L

25

CONN_ONOFF_FTR_L

25

CONN_DMIC_SD_SENSOR

25

CONN_DMIC_SCLK_SENSOR

25

CONN_PP3V0_OPTICAL_SENS

25

36

2 1

CRITICAL

J5600

CABLINE-CA

F-RT-SM

31

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

33
34
35
36
37
38
39
40
41

32

SYNC_MASTER=MARK B.

PAGE TITLE

CONNECTOR: SENSOR PANEL CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-8962

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=N/A

A.0.0

56 OF 106

27 OF 42

SIZE

D

C

B

A

D

345678

2 1

USB

PPVBUS_USB_EMI

32

D

4

39

BI

4

39

BI

C5721

1

2

USB_D_P

USB_D_N

27PF

5%
25V
NP0-C0G
201

MIN_LINE_WIDTH=4.1MM
MIN_NECK_WIDTH=0.2MM

C5722

1

12PF

5%
25V

2

NP0-C0G
201

1

2 3

L5716

90-OHM-50MA

TCM0605

SYM_VER-1

L5757

FERR-70-OHM-4A

1 2

1

R5790

100K

5%
1/20W
MF
201

2

4

D5703

RCLAMP0502N

SLP1210N6

0603

5
2

NOTE:

IO
NC

VOLTAGE=5V
MIN_LINE_WIDTH=4.1MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

2

1

DZ5760

27V-100PF

0402

MAX_NECK_LENGTH=3 MM

1

2

C5750

27PF

5%
25V
NP0-C0G
201

PPVBUS_USB_PT_DK_CON

MAX CONTINUOUS VOLTAGE IS 19V - SPEC IS 16V

VBUS

1

GND

6

IO
NC

USB_PT_DK_CON_D_P

USB_PT_DK_CON_D_N

4
3

NC_D5703_6

29 39

29 39

1

C5783

0.01UF

10%

25V

2

X7R
402

29

ANALOG VIDEO

VIDEO_EMI_CVBS_PB

10 11 40

IN

VIDEO_EMI_C_Y

10 11 40

IN

VIDEO_EMI_Y_PR

10 11 40

IN

OMIT

XW5700

SM

AUDIO_PT_DK_RET

28

1 2

FL5711

80-OHM-0.2A-0.4-OHM

1 2

0201

FL5707

80-OHM-0.2A-0.4-OHM

1 2

0201

FL5708

80-OHM-0.2A-0.4-OHM

1 2

0201

CRITICAL

U5700

NUP412VP5XXG

SOT953

1

2

3 4

VIDEO_PT_DK_CON_CVBS_PB

VIDEO_PT_DK_CON_C_Y

VIDEO_PT_DK_CON_Y_PR

VIDEO_PT_DK_CON_Y_PR

VIDEO_PT_DK_CON_C_Y

VIDEO_PT_DK_CON_CVBS_PB

AV_PT_DK_CON_RET

5

28 29 40

28 29 40

28 29 40

28 29 40

28 29 40

28 29 40

29

JTAG

4

39

IN

4

39

IN

=PP1V8_S2R_MISC

5

32

1

2

JTAG_AP_TCK
JTAG_AP_TMS

DEVELOPMENT_JTAG

C5730

0.1UF

10%

6.3V
X5R
201

R5730
R5731

DEVELOPMENT_JTAG

1

R5795

523K

1%
1/32W
MF
01005

2

U5730_IN

DEVELOPMENT_JTAG

1

R5796

1.00M

1%
1/32W
MF
01005

2

DEVELOPMENT_JTAG

1 2
1 2

DEVELOPMENT_JTAG

DEVELOPMENT_JTAG

U5730

MAX9061

UCSP

B1

REF

A2

IN OUT

PT_DK_CON_P14

0

PT_DK_CON_P17

0

A1

(JTAG_TCK)

(JTAG_TMS)

RST_AP_L

OUT

GND

B2

NOTE:
JTAG_AP_TMS = 3.3V: U5730’S IN = 2.13V
JTAG_AP_TMS = 1.8V: U5730’S IN = 1.16V

29

29

D

4

31 35

LINEOUT

L5760

FERR-120-OHM-1.5A

AUDIO_EMI_LO_L

21

ACCESSORY

VOLTAGE=3.3V

2

1

1

2

R5752

100K

1 2

201

1%MF

1

2

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.1MM
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR

DZ5790

8V-100PF

0201

R5750

220K

5%
1/20W
MF
201

C5760

0.01UF

10%
16V

X5R-CERM

0201

R5720

0

1 2

5%

1/20W

MF

201

ACC_PT_DK_CON_PP3V3

1

2

C5751

27PF

5%
25V
NP0-C0G
201

1

C5782

0.01UF

10%
10V

2

X5R
201

29

2

DZ5753

6.8V-100PF

0201

1

C

0201

14.2V-6PF

DZ5752

A

A1A2B1

DZ5751

USBULC6-2F3

BGA

B2

ACC_PT_DK_CON_DET_L

1

C5752

27PF

5%
25V

2

NP0-C0G
201

ACC_PT_DK_CON_ID

1

C5753

27PF

5%
25V

2

NP0-C0G
201

NOSTUFF

1

C5754

27PF

5%
25V

2

NP0-C0G
201

29

29

29 39

L5714

FERR-120-OHM-1.5A

11 39

IN

1 2

0402

0.095 OHM DCR

=PPVCC_MAIN_DOCK

32

R5751

10K

1 2

5%

1/20W

MF

201

R5753

10K

1 2

5%

1/20W

MF

201

USB_FS_N_ACC_TX

1/20W

=PP3V3_PORT_ACC

32

C

PORT_DOCK_ACC_DET_L

35

OUT

PLACE BY PMU

PMU_ADC_REF

35

B

PORT_DOCK_ACCID

35

OUT

A

ALTERNATE FOR
PART NUMBER

377S0066377S0107

11 39

OUT

USB_FS_P_ACC_RX

R5721

0

1 2

5%

1/20W

MF

201

ACC_PT_DK_CON_RX

NOSTUFF

1

C5755

27PF

5%
25V

2

NP0-C0G
201

29 39

PART NUMBER

377S0090 377S0081

377S0111 377S0099

155S0625 155S0559

8 7 5 4 2 1

DISPLAYPORT

DP_EMI_TX_P<0>

13 40

IN

DP_EMI_TX_N<0>

13 40

IN

DP_EMI_TX_P<1>

13 40

IN

DP_EMI_TX_N<1>

13 40

IN

DP_EMI_AUX_P

13 40

IN

DP_EMI_AUX_N

13 40

IN

BOM OPTION

D5700,D5701,D5702,D5703

REF DES

DZ5751

DZ5710,DZ5711

L5700,L5701

L5700

12-OHM-100MA-8.5GHZ

TCM0806-4SM

SYM_VER-1

1

2 3

RCLAMP0502N

L5701

12-OHM-100MA-8.5GHZ

TCM0806-4SM

SYM_VER-1

1

2 3

RCLAMP0502N

L5702

90-OHM-50MA

TCM0605

SYM_VER-1

1

2 3

RCLAMP0502N

COMMENTS:

?

RADAR:8379541

RADAR:8289785

RADAR:8423156

4

D5700

SLP1210N6

4

D5701

SLP1210N6

4

D5702

SLP1210N6

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

DP_PT_DK_CON_TX_P<0>

DP_PT_DK_CON_TX_N<0>

NC_D5700_6

6

VBUS

4

IO

5

IO

2

NC

3

NC

GND

1

DP_PT_DK_CON_TX_P<1>

DP_PT_DK_CON_TX_N<1>

NC_D5701_6

6

VBUS

4

IO

5

IO

2

NC

3

NC

GND

1

DP_PT_DK_CON_AUX_P

DP_PT_DK_CON_AUX_N

NC_D5702_6

6

VBUS

4

IO

5

IO

2

NC

3

NC

GND

1

29 40

29 40

29 40

29 40

29 40

29 40

36

IN

AUDIO_EMI_LO_R

21

IN

AV_EMI_DIFF_SENSE

21

IN

GND_AUDIO_PT_DK

21

IN

FIREWIRE DETECT/ DISPLAYPORT HPD

FW_ZENER_PWR

13 35

OUT

1 2

0402

L5761

FERR-120-OHM-1.5A

1 2

0402

L5762

22-OHM-25%-900MA

1 2

0201

L5763

30-OHM-1.7A

1 2

0402

2

DZ5720

GDZT2R5.1B

GDZ-0201

1

SYNC_MASTER=JAMES

PAGE TITLE

AUDIO_PT_DK_CON_LO_L

2

DZ5710

UCLAMP0511Z

0201

1

AUDIO_PT_DK_CON_LO_R

2

DZ5711

UCLAMP0511Z

0201

1

2

DZ5712

6.8V-100PF

0201

1

R5710

47K

1 2

5%

1/20W

MF

201

MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.07MM

MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.07MM

AV_PT_DK_CON_DIFF_SENSE

MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.07MM

R5740

1

100

5%
1/20W
MF
201

2

AUDIO_PT_DK_RET

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

FW_PT_DK_CON_PWRACC_PT_DK_CON_TX

1

C5780

0.01UF

10%
50V

2

X7R
402

IO FLEX: DOCK COMPONENTS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

29

29

DRAWING NUMBER

051-8962

REVISION

BRANCH

PAGE

57 OF 106

SHEET

28 OF 42

29

28

29

SYNC_DATE=N/A

A.0.0

SIZE

C

B

A

D

345678

2 1

D

PN 516S0817 (PLUG - MALE)

CRITICAL

J5900

AXK844135WG

M-ST-SM

1

PPVBUS_USB_PT_DK_CON

C

(DP_HPD)

(JTAG_TCK)
(JTAG_TMS)

28

VIDEO_PT_DK_CON_CVBS_PB

28 40

IN

VIDEO_PT_DK_CON_C_Y

28 40

IN

VIDEO_PT_DK_CON_Y_PR

28 40

IN

28

OUT

28

OUT

28

28

IN

28

IN

28 39

OUT

28 39

IN

ACC_PT_DK_CON_ID
FW_PT_DK_CON_PWR
ACC_PT_DK_CON_PP3V3

PT_DK_CON_P14
PT_DK_CON_P17
ACC_PT_DK_CON_RX
ACC_PT_DK_CON_TX

2

3

4

56
78

10

9
1112
1314
1516
1718
19

20

2122
2324
2526
2728
29

30

3132
3334
3536
3738
39

40

4142
4344

USB_PT_DK_CON_D_P
USB_PT_DK_CON_D_N

DP_PT_DK_CON_TX_P<0>
DP_PT_DK_CON_TX_N<0>

DP_PT_DK_CON_TX_P<1>
DP_PT_DK_CON_TX_N<1>

AV_PT_DK_CON_DIFF_SENSE

AUDIO_PT_DK_CON_LO_L
AUDIO_PT_DK_CON_LO_R

AV_PT_DK_CON_RET

ACC_PT_DK_CON_DET_L

DP_PT_DK_CON_AUX_P
DP_PT_DK_CON_AUX_N

HOME_L

28 39

BI

28 39

BI

28 40

IN

28 40

IN

28 40

IN

28 40

IN

28

OUT

28

IN

28

IN

28

OUT

28

OUT

28 40

BI

28 40

BI

5

29 35

OUT

D

C

SIZE

B

A

D

B

HOME_L

5

29 35

OUT

2

DZ5750

6.8V-100PF

0201

1

A

8 7 5 4 2 1

36

SYNC_MASTER=JAMES

PAGE TITLE

IO FELX: B2B Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

59 OF 106

SHEET

29 OF 42

X23 WIFI/BT CONNECTOR

345678

2 1

D

L6000

1 2

1

2

0603

=PPVCC_MAIN_WL

32

PPVCC_MAIN_WL_CONN

VOLTAGE=4.7V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

22-OHM-25%-0.5A-0.20DCR

C6000

68PF

5%

25V

CERM
201

D

516S0884

1 2

1

2

L6001

0402

=PP1V8_S2R_WL

32

C

C

RST_WLAN_L

35

IN

PM_WLAN_HOST_WAKE

35

OUT

RST_BT_L

35

IN

PM_BT_HOST_WAKE

35

OUT

PM_BT_WAKE

5

IN

UART_AP_3_RXD

10

OUT

UART_AP_3_TXD

10

IN

UART_AP_3_CTS_L

10

OUT

UART_AP_3_RTS_L

10

IN

IN
IN
OUT
IN

I2S_AP_2_BCLK
I2S_AP_2_DOUT

I2S_AP_2_DIN

I2S_AP_2_LRCK

5

19 39

5

19 39

5

19 39

5

19 39

J6000

AXT530224

F-ST-SM
1
3
5
7
9

11
13
15
17
19
21
23
25
27
29

PP1V8_S2R_WL_CONN

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

SDIO_WL_CLK

SDIO_WL_CMD
SDIO_WL_DATA<3>
SDIO_WL_DATA<2>
SDIO_WL_DATA<1>
SDIO_WL_DATA<0>

CLK_32K_WLAN

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

22-OHM-25%-0.4A-0.35DCR

C6001

68PF

5%

25V

CERM
201

5

40

IN

5

40

BI

5

40

BI

5

40

BI

5

40

BI

5

40

BI

35 39

IN

SIZE

B

A

D

B

A

SYNC_MASTER=MIKE

PAGE TITLE

CONNECTOR: X23 WIFI/BT

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

60 OF 106

SHEET

30 OF 42

X24 CELLULAR/GPS CONNECTOR

345678

2 1

D

D

998-3141

J6100

CELL-MODULE-X24

HB-SM

SNSV_BATT_POS_ACF

1

R6100

255K

1%
1/32W
MF
01005

35

ADC_IN7

OUT

NOSTUFF

1

C6100

0.01UF

10%

6.3V

2

X5R

01005

2

1

R6101

255K

1%
1/32W
MF
01005

2

C

B

MIN_NECK_MIDTH SHOULD BE 0.2MM

=BATT_POS_F_3G

32

4

28 35

OUT

5

IN

35

IN

5

OUT

5

IN

5

OUT

5

40

IN

5

OUT

5

40

IN

5

40

IN

5

40

OUT

5

OUT

35

OUT

35

IN

11 39

BI

11 39

BI

10

IN

10

OUT

10

OUT

10

IN

10

OUT

10

IN

=PP1V8_S2R_GPS

32

5

IN

5

IN

10

OUT

10

IN

10

OUT

10

IN

5

IN

5

OUT

35 39

IN

25 26

25

IN

25

OUT

26

OUT

25

BI

RST_AP_L
PM_RADIO_ON
RST_BB_PMU_L
GSM_TXBURST_IND
RST_BB_L
RST_DET_L

SPI_IPC_MRDY
SPI_IPC_SRDY
SPI_IPC_SCLK
SPI_IPC_MOSI

SPI_IPC_MISO
IPC_GPIO
PM_BB_HOST_WAKE

BB_VBUS_DET

USB_BB_D_P
USB_BB_D_N

UART_AP_1_RXD
UART_AP_1_TXD
UART_AP_1_CTS_L
UART_AP_1_RTS_L
UART_AP_2_RXD
UART_AP_2_TXD

RST_GPS_L
PM_GPS_STANDBY_L
UART_AP_4_RXD
UART_AP_4_TXD
UART_AP_4_CTS_L
UART_AP_4_RTS_L
GPS_SYNC
IRQ_GPS_INT_L

CLK_32K_GPS

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

PPVSIM
SIM_DET
SIM_RST
SIM_CLK
SIM_IO

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.1 MM

OMIT

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

C

B

A

SYNC_MASTER=MIKE

PAGE TITLE

CONNECTOR: X24 CELLULAR/GPS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

61 OF 106

SHEET

31 OF 42

SIZE

A

D

POWER CONN / ALIAS

345678

2 1

LDO RAILS

PROGRAMMABLE ON/OFF

PP1V2_SOC

34

MAKE_BASE=TRUE

PP3V0_S2R_HALL

34

D

C

B

MIN_NECK_MIDTH SHOULD BE 0.2MM

MAKE_BASE=TRUE
VOLTAGE=3.0V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP1V7_VA_VCP

MAKE_BASE=TRUE
VOLTAGE=1.7V
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP3V0_VIDEO

34

MAKE_BASE=TRUE
VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP3V0_OPTICAL

34

MAKE_BASE=TRUE
VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP3V2_SD

34

BI

MAKE_BASE=TRUE
VOLTAGE=3.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP3V3_ACC

34

MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP3V0_VIDEO_BUF

34

MAKE_BASE=TRUE
VOLTAGE=3.0V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP3V2_S2R_USBMUX

34

MAKE_BASE=TRUE
VOLTAGE=3.2V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP3V0_IO

34

MAKE_BASE=TRUE
VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP2V85_CAM

34

MAKE_BASE=TRUE
VOLTAGE=2.85V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP3V0_GRAPE

34

MAKE_BASE=TRUE
VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP1V1

34

MAKE_BASE=TRUE
VOLTAGE=1.1V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.1 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=0.8 MM

PP1V8_ALWAYS

34

MAKE_BASE=TRUE
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

=PP3V0_S2R_HALL
=PP3V0_S2R_HALL_CHSW

=PP1V7_VA_VCP

=PP3V0_VIDEO_BUFFER
=PP3V0_VIDEO_H4

=PP3V0_OPTICAL

=PP3V3_PORT_ACC

=PP3V0_VIDEO_BUF

=PP3V2_S2R_USBMUX

=PP3V0_IO_H4
=PP3V0_IO_MISC

=PP2V85_CAM

=PP3V0_GRAPE

=PP3V0_GRAPE_Z1
=PP3V0_GRAPE_Z2
=PP3V0_GRAPE_MARIO1

=PP1V1_PLL_H4
=PP1V1_MIPI_H4
=PP1V1_DPORT_H4
=PP1V1_USB_H4
=PP1V1_MIPI_PLL_H4

=PP1V8_ALWAYS

27

23

19 34

11

7

5

28

11

11

7 9

13

26 27

17 18

18

18

17

4

7

7

4

4

5

26 27

MIN_NECK_MIDTH SHOULD BE 0.2MM

MIN_NECK_MIDTH SHOULD BE 0.2MM

MIN_NECK_MIDTH SHOULD BE 0.2MM

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.1 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=0.8 MM

PP1V2_CPU

34

MAKE_BASE=TRUE
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.1 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=0.8 MM

PP1V2_S2R

34

MAKE_BASE=TRUE
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.1 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=0.8 MM

PP1V8_S2R

34

MAKE_BASE=TRUE
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP1V8

34

MAKE_BASE=TRUE
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=0.8 MM

PP3V3_OUT

34

MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=0.8 MM

PPLED_OUT

35

MAKE_BASE=TRUE
VOLTAGE=20.4V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

PP3V3_MLC_OUT

36

MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

PP1V2

34

MAKE_BASE=TRUE
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.1 MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=0.8 MM

BUCK RAILS

=PPVDD_SOC_H4

MIN_NECK_MIDTH SHOULD BE 0.2MM

=PPVDD_CPU_H4

MIN_NECK_MIDTH SHOULD BE 0.2MM

=PP1V2_S2R_H4

MIN_NECK_MIDTH SHOULD BE 0.2MM

=PP1V8_S2R_H4
=PP1V8_S2R_WL
=PP1V8_S2R_GPS
=PP1V8_S2R_MISC

=PP1V8_CAM

=PP1V8_SENSOR
=PP1V8_AUDIO
=PP1V8_H4
=PP1V8_VDDIO18_H4
=PP1V8_MIPI_H4
=PP1V8_DPORT_H4

=PP3V3_NAND

=PP3V3_USB_H4
=PP3V3_MLC_HI

=PP3V3_LCD
=PP3V3_NAND_H4

=PPLED_REG

NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

=PP3V3_MLC

=PP1V2_VDDQ_H4

=PP1V2_VDDIOD_H4

=PP1V2_HSIC_H4

GND

MAKE_BASE=TRUE
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.10MM
NET_SPACING_TYPE=GND

MAX_NECK_LENGTH=5 MM

9

9

8

8

30

31

5

26

27

19

4 5 7

8 9

7

7

12

4

36

16

10

16

14 16

8

8

4

CHARGER MAIN

PPVCC_MAIN

34 35

MAKE_BASE=TRUE
VOLTAGE=4.7V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

=PPVCC_MAIN_AUDIO
=PPVCC_MAIN_WL
=PPVCC_MAIN_DOCK
=PPVCC_MAIN_LED

19 20

30

28

35

D

BATTERY

PPBATT_VCC

34 37

MAKE_BASE=TRUE
VOLTAGE=4.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
NET_SPACING_TYPE=PWR

28

MAX_NECK_LENGTH=1.7 MM

=BATT_POS_F_3G

=BATT_POS_CONN

31

33

C

10 13

PPVBUS_USB_EMI

28

USB POWER INPUT

PPVBUS_USB_DCIN

MAKE_BASE=TRUE

34

B

A

8 7 5 4 2 1

36

SYNC_MASTER=YOSH

PAGE TITLE

POWER: ALIASES

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

73 OF 106

SHEET

32 OF 42

SIZE

A

D

345678

2 1

D

C

D

C

XW7520

MIN_NECK_MIDTH SHOULD BE 0.2MM

BATT_SNS

34

NET_SPACING_TYPE=ANLG
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.15 MM

=BATT_POS_CONN

32

B

35

BATTERY_SWI

5

BI

BATTERY_NTC

35

BI

NET_SPACING_TYPE=ANLG

NOTE: GET RID OF THE

240-OHM-0.2A-0.8-OHM

RES AFTER BRINGUP

A

8 7 5 4 2 1

SM

1 2

FL7500

1 2

0201-1

R7541

0

1 2

MF

5%

201

1/20W

C7522

33PF

NP0-C0G

TP7500

A

TP-P55

NOSTUFF

1

5%

25V

2

201

1

C7523

33PF

NP0-C0G

CRITICAL

J7500

BATT-K93

F-ST-SM

7
BATT_SWI_CONN
BATT_NTC_CONN

NET_SPACING_TYPE=ANLG

C7524

1000PF

1

10%
16V

2

X7R
201

C7525

82PF

CERM
0201

1

5%

25V

2

TP7501

1

A

TP-P55

NOSTUFF

TP7502

1

A

TP-P55

NOSTUFF

TP7503

1

A

TP-P55

NOSTUFF

1

5%

25V

2

201

5

1

POS

2

HDQ

3

THERM

4

GND

6

8

APN:516-0240

NOTE:
VERIFY PINOUT OF

BATTERY CONNECTOR
VERIFY MOUNTING CONN TO GND

SYNC_MASTER=YOSH

PAGE TITLE

POWER: BATTERY CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-8962

REVISION

BRANCH

PAGE

75 OF 106

SHEET

33 OF 42

SYNC_DATE=N/A

A.0.0

SIZE

B

A

D

36

D

MOSFET
CHANNEL
RDS(ON)
IMAX
VGS MAX

C

B

A

PLACEMENT_NOTE=PLACE NEAR L8225.1

CRITICAL

C8166

150UF-0.035OHM

POLY-TANT

CASE-B15G-SM

NOTE: CONCERNED ABOUT ESR > 20MOHM

345678

CRITICAL

CRITICAL

C8145

2.2UF

6.3V

CRITICAL

C8152

4.7UF

6.3V

X5R-CERM1

36

L8100

1 2

PST25201B-SM

CRITICAL

L8101

1 2

PST25201B-SM

XW8103

1 2

SM

NOSTUFF

CRITICAL

L8105

1 2

PST25201B-SM

CRITICAL

L8107

1 2

PST25201B-SM

CRITICAL

L8110

1 2

PST25201B-SM

XW8113

1 2

SM

NOSTUFF

1

C8138

1UF

20%

6.3V

2

X5R
0201

CRITICAL

1

C8144

10%

2

X5R

CERM-X5R

402

CRITICAL

1

C8151

20%

2

402

2.2UH-20%-1.85A-80MOHM

2.2UH-20%-1.85A-80MOHM

BUCK4_LXL

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

BUCK4_LXM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

BUCK4_FB

NET_SPACING_TYPE=ANLG
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

2.2UH-20%-1.85A-80MOHM

2.2UH-20%-3.3A-0.064OHM

BUCK5_LX

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

BUCK5_FB

NET_SPACING_TYPE=ANLG
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

1

C8140

1UF

10%

6.3V

2

CERM
402

CRITICAL

1

6.3V
0402

1UF

6.3V
CERM

C8147

2.2UF

20%

2

1

10%

2

402

10UF

1

C8139

1UF

10%

6.3V

2

CERM
402

10%

6.3V
X5R
402

CRITICAL

1

C8102

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C8107

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

L8115

1 2

PST25201B-SM

XW8117

1 2

NOSTUFF

CRITICAL

L8119

1 2

PST25201B-SM

CRITICAL

L8121

1 2

PST25201B-SM

XW8126

1 2

NOSTUFF

CRITICAL

L8128

1 2

PIME051E-SM

DCR=64MOHM MAX

XW8132

1 2

SM

NOSTUFF

1

2

1

2

2.2UH-20%-1.85A-80MOHM

PART#

QTY

343S0542

PART NUMBER

NOSTUFF

1

R8116

FDMC6676BZ
P-TYPE
27 MOHM @-4.5V

470K

1%
1/20W
MF
201

2

6.9 A
+/- 25V

CRITICAL

Q8123

FDMC6676BZ

MLP3.3X3.3

PPVBUS_USB_DCIN

32

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=6V

123

S

G

4

D

5

R8130

220K

1/20W

USB REVERSE VOLTAGE PROTECTION

NOTE: FOR NO BATTERY SITUATION

PPBATT_VCC

6.3V

20%

1

2

32 34 37

CRITICAL

150UF-0.035OHM

CASE-B15G-SM

C8165

POLY-TANT

6.3V

20%

NOSTUFF
CRITICAL

C8100

22UF

20%

6.3V

X5R-CERM

603

R8100

0.5

1/16W

402

1

2

1

2

1

1%
MF

2

CRITICAL

1

C8154

10UF

20%

6.3V

2

X5R
603

CRITICAL

1

C8101

22UF

20%

6.3V

2

X5R-CERM

603

BATT_POS_RC

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=4.6V

CRITICAL

1

C8155

10UF

20%

6.3V

2

X5R
603

DESCRIPTION

IC,PMU,ALISON,D1946A2,OTPXX,UFBGA292

1

ALTERNATE FOR
PART NUMBER

197S0299197S0392

1 2

VBUS_PROT_G

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=ANLG

1

1%
MF

201

2

BOM OPTION

DZ8120

BZT52C10LP

LLP

CRITICAL

NOTE: 10V ZENER

PPVBUS_PROT

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.25MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=6V

PPVCC_MAIN

32 34 35

PPBATT_VCC

32 34 37

REFERENCE DESIGNATOR(S)

U8100

REF DES

COMMENTS:

ALT FOUNDRY

Y8138

4

G

ACT_DIO

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.1 MM
NET_SPACING_TYPE=ANLG

CRITICAL

1

C8124

2.2UF

10%
25V

LAYOUT NOTE: PLACE

2

X5R-CERM

805

RIGHT AT THE PIN

PP1V8_S2R

32 34

1

2

1 2 3

S

D

RDSON=0.0136@VGS=-2.5V

5

ID=12.0A

4

C8135

1UF

10%

6.3V
CERM
402

(PLACE ONE 1UF CAP AT EACH VDD INPUT)

CRITICAL

1

C8156

2

4.7UF

20%

6.3V
X5R-CERM1
402

CRITICAL

1

C8157

4.7UF

20%

6.3V

2

X5R-CERM1
402

CRITICAL

1

C8158

4.7UF

20%

6.3V

2

X5R-CERM1
402

CRITICAL

1

C8159

4.7UF

20%

6.3V

2

X5R-CERM1
402

CRITICAL

1

2

CRITICAL BOM OPTION

CRITICAL

TABLE_ALT_HEAD

TABLE_ALT_ITEM

CRITICAL

L8112

2.2UH-3.5A-54M-OHM

1 2

PIME061E-SM

DCR=54MOHM MAX

D8100

SOD-123W

PMEG4030ER

SHORT-0201

NOSTUFF

PPVCC_MAIN
PP1V2_S2R

1

C8136

1UF

10%

6.3V

2

CERM
402

C8142

18PF

25V

NP0-C0G

201

CRITICAL

XW8114

NET_SPACING_TYPE=CRYSTAL

32.768K-20PPM-12.5PF

PMU_XTAL

1

5%

2

CRITICAL

Q8104

FDMC6683

MLP3.3X3.3

PPVBUS_USB

32 34 35

32 34

VCC_MAIN BYPASS

TOTAL CAPS = ~400UF

CRITICAL

1

C8160

4.7UF

20%

6.3V
X5R-CERM1
402

C8161

4.7UF

20%

6.3V

2

X5R-CERM1
402

SW_CHGA

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

2

NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

1

12

1

C8125

10UF

10%
25V

2

X5R
805

CRITICAL

LAYOUT NOTE: PLACE

RIGHT AT THE PIN

CRITICAL

Y8138

1 2

CRITICAL

1

C8162

4.7UF

20%

6.3V

2

X5R-CERM1
402

TABLE_5_HEAD

TABLE_5_ITEM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

33

NC_CHGB

BATT_SNS

NC_VBUS_A_OV_N

PMU_VCENTER

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.25MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=6V

NC_VBUS_B_OV_N

PMU_EXTAL

2012

CRITICAL

1

C8130

4.7UF

20%

6.3V

2

X5R-CERM1
402

OMIT

U8100

ALISON-A0-OTPXX

D1946A0-110-00

UFBGA
G24
G25
H24
H25
L25

VBAT

P25

IBAT_S

N17
P17
N18
P18
P24

ACT_DIO

F24
F25
A22
A23
B24

VBUS_A_OV_N

J24
J25
P22
P23
N22

VBUS_B_OV_N

A10
B10

A3
B3
B7
B6

A17

VDD_BUCK3

A13
B13

E1
E2
G1
G2
H2

G22

VCC_MAIN_S

N19
P19
N20
P20

K2

VDD_LDO1_6

L4

VDD_LDO2

N9

VDD_LDO3_5_8

N4

VDD_LDO4_7

N10

VDD_LDO9

N6

VDD_LDO10

L2

VDD_LDO11

N7

VDD_LDO12

P1

XTAL1

P2

XTAL2

NET_SPACING_TYPE=CRYSTAL

1

C8143

18PF

5%
25V

2

NP0-C0G
201

(SYM 2 OF 3)

CHG_A_LX

CHG_B_LX

IBAT

VCENTER_A

VBUS_A

VCENTER_B

VBUS_B

VDD_BUCK0

VDD_BUCK2

VDD_BUCK4

VDD_BUCK5

VDD_BUCK5_BYP

VCC_MAIN

BUCK

USB/BAT

LDO

SWITCH POWER

VBUCK0_SW0_G
VBUCK0_SW0_S

LDO INPUT

XTAL VCC-MAIN

(DISTRIBUTED AND NO DE-RATING)

CRITICAL

1

C8131

1.0UF

20%

6.3V

2

X5R
0201-MUR

1

C8163

82PF

5%
25V

2

CERM
0201

PPVCC_MAIN

1

C8164

18PF

5%
25V

2

NP0-C0G
201

32 34 35

BUCK0_LXL
BUCK0_LXM

BUCK0_FB

BUCK2_LXL

BUCK2_LXM
BUCK2_LXR

BUCK2_FB

BUCK3_LX
BUCK3_FB

BUCK4_LXL
BUCK4_LXM

BUCK4_FB

BUCK5_LX

BUCK5_BYP

BUCK5_FB

VLDO10
VLDO11
VLDO12
ON_BUF

VBUCK4

CPU1V2_SW

DSP_SW

VBUCK3

CPU1V8_SW

WDIG_SW

VLDO1
VLDO2
VLDO3
VLDO4
VLDO5
VLDO6
VLDO7
VLDO8
VLDO9

VPUMP

A11
A9
D9

A7
B8
A6
A4
D7

A16
D16

A14
B11
D14

F1
F2
H1
J1

(BYPASS RON=0.14 OHM MAX)

J2
G4

(150MA; 2.5-3.55V)

L1

(100MA; 1.65-1.805V; BUCK3)

P3

(50MA; 2.5-3.3V)

P9

(100MA; 1.8-3.3V)

N5

(300MA; 2.5-3.6V)

P10

(150MA; 2.5-3.6V)

K1

(50MA; 1.5-3.3V)

P4

(10MA; 2.0-3.55V)

P8

(300MA; 1.2-3.0V)

P11

(200MA; 2.5-3.55V)

P5

(200MA; 1.7-3.0V)

M1

(150MA; 0.6-1.3V)

P6
M2

B17

(RON=0.1 OHM MAX)

A18

(RON=1 OHM MAX)

B20

A19

(RON=0.2 OHM MAX)

A20

(RON=0.5 OHM MAX)

B19

B21

NC_PMU_VBUCK0_SW0_G

A21

NC_PMU_VBUCK0_SW0_S

B18

PMU_VPUMP

1

C8137

0.01UF

10%

6.3V

2

X5R

01005

PP3V0_GRAPE

32 34

PP1V7_VA_VCP

32 34

PP3V0_VIDEO

32 34

PP3V0_OPTICAL

32 34

PP3V2_SD

32 34

PP3V3_ACC

32 34

PP3V0_VIDEO_BUF

32 34

CRITICAL

C8150

2.2UF

10%

6.3V
X5R
402

PP3V2_S2R_USBMUX

32 34

PP3V0_IO

32 34

PP3V0_S2R_HALL

32 34

PP2V85_CAM

32 34

PP1V1

32 34

PP1V8_ALWAYS

32 34

C8169

0.22UF

20%

6.3V
X5R

0201

PP3V0_GRAPE

PP1V7_VA_VCP

PP3V0_VIDEO

PP3V0_OPTICAL

PP3V0_VIDEO_BUF

PP3V2_S2R_USBMUX

PP3V0_S2R_HALL

PP1V8_ALWAYS

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=4.6V

LDO BYPASS

CRITICAL

1

C8149

2.2UF

10%

6.3V

2

X5R
402

CRITICAL

1

C8168

2.2UF

10%

6.3V

2

X5R
402

PP3V2_SD

PP3V3_ACC

PP3V0_IO

PP2V85_CAM

PP1V1

CRITICAL

1

C8148

4.7UF

2

X5R-CERM1

CRITICAL

1

C8167

2.2UF

2

6.3V

6.3V

20%

402

10%
X5R

402

32 34

32 34

32 34

32 34

32 34

32 34

32 34

32 34

32 34

32 34

32 34

32 34

32 34

1

2

1

2

CRITICAL

C8146

2.2UF

CRITICAL

C8153

2.2UF

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

2.2UH-20%-1.85A-80MOHM

BUCK0_LXM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

BUCK0_FB

NET_SPACING_TYPE=ANLG
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

2.2UH-20%-1.85A-80MOHM

BUCK2_LXL

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

2.2UH-20%-1.85A-80MOHM

BUCK2_LXM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

2.2UH-20%-1.85A-80MOHM

BUCK2_LXR

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

BUCK2_FB

NET_SPACING_TYPE=ANLG
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

BUCK3_LX

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

BUCK3_FB

NET_SPACING_TYPE=ANLG
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

1

10%

6.3V
2

X5R
402

1

10%

6.3V
2

X5R
402

8 7 5 4 2 1

2 1

CRITICAL

1

C8103

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C8108

22UF

20%

6.3V

2

X5R-CERM
603

SM

SM

C8141

1UF

10%

6.3V
CERM
402

SYNC_MASTER=YOSH

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

ADDITIONAL DISTRIBUTED
25UF (NO DE-RATING)

ADDITIONAL DISTRIBUTED
30UF (NO DE-RATING)

1

C8117

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C8121

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C8119

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

ADDITIONAL DISTRIBUTED:
PP1V2: 30UF (NO DE-RATING)
PP1V8: 6UF (NO DE-RATING)

POWER: PMU

Apple Inc.

R

PP1V2_CPUBUCK0_LXL

PP1V2_SOC

PP1V8_S2R

ADDITIONAL DISTRIBUTED
14UF (NO DE-RATING)

1

C8118

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

PP1V2_S2R

ADDITIONAL DISTRIBUTED
20UF (NO DE-RATING)

1

C8122

10UF

20%

6.3V

2

X5R
603

CRITICAL

PP3V3_OUT

ADDITIONAL DISTRIBUTED
47UF (NO DE-RATING)

1

C8120

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

PP1V2_S2R

PP1V8_S2R

PP1V8_GRAPE

PP1V2

DSP_SW

PP1V8

32

32

32 34

32 34

32

32 34

32

TP8133

1

TP

32 34

32

TP8101

1

TP

TP-P55

NOSTUFF

TP-P55

NOSTUFF

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

81 OF 106

SHEET

34 OF 42

SIZE

D

C

B

A

D

345678

1

1

D

1

C8206

0.01UF

10%

6.3V

2

X5R
01005

FW_ZENER_PWR

13 28

IN

HOME_L

5

29

IN

ONOFF_L

5

25

IN

SRL_L

5

25

IN

PORT_DOCK_ACC_DET_L

28

IN

PORT_DOCK_ACCID

28

IN

USB_BRICKID

4

IN

ADC_IN7

31

IN

1

CRITICAL

R8216

10KOHM-1%

1

C8215

100PF

5%

6.3V

2

C

CERM

01005

BOARD_TEMP1_N

0201

2

C8221

100PF

5%

6.3V
CERM

01005

XW8200

1 2

SM

NOSTUFF

PLACE CLOSE TO PMU

32

32

B

1

CRITICAL

1

2

2

BOARD_TEMP2_N

PLACE CLOSE TO PMU

=PPVCC_MAIN_LED

1

C8226

10UF

20%
10V

2

X5R
603

PPLED_OUT

CRITICAL

1

C8233

22UF

20%
25V

2

X5R-CERM
0805

R8222

10KOHM-1%

0201

C8217

100PF

5%

6.3V
CERM

01005

XW8201

1 2

SM

NOSTUFF

4.7UH-3.2A

1 2

DCR=106MOHM MAX

1

2

BOARD_TEMP3_N

CRITICAL

L8225

PIME051E-SM

1

C8234

2

1

CRITICAL

2

PLACE CLOSE TO PMU

1UF

10%
25V
X5R
402

R8218

10KOHM-1%

0201

C8223

100PF

5%

6.3V
CERM

01005

XW8202

1 2

SM

NOSTUFF

CRITICAL

D8228

PMEG4010BEA

1 2

SOD-323

1

C8235

1UF

10%
25V

2

X5R
402

NOTE: TDEV4 NTC ON PANEL

1

2

BOARD_TEMP4_N

16

PLACE CLOSE TO PMU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

1

C8232

1UF

10%
25V

2

X5R
402

XW8203

1 2

NOSTUFF

SM

1

C8220

100PF

5%

6.3V
2

CERM

01005

PLACE CLOSE TO PMU

RESISTOR FOR TEMP CALIBRATION

DWI NAMING RELATIVE TO AP

WLED_LX

LED_IO_1

16

OUT

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

LED_IO_2

16

OUT

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

LED_IO_3

16

OUT

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

LED_IO_4

16

OUT

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

LED_IO_5

16

OUT

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

LED_IO_6

16

OUT

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

CRITICAL

2

R8219

3.92K

0.1%
402
1/16W
MF

1

1

C8207

0.01UF

10%

2

6.3V
X5R

01005

(DOCK CONN)
(BETWEEN WLED AND CHARGER)
(H4P)
(PANEL)

R8227

1.00

1 2

1%

1.00

1/20W

201

1.00

1/20W

201

1.00

1/20W

201

1%

MF

1%

MF

1%

MF

1/20W

MF

201

R8232

1.00

1 2

1%

1/20W

MF

201

R8239

1.00

1 2

1%

1/20W

MF

201

R8231

1 2

R8235

1 2

R8240

1 2

1

2

16

33

IN

5

IN

37

IN

4

IN

4

28 31

OUT

5

OUT

5

10 19 39

IN

5

10 19 39

BI

5

39

IN

5

39

IN

5

39

OUT

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

PPVCC_MAIN

R8202

220K

1%
1/20W
MF
201

PMU_ACC_DET_B

BOARD_TEMP1
BOARD_TEMP2
BOARD_TEMP3
BOARD_TEMP4
BATTERY_NTC
PMU_TCAL

PM_KEEPACT
PMU_SHDWN

NET_SPACING_TYPE=ANLG

RST_PMU_IN
RST_AP_L
IRQ_PMU_L

I2C0_SCL_1V8
I2C0_SDA_1V8

DWI_AP_CLK
DWI_AP_DO
DWI_AP_DI

NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

32 34 35

(INTERNAL PULL-DOWN)

NET_SPACING_TYPE=ANLG

NET_SPACING_TYPE=ANLG

NET_SPACING_TYPE=ANLG

NET_SPACING_TYPE=ANLG

NET_SPACING_TYPE=ANLG

(INTERNAL PULL-DOWN)

(INTERNAL PULL-DOWN)

(PULLUP INSIDE H4P)

(INTERNAL PULL-DOWN)
(INTERNAL PULL-DOWN)

LED_IO1_R
LED_IO2_R
LED_IO3_R
LED_IO4_R
LED_IO5_R
LED_IO6_R

PLACEMENT_NOTE=PLACE NEAR U8100.N23

C8201

1UF

1

10%
25V

2

X5R
402

I2C ADDRESS: 0111100X (0X78)

ALISON-A0-OTPXX

D1946A0-110-00

F22

FW_DET

L15

BUTTON1

L16

BUTTON2

L17

BUTTON3

A2

ACC_DET_A

A1

ACC_DET_B

K24

ACC_ID

K22

BRICK_ID

K25

ADC_IN7

M25

TDEV1

M24

TDEV2

L22

TDEV3

L24

TDEV4

N24

TBAT

N25

TCAL

C24

KEEPACT

B1

SHDN

F20

RESET_IN

D24

RESET*

B25

IRQ*

A25

SCL

A24

SDA

F21

DWI_CK

D22

DWI_DI

E21

DWI_DO

N15

WLED_LX

P15
N23

VOUT_LED

L11

WLED1

L12

WLED2

N13

WLED3

P13

WLED4

L13

WLED5

L14

WLED6

OMIT

U8100

UFBGA

(SYM 1 OF 3)

REFERENCES

DIGITAL INPUT

INPUTRESET

ANALOG

GPIO

TEMPERATURE

WDOG

I2C & DWI

ANALOG MUX

LED

BACKLIGHT

LCM/GRAPE

VIB

IREF
VREF

VDD_REF

VDD_REF_A

VDD_RTC
ADC_REF

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18

AMUX_A0
AMUX_A1
AMUX_A2
AMUX_A3
AMUX_AY
AMUX_B0
AMUX_B1
AMUX_B2
AMUX_B3
AMUX_BY

VDD_LCM

VDD_LCM_SW

LCM_LX

VBOOST_LCM

LCM2_EN

VLCM2

VLCM1

VLCM3

N2

PMU_IREF

NET_SPACING_TYPE=ANLG

N1

PMU_VREF

NET_SPACING_TYPE=ANLG

H22

PMU_VDD_REF

NET_SPACING_TYPE=ANLG

K4
P7

PMU_VDD_RTC

NET_SPACING_TYPE=ANLG

N8

NET_SPACING_TYPE=ANLG
MIN_LINE_WIDTH=0.1MM

MIN_NECK_WIDTH=0.1MM

D11
D12
D13
D18
D19
D20
D15
D17
E20
D21
B22
B23
L18
L19
L20
K20
K21
L21

E24
E25
G21
D25
G20
H21
H20
J20
J21
K19

N21

PPVCC_MAIN

P21

PP6V0_LCM_HI

P16

LCM_LX

N12

PP6V0_LCM_VBOOST

C25

NC_LCM2_EN

N11

NC_VLCM2

P12

NC_VLCM1

L10

C8236

2.2UF

X5R-CERM

CLK_32K_PMU
CLK_32K_WLAN
RST_BT_L
RST_WLAN_L
RST_BB_PMU_L
BATTERY_SWI
PM_BT_HOST_WAKE
PM_WLAN_HOST_WAKE
PM_BB_HOST_WAKE
AUD_MIK_HS1_INT_L
DOCK_BB_EN
CLK_32K_GPS
NC_PMU_GPIO13
RST_L63_L
IRQ_HALL
NC_PMU_GPIO16
NC_PMU_GPIO17
NC_PMU_GPIO18

NC_PMU_AMUX_A0
NC_PMU_AMUX_A1
NC_PMU_AMUX_A2
NC_PMU_AMUX_A3
NC_PMU_AMUX_AY
NC_PMU_AMUX_B0
NC_PMU_AMUX_B1
NC_PMU_AMUX_B2
NC_PMU_AMUX_B3
NC_PMU_AMUX_BY

32 34 35

1

1

20%
10V

402

C8237

2

2

10UF

20%
10V
X5R
603

C8204

0.1UF

10%

6.3V

2

X5R
201

1

C8212

0.1UF

10%

6.3V

2

X5R
201

OUT
OUT
OUT
OUT
OUT

IN
IN
IN
IN

IN
OUT
OUT

OUT

IN

(WHAT SIGNALS DO YOU WANT MEASURED?)

2.2UH-1.05A-0.195OHM

MAKE_BASE=TRUE
VOLTAGE=5V
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

(INTERNAL PULLDOWN; TE ENABLE)

R8203

200K

1%
1/20W
MF
201

2

PLACEMENT NOTE: PLACE NEAR PIN K4

1

C8209

1UF

10%

6.3V

2

CERM
402

1

C8210

0.22UF

20%

PLACEMENT NOTE: PLACE NEAR PIN H22

6.3V

2

X5R
0201

PMU_ADC_REF

(1.8 PUSH-PULL)

18 39

(1.8_S2R PUSH-PULL)

30 39

(1.8_S2R;NO PD REQ’D PER BB TEAM)

30

(1.8_S2R;NO PD REQ’D PER BB TEAM)

30

(PU TO BATTERY IN BB)

31

(2.5V ALWAYS ON PU IN BMU)

5

33

(INTERNAL PD)

30

(INTERNAL PD)

30

(INTERNAL PD; CAN’T BE USED FOR 32K CLK OUTPUT)

31

(INTERNAL PU TO PP1V8_S2R)

19

(1.8_S2R;EXT PD BY BB MUXES)

11

(1.8 PUSH-PULL)

31 39

19

(EXTERNAL PU)

25

CRITICAL

(NOTE: 2MHZ)

L8229

1 2

VLS201612E-SM

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE

CRITICAL

PMEG2005AEL

BB_VBUS_DET

1

C8238

1UF

10%

6.3V

2

CERM
402

2 1

ALISON-A0-OTPXX

D1946A0-110-00

B2
B4

E10
E11
E12
E13
E14
E15
E16
E17
E18
E19

F10
F11
F12
F13
F14
F15
F16
F17
F18
F19

G10
G11
G12
G13
G14
G15
G16
G17
G18
G19

H10
H11
H12

C2
D4
D5
D6

E4
E5
E6
E7
E8
E9

F4
F5
F6
F7
F8
F9

VSS

G5
G6
G7
G8
G9

H4
H5
H6
H7
H8
H9

D8230

1 2

SOD882

MAKE_BASE=TRUE
VOLTAGE=6V
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

OUT

1

C8214

1000PF

10%

6.3V

2

X5R
01005

31

28

OMIT

U8100

UFBGA

(SYM 3 OF 3)

VSS_BUCK02

VSS_BUCK2

VSS_BUCK04

VSS_BUCK34

VSS_BUCK5
VSSA_BUCK0

VSSA_BUCK2
VSSA_BUCK3
VSSA_BUCK4
VSSA_BUCK5
PVSS_CHG_A
PVSS_CHG_B

VSS_WLED

VSS_LCM

VSS

A8
B9

A5
B5
A12
B12
A15
B15
D1
D2
D10
D8
B16
B14
C1
E22
J22
N14
P14
N16

N3
L8
L6
K18
K16
K14
K12
K10
K8
K6
J19
J17
J15
J13
J11
J9
J7
J5
H19
H13
H14
H15
H16
H17
H18
J4
J6
J8
J10
J12
J14
J16
J18
K5
K7
K9
K11
K13
K15
K17
L5
L7
L9

D

C

B

A

SYNC_MASTER=YOSH

PAGE TITLE

POWER: PMU

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

82 OF 106

SHEET

35 OF 42

SIZE

A

D

345678

2 1

D

C

K48

CRITICAL

Q8350

CSD68803W15

BGA

S

C3
C2
B3
A3

NOSTUFF

1

R8351

10K

1%
1/20W
MF
201

R8352

2

3

D

2

1 2

Q8351

SSM3K15FV

SOD-VESM-HF

PM_P3V3MLC_EN

B

PM_MLC_PWR_EN

6

IN

1

R8350

100K

1%
1/20W
MF
201

2

1

G S

47K

1/20W

201

1

R8353

39K

1%
1/20W
MF
201

2

R8354

0

1 2

R8354_SS

1%
MF

5%

PM_P3V3MLCWR_SS

1/20W

MF

201

G

A1

D

C8351

0.015UF

1 2

10%

6.3V
X5R

0201

C1
B2
B1
A2

MOSFET
CHANNEL
RDS(ON)
IMAX
VGS MAX

POWER BUDGET

PEAK=0.12A

AVG=0.12A

PP3V3_MLC_OUT=PP3V3_MLC_HI

1

C8352

4.7UF

10%

6.3V

2

X5R-CERM
603

CSD68803

CSD68803W15
P-TYPE
52MOHM @-1.8V
4 A
+/- 6V

1

C8353

1000PF

10%
16V

2

X7R
201

32 32

D

C

B

PART NUMBER

376S0972 376S0612

ALTERNATE FOR
PART NUMBER

BOM OPTION

REF DES

Q8351

COMMENTS:

RADAR:8537160

A

8 7 5 4 2 1

TABLE_ALT_HEAD

TABLE_ALT_ITEM

SIZE

A

D

SYNC_MASTER=YOSH

PAGE TITLE

POWER: 3.3V MLC & 1.2V VR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

83 OF 106

SHEET

36 OF 42

36

345678

2 1

DEBUG RESET ACCESS

D

PLACE OUTSIDE OF CAN?

PPBATT_VCC

32 34

NOSTUFF

1

R9002

1.5K

FORCE_DFU

5

OUT

NOSTUFF

1

R9000

300

5%
1/20W
MF
201

C

2

1%
1/20W
MF
201

2

PWR_ON_LED

NOSTUFF

A

LED9000

RED-50MCD-20MA
0603

K

PMU_SHDWN

35

OUT

NOSTUFF

1

R9001

300

5%
1/20W
MF
201

2

D

C

SIZE

B

A

D

B

A

8 7 5 4 2 1

LEFT AND RIGHT MOUNTING TABS

MT1

BRKT-MTG-TAB-MLB-K93K94

SM

1 2

SYNC_MASTER=MIKE

PAGE TITLE

DEBUG AND MISC

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

90 OF 106

SHEET

37 OF 42

36

345678

2 1

D

C

PLATED THROUGH HOLES

DRILL SIZE: 1.1MM X 0.4MM
PLATING SIZE: 1.4MM X 0.7MM

SL9300

TH-NSP

1

SL-1.1X0.4-1.4X0.7

SL9302

TH-NSP

1

SL-1.1X0.4-1.4X0.7

D

C

SL9303

TH-NSP

1

SL-1.1X0.4-1.4X0.7

SL9304

TH-NSP

B

A

8 7 5 4 2 1

1

SL-1.1X0.4-1.4X0.7

SL9305

TH-NSP

1

SL-1.1X0.4-1.4X0.7

SL9306

TH-NSP

1

SL-1.1X0.4-1.4X0.7

SYNC_MASTER=MIKE

PAGE TITLE

FCT/ICT TEST/BRACKETS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

93 OF 106

SHEET

38 OF 42

36

SIZE

B

A

D

345678

2 1

Clock Signal Constraints

50_OHM_SE

PHYSICAL

50_OHM_SE

PHYSICAL

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

AREA_TYPE

NET_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

AREA_TYPE

*

NET_TYPE

SPACING_RULE_SET

SPACING

CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK

CLK
CLK
CLK
CLK

SPACING_RULE_SET

SPACING

NAND
NAND
NANDNAND_50S
NANDNAND_50S
NANDNAND_50S
NANDNAND_50S

NANDNAND_50S
NANDNAND_50S
NANDNAND_50S
NANDNAND_50S
NANDNAND_50S

NANDNAND_50S
NANDNAND_50S
NANDNAND_50S
NANDNAND_50S
NANDNAND_50S
NANDNAND_50S
NANDNAND_50S
NANDNAND_50S

NANDNAND_50S
NANDNAND_50S
NANDNAND_50S
NANDNAND_50S
NANDNAND_50S
NANDNAND_50S
NANDNAND_50S
NANDNAND_50S
NANDNAND_50S
NANDNAND_50S
NANDNAND_50S

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

5:1_SPACING

CLK_32K_PMU
CLK_32K_WLAN
CLK_32K_GPS
CLK_CAM_FF
CLK_CAM_FF_FILT
CLK_CAM_FF_CONN
CLK_CAM_RF
CLK_CAM_RF_FILT

I2S_AP_0_MCK
I2S_AP_0_MCK_R
CLK_CAM_FF_R
CLK_CAM_RF_R

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

2:1_SPACING

F0AD<7..0>
F0CE0_L
F0CE1_L
F0CE2_L
F0CE3_L
F0CE4_L
F0CE5_L
F0CE6_L
F0CE7_L
F0CLE
F0ALE
F0RE_L
F0WE_L
F0WP_L
F1AD<7..0>
F1CE0_L
F1CE1_L
F1CE2_L
F1CE3_L
F1CE4_L
F1CE5_L
F1CE6_L
F1CE7_L
F1CLE
F1ALE
F1RE_L
F1WE_L
F1WP_L

F2AD<7..0>
F2CE0_L
F2CE1_L
F2CE2_L
F2CE3_L
F2CLE
F2ALE
F2RE_L
F2WE_L
F2WP_L
F3AD<7..0>
F3CE0_L
F3CE1_L
F3CE2_L
F3CE3_L
F3CLE
F3ALE
F3RE_L
F3WE_L
F3WP_L

18 35

30 35

31 35

7

25 26

7

25 27

5

5

7

7

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

USB

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

90_OHM_DIFF

AREA_TYPE

NET_TYPE

PHYSICAL

PHYSICAL_RULE_SET

45_OHM_SE

AREA_TYPE

NET_TYPE

PHYSICAL

I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S

AREA_TYPE

NET_TYPE

PHYSICAL

*

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

*

*

**

USB
USB
USB
USB

USB
USB
USB
USB

USB
USB
USB
USB

SPACING_RULE_SET

5:1_SPACING

SPACING

SPACING_RULE_SET

SPACING

I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S

SPACING_RULE_SET

SPACING

DWI
DWI
DWI

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

USB_D_P
USB_D_N
USB_PT_DK_CON_D_P
USB_PT_DK_CON_D_N

USB_BB_D_P
USB_BB_D_N
USB_FS_D_P
USB_FS_D_N

USB_FS_N_ACC_TX
USB_FS_P_ACC_RX
ACC_PT_DK_CON_TX
ACC_PT_DK_CON_RX

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

3:1_SPACING

TABLE_SPACING_ASSIGNMENT_ITEM

2:1_SPACING

I2S_AP_0_BCLK
I2S_AP_0_LRCK
I2S_AP_0_DIN
I2S_AP_0_DOUT
L63_ASP_SDOUT
I2S_AP_2_BCLK
I2S_AP_2_LRCK
I2S_AP_2_DIN
I2S_AP_2_DOUT
L63_VSP_SDOUT
I2S_AP_3_BCLK
I2S_AP_3_LRCK
I2S_AP_3_DIN
I2S_AP_3_DOUT
L63_XSP_SDOUT

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

2:1_SPACING

DWI_AP_CLK
DWI_AP_DI
DWI_AP_DO

SYNC_MASTER=MIKE

PAGE TITLE

4

4

28 29

28 29

11 31

11 31

4

4

11 28

11 28

28 29

28 29

28

28

11

11

5

19

5

19

5

19

5

19

19

5

19 30

5

19 30

5

19 30

5

19 30

19

5

19

5

19

5

19

5

19

19

5

35

5

35

5

35

CONSTRAINTS: ASSIGNMENTS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

100 OF 106

SHEET

39 OF 42

SIZE

D

C

B

A

D

*

AREA_TYPE

*

PHYSICAL_RULE_SET

*

USB_90D
USB_90D
USB_90D
USB_90D

USB_90D
USB_90D
USB_90D
USB_90D

USB_90D
USB_90D
USB_90D
USB_90D

*

I2S

JTAG

2:1_SPACING

JTAG_AP_TRST_L

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

JTAG_AP_TCK
JTAG_AP_TMS
JTAG_AP_TDI
JTAG_AP_TDO

4

28

4

28

4

10

4

10

4

10

NET_SPACING_TYPE1 NET_SPACING_TYPE2

JTAG

* *

ELECTRICAL_CONSTRAINT_SET

I16

I15

26

27

19

I14
I13

I20

AREA_TYPE

PHYSICAL

NET_TYPE

SPACING_RULE_SET

SPACING

JTAG
JTAG
JTAG
JTAG
JTAG

I2C

50_OHM_SE

PHYSICAL

PHYSICAL

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

AREA_TYPE

**

NET_TYPE

AREA_TYPE

NET_TYPE

SPACING_RULE_SET

1.5:1_SPACING

SPACING

I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C

I2C
I2C

SPACING_RULE_SET

5:1_SPACING

SPACING

CRYSTAL
CRYSTAL
CRYSTAL

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

I2C1_SDA_1V8

I2C1_SCL_1V8
I2C0_SDA_1V8
I2C0_SCL_1V8
I2C2_SDA_3V0
I2C2_SCL_3V0
ISP_AP_0_SCL
ISP_AP_0_SDA
ISP_AP_1_SCL
ISP_AP_1_SDA
I2C2_SCL_3V0_ALS
I2C2_SDA_3V0_ALS

ISP_CAM_1_SCL
ISP_CAM_1_SDA

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

XTAL_24M_I
XTAL_24M_O

24M_O

5

25

5

25

5

10 19 35

5

10 19 35

5

25 26

5

25 26

7

25

7

25

7

26

7

26

25 26

25 26

25 26

25 26

4

4

4

NET_PHYSICAL_TYPE

AREA_TYPE

I2C_50S

NET_SPACING_TYPE1 NET_SPACING_TYPE2

I2C

PHYSICAL_RULE_SET

*

ELECTRICAL_CONSTRAINT_SET

I1

I2

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

I3

I4

I61
I62

I98

I99
I100

I101
I102

I103

I124

I125

XTAL

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CRYSTAL

ELECTRICAL_CONSTRAINT_SET

I92

I90
I93

I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S

I2C_50S
I2C_50S

* *

VREF

5:1_SPACING

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

PPVREF_DDR0_CA
PPVREF_DDR0_DQ
PPVREF_DDR1_CA
PPVREF_DDR1_DQ

8

8

8

8

NET_SPACING_TYPE1 NET_SPACING_TYPE2

VREF

* *

ELECTRICAL_CONSTRAINT_SET

I136
I137

I139

I138

PHYSICAL

AREA_TYPE

NET_TYPE

SPACING_RULE_SET

SPACING

VREF
VREF
VREF
VREF

NET_PHYSICAL_TYPE

USB_90D

NET_SPACING_TYPE1 NET_SPACING_TYPE2

USB

ELECTRICAL_CONSTRAINT_SET

I5

I6

I7
I8

I82
I83

I84

I85

I128

I129

I171
I172

I2S

NET_PHYSICAL_TYPE

I2S_90S

NET_SPACING_TYPE1 NET_SPACING_TYPE2

I2S

I2S

ELECTRICAL_CONSTRAINT_SET

I140

I143

I142
I141

I159

I144
I148

I147

I146
I160

I145
I149

I150

I151
I161

DWI

NET_SPACING_TYPE1 NET_SPACING_TYPE2

DWI

ELECTRICAL_CONSTRAINT_SET

I152
I153

I156

AREA_TYPE

36

NET_PHYSICAL_TYPE

AREA_TYPE

CLK_50S

NET_SPACING_TYPE1 NET_SPACING_TYPE2

D

CLK

PHYSICAL_RULE_SET

*

* *

ELECTRICAL_CONSTRAINT_SET

I63

I162
I81

I88

I89
I95

I96

I94

I130

I131
I157

I158

CLK_50S
CLK_50S
CLK_50S
CLK_50S
CLK_50S
CLK_50S
CLK_50S
CLK_50S

CLK_50S
CLK_50S
CLK_50S
CLK_50S

NAND

NET_PHYSICAL_TYPE

AREA_TYPE

NAND_50S

C

NET_SPACING_TYPE1 NET_SPACING_TYPE2

NAND

ELECTRICAL_CONSTRAINT_SET

I50
I45

I48

I47
I46

I163
I164

I166

I165
I41

I42

I43
I44

I37

I49
I51

I52
I53

I54

I167

B

A

I168

I169

I170
I55

I56

I57
I58

I59

I105

I104

I106
I108

I107

I109
I110

I111
I113

I112

I114
I115

I116

I117
I118

I119

I120
I121

I122
I123

PHYSICAL_RULE_SET

*

*

NAND_50S
NAND_50S

NAND_50S NAND
NAND_50S NAND
NAND_50S NAND
NAND_50S NAND
NAND_50S NAND
NAND_50S NAND
NAND_50S NAND
NAND_50S NAND

NAND_50S NAND
NAND_50S NAND
NAND_50S NAND
NAND_50S NAND
NAND_50S NAND
NAND_50S NAND
NAND_50S NAND
NAND_50S NAND
NAND_50S NAND

NAND_50S NAND

8 7 5 4 2 1

345678

2 1

ANALOG VIDEO CONSTRAINTS

LAYER

VID_50S

NET_SPACING_TYPE1 NET_SPACING_TYPE2

ANALOG_VIDEO

ANALOG_VIDEO

D

ELECTRICAL_CONSTRAINT_SET

I213

I214
I215

I232

I231

I233

I219
I220

I221

I222

I224
I223

ANALOG_VIDEO

ALLOW ROUTE
ON LAYER?

* Y

PHYSICAL

VID_50S
VID_50S
VID_50S

VID_50S
VID_50S
VID_50S

VID_50S
VID_50S
VID_50S

VID_50S
VID_50S
VID_50S

AREA_TYPE

NET_TYPE

MINIMUM LINE WIDTH

**

*

SPACING

ANALOG_VIDEO
ANALOG_VIDEO
ANALOG_VIDEO

ANALOG_VIDEO
ANALOG_VIDEO
ANALOG_VIDEO

ANALOG_VIDEO
ANALOG_VIDEO
ANALOG_VIDEO

ANALOG_VIDEO
ANALOG_VIDEO
ANALOG_VIDEO

MINIMUM NECK WIDTH

=50_OHM_SE

SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

5:1_SPACING

TABLE_SPACING_ASSIGNMENT_ITEM

3:1_SPACING

DAC_AP_OUT1
DAC_AP_OUT2
DAC_AP_OUT3

BUF_C_Y
BUF_CVBS_PB
BUF_Y_PR

VIDEO_EMI_CVBS_PB
VIDEO_EMI_C_Y
VIDEO_EMI_Y_PR

VIDEO_PT_DK_CON_CVBS_PB
VIDEO_PT_DK_CON_C_Y
VIDEO_PT_DK_CON_Y_PR

=50_OHM_SE

7

11

7

11

7

11

11

11

11

10 11 28

10 11 28

MAXIMUM NECK LENGTH

=50_OHM_SE

10 11 28

28 29

28 29

28 29

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

LVDS

NET_PHYSICAL_TYPE

LVDS_100D

NET_SPACING_TYPE1 NET_SPACING_TYPE2

LVDS

ELECTRICAL_CONSTRAINT_SET

I175

I174

I245
I244

I176
I178

I234
I235

AREA_TYPE

*

DISPLAYPORT

C

NET_PHYSICAL_TYPE

AREA_TYPE

MIPI_100D

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MIPI

ELECTRICAL_CONSTRAINT_SET

I91

I92
I93

I94

I95
I96

I271

I270
I97

I98

I311

I312
I315

I316

I341

B

I344

I343
I342

I345

I346

I347
I348

I353
I355

I354

I356

*

*

MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D

MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D

MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D

PHYSICAL_RULE_SET

PHYSICAL

MIPI

90_OHM_DIFF

AREA_TYPE

NET_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

*

SPACING

MIPI
MIPI
MIPI
MIPI
MIPI
MIPI
MIPI
MIPI
MIPI
MIPI

MIPI
MIPI
MIPI
MIPI
MIPI
MIPI
MIPI
MIPI

MIPI
MIPI
MIPI
MIPI
MIPI
MIPI
MIPI
MIPI

SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

4:1_SPACING

MIPID_AP_DATA_P<0>
MIPID_AP_DATA_N<0>
MIPID_AP_DATA_P<1>
MIPID_AP_DATA_N<1>
MIPID_AP_DATA_P<2>
MIPID_AP_DATA_N<2>
MIPID_AP_DATA_P<3>
MIPID_AP_DATA_N<3>
MIPID_AP_CLK_P
MIPID_AP_CLK_N

MIPI0C_AP_DATA_P<0>
MIPI0C_AP_DATA_N<0>
MIPI0C_AP_CLK_P
MIPI0C_AP_CLK_N
MIPI0C_CAM_DATA_P<0>
MIPI0C_CAM_DATA_N<0>
MIPI0C_CAM_CLK_P
MIPI0C_CAM_CLK_N

MIPI1C_AP_DATA_P<0>
MIPI1C_AP_DATA_N<0>
MIPI1C_AP_CLK_P
MIPI1C_AP_CLK_N
MIPI1C_CAM_DATA_P<0>
MIPI1C_CAM_DATA_N<0>
MIPI1C_CAM_CLK_P
MIPI1C_CAM_CLK_N

7

7

7

7

7

7

14

14

27

27

25 27

25 27

26

26

25 26

25 26

7

14

7

14

7

14

7

14

7

14

7

14

7

14

7

14

7

27

7

27

25 27

25 27

7

26

7

26

25 26

25 26

NET_PHYSICAL_TYPE

DP_100D

NET_SPACING_TYPE1 NET_SPACING_TYPE2

DP

ELECTRICAL_CONSTRAINT_SET

I247

I249

I248
I250

I251
I252

I273

I274
I275

I276

I277
I272

I327

I329
I328

I331
I330

I332

AREA_TYPE

*

=STANDARD

PHYSICAL_RULE_SET

90_OHM_DIFF

PHYSICAL

LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D

LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D

PHYSICAL_RULE_SET

90_OHM_DIFF

PHYSICAL

DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

NET_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

AREA_TYPE

**

NET_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

AREA_TYPE

**

SPACING

DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP

SPACING

SPACING_RULE_SET

LVDS
LVDS
LVDS
LVDS

LVDS
LVDS
LVDS
LVDS

SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

4:1_SPACING

LVDS_DATA_P<2..0>
LVDS_DATA_N<2..0>
LVDS_DATA_CONN_P<2..0>
LVDS_DATA_CONN_N<2..0>

LVDS_CLK_P
LVDS_CLK_N
LVDS_CLK_CONN_P
LVDS_CLK_CONN_N

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

5:1_SPACING

DP_AP_TX_P<0>
DP_AP_TX_N<0>
DP_AP_TX_P<1>
DP_AP_TX_N<1>
DP_AP_AUX_P
DP_AP_AUX_N
DP_EMI_TX_P<0>
DP_EMI_TX_N<0>
DP_EMI_TX_P<1>
DP_EMI_TX_N<1>
DP_EMI_AUX_P
DP_EMI_AUX_N
DP_PT_DK_CON_TX_P<0>
DP_PT_DK_CON_TX_N<0>
DP_PT_DK_CON_TX_P<1>
DP_PT_DK_CON_TX_N<1>
DP_PT_DK_CON_AUX_P
DP_PT_DK_CON_AUX_N

14 16

14 16

16

16

14 16

14 16

16

16

7

10 13

7

10 13

7

10 13

7

10 13

7

13

7

13

13 28

13 28

13 28

13 28

13 28

13 28

28 29

28 29

28 29

28 29

28 29

28 29

AUDIO/SPEAKER

NET_PHYSICAL_TYPE

AUDIO

SPEAKER

NET_SPACING_TYPE1 NET_SPACING_TYPE2

AUDIO

ELECTRICAL_CONSTRAINT_SET

I287

I288

I289
I290

I359
I291

I292

I293
I294

I357

I371

I372

AREA_TYPE

*
*

* *

SDIO

NET_PHYSICAL_TYPE

SDIO_50S

NET_SPACING_TYPE1 NET_SPACING_TYPE2

SDIO

SDIO_CLK

ELECTRICAL_CONSTRAINT_SET

I200

I280

I201

I202

AREA_TYPE

*

*

* *

SPI

NET_PHYSICAL_TYPE

SPI_50S

NET_SPACING_TYPE1 NET_SPACING_TYPE2

SPI

ELECTRICAL_CONSTRAINT_SET

I360

I363

I361
I362

I364

I365

I366
I367

AREA_TYPE

*

*

PHYSICAL_RULE_SET

PHYSICAL_RULE_SET

PHYSICAL_RULE_SET

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

1:1_DIFFPAIR

TABLE_PHYSICAL_ASSIGNMENT_ITEM

SPEAKER

AREA_TYPE

NET_TYPE

PHYSICAL

AUDIO AUDIO
AUDIO
AUDIO
AUDIO

AUDIO
AUDIO AUDIO

AUDIO AUDIO

50_OHM_SE

AREA_TYPE

NET_TYPE

PHYSICAL

SDIO_50S SDIO_CLK
SDIO_50S SDIO_CLK

SDIO_50S SDIO
SDIO_50S SDIO

45_OHM_SE

AREA_TYPE

NET_TYPE

PHYSICAL

SPI_50S
SPI_50S
SPI_50S
SPI_50S

SPI_50S
SPI_50S
SPI_50S
SPI_50S

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

*

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

*

SPACING_RULE_SET

SPACING

AUDIOAUDIO
AUDIOAUDIO

AUDIO
AUDIO
AUDIO
AUDIOAUDIO
AUDIO

AUDIOAUDIO

AUDIOAUDIO

SPACING_RULE_SET

SPACING

SPACING_RULE_SET

SPACING

SPI
SPI
SPI
SPI

SPI
SPI
SPI
SPI

3:1_SPACING

2:1_SPACING

4:1_SPACING

2:1_SPACING

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

LEFT_CH_OUT_P

LEFT_CH_OUT_REF

LEFT_CH_P
SSM2375_L_IN_P

SSM2375_L_IN_N
RIGHT_CH_OUT_P
RIGHT_CH_OUT_REF

RIGHT_CH_P
SSM2375_R_IN_P
SSM2375_R_IN_N

EXT_MIC_P
EXT_MIC_REF

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

SDIO_WL_CLK
SDIO_WL_CLK_R

SDIO_WL_CMD
SDIO_WL_DATA<3..0>

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SPI_GRAPE_MISO
SPI_GRAPE_MOSI
SPI_GRAPE_SCLK
SPI_GRAPE_CS_L

SPI_IPC_MISO
SPI_IPC_MOSI
SPI_IPC_SCLK
SPI_IPC_MRDY

D

19 20

19 20

20

20

20

19 20

19 20

20

20

20

19 23

19 23

C

5

30

5

30

5

30

B

5

17

5

17

5

17

5

17

5

31

5

31

5

31

5

31

A

8 7 5 4 2 1

36

SYNC_MASTER=MIKE

PAGE TITLE

CONSTRAINTS: ASSIGNMENTS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-8962

REVISION

BRANCH

PAGE

101 OF 106

SHEET

40 OF 42

SYNC_DATE=N/A

A.0.0

SIZE

A

D

MLB CONSTRAINTS

BOARD LAYERS

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,BOTTOM

BOARD AREAS

NO_TYPE,BGA,BGA06-06

BOARD UNITS
(MIL or MM)

MM

ALLEGRO
VERSION

15.2

345678

TABLE_BOARD_INFO

2 1

D

PHYSICAL CONSTRAINTS

=DEFAULT

0.210 MM

0.300 MM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LAYER

DEFAULT

STANDARD

SINGLE-ENDED PHYSICAL RULES
45 OHMS

LAYER

45_OHM_SE

45_OHM_SE

ISL2,ISL3,ISL8,ISL9

ISL4,ISL5,ISL6,ISL7

ALLOW ROUTE
ON LAYER?

* Y

*

ALLOW ROUTE
ON LAYER?

45_OHM_SE

C

50 OHMS

LAYER

ALLOW ROUTE
ON LAYER?

50_OHM_SEYTOP,BOTTOM

50_OHM_SE

* N

Y

Y

Y

N*

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=45_OHM_SE

=DEFAULT

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.055 MM 0.055 MM

0.060 MM

0.060 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.085 MM 0.085 MM

0.050 MM

=45_OHM_SE

=DEFAULT

0.060 MM

0.060 MM

0.050 MM

MAXIMUM NECK LENGTH

30 MM

12.7 MM

MAXIMUM NECK LENGTH

3.0 MM

3.0 MM

3.0 MM

MAXIMUM NECK LENGTH

3.0 MM

3.0 MM

DIFFPAIR PRIMARY GAP

0 MM 0 MM

=DEFAULT

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

50 OHMS - CLEAR ON LAYER 2 AND 5

50_OHM_SE_RF

50_OHM_SE

LAYER

TOP

ALLOW ROUTE
ON LAYER?

Y

Y

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.240 MM 0.240 MM

MAXIMUM NECK LENGTH

3.0 MM

0.060 MM0.060 MMISL4

3.0 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

50 OHMS - CLEAR ON TOP AND BOTTOM

50_OHM_SE

LAYER

ISL2,ISL9

ALLOW ROUTE
ON LAYER?

Y

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.090 MM 0.090 MM

MAXIMUM NECK LENGTH

3.0 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFERENTIAL PAIR PHYSICAL RULES
100 OHMS

LAYER

B

100_OHM_DIFFYTOP,BOTTOM

100_OHM_DIFF

ALLOW ROUTE
ON LAYER?

N

Y

MINIMUM LINE WIDTH

0.076 MM

0.057 MM

MINIMUM NECK WIDTH

0.076 MM

0.057 MM

MAXIMUM NECK LENGTH

=STANDARD

DIFFPAIR PRIMARY GAP

0.210 MM

0.300 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

SPACING CONSTRAINTS

DEFAULT/BGA SPACING RULES

SPACING_RULE_SET

BGA_SPA

LAYER

LINE-TO-LINE SPACING

* ?

* ?

*

0.08 MMDEFAULT

=DEFAULTSTANDARD

=DEFAULT

REGULAR SPACING RULES

SPACING_RULE_SET

LAYER

1:1_SPACING

0P08_SPACING

1.5:1_SPACING

2:1_SPACING

2.5:1_SPACING

3:1_SPACING

4:1_SPACING

5:1_SPACING

0P5MM_SPACING

*NOTE: ASSUMING 0.060MM DIELECTRIC THICKNESS

LINE-TO-LINE SPACING

*

* ?

0.060 MM

0.080 MM

0.090 MM

*

*

*

0.120 MM

0.150 MM

0.180 MM

0.240 MM

*

*

*

0.300 MM

0.5 MM

0.64 MM0P64MM_SPACING

POWER/GND SPACING RULES

*

*

*

LINE-TO-LINE SPACING

0.1 MM

0.1 MM

0.5 MM

0.2 MM

SPACING_RULE_SET

PWR_P1SPACING

GND_P1SPACING

SWITCHNODE

SWITCHNODE

LAYER

TOP,BOTTOM

WEIGHT

WEIGHT

WEIGHT

900

950
1000
1000

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

*

*

AREA_TYPE

*

PWR

GND

SWITCHNODE SWITCHNODE

ANLG

* *

* *

SPACING_RULE_SET

BGA

BGACLK

**

**

NOTES:

0.075 MM ~ 3 MIL

0.089 MM ~ 3.5 MIL

0.102 MM ~ 4 MIL

0.114 MM ~ 4.5 MIL

0.125 MM ~ 5 MIL

0.140 MM ~ 5.5 MIL

0.15 MM ~ 6 MIL

0.18 MM ~ 7 MIL

0.2 MM ~ 8 MIL

0.25 MM ~ 10 MIL

0.3 MM ~ 12 MIL

0.33 MM ~ 13 MIL

0.4 MM ~ 16 MIL

1.0 MM = 39.37 MIL

BGA_SPA

BGA_SPA

PWR_P1SPACING

GND_P1SPACING

3:1_SPACING

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

D

C

B

90 OHMS

90_OHM_DIFF

90_OHM_DIFF

90_OHM_DIFF

LAYER

TOP,BOTTOM

ISL2,ISL3,ISL8,ISL9

ISL4,ISL5,ISL6,ISL7

ALLOW ROUTE
ON LAYER?

Y

Y

Y

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.095 MM

0.054 MM 0.054 MM

0.060 MM 0.060 MM

0.095 MM

MAXIMUM NECK LENGTH

=STANDARD

=STANDARD

DIFFPAIR PRIMARY GAP

0.200 MM 0.200 MM

0.200 MM

0.200 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

AUDIO PHYSICAL RULES

LAYER

1:1_DIFFPAIR

ALLOW ROUTE
ON LAYER?

*

SPEAKER

BGA AREA PHYSICAL RULES

BGA

LAYER

*

PHYSICAL_RULE_SET

BGA_PHY

ALLOW ROUTE
ON LAYER?

NET_PHYSICAL_TYPE

A

*

AREA_TYPE

BGA_PHY

Y

Y*

Y

MINIMUM LINE WIDTH

=STANDARD =STANDARD

MINIMUM NECK WIDTH

=STANDARD

0.3 MM 0.19MM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

0.060 MM

MINIMUM NECK WIDTH

0.060 MM

MAXIMUM NECK LENGTH

10 MM

MAXIMUM NECK LENGTH

=STANDARD

DIFFPAIR PRIMARY GAP

0.08 MM

0.08 MM

DIFFPAIR PRIMARY GAP

0.076 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

8 7 5 4 2 1

0.100 MM

0.100 MM

0.08 MM

0.08 MM

0.075 MM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SIZE

A

D

SYNC_MASTER=MIKE

PAGE TITLE

CONSTRAINTS: MLB RULES

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-8962

REVISION

A.0.0

BRANCH

PAGE

102 OF 106

SHEET

41 OF 42

36