AR-7030 Computer remote control protocol.
Information for firmware releases 1.1A, 1.2A, 1.4A and 1.4B
1) Remote control overview.
The AR-7303 receiver allows remote control of all of its functions by means of a direct memory access
system.
A controlling computer can read and modify the internal memory maps of the receiver to set required parameters and then call for the receiver’s control program to process the new settings.
Commands to the receiver are byte structured in binary format, so it is not possible to control from a terminal.
All multi-byte numbers within the receiver are binary, stored msb first.
2) Receiver frequency configuration.
Receive frequency is set by two oscillators - local and carrier. In AM and FM modes the carrier oscillator is
not used, and the final IF frequency is 455kHz. In Sync mode the carrier oscillator is offset by +20.29kHz
before mixing with the IF.
The IF frequencies have a fixed inter-conversion frequency of 44.545MHz and, because of the high-side local
oscillator, both IF’s are inverted.
The receiver controller processes the following variables to establish the tuned frequency :-
[
local offset
[
carrier offset
[
filter offset
[PBS] User set filter shift.
[BFO] User set offset between carrier position and frequency display.
[TUNE] Receiver tuned frequency as shown on display.
] Frequency shift applied to local oscillator.
] 455.00kHz for LSB, USB, Data and CW modes / 434.71kHz for Sync mode.
] IF Filter frequency at the (vestigial) carrier position as an offset from 455kHz.
The relationship between these variables and the tuning is as follows :-
[
carrier offset
45.000MHz + [
[TUNE] + [
3) Serial data protocol.
All data transfers are at 1200 baud, No parity, 8 bits, 1 stop bit (1200 N 8 1). There is no hardware or software flow control other than that inherent in the command structure. The receiver can accept data at any time
at full rate provided the IR remote controller is not used or is disabled. A maximum of one byte can be
transmitted for each byte received, so data flow into a controlling computer is appropriately limited.
Each byte sent to the receiver is a complete command - it is best thought of as two hexadecimal digits - the
first digit is the
receiver operates with 8-bit bytes, intermediate 4-bit values are stored in
nation and processing. For example to write into the receiver’s memory, the following steps would be followed
:-
a) Send address high order 4-bits into
b) Send address low order 4-bits and set
c) Send first data byte high order 4-bits into
d) Send first data byte low order 4-bits and execute
e) Send second data byte high order 4-bits into
f) Send second data byte low order 4-bits and execute
g) Repeat (e) and (f) for each subsequent byte to be written.
4) Memory organisation.
Different memory areas in the receiver are referenced by selecting
The memory is broadly divided into 3 sections :-
] + [
filter offset
filter offset
local offset
operation code
] + [PBS] + [BFO] ——> Carrier oscillator
] + [PBS] ——> [
] ——> Local oscillator
, the second digit is 4-bits of
local offset
data
relating to the operation. Because the
]
registers
H-register
Address register
H-register
Write Data Operation
H-register
Write Data Operation
Pages
- up to 16 pages are supported.
in the receiver for recombi-
a) Working memory - where all current operating variables are stored and registers and stack are
located. This memory is volatile and data is lost when power to the receiver is removed.
b) Battery sustained memory - where duplicate parameters are stored for retention when power is
removed. This memory area is also used for storage of filter parameters, setup memories and
squelch and BFO settings for the frequency memories and contains the real time clock registers.
c) EEPROM - where frequency, mode, filter and PBS information for the frequency memories is
stored. Additionally S-meter and IF calibration values are stored here. This memory can be
read or written to download and upload the receiver’s frequency memories, but repetitive
writing should be avoided because the memory devices will only support a finite number of
write cycles.
5) Variations between A and B types and firmware revisions.
Type A firmware supports only basic receiver functions, type B extends operations and includes support for
the Notch / Noise Blanker option. The whole of the type A memory map is retained in type B, but more
memory and operations are added for the extended functions of type B.
In the following information, circled note numbers are included to indicate where items are specific to one
type or
revision of the firmware:-
Applicable to type B firmware only.
Applicable to revision 1.4 only, types A and B
Function is changed or added to in type B
6) Operation codes.
The high order 4-bits of each byte sent to the receiver is the
(shown here as x) :-
Code Ident Operation
0
x
3
x
5
x
4
x
1
x
6
x
9
x
2
x
A
x
7
x
8
x
Note that the
(if non-zero) after the low order 8-bits. The
data operation and by x after a read data operation.
When writing to any of the EEPROM memory pages a time of 10ms per byte has to be allowed. For this
reason it is recommended that instructions SRH and WRD are always used together (even if the SRH is not
needed) since this will ensure that the EEPROM has sufficient time to complete its write cycle.
Additionally to allow time for local receiver memory updates and SNC detector sampling in addition to the
EEPROM write cycle, it is recommended to lock the receiver to level 2 or 3, or add a NOP instruction after
each write. This is not required for firmware revision 1.4 but locking is still recommended.
The mask operation helps with locations in memory that are shared by two parameters and aids setting and
clearing bits. The mask operates only in Page 0. If bits in the mask are set, then a following write operation
will leave the corresponding bits unchanged. The mask register is cleared after a write so that subsequent
writes are processed normally. Because it defaults to zero at reset, the mask is inoperative unless specifically
set.
The operate button instruction uses the same button codes as are returned from routine 15 (see section 8),
with an additional code of zero which operates the
0 will switch the receiver on (from standby state).
NOP No Operation
SRH Set H-register
PGE Set page
ADR Set address 0
ADH Set address high
WRD Write data
MSK Set mask
EXE Execute routine
BUT Operate button
RDD Read data [Page, Address] —> Serial output
LOC Set lock level
H-register
is zeroed after use, and that the high order 4-bits of the
x
x
x
Address register
power
operation code
x
—>
H-register
x
—>
Page register
Hx
—>
Address register
0 —>
H-register
x
—>
Address register
Hx
—> [Page, Address]
Address register
0 —>
H-register,
Hx
—>
Mask register
0 —>
H-register
Address register
, the low order 4-bits is
(4-bits)
(4-bits)
(12-bits)
(high 4-bits)
+ 1 —>
+ x —>
Address register
0 —>
Mask register
Address register
Address register
is automatically incremented by one after a write
button, but will not switch the receiver off. Also code
data
must be set
7) Memory pages.
Page 0 Working memory (RAM) 256 bytes.
Page 1 Battery sustained memory (RAM) 256 bytes.
Page 2 Non-volatile memory (EEPROM) 512 bytes.
Page 3 Non-volatile memory (EEPROM) 4096 bytes.
Page 4
Pages 5 - 14 Not assigned.
Page 15 Receiver Ident (ROM) 8 bytes.
8) Lock levels.
Level 0 Normal operation.
Level 1 IR remote control disabled.
Non-volatile memory (EEPROM) 4096 bytes.
The ident is divided into model number (5 bytes), software revision (2 bytes) and
type letter (1 byte).
eg 7030_14A —> Model AR-7030, revision 1.4, type letter A.
Front panel buttons ignored.
Front panel spin-wheels logged but not actioned.
Display update (frequency & S-meter) continues.
Level 2 As level 1, but display update suspended. In revisions before 1.4
squelch operation is inhibited, which results in no audio output
after a mode change. In revision 1.4 squelch operation continues
and mode changing is as expected.
Level 3 Remote operation exclusively.
Lock level 1 is recommended during any multi-byte reads or writes of the receiver’s memory to prevent data
contention between internal and remote memory access. See also EEPROM notes in section (6)
8) Routines.
Routine 0 Reset Setup receiver as at switch-on.
Routine 1 Set frequency Program local oscillator from
oscillator range.
Routine 2 Set mode Setup from
Routine 3 Set passband Setup all IF parameters from
Routine 4 Set all Set all receiver parameters from current memory values
Routine 5 Set audio Setup audio controller from memory register values.
Routine 6
Routine 7 Not assigned
Routine 8 Not assigned
Routine 9 Direct Rx control Program control register from
Routine 10 Direct DDS control Program local oscillator and carrier oscillator DDS systems
Routine 11 Display menus Display menus from
Routine 12 Display frequency Display frequency from
Routine 13 Display buffer Display ASCII data in
Routine 14 Read signal strength Transmits byte representing received signal strength (read
Routine 15 Read buttons Transmits byte indicating state of front panel buttons. Output is 8-
Note that the work buffer
are invoked. Lock levels of 1 or more should be used when reading any front panel controls to prevent erratic
results.
Set RF-IF Setup RF Gain, IF Gain and AGC speed. Also sets Notch Filter and Noise
Button codes :-
wbuff
area in memory is used continuously by the receiver unless lock levels 2 or 3
mode
byte in memory and display mode, select preferred filter
and PBS, BFO values etc.
Blanker if these options are fitted.
from
wbuff
area. The 32-bits at
frequency, value is 385674.4682 / kHz. The 32 bits at
wbuff+4
753270.4456 / MHz.
control the local osc frequency, value is
menu1
starting at 128 for the top line and 192 for the bottom line.
An address value of 1 clears the display. Data string (max
length 24 characters) ends with a zero byte.
from AGC voltage). Output is 8-bit binary in range 0 to 255.
bit binary with an offset of +48 (ie ASCII numbers). Buttons
held continuously will only be registered once.
0 = None pressed 5 = RF-IF button
1 = Mode up button 6 = Memory button
2 = Mode down button 7 = * button
3 = Fast button 8 = Menu button
4 = Filter button 9 = Power button
frequ
area and setup RF filters and
filter, pbsval
rxcon
and
menu2
frequ
wbuff
area. First byte is display address,
area.
wbuff
area.
and
bfoval
control the carrier
bytes.
bytes.
10) Battery sustained RAM (Memory page 1)
Address Ident Length Description
0 00 13 bytes Real time clock / timer registers :-
0 00 rt_con 1 byte Clock control register
2 02 rt_sec 1 byte Clock seconds (2 BCD digits)
3 03 rt_min 1 byte Clock minutes (2 BCD digits)
4 04 rt_hrs 1 byte Clock hours (2 BCD digits - 24 hr format)
5 05 rt_dat 1 byte Clock year (2 bits) and date (2 BCD digits)
6 06 rt_mth 1 byte Clock month (2 BCD digits - low 5 bits only)
8 08 tm_con 1 byte Timer control register
10 0A tm_sec 1 byte Timer seconds (2 BCD digits)
11 0B tm_min 1 byte Timer minutes (2 BCD digits)
12 0C tm_hrs 1 byte Timer hours (2 BCD digits - 24 hr format)
13 0D 15 bytes Power-down save area :-
13 0D ph_cal 1 byte Sync detector phase cal value
14 0E pd_slp 1 byte Timer run / sleep time in minutes
15 0F pd_dly 1 byte Scan delay value x 0.125 seconds
16 10 pd_sst 1 byte Scan start channel
17 11 pd_ssp 1 byte Scan stop channel
18 12 pd_stp 2 bytes Channel step size
20 14 pd_sql 1 byte Squelch
21 15 pd_ifg 1 byte IF gain
22 16 pd_flg 1 byte Flags (from
23 17 pd_frq 3 bytes Frequency
26 1A pd_mod 1 byte Mode (bits 0-3) and NB threshold (bits 4-7)
27 1B pd_vol
28 1C 26 bytes Receiver setup save area :28 1C md_flt 1 byte AM mode : Filter (bits 0-3) and AGC speed (bits 4-7)
29 1D md_pbs 1 byte AM mode : PBS value
30 1E md_bfo 1 byte AM mode : BFO value
31 1F 3 bytes Ditto for Sync mode
34 22 3 bytes Ditto for NFM mode - except Squelch instead of BFO
37 25 3 bytes Ditto for Data mode
40 28 3 bytes Ditto for CW mode
43 2B 3 bytes Ditto for LSB mode
46 2E 3 bytes Ditto for USB mode
49 31 st_aud
50 32 1 byte Audio treble setting (bits 0-3) and RF Gain (bits 4-7)
51 33 1 byte Aux output level - left channel
52 34 1 byte Aux output level - right channel
53 35 st_flg 1 byte Flags (from
1 byte Volume (bits 0-5) and rx memory hundreds (bits 6&7)
1 byte Audio bass setting (bits 0-4)
bit 5 Notch auto track enable
bit 6 Ident search enable
bit 7 Ident preview enable
pdflgs
stflgs
)
)
54 36 26 bytes Setup memory A (configured as above)
80 50 26 bytes Setup memory B (configured as above)
106 6A 26 bytes Setup memory C (configured as above)
132 84 24 bytes Filter data area :132 84 fl_sel 1 byte Filter 1 : selection bits and IF bandwidth
133 85 fl_bw 1 byte Filter 1 : bandwidth (2 BCD digits, x.x kHz)
134 86 fl_uso 1 byte Filter 1 : USB offset value x 33.19Hz
135 87 fl_lso 1 byte Filter 1 : LSB offset value x 33.19Hz
136 88 4 bytes Ditto for filter 2
140 8C 4 bytes Ditto for filter 3
144 90 4 bytes Ditto for filter 4
148 94 4 bytes Ditto for filter 5
152 98 4 bytes Ditto for filter 6
156 9C mem_sq 100 bytes Squelch / BFO values for frequency memories 0 to 99
11) EEPROM (Memory page 2)
Address Ident Length Description
0 000 4 bytes Frequency memory data :-
0 000 mem_fr 3 bytes Memory 00 : 24-bit frequency
3 003 mem_md 1 byte bits 0 - 3 mode
4 004 396 bytes Ditto for memories 01 to 99
400 190 mem_pb 100 bytes PBS values for frequency memories 0 to 99
500 1F4 sm_cal 8 bytes S-meter calibration values :500 1F4 1 byte RSS offset for S1 level
501 1F5 1 byte RSS steps up to S3 level
502 1F6 1 byte RSS steps up to S5 level
503 1F7 1 byte RSS steps up to S7 level
504 1F8 1 byte RSS steps up to S9 level
505 1F9 1 byte RSS steps up to S9+10 level
506 1FA 1 byte RSS steps up to S9+30 level
507 1FB 1 byte RSS steps up to S9+50 level
508 1FC if_cal 2 bytes RSS offsets for -20dB and -8dB filter alignment
(BFO for Data and CW modes, Squelch for others)
bits 4 - 6 filter
bit 7 scan lockout
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