Datasheet UG-284 Datasheet (ANALOG DEVICES)

Evaluation Board User Guide

One Technology Way • P. O . Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel : [phone] • Fax : [phone] • www.analog.com

UG-284

ADAU1373 Evaluation Board User Guide

PACKAGE CONTENTS

ADAU1373 evaluation board

5 V ac-to-dc power adapter
Evaluation board user guide

DOCUMENTS NEEDED

ADAU1373 data sheet
AN-1006 Application Note, Using the EVAL-ADUSB2EBZ

GENERAL DESCRIPTION

The ADAU1373 is a low power audio codec that supports stereo
record and playback. It provides eight single-ended or four
differential analog inputs with PGA for adjusting the gain. The
support for two stereo digital microphone inputs is provided so
that, in total, four digital microphones can be connected. In
addition, three serial digital audio in/out ports are provided
with ASRCs to support various sampling rates at the
input/output ports, allowing flexible system design.

The analog output side consists of line outputs, a headphone
output, a speaker output, and a receiver output. The two stereo
single-ended line level outputs are included, which can be

configured as two differential outputs. The headphone output is
stereo true-ground-centered with efficient Class-G architecture.
The efficient stereo filterless Class-D switching amplifier pro­vides around 1 W stereo power for speakers. The differential
receiver amplifier can be used to connect the separate receiver
speaker.

The ADAU1373 evaluation board includes the complete
application circuit for the ADAU1373. The board is featured
with USBi connection to the SigmaStudio™ graphical develop­ment tool running on a host PC, which is used to program the

ADAU1373.

Included in this user guide is a detailed description for the

ADAU1373 evaluation board. It is recommended that the
ADAU1373 data sheet be read along with this user guide. Full

details about the part are available in the ADAU1373 data sheet,
which provides more detailed information about the specifica­tions, internal block diagrams, and application guidance for the
codec IC.

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.

Rev. 0 | Page 1 of 24

UG-284 Evaluation Board User Guide

TABLE OF CONTENTS

Package Contents .............................................................................. 1

Documents Needed .......................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Setting Up the Board—Quick Start ................................................ 3

SigmaStudio Software Installation ............................................. 3

Hardware Setup, USBi .................................................................. 3

Powering the Board ...................................................................... 3

Setting Up the Registers in SigmaStudio ................................... 3

REVISION HISTORY

6/11—Revision 0: Initial Version

Evaluation Board Hardware .............................................................5

Power Supplies ...............................................................................5

Digital Audio Interface and Digital Microphone Interface .....7

Analog Input and Output .............................................................9

Clock and Control Port ............................................................. 10

Evaluation Board Schematics and Artwork ................................ 11

Ordering Information .................................................................... 20

Bill of Materials ........................................................................... 20

Related Links ................................................................................... 21

Rev. 0 | Page 2 of 24

Evaluation Board User Guide UG-284

SETTING UP THE BOARD—QUICK START

SigmaStudio SOFTWARE INSTALLATION

To install the SigmaStudio software, follow these steps:

1. Open the provided .zip file and extract the files to your PC.

Alternatively, insert the SigmaStudio CD into the PC
optical drive and locate the SigmaStudio folder on the CD.

2. If Microsoft .NET Framework Version 3.5 is not already

installed on the PC, install it by double-clicking
dotnetfx.exe.

3. Install SigmaStudio by double-clicking setup.exe and

following the prompts. A computer restart is not required.

HARDWARE SETUP, USBi

To set up the USBi hardware, follow these steps:

1. Plug the USBi ribbon cable into Header J23.

2. Connect the USB cable to your computer and to the USBi.

3. When prompted for drivers, follow these steps:
a) Select Install from a list or a specific location.
b) Select Search for the best driver in these locations.
c) Select the box for Include this location in the search.

The USBi driver is located in C:\Program Files\Analog
Devices Inc\Sigma Studio\USB drivers.

d) Click Next.
e) If prompted to choose a driver, select CyUSB.sys.
f) If the PC is running Windows® XP and you receive the

message that the software has not passed Windows
logo testing, click Continue Anyway.

POWERING THE BOARD

1. Plug the external dc power adapter into J34 to input 5 V dc

power to the board.

2. Short Jumpers J40, J33, J31, and J32 to select the on-board

LDO-generated voltages that are connected to SPKVDD,
HPVDD, AVDD, and DVDD, respectively.

3. Set Jumpers J43, J36, J39, J37, and J38 to select the required

voltage (1.8 V, 2.4 V, or 3.3 V) connected to each IOVDDx
(x = 1 to 5).

SETTING UP THE REGISTERS IN SigmaStudio

The codec is configured with SigmaStudio software. To set up
the registers in SigmaStudio, follow these steps:

1. Create a new project. Select New Project under the File

menu. The Hardware Configuration tab opens.

2. Click and drag an ADAU1373 cell and a USBi cell into the

blank work area.

3. Connect the USBi cell to the ADAU1373 cell by clicking

and dragging from the top blue output pin of the USBi cell
to the green input pin of the ADAU1373 cell. The window
should now resemble Figure 1.

4. In the IC 1 - ADAU1373_REVB_V1.13 tab, configure the

ADAU1373 registers by clicking the intuitive graphic user
interface (GUI) elements in the Input A to Input D,
Analog Input Signal Routing, and Mic Bias Control
sections to set up the proper datapath (see Figure 2).

The SigmaStudio software includes help information. Press the
F1 key to open the help window.

Figure 1. Hardware Configuration Tab—USBi Connection

Rev. 0 | Page 3 of 24

09899-001

UG-284 Evaluation Board User Guide

09899-002

Figure 2. Hardware Configuration Tab—Register Setup

Rev. 0 | Page 4 of 24

Evaluation Board User Guide UG-284

EVALUATION BOARD HARDWARE

POWER SUPPLIES

IOVDD5

FOR

2

I

C/SPI

IOVDD2

FOR

DAI B

IOVDD1

FOR

DAI A

IOVDD4

FOR

DMIC

IOVDD3

FOR

DAI C

SPKVDD

DVDD

5V DC INPUT

Figure 3. Power Supply

The evaluation board requires an external 5 V dc power adapter
plugged into J34. This 5 V dc input drives the on-board LDOs
to generate 1.5 V, 1.8 V, 2.4 V, 3.3 V, or 3.6 V, which feeds into
the ADAU1373 and other on-board circuits. The power
supplies the ADAU1373 requires are listed in Tab le 1.

Table 1. ADAU1373 Power Supplies

Power Supply LDO Voltage
AVDD 1.8 V
HPVDD 1.8 V
SPKVDD 3.6 V
DVDD 1.5 V
IOVDD1 to IOVDD5 1.8 V, 2.4 V, or 3.3 V

If voltages other than the default LDO output are needed, external
power supplies can be used for this purpose. Each power supply
for the ADAU1373 has a set of jumpers to select the LDO
output or external power supply.

J31 is for AVDD power supply selection. The selection options
are shown in Ta ble 2 .

Table 2. J31

Jumper
Position

Func tion

On On-board LDO-generated 1.8 V connected to AVDD
Off

External power supply connected to Test Pin AVDD
and Test Pin GND

J33 is for HPVDD power supply selection. The selection table is
shown in Table 3.

Rev. 0 | Page 5 of 24

HPVDD AVDD

09899-003

Table 3. J33

Jumper
Position

On

Off

Function

On-board LDO-generated 1.8 V connected to
HPVDD

External power supply connected to Test Pin HPVDD
and Test Pin GND

J32 is for DVDD power supply selection. The selection options
are shown in Ta ble 4 .

Table 4. J32

Jumper
Position

Function

On On-board LDO-generated 1.5 V connected to DVDD
Off

External power supply connected to Test Pin DVDD
and Test Pin GND

J40 is for SPKVDD power supply selection. The selection
options are shown in Tab l e 5.

Table 5. J40

Jumper
Position

On

Off

Function

On-board LDO-generated 3.6 V connected to
SPKVDD

External power supply connected to SPKVDD: J41
for SPKVDD and J42 for GND

J43 is for IOVDD1 power supply selection, which powers
Digital Audio Interface A. The selection options are shown in
Tabl e 6.

UG-284 Evaluation Board User Guide

Table 6. J43

Jumper
Position

1-2

3-4

5-6

Off

1

Jumper Position x-y means Pin x and Pin y are connected together via a

1

Func tion

On-board LDO-generated 1.8 V connected to
IOVDD1

On-board LDO-generated 3.3 V connected to
IOVDD1

On-board LDO-generated 2.4 V connected to
IOVDD1

External power supply connected to
Test Pin IOVDD1 and Test Pin GND

jumper capacitor.

J36 is for IOVDD2 power supply selection, which powers digital
Audio Interface B. The selection options are shown in Ta ble 7 .

Table 7. J36

Jumper
Position

1-2

3-4

5-6

Off

1

Jumper Position x-y means Pin x and Pin y are connected together via a

1

Function

On-board LDO-generated 1.8 V connected to
IOVDD2

On-board LDO-generated 3.3 V connected to
IOVDD2

On-board LDO-generated 2.4 V connected to
IOVDD2

External power supply connected to
Test Pin IOVDD2 and Test Pin GND

jumper capacitor.

J39 is for IOVDD3 power supply selection, which powers digital
Audio Interface C. The selection options are shown in Tab le 8.

Table 8. J39

Jumper
Position

1-2

3-4

5-6

Off

1

Jumper Position x-y means Pin x and Pin y are connected together via a

1

Function

On-board LDO-generated 1.8 V connected to
IOVDD3

On-board LDO-generated 3.3 V connected to
IOVDD3

On-board LDO-generated 2.4 V connected to
IOVDD3

External power supply connected to
Test Pin IOVDD3 and Test Pin GND

jumper capacitor.

J37 is for IOVDD4 power supply selection, which powers the
digital microphone interface. The selection options are shown
in Tabl e 9 .

Table 9. J37

Jumper
Position

1-2

3-4

5-6

Off

1

Jumper Position x-y means Pin x and Pin y are connected together via a

1

Function

On-board LDO-generated 1.8 V connected to
IOVDD4

On-board LDO-generated 3.3 V connected to
IOVDD4

On-board LDO-generated 2.4 V connected to
IOVDD4

External power supply connected to
Test Pin IOVDD4 and Test Pin GND

jumper capacitor.

J38 is for IOVDD5 power supply selection, which powers the

2

I

C/SPI port. The selection options are shown in Tab le 1 0.

Table 10. J38

Jumper
Position

1-2

3-4

5-6

Off

1

Jumper Position x-y means Pin x and Pin y are connected together via a

1

Func tion

On-board LDO-generated 1.8 V connected to
IOVDD5

On-board LDO-generated 3.3 V connected to
IOVDD5

On-board LDO-generated 2.4 V connected to
IOVDD5

External power supply connected to
Test Pin IOVDD5 and Test Pin GND

jumper capacitor.

Rev. 0 | Page 6 of 24

Evaluation Board User Guide UG-284

DIGITAL AUDIO INTERFACE AND DIGITAL MICROPHONE INTERFACE

DIGITAL AUDIO
INTERFACE A

DIGITAL MIC

INTERFACE 1

DIGITAL MIC

INTERFACE 2

Figure 4. Digital Audio Interface and Digital Microphone Interface

The evaluation board provides three digital audio interfaces
(J28 to J30) and two digital microphone interfaces (J44/J45
and J46/J47).

The pin definitions for J28, J29, and J30 are shown in Figure 5,
Figure 6, and Figure 7, respectively.

12

GND

1

GND

3

GND

5

GND

7

GND

9

GND

11

Figure 5. Pin Definitions for J28

12

GND

1

GND

3

GND

5

GND

7

GND

9

GND

11

Figure 6. Pin Definitions for J29

2

4

6

8

10

12

2

4

6

8

10

12

MCLK1

GPIO1

A_BCLK

A_LRC

A_DACDAT

A_ADCDAT

MCLK2

GPIO2

B_BCLK

B_LRC

B_DACDAT

B_ADCDAT

09899-016

09899-017

DIGITAL AUDIO
INTERFACE B

DIGITAL AUDIO
INTERFACE C

09899-004

12

1

GND

3

GND

5

GND

7

GND

9

GND

11

GND

NC = NO CONNECT. DO NOT
CONNECT TO THIS PIN.

2

NC

4

GPIO3

6

C_BCLK

8

C_LRC

10

C_DACDAT

12

C_ADCDAT

09899-018

Figure 7. Pin Definitions for J30

The pin definitions for J44 are listed in Tabl e 11.

Table 11. J44

Pin No. Signal

1 IOVDD4
2 DMIC_DATA1
3 LR_SEL (high)
4 NC
5 DMIC_CLK
6 GND

Rev. 0 | Page 7 of 24

UG-284 Evaluation Board User Guide

The pin definitions for J45 are listed in Tabl e 12.

The pin definitions for J47 are listed in Tabl e 14.

Table 12. J45

Pin No. Signal

1 IOVDD4
2 DMIC_DATA1
3 LR_SEL (low)
4 NC
5 DMIC_CLK
6 GND

The pin definitions for J46 are listed in Tabl e 13.

Table 13. J46

Pin No. Signal

1 IOVDD4
2 DMIC_DATA1
3 LR_SEL (high)
4 NC
5 DMIC_CLK
6 GND

Table 14. J47

Pin No. Signal

1 IOVDD4
2 DMIC_DATA1
3 LR_SEL (low)
4 NC
5 DMIC_CLK
6 GND

Rev. 0 | Page 8 of 24

Evaluation Board User Guide UG-284

A

A

A

G

A

ANALOG INPUT AND OUTPUT

NALOG

INPUT 4

NALO

INPUT 3

NALOG

INPUT 2

NALOG

INPUT 1

EARPIECE
OUTPUT

ANALOG
OUTPUT 1

ANALOG
OUTPUT 2

HEADPHONE
OUTPUT

SPEAKER
OUTPUT

Figure 8. Analog Input and Output Interface

On the board, there are four analog inputs (J4, J5, J8, and J9).
Near each input, there is a three-way jumper that selects which
bias voltage is routed to this input pair. These jumpers are J2, J3,
J6, and J7. The configurations are shown in Figure 9, and the
definitions of these jumper configurations are listed in Tab le 15 ,
Tabl e 16, Tab le 17 , and Table 18, respectively.

MICB2

MICB1

POSITION A POSITION B

Figure 9. Configuration for Jumpers J2, J3, J6, and J7

MICB2

MICB1

09899-019

Table 15. J2

Position Function

A Microphone Bias 1 connected to Analog Input 1
B Microphone Bias 2 connected to Analog Input 1

Table 16. J3

Position Function

A Microphone Bias 1 connected to Analog Input 2
B Microphone Bias 2 connected to Analog Input 2

09899-005

Table 17. J6

Position Function

A Microphone Bias 1 connected to Analog Input 3
B Microphone Bias 2 connected to Analog Input 3

Table 18. J7

Position Function

A Microphone Bias 1 connected to Analog Input 4
B Microphone Bias 2 connected to Analog Input 4

On the board, there are two analog outputs (J10 and J11),
one earpiece output for mono differential signals (J18), one
headphone output (J12), and two pairs of speaker outputs
(J13/J14 and J15/J16).

Rev. 0 | Page 9 of 24

UG-284 Evaluation Board User Guide

S

S

A

A

A

CLOCK AND CONTROL PORT

2

C

I2C ADDRESS
SELECTION

I2C/SPI
SELECTION

MCLK2

ELECTION

JUMPER

MCLK1

ELECTION

JUMPER

EXTERNAL

CLOCK

IMPUT

RESET

EXTERNAL I

ADAPTER

CONNECTOR

Figure 10. Clock and Control Port

There are two master clock input pins for the ADAU1373:
MCLK1 and MCLK2. For each master clock, there are three
clock sources that can be selected by Jumper 21 and Jumper 22.

OSC SMA1

PSI

POSITION A

1

2

OSC SMA1

POSITIO N B

PSI

Figure 11. Configuration for Jumpers 21 and 22

1

2

OSC SMA1

POSITIO N C

PSI

1

2

09899-023

J21 is for MCLK1 selection. The position definitions are shown
Figure 11 and Tab le 1 9.

Table 19. J21

Jumper
Position Function

A Use an on-board 12.288 MHz oscillator as MCLK1.
B Use an external SMA clock input as MCLK1.
C

Use an audio precision PSIA MCLK input connected
to J28 as MCLK1.

09899-006

J22 is for MCLK2 selection. The position definitions are shown
in Figure 11 and Ta ble 20 .

Table 20. J22

Jumper
Position Function

A Use an on-board 12.288 MHz oscillator as MCLK2.
B Use an external SMA clock input as MCLK2.
C

Use an audio precision PSIA MCLK input connected
to J29 as MCLK2.

J23 is for the external I2C/SPI controller (USBi board) connec­tion. J24 selects the control port mode of the ADAU1373. The
position definitions of this jumper are shown in Ta ble 2 1 .

Table 21. J24

Jumper Position Function

On I2C mode
Off SPI mode

J25 selects the I2C device address of the ADAU1373. The
position definitions of this jumper are shown in Ta ble 2 2 .

Table 22. J25

Jumper Position Function

On I2C devices address = 0x1C.
Off I2C devices address = 0x1A.

Rev. 0 | Page 10 of 24

Evaluation Board User Guide UG-284

EVALUATION BOARD SCHEMATICS AND ARTWORK

C14

0.1uf

C14

C11

0.1uf

C11

C1

0.1ufC10.1uf

IOVDD1

AVDD

CF2
CF1

CPVDD

CPVSS

GND

C3

2.2ufC32.2uf

C2

GND

0.1ufC20.1uf

C4

2.2uFC42.2uF

CF1

DVDD

CF2
CF1
CPVDD
CPVSS

C6

0.1ufC60.1uf

IOVDD2

HPVDD

C7

CF2

MODE

MODE

IOVDD5

A2

B3

IOVDD5

DVDD

B1

CF2

J7

CF1

J9
H9
H7
H8
H3

H2
G2
G1

E9
A9

GND

C5

2.2ufC52.2uf

0.1ufC70.1uf

CSB

SCL

SDA

CSB

SCL

SDA

C3

B2

C5

SCL

SDA

CSB

MODE

CPVDD

CPVSS

HPVDD

SPKVDD4
SPKVDD3
SPKVDD2
SPKVDD1

AVDD2
AVDD1

DVDD

GND

DMIC1

DMIC2

DMICCLK

GPIO4

GPIO4

DMIC2

DMIC1

IOVDD4

DMICCLK

C4

A4

B4

C6

A3

GPIO4

DMIC1

IOVDD4

DMICCLK

0.1uf

IOVDD3

CPVSS

IOVDD1

C1

DMIC2

IOVDD1

GND

C10

2.2uf

C10

2.2uf

C9

0.1ufC90.1uf

GND

C8

2.2uFC82.2uF

GND

MCLK1

A_LRC

GPIO1

A_BCLK

GPIO1

MCLK1

A_LRC

A_BCLK

D6

D2

C2

D3

GPIO1

A_LRC

MCLK1

A_BCLK

MCLK2

A_ADCD AT

A_DACDAT

MCLK2

IOVDD2

A_DACDAT

A_ADCDAT
D4

D1

F4

IOVDD2

A_DACDATD5A_ADCD AT

ADAU1373_WLCSPU1ADAU1373_WLCSP

0.1uf

IOVDD4

C13

10uf

C13

10uf

SPKVDD

C12

0.1uf

C12

0.1uf

CPVDD

B_LRC

GPIO2

B_ADCDAT

B_BCLK

B_DACDAT

B_BCLK

B_LRC

GPIO2

B_DACDAT

B_ADCD AT

E3

E6

E4

E2

GPIO2

B_LRC

MCLK2

B_BCLK

B_DACDATF6B_ADCD AT

09899-007

C16

0.1uf

C16

0.1uf

GND

GPIO3

GPIO3

IOVDD3

F5

E1

GPIO3

IOVDD3

C15

2.2uF

C15

2.2uF

C_BCLK

C_LRC

C_BCLK

F1

F2

C_BCLK

C_LRC

C_LRC

IOVDD5

GND

GND

C_ADCDAT

C_DACDAT

SDB

JACKDECT

C_ADCDAT

C_DACDAT

SDB

JACKDECT

G6

G5

F3

SDB

C_ADCDATG3C_DACDAT

GND

J1J1

1 2

GND

C19

0.1uF

C19

0.1uF

IOVDD5

100KR2100K

R2

JACKDECT

IOVDD5

SPKGND4

J5

SPKGND3

J1

SPKGND2

H5

SPKGND1

H4

DGND2

E5

DGND1

A1

HPGND

J8

AGND2

F8

AGND1

F7

R1

GND

C18

0.1uF

C18

0.1uF

100KR1100K

SDB JACKDECT

4

2

SW1SW1

GND

3

1

G8

LHP

VMID

SGNDG7RHPG9LHP

B9

C17

1uf

C17

1uf

GND

SGND

RHP

LHP

RHP

SGND

AIN1NA8AIN1P

HPVDD

SPKVDD

U1

AVDD

AIN2PB7AIN2NA7AIN3PB6AIN3NA6AIN4PB5AIN4NA5MICB2

B8

AIN2N

AIN1N

AIN2P

AIN1P

AIN2P

AIN1P

AIN2N

AIN1N

AIN3N

AIN3P

AIN3P

MICB1

C8

AIN4N

AIN4P

MICB1

MICB2

AIN4P

AIN3N

AIN4N

MICB1

LOUTPC7LOUTND8ROUTPD7ROUTN

INFB1E7INFB2

C9

INFB1

LOUTP

LOUTN

MICB2

INFB1

LOUTN

LOUTP

EPPH6EPN

LSPKPJ4LSPKNJ3RSPKPJ2RSPKN

J6

E8

D9

INFB2

ROUTN

EPP

EPN

LSPKN

ROUTP

ROUTP

ROUTN

LSPKP

EPP

EPN

LSPKP

INFB2

LSPKN

VBATSENSEF9BSTEN

H1

G4

VBAT

RSPKN

RSPKP

BSTEN

RSPKP

BSTEN

VBAT

RSPKN

Figure 12. Schematic of the ADAU1373 Evaluation Board, ADAU1373 Chip

Rev. 0 | Page 11 of 24

UG-284 Evaluation Board User Guide

AIN2P

AIN2P

C24

1uF

C24

1uF

MB1

MB2

3

3

2

2

1

1

J3J3

C25

220pF, NC

C25

220pF, NC

R60RR6

0R

1

TP60

J5

AIN2N

AIN2N

C28

1uF

C28

1uF

MB1

C29

220pF, NC

C29

220pF, NC

GND

R80RR8

TP62

123

AUDIOJACKJ5AUDIOJACK

1

GND

TP64

0R

1

R97NCR97

NC

GND

MB2

3
2
1

AIN4P

AIN4P

C32

1uF

C32

1uF

C33

220pF, NC

C33

3
2
1

J7J7

R100RR10

TP66

220pF, NC

0R

1

J9

AIN4N

AIN4N

C36

1uF

C36

1uF

C37

C37

GND

R120RR12

0R

1

TP68

R99NCR99

NC

GND

123

AUDIOJACKJ9AUDIOJACK

09899-008

220pF, NC

220pF, NC

1

GND

TP70

MICB1

1

TP57TP57

C20

0.1uF

C20

0.1uF

2K2R32K2

R3

MB1

MICB2

1

TP58TP58

GND

C21

0.1uF

C21

0.1uF

2K2R42K2

R4

MB2

3
2
1

AIN1P

AIN1P

C22

1uF

C22

1uF

C23

220pF, NC

C23

3
2
1

J2J2

R50RR5

TP59

220pF, NC

0R

1

AIN1N

AIN1N

C26

1uF

C26

1uF

MB1

C27

220pF, NC

C27

220pF, NC

GND

R70RR7

TP61

123

1

GND

TP63

0R

1

R96NCR96

NC

GND

MB2

3

3

2

2

1

1

AIN3P

AIN3P

C30

1uF

C30

1uF

C31

220pF, NC

C31

220pF, NC

J6J6

R90RR9

0R

1

TP65

AIN3N

AIN3N

C34

1uF

C34

1uF

C35

220pF, NC

C35

220pF, NC

GND

R110RR11

TP67

123

1

GND

TP69TP69

0R

1

R98NCR98

NC

GND

J4

AUDIOJACKJ4AUDIOJACK

J8

AUDIOJACKJ8AUDIOJACK

Figure 13. Schematic of the ADAU1373 Evaluation Board—Line Input

Rev. 0 | Page 12 of 24

Evaluation Board User Guide UG-284

J11

J11

AUDIOJACK

123

1

TP72

R14

C39

1uF

LOUTP

LOUTP

1

TP74

R16

100K, NC

C41

1uF

ROUTP

ROUTP

1

TP76

R18

0R

100K, NC

C43

2.2uF

1

INFB1

INFB1

J12

AUDIOJACK

3

1

2

TP80

R24

09899-009

GND

0R

1

J10

AUDIOJACK

123

1

TP71

R13

100K, NC

C38

1uF

LOUTN

LOUTN

1

TP73

C40

ROUTN

ROUTN

TP75

GND GND

R17

0R

C44

NC

R15

100K, NC

GND GND

C42

1uF

2.2uF

TP77

INFB2

INFB2

R20

NC

R19

0R

1

LHP

LHP

TP78

C45

NC

R22

NC

GND

0R

0R

R21

0R

R23

1

RHP

RHP

1

TP79

SGND

SGND

GND

R25

0R,NC

Figure 14. Schematic of the ADAU1373 Evaluation Board—Line and Headphone Output

Rev. 0 | Page 13 of 24

UG-284 Evaluation Board User Guide

J17

112

2

C47

R27

J14J14

GND

NC

L2

NC

TP82

J16J16

1

C49

RSPKP

1

RSPKP

1

GND

1nF, NC

C51

1nF, NC

L4

0R

R28NCR28

NC

1

TP84

TP85

GND

C53

NC

0R

R30

NC

RSPKN

RSPKN

C54

10uf

1

VBAT

L5 2.2uH

1

GND

TP86

VBAT

SPKVDD

R31

100K

BSTEN

BSTEN

J19

1 2

GND

09899-010

J18

112

2

1

TP87

R32 0R

EPP

1

TP88

1

TP89

GND

R33 0R

EPN

C46

R26

J13J13

GND

NC

L1

NC

TP81

J15J15

1

C48

LSPKP

1

LSPKP

1

GND

C50

1nF, NC

1

L3

0R

TP56

TP83

GND

1nF, NC

C52

NC

0R

R29

NC

LSPKN

1

LSPKN

Figure 15. Schematic of the ADAU1373 Evaluation Board—Speaker and Receiver Output

Rev. 0 | Page 14 of 24

Evaluation Board User Guide UG-284

C57

0.1uf

0.1uf

0.1uf

Y

A

GND

GND

GND

MCLK2

MCLK2

1

TP92

0R

IOVDD23V3

GND

TP91

3

1

GND

FXLP34P5X

0R

R39

4

Y

VCC

5
1

U4

GND

VCCI

A

2

IOVDD2

C56

IOVDD1

C55

3V3

MCLK1

MCLK1

1

TP90

R37

4

IOVDD13V3

VCC

5

VCCI

1

U2

2

3

1

FXLP34P5X

09899-011

TP93

GND

2

4

6

1

3

J21

PSIA_MCLK1

0R

R35

R34

NC

R36

NC

3V3

54321

J20

SMA

5

SMA_CLK

112896M_CLK

PSIA_MCLK1

GND

3V3

L6

3

2

OUT

GND

VDD4OE

U3

R38

1

100K

600Z

C58

GNDGND

12.288MHz

0.1uf

246

135

J22

SMA_CLK

112896M_CLK

PSIA_MCLK2

PSIA_MCLK2

Figure 16. Schematic of the ADAU1373 Evaluation Board—Clock

Rev. 0 | Page 15 of 24

UG-284 Evaluation Board User Guide

IOVDD5

R47

100K

GPIO4
1

TP96

GPIO4

MODE

MODE

J24

R46

100K

IOVDD5

SCL

1

TP94

2K2

R45

2K2

IOVDD5

R41

R1040R

2

G

S

1

IOVDD5

3V3

D

Q1,NC

3

NC

R40

113355779

J23

2244668

1

IOVDD5

N-MOSFET

NC

R44

NC

R43

8

1 2

GND

11223344556

SDA

1

TP95

2K2

R49

R1050R

2

G

S

IOVDD5

D

Q2,NC

N-MOSFET

3

NC

R48

9

10
10

GND

CSB

1

TP97

R1060R

2

G

S

1

D

Q3,NC

3

N-MOSFET

GND

12

J25

J47

11223344556

J46

R51

IOVDD4

DMIC2

1

TP99

DMIC2

11223344556

J45

11223344556

J44

R50

IOVDD4

DMIC1

1

TP98

DMIC1

100K

DMCLK

100K

TP100

R52

DMCLK

1

09899-012

CON1x6

6

CON1x6

6

GND

CON1x6

6

CON1x6

6

GND

0R

DMICCLK

NC

R42

Figure 17. Schematic of the ADAU1373 Evaluation Board—I

2

C Port and Digital Microphone Interface

Rev. 0 | Page 16 of 24

Evaluation Board User Guide UG-284

IOVDD2

C60

R54

GPIO2

R56 100K

1

TP104

GND

GPIO2

22pF

R58

49R9

J29J29

PSIA_MCLK2

1

TP102

PSIA_MCLK2

TP106

GND

C62

22pF

0R

R62

R60

49R9

246

13579

B_BCLK

1

B_BCLK_J B_BCLK

C64

0R

R64

B_LRC

1

TP108

GND

B_LRC

22pF

R66

49R9

B_LRC_J

8

10

B_DACDAT

1

TP110

GND

C66

22pF

B_DACDAT

0R

R68

49R9

12

11

GND

C68

R70

B_ADCDAT

1

TP112

GND

B_ADCDAT

22pF

R72

0R

49R9

B_ADCD AT_J

1

TP119

1

TP118

1

GND

TP117

1

TP116

09899-013

IOVDD1

C59

R53

GPIO1

R55 100K

1

TP103

GND

GPIO1

22pF

R57

49R9

J28J28

PSIA_MCLK1

1

TP101

PSIA_MCLK1

C61

0R

R59

TP105

GND

22pF

R61

49R9

A_BCLK_J A_BCLK

246

135

A_BCLK

1

C63

0R

R63

A_LRC

1

TP107

GND

22pF

R65

49R9

A_LRC_J A_LRC

8

10

9

7

C65

0R

R67

12

11

A_DACDAT

1

TP109

GND

A_DACDAT

22pF

49R9

GND

C67

R69

A_ADCDAT

1

TP111

GND

A_ADCDAT

22pF

R71

0R

49R9

A_ADCDAT_J

IOVDD3

GPIO3

R73 100K

1

TP113

GPIO3

R74

J30

TP114

GND

C69

22pF

R76

0R

R75

49R9

246

13579

C_BCLK

1

C_BCLK

C70

0R

R77

C_BCLK_J

C_LRC

1

TP115

GND

C_LRC

22pF

R78

49R9

C_LRC_J

8

10

C71

0R

R79

12

11

C_DACDAT

1

TP120

GND

22pF

C_DACDAT

49R9

GND

C72

R80

C_ADCDAT

1

TP121

GND

22pF

C_ADCDAT

R81

0R

49R9

C_ADCDAT_J

Figure 18. Schematic of the ADAU1373 Evaluation Board—Digital Audio Interface

Rev. 0 | Page 17 of 24

UG-284 Evaluation Board User Guide

C80

1

TP123

DVDD

D2

GREEN

R83

1K

12

J32

5V

1

3

2

IN

EN

U6

OUT

GND05GND16GND27GND3

0.1uf

1

R85

10K

C78

10uf

C77

0.1uF

C79

10nF

4

ADJ

ADP1715_1V5

8

TP125

1

2 3

Q5

MMBT3904

5V

C96

1nF

L7

600Z

J35

1 2

321

J34

PowerJack

09899-014

GND

C84

C76

1

TP122

AVDD

D1

GREEN

R82

12

1K

J31

5V

1

3

2

IN

EN

U5

OUT

GND05GND16GND27GND3

0.1uf

1

R84

10K

C75

10uf

C74

0.1uF

C73

10nF

4

ADJ

ADP1715_1V8

8

TP124

1

2 3

Q4

MMBT3904

GND GND

D3

5V

1

TP126

HPVDD

GREEN

R86

1K

1K

12

J33

1

4

3

2

IN

EN

U7

OUT

GND05GND16GND27GND3

8

0.1uf
1

TP127

2 3

Q6

1

R87

10K

MMBT3904

C82

10uf

C81

0.1uF

C83

10nF

ADJ

ADP1715_1V8

GND

Figure 19. Schematic of the ADAU1373 Evaluation Board—Power Supply

Rev. 0 | Page 18 of 24

Evaluation Board User Guide UG-284

TP141

IOVDD5

1

1

TP138

1

TP129TP129

1V8

R91

10K

R91

3

2

IN

EN

OUT

GND05GND16GND27GND3

1

3

2

IN

OUT

10K

C91

C91

C92

C92

C89

C89

C90

C90

4

ADJ

ADP1715_1V8U9ADP1715_1V8

8

1

R90

10K

R90

10K

C86

C86

C88

10uf

C88

10uf

C87

0.1uF

C87

0.1uF

C85

C85

4

ADJ

ADP1715_3V3U8ADP1715_3V3

8

D5

GREEND5GREEN

R891KR89

1K

5V

1

U9

TP128TP128

3V3

D4

GREEND4GREEN

R881KR88

1K

5V

1

EN

U8

GND05GND16GND27GND3

TP131TP131

2 3

1

GND

Q8

1

MMBT3904Q8MMBT3904

10uf

10uf

10uf

10uf

0.1uF

0.1uF

10nF

10nF

TP130TP130

2 3

1

GND

Q7

MMBT3904Q7MMBT3904

10uf

10uf

10nF

10nF

246

135

J38

1V8

3V3

IOVDD4

1

TP135

246

135

J37

1V8

3V3

IOVDD3

1

TP134

246

135

J39

1V8

3V3

IOVDD2

1

TP133

246

135

J36

1V8

3V3

IOVDD1

1

TP132

246

135

J43

1V8

3V3

CON2x3

2V4

TP140

1

CON2x3

TP139

1

CON2x3

TP136

1

CON2x3

TP137

1

GND GND GND GND GND

CON2x3

2V4 2V 4 2V4 2V4

D7

5V

D6

D6

5V

1

TP142

2V4

1

Q10

R101

10K

GREEN

R100

1K

R103

1

4

3

2

IN

EN

U10

ADJ

OUT

GND05GND16GND27GND3

8

J41

1

1

TP143

SPKVDD

R94

GREEN

R92

1K

J40

1 2

R93

8

5

7

ADJ

OUT16OUT2

SENSE

PAD

U11

EN1GND2IN13IN2

4

MMBT3904

C97

10uf

C98

10uf

C100

0.1uF

2K

R102

1K

ADP1715_ADJ

J42

C95

10uf

Q9

1

10K

MMBT3904

R95

3.48K

ADP1708

9

C94

10uf

C93

0.1uF

09899-015

TP144

1

2 3

GND

1

1

TP145

2 3

1k

GND

Figure 20. Schematic of the ADAU1373 Evaluation Board—Power Supply

Rev. 0 | Page 19 of 24

UG-284 Evaluation Board User Guide

ORDERING INFORMATION

BILL OF MATERIALS

Table 23.

Qty Part Reference Description Manufacturer Part Number

9 C1, C11, C12, C14, C16, C2, C6, C7, C9 MLCC, 0.1 μF, 0402 Panasonic ECJ-0EX1C104K
3 C10, C3, C5, MLCC, 2.2 μF, 0603 Panasonic ECJ-1VB1A225K
13

C13, C54, C75, C78, C82, C86, C88, C91, C92,

C94, C95, C97, C98
1 C17 MLCC, 1 μF, 0402 Panasonic ECJ-0EB1A105M
12

C22, C24, C26, C28, C30, C32, C34, C36, C38,

C39, C40, C41
21

C18, C19, C20, C21, C42, C43, C55, C56, C57,

C58, C74, C76, C77, C80, C81, C84, C87, C89,

C93, C96, C100
3 C4, C8, C15 MLCC, 2.2 μF, 0402 Panasonic ECJ-0EB0J225M
6 C44, C45, C46, C47, C52, C53 Capacitor (open)
4 C48, C49, C50, C51 Capacitor (open)
8 C23, C25, C27, C29, C31, C33, C35, C37 Capacitor (open)
14

C59, C60, C61, C62, C63, C64, C65, C66, C67,

C68, C69, C70, C71, C72
5 C73, C79, C83, C85, C90 MLCC, 10 nF, 0603 Panasonic ECJ-1VB1H103K
7 D1, D2, D3, D4, D5, D6, D7, LED, green Lumex SML-LXT0805GW-TR
8 J1, J19, J24, J25, J31, J32, J33, J40 Jumper, 2 mm pitch
7 J10, J11, J12, J4, J5, J8, J9 Stereo audio jack CUI SJ-3523-SMT
6 J13, J14, J15, J16, J41, J42 Binding post connector Johnson/Emerson 111-2223-001
3 J17, J18, J35 Jumper, 2.54 mm pitch
4 J2, J3, J6, J7 Header, 3-way (1 × 3)
1 J20 SMA header MULTICOMP 60-04 TGG
7 J21, J22, J36, J37, J38, J39, J43 Header, 6-way (2 × 3)
1 J23 Header, 10-way (2 × 5), polarized
3 J28, J29, J30 Header, 12-way (2 × 6)
1 J34 Power jack Switchcraft Inc. RAPC712
4 J44, J45, J46, J47 Header, 6-way (1 × 6)
4 L1, L2, L3, L4 Chip resistor, 0 Ω, 0805 Panasonic ERJ-6GEY0R00V
1 L5 Inductor (open)
2 L6, L7 Chip ferrite bead, 600 Ω at 100 MHz TDK MPZ1608S601A
3 Q1, Q2, Q3 N-MOSFET (open)
7 Q10, Q4, Q5, Q6, Q7, Q8, Q9 Transistor, NPN, SOT23

11

R1, R2, R31, R38, R46, R47, R50, R51, R55, R56,

R73
33

R10, R104, R105, R106, R11, R12, R17, R18,

R19, R21, R23, R24, R35, R37, R39, R5, R52,

R57, R58, R6, R61, R62, R65, R66, R7, R71, R72,

R74, R76, R78, R8, R81, R9
9 R100, R102, R82, R83, R86, R88, R89, R92, R95 Chip resistor, 1 kΩ, 0603 Panasonic ERJ-3EKF1001V
7 R101, R84, R85, R87, R90, R91, R94 Chip resistor, 10 kΩ, 0603 Panasonic ERJ-3EKF1002V
1 R103 Chip resistor, 2 kΩ, 0603 Panasonic ERJ-3EKF2001V
4 R13, R14, R15, R16 Chip resistor (open)
18

R20, R22, R26, R27, R28, R29, R30, R34, R36,

R40, R42, R43, R44, R48, R96, R97, R98, R99
1 R25 Chip resistor (open)
5 R3, R4, R41, R45, R49 Chip resistor, 2.2 kΩ, 0603 Panasonic ERJ-3EKF2201V
2 R32, R33 Chip resistor, 0 Ω, 0805 Panasonic ERJ-6GEY0R00V

MLCC, 10 μF, 0805 Panasonic ECJ-2FF1A106Z

MLCC, 1 μF, 0603 Panasonic ECJ-1VB1A105K

MLCC, 0.1 μF, 0603 Panasonic ECJ-1VB1H104K

Capacitor (open)

ON
Semiconductor

Chip resistor, 100 kΩ, 0603 Panasonic ERJ-3EKF1003V

Chip resistor, 0 Ω, 0603 Panasonic ERJ-3GEY0R00V

Chip resistor (open)

MMBT3904LT1G

Rev. 0 | Page 20 of 24

Evaluation Board User Guide UG-284

Qty Part Reference Description Manufacturer Part Number

14

R53, R54, R59, R60, R63, R64, R67, R68, R69,

R70, R75, R77, R79, R80,
1 R93 3.48 kΩ Panasonic ERJ-3EKF3481V
1 SW1 Push-button
1 U1 ADAU1373 ADI
1 U10 Low dropout voltage regulator ADI ADP1715_ADJ
1 U11 Low dropout voltage regulator ADI ADP1708
2 U2, U4 Translator, 1-bit, unidirectional Fairchild FXLP34P5X
1 U3 Oscillator, 12.288 MHz Abracon ASFL1-12.288MHZ-EC-T
3 U5, U7, U9 Low dropout voltage regulator ADI ADP1715_1V8
1 U6 Low dropout voltage regulator ADI ADP1715_1V5
1 U8 Low dropout voltage regulator ADI ADP1715_3V3

RELATED LINKS

Resource Description

ADAU1373 Product Page, Low Power Codec with Speaker and Headphone Amplifier
AN-1006 Application Note, Using the EVAL-ADUSB2EBZ
ADP1715 Product Page, 500 mA Low-Dropout CMOS Linear Regulator with Soft Start
ADP1708 Product Page, 1 A, Low Dropout, CMOS Linear Regulator

Chip resistor (open)

Rev. 0 | Page 21 of 24

UG-284 Evaluation Board User Guide

NOTES

Rev. 0 | Page 22 of 24

Evaluation Board User Guide UG-284

NOTES

Rev. 0 | Page 23 of 24

UG-284 Evaluation Board User Guide

NOTES

ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection

circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

Legal Terms and Conditions

By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions
set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you
have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc.
(“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal,
temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided
for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional
limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term
“Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including
ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may
not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to
promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any
occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board.
Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice
to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO
WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED
TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL
PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF
THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE
AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable
United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of
Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby
submits to the pers onal jurisdiction and venu e of such courts. The United Nations Conventi on on Contracts for the Internation al Sale of Goods shall not apply to this Agreement and is expressly disclaimed.

©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
UG09899-0-6/11(0)

Rev. 0 | Page 24 of 24