ANALOG DEVICES UG-237 Service Manual

Hardware User Guide

UG-237

One Technology Way • P. O . Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel : 781.329.4700 • Fax : 781.461.3113 • www.analog.com

Dual Port Xpressview™ Advantiv HDMI Receiver Functionality and Features

SCOPE

This user guide provides a detailed description of the Advantiv™ ADV7619 functionality and features.

DISCLAIMER

Information furnished by Analog Devices, Inc. is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

XTALP XTALN

RXA_5V RXB_5V

HPA_A/INT2

HPA_B

DDCA_SDA

DDCA_SCL

DDCB_SDA

DDCB_SCL

RXA_C±

RXA_0± RXA_1±

RXA_2±

RXB_C±

RXB_0± RXB_1±

RXB_2±

SCL SDA

CEC

DPLL

CONTRO L

CEC

CONTROLL ER

5V DETECT

AND HPD

CONTROLL ER

EDID

REPEATER

CONTROLL ER

PLL

EQUALIZER SAMPLER

PLL

EQUALIZER SAMPLER

INTERFACE

HDCP

EEPROM

HDCP

ENGINE

CONTROL

AND DATA

HDMI

PROCESSOR

DATA

PREPROCESSO R

AND COLOR

SPACE

CONVERSION

XPressView™

FAST SWITCHING

PACKET

PROCESSOR

Figure 1. Functional Block Diagram

3Gbs VIDEO PATH

BACKEND

COLOR SPACE

CONVERSION

COMPONENT PROCESSOR

A B C

PACKET/

INFOFRAME

MEMORY

INTERRUPT

CONTRO LLER

(INT1, INT2)

MUTE

AUDIO

PROCESSOR

ADV7619

AUDIO OUTPUT FORMATTER VIDEO OUT PUT FORMATTER

P0 TO P11

P12 TO P23

P24 TO P35

P36 TO P47

LLC

HS/CS

VS/FIELD/ALSB

INT1

AP1/I2S_TDM

AP2

AP3

AP4

AP5

SCLK/INT2

MCLK/INT2

AP0

09581-001

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS.

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UG-237 Hardware User Guide

Scope .................................................................................................. 1

Disclaimer .......................................................................................... 1

Revision History ............................................................................... 3

Using the ADV7619 Hardware User Guide .................................. 4

Number Notations ........................................................................ 4

Acronyms and Abbreviations ..................................................... 4

Field Function Descriptions ........................................................ 6

References ...................................................................................... 6

Introduction to the ADV7619 ........................................................ 7

HDMI Receiver ............................................................................. 7

Component Processor ................................................................. 7

Main Features of ADV7619 ........................................................ 7

Functional Block Diagram .......................................................... 9

Pin Configuration and Function Descriptions ....................... 10

Global Control Registers ............................................................... 15

ADV7619 Revision Identification ............................................ 15

Power-Down Controls ............................................................... 15

Global Pin Control ..................................................................... 17

Primary Mode and Video Standard ............................................. 22

Primary Mode and Video Standard Controls ......................... 22

HDMI Decimation Modes ........................................................ 24

Primary Mode and Video Standard Configuration for HDMI

Free Run ....................................................................................... 24

Recommended Settings for HDMI Inputs .............................. 25

Pixel Port Configuration ................................................................ 27

Pixel Port Output Modes ........................................................... 27

DDR Output Interface ............................................................... 28

LLC Controls ............................................................................... 29

DLL on LLC Clock Path ............................................................ 29

HDMI Receiver ............................................................................... 30

+5 V Cable Detect ...................................................................... 30

Hot Plug Assert ........................................................................... 31

E-EDID/Repeater Controller .................................................... 33

E-EDID Data Configuration ..................................................... 33

Transitioning of Power Modes .................................................. 35

Structure of Internal E-EDID for Port A ................................. 35

Structure of Internal E-EDID for Port B ................................. 36

TMDS Equalization .................................................................... 39

Port Selection .............................................................................. 39

Fast Switching and Background Port Selection ...................... 39

TMDS Clock Activity Detection .............................................. 40

HDMI/DVI Status Bits .............................................................. 41

Video 3D Detection ................................................................... 42

TMDS Measurement.................................................................. 42

Deep Color Mode Support ........................................................ 45

Video FIFO .................................................................................. 46

Pixel Repetition .......................................................................... 47

HDCP Support ........................................................................... 49

HDMI Synchronization Parameters ........................................ 52

Audio Control and Configuration ........................................... 58

Audio FIFO ................................................................................. 60

Audio Packet Type Flags ........................................................... 61

Audio Output Interface ............................................................. 63

MCLKOUT Setting .................................................................... 71

Audio Channel Mode ................................................................ 71

Audio Muting .............................................................................. 71

Audio Clock Regeneration Parameters ................................... 76

Channel Status ............................................................................ 77

Packets and InfoFrames Registers ............................................ 81

Packet Registers .......................................................................... 88

Customizing Packet/InfoFrame Storage Registers ................. 92

Repeater Support ........................................................................ 93

Interface to DPP Section ......................................................... 100

Pass Through Mode ................................................................. 101

Color Space Information Sent to the DPP and CP

Sections ...................................................................................... 102

Status Registers ......................................................................... 102

HDMI Section Reset Strategy ................................................. 105

HDMI Packet Detection Flag Reset ....................................... 105

Data Preprocessor and Color Space Conversion and Color

Controls ......................................................................................... 106

Color Space Conversion Matrix ............................................. 106

Color Controls .......................................................................... 115

Component Processor ................................................................. 117

Introduction to the Component Processor ........................... 117

Clamp Operation ...................................................................... 117

CP Gain Operation .................................................................. 119

CP Offset Block ........................................................................ 122

AV Code Block ......................................................................... 124

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Hardware User Guide UG-237

CP Data Path for HDMI Modes ............................................. 125

Sync Processed by CP Section ................................................ 129

CP Output Synchronization Signal Positioning ................... 136

CP HDMI Controls .................................................................. 148

Free Run Mode ......................................................................... 148

CP Status ................................................................................... 152

CP Core Bypassing ....................................................................... 152

Consumer Electronics Control ................................................... 153

Main Controls ........................................................................... 153

CEC Transmit Section ............................................................. 154

CEC Receive Section ................................................................ 156

Antiglitch Filter Module .......................................................... 161

Typical Operation Flow ........................................................... 162

Low Power CEC Message Monitoring .................................. 165

Interrupts ....................................................................................... 167

Interrupt Architecture Overview ........................................... 167

Interrupt Pins ............................................................................ 170

Description of Interrupt Bits ................................................... 173

Additional Explanations .......................................................... 174

Main I2C Port ............................................................................. 189

DDC Ports .................................................................................. 191

Appendix A .................................................................................... 193

PCB Layout Recommendations .............................................. 193

Power Supply Bypassing ........................................................... 193

Digital Outputs (Data and Clocks) ......................................... 193

Digital Inputs ............................................................................. 194

XTAL and Load Cap Value Selection ..................................... 194

Appendix B .................................................................................... 195

Recommended Unused Pin Configurations ......................... 195

Appendix C .................................................................................... 198

Pixel Output Formats ............................................................... 198

REVISION HISTORY

12/11—Rev. 0 to Rev. A

Changes to the Fourth Paragraph of the Introduction to the

ADV7619 Section .............................................................................. 7

Changes to Video Output Formats Section ................................... 8

Changes to Pin 113 Description .................................................... 13

Changes to Table 7 .......................................................................... 25

Added Endnote 1 and Endnote 2 to OP_FORMAT_SEL[7:0], IO,

Address 0x03[7:0] Section .............................................................. 27

Changes to DLL on LLC Clock Path Section .............................. 29

Changes to CS_DATA[27:24], Sampling Fequency, HDMI Map,

Address 0x39[3:0] Section .............................................................. 80

Changes to Check the Value of Each Coefficient Section........114

Changes to CP_HUE[7:0], Addr 44 (CP), Address 0x3D[7:0]

Section ............................................................................................116

Changes to CP Core Bypassing Section .....................................152

Changes to INT2_POL, IO, Address 0x41[2] Section ..............171

Added Endnote 1 to Table 76 ......................................................198

Added Endnote 1 to Table 81 ......................................................203

8/11—Revision 0: Initial Version

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UG-237 Hardware User Guide

USING THE ADV7619 HARDWARE USER GUIDE

NUMBER NOTATIONS

Table 1.

Notation Description

Bit N Bits are numbered in little endian format, that is, the least significant bit of a number is referred to as Bit 0. V[X:Y] Bit field representation covering Bit X to Bit Y of a value or a field (V). 0xNN Hexadecimal (base-16) numbers are preceded by the prefix ‘0x’. 0bNN Binary (base-2) numbers are preceded by the prefix ‘0b’. NN Decimal (base-10) are represented using no additional prefixes or suffixes.

REGISTER ACCESS CONVENTIONS

Table 2.

Mode Description

R/W Memory location has read and write access. R Memory location is read access only. A read always returns 0 unless otherwise specified. W Memory location is write access only.

ACRONYMS AND ABBREVIATIONS

Table 3.

Acronym/Abbreviation Description

ACP Audio content protection. AGC Automatic gain control. Ainfo HDCP register. Refer to HDCP documentation. AKSV HDCP transmitter key selection vector. Refer to HDCP documentation. An 64-bit pseudo-random value generated by HDCP cipher function of Device A. AP Audio output pin. AVI Auxiliary video information. BCAPS HDCP register. Refer to HDCP documentation. BKSV HDCP receiver key selection vector. Refer to HDCP documentation. CP Component processor. CSC Color space converter/conversion. DDR Double data rate. DE Data enable. DLL Delay locked loop. DPP Data preprocessor. DVI Digital visual interface. EAV End of active video. EMC Electromagnetic compatibility. EQ Equalizer. HD High definition. HDCP High bandwidth digital content protection. HDMI® High bandwidth multimedia interface. HDTV High definition television. HPA Hot plug assert. HPD Hot plug detect. HSync Horizontal synchronization. IC Integrated circuit. ISRC International standard recording code. I2S Inter IC sound. I2C Inter integrated circuit.

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Hardware User Guide UG-237

Acronym/Abbreviation Description

KSV Key selection vector. LLC Line locked clock. LSB Least significant bit. L-PCM Linear pulse coded modulated. Mbps Megabit per second. MPEG Moving picture expert group. ms Millisecond. MSB Most significant bit. NC No connect. OTP One-time programmable. Pj’ HDCP enhanced link verification response. Refer to HDCP documentation. Ri’ HDCP link verification response. Refer to HDCP documentation. Rx Receiver. SAV Start of active video. SDR Single data rate. SHA-1 Refer to HDCP documentation. SMPTE Society of Motion Picture and Television Engineers. SOG Sync on green. SOY Sync on Y. SPA Source physical address. SPD Source production descriptor. STDI Standard detection and identification. TDM Time division multiplexed. TMDS Transition minimized differential signaling. Tx Transmitter. VBI Video blanking interval. VSync Vertical synchronization. XTAL Crystal oscillator.

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UG-237 Hardware User Guide

FIELD FUNCTION DESCRIPTIONS

Throughout this user guide, a series of function tables are provided. The function of a field is described in a table preceded by the bit name, a short function description, the I

The detailed description consists of:

• For a readable field, the values the field can take

• For a writable field, the values the field can be set to

Example Field Function Description

This section provides an example of a field function table followed by a description of each part of the table.

PRIM_MODE[3:0], IO Map, Address 0x01[3:0].

A control to select the primary mode of operation of the decoder.

Function PRIM_MODE[3:0] Description

0000 Reserved 0001 Reserved 0010 Reserved 0011 Reserved 0100 Reserved 0101 HDMI-Comp 0110 (default) HDMI-GR 0111 to 1111 Reserved

In this example

• The name of the field is PRIM_MODE and it is four bit long.

• Address 0x01 is the I

C location of the field in big endian format (MSB first, LSB last).

• The address is followed by a detailed description of the field.

C map, the register location within the I2C map, and a detailed description of the field.

• The first column of the table lists values the field can take or can be set to. These values are in binary format if not preceded by 0x or

in hexadecimal format if preceded by 0x.

• The second column describes the function of each field for each value the field can take or can be set to. Values are in binary format.

REFERENCES

CEA, CEA-861-D, A DTV Profile for Uncompressed High Speed Digital Interfaces, Revision D, July 18, 2006.

Digital Content Protection (DCP) LLC, High-Bandwidth Digital Content Protection System, Revision 1.4, July 8, 2009.

HDMI Licensing and LLC, High-Definition Multimedia Interface, Revision 1.4a, March 4, 2010.

ITU, ITU-R BT.656-4, Interface for Digital Component Video Signals in 525-Line and 625-Line Television Systems Operating at the 4:2:2 Level of Recommendation ITU-R BT.601, February 1998.

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Hardware User Guide UG-237

INTRODUCTION TO THE ADV7619

The ADV7619 is a high quality, 3Gbps high bandwidth, 2:1 multiplexed High-Definition Multimedia Interface (HDMI®) receiver.

The ADV7619 incorporates a dual input HDMI receiver that supports all mandatory 3D TV formats defined in HDMI 1.4a specification, HDTV formats up to 1080p deep color 12-bit per channel or 2160p8bit color per channel and display resolutions up to 4k by 2k (3840 x 2160 at 30 Hz).

The ADV7619 also integrates an CEC controller that supports the capability discovery and control (CDC) feature.

The ADV7619 incorporates Xpressview™ fast switching on both input HDMI ports. Using Analog Devices’ hardware-based HDCP engine that minimizes software overhead, Xpressview™ technology allows fast switching between both HDMI input ports in less than 1 second. Each HDMI port has dedicated +5V Detect and Hot Plug Assert pins. The HDMI receiver also includes an integrated equalizer that ensures robust operation of the interface with long cables.

Fabricated in an advanced CMOS process, the ADV7619 is provided in a 14 mm × 14 mm, 128-pin surface-mount TQFP_EP, RoHScompliant package and is specified over 0°C to +70°C temperature range.

HDMI RECEIVER

The HDMI receiver on the ADV7619 supports 3Gbps data bandwidth allowing for video resolutions up to 4k by 2k. incorporates a fast switching feature that allows inactive ports to be HDCP authenticated to provide rapid switching between encrypted HDMI sources. The ADV7619 HDMI receiver incorporates active equalization of the HDMI data signals to compensate for the losses inherent in HDMI and DVI cabling, especially at longer lengths and higher frequencies. The equalizer is highly effective and is capable of equalizing for long cables to achieve robust receiver performance.

With the inclusion of HDCP, displays can receive encrypted video content. The HDMI interface of the ADV7619 allows a video receiver to authenticate, decrypt encoded data and renew that authentication during transmission, as specified by the HDCP v1.4 protocol for both active and background HDMI ports.

The ADV7619 offers a flexible audio output port for audio data extraction from the HDMI stream. HDMI audio formats, including Super Audio CD (SACD) via DSD and HBR are supported by ADV7619. The HDMI receiver has advanced audio functionality, such as a mute controller, that prevents audible extraneous noise in the audio output. Additionally ADV7619 can be set to output Time Division Multiplexed I

S, which provides four multiplexed I2S channels.

COMPONENT PROCESSOR

The ADV7619 contains component processor (CP), which processes the video data up to 1080p 36-bitdeep color. The CP section provides color adjustment features, such as brightness, saturation, and hue. The color space conversion (CSC) matrix allows the color space to be changed as required. The standard detection and identification (STDI) block allows the detection of video timings.

MAIN FEATURES OF ADV7619

HDMI Receiver

• HDMI 1.4a features supported

• 3D HDMI 1.4a video format support

• Full colorimetry including sYCC601, Adobe RGB, Adobe YCC601, xvYCC extended gamut color

• CEC 1.4-compatible

• HDCP 1.4 support

• 3D Video Support including Frame packing for all 3D formats up to a 297 MHz TMDS clock

• Xpressview™ fast switching between HDMI ports

• Supports display resolutions up to 4k by 2k (4096 x 2160 at 30 Hz)

• Supports all display resolutions up to UXGA (1600 x 1200 at 60Hz, 10-bit)

• Supports many audio formats including DSD, HBR, S/PDIF (IEC60958-compatible) with sampling with sampling frequency up to

192 kHz

• Programmable front-end equalization for long cable lengths

• Audio mute for removing extraneous noise

• Programmable interrupt generator to detect HDMI packets

• Internal EDID support

• Repeater support (up to 127 KSVs)

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UG-237 Hardware User Guide

Component Video Processing

• Support video formats only up to 1080p 36-bit deep color and graphics up to UXGA 10-bit

• An any-to-any 3 × 3 CSC matrix support YCrCb to RGB and RGB to YCrCb

• Provides color controls, such as saturation, brightness, hue, and contrast

• STDI block that enables format detection

• Free run output mode provides stable timing when no video input is present

Video Output Formats

• Double data rate (DDR) 8-/10-/12-bit 4:2:2 YCrCb1

• Pseudo DDR (CCIR-656 type stream) 8-/10-/12-bit 4:2:2 YCrCb for 525i, 625i, 525P, and 625P

• SDR 16-/20-/24-bit 4:2:2 YCrCb for all standards

• SDR 24-/30-/36-bit 4:4:4 YCrCb/RGB for all HDMI standards

• DDR 12-/24-/30-/36-bit 4:4:4 RGB

• Interleaved 2x SDR 24 bit 422 YCrCb

• Interleaved 2x SDR 24 bit 444 YCrCb/RGB

Double data rate (DDR) is supported only up to 50 MHz (an equivalent to data rate clocked with 100 MHz clock in SDR mode).

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Hardware User Guide UG-237

Additional Features

• HS, VS, FIELD, and DE output signals with programmable position, polarity, and width

• Numerous interrupt sources available for the INT1 and INT2 interrupt request output pins, available via one of the selected pins, that

is, SCLK/INT2, MCLK/INT2, or HPA_A/INT2

• Temperature range of 0°C to +70°C

• 14 mm × 14 mm, 128-pin TQFP_EP package

FUNCTIONAL BLOCK DIAGRAM

XTALP XTALN

SCL SDA

CEC

RXA_5V RXB_5V

HPA_A/INT2

HPA_B

DDCA_SDA

DDCA_SCL

DDCB_SDA

DDCB_SCL

RXA_C±

RXA_0± RXA_1±

RXA_2±

RXB_C±

RXB_0± RXB_1±

RXB_2±

DPLL

CONTRO L

CEC

CONTROLL ER

5V DETECT

AND HPD

CONTROLL ER

EDID

REPEATER

CONTROLL ER

PLL

EQUALIZER SAMPLER

PLL

EQUALIZER SAMPLER

INTERFACE

HDCP

EEPROM

HDCP

ENGINE

CONTROL

AND DATA

HDMI

PROCESSOR

DATA

PREPROCESSO R

AND COLOR

SPACE

CONVERSION

XPressView™

FAST SWITCHING

PACKET

PROCESSOR

Figure 2. Functional Block Diagram

3Gbs VIDEO PATH

BACKEND

COLOR SPACE

CONVERSION

COMPONENT PROCESSOR

A B C

PACKET/

INFOFRAME

MEMORY

INTERRUPT

CONTRO LLER

(INT1, INT2)

MUTE

AUDIO

PROCESSOR

ADV7619

AUDIO OUTPUT FORMATTER VIDEO OUTPUT FORMATTER

P0 TO P11

P12 TO P23

P24 TO P35

P36 TO P47

LLC

HS/CS

VS/FIELD/ALSB

INT1

AP1/I2S_TDM

AP2

AP3

AP4

AP5

SCLK/INT2

MCLK/INT2

AP0

09581-001

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UG-237 Hardware User Guide

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DDCA_SDA

RXA_5V

HPA_A/I NT2

RXB_5V

HPA_B

DDCB_SDA

DDCB_SCL

128NC127

DDCA_SCL

123

126

125

124

122

121

DVDD

CEC

120

119

118

117

XTALN

116

115

PVDD

XTALP

114

113CS112

INT1

SCL

SDA

DVDD

RESET

109

110

111

AP5

MCLK/INT2

SCLK/INT2

AP4

AP2

AP3

AP1/I2S_TDM

AP099NC98NC97NC

108

107

106

105

104

103

102

101

100

GND

CVDD

RXA_C–

RXA_C+

TVDD

RXA_0–

RXA_0+

TVDD

RXA_1–

RXA_1+

TVDD

RXA_2–

RXA_2+

CVDD

GND

TEST1

DVDD

TEST2

CVDD

RXB_C–

RXB_C+

TVDD

RXB_0–

RXB_0+

TVDD

RXB_1–

RXB_1+

TVDD

RXB_2–

RXB_2+

CVDD

GND

PIN 1

ADV7619

TOP VIEW

(Not to Scale)

VS/FIELD/ALSB

DVDDIO

P10

P11

DVDD

P12

DVDDIO

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

P23

DVDDIO

P4736P46

DVDD

NOTES

1. NC = NO CONNECT . DO NOT CONENCT T O THIS PIN.

2. THE EXPO SED PADDLE SHOULD BE CONNE CTED TO GROUND.

P45

P43

P44

DVDDIO

P4242P41

P40

P39

P3846P37

P35

P36

P3351P32

P34

P30

P31

DVDD

DVDDIO

P2957P28

LLC

DVDD64DVDD

P26

P27

P2561P24

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Type Description

0 GND Ground Ground. 1 GND Ground Ground. 2 CVDD Power HDMI Analog Block Supply Voltage (1.8 V). 3 RXA_C− HDMI input Digital Input Clock Complement of Port A in the HDMI Interface. 4 RXA_C+ HDMI input Digital Input Clock True of Port A in the HDMI Interface. 5 TVDD Power Terminator Supply Voltage (3.3 V). 6 RXA_0− HDMI input Digital Input Channel 0 Complement of Port A in the HDMI Interface. 7 RXA_0+ HDMI input Digital Input Channel 0 True of Port A in the HDMI Interface. 8 TVDD Power Terminator Supply Voltage (3.3 V). 9 RXA_1− HDMI input Digital Input Channel 1 Complement of Port A in the HDMI Interface. 10 RXA_1+ HDMI input Digital Input Channel 1 True of Port A in the HDMI Interface.

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09581-002

Hardware User Guide UG-237

Pin No. Mnemonic Type Description

11 TVDD Power Terminator Supply Voltage (3.3 V). 12 RXA_2− HDMI input Digital Input Channel 2 Complement of Port A in the HDMI Interface. 13 RXA_2+ HDMI input Digital Input Channel 2 True of Port A in the HDMI Interface. 14 CVDD Power HDMI Analog Block Supply Voltage (1.8 V). 15 GND Ground Ground. 16 TEST1 Test This pin must be left floating. 17 DVDD Power Digital Core Supply Voltage (1.8 V) 18 TEST2 Test This pin must be left floating. 19 CVDD Power HDMI Analog Block Supply Voltage (1.8 V). 20 RXB_C− HDMI input Digital Input Clock Complement of Port B in the HDMI Interface. 21 RXB_C+ HDMI input Digital Input Clock True of Port B in the HDMI Interface. 22 TVDD Power Terminator Supply Voltage (3.3 V). 23 RXB_0− HDMI input Digital Input Channel 0 Complement of Port B in the HDMI Interface. 24 RXB_0+ HDMI input Digital Input Channel 0 True of Port B in the HDMI Interface. 25 TVDD Power Terminator Supply Voltage (3.3 V). 26 RXB_1− HDMI input Digital Input Channel 1 Complement of Port B in the HDMI Interface. 27 RXB_1+ HDMI input Digital Input Channel 1 True of Port B in the HDMI Interface. 28 TVDD Power Terminator Supply Voltage (3.3 V). 29 RXB_2− HDMI input Digital Input Channel 2 Complement of Port B in the HDMI Interface. 30 RXB_2+ HDMI input Digital Input Channel 2 True of Port B in the HDMI Interface. 31 CVDD Power HDMI Analog Block Supply Voltage (1.8 V). 32 GND Ground Ground. 33 NC No connect No connect. 34 DVDD Power Digital Core Supply Voltage (1.8 V). 35 P47 Digital video

output

36 P46 Digital video

output

37 P45 Digital video

output

38 P44 Digital video

output

39 P43 Digital video

output

40 DVDDIO Power Digital I/O Supply Voltage (3.3 V). 41 P42 Digital video

output

42 P41 Digital video

output

43 P40 Digital video

output

44 P39 Digital video

output

45 P38 Digital video

output

46 P37 Digital video

output

47 P36 Digital video

output

48 P35 Digital video

output

49 P34 Digital video

output

50 P33 Digital video

output

51 P32 Digital video

output

52 DVDDIO Power Digital I/O Supply Voltage (3.3 V).

Video Pixel Output Port.

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Pin No. Mnemonic Type Description

53 DVDD Power Digital Core Supply Voltage (1.8 V). 54 P31 Digital video

output

55 P30 Digital video

output

56 P29 Digital video

output

57 P28 Digital video

output

58 P27 Digital video

output

59 P26 Digital video

output

60 P25 Digital video

output

61 P24 Digital video

output

62 LLC Digital video

output

63 DVDD Power Digital Core Supply Voltage (1.8 V). 64 DVDD Power Digital Core Supply Voltage (1.8 V). 65 DVDDIO Power Digital I/O Supply Voltage (3.3 V). 66 P23 Digital video

output

67 P22 Digital video

output

68 P21 Digital video

output

69 P20 Digital video

output

70 P19 Digital video

output

71 P18 Digital video

output

72 P17 Digital video

output

73 P16 Digital video

output

74 P15 Digital video

output

75 P14 Digital video

output

76 P13 Digital video

output

77 DVDDIO Power Digital I/O Supply Voltage (3.3 V). 78 P12 Digital video

output

79 DVDD Power Digital Core Supply Voltage (1.8 V). 80 P11 Digital video

output

81 P10 Digital video

output

82 P9 Digital video

output

83 P8 Digital video

output

84 P7 Digital video

output

85 P6 Digital video

output

86 P5 Digital video

output

Video Pixel Output Port.

Pixel Output Clock for the Pixel Data (Range is 13.5 MHz to 170 MHz).

Video Pixel Output Port.

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Hardware User Guide UG-237

Pin No. Mnemonic Type Description

87 P4 Digital video

output

88 P3 Digital video

output

89 P2 Digital video

output

90 P1 Digital video

output

91 P0 Digital video

output

92 DVDDIO Power Digital I/O Supply Voltage (3.3 V). 93 DE Miscellaneous

digital

94 HS Digital video

output

95 VS/FIELD/ALSB Digital video

output

96 NC No connect No connect. 97 NC No connect No connect. 98 NC No connect No connect. 99 NC No connect No connect. 100 AP0 Miscellaneous Audio Output Pin. Pins AP0-AP5 can be configured to output SPDIF Digital Audio Output

101 AP1/I2S_TDM Miscellaneous Audio Output Pin. Pins AP0-AP5 can be configured to output SPDIF Digital Audio Output

102 AP2 Miscellaneous Audio Output Pin. Pins AP0-AP5 can be configured to output SPDIF Digital Audio Output

103 AP3 Miscellaneous Audio Output Pin. Pins AP0-AP5 can be configured to output SPDIF Digital Audio Output

104 AP4 Miscellaneous Audio Output Pin. Pins AP0-AP5 can be configured to output SPDIF Digital Audio Output

105 SCLK/INT2 Miscellaneous

digital

106 AP5 Miscellaneous Audio Output Pin. Pins AP0-AP5 can be configured to output SPDIF Digital Audio Output

107 MCLK/INT2 Miscellaneous A dual function pin that can be configured to output Audio Master Clock or an Interrupt2

108 DVDD Power Digital Core Supply Voltage (1.8 V). 109 SDA Miscellaneous

digital

110 SCL Miscellaneous

digital

111 INT1 Miscellaneous

digital

112

RESET

Miscellaneous digital

113

Miscellaneous

digital 114 PVDD Power PLL Supply Voltage (1.8 V). 115 XTALP Miscellaneous

analog 116 XTALN Miscellaneous

analog 117 DVDD Power Digital Core Supply Voltage (1.8 V).

118 CEC Digital

input/output 119 DDCB_SCL HDMI input HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant.

120 DDCB_SDA HDMI input HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input that is 5 V tolerant.

Video Pixel Output Port.

DE (data enable) is a signal that indicates active pixel data.

HS is a horizontal synchronization output signal.

VS is a vertical synchronization output signal. FIELD is a field synchronization output signal in all interlaced video modes. VS or FIELD can be configured for this pin. The ALSB allows selection of the I

(SPDIF), High Bit Rate (HBR), Direct Stream Digital (DSD) or I

(SPDIF), High Bit Rate (HBR), Direct Stream Digital (DSD) or Time-Division-Multiplexed I

(SPDIF), High Bit Rate (HBR), Direct Stream Digital (DSD) or I

C address.

S. A dual function pin that can be configured to output Audio Serial Clock or an Interrupt2 signal.

(SPDIF), High Bit Rate (HBR), Direct Stream Digital (DSD) or I

S. Additionally pin AP5 can be configured to provide LRCLK.

signal.

I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port.

I2C Port Serial Clock Input. SCL is the clock line for the control port.

Interrupt. This pin can be active low or active high. When status bits change, this pin is triggered. The events that trigger an interrupt are under user configuration. System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset the ADV7619 circuitry.

Chip Select. This pin has an internal pull-down. Pulling this line up causes I to ignore I

C transmission.

C state machine

Input Pin for 28.63636 MHz Crystal or an External 1.8 V, 28.63636 MHz Clock Oscillator Source to Clock the ADV7619. Crystal Input. Input pin for 28.63636 MHz crystal.

Consumer Electronic Control Channel.

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Pin No. Mnemonic Type Description

121 HPA_B Miscellaneous

digital

122 RXB_5V HDMI input 5 V Detect Pin for Port B in the HDMI Interface. 123 DDCA_SCL HDMI input HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant. 124 DDCA_SDA HDMI input HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input that is 5 V tolerant. 125 HPA_A/INT2 Miscellaneous

digital

126 RXA_5V HDMI input 5 V Detect Pin for Port A in the HDMI Interface. 127 NC No connect No connect. 128 NC No connect No connect.

Hot Plug Assert signal output for HDMI Port B.

A dual function pin that can be configured to output Hot Plug Assert signal (for HDMI Port A) or an Interrupt2 signal.

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GLOBAL CONTROL REGISTERS

The register control bits described in this section deal with the general control of the chip, and the CP and the HDMI receiver sections of the ADV7619.

ADV7619 REVISION IDENTIFICATION

RD_INFO[15:0], IO, Address 0xEA[7:0]; Address 0xEB[7:0] (Read Only)

Chip revision code.

Function RD_INFO[15:0] Description

0x20C0 ADV7619

POWER-DOWN CONTROLS

Primary Power-Down Controls

POWER_DOWN is the main power-down control. It is the main control for power-down Mode 0 and Mode 1. See the Power-Down Modes section for more details.

POWER_DOWN, IO, Address 0x0C[5]

A control to enable power-down mode. This is the main I

Function POWER_DOWN Description

0 Chip operational 1 (default) Enables chip power down

Secondary Power-Down Controls

The following controls allow various sections of the ADV7619 to be powered down.

It is possible to stop the clock to the CP to reduce power for a power-sensitive application. The CP_PWRDN bit enables this power-save mode. The HDMI block is not affected by this power-save mode. This allows the use of limited HDMI, STDI monitoring features while reducing the power consumption. For full processing of the HDMI input, the CP core needs to be powered up.

CP_PWRDN, IO, Address 0x0C[2]

A power-down control for the CP core.

Function CP_PWRDN Description

0 (default) Powers up clock to CP core. 1 Powers down clock to CP core. HDMI block not affected by this bit.

XTAL_PDN

XTAL_PDN allows the user to power down the XTAL clock in the following sections:

C power-down control.

• STDI blocks

• Free run synchronization generation block

C sequencer block, which is used for the configuration of the gain, clamp, and offset

• I

• CP and HDMI section

The XTAL clock is also provided to the HDCP engine, EDID, and the repeater controller within the HDMI receiver. The XTAL clock within these sections is not affected by XTAL_PDN.

XTAL_PDN, IO, Address 0x0B[0]

A power-down control for the XTAL in the digital blocks.

Function XTAL_PDN Description

0 (default) Powers up XTAL buffer to digital core 1 Powers down XTAL buffer to digital core

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CORE_PDN

CORE_PDN allows the user to power down clocks, with the exception of the XTAL clock, in the following sections:

• CP block

• Digital section of the HDMI block

CORE_PDN, IO, Address 0x0B[1]

A power-down control for the DPP, CP core, and digital sections of the HDMI core.

Function CORE_PDN Description

0 (default) Powers up CP and digital sections of HDMI block 1 Powers down CP and digital section of HDMI block

Power-Down Modes

The ADV7619 supports the following power-down modes:

• Power-Down Mode 0

• Power-Down Mode 1

Tabl e 5 shows the power-down and normal modes of ADV7619.

Table 5. Power-Down Modes

POWER_DOWN Bit CEC_POWER_UP Bit CEC EDID Power-Down Mode

0 0 Disabled Enabled Power-Down Mode 0 0 1 Enabled Enabled Power-Down Mode 1 1 0 Disabled Enabled1 Normal mode 1 1 Enabled Enabled1 Normal mode

Dependent on the values of EDID_X_ENABLE_CPU and EDID_X_ENABLE for the HDMI port (where X is A).

Power-Down Mode 0

In Power-Down Mode 0, selected sections and pads are kept active to provide EDID and +5 V antiglitch filter functionality.

In Power-Down Mode 0, the sections of the ADV7619 are disabled except for the following blocks:

• I2C slave section

• EDID/repeater controller

• EDID ring oscillator

The ring oscillator provides a clock to the EDID/repeater controller (refer to the E-EDID/Repeater Controller section) and the +5 V power supply antiglitch filter. The clock output from the ring oscillator runs at approximately 50 MHz.

The following pads only are enabled in Power-Down Mode 0:

• I

C pads

• SDA

• SCL

• +5 V pads

• RXA_5V

• RXB_5V

• HPA_A

• HPA_B

• DDC pads

• DDCA_SCL

• DDCA_SDA

• DDCB_SCL

• DDCB_SDA

• Reset pad

Power-Down Mode 0 is initiated through a software (I

RESET

C register) configuration.

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Entering Power-Down Mode 0 via Software

The ADV7619 can be put into Power-Down Mode 0 by setting POWER_DOWN to 1 (default value) and CEC_POWER_UP to 0. This method allows an external processor to put the system in which the ADV7619 is integrated into standby mode. In this case, the CP and HDMI cores of the ADV7619 are kept powered up from the main power (for example, ac power) and set in or out of power-down Mode 0 through the POWER_DOWN bit.

Power-Down Mode 1

Power-Down Mode 1 is enabled when the following conditions are met:

• POWER_DOWN bit is set to 1

• CEC section is enabled by setting CEC_POWER_UP to 1

Power-Down Mode 1 provides the same functionality as Power-Down Mode 0, with the addition of the following sections:

• XTAL clock

• CEC section

• Interrupt controller section

The following pads are enabled in Power-Down Mode 1:

• Same pads as enabled in Power-Down Mode 0

• CEC pad

• INT1 and INT2 interrupt pads

The internal EDID is also accessible through the DDC bus for Port A and Port B in Power-Down Mode 0 and Power-Down Mode 1.

GLOBAL PIN CONTROL

RESET

The ADV7619 can be reset by a low reset pulse on the reset pin with a minimum width of 5 ms. It is recommended to wait 5 ms after the low pulse before an I

Reset Controls

MAIN_RESET, IO, Address 0xFF[7] (Self-Clearing)

Main reset where I

Function MAIN_RESET Description

0 (default) Normal operation 1 Applies main I2C reset

Tristate Output Drivers

PA D S _ P DN , IO, Address 0x0C[0]

A power-down control for pads of the digital outputs. When enabled, the pads are tristated and the input path is disabled. This control applies to the DE, HS, VS/FIELD/ALSB, INT1, and LLC pads and to the P0 to P47 pixel pads.

Function PADS_PDN Description

0 (default) Powers up pads of digital output pins 1 Powers down pads of digital output pins

DDC_PWRDN[7:0], Addr 68 (HDMI), Address 0x73[7:0]

A power-down control for DDC pads.

Function DDC_PWRDN[7:0] Description

00000000 (default) Powers up DDC pads

xxxxxxx1 xxxxxx1x

C write is performed to the ADV7619.

C registers are reset to their default values.

Powers down DDC pads on Port A Powers down DDC pads on Port B

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TRI_PIX

This bit allows the user to tristate the output driver of pixel outputs. Upon setting TRI_PIX, the pixel output P[35:0] is tristated.

TRI_PIX, IO, Address 0x15[1]

A control to tristate the pixel data on the pixel pins, P[47:0].

Function TRI_PIX Description

0 Pixel bus active 1 (default) Tristates pixel bus

Tristate LLC Driver

TRI_LLC, IO, Address 0x15[2]

A control to tristate the output pixel clock on the LLC pin.

Function TRI_LLC Description

0 LLC pin active 1 (default) Tristates LLC pin

Tristate Synchronization Output Drivers

The following output synchronization signals are tristated when TRI_SYNCS is set:

• VS/FIELD/ALSB

• HS

• DE

The drive strength controls for these signals are provided via the DR_STR_SYNC bits. The ADV7619 does not support tristating via a dedicated pin.

TRI_SYNCS, IO, Address 0x15[3]

Synchronization output pins tristate control. The synchronization pins under this control are HS, VS/FIELD/ALSB, and DE.

Function TRI_SYNCS Description

0 Sync output pins active 1 (default) Tristates sync output pins

Tristate Audio Output Drivers

TRI_AUDIO, IO Map, Address 0x15, [4]

TRI_AUDIO allows the user to tristate the drivers of the following audio output signals:

• AP0

• AP1/I2S_TDM

• AP2

• AP3

• AP4

• AP5

• SCLK/INT2

• MCLK/INT2

The drive strength for the output pins can be controlled by the DR_STR[1:0] bits. The ADV7619 does not support tristating via a dedicated pin.

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TRI_AUDIO, IO, Address 0x15[4]

A control to tristate the audio output interface pins (AP0, AP1/I2S_TDM, AP2, …, AP5).

Function TRI_AUDIO Description

0 Audio output pins active 1 (default) Tristates audio output pins

Drive Strength Selection

DR_STR

It may be desirable to strengthen or weaken the drive strength of the output drivers for Electromagnetic Compatibility (EMC) and crosstalk reasons. This section describes the controls to adjust the output drivers used by the CP and HDMI modes.

The drive strenth DR_STR_SYNC[1:0] bits allow the user to select the strength of the following synchronization signals:

• DE

• HS

• VS/FIELD

The DR_STR[1:0] drive strength bits affect output drivers for the following output pins:

• P[47:0]

• AP0, AP1/I2S_TDM, AP2-AP5

• SCLK

• SDA

• SCL

The drive strength DR_STR_CLK[1:0] bits affect output driver for LLC line.

DR_STR[1:0], IO, Address 0x14[5:4]

A control to set the drive strength of the data output drivers.

Function DR_STR[1:0] Description

00 Reserved 01 Medium low (2×) 10 (default) Medium high (3×) 11 High (4×)

DR_STR_CLK[1:0], IO, Address 0x14[3:2]

A control to set the drive strength control for the output pixel clock out signal on the LLC pin.

Function DR_STR_CLK[1:0] Description

00 Reserved 01 Medium low (2×) for LLC up to 60 MHz 10 (default) Medium high (3×) for LLC from 44 MHz to 105 MHz 11 High (4×) for LLC greater than 100 MHz

DR_STR_SYNC[1:0], IO, Address 0x14[1:0]

A control to set the drive strength of the synchronization pins, HS, VS/FIELD/ALSB, and DE.

Function DR_STR_SYNC[1:0] Description

00 Reserved 01 Medium low (2×) 10 (default) Medium high (3×) 11 High (4×)

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Output Synchronization Selection

VS_OUT_SEL, IO, Address 0x06[7]

A control to select the VSync or FIELD signal to be output on the VS/FIELD/ALSB pin.

Function VS_OUT_SEL Description

0 Selects FIELD output on VS/FIELD/ALSB pin 1 (default) Selects VSync output on VS/FIELD/ALSB pin

F_OUT_SEL, IO, Address 0x05[4]

A control to select the DE or FIELD signal to be output on the DE pin.

Function F_OUT_SEL Description

0 (default) Selects DE output on DE pin 1 Selects FIELD output on DE pin

Output Synchronization Signals Polarity

INV_LLC_POL, IO Map, Address 0x06, [0]

The polarity of the pixel clock provided by the ADV7619 via the LLC pin can be inverted using the INV_LLC_POL bit. Note that this inversion affects only the LLC output pin. The other output pins are not affected by INV_LLC_POL.

Changing the polarity of the LLC clock output may be necessary in order to meet the setup and hold time expectations of the downstream devices processing the output data of the ADV7619. It is expected that these parameters must be matched regardless of the type of video data that is transmitted. Therefore, INV_LLC_POL is designed to be mode independent.

INV_LLC_POL, IO, Address 0x06[0]

A control to select the polarity of the LLC.

Function INV_LLC_POL Description

0 (default) Does not invert LLC 1 Inverts LLC

The output synchronization signals HS, VS/FIELD/ALSB, and DE can be inverted using the following control bits:

• INV_HS_POL

• INV_VS_POL

• INV_F_POL

INV_HS_POL, IO, Address 0x06[1]

A control to select the polarity of the HS signal.

Function INV_HS_POL Description

0 (default) Negative polarity HS 1 Positive polarity HS

INV_VS_POL, IO, Address 0x06[2]

A control to select the polarity of the VS/FIELD/ALSB signal.

Function INV_VS_POL Description

0 (default) Negative polarity VS/FIELD/ALSB 1 Positive polarity VS/FIELD/ALSB

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INV_F_POL, IO, Address 0x06[3]

A control to select the polarity of the DE signal.

Function INV_F_POL Description

0 (default) Negative FIELD/DE polarity 1 Positive FIELD/DE polarity

Digital Synthesizer Controls

The ADV7619 features two digital encoder synthesizers that generate the following clocks:

• Video DPLL: this clock synthesizer generates the pixel clock. It undoes the effect of deep color and pixel repetition that are inherent

to HDMI streams. The output of the LLC pin is either this pixel clock or a divided down version, depending on the datapath configuration. It takes less than one video frame for this synthesizer to lock.

• Audio DPLL: this clock synthesizer generates the audio clock. As per HDMI specification, the incomming HDMI clock is divided

down by CTS and then multiplied up by N. This audio clock is used as the main clock in the audio stream section. The output of MCLK represents this clock. It takes less than 5 ms after a valid ACR packet for this synthesizer to lock.

Crystal Frequency Selection

The ADV7619 supports 27.0, 28.63636, 24.576 and 24.0 MHz frequency crystals. Following control allows selecting crystal frequency.

XTAL_FREQ_SEL[1:0], IO, Address 0x04[2:1]

A control to set the XTAL frequency used.

Function XTAL_FREQ_SEL[1:0] Description

00 27 MHz 01 (default) 28.63636 MHz 10 24.576 MHz 11 24.0 MHz

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PRIMARY MODE AND VIDEO STANDARD

Setting the primary mode and choosing a video standard are the most fundamental settings when configuring the ADV7619. There are two primary modes for the ADV7619: HDMI-component and HDMI-graphic modes. The appropriate mode should be set with PRIM_MODE[3:0].

In HDMI modes, the ADV7619 can receive and decode HDMI or DVI data throughout the DVI/HDMI receiver front end. Video data from the HDMI receiver is routed to the CP block while audio data is available on the audio interface. One of these modes is enabled by selecting either the HDMI-component or the HDMI-graphics primary mode.

Note: The HDMI receiver decodes and processes any applied HDMI stream irrespective of the video resolution. However, many primary mode and video standard combinations can be used to define how the decoded video data routed to the DPP and CP blocks is processed. This allows for free run features and data decimation modes that some systems may require.

If free run and decimation are not required, it is recommended to set the following configuration for HDMI mode:

• PRIM_MODE[3:0]: 0x06

• VID_STD[5:0]: 0x02

PRIMARY MODE AND VIDEO STANDARD CONTROLS

PRIM_MODE[3:0], IO, Address 0x01[3:0]

A control to select the primary mode of operation of the decoder. Setting the appropriate HDMI mode is important for free run mode to work properly. This control is used with VID_STD[5:0].

Function PRIM_MODE[3:0] Description

0000 Reserved 0001 Reserved 0010 Reserved 0011 Reserved 0100 Reserved 0101 HDMI component 0110 (default) HDMI graphics 0111 to 1111 Reserved

VID_STD[5:0], IO, Address 0x00[5:0]

Sets the input video standard mode. Configuration is dependent on PRIM_MODE[3:0]. Setting the appropriate mode is important for free run mode to work properly.

Function VID_STD[5:0] Description

000010 Default value

PRIM_MODE[3:0] should be used with VID_STD[5:0] to select the required video mode. These controls are set according to Tabl e 6.

Table 6. Primary Mode and Video Standard Selection

PRIM_MODE[3:0] VID_STD[5:0] Code Description Processor Code Input Video Output Resolution Comment

0000 Reserved xxxxxx Reserved Reserved 0001 Reserved xxxxxx Reserved Reserved 0010 Reserved xxxxxx Reserved Reserved 0100 Reserved xxxxxx Reserved Reserved 0011 Reserved xxxxxx Reserved Reserved

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PRIM_MODE[3:0] VID_STD[5:0] Code Description Processor Code Input Video Output Resolution Comment

0101 HDMI-COMP

(Component video)

0110 HDMI-GR

(Graphics)

0111 Reserved xxxxxx Reserved Reserved 1000 Reserved xxxxxx Reserved Reserved 1001 Reserved xxxxxx Reserved Reserved

CP 000000 SD 1×1 525i 720 × 480 CP 000001 SD 1×1 625i 720 × 576 CP 000010 SD 2×1 525i 720 × 480 CP 000011 SD 2×1 625i 720 × 576 000100 Reserved Reserved 000101 Reserved Reserved 000110 Reserved Reserved 000111 Reserved Reserved 001000 Reserved Reserved 001001 Reserved Reserved CP 001010 PR 1×1 525p 720 × 480 CP 001011 PR 1×1 625p 720 × 576 CP 001100 PR 2×1 525p 720 × 480 CP 001101 PR 2×1 625p 720 × 576 001110 Reserved Reserved 001111 Reserved Reserved 010000 Reserved Reserved 010001 Reserved Reserved 010010 Reserved Reserved CP 010011 HD 1×1 1280 × 720 CP 010100 HD 1×1 1920 × 1080 CP 010101 HD 1×1 1920 × 1035 CP 010110 HD 1×1 1920 × 1080 CP 010111 HD 1×1 1920 × 1152 011000 Reserved Reserved CP 011001 HD 2×1 720p 1280 × 720 CP 011010 HD 2×1 1125 1920 × 1080 CP 011011 HD 2×1 1125 1920 × 1035 CP 011100 HD 2×1 1250 1920 × 1080 CP 011101 HD 2×1 1250 1920 × 1152 CP 011110 HD 1×1 1920 × 1080 CP 011111 HD 1×1 1920 × 1080 CP 000000 SVGA 800 × 600 @ 56 CP 000001 SVGA 800 × 600 @ 60 CP 000010 SVGA 800 × 600 @ 72 CP 000011 SVGA 800 × 600 @ 75 CP 000100 SVGA 800 × 600 @ 85 CP 000101 SXGA 1280 × 1024 @ 60 CP 000110 SXGA 1280 × 1024 @ 75 000111 Reserved Reserved CP 001000 VGA 640 × 480 @ 60 CP 001001 VGA 640 × 480 @ 72 CP 001010 VGA 640 × 480 @ 75 CP 001011 VGA 640 × 480 @ 85 CP 001100 XGA 1024 × 768 @ 60 CP 001101 XGA 1024 × 768 @ 70 CP 001110 XGA 1024 × 768 @ 75 CP 001111 XGA 1024 × 768 @ 85 01xxxx Reserved

HDMI receiver support

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PRIM_MODE[3:0] VID_STD[5:0] Code Description Processor Code Input Video Output Resolution Comment

1010 Reserved xxxxxx Reserved Reserved 1011 Reserved xxxxxx Reserved Reserved 1100 Reserved xxxxxx Reserved Reserved 1101 Reserved xxxxxx Reserved Reserved 1110 Reserved xxxxxx Reserved Reserved 1111 Reserved xxxxxx Reserved Reserved

V_FREQ

This control is set to allow free run to work correctly (refer to Tabl e 7).

V_FREQ[2:0], IO, Address 0x01[6:4]

A control to set vertical frequency.

Function V_FREQ[2:0] Description

000 (default) 60 Hz 001 50 Hz 010 30 Hz 011 25 Hz 100 24 Hz 101 Reserved 110 Reserved 111 Reserved

HDMI DECIMATION MODES

Some of the modes defined by VID_STD have an inherent 2×1 decimation. For these modes, the main clock generator and the decimation filters in the DPP block are configured automatically. This ensures the correct data rate at the input to the CP block. Refer to the Data Preprocessor and Color Space Conversion and Color Controls section for more information on the automatic configuration of the DPP block.

The ADV7619 correctly decodes and processes any incoming HDMI stream with the required decimation, irrespective of its video resolution:

• In 1×1 mode (that is, without decimation), as long the PRIM_MODE and VID_STD registers are programmed for any HDMI mode

without decimation. For example:

• Set PRIM_MODE to 0x5 and VID_STD to 0x00

• Set PRIM_MODE to 0x5 and VID_STD to 0x13

• Set PRIM_MODE to 0x6 and VID_STD to 0x02

• In 2×1 decimation mode, as long the PRIM_MODE and VID_STD registers are programmed for any HDMI mode with 2×1

decimation. For example:

• Set PRIM_MODE to 0x5 and VID_STD to 0x0C

• Set PRIM_MODE to 0x5 and VID_STD to 0x19

Note: Decimating the video data from an HDMI stream is optional and should be performed only if it is required by the downstream devices connected to the ADV7619.

PRIMARY MODE AND VIDEO STANDARD CONFIGURATION FOR HDMI FREE RUN

If free run is enabled in HDMI mode, PRIM_MODE[3:0] and VID_STD[5:0] specify the input resolution expected by the ADV7619 (for free run Mode 1) and/or the output resolution to which the ADV7619 free runs (for free run Mode 0 and Mode 1). Refer to the Free Run Mode section for additional details on the free run feature for HDMI inputs and to HDMI_FRUN_MODE.

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RECOMMENDED SETTINGS FOR HDMI INPUTS

This section provides the recommended settings for an HDMI input encapsulating a video resolution corresponding to a selection Video ID Code described in the 861 specification.

Table 7 provides the recommended settings for the following registers:

 PRIM_MODE  VID_STD  V_FREQ (V_FREQ should be set to 0x0 if not specified in Table 7.)  INV_HS_POL = 1 (INV_HS_POL should be set to 1 if not specified in Table 7.)  INV_VS_POL = 1 (INV_VS_POL should be set to 1 if not specified in Table 7.)

Table 7. Recommended Settings for HDMI Inputs

Recommended Settings if

Recommended Settings if Video ID Codes (861 Specification)

2, 3 720 × 480p @ 60 Hz 0 PRIM_MODE = 0x5

4 1280 × 720p @ 60 Hz 0 PRIM_MODE = 0x5

5 1920 × 1080i @ 60 Hz 0 PRIM_MODE = 0x5

6, 7 720 (1440) × 480i @ 60 Hz 1 PRIM_MODE = 0x5

10, 11 2880 × 480i @ 60 Hz 3 PRIM_MODE = 0x5

14, 15 1440 × 480p @ 60 Hz 1 PRIM_MODE=0x5

16 1920 × 1080p @ 60 Hz 0 PRIM_MODE = 0x5

17, 18 720 × 576p @ 60 Hz 0 PRIM_MODE = 0x5

19 1280 × 720p @ 50 Hz 0 PRIM_MODE = 0x5

20 1920 × 1080i @ 50 Hz 0 PRIM_MODE = 0x5

21, 22 720 (1440) ×576i @ 60 Hz 1 PRIM_MODE = 0x5

25, 26 2880 × 480i @ 60 Hz 3 PRIM_MODE=0x5

29, 30 144 0× 576p @ 60 Hz 1 PRIM_MODE = 0x5

31 1920 × 1080p @ 50 Hz 0 PRIM_MODE = 0x5

32 1920 × 1080p @ 24 Hz 0 PRIM_MODE = 0x5

33 1920 × 1080p @ 25 Hz 0 PRIM_MODE = 0x5

35, 36 2880 × 480p @ 60 Hz 3 PRIM_MODE = 0x5

Formats

Pixel Repetition

Free Run Used and

DIS_AUTOPRAM_BUFFER = 0

VID_STD = 0xA

VID_STD = 0x13

VID_STD = 0x14

VID_STD = 0x0

VID_STD = 0xA

VID_STD = 0x1E

VID_STD = 0xB

VID_STD = 0xA3

V_FREQ = 0x1

VID_STD = 0x14

V_FREQ = 0x1

VID_STD = 0x1

VID_STD = 0xA

VID_STD = 0x1E

V_FREQ = 0x1

VID_STD = 0x1E

V_FREQ = 0x4

VID_STD = 0x1E

V_FREQ = 0x3

VID_STD = 0xA

Free Run Not Used or Free Run Used and DIS_AUTO_PARAM_BUFFER = 1

PRIM_MODE = 0x6 VID_STD = 0x2 PRIM_MODE = 0x6 VID_STD = 0x2 PRIM_MODE = 0x6 VID_STD = 0x2 PRIM_MODE = 0x6 VID_STD = 0x2 PRIM_MODE = 0x6 VID_STD = 0x2 PRIM_MODE = 0x6 VID_STD = 0x2 PRIM_MODE = 0x6 VID_STD = 0x2 PRIM_MODE = 0x6 VID_STD = 0x2 PRIM_MODE = 0x6 VID_STD = 0x2

PRIM_MODE = 0x6 VID_STD = 0x2

PRIM_MODE = 0x6 VID_STD = 0x2 PRIM_MODE = 0x6 VID_STD = 0x2 PRIM_MODE = 0x6 VID_STD = 0x2 PRIM_MODE = 0x6 VID_STD = 0x2

PRIM_MODE = 0x6 VID_STD = 0x2

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Recommended Settings if

Recommended Settings if Video ID Codes (861 Specification) Formats

37, 38 2880 × 576p @ 60 Hz 3 PRIM_MODE = 0x5

N/A SVGA 800 × 600p @ 56 Hz 0 PRIM_MODE = 0x06

N/A SVGA 800 × 600p @ 60 Hz 0 PRIM_MODE = 0x06

N/A SVGA 800 × 600p @ 72 Hz 0 PRIM_MODE = 0x06

N/A SVGA 800 × 600p @ 75 Hz 0 PRIM_MODE = 0x06

N/A SVGA 800 × 600p @ 85 Hz 0 PRIM_MODE = 0x06

N/A SXGA 1280 × 1024p @ 60 Hz 0 PRIM_MODE = 0x06

N/A SXGA 1280 × 1024p @ 75 Hz 0 PRIM_MODE = 0x06

N/A VGA 640 × 480p @ 60 Hz 0 PRIM_MODE = 0x06

N/A VGA 640 × 480p @ 72 Hz 0 PRIM_MODE = 0x06

N/A VGA 640 × 480p @ 75 Hz 0 PRIM_MODE = 0x06

N/A VGA 640 × 480p @ 85 Hz 0 PRIM_MODE = 0x06

N/A VGA 1024 × 768p @ 60 Hz 0 PRIM_MODE = 0x06

N/A VGA 1024 × 768p @ 70 Hz 0 PRIM_MODE = 0x06

N/A VGA 1024 × 768p @ 75 Hz 0 PRIM_MODE = 0x06

N/A VGA 1024 × 768p @ 85 Hz 0 PRIM_MODE = 0x06

Pixel Repetition

Free Run Used and

DIS_AUTOPRAM_BUFFER = 0

VID_STD = 0xA

VID_STD = 0x0

Free Run Not Used or Free Run Used and DIS_AUTO_PARAM_BUFFER = 1

PRIM_MODE = 0x6 VID_STD = 0x2 PRIM_MODE = 0x06 VID_STD = 0x0 PRIM_MODE = 0x06 VID_STD = 0x1 PRIM_MODE = 0x06 VID_STD = 0x2 PRIM_MODE = 0x06 VID_STD = 0x3 PRIM_MODE = 0x06 VID_STD = 0x04 PRIM_MODE = 0x06 VID_STD = 0x05 PRIM_MODE = 0x06 VID_STD = 0x06 PRIM_MODE = 0x06 VID_STD = 0x08 PRIM_MODE = 0x06 VID_STD = 0x09 PRIM_MODE = 0x06 VID_STD = 0x0A PRIM_MODE = 0x06 VID_STD = 0x0B PRIM_MODE = 0x06 VID_STD = 0x0C PRIM_MODE = 0x06 VID_STD = 0x0D PRIM_MODE = 0x06 VID_STD = 0x0E PRIM_MODE = 0x06 VID_STD = 0x0F

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Hardware User Guide UG-237

PIXEL PORT CONFIGURATION

The ADV7619 has a very flexible pixel port, which can be configured in a variety of formats to accommodate downstream ICs. The ADV7619 can provide output modes up to 36 bits for video with pixel clock frequency below 170 MHz, and 48 bits for video with pixel rates above 170 MHz.

For an HDMI stream with bit pixel rates above 170 MHz, ADV7619 outputs data using two video buses running at half the video pixel clock frequency. Video data is interleaved. On a single clock edge, the first bus outputs information about odd pixels and the second video bus outputs information about even pixels. Video output modes for pixel rates above 170 MHz are shown in Tab le 81 .

This section details the controls required to configure the ADV7619 pixel port. Appendix C contains tables describing some of the pixel port configurations.

PIXEL PORT OUTPUT MODES

OP_FORMAT_SEL[7:0], IO, Address 0x03[7:0]

A control to select the data format and pixel bus configuration. Refer to the Appendix for full information on pixel port modes and configuration settings.

Function OP_FORMAT_SEL[7:0] Description

0x00 1 8-bit SDR ITU-656 mode 0x011 10-bit SDR ITU-656 mode 0x021 12-bit SDR ITU-656 Mode 0 0x061 12-bit SDR ITU-656 Mode 1 0x0A 12-bit SDR ITU Mode 2 0x20 8-bit 4:2:2 DDR Mode 0x21 10-bit 4:2:2 DDR Mode 0x22 12-bit 4:2:2 DDR Mode 0 0x23 12-bit 4:2:2 DDR Mode 1 0x24 12-bit 4:2:2 DDR Mode 2 0x40 24-bit 4:4:4 SDR Mode 0x41 30-bit 4:4:4 SDR Mode 0x42 36-bit 4:4:4 SDR Mode 0 0x46 36-bit SDR 4:4:4 Mode 1 0x4C 24-bit SDR 4:4:4 Mode 3 0x50 24-bit SDR 4:4:4 Mode 4 0x51 30-bit SDR 4:4:4 Mode 4 0x52 36-bit SDR 4:4:4 Mode 4 0x542 2 × 24-bit SDR 4:4:4 interleaved Mode 0 0x60 24-bit 4:4:4 DDR mode 0x61 30-bit 4:4:4 DDR mode 0x62 36-bit 4:4:4 DDR mode 0x80 16-bit ITU-656 SDR mode 0x81 20-bit ITU-656 SDR mode 0x82 24-bit ITU-656 SDR Mode 0 0x86 24-bit ITU-656 SDR Mode 1 0x8A 24-bit ITU-656 SDR Mode 2 0x8D 20-bit SDR 4:2:2 Mode 3 0x90 16-bit SDR 4:2:2 Mode 4 0x942 2 × 16-bit SDR 4:2:2 interleaved Mode 0 0x952 2 × 20-bit SDR 4:2:2 interleaved Mode 0 0x962 2 × 24-bit SDR 4:2:2 interleaved Mode 0

Refer to DLL Settings for 656, 8-/10-/12-Bit Modes in chapter DLL on LLC Clock Path.

The 0x54, 0x94, 0x95, 0x96 modes registers should be set as follows:

DPLL Map, Register 0xC3 to Register 0x80. DPLL Map, Register 0xCF to Register0x03. IO Map, Register 0xDD to Register 0xA0. IO Map, Register 0xBF[0] = 0 (CP_COMPLETE_BYPASS_IN_HDMI_MODES disabled).

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UG-237 Hardware User Guide

Bus Rotation and Reordering Controls

Bus reordering controls are available for ADV7619. OP_CH_SEL[2:0] allows the three output buses to be rearranged, thus providing six different output possibilities.

OP_CH_SEL[2:0], IO, Address 0x04[7:5]

A control to select the configuration of the pixel data bus on the pixel pins. Refer to the pixel port configuration for full information on pixel port modes and configuration settings.

Function OP_CH_SEL[2:0] Description

000 P[35:24] Y/G, P[23:12] U/CrCb/B, P[11:0] V/R 001 P[35:24] Y/G, P[23:12] V/R, P[11:0] U/CrCb/B 010 P[35:24] U/CrCb/B, P[23:12] Y/G, P[11:0] V/R 011 (default) P[35:24] V/R, P[23:12] Y/G, P[11:0] U/CrCb/B 100 P[35:24] U/CrCb/B, P[23:12] V/R, P[11:0]Y/G 101 P[35:24] V/R, P[23:12] U/CrCb/B, P[11:0] Y/G 110 Reserved 111 Reserved

PIXBUS_MSB_TO_LSB_REORDER, IO, Address 0x30[4]

A control to swap the MSB to LSB orientation on the pixel bus.

Function PIXBUS_MSB_TO_LSB_REORDER Description

0 (default) Output bus goes from MSB to LSB 1 Output bus goes from LSB to MSB

Pixel Data and Synchronization Signals Control

The polarity of the LLC and synchronization signals can be inverted, and the LLC, the synchronization signals, and the pixel data output can be tristated. Refer to the information on the following controls:

• INV_F_POL

• INV_VS_POL

• INV_HS_POL

• TRI_PIX

• TRI_LLC

• TRI_SYNCS

OP_SWAP_CB_CR, IO, Address 0x05[0]

A controls the swapping of Cr and Cb data on the pixel buses.

Function OP_SWAP_CB_CR Description

0 (default) Outputs Cr and Cb as per OP_FORMAT_SEL 1 Inverts the order of Cb and Cr in the interleaved data stream

OP_SWAP_CB_CR swaps the order in which Cb and Cr are interleaved in the output data stream. It caters for cases in which the data on Channels B and C are swapped. It is effective only if OP_FORMAT_SEL[7:0] is set to a 4:2:2 compatible output mode.

Note: It has no effect for 36-bit SDR modes and DDR modes.

DDR OUTPUT INTERFACE

The ADV7619 allows data to be output in a DDR mode only for modes below 2.25GBps. To enable DDR mode -

OP_FORMAT_SEL[7:0] should be set to one of DDR modes. Refer also to Pixel Output Formats section.

Important: The maximum frequency of the DDR clock supported by the ADV7844 is 50 MHz. The DDR clock is output through the

LLC pin.

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Hardware User Guide UG-237

LLC CONTROLS

The ADV7619 has a number of adjustment features available for the line locked clock (LLC) output. The polarity of the LLC can be inverted and the LLC of the output driver can be tristated. Controls also exist to skew the LLC versus the output data to achieve suitable setup and hold times for any back end device. The LLC controls are as follows:

• INV_LLC_POL

• TRI_LLC

• LLC_DLL_EN

• LLC_DLL_MUX

• LLC_DLL_PHASE[4:0]

DLL ON LLC CLOCK PATH

A delay locked loop (DLL) block is implemented on the LLC clock path. This DLL allows the changing of the phase of the output pixel clock on the LLC pin.

Adjusting DLL Phase in All Modes

LLC_DLL_EN, IO, Address 0x19[7]

A control to enable the DLL for the output pixel clock.

Function LLC_DLL_EN Description

1 Enables LLC DLL 0 (default) Disables LLC DLL

LLC_DLL_MUX, IO, Address 0x33[6]

A control to apply the pixel clock DLL to the pixel clock output on the LLC pin.

Function LLC_DLL_MUX Description

0 (default) Bypasses the DLL 1 Muxes the DLL output on LLC output

LLC_DLL_PHASE[4:0], IO, Address 0x19[4:0]

A control to adjust LLC DLL phase in increments of 1/32 of a clock period.

Function LLC_DLL_PHASE[4:0] Description

00000 (default) Default xxxxx Sets one of 32 phases of DLL to vary LLC CLK

LLC_DLL_DOUBLE, IO, 0x19[6]: Doubles LLC frequency.

Function LLC_DLL_DOUBLE[6] Description

0 (default) Normal LLC Frequency 1 Double LLC Frequency

DLL Settings for 656, 8-/10-/12-Bit Modes

Following settings must be done in order to enable 8-/10-/12-bit 656 output:

IO Map 0x19[7] = 1 ; Enable LLC DLL

IO Map 0x33[6] = 1 ; Muxes the DLL output on LLC output

IO Map 0x19[6] = 1 ; Double the clock

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UG-237 Hardware User Guide

HDMI RECEIVER

HPA_A/INT2

HPA_B

RXA_5V RXB_5V

CEC

DDCA_SDA/DDCA_SC L DDCB_SDA/DDCB_SC L

5V DETECT

AND HPA

CONTROLL ER

CEC

CONTROLL ER

EDID/

REPEATER

CONTROLL ER

DEEP COLOR CONVERSION

4:2:2 TO 4:4:4 CONVERSION

DATA

TO INTERRUPT CONTROLL ER

VIDEO OUTPUT FORMATTER (3Gbs VIDEO PATH)

TO DATA PREPROCESSO R (2.25Gbs V IDEO PATH)

RXA_C±

RXB_C±

RXA_0± RXA_1± RXA_2±

RXB_0± RXB_1± RXB_2±

PLL

EQUALIZER

HDCP

EEPROM

HDCP

BLOCK

SAMPLEREQUALIZER

SAMPLER

AP0

AUDIO OUTPUT FORMATTER

AP1/I2S_TDM AP2 AP3 AP4 AP5

SCLK/INT2

MCLK/INT2

09581-003

FILTER

PACKET/

INFOFRAME

+ MUX

FAST SWITCHING BLOCK

HDMI DECODE + PO RT MEASUREMENT

MEMORY

PACKET

PROCESSOR

AUDIO

PROCESSOR

Figure 4. Functional Block Diagram of HDMI Core

ADV7619 feature HDMI 1.4a compliant HDMI Receiver capable to support HDMI stream with bit rate up to 3 Gbs. HDMI stream with bit rate below 2.25 Gbs is receiver and can be processes by CP core, where HDMI stream with bit rates above 2.25 Gbs and below 3 Gbs is directly output to OUTPUT DATA FORMATTER. These two video paths: 2.25 Gbs and 3 Gbs are shown in Figure 4.

+5 V CABLE DETECT

The HDMI receiver in the ADV7619 can monitor the level on the +5 V power signal pin of each connected HDMI port. The results of this detection can be read back from the following I HDMI mode.

CABLE_DET_A_RAW, IO, Address 0x6F[0] (Read Only)

Raw status of Port A +5 V cable detection signal.

Function CABLE_DET_A_RAW Description

0 (default) No cable detected on Port A 1 Cable detected on Port A (high level on RXA_5V)

CABLE_DET_B_RAW, IO, Address 0x6A[7] (Read Only)

Raw status of Port B +5 V cable detection signal.

Function CABLE_DET_B_RAW Description

0 (default) No cable detected on Port B 1 Cable detected on Port B (high level on RXB_5V)

The ADV7619 provides a digital glitch filter on the +5 V power signals from the HDMI port. The output of this filter is used to reset the HDMI block (refer to the HDMI Section Reset Strategy section).

The +5 V power signal must be constantly high for the duration of the timer (controlled by FILT_5V_DET_TIMER[6:0]), otherwise the output of the filter is low. The output of the filter returns low as soon as any change in the +5 V power signal is detected.

FILT_5V_DET_DIS, Addr 68 (HDMI), Address 0x56[7]

This control is used to disable the digital glitch filter on the HDMI 5 V detect signals. The filtered signals are used as interrupt flags and used to reset the HDMI section. The filter works from an internal ring oscillator clock and, therefore, is available in power-down mode. The clock frequency of the ring oscillator is 42 MHz ± 10%.

C registers. These readbacks are valid even when the part is not configured for

Rev. A | Page 30 of 204

+ 174 hidden pages

ANALOG DEVICES UG-237 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

SCOPE

DISCLAIMER

TABLE OF CONTENTS

REVISION HISTORY

USING THE ADV7619 HARDWARE USER GUIDE

NUMBER NOTATIONS

REGISTER ACCESS CONVENTIONS

ACRONYMS AND ABBREVIATIONS

FIELD FUNCTION DESCRIPTIONS

Example Field Function Description

REFERENCES

INTRODUCTION TO THE ADV7619

HDMI RECEIVER

COMPONENT PROCESSOR

MAIN FEATURES OF ADV7619

HDMI Receiver

Component Video Processing

Video Output Formats

Additional Features

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GLOBAL CONTROL REGISTERS

ADV7619 REVISION IDENTIFICATION

POWER-DOWN CONTROLS

Primary Power-Down Controls

Secondary Power-Down Controls

XTAL_PDN

CORE_PDN

Power-Down Modes

Power-Down Mode 0

Power-Down Mode 1

GLOBAL PIN CONTROL

Reset Controls

Tristate Output Drivers

TRI_PIX

Tristate LLC Driver

Tristate Synchronization Output Drivers

Tristate Audio Output Drivers

Drive Strength Selection

DR_STR

Output Synchronization Selection

Output Synchronization Signals Polarity

Digital Synthesizer Controls

Crystal Frequency Selection

PRIMARY MODE AND VIDEO STANDARD

PRIMARY MODE AND VIDEO STANDARD CONTROLS

V_FREQ

HDMI DECIMATION MODES

PRIMARY MODE AND VIDEO STANDARD CONFIGURATION FOR HDMI FREE RUN

RECOMMENDED SETTINGS FOR HDMI INPUTS

PIXEL PORT CONFIGURATION

PIXEL PORT OUTPUT MODES

Bus Rotation and Reordering Controls

Pixel Data and Synchronization Signals Control

DDR OUTPUT INTERFACE

LLC CONTROLS

DLL ON LLC CLOCK PATH

Adjusting DLL Phase in All Modes

DLL Settings for 656, 8-/10-/12-Bit Modes

HDMI RECEIVER

+5 V CABLE DETECT