ANALOG DEVICES SSM2517 Service Manual
PDM Digital Input, Mono
V
Data Sheet
FEATURES
Filterless digital Class-D amplifier
Pulse density modulation (PDM) digital input interface
2.4 W into 4 Ω load and 1.38 W into 8 Ω load at 5.0 V supply
with <1% total harmonic distortion plus noise (THD + N)
Available in 9-ball, 1.5 mm × 1.5 mm, 0.5 mm pitch WLCSP
92% efficiency into 8 Ω at full scale
Output noise: 43 μV rms at 3.6 V, A-weighted
THD + N: 0.035% at 1 kHz, 100 mW output power
PSRR: 85 dB at 217 Hz, input referred with dither input
Quiescent power consumption: 10.4 mW
(VDD = 1.8 V, PVDD = 3.6 V, 8 Ω + 33 μH load)
Pop-and-click suppression
Configurable with PDM pattern inputs
Short-circuit and thermal protection with autorecovery
Smart power-down when PDM stop condition
or no clock input detected
64 × f
or 128 × fS operation supporting 3 MHz and 6 MHz clocks
S
DC blocking high-pass filter and static input dc protection
User-selectable ultralow EMI emissions mode
Power-on reset (POR)
Minimal external passive components
APPLICATIONS
Mobile handsets
GENERAL DESCRIPTION
The SSM2517 is a PDM digital input Class-D power amplifier
that offers higher performance than existing DAC plus Class-D
solutions. The SSM2517 is ideal for power sensitive applications,
such as mobile phones and portable media players, where system
noise can corrupt the small analog signal sent to the amplifier.
The SSM2517 combines an audio digital-to-analog converter
(DAC), a power amplifier, and a PDM digital interface on a single
chip. The integrated DAC plus analog Σ-Δ modulator architecture
2.4 W Class-D Audio Amplifier
SSM2517
enables extremely low real-world power consumption from
digital audio sources with excellent audio performance. Using
the SSM2517, audio can be transmitted digitally to the audio
amplifier, significantly reducing the effect of noise sources such as
GSM interference or other digital signals on the transmitted audio.
The SSM2517 is capable of delivering 2.4 W of continuous output
power with <1% THD + N driving a 4 Ω load from a 5.0 V supply.
The SSM2517 features a high efficiency, low noise modulation
scheme that requires no external LC output filters. The closed-loop,
three-level modulator design retains the benefits of an all-digital
amplifier, yet enables very good PSRR and audio performance. The
modulation continues to provide high efficiency even at low output
power and has an SNR of 96 dB. Spread-spectrum pulse density
modulation is used to provide lower EMI-radiated emissions
compared with other Class-D architectures.
The SSM2517 has a four-state gain and sample frequency selection
pin that can select two different gain settings, optimized for 3.6 V
and 5 V operation. This same pin also controls the internal digital
filtering and clocking, which can be set for 64 × f
sample rates to support both 3 MHz and 6 MHz PDM clock rates.
The SSM2517 has a micropower shutdown mode with a typical
shutdown current of 1 μA for both power supplies. Shutdown is
enabled automatically by gating input clock and data signals. A
standby mode can be entered by applying a designated PDM stop
condition sequence. The device also includes pop-and-click suppression circuitry. This suppression circuitry minimizes voltage
glitches at the output when entering or leaving the low power
state, reducing audible noises on activation and deactivation.
The SSM2517 is specified over the industrial temperature range
of −40°C to +85°C. It has built-in thermal shutdown and output
short-circuit protection. It is available in a 9-ball, 1.5 mm × 1.5 mm
wafer level chip scale package (WLCSP).
or 128 × fS input
S
FUNCTIONAL BLOCK DIAGRAM
DD
POWER-ON
RESET
PDAT
PCLK
Rev. B
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responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarks and registered trademarks are the property of their respective owners.
INPUT
INTERFACE
CLOCKING P OWER
CONTROL
FILTERING/
DAC
Σ-∆
CLASS-D
MODULATO R
GAIN_FS LRSEL
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2010-2011 Analog Devices, Inc. All rights reserved.
PVDD PGND
SSM2517
FULL-BRI DGE
POWER STAGE
OUT+
OUT–
09211-001
SSM2517 Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Digital Input Specifications......................................................... 4
PDM Interface Digital Timing Specifications .......................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 13
Master Clock............................................................................... 13
Power Supplies............................................................................ 13
Power Control............................................................................. 13
Power-On Reset/Voltage Supervisor ....................................... 13
System Gain/Input Frequency.................................................. 13
PDM Pattern Control ................................................................ 14
EMI Noise.................................................................................... 14
Output Modulation Description .............................................. 14
Applications Information.............................................................. 15
Layout .......................................................................................... 15
Power Supply Decoupling......................................................... 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
9/11—Rev. A to Rev. B
Changes to Table 3, Endnote 1, and Figure 2................................ 5
5/11—Rev. 0 to Rev. A
Changes to Table 6, LRSEL Pin Description................................. 7
10/10—Revision 0: Initial Version
Rev. B | Page 2 of 16
Data Sheet SSM2517
SPECIFICATIONS
PVDD = 5.0 V, VDD = 1.8 V, fS = 128×, TA = 25°C, RL = 8 Ω + 33 μH, unless otherwise noted. When fS = 128×, PDM clock = 6.144 MHz;
when f
= 64×, PDM clock = 3.072 MHz.
S
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DEVICE CHARACTERISTICS
Output Power P
O
R
R
R
R
R
Total Harmonic Distortion Plus Noise THD + N f = 1 kHz, BW = 20 kHz
P
P
P
R
R
R
R
Efficiency η PO = 2.4 W into 4 Ω, PVDD = 5.0 V 86 %
P
Average Switching Frequency fSW No input 290 kHz
Closed-Loop Gain Gain
PVDD = 3.6 V 3.5 VP
PVDD = 5.0 V 4.78 VP
Differential Output Offset Voltage V
Low Power Mode Wake Time t
OOS
WAKE
Input Sampling Frequency fS f
f
POWER SUPPLY
Supply Voltage Range
Amplifier Power Supply PVDD 2.5 3.6 5.5 V
Digital Power Supply VDD 1.62 1.8 3.6 V
Power Supply Rejection Ratio PSRR
Supply Current, H-Bridge I
PVDD
PVDD = 5.0 V, fS = 64× 3.1 mA
PVDD = 5.0 V, fS = 128× 3.2 mA
PVDD = 3.6 V, fS = 64× 2.6 mA
PVDD = 3.6 V, fS = 128× 2.7 mA
PVDD = 2.5 V, fS = 64× 2.2 mA
PVDD = 2.5 V, fS = 128× 2.3 mA
Standby Current PVDD = 5.0 V 0.0 mA
Power-Down Current 100 nA
Supply Current, Modulator I
VDD
VDD = 3.3 V, fS = 64× 1.3 mA
VDD = 3.3 V, fS = 128× 2.4 mA
VDD = 1.8 V, fS = 64× 0.6 mA
VDD = 1.8 V, fS = 128× 1.2 mA
f = 1 kHz, BW = 20 kHz
RL = 4 Ω, THD = 1%, PVDD = 5.0 V 2.4 W
= 8 Ω, THD = 1%, PVDD = 5.0 V 1.38 W
L
= 4 Ω, THD = 1%, PVDD = 3.6 V 1.2 W
L
= 8 Ω, THD = 1%, PVDD = 3.6 V 0.7 W
L
= 4 Ω, THD = 10%, PVDD = 3.6 V 1.5 W
L
= 8 Ω, THD = 10%, PVDD = 3.6 V 0.9 W
L
= 100 mW into 8 Ω, PVDD = 3.6 V 0.035 %
O
= 500 mW into 8 Ω, PVDD = 3.6 V 0.1 %
O
= 1 W into 8 Ω, PVDD = 5.0 V 0.12 %
O
= 4 Ω, −6 dBFS input, PVDD = 5.0 V 3.6 %
L
= 8 Ω, −6 dBFS input, PVDD = 5.0 V 1.0 %
L
= 4 Ω, −6 dBFS input, PVDD = 3.6 V 5.2 %
L
= 8 Ω, −6 dBFS input, PVDD = 3.6 V 2.3 %
L
= 1.38 W into 8 Ω, PVDD = 5.0 V 92 %
O
−6 dBFS PDM input, BTL output,
f = 1 kHz
Gain = 6 dB 0.5 mV
0.5 ms
= 64× 1.84 3.072 3.23 MHz
S
= 128× 3.68 6.144 6.46 MHz
S
GSM VRIPPLE
= 100 mV at 217 Hz 85 dB
Dither input, 8 Ω + 33 μH load
Dither input, 8 Ω + 33 μH load
Rev. B | Page 3 of 16
SSM2517 Data Sheet
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Standby Current VDD = 1.8 V, fS = 64× 57 μA
VDD = 1.8 V, fS = 128× 114 μA
Shutdown Current VDD = 3.3 V 3.0 μA
VDD = 1.8 V 0.9 μA
NOISE PERFORMANCE
Output Voltage Noise en Dithered input, A-weighted
PVDD = 3.6 V, fS = 64× 43 μV
PVDD = 3.6 V, fS = 128× 52 μV
PVDD = 5.0 V, fS = 64× 52 μV
PVDD = 5.0 V, fS = 128× 60 μV
Signal-to-Noise Ratio SNR
f
f
= 1.38 W, PVDD = 5.0 V, RL = 8 Ω,
P
O
A-weighted
= 64× 96 dB
S
= 128× 95 dB
S
DIGITAL INPUT SPECIFICATIONS
Table 2.
Parameter Symbol Min Typ Max Unit
INPUT SPECIFICATIONS
Input Voltage High VIH
PCLK, PDAT, LRSEL Pins 0.7 × VDD 3.6 V
GAIN_FS Pin 1.35 5.5 V
Input Voltage Low VIL V
PCLK, PDAT, LRSEL Pins −0.3 0.3 × VDD V
GAIN_FS Pin −0.3 +0.35 V
Input Leakage High IIH
PDAT, LRSEL, GAIN_FS Pins 1 μA
PCLK Pin 3 μA
Input Leakage Low IIL
PDAT, LRSEL, GAIN_FS Pins 1 μA
PCLK Pin 3 μA
Input Capacitance 5 pF
Rev. B | Page 4 of 16
Data Sheet SSM2517
PDM INTERFACE DIGITAL TIMING SPECIFICATIONS
Table 3.
Limit
Parameter
t
t
MIN
MAX
tDS 44 ns Valid data start time1
tDE 7 ns Valid data end time1
1
The SSM2517 was designed so that the data line can transition coincident with or close to a clock edge. It is not necessary to delay the data line transition until after the
clock edge because the SSM2517 does this internally to ensure good timing margins. The data line should remain constant during the valid sample period illustrated
in Figure 2; it may transition at any other time. Timing is measured from 70% of VDD on the rising edge or 30% VDD on the falling edge.
Timing Diagram
PCLK
t
DS
PDAT
Unit Description
t
DE
VALID LEFT SAMPLE VALID LEFT SAMPLEVALID RIGHT SAMPLE
09211-002
Figure 2. PDM Interface Timing
Rev. B | Page 5 of 16
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