Analog Devices SMP18FP, SMP18FRU, SMP18FS Datasheet

Octal Sample-and-Hold

a

FEATURES
High Speed Version of SMP08
Internal Hold Capacitors
Low Droop Rate
TTL/CMOS Compatible Logic Inputs
Single or Dual Supply Operation
Break-Before-Make Channel Addressing
Compatible With CD4051 Pinout
Low Cost

APPLICATIONS
Multiple Path Timing Deskew for A.T.E.
Memory Programmers
Mass Flow/Process Control Systems
Multichannel Data Acquisition Systems
Robotics and Control Systems
Medical and Analytical Instrumentation
Event Analysis
Stage Lighting Control

GENERAL DESCRIPTION

The SMP18 is a monolithic octal sample-and-hold; it has eight
internal buffer amplifiers, input multiplexer, and internal hold
capacitors. It is manufactured in an advanced oxide isolated
CMOS technology to obtain high accuracy, low droop rate, and
fast acquisition time. The SMP18 has a typical linearity error of
only 0.01% and can accurately acquire a 10-bit input signal to
±1/2 LSB in less than 2.5 microseconds. The SMP18’s output
swing includes the negative supply in both single and dual sup­ply operation.

The SMP18 was specifically designed for systems that use a
calibration cycle to adjust a multiple of system parameters. The
low cost and high level of integration make the SMP18 ideal for
calibration requirements that have previously required an ASIC,
or high cost multiple D/A converters.

The SMP18 is also ideally suited for a wide variety of sample­and-hold applications including amplifier offset or VCA gain ad­justments. One or more SMP18s can be used with single or
multiple DACs to provide multiple set points within a system.

with Multiplexed Input

SMP18

FUNCTIONAL BLOCK DIAGRAM

(LSB)

A

INPUT

3

SW

SW

HOLD CAPS

(INTERNAL)

SMP18

The SMP18 offers significant cost and size reduction over
discrete designs. It is available in a 16-pin plastic DIP, a
narrow body SO-16 surface-mount SOIC package or the thin
TSSOP-16 package. The SMP18 is a higher speed direct
replacement for the SMP08.

(MSB)

C

B

1 OF 8 DECODER

SW

SW

SW

SW

INH

SW

691011

8

DGND

16

V

DD

SW

13

14

15

12

1

5

2

4

7

CH0OUT

CH1OUT

CH2OUT

OUT

CH

3

OUT

CH

4

CH5OUT

CH6OUT

OUT

CH

7

V

SS

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1996

SMP18–SPECIFICATIONS

(@ VDD = +5 V, VSS = –5 V, DGND = 0 V, RL = No Load, TA = –408C to +858C for SMP18F,

ELECTRICAL CHARACTERISTICS

P

arameter Symbol Conditions Min Typ Max Units

unless otherwise noted)

Linearity Error –3 V ≤ V
Buffer Offset Voltage V

OS

TA = +25°C, VIN = 0 V 2.5 10 mV
–40°C ≤ T

Hold Step V
Droop Rate ∆V

Output Source Current I
Output Sink Current I

HS

CH
SOURCE
SINK

VIN = 0 V, TA = +25°C to +85°C 46mV
V

IN

/∆tTA = +25°C, VIN = 0 V 2 40 mV/s

VIN = 0 V
VIN = 0 V

≤ +3 V 0.01 %

IN

≤ +85°C, VIN = 0 V 3.5 20 mV

A

= 0 V, TA = –40°C8mV

1
1

1.2 mA

0.5 mA

Output Voltage Range RL = 20 kΩ –3.0 +3.0 V
LOGIC CHARACTERISTICS

Logic Input High Voltage V
Logic Input Low Voltage V
Logic Input Current I

DYNAMIC PERFORMANCE

Acquisition Time

3

2

Hold Mode Settling Time t
Channel Select Time t
Channel Deselect Time t
Inhibit Recovery Time t

t

INH
INL

IN

AQ
H
CH
DCS
IR

VIN = 2.4 V 0.5 1 µA

TA = +25°C, –3 V to +3 V to 0.1% 3.5 µs
To ±1 mV of Final Value 1 µs

2.4 V

0.8 V

90 ns
45 ns
90 ns

Slew Rate SR 6 V/µs
Capacitive Load Stability <30% Overshoot 500 pF
Analog Crosstalk –3 V to +3 V Step –72 dB

SUPPLY CHARACTERISTICS

Power Supply Rejection Ratio PSRR V
Supply Current I

DD

= ±5 V to ±6 V 60 75 dB

SS

TA = +25°C 5.5 7.5 mA
–40°C ≤ TA ≤ +85°C

7.5 9.5 mA

(@ VDD = +12 V, VSS = 0 V, DGND = 0 V, RL = No Load, TA = –408C to +858C for SMP18F,

ELECTRICAL CHARACTERISTICS

unless otherwise noted)

Parameter Symbol Conditions Min Typ Max Limits

Linearity Error 60 mV ≤ V
Buffer Offset Voltage V

OS

TA = +25°C, VIN = 6 V 2.5 10 mV
–40°C ≤ T

Hold Step V
Droop Rate ∆V

Output Source Current I
Output Sink Current I

HS

CH
SOURCE
SINK

Output Voltage Range R

VIN = 6 V, TA = +25°C to +85°C 46mV
V

= 6 V, TA = –40°C8mV

IN

/∆tTA = +25°C, VIN = 6 V 2 40 mV/s

VIN = 6 V
VIN = 6 V

= 20 kΩ 0.06 10.0 V

L

≤ 10 V 0.01 %

IN

≤ +85°C, VIN = 6 V 3.5 20 mV

A

1
1

1.2 mA

0.5 mA

RL = 10 kΩ 0.06 9.5 V

LOGIC CHARACTERISTICS

Logic Input High Voltage V
Logic Input Low Voltage V
Logic Input Current I

DYNAMIC PERFORMANCE

Acquisition Time

3

2

Hold Mode Settling Time t
Channel Select Time t
Channel Deselect Time t
Inhibit Recovery Time t
Slew Rate

4

INH

t

INL

IN

AQ
H
CH
DCS
IR

VIN = 2.4 V 0.5 1 µA

TA = +25°C, 0 to 10 V to 0.1% 2.5 3.25 µs
To ±1 mV of Final Value 1 µs

SR 7 V/µs

2.4 V

0.8 V

90 ns
45 ns
90 ns

Capacitive Load Stability <30% Overshoot 500 pF
Analog Crosstalk 0 V to 10 V Step –72 dB

SUPPLY CHARACTERISTICS

Power Supply Rejection Ratio PSRR 10.8 V ≤ V
Supply Current I

DD

TA = +25°C 6.0 8.0 mA

≤ 13.2 V 60 75 dB

DD

–40°C ≤ TA ≤ +85°C 8.0 10.0 mA

NOTES

1

Outputs are capable of sinking and sourcing over 10 mA but offset is guaranteed at specified load levels.

2

All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.

3

This parameter is guaranteed without test.

4

Slew rate is measured in the sample mode with a 0 to 10 V step from 20% to 80%.

Specifications subject to change without notice.

–2–

REV. C

SMP18

14
13
12
11

16
15

10

9

8

1
2
3
4

7

6

5

TOP VIEW

(Not to Scale)

SMP18

CH4OUT

CH

0

OUT

CH

1

OUT

CH

2

OUT

V

DD

CH6OUT

INPUT

CH

7

OUT

B CONTROL

A CONTROL

CH

3

OUT

CH

5

OUT

INH
V

SS

DGND

C CONTROL

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

PIN CONNECTIONS

VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V

V

to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V

DD

V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V

LOGIC

VIN to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V

V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V

OUT

DD
DD
DD

Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

(Not short-circuit protected)

Operating Temperature Range

FP, FS . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C

Package Type uJA* u

JC

16-Pin Plastic DIP (P) 76 33 °C/W
16-Pin SOIC (S) 92 27 °C/W
16-Lead TSSOP (RU) 180 35 °C/W

NOTES
*θJA is specified for worst case mounting conditions, i.e., θJA is specified for device

in socket for plastic DIP packages; θJA is specified for device soldered to printed
circuit board for SOIC and TSSOP packages.

Units

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

SMP18FP –40°C to +85°C Plastic DIP N-16
SMP18FRU –40°C to +85°C TSSOP-16 RU-16
SMP18FS –40°C to +85°C SO-16 R-16A

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SMP18 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. C

–3–