Analog Devices errata832 B1 Datasheet

MicroConverter®, Multi-Channel 12-bit

a

Errata Sheet

A. This Errata sheet contains the following known bugs, anomalies and work-arounds for the ADuC832 MicroConverter

832_S01. NUMBER OF ADC CLOCKS IN PIPLINED MODE

832_S02. DAC CLEAR BIT FUNCTIONALITY

832_S03. EXTENDED (11-BIT) STACK POINTER - PUSH AND POP OPERATION

B. The Errata listed, apply to all ADuC832 packaged material branded as follows:

First Line: ADuC832XX
Fourth Line: BXX

C. Analog Devices Inc. is committed, through future silicon revisions to continuously improve silicon functionality.

Analog Devices Inc. will use its best endeavors to ensure that these future silicon revisions remain compatible with
your present software/systems that implement the recommended work-arounds outlined in this document.

ADCs and DACs with Embedded FLASH MCU

ADuC832

REV. B.1 November/2002

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

® MicroConverter is a Trademark of Analog Devices, Inc.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] Analog Devices, Inc., 2002

ADuC832

832_S01. NUMBER OF ADC CLOCKS IN PIPLINED MODE

Backgound: An adc conversion takes 16 ADC clocks plus the selected acquisition

clocks.

Issue: At voltages below 3.5V in piplined mode the number of ADC clocks

required for a conversion can vary between 15 and 16 ADC clocks.

Work-Around : none.

Related Issues : This issue does not affect the performance of the ADC.

832_S02. DAC CLEAR BIT FUNCTIONALITY

Backgound: The DAC outputs are controlled by the SFR DACCON. The CLR1 and

CLR0 bits in DACCON can be used to force the output of DAC1 and
DAC0 to 0V.

Issue: When the DAC is enabled and in buffered mode setting the CLR1 or

CLR0 bits may cause a momentary spike on the DAC ouput before the
DAC is forced to 0V.

Errata Sheet

Work-Around : To force the output of DAC1 or DAC0 to 0V write 0000H to the

corresponding DAC data registers.

Related Issues : none.

2 of 3 REV. B.1 November/2002